From 28ab495a49c385a03dc6a7d1f48b3bb8eac9a623 Mon Sep 17 00:00:00 2001 From: rcitach Date: Fri, 31 Jul 2026 08:07:02 +0000 Subject: [PATCH] =?UTF-8?q?RA6W1=E5=9F=BA=E7=A1=80BSP=E5=86=85=E5=AE=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/ALL_BSP_COMPILE.json | 1 + bsp/renesas/.clang-format-ignore | 6 + .../HAL_Drivers/drivers/config/drv_config.h | 6 + .../drivers/config/raw/ra6w1/uart_config.h | 59 + .../HAL_Drivers/drivers/drv_usart_v2.c | 48 +- bsp/renesas/libraries/Kconfig | 10 + bsp/renesas/ra6w1-ek/.config | 1460 + bsp/renesas/ra6w1-ek/Kconfig | 24 + bsp/renesas/ra6w1-ek/README.md | 127 + bsp/renesas/ra6w1-ek/SConscript | 19 + bsp/renesas/ra6w1-ek/SConstruct | 49 + bsp/renesas/ra6w1-ek/board/Kconfig | 44 + bsp/renesas/ra6w1-ek/board/SConscript | 16 + bsp/renesas/ra6w1-ek/board/board.h | 57 + bsp/renesas/ra6w1-ek/board/bsp_linker_info.h | 135 + bsp/renesas/ra6w1-ek/board/ports/SConscript | 19 + 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bsp/renesas/ra6w1-ek/ra/fsp/src/r_spi_w/r_spi_w.c create mode 100644 bsp/renesas/ra6w1-ek/ra/fsp/src/r_tim_w/r_tim_w.c create mode 100644 bsp/renesas/ra6w1-ek/ra/fsp/src/r_uart_w/r_uart_w.c create mode 100644 bsp/renesas/ra6w1-ek/ra/fsp/src/r_wdog_w/r_wdog_w.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/SConscript create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_adc_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ext_irq_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_gpio_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_i2c_master_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ospi_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_qspi_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_rtc_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_spi_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_tim_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_uart_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_wdog_w_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/SConscript create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/common_data.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/common_data.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/hal_data.h create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/main.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/vector_data.c create mode 100644 bsp/renesas/ra6w1-ek/rafw_gen/vector_data.h create mode 100644 bsp/renesas/ra6w1-ek/rtconfig.h create mode 100644 bsp/renesas/ra6w1-ek/rtconfig.py create mode 100644 bsp/renesas/ra6w1-ek/script/fsp.ld create mode 100644 bsp/renesas/ra6w1-ek/script/memory_regions.ld create mode 100644 bsp/renesas/ra6w1-ek/scripts/gen_rrq61_flash_image.py create mode 100644 bsp/renesas/ra6w1-ek/scripts/rrq61_fw_version.py create mode 100644 bsp/renesas/ra6w1-ek/src/hal_entry.c diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 668a0f0ea506..9ad92b89eefa 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -271,6 +271,7 @@ "renesas/ra6m3-hmi-board", "renesas/ra6e2-ek", "renesas/ra6e2-fpb", + "renesas/ra6w1-ek", "renesas/ra4e2-eco", "renesas/ra4m1-ek", "renesas/ra4m2-eco", diff --git a/bsp/renesas/.clang-format-ignore b/bsp/renesas/.clang-format-ignore index b36f1ccad5c0..91c6400fec3c 100644 --- a/bsp/renesas/.clang-format-ignore +++ b/bsp/renesas/.clang-format-ignore @@ -9,9 +9,15 @@ /**/ra/ /**/ra_cfg/ /**/ra_gen/ +/**/rafw_cfg/ +/**/rafw_gen/ /libraries/bsp-template/ /**/RTE/ # RA8P1 Titan generated and migrated sources /ra8p1-titan-board/*/board/bsp_linker_info.h /ra8p1-titan-board/m85/board/ports/ + +# RA6W1 generated and migrated sources +/ra6w1-ek/board/bsp_linker_info.h +/ra6w1-ek/board/ports/ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h index 9d758f371eb6..e7bf194c8c18 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h @@ -287,6 +287,12 @@ extern "C" #endif #endif /* SOC_SERIES_R7FA2A1 */ +#if defined(SOC_FAMILY_RENESAS_RA_WIRELESS) +#if defined(SOC_SERIES_R7SA6W1) +#include "raw/ra6w1/uart_config.h" +#endif /* SOC_SERIES_R7SA6W1 */ +#endif /* SOC_FAMILY_RENESAS_RA_WIRELESS */ + #ifdef __cplusplus } #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/raw/ra6w1/uart_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/raw/ra6w1/uart_config.h new file mode 100644 index 000000000000..82e8ecaf23aa --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/raw/ra6w1/uart_config.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-07-29 rcitach first version + */ + +#ifndef __RAW61_UART_CONFIG_H__ +#define __RAW61_UART_CONFIG_H__ + +#include +#include "hal_data.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .name = "uart0", \ + .p_api_ctrl = &g_uart1_ctrl, \ + .p_cfg = &g_uart1_cfg, \ + } +#endif /* UART0_CONFIG */ +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .p_api_ctrl = &g_uart2_ctrl, \ + .p_cfg = &g_uart2_cfg, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .p_api_ctrl = &g_uart3_ctrl, \ + .p_cfg = &g_uart3_cfg, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RAW61_UART_CONFIG_H__ */ + diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c index 7509f3f3b116..d18bbacc871c 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c @@ -15,16 +15,15 @@ #ifdef RT_USING_SERIAL_V2 //#define DRV_DEBUG -#define DBG_TAG "drv.usart" +#define DBG_TAG "drv.usart" #ifdef DRV_DEBUG - #define DBG_LVL DBG_LOG +#define DBG_LVL DBG_LOG #else - #define DBG_LVL DBG_INFO +#define DBG_LVL DBG_INFO #endif /* DRV_DEBUG */ #include -static struct ra_uart_config uart_config[] = -{ +static struct ra_uart_config uart_config[] = { #ifdef BSP_USING_UART0 UART0_CONFIG, #endif @@ -109,7 +108,7 @@ enum #endif }; -static struct ra_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static struct ra_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = { 0 }; static void ra_uart_get_config(void) { @@ -213,6 +212,16 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial #if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg); +#elif defined(SOC_SERIES_R7SA6W1) + uart_w_extended_cfg_t *p_extend = (uart_w_extended_cfg_t *)uart->config->p_cfg->p_extend; + RT_ASSERT(p_extend != RT_NULL); + RT_ASSERT(p_extend->p_baud_setting != RT_NULL); + + err = R_UART_W_BaudCalculate(cfg->baud_rate, p_extend->p_baud_setting); + if (FSP_SUCCESS == err) + { + err = R_UART_W_Open(uart->config->p_api_ctrl, uart->config->p_cfg); + } #else err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg); #endif @@ -237,18 +246,28 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c) uart = rt_container_of(serial, struct ra_uart, serial); RT_ASSERT(uart != RT_NULL); -#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) +#if defined(SOC_SERIES_R7SA6W1) + uart_w_instance_ctrl_t *p_ctrl = (uart_w_instance_ctrl_t *)uart->config->p_api_ctrl; + + p_ctrl->p_reg->UART_DR_REG = c; + + while (p_ctrl->p_reg->UART_FR_REG_b.BUSY); +#elif defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) sci_b_uart_instance_ctrl_t *p_ctrl = (sci_b_uart_instance_ctrl_t *)uart->config->p_api_ctrl; + + p_ctrl->p_reg->TDR = c; + + while ((p_ctrl->p_reg->CSR_b.TEND) == 0); #else sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl; -#endif p_ctrl->p_reg->TDR = c; -#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0) || defined(SOC_SERIES_R7KA8P1) +#if defined(SOC_SERIES_R9A07G0) while ((p_ctrl->p_reg->CSR_b.TEND) == 0); #else while ((p_ctrl->p_reg->SSR_b.TEND) == 0); +#endif #endif return RT_EOK; @@ -259,10 +278,10 @@ static int ra_uart_getc(struct rt_serial_device *serial) return RT_EOK; } -static rt_ssize_t ra_uart_transmit(struct rt_serial_device *serial, - rt_uint8_t *buf, - rt_size_t size, - rt_uint32_t tx_flag) +static rt_ssize_t ra_uart_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) { struct ra_uart *uart; @@ -467,8 +486,7 @@ void user_uart9_callback(uart_callback_args_t *p_args) } #endif -static const struct rt_uart_ops ra_uart_ops = -{ +static const struct rt_uart_ops ra_uart_ops = { .configure = ra_uart_configure, .control = ra_uart_control, .putc = ra_uart_putc, diff --git a/bsp/renesas/libraries/Kconfig b/bsp/renesas/libraries/Kconfig index f590f7e8c73f..1d0aff98aa8d 100644 --- a/bsp/renesas/libraries/Kconfig +++ b/bsp/renesas/libraries/Kconfig @@ -3,6 +3,10 @@ config SOC_FAMILY_RENESAS_RA bool default n +config SOC_FAMILY_RENESAS_RA_WIRELESS + bool + default n + config SOC_FAMILY_RENESAS_RZ bool default n @@ -91,6 +95,12 @@ config SOC_SERIES_R7FA6E2 select SOC_FAMILY_RENESAS_RA default n +config SOC_SERIES_R7SA6W1 + bool + select ARCH_ARM_CORTEX_M33 + select SOC_FAMILY_RENESAS_RA_WIRELESS + default n + config SOC_SERIES_R7FA2A1 bool select ARCH_ARM_CORTEX_M23 diff --git a/bsp/renesas/ra6w1-ek/.config b/bsp/renesas/ra6w1-ek/.config new file mode 100644 index 000000000000..51abcedfedba --- /dev/null +++ b/bsp/renesas/ra6w1-ek/.config @@ -0,0 +1,1460 @@ +CONFIG_SOC_R7SA6W1CED=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_RENESAS_RA_WIRELESS=y +CONFIG_SOC_SERIES_R7SA6W1=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO_W=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=256 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/renesas/ra6w1-ek/Kconfig b/bsp/renesas/ra6w1-ek/Kconfig new file mode 100644 index 000000000000..8571e9e23404 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/Kconfig @@ -0,0 +1,24 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +PKGS_DIR := packages + +ENV_DIR := / + +config SOC_R7SA6W1CED + bool + select SOC_SERIES_R7SA6W1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +source "$(BSP_DIR)/board/Kconfig" diff --git a/bsp/renesas/ra6w1-ek/README.md b/bsp/renesas/ra6w1-ek/README.md new file mode 100644 index 000000000000..7390b7e73584 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/README.md @@ -0,0 +1,127 @@ +# 瑞萨 EK-RA6W1 开发板 BSP 说明 + +## 简介 + +本文档为瑞萨 EK-RA6W1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +主要内容如下： + +- 开发板介绍 +- BSP 快速上手指南 + +## 开发板介绍 + +基于瑞萨 RA6W1 MCU 开发的 EK-RA6W1 MCU 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA6W1 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。 + +开发板正面外观如下图： + +![](docs/picture/ek-ra6w1.png) + + +该开发板常用 **板载资源** 如下： + +- MCU：R7SA6W1CED，160MHz，Arm Cortex®-M33内核，704KB SRAM +- 网络：Wi-Fi 6，802.11a/b/g/n/ac/ax 2.4/5GHz，1x1，20MHz，MCS9 115Mbps，OFDMA，TWT +- 板载资源：8MB QSPI Flash，8MB pSRAM，2x SPI，3x UART，2x I2C，12 位 ADC、I2S、PDM、PWM + +**更多详细资料及工具** + +## 外设支持 + +* 本 BSP 目前对外设的支持情况如下： + + | **片上外设** | **支持情况** | **备注** | + | :----------: | :----------: | :----------------------- | + | UART | 支持 | UART1 为默认日志输出端口 | + | GPIO | 支持 | | + +* 注意：仓库刚拉下来是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程) + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +## ENV 编译、调试烧录 + +- 编译：打开ENV进入到 *rt-thread/bsp/renesas/ra6w1-ek* 目录，执行 scons 进行编译 + +* 下载：使用Renesas Flash Programmer 进行程序烧录，Microcontroller 选择 RA6W1, 烧录rtthread.img.bin文件，偏移为0 + +![](docs/picture/download.png) + +### 快速上手 + +本 BSP 目前仅提供 ENV 工程。下面以 ENV 开发环境为例，介绍如何将系统运行起来。 + +**硬件连接** + +使用 USB 数据线连接开发板到 PC + +**编译下载** + +- 编译：打开ENV进入到 *rt-thread/bsp/renesas/ra6w1-ek* 目录，执行 scons 进行编译 + +* 下载：使用Renesas Flash Programmer 进行程序烧录，Microcontroller 选择 RA6W1, 烧录rtthread.img.bin文件，偏移为0 + +**查看运行结果** + +下载程序成功之后，系统会自动运行并打印系统信息。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.3.0 build Jul 31 2026 08:52:35 + 2006 - 2024 Copyright by RT-Thread team +[I/utest] utest is initialize success. +[I/utest] total utest testcase num: (24) + +Hello RT-Thread on RA6W1! +msh >help +RT-Thread shell commands: +reboot - Reboot System +utest_list - output all utest testcase +utest_run - utest_run [-thread or -help] [testcase name] [loop num] +pin - pin [option] +clear - clear the terminal screen +version - show RT-Thread version information +console - console setting +list - list objects +help - RT-Thread shell help +ps - List threads in the system +free - Show the memory usage in the system +backtrace - print backtrace of a thread + +msh > + +``` + +### 进阶使用 + +**资料及文档** + +- [瑞萨RA6W1 MCU 基础知识](https://www.renesas.cn/zh/products/ra6w1) +- [RA6W1 MCU 使用指南](https://www.renesas.cn/zh/document/mah/ra6w1-hardware-design-guide) + +**FSP 配置** + +需要根据指南安装好e2studio工具，并完成指南中软件包的安装, +[软件包安装链接](https://www.renesas.com/en/document/sws/rafw-flexible-software-package?r=25578118&_gl=1*3jbk41*_gcl_au*NzAxNzk2MDQyLjE3ODM0MTk0NTE.*_ga*MTIzMjEwMzY0MS4xNzgzNDE5NDUx*_ga_D1706WVDQV*czE3ODU0OTI2NDIkbzgkZzAkdDE3ODU0OTI2NDIkajYwJGwwJGgw) +，获取 [rafw-example](https://github.com/renesas/rafw-fsp-examples.git) 并导入基础 gpio_ek_ra6w1_ep 示例，根据需求选择对应功能，并将对应生成的ra系列代码复制到对应目录 + +## 联系人信息 + +在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/) + +## 贡献代码 + +如果您对 EK-RA6W1 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。 diff --git a/bsp/renesas/ra6w1-ek/SConscript b/bsp/renesas/ra6w1-ek/SConscript new file mode 100644 index 000000000000..d553e19c6768 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] +list = os.listdir(cwd) + +src = Glob('./src/*.c') +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/bsp/renesas/ra6w1-ek/SConstruct b/bsp/renesas/ra6w1-ek/SConstruct new file mode 100644 index 000000000000..8a9fb62c7201 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/SConstruct @@ -0,0 +1,49 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +rtconfig.BSP_LIBRARY_TYPE = None + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/renesas/ra6w1-ek/board/Kconfig b/bsp/renesas/ra6w1-ek/board/Kconfig new file mode 100644 index 000000000000..6e7cb35098be --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/Kconfig @@ -0,0 +1,44 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO_W + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + endif + endmenu +endmenu diff --git a/bsp/renesas/ra6w1-ek/board/SConscript b/bsp/renesas/ra6w1-ek/board/SConscript new file mode 100644 index 000000000000..a27ea8e470cc --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd] +src = Glob('*.c') + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/ra6w1-ek/board/board.h b/bsp/renesas/ra6w1-ek/board/board.h new file mode 100644 index 000000000000..0c367c3db101 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/board.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-10 Sherman first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RA_SRAM_SIZE 660 +#define RA_SRAM_END (0x20000000 + 0x000a5000) + +#ifdef __ARMCC_VERSION +extern int Image$$RAM_END$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base) +#elif __ICCARM__ +#pragma section = "CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __RAM_segment_used_end__; +#define HEAP_BEGIN (&__RAM_segment_used_end__) +#endif + +#define HEAP_END RA_SRAM_END + +#ifdef BSP_USING_GPIO_W +#define R_IOPORT_Open R_GPIO_W_Open +#define R_IOPORT_Close R_GPIO_W_Close +#define R_IOPORT_PinsCfg R_GPIO_W_PinsCfg +#define R_IOPORT_PinCfg R_GPIO_W_PinCfg +#define R_IOPORT_PinRead R_GPIO_W_PinRead +#define R_IOPORT_PinWrite R_GPIO_W_PinWrite +#define R_IOPORT_PortDirectionSet R_GPIO_W_PortDirectionSet +#define R_IOPORT_PortEventInputRead R_GPIO_W_PortEventInputRead +#define R_IOPORT_PortEventOutputWrite R_GPIO_W_PortEventOutputWrite +#define R_IOPORT_PortRead R_GPIO_W_PortRead +#define R_IOPORT_PortWrite R_GPIO_W_PortWrite + +#define g_ioport g_gpio_w +#define g_ioport_ctrl g_gpio_w_ctrl +int rt_hw_pin_init(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/renesas/ra6w1-ek/board/bsp_linker_info.h b/bsp/renesas/ra6w1-ek/board/bsp_linker_info.h new file mode 100644 index 000000000000..c4ab32218f10 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/bsp_linker_info.h @@ -0,0 +1,135 @@ +/* UNCRUSTIFY-OFF */ +#ifndef BSP_LINKER_H +#define BSP_LINKER_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******* Solution Definitions *************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +/* linker generated initialization table data structures types */ +typedef enum e_bsp_init_mem { + INIT_MEM_ZERO, + INIT_MEM_FLASH, + INIT_MEM_DATA_FLASH, + INIT_MEM_RAM, + INIT_MEM_DTCM, + INIT_MEM_ITCM, + INIT_MEM_CTCM, + INIT_MEM_STCM, + INIT_MEM_OSPI0_CS0, + INIT_MEM_OSPI0_CS1, + INIT_MEM_OSPI1_CS0, + INIT_MEM_OSPI1_CS1, + INIT_MEM_QSPI_FLASH, + INIT_MEM_SDRAM, + INIT_MEM_RAMCODE, + INIT_MEM_IPDRAM, + INIT_MEM_FRAGRAM, + INIT_MEM_SHARED_TCM_RAM, + INIT_MEM_MACHW_MIB, +} bsp_init_mem_t; + +typedef struct st_bsp_init_type { + uint32_t copy_64 :8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */ + uint32_t external :8; /* =1 if either source or destination is external, else 0 */ + uint32_t source_type :8; + uint32_t destination_type :8; +} bsp_init_type_t; + +typedef struct st_bsp_init_zero_info { + uint32_t *const p_base; + uint32_t *const p_limit; + bsp_init_type_t type; +} bsp_init_zero_info_t; + +typedef struct st_bsp_init_copy_info { + uint32_t *const p_base; + uint32_t *const p_limit; + uint32_t *const p_load; + bsp_init_type_t type; +} bsp_init_copy_info_t; + +typedef struct st_bsp_init_info { + uint32_t zero_count; + bsp_init_zero_info_t const *const p_zero_list; + uint32_t copy_count; + bsp_init_copy_info_t const *const p_copy_list; +} bsp_init_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern bsp_init_info_t const g_init_info; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#endif /* BSP_LINKER_H */ +#ifdef BSP_LINKER_C +/*********************************************************************************************************************** + * Objects allocated by bsp_linker.c + **********************************************************************************************************************/ +/* DDSC symbol definitions */ +/* Zero initialization tables */ +extern uint32_t __ipdram_zero$$Base; +extern uint32_t __ipdram_zero$$Limit; +extern uint32_t __fragram_zero$$Base; +extern uint32_t __fragram_zero$$Limit; +extern uint32_t __machw_mib_zero$$Base; +extern uint32_t __machw_mib_zero$$Limit; +extern uint32_t __ram_zero$$Base; +extern uint32_t __ram_zero$$Limit; +static const bsp_init_zero_info_t zero_list[] = +{ + {.p_base = &__ipdram_zero$$Base, .p_limit = &__ipdram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_IPDRAM}}, + {.p_base = &__fragram_zero$$Base, .p_limit = &__fragram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_FRAGRAM}}, + {.p_base = &__machw_mib_zero$$Base, .p_limit = &__machw_mib_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_MACHW_MIB}}, + {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}} +}; +/* Load initialization tables */ +extern uint32_t __ipdram_from_flash$$Base; +extern uint32_t __ipdram_from_flash$$Limit; +extern uint32_t __ipdram_from_flash$$Load; +extern uint32_t __fragram_from_flash$$Base; +extern uint32_t __fragram_from_flash$$Limit; +extern uint32_t __fragram_from_flash$$Load; +extern uint32_t __machw_mib_from_flash$$Base; +extern uint32_t __machw_mib_from_flash$$Limit; +extern uint32_t __machw_mib_from_flash$$Load; +extern uint32_t __ram_from_flash$$Base; +extern uint32_t __ram_from_flash$$Limit; +extern uint32_t __ram_from_flash$$Load; +extern uint32_t __ramcode_from_flash$$Base; +extern uint32_t __ramcode_from_flash$$Limit; +extern uint32_t __ramcode_from_flash$$Load; +static const bsp_init_copy_info_t copy_list[] = +{ + {.p_base = &__ipdram_from_flash$$Base, .p_limit = &__ipdram_from_flash$$Limit, .p_load = &__ipdram_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_IPDRAM}}, + {.p_base = &__fragram_from_flash$$Base, .p_limit = &__fragram_from_flash$$Limit, .p_load = &__fragram_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_FRAGRAM}}, + {.p_base = &__machw_mib_from_flash$$Base, .p_limit = &__machw_mib_from_flash$$Limit, .p_load = &__machw_mib_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_MACHW_MIB}}, + {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ramcode_from_flash$$Base, .p_limit = &__ramcode_from_flash$$Limit, .p_load = &__ramcode_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAMCODE}} +}; + +/* initialization data structure */ +const bsp_init_info_t g_init_info = +{ + .zero_count = sizeof(zero_list) / sizeof(zero_list[0]), + .p_zero_list = zero_list, + .copy_count = sizeof(copy_list) / sizeof(copy_list[0]), + .p_copy_list = copy_list +}; + +#endif /* BSP_LINKER_C */ +/* TODO: Revert once solution project is ready. */ +#if !defined(BOARD_RA6B1_PRODK) && !defined(BOARD_RA6U1_EK) +#endif + +/* UNCRUSTIFY-ON */ + diff --git a/bsp/renesas/ra6w1-ek/board/ports/SConscript b/bsp/renesas/ra6w1-ek/board/ports/SConscript new file mode 100644 index 000000000000..6bc17b8362e2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/ports/SConscript @@ -0,0 +1,19 @@ +import os +from building import * + +src = [] +objs = [] +cwd = GetCurrentDir() +CPPPATH = [cwd] + +if GetDepend(["BSP_USING_GPIO_W"]): + src += ["drv_gpio_w.c"] + +objs = DefineGroup('Port', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/ra6w1-ek/board/ports/drv_gpio_w.c b/bsp/renesas/ra6w1-ek/board/ports/drv_gpio_w.c new file mode 100644 index 000000000000..0eaeee5b76f6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/ports/drv_gpio_w.c @@ -0,0 +1,446 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-29 KyleChan first version + * 2026-07-15 rain RA Wireless GPIO adapter + */ + +#include +#include +#include +#include +#include "r_ext_irq_w.h" +#include "common_data.h" +#include "board.h" + +#ifdef BSP_USING_GPIO_W + +#define DBG_TAG "drv.gpio.wireless" +#ifdef DRV_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#define RA_WIRELESS_EXT_IRQ_MAX_CHANNEL 30 + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_WIRELESS_EXT_IRQ_MAX_CHANNEL] = {0}; +static ext_irq_w_instance_ctrl_t ra_ext_irq_ctrl_tab[RA_WIRELESS_EXT_IRQ_MAX_CHANNEL]; +static ext_irq_w_extended_cfg_t ra_ext_irq_extend_tab[RA_WIRELESS_EXT_IRQ_MAX_CHANNEL]; +static external_irq_cfg_t ra_ext_irq_cfg_tab[RA_WIRELESS_EXT_IRQ_MAX_CHANNEL]; +static rt_int32_t ra_ext_irq_pin_to_channel[RA_WIRELESS_EXT_IRQ_MAX_CHANNEL]; + +static void ra_irq_tab_init(void) +{ + for (int i = 0; i < RA_WIRELESS_EXT_IRQ_MAX_CHANNEL; ++i) + { + pin_irq_hdr_tab[i].pin = -1; + pin_irq_hdr_tab[i].mode = 0; + pin_irq_hdr_tab[i].args = RT_NULL; + pin_irq_hdr_tab[i].hdr = RT_NULL; + ra_ext_irq_pin_to_channel[i] = -1; + } +} + +static rt_int32_t ra_pin_find_irq_channel(rt_uint32_t pin) +{ + for (int i = 0; i < RA_WIRELESS_EXT_IRQ_MAX_CHANNEL; ++i) + { + if (ra_ext_irq_pin_to_channel[i] == (rt_int32_t) pin) + { + return i; + } + } + + return -1; +} + +static rt_int32_t ra_pin_alloc_irq_channel(rt_uint32_t pin) +{ + rt_int32_t channel = ra_pin_find_irq_channel(pin); + + if (channel >= 0) + { + return channel; + } + + for (int i = 0; i < RA_WIRELESS_EXT_IRQ_MAX_CHANNEL; ++i) + { + if (ra_ext_irq_pin_to_channel[i] < 0) + { + ra_ext_irq_pin_to_channel[i] = (rt_int32_t) pin; + return i; + } + } + + return -1; +} + +static rt_bool_t ra_wireless_pin_valid(rt_base_t pin) +{ + rt_uint32_t port; + rt_uint32_t pin_id; + + if (pin < 0) + { + return RT_FALSE; + } + + port = ((rt_uint32_t) pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET; + pin_id = (rt_uint32_t) pin & BSP_IO_PIN_BITS; + + return (((BSP_IO_PORT_00 == port) && (pin_id < BSP_FEATURE_IO_PORT0_GPIO_COUNT)) || + ((BSP_IO_PORT_01 == port) && (pin_id < BSP_FEATURE_IO_PORT1_GPIO_COUNT))); +} + +static rt_bool_t ra_ext_irq_w_pin_supported(rt_base_t pin) +{ + rt_uint32_t port; + rt_uint32_t pin_id; + + if (pin < 0) + { + return RT_FALSE; + } + + port = ((rt_uint32_t) pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET; + pin_id = (rt_uint32_t) pin & BSP_IO_PIN_BITS; + + return (((BSP_IO_PORT_00 == port) && (pin_id <= 13U)) || + ((BSP_IO_PORT_01 == port) && (pin_id <= 15U))); +} + +static external_irq_trigger_t ra_pin_irq_mode_to_trigger(rt_uint8_t mode) +{ + switch (mode) + { + case PIN_IRQ_MODE_RISING: + return EXTERNAL_IRQ_TRIG_RISING; + case PIN_IRQ_MODE_FALLING: + return EXTERNAL_IRQ_TRIG_FALLING; + case PIN_IRQ_MODE_HIGH_LEVEL: + return EXTERNAL_IRQ_TRIG_LEVEL_HIGH; + case PIN_IRQ_MODE_LOW_LEVEL: + return EXTERNAL_IRQ_TRIG_LEVEL_LOW; + default: + return (external_irq_trigger_t) -1; + } +} + +static void ra_ext_irq_w_callback(external_irq_callback_args_t *p_args) +{ + struct rt_pin_irq_hdr *irq_hdr = (struct rt_pin_irq_hdr *) p_args->p_context; + + rt_interrupt_enter(); + if ((RT_NULL != irq_hdr) && (RT_NULL != irq_hdr->hdr)) + { + irq_hdr->hdr(irq_hdr->args); + } + rt_interrupt_leave(); +} + +static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + fsp_err_t err; + uint32_t cfg; + + RT_UNUSED(dev); + + if (!ra_wireless_pin_valid(pin)) + { + LOG_E("invalid pin: 0x%x", pin); + return; + } + + err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + if ((err != FSP_SUCCESS) && (err != FSP_ERR_ALREADY_OPEN)) + { + LOG_E("GPIO open failed"); + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + cfg = GPIO_W_CFG_PORT_DIRECTION_OUTPUT; + break; + + case PIN_MODE_INPUT: + cfg = GPIO_W_CFG_PORT_DIRECTION_INPUT; + break; + + case PIN_MODE_INPUT_PULLUP: + cfg = GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_PULLUP_ENABLE; + break; + + case PIN_MODE_INPUT_PULLDOWN: + cfg = GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_PULLDOWN_ENABLE; + break; + + case PIN_MODE_OUTPUT_OD: + cfg = GPIO_W_CFG_OPEN_DRAIN_ENABLE; + break; + + default: + LOG_E("unsupported pin mode: %d", mode); + return; + } + + err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t) pin, cfg); + if (err != FSP_SUCCESS) + { + LOG_E("pin mode configuration failed: %d", err); + } +} + +static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + bsp_io_level_t level = BSP_IO_LEVEL_HIGH; + + RT_UNUSED(dev); + + if (!ra_wireless_pin_valid(pin)) + { + LOG_E("invalid pin: 0x%x", pin); + return; + } + + if (value != level) + { + level = BSP_IO_LEVEL_LOW; + } + + R_BSP_PinAccessEnable(); + R_BSP_PinWrite(pin, level); + R_BSP_PinAccessDisable(); +} + +static rt_ssize_t ra_pin_read(rt_device_t dev, rt_base_t pin) +{ + RT_UNUSED(dev); + + if (!ra_wireless_pin_valid(pin)) + { + return -RT_EINVAL; + } + return R_BSP_PinRead(pin); +} + +static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) +{ + fsp_err_t err; + rt_int32_t irqx = ra_pin_find_irq_channel((rt_uint32_t) pin); + + RT_UNUSED(device); + + if ((irqx < 0) || (irqx >= RA_WIRELESS_EXT_IRQ_MAX_CHANNEL)) + { + return -RT_ERROR; + } + + if (PIN_IRQ_ENABLE == enabled) + { + err = R_EXT_IRQ_W_ExternalIrqOpen((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx], + (external_irq_cfg_t const *) &ra_ext_irq_cfg_tab[irqx]); + if ((FSP_SUCCESS != err) && (FSP_ERR_ALREADY_OPEN != err)) + { + LOG_E("R_EXT_IRQ_W_ExternalIrqOpen failed: %d", err); + return -RT_ERROR; + } + + err = R_EXT_IRQ_W_ExternalIrqEnable((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx]); + if (FSP_SUCCESS != err) + { + LOG_E("R_EXT_IRQ_W_ExternalIrqEnable failed: %d", err); + return -RT_ERROR; + } + } + else if (PIN_IRQ_DISABLE == enabled) + { + err = R_EXT_IRQ_W_ExternalIrqDisable((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx]); + if ((FSP_SUCCESS != err) && (FSP_ERR_NOT_OPEN != err)) + { + LOG_E("R_EXT_IRQ_W_ExternalIrqDisable failed: %d", err); + return -RT_ERROR; + } + + err = R_EXT_IRQ_W_ExternalIrqClose((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx]); + if ((FSP_SUCCESS != err) && (FSP_ERR_NOT_OPEN != err)) + { + LOG_E("R_EXT_IRQ_W_ExternalIrqClose failed: %d", err); + return -RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + rt_int32_t irqx; + external_irq_trigger_t trigger = ra_pin_irq_mode_to_trigger(mode); + + if (((external_irq_trigger_t) -1) == trigger) + { + LOG_W("RA Wireless EXT IRQ does not support mode %d", mode); + return -RT_EINVAL; + } + + RT_UNUSED(device); + + if (!ra_ext_irq_w_pin_supported(pin)) + { + return -RT_EINVAL; + } + + irqx = ra_pin_alloc_irq_channel((rt_uint32_t) pin); + if ((irqx < 0) || (irqx >= RA_WIRELESS_EXT_IRQ_MAX_CHANNEL)) + { + return -RT_ERROR; + } + + int level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqx].pin == pin && + pin_irq_hdr_tab[irqx].hdr == hdr && + pin_irq_hdr_tab[irqx].mode == mode && + pin_irq_hdr_tab[irqx].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + if (pin_irq_hdr_tab[irqx].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + + pin_irq_hdr_tab[irqx].pin = pin; + pin_irq_hdr_tab[irqx].hdr = hdr; + pin_irq_hdr_tab[irqx].mode = mode; + pin_irq_hdr_tab[irqx].args = args; + + ra_ext_irq_extend_tab[irqx].irq_pin = (bsp_io_port_pin_t) pin; + + ra_ext_irq_cfg_tab[irqx].channel = (uint8_t) irqx; + ra_ext_irq_cfg_tab[irqx].ipl = 4; + ra_ext_irq_cfg_tab[irqx].irq = FSP_INVALID_VECTOR; + ra_ext_irq_cfg_tab[irqx].trigger = trigger; + ra_ext_irq_cfg_tab[irqx].clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1; + ra_ext_irq_cfg_tab[irqx].filter_enable = false; + ra_ext_irq_cfg_tab[irqx].p_callback = ra_ext_irq_w_callback; + ra_ext_irq_cfg_tab[irqx].p_context = &pin_irq_hdr_tab[irqx]; + ra_ext_irq_cfg_tab[irqx].p_extend = &ra_ext_irq_extend_tab[irqx]; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_base_t pin) +{ + fsp_err_t err; + rt_int32_t irqx = ra_pin_find_irq_channel((rt_uint32_t) pin); + + RT_UNUSED(device); + + if ((irqx < 0) || (irqx >= RA_WIRELESS_EXT_IRQ_MAX_CHANNEL)) + { + return -RT_ERROR; + } + + err = R_EXT_IRQ_W_ExternalIrqDisable((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx]); + if ((FSP_SUCCESS != err) && (FSP_ERR_NOT_OPEN != err)) + { + return -RT_ERROR; + } + + err = R_EXT_IRQ_W_ExternalIrqClose((external_irq_ctrl_t *) &ra_ext_irq_ctrl_tab[irqx]); + if ((FSP_SUCCESS != err) && (FSP_ERR_NOT_OPEN != err)) + { + return -RT_ERROR; + } + + int level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqx].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + pin_irq_hdr_tab[irqx].pin = -1; + pin_irq_hdr_tab[irqx].hdr = RT_NULL; + pin_irq_hdr_tab[irqx].mode = 0; + pin_irq_hdr_tab[irqx].args = RT_NULL; + ra_ext_irq_pin_to_channel[irqx] = -1; + rt_memset(&ra_ext_irq_ctrl_tab[irqx], 0, sizeof(ra_ext_irq_ctrl_tab[irqx])); + rt_memset(&ra_ext_irq_cfg_tab[irqx], 0, sizeof(ra_ext_irq_cfg_tab[irqx])); + rt_memset(&ra_ext_irq_extend_tab[irqx], 0, sizeof(ra_ext_irq_extend_tab[irqx])); + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_base_t ra_pin_get(const char *name) +{ + rt_int32_t port = -1; + rt_int32_t pin = -1; + + if ((rt_strlen(name) == 5) && + ((name[0] == 'P') || (name[0] == 'p')) && + (name[2] == '_') && + ('0' <= (int) name[1] && (int) name[1] <= '9') && + ('0' <= (int) name[3] && (int) name[3] <= '9') && + ('0' <= (int) name[4] && (int) name[4] <= '9')) + { + port = (rt_int32_t) (name[1] - '0'); + pin = (rt_int32_t) ((name[3] - '0') * 10 + (name[4] - '0')); + } + else if ((rt_strlen(name) == 4) && + ((name[0] == 'P') || (name[0] == 'p')) && + ('0' <= (int) name[1] && (int) name[1] <= '9') && + ('0' <= (int) name[2] && (int) name[2] <= '9') && + ('0' <= (int) name[3] && (int) name[3] <= '9')) + { + port = (rt_int32_t) (name[1] - '0'); + pin = (rt_int32_t) ((name[2] - '0') * 10 + (name[3] - '0')); + } + + if ((port >= 0) && (pin >= 0) && (pin <= (rt_int32_t) BSP_IO_PIN_BITS)) + { + rt_base_t pin_value = (rt_base_t) ((port << BSP_IO_PORT_OFFSET) | pin); + if (ra_wireless_pin_valid(pin_value)) + { + return pin_value; + } + } + + LOG_W("Invalid pin expression, use `P0_06` or `P006` format"); + return -RT_ERROR; +} + +const static struct rt_pin_ops _ra_pin_ops = +{ + .pin_mode = ra_pin_mode, + .pin_write = ra_pin_write, + .pin_read = ra_pin_read, + .pin_attach_irq = ra_pin_attach_irq, + .pin_detach_irq = ra_pin_dettach_irq, + .pin_irq_enable = ra_pin_irq_enable, + .pin_get = ra_pin_get, +}; + +int rt_hw_pin_init(void) +{ + ra_irq_tab_init(); + return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL); +} + +#endif /* BSP_USING_GPIO_W */ + diff --git a/bsp/renesas/ra6w1-ek/board/ports/gpio_cfg.h b/bsp/renesas/ra6w1-ek/board/ports/gpio_cfg.h new file mode 100644 index 000000000000..ad2b4c86d17c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/board/ports/gpio_cfg.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-01-19 Sherman first version + */ + +/* Number of IRQ channels on the device */ +#define RA_IRQ_MAX 16 + +/* PIN to IRQx table */ +#define PIN2IRQX_TABLE \ +{ \ + switch (pin) \ + { \ + case BSP_IO_PORT_04_PIN_00: \ + case BSP_IO_PORT_02_PIN_06: \ + case BSP_IO_PORT_01_PIN_05: \ + return 0; \ + case BSP_IO_PORT_02_PIN_05: \ + case BSP_IO_PORT_01_PIN_01: \ + case BSP_IO_PORT_01_PIN_04: \ + return 1; \ + case BSP_IO_PORT_02_PIN_03: \ + case BSP_IO_PORT_01_PIN_00: \ + case BSP_IO_PORT_02_PIN_13: \ + return 2; \ + case BSP_IO_PORT_02_PIN_02: \ + case BSP_IO_PORT_01_PIN_10: \ + case BSP_IO_PORT_02_PIN_12: \ + return 3; \ + case BSP_IO_PORT_04_PIN_02: \ + case BSP_IO_PORT_01_PIN_11: \ + case BSP_IO_PORT_04_PIN_11: \ + return 4; \ + case BSP_IO_PORT_04_PIN_01: \ + case BSP_IO_PORT_03_PIN_02: \ + case BSP_IO_PORT_04_PIN_10: \ + return 5; \ + case BSP_IO_PORT_03_PIN_01: \ + case BSP_IO_PORT_00_PIN_00: \ + case BSP_IO_PORT_04_PIN_09: \ + return 6; \ + case BSP_IO_PORT_00_PIN_01: \ + case BSP_IO_PORT_04_PIN_08: \ + return 7; \ + case BSP_IO_PORT_00_PIN_02: \ + case BSP_IO_PORT_03_PIN_05: \ + case BSP_IO_PORT_04_PIN_15: \ + return 8; \ + case BSP_IO_PORT_00_PIN_04: \ + case BSP_IO_PORT_03_PIN_04: \ + case BSP_IO_PORT_04_PIN_14: \ + return 9; \ + case BSP_IO_PORT_00_PIN_05: \ + case BSP_IO_PORT_07_PIN_09: \ + return 10; \ + case BSP_IO_PORT_05_PIN_01: \ + case BSP_IO_PORT_00_PIN_06: \ + case BSP_IO_PORT_07_PIN_08: \ + return 11; \ + case BSP_IO_PORT_05_PIN_02: \ + case BSP_IO_PORT_00_PIN_08: \ + return 12; \ + case BSP_IO_PORT_00_PIN_15: \ + case BSP_IO_PORT_00_PIN_09: \ + return 13; \ + case BSP_IO_PORT_04_PIN_03: \ + case BSP_IO_PORT_05_PIN_12: \ + case BSP_IO_PORT_05_PIN_05: \ + return 14; \ + case BSP_IO_PORT_04_PIN_04: \ + case BSP_IO_PORT_05_PIN_11: \ + case BSP_IO_PORT_05_PIN_06: \ + return 15; \ + default : \ + return -1; \ + } \ +} + diff --git a/bsp/renesas/ra6w1-ek/docs/picture/ek-ra6w1.png b/bsp/renesas/ra6w1-ek/docs/picture/ek-ra6w1.png new file mode 100644 index 0000000000000000000000000000000000000000..52dcc2d11a6a080004ae23e19895a212ba3a5d8a GIT binary patch literal 830796 zcmZsCbzGEb_xB1YDKIqBLkuY?-3-zV(hQACcY{MoNq2WkiAZ<1baxKY-7oIy?mqi_ z|C-O-aoy*-PJhoiL5lJc&rx2W{PD*h&!r^6%76TUu>Hp$aP3IX9HQ0-*PJwImQ=M#SNTQ7#l`p6Zi{2r_4|a_jql)+KG0+! zzy0q|%XfLWSM!x-w`;T$O%8b z%K`N!eIoGXKkM7X03IKttueE=F zB0K$qUM9_1P8BQ*Cp5<*9==P&bOcXo6IM2%bipiTciKF zAdKxIg7mnekN$-3`@at7HXGs8_5ZVa!}!k!mFrjC8iPNe|F!Y|rSa!K?rUUXR)%q( z{lHpPUZwxvQ_%MC4?~iF9@_)oBa!z9XlF?O`CbdEjBt4AKa7xg^>a6{{$l+6-xqK9 z5F8Z#&-#~JKe?0Mt~*?W+@OlQ?P&gAj{g#amM=)e{yzJf4CD3x`S#y(VuOP02ReeS;oViOl=rED?8mW2P{;mtCd)QIk6^_H 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zbZ(s8d6BLmL+y}xlwa%?99@=DE*}nrT8@u&(1ms0E$!-2_62_EBa+Szuz*g5frpR>i3i4?Ajbj ztik*5;rEP|rPUtIgFTAb#EV(RALNS0;ulY|Uz*B|^?2~F_AiJu1#k^E6k_`yHLVix zrhbE8Lkb03S~B&wNAG^!w?g8@pAGXDPdAhT%$X#EV4Oh>Ys9WM{=11HJ%IT5&*-av zYFyN{s>fsDi1q`lA_>f^^YWtjtX&V2prci_@% literal 0 HcmV?d00001 diff --git a/bsp/renesas/ra6w1-ek/ra/SConscript b/bsp/renesas/ra6w1-ek/ra/SConscript new file mode 100644 index 000000000000..8daa4a4e3835 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/SConscript @@ -0,0 +1,55 @@ +Import("RTT_ROOT") +Import("rtconfig") +from building import * + +cwd = GetCurrentDir() +src = [] + +CPPPATH = [cwd + "/arm/CMSIS_6/CMSIS/Core/Include", + cwd + "/board/rrq61xxx_evb", + cwd + "/fsp/inc", + cwd + "/fsp/inc/api", + cwd + "/fsp/inc/instances", + cwd + "/fsp/src/bsp/cmsis/Device/RENESAS/Include", + cwd + "/fsp/src/bsp/mcu/all", + cwd + "/fsp/src/bsp_w/cmsis/Device/RENESAS/Include", + cwd + "/fsp/src/bsp_w/mcu/all", + cwd + "/fsp/src/bsp_w/mcu/ra6w1", + cwd + "/fsp/src/bsp_w/mcu/ra6w1/config"] + +src += Glob("./board/rrq61xxx_evb/*.c") +src += Glob("./fsp/src/bsp_w/cmsis/Device/RENESAS/Source/*.c") +src += Glob("./fsp/src/bsp_w/mcu/all/*.c") +src += Glob("./fsp/src/bsp_w/mcu/all/*.S") +src += Glob("./fsp/src/bsp_w/mcu/ra6w1/*.c") + +src += Glob("./fsp/src/r_gpio_w/*.c") +src += Glob("./fsp/src/r_uart_w/*.c") +src += Glob("./fsp/src/r_ext_irq_w/*.c") + +if GetDepend(["BSP_USING_ONCHIP_RTC"]): + src += Glob("./fsp/src/r_rtc_w/*.c") + +if GetDepend(["BSP_USING_SPI"]): + src += Glob("./fsp/src/r_spi_w/*.c") + +if GetDepend(["BSP_USING_ADC"]): + src += Glob("./fsp/src/r_adc_w/*.c") + +if GetDepend(["BSP_USING_TIM"]): + src += Glob("./fsp/src/r_tim_w/*.c") + +if GetDepend(["BSP_USING_WDT"]): + src += Glob("./fsp/src/r_wdog_w/*.c") + +if GetDepend(["BSP_USING_QSPI"]): + src += Glob("./fsp/src/r_qspi_w/*.c") + +if GetDepend(["BSP_USING_HW_I2C"]): + src += Glob("./fsp/src/r_i2c_master_w/*.c") + +if GetDepend(["BSP_USING_OSPI_FLASH"]): + src += Glob("./fsp/src/r_ospi_w/*.c") + +group = DefineGroup("ra", src, depend = [""], CPPPATH = CPPPATH) +Return("group") diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h new file mode 100644 index 000000000000..760c63057290 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_A_H +#define __CMSIS_ARMCLANG_A_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) ); +} + + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + // Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + // Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + // Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + // Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_A_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h new file mode 100644 index 000000000000..91ca6a2a5900 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_A_H +#define __CMSIS_CLANG_A_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) ); +} + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + // Permit access to VFP/NEON, registers by modifying CPACR + const uint32_t cpacr = __get_CPACR(); + __set_CPACR(cpacr | 0x00F00000ul); + __ISB(); + + // Enable VFP/NEON + const uint32_t fpexc = __get_FPEXC(); + __set_FPEXC(fpexc | 0x40000000ul); + + __ASM volatile( + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + : : : "cc", "r2" + ); + + // Initialise FPSCR to a known state + const uint32_t fpscr = __get_FPSCR(); + __set_FPSCR(fpscr & 0x00086060ul); +} + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma clang diagnostic pop + +#endif /* __CMSIS_CLANG_A_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h new file mode 100644 index 000000000000..582b1bc54fec --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions + */ + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +/******************************* VIRTUAL TIMER *******************************/ +/** see [ARM DDI 0406C.d] : + . §B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register" + . §B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register" + . §B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register" + . §B4.1.34 "CNTVCT, Counter-timer Virtual Count register" +**/ +/** \brief Set CNTV_TVAL + This function assigns the given value to VL1 Virtual Timer Value Register (CNTV_TVAL). + \param [in] value CNTV_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 0); +} + +/** \brief Get CNTV_TVAL + This function returns the value of the VL1 Virtual Timer Value Register (CNTV_TVAL). + \return CNTV_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 0); + return result; +} + +/** \brief Get CNTVCT + This function returns the value of the 64 bits VL1 Virtual Count Register (CNTVCT). + \return CNTVCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void) +{ + uint64_t result; + __get_CP64(15, 1, result, 14); + return result; +} + +/** \brief Set CNTV_CVAL + This function assigns the given value to 64bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL). + \param [in] value CNTV_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CVAL(uint64_t value) +{ + __set_CP64(15, 3, value, 14); +} + +/** \brief Get CNTV_CVAL + This function returns the value of the 64 bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL). + \return CNTV_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTV_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 3, result, 14); + return result; +} + +/** \brief Set CNTV_CTL + This function assigns the given value to VL1 Virtual Timer Control Register (CNTV_CTL). + \param [in] value CNTV_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 1); +} + +/** \brief Get CNTV_CTL register + \return CNTV_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 1); + return result; +} + +/***************************** VIRTUAL TIMER END *****************************/ +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set ICIMVAC + + Instruction Cache Invalidate + */ +__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 1); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h new file mode 100644 index 000000000000..5d2aaca75dd3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_A_H +#define __CMSIS_GCC_A_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + + +/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + // Permit access to VFP/NEON, registers by modifying CPACR + const uint32_t cpacr = __get_CPACR(); + __set_CPACR(cpacr | 0x00F00000ul); + __ISB(); + + // Enable VFP/NEON + const uint32_t fpexc = __get_FPEXC(); + __set_FPEXC(fpexc | 0x40000000ul); + + __ASM volatile( + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + : : : "cc", "r2" + ); + + // Initialise FPSCR to a known state + const uint32_t fpscr = __get_FPSCR(); + __set_FPSCR(fpscr & 0x00086060ul); +} + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_A_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h new file mode 100644 index 000000000000..3ddd0ba79a46 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2017-2018 IAR Systems + * Copyright (c) 2018-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_A_H__ +#define __CMSIS_ICCARM_A_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_A_H__ */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h new file mode 100644 index 000000000000..7264fb9367fb --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Interrupt Controller API Header File + */ + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +// Encoding in some early GIC implementations +#define IRQ_MODE_MODEL_Pos (13U) +#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) +#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model +#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 000000000000..446d21a918fa --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h new file mode 100644 index 000000000000..872e16c838a0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_clang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 000000000000..cf3f5b027ddc --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Compiler Generic Header File + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler above 6.10.1 (armclang) + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + + +/* + * LLVM/Clang Compiler + */ +#elif defined ( __clang__ ) + #include "cmsis_clang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 000000000000..4771466f0654 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,1006 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +#pragma GCC system_header /* treat file as system include file */ + +#include + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + return (int16_t)__builtin_bswap16(value); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if (__ARM_FEATURE_SAT >= 1) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 000000000000..849a8a4a15d3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core Version Definitions + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h new file mode 100644 index 000000000000..df5a95d7148a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h @@ -0,0 +1,3000 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-A Core Peripheral Access Layer Header File + */ + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#include "cmsis_version.h" + +/* CMSIS CA definitions */ + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U /*!< \brief Contains the core revision for a Cortex-A class device */ + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \ + defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/* GICDistributor CTLR Register */ +#define GICDistributor_CTLR_EnableGrp0_Pos 0U /*!< GICDistributor CTLR: EnableGrp0 Position */ +#define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/) /*!< GICDistributor CTLR: EnableGrp0 Mask */ +#define GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk) + +#define GICDistributor_CTLR_EnableGrp1_Pos 1U /*!< GICDistributor CTLR: EnableGrp1 Position */ +#define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos) /*!< GICDistributor CTLR: EnableGrp1 Mask */ +#define GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk) + +#define GICDistributor_CTLR_ARE_Pos 4U /*!< GICDistributor CTLR: ARE Position */ +#define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos) /*!< GICDistributor CTLR: ARE Mask */ +#define GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk) + +#define GICDistributor_CTLR_DC_Pos 6U /*!< GICDistributor CTLR: DC Position */ +#define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos) /*!< GICDistributor CTLR: DC Mask */ +#define GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk) + +#define GICDistributor_CTLR_EINWF_Pos 7U /*!< GICDistributor CTLR: EINWF Position */ +#define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos) /*!< GICDistributor CTLR: EINWF Mask */ +#define GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk) + +#define GICDistributor_CTLR_RWP_Pos 31U /*!< GICDistributor CTLR: RWP Position */ +#define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos) /*!< GICDistributor CTLR: RWP Mask */ +#define GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk) + +/* GICDistributor TYPER Register */ +#define GICDistributor_TYPER_ITLinesNumber_Pos 0U /*!< GICDistributor TYPER: ITLinesNumber Position */ +#define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */ +#define GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk) + +#define GICDistributor_TYPER_CPUNumber_Pos 5U /*!< GICDistributor TYPER: CPUNumber Position */ +#define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos) /*!< GICDistributor TYPER: CPUNumber Mask */ +#define GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk) + +#define GICDistributor_TYPER_SecurityExtn_Pos 10U /*!< GICDistributor TYPER: SecurityExtn Position */ +#define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos) /*!< GICDistributor TYPER: SecurityExtn Mask */ +#define GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk) + +#define GICDistributor_TYPER_LSPI_Pos 11U /*!< GICDistributor TYPER: LSPI Position */ +#define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos) /*!< GICDistributor TYPER: LSPI Mask */ +#define GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk) + +/* GICDistributor IIDR Register */ +#define GICDistributor_IIDR_Implementer_Pos 0U /*!< GICDistributor IIDR: Implementer Position */ +#define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/) /*!< GICDistributor IIDR: Implementer Mask */ +#define GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk) + +#define GICDistributor_IIDR_Revision_Pos 12U /*!< GICDistributor IIDR: Revision Position */ +#define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos) /*!< GICDistributor IIDR: Revision Mask */ +#define GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk) + +#define GICDistributor_IIDR_Variant_Pos 16U /*!< GICDistributor IIDR: Variant Position */ +#define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos) /*!< GICDistributor IIDR: Variant Mask */ +#define GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk) + +#define GICDistributor_IIDR_ProductID_Pos 24U /*!< GICDistributor IIDR: ProductID Position */ +#define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos) /*!< GICDistributor IIDR: ProductID Mask */ +#define GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk) + +/* GICDistributor STATUSR Register */ +#define GICDistributor_STATUSR_RRD_Pos 0U /*!< GICDistributor STATUSR: RRD Position */ +#define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/) /*!< GICDistributor STATUSR: RRD Mask */ +#define GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk) + +#define GICDistributor_STATUSR_WRD_Pos 1U /*!< GICDistributor STATUSR: WRD Position */ +#define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos) /*!< GICDistributor STATUSR: WRD Mask */ +#define GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk) + +#define GICDistributor_STATUSR_RWOD_Pos 2U /*!< GICDistributor STATUSR: RWOD Position */ +#define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos) /*!< GICDistributor STATUSR: RWOD Mask */ +#define GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk) + +#define GICDistributor_STATUSR_WROD_Pos 3U /*!< GICDistributor STATUSR: WROD Position */ +#define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos) /*!< GICDistributor STATUSR: WROD Mask */ +#define GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk) + +/* GICDistributor SETSPI_NSR Register */ +#define GICDistributor_SETSPI_NSR_INTID_Pos 0U /*!< GICDistributor SETSPI_NSR: INTID Position */ +#define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/) /*!< GICDistributor SETSPI_NSR: INTID Mask */ +#define GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk) + +/* GICDistributor CLRSPI_NSR Register */ +#define GICDistributor_CLRSPI_NSR_INTID_Pos 0U /*!< GICDistributor CLRSPI_NSR: INTID Position */ +#define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/) /*!< GICDistributor CLRSPI_NSR: INTID Mask */ +#define GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk) + +/* GICDistributor SETSPI_SR Register */ +#define GICDistributor_SETSPI_SR_INTID_Pos 0U /*!< GICDistributor SETSPI_SR: INTID Position */ +#define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/) /*!< GICDistributor SETSPI_SR: INTID Mask */ +#define GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk) + +/* GICDistributor CLRSPI_SR Register */ +#define GICDistributor_CLRSPI_SR_INTID_Pos 0U /*!< GICDistributor CLRSPI_SR: INTID Position */ +#define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/) /*!< GICDistributor CLRSPI_SR: INTID Mask */ +#define GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk) + +/* GICDistributor ITARGETSR Register */ +#define GICDistributor_ITARGETSR_CPU0_Pos 0U /*!< GICDistributor ITARGETSR: CPU0 Position */ +#define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/) /*!< GICDistributor ITARGETSR: CPU0 Mask */ +#define GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk) + +#define GICDistributor_ITARGETSR_CPU1_Pos 1U /*!< GICDistributor ITARGETSR: CPU1 Position */ +#define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos) /*!< GICDistributor ITARGETSR: CPU1 Mask */ +#define GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk) + +#define GICDistributor_ITARGETSR_CPU2_Pos 2U /*!< GICDistributor ITARGETSR: CPU2 Position */ +#define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos) /*!< GICDistributor ITARGETSR: CPU2 Mask */ +#define GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk) + +#define GICDistributor_ITARGETSR_CPU3_Pos 3U /*!< GICDistributor ITARGETSR: CPU3 Position */ +#define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos) /*!< GICDistributor ITARGETSR: CPU3 Mask */ +#define GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk) + +#define GICDistributor_ITARGETSR_CPU4_Pos 4U /*!< GICDistributor ITARGETSR: CPU4 Position */ +#define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos) /*!< GICDistributor ITARGETSR: CPU4 Mask */ +#define GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk) + +#define GICDistributor_ITARGETSR_CPU5_Pos 5U /*!< GICDistributor ITARGETSR: CPU5 Position */ +#define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos) /*!< GICDistributor ITARGETSR: CPU5 Mask */ +#define GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk) + +#define GICDistributor_ITARGETSR_CPU6_Pos 6U /*!< GICDistributor ITARGETSR: CPU6 Position */ +#define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos) /*!< GICDistributor ITARGETSR: CPU6 Mask */ +#define GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk) + +#define GICDistributor_ITARGETSR_CPU7_Pos 7U /*!< GICDistributor ITARGETSR: CPU7 Position */ +#define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos) /*!< GICDistributor ITARGETSR: CPU7 Mask */ +#define GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk) + +/* GICDistributor SGIR Register */ +#define GICDistributor_SGIR_INTID_Pos 0U /*!< GICDistributor SGIR: INTID Position */ +#define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/) /*!< GICDistributor SGIR: INTID Mask */ +#define GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk) + +#define GICDistributor_SGIR_NSATT_Pos 15U /*!< GICDistributor SGIR: NSATT Position */ +#define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos) /*!< GICDistributor SGIR: NSATT Mask */ +#define GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk) + +#define GICDistributor_SGIR_CPUTargetList_Pos 16U /*!< GICDistributor SGIR: CPUTargetList Position */ +#define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos) /*!< GICDistributor SGIR: CPUTargetList Mask */ +#define GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk) + +#define GICDistributor_SGIR_TargetFilterList_Pos 24U /*!< GICDistributor SGIR: TargetFilterList Position */ +#define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */ +#define GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk) + +/* GICDistributor IROUTER Register */ +#define GICDistributor_IROUTER_Aff0_Pos 0UL /*!< GICDistributor IROUTER: Aff0 Position */ +#define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/) /*!< GICDistributor IROUTER: Aff0 Mask */ +#define GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk) + +#define GICDistributor_IROUTER_Aff1_Pos 8UL /*!< GICDistributor IROUTER: Aff1 Position */ +#define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos) /*!< GICDistributor IROUTER: Aff1 Mask */ +#define GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk) + +#define GICDistributor_IROUTER_Aff2_Pos 16UL /*!< GICDistributor IROUTER: Aff2 Position */ +#define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos) /*!< GICDistributor IROUTER: Aff2 Mask */ +#define GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk) + +#define GICDistributor_IROUTER_IRM_Pos 31UL /*!< GICDistributor IROUTER: IRM Position */ +#define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos) /*!< GICDistributor IROUTER: IRM Mask */ +#define GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk) + +#define GICDistributor_IROUTER_Aff3_Pos 32UL /*!< GICDistributor IROUTER: Aff3 Position */ +#define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos) /*!< GICDistributor IROUTER: Aff3 Mask */ +#define GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk) + + + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ + +/* GICInterface CTLR Register */ +#define GICInterface_CTLR_Enable_Pos 0U /*!< PTIM CTLR: Enable Position */ +#define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/) /*!< PTIM CTLR: Enable Mask */ +#define GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk) + +/* GICInterface PMR Register */ +#define GICInterface_PMR_Priority_Pos 0U /*!< PTIM PMR: Priority Position */ +#define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/) /*!< PTIM PMR: Priority Mask */ +#define GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk) + +/* GICInterface BPR Register */ +#define GICInterface_BPR_Binary_Point_Pos 0U /*!< PTIM BPR: Binary_Point Position */ +#define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */ +#define GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk) + +/* GICInterface IAR Register */ +#define GICInterface_IAR_INTID_Pos 0U /*!< PTIM IAR: INTID Position */ +#define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/) /*!< PTIM IAR: INTID Mask */ +#define GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk) + +/* GICInterface EOIR Register */ +#define GICInterface_EOIR_INTID_Pos 0U /*!< PTIM EOIR: INTID Position */ +#define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/) /*!< PTIM EOIR: INTID Mask */ +#define GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk) + +/* GICInterface RPR Register */ +#define GICInterface_RPR_INTID_Pos 0U /*!< PTIM RPR: INTID Position */ +#define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/) /*!< PTIM RPR: INTID Mask */ +#define GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk) + +/* GICInterface HPPIR Register */ +#define GICInterface_HPPIR_INTID_Pos 0U /*!< PTIM HPPIR: INTID Position */ +#define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/) /*!< PTIM HPPIR: INTID Mask */ +#define GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk) + +/* GICInterface ABPR Register */ +#define GICInterface_ABPR_Binary_Point_Pos 0U /*!< PTIM ABPR: Binary_Point Position */ +#define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */ +#define GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk) + +/* GICInterface AIAR Register */ +#define GICInterface_AIAR_INTID_Pos 0U /*!< PTIM AIAR: INTID Position */ +#define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/) /*!< PTIM AIAR: INTID Mask */ +#define GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk) + +/* GICInterface AEOIR Register */ +#define GICInterface_AEOIR_INTID_Pos 0U /*!< PTIM AEOIR: INTID Position */ +#define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */ +#define GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk) + +/* GICInterface AHPPIR Register */ +#define GICInterface_AHPPIR_INTID_Pos 0U /*!< PTIM AHPPIR: INTID Position */ +#define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */ +#define GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk) + +/* GICInterface STATUSR Register */ +#define GICInterface_STATUSR_RRD_Pos 0U /*!< GICInterface STATUSR: RRD Position */ +#define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/) /*!< GICInterface STATUSR: RRD Mask */ +#define GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk) + +#define GICInterface_STATUSR_WRD_Pos 1U /*!< GICInterface STATUSR: WRD Position */ +#define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos) /*!< GICInterface STATUSR: WRD Mask */ +#define GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk) + +#define GICInterface_STATUSR_RWOD_Pos 2U /*!< GICInterface STATUSR: RWOD Position */ +#define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos) /*!< GICInterface STATUSR: RWOD Mask */ +#define GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk) + +#define GICInterface_STATUSR_WROD_Pos 3U /*!< GICInterface STATUSR: WROD Position */ +#define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos) /*!< GICInterface STATUSR: WROD Mask */ +#define GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk) + +#define GICInterface_STATUSR_ASV_Pos 4U /*!< GICInterface STATUSR: ASV Position */ +#define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos) /*!< GICInterface STATUSR: ASV Mask */ +#define GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk) + +/* GICInterface IIDR Register */ +#define GICInterface_IIDR_Implementer_Pos 0U /*!< GICInterface IIDR: Implementer Position */ +#define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/) /*!< GICInterface IIDR: Implementer Mask */ +#define GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk) + +#define GICInterface_IIDR_Revision_Pos 12U /*!< GICInterface IIDR: Revision Position */ +#define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos) /*!< GICInterface IIDR: Revision Mask */ +#define GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk) + +#define GICInterface_IIDR_Arch_version_Pos 16U /*!< GICInterface IIDR: Arch_version Position */ +#define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos) /*!< GICInterface IIDR: Arch_version Mask */ +#define GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk) + +#define GICInterface_IIDR_ProductID_Pos 20U /*!< GICInterface IIDR: ProductID Position */ +#define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos) /*!< GICInterface IIDR: ProductID Mask */ +#define GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk) + +/* GICInterface DIR Register */ +#define GICInterface_DIR_INTID_Pos 0U /*!< PTIM DIR: INTID Position */ +#define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/) /*!< PTIM DIR: INTID Mask */ +#define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk) +#endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */ + +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ + +/* PTIM Control Register */ +#define PTIM_CONTROL_Enable_Pos 0U /*!< PTIM CONTROL: Enable Position */ +#define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/) /*!< PTIM CONTROL: Enable Mask */ +#define PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk) + +#define PTIM_CONTROL_AutoReload_Pos 1U /*!< PTIM CONTROL: Auto Reload Position */ +#define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos) /*!< PTIM CONTROL: Auto Reload Mask */ +#define PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk) + +#define PTIM_CONTROL_IRQenable_Pos 2U /*!< PTIM CONTROL: IRQ Enabel Position */ +#define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos) /*!< PTIM CONTROL: IRQ Enabel Mask */ +#define PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk) + +#define PTIM_CONTROL_Prescaler_Pos 8U /*!< PTIM CONTROL: Prescaler Position */ +#define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos) /*!< PTIM CONTROL: Prescaler Mask */ +#define PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk) + +/* WCONTROL Watchdog Control Register */ +#define PTIM_WCONTROL_Enable_Pos 0U /*!< PTIM WCONTROL: Enable Position */ +#define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/) /*!< PTIM WCONTROL: Enable Mask */ +#define PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk) + +#define PTIM_WCONTROL_AutoReload_Pos 1U /*!< PTIM WCONTROL: Auto Reload Position */ +#define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos) /*!< PTIM WCONTROL: Auto Reload Mask */ +#define PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk) + +#define PTIM_WCONTROL_IRQenable_Pos 2U /*!< PTIM WCONTROL: IRQ Enable Position */ +#define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos) /*!< PTIM WCONTROL: IRQ Enable Mask */ +#define PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk) + +#define PTIM_WCONTROL_Mode_Pos 3U /*!< PTIM WCONTROL: Watchdog Mode Position */ +#define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos) /*!< PTIM WCONTROL: Watchdog Mode Mask */ +#define PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk) + +#define PTIM_WCONTROL_Presacler_Pos 8U /*!< PTIM WCONTROL: Prescaler Position */ +#define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos) /*!< PTIM WCONTROL: Prescaler Mask */ +#define PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk) + +/* WISR Watchdog Interrupt Status Register */ +#define PTIM_WISR_EventFlag_Pos 0U /*!< PTIM WISR: Event Flag Position */ +#define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/) /*!< PTIM WISR: Event Flag Mask */ +#define PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk) + +/* WRESET Watchdog Reset Status */ +#define PTIM_WRESET_ResetFlag_Pos 0U /*!< PTIM WRESET: Reset Flag Position */ +#define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/) /*!< PTIM WRESET: Reset Flag Mask */ +#define PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk) + +#endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */ +#endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */ + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Clean instruction cache line by address. +* \param [in] va Pointer to instructions to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) { + __set_ICIMVAC((uint32_t)va); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + uint8_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if (log2_num_ways > 32U) { + return; // FATAL ERROR + } + shift_way = 32U - log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \ + defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; /* read current register content */ + uint32_t shift = (IRQn % 16U) << 1U; /* calculate shift value */ + + int_config &= 3U; /* only 2 bits are valid */ + icfgr &= (~(3U << shift)); /* clear bits to change */ + icfgr |= ( int_config << shift); /* set new configuration */ + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; /* write new register content */ +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} + +/******************************* VIRTUAL TIMER *******************************/ +/** \brief Virtual Timer Control register */ + +/** \brief Sets the reset value of the virtual timer. +* \param [in] value The value the virtual timer is loaded with. +*/ +__STATIC_INLINE void VL1_SetCurrentTimerValue(uint32_t value) +{ + __set_CNTV_TVAL(value); + __ISB(); +} + +/** \brief Get the current virtual timer value. +* \return Current virtual timer value. +*/ +__STATIC_INLINE uint32_t VL1_GetCurrentTimerValue(void) +{ + return(__get_CNTV_TVAL()); +} + +/** \brief Get the current virtual count value. +* \return Current virtual count value. +*/ +__STATIC_INLINE uint64_t VL1_GetCurrentCountValue(void) +{ + return(__get_CNTVCT()); +} + +/** \brief Set the virtual timer compare value. +* \param [in] value New virtual timer compare value. +*/ +__STATIC_INLINE void VL1_SetTimerCompareValue(uint64_t value) +{ + __set_CNTV_CVAL(value); + __ISB(); +} + +/** \brief Get the virtual timer compare value. +* \return Virtual timer compare value. +*/ +__STATIC_INLINE uint64_t VL1_GetTimerCompareValue(void) +{ + return(__get_CNTV_CVAL()); +} + +/** \brief Configure the virtual timer by setting the control value. +* \param [in] value New virtual timer control value. +*/ +__STATIC_INLINE void VL1_SetControl(uint32_t value) +{ + __set_CNTV_CTL(value); + __ISB(); +} + +/** \brief Get the virtual timer control value. +* \return Virtual timer control value. +*/ +__STATIC_INLINE uint32_t VL1_GetControl(void) +{ + return(__get_CNTV_CTL()); +} +/***************************** VIRTUAL TIMER END *****************************/ +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 000000000000..eeb599fc77f0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,967 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 000000000000..1ee9457560f0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 000000000000..d41cf05b3369 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,992 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 000000000000..d6337a4848bc --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2253 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M23 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM23 definitions */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED14[992U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/* NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/* NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 000000000000..624b9f69b02c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,2045 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M3 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 000000000000..5f7d9b1575c5 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 000000000000..def2589fadb1 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M35P Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35 definitions */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 000000000000..8354ccfbcffd --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2237 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M4 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h new file mode 100644 index 000000000000..a6195940426b --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h @@ -0,0 +1,4783 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. Copyright (c) 2024 Arm Technology (China) Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M52 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM52_H_GENERIC +#define __CORE_CM52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M52 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM52 definitions */ + +#define __CORTEX_M (52U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM52_H_DEPENDANT +#define __CORE_CM52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM52_REV + #define __CM52_REV 0x0002U + #warning "__CM52_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __UCACHE_PRESENT + #define __UCACHE_PRESENT 0U + #warning "__UCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M52 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED0[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED1[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED2[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED3[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED4[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_CTYPE1_Pos 0U +#define SCB_CLIDR_CTYPE1_Msk (7UL << SCB_CLIDR_CTYPE1_Pos) + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/** \brief SCB U-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_UC_WAY_Pos 31U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_UC_WAY_Msk (1UL << SCB_DCISW_UC_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_UC_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_UC_SET_Msk (0x3FFUL << SCB_DCISW_UC_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB U-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_UC_WAY_Pos 31U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_UC_WAY_Msk (1UL << SCB_DCCSW_UC_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_UC_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_UC_SET_Msk (0x3FFUL << SCB_DCCSW_UC_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB U-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_UC_WAY_Pos 31U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_UC_WAY_Msk (1UL << SCB_DCCISW_UC_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_UC_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_UC_SET_Msk (0x3FFUL << SCB_DCCISW_UC_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + uint32_t RESERVED1[3U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup DCAR_Type Direct Cache Access Registers + \brief Type definitions for the Direct Cache Access Registers (DCAR) + @{ + */ + +/** + \brief Structure type to access the Direct Cache Access Registers (DCAR). + */ +typedef struct +{ + __IM uint32_t DCADCRR; /*!< Offset: 0x000 (R/W) Direct Cache Access Data Cache Read Register */ + __IM uint32_t DCAICRR; /*!< Offset: 0x004 (R/W) Direct Cache Access Instruction Cache Read Register */ + uint32_t RESERVED1[2]; + __IOM uint32_t DCADCLR; /*!< Offset: 0x010 (R/W) Direct Cache Access Data Cache Location Registers */ + __IOM uint32_t DCAICLR; /*!< Offset: 0x014 (R/W) Direct Cache Access Instruction Cache Location Registers */ +} DCAR_Type; + +/*@}*/ /* end of group DCAR_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + __IM uint32_t TEBRDATA0; /*!< Offset: 0x024 (RO) Storage for corrected data that is associated with an error.*/ + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ + __IM uint32_t TEBRDATA1; /*!< Offset: 0x02c (RO) Storage for corrected data that is associated with an error.*/ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 27U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 26U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 27U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 26U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLDMPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register Definitions */ +#define STL_STLDMPUOR_HITREGION_Pos 9U /*!< STL STLDMPUOR: HITREGION Position */ +#define STL_STLDMPUOR_HITREGION_Msk (0xFFUL << STL_STLDMPUOR_HITREGION_Pos) /*!< STL STLDMPUOR: HITREGION Mask */ + +#define STL_STLDMPUOR_ATTR_Pos 0U /*!< STL STLDMPUOR: ATTR Position */ +#define STL_STLDMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLDMPUOR_ATTR_Pos*/) /*!< STL STLDMPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define DCAR_BASE (0xE001E200UL) /*!< Direct Cache Access Registers */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define DCAR ((DCAR_Type *) DCAR_BASE ) /*!< Direct Read Access to the embedded RAM associated with the L1 instruction and data cache */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M52 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM52_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM52_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM52_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM52_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM52_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM52_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM52_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM52_PMU_AXI_SAHB_WRITE_ACCESS 0xC302 /*!< M-AXI configuration: Any beat access to the M-AXI write interface.M-AHB configuration: Any write beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_AXI_SAHB_READ_ACCESS 0xC303 /*!< M-AXI configuration: Any beat access to the M-AXI read interface.M-AHB configuration: Any read beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM52_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM52_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM52_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM52_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM52_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM52_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM52_PMU_CAHB_WRITE_ACCESS 0xC420 /*!< M-AHB configuration: A Write beat transfer on Code-AHB */ +#define ARMCM52_PMU_CAHB_READ_ACCESS 0xC421 /*!< M-AHB configuration: A Read beat transfer on Code-AHB. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + + + + + diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 000000000000..a7c9f7436b4e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4895 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M55 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM55_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM55_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM55_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM55_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM55_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM55_PMU_PF_LF_LA_1 0xC41C /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */ +#define ARMCM55_PMU_PF_LF_LA_2 0xC41D /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */ +#define ARMCM55_PMU_PF_LF_LA_3 0xC41E /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */ +#define ARMCM55_PMU_PF_LF_LA_4 0xC41F /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */ +#define ARMCM55_PMU_PF_LF_LA_5 0xC420 /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */ +#define ARMCM55_PMU_PF_LF_LA_6 0xC421 /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */ +#define ARMCM55_PMU_PF_BUFFER_FULL 0xC422 /*!< A data prefetcher request is made while the buffer is full. */ +#define ARMCM55_PMU_PF_BUFFER_MISS 0xC423 /*!< A load requires a line-fill which misses in the data prefetcher buffer. */ +#define ARMCM55_PMU_PF_BUFFER_HIT 0xC424 /*!< A load access hits in the data prefetcher buffer. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 000000000000..182081940b7f --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2468 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M7 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/** \brief SCB Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief SCB Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief SCB AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/** \brief SCB L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/** \brief SCB AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/** \brief SCB Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 000000000000..8a8b8954f958 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4936 @@ +/* + * Copyright (c) 2022-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M85 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + __IM uint32_t STLD2MPUOR; /*!< Offset: 0x020 (R/ ) MPU Memory Attributes Register 2 */ + __IM uint32_t STLD3MPUOR; /*!< Offset: 0x024 (R/ ) MPU Memory Attributes Register 3 */ + __IOM uint32_t STLSTBSLOTSR; /*!< Offset: 0x028 (R/W) STB Control Register */ + __IOM uint32_t STLLFDENTRYSR; /*!< Offset: 0x02C (R/W) LFD Control Register */ +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 2 Definitions */ +#define STL_STLD2MPUOR_HITREGION_Pos 9U /*!< STL STLD2MPUOR: HITREGION Position */ +#define STL_STLD2MPUOR_HITREGION_Msk (0xFFUL << STL_STLD2MPUOR_HITREGION_Pos) /*!< STL STLD2MPUOR: HITREGION Mask */ + +#define STL_STLD2MPUOR_ATTR_Pos 0U /*!< STL STLD2MPUOR: ATTR Position */ +#define STL_STLD2MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD2MPUOR_ATTR_Pos*/) /*!< STL STLD2MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 3 Definitions */ +#define STL_STLD3MPUOR_HITREGION_Pos 9U /*!< STL STLD3MPUOR: HITREGION Position */ +#define STL_STLD3MPUOR_HITREGION_Msk (0xFFUL << STL_STLD3MPUOR_HITREGION_Pos) /*!< STL STLD3MPUOR: HITREGION Mask */ + +#define STL_STLD3MPUOR_ATTR_Pos 0U /*!< STL STLD3MPUOR: ATTR Position */ +#define STL_STLD3MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD3MPUOR_ATTR_Pos*/) /*!< STL STLD3MPUOR: ATTR Mask */ + +/** \brief STL STB Control Register Definitions */ +#define STL_STLSTBSLOTSR_VALID_Pos 4U /*!< STL STLSTBSLOTSR: VALID Position */ +#define STL_STLSTBSLOTSR_VALID_Msk (1UL << STL_STLSTBSLOTSR_VALID_Pos) /*!< STL STLSTBSLOTSR: VALID Mask */ + +#define STL_STLSTBSLOTSR_STBSLOTNUM_Pos 0U /*!< STL STLSTBSLOTSR: STBSLOTNUM Position */ +#define STL_STLSTBSLOTSR_STBSLOTNUM_Msk (0xFUL /*<< STL_STLSTBSLOTSR_STBSLOTNUM_Pos*/) /*!< STL STLSTBSLOTSR: STBSLOTNUM Mask */ + +/** \brief STL LFD Control Register Definitions */ +#define STL_STLLFDENTRYSR_VALID_Pos 4U /*!< STL STLLFDENTRYSR: VALID Position */ +#define STL_STLLFDENTRYSR_VALID_Msk (1UL << STL_STLLFDENTRYSR_VALID_Pos) /*!< STL STLLFDENTRYSR: VALID Mask */ + +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Pos 0U /*!< STL STLLFDENTRYSR: LFDENTRYNUM Position */ +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Msk (0xFUL /*<< STL_STLLFDENTRYSR_LFDENTRYNUM_Pos*/) /*!< STL STLLFDENTRYSR: LFDENTRYNUM Mask */ +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM85_PMU_FUSED_INST_RETIRED 0xC500 /*!< Fused instructions architecturally executed */ +#define ARMCM85_PMU_BR_INDIRECT 0xC501 /*!< Indirect branch instruction architecturally executed */ +#define ARMCM85_PMU_BTAC_HIT 0xC502 /*!< BTAC branch predictor hit */ +#define ARMCM85_PMU_BTAC_HIT_RETURNS 0xC503 /*!< Return branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_CALLS 0xC504 /*!< Call branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_INDIRECT 0xC505 /*!< Indirect branch hits BTACT */ +#define ARMCM85_PMU_BTAC_NEW_ALLOC 0xC506 /*!< New allocation to BTAC */ +#define ARMCM85_PMU_BR_IND_MIS_PRED 0xC507 /*!< Indirect branch mis-predicted */ +#define ARMCM85_PMU_BR_RETURN_MIS_PRED 0xC508 /*!< Return branch mis-predicted */ +#define ARMCM85_PMU_BR_BTAC_OFFSET_OVERFLOW 0xC509 /*!< Branch does not allocate in BTAC due to offset overflow */ +#define ARMCM85_PMU_STB_FULL_STALL_AXI 0xC50A /*!< STore Buffer (STB) full with AXI requests causing CPU to stall */ +#define ARMCM85_PMU_STB_FULL_STALL_TCM 0xC50B /*!< STB full with TCM requests causing CPU to stall */ +#define ARMCM85_PMU_CPU_STALLED_AHBS 0xC50C /*!< CPU is stalled because TCM access through AHBS */ +#define ARMCM85_PMU_AHBS_STALLED_CPU 0xC50D /*!< AHBS is stalled due to TCM access by CPU */ +#define ARMCM85_PMU_BR_INTERSTATING_MIS_PRED 0xC50E /*!< Inter-stating branch is mis-predicted. */ +#define ARMCM85_PMU_DWT_STALL 0xC50F /*!< Data Watchpoint and Trace (DWT) stall */ +#define ARMCM85_PMU_DWT_FLUSH 0xC510 /*!< DWT flush */ +#define ARMCM85_PMU_ETM_STALL 0xC511 /*!< Embedded Trace Macrocell (ETM) stall */ +#define ARMCM85_PMU_ETM_FLUSH 0xC512 /*!< ETM flush */ +#define ARMCM85_PMU_ADDRESS_BANK_CONFLICT 0xC513 /*!< Bank conflict prevents memory instruction dual issue */ +#define ARMCM85_PMU_BLOCKED_DUAL_ISSUE 0xC514 /*!< Dual instruction issuing is prevented */ +#define ARMCM85_PMU_FP_CONTEXT_TRIGGER 0xC515 /*!< Floating Point Context is created */ +#define ARMCM85_PMU_TAIL_CHAIN 0xC516 /*!< New exception is handled without first unstacking */ +#define ARMCM85_PMU_LATE_ARRIVAL 0xC517 /*!< Late-arriving exception taken during exception entry */ +#define ARMCM85_PMU_INT_STALL_FAULT 0xC518 /*!< Delayed exception entry due to ongoing fault processing */ +#define ARMCM85_PMU_INT_STALL_DEV 0xC519 /*!< Delayed exception entry due to outstanding device access */ +#define ARMCM85_PMU_PAC_STALL 0xC51A /*!< Stall caused by authentication code computation */ +#define ARMCM85_PMU_PAC_RETIRED 0xC51B /*!< PAC instruction architecturally executed */ +#define ARMCM85_PMU_AUT_RETIRED 0xC51C /*!< AUT instruction architecturally executed */ +#define ARMCM85_PMU_BTI_RETIRED 0xC51D /*!< BTI instruction architecturally executed */ +#define ARMCM85_PMU_PF_NL_MODE 0xC51E /*!< Prefetch in next line mode */ +#define ARMCM85_PMU_PF_STREAM_MODE 0xC51F /*!< Prefetch in stream mode */ +#define ARMCM85_PMU_PF_BUFF_CACHE_HIT 0xC520 /*!< Prefetch request that hit in the cache */ +#define ARMCM85_PMU_PF_REQ_LFB_HIT 0xC521 /*!< Prefetch request that hit in line fill buffers */ +#define ARMCM85_PMU_PF_BUFF_FULL 0xC522 /*!< Number of times prefetch buffer is full */ +#define ARMCM85_PMU_PF_REQ_DCACHE_HIT 0xC523 /*!< Generated prefetch request address that hit in D-Cache */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 000000000000..4d85c48d0817 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC000 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ + +#define __CORTEX_SC (000U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 000000000000..670d9114133f --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,2028 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC300 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ + +#define __CORTEX_SC (300U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 000000000000..3b4e93e41352 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3614 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ + +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +} EMSS_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/** \brief Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h new file mode 100644 index 000000000000..d7338a72e0a3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h new file mode 100644 index 000000000000..5a4eba231c17 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h new file mode 100644 index 000000000000..648cf886476c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h new file mode 100644 index 000000000000..d743af12c787 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h new file mode 100644 index 000000000000..fb1653317304 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h new file mode 100644 index 000000000000..82fb6d46f435 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h @@ -0,0 +1,818 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h new file mode 100644 index 000000000000..a594442664c2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CMSIS_CLANG_M_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h new file mode 100644 index 000000000000..54d1f5495779 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h new file mode 100644 index 000000000000..cfc6f8083653 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h @@ -0,0 +1,1043 @@ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + #endif + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + + /* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + */ + #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extension and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h new file mode 100644 index 000000000000..5b193a17a5dc --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h @@ -0,0 +1,1451 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h new file mode 100644 index 000000000000..fd9f0e9a16f6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_armclang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_R_H +#define __CMSIS_ARMCLANG_R_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_ARMCLANG_R_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h new file mode 100644 index 000000000000..f27eef08f6cf --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_clang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_CORER_H +#define __CMSIS_CLANG_CORER_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_CLANG_COREA_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h new file mode 100644 index 000000000000..be2117c953e3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file cmsis_gcc_r.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 4. August 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_R_H +#define __CMSIS_GCC_R_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + + +/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_R_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h new file mode 100644 index 000000000000..e095956a8cb3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core(M) Context Management for Armv8-M TrustZone + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/LICENSE b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/LICENSE new file mode 100644 index 000000000000..8dada3edaf50 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/arm/CMSIS_6/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "{}" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board.h b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board.h new file mode 100644 index 000000000000..808fbe3c8d7a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board.h @@ -0,0 +1,51 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RRQ61XXX_EVB BSP for the RRQ61XXX EVB + * @brief BSP for the RRQ61XXX EVB + * + * The RRQ61XXX_EVB is a development kit for the Renesas RRQ61XXX EVB. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#ifndef __ASSEMBLER__ + #include "board_init.h" + #include "board_leds.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RRQ61XXX_EVB + +#define __IOM volatile + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RRQ61XXX_EVB) */ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_init.h b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_init.h new file mode 100644 index 000000000000..e1f326311da2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_init.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RRQ61XXX_EVB + * @defgroup BOARD_RRQ61XXX_EVB_INIT + * @brief Board specific code for the RRQ61XXX EVB + * + * This include file is specific to the RRQ61XXX EVB. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of t + * his file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RRQ61XXX_EVB_INIT) */ diff --git a/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.c b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.c new file mode 100644 index 000000000000..1351b5fdacac --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.c @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RRQ61XXX_EVB_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RRQ61XXX_EVB) + #include "bsp_pin_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED GPIO pins. + * @note In this board any GPIO can be used as an LED. For enabling an LED, a jumper wire must be connected + * between a GPIO and one of the pins of J611. Then, through the Pin Configurator of E2S, the + * BSP_GPIO_LED_ 'Symbolic Name' must be assigned to the corresponding GPIO. + */ +static const uint16_t g_bsp_prv_leds[] = +{ + #if defined(BSP_GPIO_LED_0) + (uint16_t) BSP_GPIO_LED_0, ///< LED0 + #endif + #if defined(BSP_GPIO_LED_1) + (uint16_t) BSP_GPIO_LED_1, ///< LED1 + #endif + #if defined(BSP_GPIO_LED_2) + (uint16_t) BSP_GPIO_LED_2, ///< LED2 + #endif + #if defined(BSP_GPIO_LED_3) + (uint16_t) BSP_GPIO_LED_3, ///< LED3 + #endif +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) FSP_ARRAY_LENGTH(g_bsp_prv_leds), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RRQ61XXX_EVB_LEDS) */ diff --git a/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.h b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.h new file mode 100644 index 000000000000..52b4653cd8ac --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/board/rrq61xxx_evb/board_leds.h @@ -0,0 +1,62 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RRQ61XXX_EVB + * @defgroup BOARD_RRQ61XXX_EVB_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the RRQ61XXX EVB. It includes info on the number of LEDs and which pins they are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED0 = 0, ///< LED0 + BSP_LED_LED1 = 1, ///< LED1 + BSP_LED_LED2 = 2, ///< LED2 + BSP_LED_LED3 = 3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of t + * his file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RRQ61XXX_EVB_LEDS) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/bsp_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/bsp_api.h new file mode 100644 index 000000000000..961ee4a3c8f8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/bsp_api.h @@ -0,0 +1,101 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "../../src/bsp/mcu/all/bsp_exceptions.h" +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + +/* BSP Common Includes. */ + #include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" + +/* Factory MCU information. */ + #include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + + #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") + #include "../../src/bsp/mcu/all/internal/bsp_internal.h" + #endif + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/fsp_common_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/fsp_common_api.h new file mode 100644 index 000000000000..7b0486c078b9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/fsp_common_api.h @@ -0,0 +1,384 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + FSP_ERR_HUK_ZEROIZATION = 505, ///< W-HUK zeroization is in progress + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + FSP_ERR_CRYPTO_SCE_PASS_1 = 0x10016, // Private SCE return code + FSP_ERR_CRYPTO_SCE_PASS_2 = 0x10017, // Private SCE return code + + FSP_ERR_CRYPTO_SCE_LBIST_CHECK_BUSY = 0x100ff, ///< LBIST Check BUSY + + /* Start of Crypto RSIP specific (0x10100) */ + FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy + FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return + FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal + FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed + FSP_ERR_CRYPTO_RSIP_DLMS_ERROR = 0x10105, ///< An error occurred during DLMS processing + + FSP_ERR_CRYPTO_RSIP_LBIST_CHECK_BUSY = 0x101ff, ///< LBIST Check BUSY + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_adc_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_adc_api.h new file mode 100644 index 000000000000..ac4b96ee7f91 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_adc_api.h @@ -0,0 +1,381 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ADC_API_H +#define R_ADC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_ANALOG_INTERFACES + * @defgroup ADC_API ADC Interface + * @brief Interface for A/D Converters. + * + * @section ADC_API_SUMMARY Summary + * The ADC interface provides standard ADC functionality including one-shot mode (single scan), continuous scan and + * group scan. It also allows configuration of hardware and software triggers for starting scans. After each conversion + * an interrupt can be triggered, and if a callback function is provided, the call back is invoked with the + * appropriate event information. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#ifndef BSP_OVERRIDE_ADC_INCLUDE + #include "r_elc_api.h" +#endif +#include "r_transfer_api.h" + +#if __has_include("r_adc_device_types.h") + #include "r_adc_device_types.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ +#ifndef BSP_OVERRIDE_ADC_MODE_T + +/** ADC operation mode definitions */ +typedef enum e_adc_mode +{ + ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels + ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels + ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels +} adc_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_RESOLUTION_T + +/** ADC data resolution definitions */ +typedef enum e_adc_resolution +{ + ADC_RESOLUTION_12_BIT = 0, ///< 12 bit resolution + ADC_RESOLUTION_10_BIT = 1, ///< 10 bit resolution + ADC_RESOLUTION_8_BIT = 2, ///< 8 bit resolution + ADC_RESOLUTION_14_BIT = 3, ///< 14 bit resolution + ADC_RESOLUTION_16_BIT = 4, ///< 16 bit resolution + ADC_RESOLUTION_24_BIT = 5, ///< 24 bit resolution +} adc_resolution_t; +#endif + +/** ADC data alignment definitions */ +typedef enum e_adc_alignment +{ + ADC_ALIGNMENT_RIGHT = 0, ///< Data alignment right + ADC_ALIGNMENT_LEFT = 1 ///< Data alignment left +} adc_alignment_t; + +#ifndef BSP_OVERRIDE_ADC_TRIGGER_T + +/** ADC trigger mode definitions */ +typedef enum e_adc_trigger +{ + ADC_TRIGGER_SOFTWARE = 0, ///< Software trigger; not for group modes + ADC_TRIGGER_SYNC_ELC = 2, ///< Synchronous trigger via ELC + ADC_TRIGGER_ASYNC_EXTERNAL = 3, ///< External asynchronous trigger; not for group modes +} adc_trigger_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_EVENT_T + +/** ADC callback event definitions */ +typedef enum e_adc_event +{ + ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_C, ///< Group C scan complete + ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete + ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete + ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested + ADC_EVENT_CONVERSION_ERROR, ///< Scan error + ADC_EVENT_OVERFLOW, ///< Overflow occurred + ADC_EVENT_LIMIT_CLIP, ///< Limiter clipping occurred + ADC_EVENT_FIFO_READ_REQUEST, ///< FIFO read requested + ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred + ADC_EVENT_WINDOW_COMPARE_A, ///< Window A comparison condition met + ADC_EVENT_WINDOW_COMPARE_B, ///< Window B comparison condition met + ADC_EVENT_ZERO_CROSS_DETECTION, ///< Zero-cross detection interrupt + ADC_EVENT_CAPTURE_A, ///< Capture A conversion complete + ADC_EVENT_CAPTURE_B, ///< Capture B conversion complete +} adc_event_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_CHANNEL_T + +/** ADC channels */ +typedef enum e_adc_channel +{ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + ADC_CHANNEL_23 = 23, ///< ADC channel 23 + ADC_CHANNEL_24 = 24, ///< ADC channel 24 + ADC_CHANNEL_25 = 25, ///< ADC channel 25 + ADC_CHANNEL_26 = 26, ///< ADC channel 26 + ADC_CHANNEL_27 = 27, ///< ADC channel 27 + ADC_CHANNEL_28 = 28, ///< ADC channel 28 + ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A + ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B + ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register + ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output + ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage +} adc_channel_t; + +#endif + +typedef enum e_adc_group_id +{ + ADC_GROUP_ID_0 = 0, ///< Group ID 0 + ADC_GROUP_ID_1 = 1, ///< Group ID 1 + ADC_GROUP_ID_2 = 2, ///< Group ID 2 + ADC_GROUP_ID_3 = 3, ///< Group ID 3 + ADC_GROUP_ID_4 = 4, ///< Group ID 4 + ADC_GROUP_ID_5 = 5, ///< Group ID 5 + ADC_GROUP_ID_6 = 6, ///< Group ID 6 + ADC_GROUP_ID_7 = 7, ///< Group ID 7 + ADC_GROUP_ID_8 = 8, ///< Group ID 8 +} adc_group_id_t; + +typedef enum e_adc_group_mask +{ + ADC_GROUP_MASK_NONE = 0x000, ///< Group Mask Unknown or None + ADC_GROUP_MASK_0 = 0x001, ///< Group Mask 0 + ADC_GROUP_MASK_1 = 0x002, ///< Group Mask 1 + ADC_GROUP_MASK_2 = 0x004, ///< Group Mask 2 + ADC_GROUP_MASK_3 = 0x008, ///< Group Mask 3 + ADC_GROUP_MASK_4 = 0x010, ///< Group Mask 4 + ADC_GROUP_MASK_5 = 0x020, ///< Group Mask 5 + ADC_GROUP_MASK_6 = 0x040, ///< Group Mask 6 + ADC_GROUP_MASK_7 = 0x080, ///< Group Mask 7 + ADC_GROUP_MASK_8 = 0x100, ///< Group Mask 8 + ADC_GROUP_MASK_ALL = 0x1FF, ///< All Groups +} adc_group_mask_t; + +/** ADC states. */ +typedef enum e_adc_state +{ + ADC_STATE_IDLE = 0, ///< ADC is idle + ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress + ADC_STATE_CALIBRATION_IN_PROGRESS = 2, ///< ADC calibration in progress - Not used by all ADC instances +} adc_state_t; + +/** ADC status. */ +typedef struct st_adc_status +{ + adc_state_t state; ///< Current state +} adc_status_t; + +/** ADC callback arguments definitions */ +typedef struct st_adc_callback_args +{ + uint16_t unit; ///< ADC device in use + adc_event_t event; ///< ADC callback event + void * p_context; ///< Placeholder for user data + adc_channel_t channel; ///< Channel of conversion result + uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b and r_sdadc_b + adc_group_mask_t group_mask; ///< Group Mask +} adc_callback_args_t; + +#ifndef BSP_OVERRIDE_ADC_INFO_T + +/** ADC Information Structure for Transfer Interface */ +typedef struct st_adc_info +{ + __I void * p_address; ///< The address to start reading the data from + uint32_t length; ///< The total number of transfers to read + + transfer_size_t transfer_size; ///< The size of each transfer + elc_peripheral_t elc_peripheral; ///< Name of the peripheral in the ELC list + elc_event_t elc_event; ///< Name of the ELC event for the peripheral + uint32_t calibration_data; ///< Temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + uint16_t room_calibration_data; ///< Room temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + uint16_t low_calibration_data; ///< Low temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + int16_t slope_microvolts; ///< Temperature sensor slope in microvolts/degrees C +} adc_info_t; + +#endif + +/** ADC general configuration */ +typedef struct st_adc_cfg +{ + uint16_t unit; ///< ADC unit to be used + adc_mode_t mode; ///< ADC operation mode + adc_resolution_t resolution; ///< ADC resolution + adc_alignment_t alignment; ///< Specify left or right alignment; ignored if addition used + adc_trigger_t trigger; ///< Default and Group A trigger source + IRQn_Type scan_end_irq; ///< Scan end IRQ number + IRQn_Type scan_end_b_irq; ///< Scan end group B IRQ number + IRQn_Type scan_end_c_irq; ///< Scan end group C IRQ number + uint8_t scan_end_ipl; ///< Scan end interrupt priority + uint8_t scan_end_b_ipl; ///< Scan end group B interrupt priority + uint8_t scan_end_c_ipl; ///< Scan end group C interrupt priority + void (* p_callback)(adc_callback_args_t * p_args); ///< Callback function; set to NULL for none + void * p_context; ///< Placeholder for user data. Passed to the user callback in @ref adc_callback_args_t. + void const * p_extend; ///< Extension parameter for hardware specific settings +} adc_cfg_t; + +/** ADC control block. Allocate using driver instance control structure from driver instance header file. */ +typedef void adc_ctrl_t; + +/** ADC functions implemented at the HAL layer will follow this API. */ +typedef struct st_adc_api +{ + /** Initialize ADC Unit; apply power, set the operational mode, trigger sources, interrupt priority, + * and configurations common to all channels and sensors. + * + * @pre Configure peripheral clocks, ADC pins and IRQs prior to calling this function. + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_cfg Pointer to configuration structure + */ + fsp_err_t (* open)(adc_ctrl_t * const p_ctrl, adc_cfg_t const * const p_cfg); + + /** Configure the scan including the channels, groups, and scan triggers to be used for the unit that + * was initialized in the open call. Some configurations are not supported for all implementations. + * See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_extend See implementation for details + */ + fsp_err_t (* scanCfg)(adc_ctrl_t * const p_ctrl, void const * const p_extend); + + /** Start the scan (in case of a software trigger), or enable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* scanStart)(adc_ctrl_t * const p_ctrl); + + /** Start the scan group (in case of a software trigger), or enable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] group_mask Mask of groups to start + */ + fsp_err_t (* scanGroupStart)(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask); + + /** Stop the ADC scan (in case of a software trigger), or disable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* scanStop)(adc_ctrl_t * const p_ctrl); + + /** Check scan status. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_status Pointer to store current status in + */ + fsp_err_t (* scanStatusGet)(adc_ctrl_t * const p_ctrl, adc_status_t * p_status); + + /** Read ADC conversion result. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] p_data Pointer to variable to load value into. + */ + fsp_err_t (* read)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); + + /** Read ADC conversion result into a 32-bit word. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] p_data Pointer to variable to load value into. + */ + fsp_err_t (* read32)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); + + /** Calibrate ADC or associated PGA (programmable gain amplifier). The driver may require implementation specific + * arguments to the p_extend input. Not supported for all implementations. See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_extend Pointer to implementation specific arguments + */ + fsp_err_t (* calibrate)(adc_ctrl_t * const p_ctrl, void const * p_extend); + + /** Set offset for input PGA configured for differential input. Not supported for all implementations. + * See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] offset See implementation for details. + */ + fsp_err_t (* offsetSet)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the ADC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(adc_ctrl_t * const p_ctrl, void (* p_callback)(adc_callback_args_t *), + void * const p_context, adc_callback_args_t * const p_callback_memory); + + /** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the + * specified A/D unit. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* close)(adc_ctrl_t * const p_ctrl); + + /** Return the ADC data register address of the first (lowest number) channel and the total number of bytes + * to be read in order for the DTC/DMAC to read the conversion results of all configured channels. + * Return the temperature sensor calibration and slope data. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_adc_info Pointer to ADC information structure + */ + fsp_err_t (* infoGet)(adc_ctrl_t * const p_ctrl, adc_info_t * const p_adc_info); +} adc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_adc_instance +{ + adc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + adc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + void const * p_channel_cfg; ///< Pointer to the channel configuration structure for this instance + adc_api_t const * p_api; ///< Pointer to the API structure for this instance +} adc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup ADC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_external_irq_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_external_irq_api.h new file mode 100644 index 000000000000..f8f9bafaeb1d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_external_irq_api.h @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INPUT_INTERFACES + * @defgroup EXTERNAL_IRQ_API External IRQ Interface + * @brief Interface for detecting external interrupts. + * + * @section EXTERNAL_IRQ_API_Summary Summary + * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an + * external IRQ pin. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_EXTERNAL_IRQ_API_H +#define R_EXTERNAL_IRQ_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Callback function parameter data */ +typedef struct st_external_irq_callback_args +{ + /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */ + void * p_context; + uint32_t channel; ///< The physical hardware channel that caused the interrupt. +} external_irq_callback_args_t; + +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_TRIGGER_T + +/** Condition that will trigger an interrupt when detected. */ +typedef enum e_external_irq_trigger +{ + EXTERNAL_IRQ_TRIGGER_FALLING = 0, ///< Falling edge trigger + EXTERNAL_IRQ_TRIGGER_RISING = 1, ///< Rising edge trigger + EXTERNAL_IRQ_TRIGGER_BOTH_EDGE = 2, ///< Both edges trigger + EXTERNAL_IRQ_TRIGGER_LEVEL_LOW = 3, ///< Low level trigger + EXTERNAL_IRQ_TRIGGER_LEVEL_HIGH = 4, ///< High level trigger + EXTERNAL_IRQ_TRIG_FALLING = EXTERNAL_IRQ_TRIGGER_FALLING, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_RISING = EXTERNAL_IRQ_TRIGGER_RISING, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_BOTH_EDGE = EXTERNAL_IRQ_TRIGGER_BOTH_EDGE, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_LEVEL_LOW = EXTERNAL_IRQ_TRIGGER_LEVEL_LOW, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_LEVEL_HIGH = EXTERNAL_IRQ_TRIGGER_LEVEL_HIGH ///< DEPRECATED, do not use +} external_irq_trigger_t; +#endif + +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_PCLK_DIV_T + +/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger + * conditions that are shorter than 3 periods of the filter clock. + */ +typedef enum e_external_irq_clock_source_div +{ + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1 = 0, ///< Filter using clock source divided by 1 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_8 = 1, ///< Filter using clock source divided by 8 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_32 = 2, ///< Filter using clock source divided by 32 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64 = 3, ///< Filter using clock source divided by 64 +} external_irq_clock_source_div_t; +#endif + +/** User configuration structure, used in open function */ +typedef struct st_external_irq_cfg +{ + uint8_t channel; ///< Hardware channel used. + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt number assigned to this instance + external_irq_trigger_t trigger; ///< Trigger setting. + external_irq_clock_source_div_t clock_source_div; ///< Digital filter clock divisor setting. + bool filter_enable; ///< Digital filter enable/disable selection. + + /** Callback provided external input trigger occurs. */ + void (* p_callback)(external_irq_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */ + void * p_context; + void const * p_extend; ///< External IRQ hardware dependent configuration. +} external_irq_cfg_t; + +/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. + */ +typedef void external_irq_ctrl_t; + +/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */ +typedef struct st_external_irq_api +{ + /** Initial configuration. + * + * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. + */ + fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); + + /** Enable callback when an external trigger condition occurs. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); + + /** Disable callback when external trigger condition occurs. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the External IRQ control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_ctrl, void (* p_callback)(external_irq_callback_args_t *), + void * const p_context, external_irq_callback_args_t * const p_callback_memory); + + /** Allow driver to be reconfigured. May reduce power consumption. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl); +} external_irq_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_external_irq_instance +{ + external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance +} external_irq_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end defgroup EXTERNAL_IRQ_API) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_i2c_master_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_i2c_master_api.h new file mode 100644 index 000000000000..60057e2e1d75 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_i2c_master_api.h @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_I2C_MASTER_API_H +#define R_I2C_MASTER_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup I2C_MASTER_API I2C Master Interface + * @brief Interface for I2C master communication. + * + * @section I2C_MASTER_API_SUMMARY Summary + * The I2C master interface provides a common API for I2C HAL drivers. The I2C master interface supports: + * - Interrupt driven transmit/receive processing + * - Callback function support which can return an event code + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Communication speed options */ +typedef enum e_i2c_master_rate +{ + I2C_MASTER_RATE_STANDARD = 100000, ///< 100 kHz + I2C_MASTER_RATE_FAST = 400000, ///< 400 kHz + I2C_MASTER_RATE_FASTPLUS = 1000000, ///< 1 MHz + I2C_MASTER_RATE_HIGHSPEED = 3400000 ///< 3.4 MHz +} i2c_master_rate_t; + +/** Addressing mode options */ +typedef enum e_i2c_master_addr_mode +{ + I2C_MASTER_ADDR_MODE_7BIT = 1, ///< Use 7-bit addressing mode + I2C_MASTER_ADDR_MODE_10BIT = 2, ///< Use 10-bit addressing mode +} i2c_master_addr_mode_t; + +/** Callback events */ +typedef enum e_i2c_master_event +{ + I2C_MASTER_EVENT_ABORTED = 1, ///< A transfer was aborted + I2C_MASTER_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully + I2C_MASTER_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully + I2C_MASTER_EVENT_START = 4, ///< I2C sent a start condition + I2C_MASTER_EVENT_BYTE_ACK = 5, ///< I2C finished sending/receiving 1 data byte +} i2c_master_event_t; + +/** I2C callback parameter definition */ +typedef struct st_i2c_master_callback_args +{ + void * p_context; ///< Pointer to user-provided context + i2c_master_event_t event; ///< Event code +} i2c_master_callback_args_t; + +/** I2C status indicators */ +typedef struct st_i2c_master_status +{ + bool open; ///< True if driver is open +} i2c_master_status_t; + +/** I2C configuration block */ +typedef struct st_i2c_master_cfg +{ + /** Generic configuration */ + uint8_t channel; ///< Identifier recognizable by implementation + i2c_master_rate_t rate; ///< Device's maximum clock rate from enum i2c_rate_t + uint32_t slave; ///< The address of the slave device + i2c_master_addr_mode_t addr_mode; ///< Indicates how slave fields should be interpreted + uint8_t ipl; ///< Interrupt priority level. Same for RXI, TXI, TEI and ERI. + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type tei_irq; ///< Transmit end IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + + /** Transfer API support */ + transfer_instance_t const * p_transfer_tx; ///< Transfer instance for I2C transmit. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< Transfer instance for I2C receive. Set to NULL if unused. + + /** Parameters to control software behavior */ + void (* p_callback)(i2c_master_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< Pointer to the user-provided context + + /** Implementation-specific configuration */ + void const * p_extend; ///< Any configuration data needed by the hardware +} i2c_master_cfg_t; + +/** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. + */ +typedef void i2c_master_ctrl_t; + +/** Interface definition for I2C access as master */ +typedef struct st_i2c_master_api +{ + /** Opens the I2C Master driver and initializes the hardware. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(i2c_master_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); + + /** Performs a read operation on an I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] p_dest Pointer to the location to store read data. + * @param[in] bytes Number of bytes to read. + * @param[in] restart Specify if the restart condition should be issued after reading. + */ + fsp_err_t (* read)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes, + bool const restart); + + /** Performs a write operation on an I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] p_src Pointer to the location to get write data from. + * @param[in] bytes Number of bytes to write. + * @param[in] restart Specify if the restart condition should be issued after writing. + */ + fsp_err_t (* write)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes, + bool const restart); + + /** Performs a reset of the peripheral. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + */ + fsp_err_t (* abort)(i2c_master_ctrl_t * const p_ctrl); + + /** Sets address of the slave device without reconfiguring the bus. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] slave_address Address of the slave device. + * @param[in] address_mode Addressing mode. + */ + fsp_err_t (* slaveAddressSet)(i2c_master_ctrl_t * const p_ctrl, uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_ctrl, void (* p_callback)(i2c_master_callback_args_t *), + void * const p_context, i2c_master_callback_args_t * const p_callback_memory); + + /** Gets the status of the configured I2C device. + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[out] p_status Pointer to store current status. + */ + fsp_err_t (* statusGet)(i2c_master_ctrl_t * const p_ctrl, i2c_master_status_t * p_status); + + /** Closes the driver and releases the I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + */ + fsp_err_t (* close)(i2c_master_ctrl_t * const p_ctrl); +} i2c_master_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2c_master_instance +{ + i2c_master_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2c_master_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2c_master_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2c_master_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup I2C_MASTER_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_ioport_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_ioport_api.h new file mode 100644 index 000000000000..4a09f1006d80 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,192 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size +#endif + +/** Pin identifier and pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port. + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_rtc_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_rtc_api.h new file mode 100644 index 000000000000..32ccbc1547de --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_rtc_api.h @@ -0,0 +1,349 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RTC_API_H +#define R_RTC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TIMERS_INTERFACES + * @defgroup RTC_API RTC Interface + * @brief Interface for accessing the Realtime Clock. + * + * + * @section RTC_API_Summary Summary + * The RTC Interface is for configuring Real Time Clock (RTC) functionality including alarm, periodic notification and + * error adjustment. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Use of time structure, tm */ +#include + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_RTC_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_rtc_event +{ + RTC_EVENT_ALARM_IRQ, ///< Real Time Clock ALARM 0 IRQ + RTC_EVENT_ALARM1_IRQ, ///< Real Time Clock ALARM 1 IRQ + RTC_EVENT_PERIODIC_IRQ, ///< Real Time Clock PERIODIC IRQ +} rtc_event_t; +#endif + +/** RTC alarm channel */ +typedef enum e_rtc_alarm_channel +{ + RTC_ALARM_CHANNEL_0, + RTC_ALARM_CHANNEL_1, +} rtc_alarm_channel_t; + +/** Callback function parameter data */ +typedef struct st_rtc_callback_args +{ + rtc_event_t event; ///< The event can be used to identify what caused the callback (compare match or error). + void * p_context; ///< Placeholder for user data. +} rtc_callback_args_t; + +/** Clock source for the RTC block */ +typedef enum e_rtc_count_source +{ + RTC_CLOCK_SOURCE_SUBCLK = 0, ///< Sub-clock oscillator + RTC_CLOCK_SOURCE_LOCO = 1, ///< Low power On Chip Oscillator + RTC_CLOCK_SOURCE_MAINCLK = 2 ///< Main clock oscillator +} rtc_clock_source_t; + +/** RTC run state */ +typedef enum e_rtc_status +{ + RTC_STATUS_STOPPED = 0, ///< RTC counter is stopped + RTC_STATUS_RUNNING = 1 ///< RTC counter is running +} rtc_status_t; + +/** Time error adjustment settings */ +typedef enum e_rtc_error_adjustment +{ + RTC_ERROR_ADJUSTMENT_NONE = 0, ///< Adjustment is not performed + RTC_ERROR_ADJUSTMENT_ADD_PRESCALER = 1, ///< Adjustment is performed by the addition to the prescaler + RTC_ERROR_ADJUSTMENT_SUBTRACT_PRESCALER = 2, ///< Adjustment is performed by the subtraction from the prescaler +} rtc_error_adjustment_t; + +/** Time error adjustment mode settings */ +typedef enum e_rtc_error_adjustment_mode +{ + RTC_ERROR_ADJUSTMENT_MODE_MANUAL = 0, ///< Adjustment mode is set to manual + RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC = 1, ///< Adjustment mode is set to automatic +} rtc_error_adjustment_mode_t; + +/** Time error adjustment period settings */ +typedef enum e_rtc_error_adjustment_period +{ + RTC_ERROR_ADJUSTMENT_PERIOD_1_MINUTE = 0, ///< Adjustment period is set to every one minute + RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND = 1, ///< Adjustment period is set to every ten second + RTC_ERROR_ADJUSTMENT_PERIOD_NONE = 2, ///< Adjustment period not supported in manual mode + RTC_ERROR_ADJUSTMENT_PERIOD_20_SECOND = 3, ///< Adjustment period is set to every twenty seconds +} rtc_error_adjustment_period_t; + +/** Time error adjustment value configuration */ +typedef struct st_rtc_error_adjustment_cfg +{ + rtc_error_adjustment_mode_t adjustment_mode; ///< Automatic Adjustment Enable/Disable + rtc_error_adjustment_period_t adjustment_period; ///< Error Adjustment period + rtc_error_adjustment_t adjustment_type; ///< Time error adjustment setting + uint32_t adjustment_value; ///< Value of the prescaler for error adjustment +} rtc_error_adjustment_cfg_t; + +#ifndef BSP_OVERRIDE_RTC_PERIODIC_IRQ_SELECT_T + +/** Periodic Interrupt select */ +typedef enum e_rtc_periodic_irq_select +{ + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_256_SECOND = 6, ///< A periodic irq is generated every 1/256 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_128_SECOND = 7, ///< A periodic irq is generated every 1/128 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_64_SECOND = 8, ///< A periodic irq is generated every 1/64 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_32_SECOND = 9, ///< A periodic irq is generated every 1/32 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_16_SECOND = 10, ///< A periodic irq is generated every 1/16 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_8_SECOND = 11, ///< A periodic irq is generated every 1/8 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_4_SECOND = 12, ///< A periodic irq is generated every 1/4 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_2_SECOND = 13, ///< A periodic irq is generated every 1/2 second + RTC_PERIODIC_IRQ_SELECT_1_SECOND = 14, ///< A periodic irq is generated every 1 second + RTC_PERIODIC_IRQ_SELECT_2_SECOND = 15, ///< A periodic irq is generated every 2 seconds + RTC_PERIODIC_IRQ_SELECT_1_MINUTE = 16, ///< A periodic irq is generated every 1 minute + RTC_PERIODIC_IRQ_SELECT_1_HOUR = 17, ///< A periodic irq is generated every 1 hour + RTC_PERIODIC_IRQ_SELECT_1_DAY = 18, ///< A periodic irq is generated every 1 day + RTC_PERIODIC_IRQ_SELECT_1_MONTH = 19, ///< A periodic irq is generated every 1 month +} rtc_periodic_irq_select_t; +#endif + +#ifndef BSP_OVERRIDE_RTC_TIME_CAPTURE_SOURCE_T + +/** Time capture trigger source */ +typedef enum e_rtc_time_capture_source +{ + RTC_TIME_CAPTURE_SOURCE_DISABLED = 0, ///< Disable trigger + RTC_TIME_CAPTURE_SOURCE_PIN_RISING = 1, ///< Rising edge pin trigger + RTC_TIME_CAPTURE_SOURCE_PIN_FALLING = 2, ///< Falling edge pin trigger + RTC_TIME_CAPTURE_SOURCE_PIN_BOTH = 3, ///< Both edges pin trigger + RTC_TIME_CAPTURE_SOURCE_SOFTWARE = 4, ///< Software trigger + RTC_TIME_CAPTURE_SOURCE_ELC_EVENT = 5, ///< ELC event trigger +} rtc_time_capture_source_t; +#endif + +/** Time capture trigger mode */ +typedef enum e_rtc_time_capture_mode +{ + RTC_TIME_CAPTURE_MODE_CONTINUOUS = 0, ///< Continuous capturing to all capturing channels + RTC_TIME_CAPTURE_MODE_ONE_SHOT = 1, ///< Single capture to a particular channel +} rtc_time_capture_mode_t; + +/** Time capture noise filter control */ +typedef enum e_rtc_time_capture_noise_filter +{ + RTC_TIME_CAPTURE_NOISE_FILTER_OFF = 0, ///< Turn noise filter off + RTC_TIME_CAPTURE_NOISE_FILTER_ON = 2, ///< Turn noise filter on (count source) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_32 = 3, ///< Turn noise filter on (count source by divided by 32) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_4096 = 4, ///< Turn noise filter on (count source by divided by 4096) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_8192 = 5, ///< Turn noise filter on (count source by divided by 8192) +} rtc_time_capture_noise_filter_t; + +/** Date and time structure defined in C standard library */ +typedef struct tm rtc_time_t; + +#ifndef BSP_OVERRIDE_RTC_ALARM_TIME_T + +/** Alarm time setting structure */ +typedef struct st_rtc_alarm_time +{ + rtc_time_t time; ///< Time structure + bool sec_match; ///< Enable the alarm based on a match of the seconds field + bool min_match; ///< Enable the alarm based on a match of the minutes field + bool hour_match; ///< Enable the alarm based on a match of the hours field + bool mday_match; ///< Enable the alarm based on a match of the days field + bool mon_match; ///< Enable the alarm based on a match of the months field + bool year_match; ///< Enable the alarm based on a match of the years field + bool dayofweek_match; ///< Enable the alarm based on a match of the dayofweek field + bool sunday_match; ///< Enable the alarm on Sunday + bool monday_match; ///< Enable the alarm on Monday + bool tuesday_match; ///< Enable the alarm on Tuesday + bool wednesday_match; ///< Enable the alarm on Wednesday + bool thursday_match; ///< Enable the alarm on Thursday + bool friday_match; ///< Enable the alarm on Friday + bool saturday_match; ///< Enable the alarm on Saturday + rtc_alarm_channel_t channel; ///< Select alarm 0 or alarm 1 +} rtc_alarm_time_t; +#endif + +/** Time capture configuration structure */ +typedef struct st_rtc_time_capture +{ + rtc_time_t time; ///< Time structure + uint8_t channel; ///< Capture channel + rtc_time_capture_source_t source; ///< Trigger source + rtc_time_capture_noise_filter_t noise_filter; ///< Noise filter + rtc_time_capture_mode_t mode; ///< Capture mode +} rtc_time_capture_t; + +/** RTC Information Structure for information returned by infoGet() */ +typedef struct st_rtc_info +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + rtc_status_t status; ///< RTC run status +} rtc_info_t; + +/** User configuration structure, used in open function */ +typedef struct st_rtc_cfg +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + uint32_t freq_compare_value; ///< The frequency comparison value + rtc_error_adjustment_cfg_t const * const p_err_cfg; ///< Pointer to Error Adjustment configuration + uint8_t alarm_ipl; ///< Alarm interrupt priority + IRQn_Type alarm_irq; ///< Alarm interrupt vector + uint8_t periodic_ipl; ///< Periodic interrupt priority + IRQn_Type periodic_irq; ///< Periodic interrupt vector + uint8_t carry_ipl; ///< Carry interrupt priority + IRQn_Type carry_irq; ///< Carry interrupt vector + void (* p_callback)(rtc_callback_args_t * p_args); ///< Called from the ISR. + void * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< RTC hardware dependant configuration. +} rtc_cfg_t; + +/** RTC control block. Allocate an instance specific control block to pass into the RTC API calls. + */ +typedef void rtc_ctrl_t; + +/** RTC driver structure. General RTC functions implemented at the HAL layer follow this API. */ +typedef struct st_rtc_api +{ + /** Open the RTC driver. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_cfg Pointer to the configuration structure + */ + fsp_err_t (* open)(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); + + /** Close the RTC driver. + * + * @param[in] p_ctrl Pointer to RTC device handle. + */ + fsp_err_t (* close)(rtc_ctrl_t * const p_ctrl); + + /** Sets the RTC clock source. + * + * @param[in] p_ctrl Pointer to RTC device handle + */ + fsp_err_t (* clockSourceSet)(rtc_ctrl_t * const p_ctrl); + + /** Set the calendar time and start the calendar counter + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time Pointer to a time structure that contains the time to set + */ + fsp_err_t (* calendarTimeSet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Get the calendar time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time Pointer to a time structure that contains the time to get + */ + fsp_err_t (* calendarTimeGet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Set the calendar alarm time and enable the alarm interrupt. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_alarm Pointer to an alarm structure that contains the alarm time to set + */ + fsp_err_t (* calendarAlarmSet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Get the calendar alarm time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_alarm Pointer to an alarm structure to fill up with the alarm time + */ + fsp_err_t (* calendarAlarmGet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Set the periodic irq rate + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] rate Rate of periodic interrupts + */ + fsp_err_t (* periodicIrqRateSet)(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); + + /** Set time error adjustment. + * + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] err_adj_cfg Pointer to the Error Adjustment Config + */ + fsp_err_t (* errorAdjustmentSet)(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the RTC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated + */ + fsp_err_t (* callbackSet)(rtc_ctrl_t * const p_ctrl, void (* p_callback)(rtc_callback_args_t *), + void * const p_context, rtc_callback_args_t * const p_callback_memory); + + /** Return the currently configure clock source for the RTC + * + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_rtc_info Pointer to RTC information structure + */ + fsp_err_t (* infoGet)(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); + + /** Config Time capture + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time_capture Pointer to a time capture structure that contains the configuration + */ + fsp_err_t (* timeCaptureSet)(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); + + /** Get the capture time and clear bit status. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time_capture Pointer to a time capture structure to fill up with the time capture + */ + fsp_err_t (* timeCaptureGet)(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); +} rtc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_rtc_instance +{ + rtc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + rtc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + rtc_api_t const * p_api; ///< Pointer to the API structure for this instance +} rtc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup RTC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_api.h new file mode 100644 index 000000000000..41ded18f9026 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_api.h @@ -0,0 +1,269 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SPI_API_H +#define R_SPI_API_H + +/*****************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup SPI_API SPI Interface + * @brief Interface for SPI communications. + * + * @section SPI_API_SUMMARY Summary + * Provides a common interface for communication using the SPI Protocol. + * + * + * @{ + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Includes + ********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + ********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_SPI_BIT_WIDTH_T + +/** Data bit width */ +typedef enum e_spi_bit_width +{ + SPI_BIT_WIDTH_4_BITS = (3), ///< Data bit width is 4 bits + SPI_BIT_WIDTH_5_BITS = (4), ///< Data bit width is 5 bits + SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits + SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits + SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits + SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits + SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits + SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits + SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits + SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits + SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits + SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits + SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits + SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits + SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits + SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits + SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits + SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits + SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits + SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits + SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits + SPI_BIT_WIDTH_25_BITS = (24), ///< Data bit width is 25 bits + SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits + SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits + SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits + SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits + SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits + SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits + SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits +} spi_bit_width_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_MODE_T + +/** Master or slave operating mode */ +typedef enum e_spi_mode +{ + SPI_MODE_MASTER, ///< Channel operates as SPI master + SPI_MODE_SLAVE ///< Channel operates as SPI slave +} spi_mode_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_PHASE_T + +/** Clock phase */ +typedef enum e_spi_clk_phase +{ + SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge + SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge +} spi_clk_phase_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_POLARITY_T + +/** Clock polarity */ +typedef enum e_spi_clk_polarity +{ + SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle + SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle +} spi_clk_polarity_t; +#endif + +/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be + * controlled by the master. This usually happens when the connecting device is also acting as master. + * A similar situation can also happen when configured as a slave. */ +typedef enum e_spi_mode_fault +{ + SPI_MODE_FAULT_ERROR_ENABLE, ///< Mode fault error flag on + SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off +} spi_mode_fault_t; + +#ifndef BSP_OVERRIDE_SPI_BIT_ORDER_T + +/** Bit order */ +typedef enum e_spi_bit_order +{ + SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission + SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission +} spi_bit_order_t; +#endif + +/** SPI events */ +typedef enum e_spi_event +{ + SPI_EVENT_TRANSFER_COMPLETE = 1, ///< The data transfer was completed + SPI_EVENT_TRANSFER_ABORTED, ///< The data transfer was aborted + SPI_EVENT_ERR_MODE_FAULT, ///< Mode fault error + SPI_EVENT_ERR_READ_OVERFLOW, ///< Read overflow error + SPI_EVENT_ERR_PARITY, ///< Parity error + SPI_EVENT_ERR_OVERRUN, ///< Overrun error + SPI_EVENT_ERR_FRAMING, ///< Framing error + SPI_EVENT_ERR_MODE_UNDERRUN ///< Underrun error +} spi_event_t; + +/** Common callback parameter definition */ +typedef struct st_spi_callback_args +{ + uint32_t channel; ///< Device channel number + spi_event_t event; ///< Event code + void * p_context; ///< Context provided to user during callback +} spi_callback_args_t; + +/** Non-secure arguments for write-read guard function */ +typedef struct st_spi_write_read_guard_args +{ + void const * p_src; + void * p_dest; + uint32_t const length; + spi_bit_width_t const bit_width; +} spi_write_read_guard_args_t; + +/** SPI interface configuration */ +typedef struct st_spi_cfg +{ + uint8_t channel; ///< Channel number to be used + + IRQn_Type rxi_irq; ///< Receive Buffer Full IRQ number + IRQn_Type txi_irq; ///< Transmit Buffer Empty IRQ number + IRQn_Type tei_irq; ///< Transfer Complete IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t rxi_ipl; ///< Receive Interrupt priority + uint8_t txi_ipl; ///< Transmit Interrupt priority + uint8_t tei_ipl; ///< Transfer Complete Interrupt priority + uint8_t eri_ipl; ///< Error Interrupt priority + spi_mode_t operating_mode; ///< Select master or slave operating mode + spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge + spi_clk_polarity_t clk_polarity; ///< Clock level when idle + spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag + spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first + transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMAC write transfer, link a transfer instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMAC read transfer, link a transfer instance here. Set to NULL if unused. + void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function + void * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extended SPI hardware dependent configuration +} spi_cfg_t; + +/** SPI control block. Allocate an instance specific control block to pass into the SPI API calls. + */ +typedef void spi_ctrl_t; + +/** Shared Interface definition for SPI */ +typedef struct st_spi_api +{ + /** Initialize a channel for SPI communication mode. + * + * @param[in, out] p_ctrl Pointer to user-provided storage for the control block. + * @param[in] p_cfg Pointer to SPI configuration structure. + */ + fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg); + + /** Receive data from a SPI device. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Transmit data to a SPI device. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex). + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the SPI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_ctrl, void (* p_callback)(spi_callback_args_t *), + void * const p_context, spi_callback_args_t * const p_callback_memory); + + /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + */ + fsp_err_t (* close)(spi_ctrl_t * const p_ctrl); +} spi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_instance +{ + spi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*****************************************************************************************************************//** + * @} (end defgroup SPI_API) + ********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_flash_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_flash_api.h new file mode 100644 index 000000000000..d0abd2f0b2c0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_spi_flash_api.h @@ -0,0 +1,342 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_STORAGE_INTERFACES + * @defgroup SPI_FLASH_API SPI Flash Interface + * @brief Interface for accessing external SPI flash devices. + * + * @section SPI_FLASH_API_SUMMARY Summary + * The SPI flash API provides an interface that configures, writes, and erases sectors in SPI flash devices. + * @{ + **********************************************************************************************************************/ + +#ifndef R_SPI_FLASH_API_H +#define R_SPI_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SPI_FLASH_ERASE_SIZE_CHIP_ERASE (UINT32_MAX) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Read mode. */ +typedef enum e_spi_flash_read_mode +{ + SPI_FLASH_READ_MODE_STANDARD = 0, ///< Standard Read Mode (no dummy cycles) + SPI_FLASH_READ_MODE_FAST_READ = 1, ///< Fast Read Mode (dummy cycles between address and data) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_OUTPUT = 2, ///< Fast Read Dual Output Mode (data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_IO = 3, ///< Fast Read Dual I/O Mode (address and data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_OUTPUT = 4, ///< Fast Read Quad Output Mode (data on 4 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO = 5, ///< Fast Read Quad I/O Mode (address and data on 4 lines) +} spi_flash_read_mode_t; + +/** SPI protocol. */ +typedef enum e_spi_flash_protocol +{ + /** Extended SPI mode (commands on 1 line) */ + SPI_FLASH_PROTOCOL_EXTENDED_SPI = 0x000, + + /** QPI mode (commands on 4 lines). Note that the application must ensure the device is in QPI mode. */ + SPI_FLASH_PROTOCOL_QPI = 0x002, + + /** SOPI mode (command and data on 8 lines). Note that the application must ensure the device is in SOPI mode. */ + SPI_FLASH_PROTOCOL_SOPI = 0x003, + + /** DOPI mode (command and data on 8 lines, dual data rate). Note that the application must ensure the device is in DOPI mode. */ + SPI_FLASH_PROTOCOL_DOPI = 0x004, + + /** 1S-1S-1S protocol mode */ + SPI_FLASH_PROTOCOL_1S_1S_1S = 0x000, + + /** 4S-4D-4D protocol mode */ + SPI_FLASH_PROTOCOL_4S_4D_4D = 0x3B2, + + /** 8D-8D-8D protocol mode */ + SPI_FLASH_PROTOCOL_8D_8D_8D = 0x3FF, + + /** 8D-8D-8S protocol mode */ + SPI_FLASH_PROTOCOL_8D_8D_8S = 0x2FF, + + /** 1S-2S-2S protocol mode */ + SPI_FLASH_PROTOCOL_1S_2S_2S = 0x048, + + /** 2S-2S-2S protocol mode */ + SPI_FLASH_PROTOCOL_2S_2S_2S = 0x049, + + /** 1S-1S-4S protocol mode */ + SPI_FLASH_PROTOCOL_1S_1S_4S = 0x080, + + /** 1S-4S-4S protocol mode */ + SPI_FLASH_PROTOCOL_1S_4S_4S = 0x090, + + /** 4S-4S-4S protocol mode */ + SPI_FLASH_PROTOCOL_4S_4S_4S = 0x092 +} spi_flash_protocol_t; + +#ifndef BSP_OVERRIDE_SPI_FLASH_ADDRESS_BYTES_T + +/** Number of bytes in the address. */ +typedef enum e_spi_flash_address_bytes +{ + SPI_FLASH_ADDRESS_BYTES_1 = 0, ///< 1-byte address phase + SPI_FLASH_ADDRESS_BYTES_2 = 1, ///< 2-byte address phase + SPI_FLASH_ADDRESS_BYTES_3 = 2, ///< 3-byte address phase + SPI_FLASH_ADDRESS_BYTES_4 = 3, ///< 4-byte address phase + + /** 4 address bytes using standard 4-byte command set. */ + SPI_FLASH_ADDRESS_BYTES_4_4BYTE_READ_CODE = 0x13, +} spi_flash_address_bytes_t; +#endif + +/** Number of data lines used. */ +typedef enum e_spi_flash_data_lines +{ + SPI_FLASH_DATA_LINES_1 = 0, ///< 1 data line + SPI_FLASH_DATA_LINES_2 = 1, ///< 2 data lines + SPI_FLASH_DATA_LINES_4 = 2, ///< 4 data lines +} spi_flash_data_lines_t; + +/** Number of dummy cycles for fast read operations. */ +typedef enum e_spi_flash_dummy_clocks +{ + SPI_FLASH_DUMMY_CLOCKS_0 = 0, ///< 0 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_1, ///< 1 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_2, ///< 2 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_3, ///< 3 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_4, ///< 4 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_5, ///< 5 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_6, ///< 6 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_7, ///< 7 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_8, ///< 8 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_9, ///< 9 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_10, ///< 10 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_11, ///< 11 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_12, ///< 12 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_13, ///< 13 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_14, ///< 14 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_15, ///< 15 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_16, ///< 16 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_17, ///< 17 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_18, ///< 18 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_19, ///< 19 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_20, ///< 20 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_21, ///< 21 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_22, ///< 22 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_23, ///< 23 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_24, ///< 24 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_25, ///< 25 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_26, ///< 26 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_27, ///< 27 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_28, ///< 28 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_29, ///< 29 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_30, ///< 30 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_31, ///< 31 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_DEFAULT = 0xFF, +} spi_flash_dummy_clocks_t; + +/** Direct Read and Write direction */ +typedef enum e_spi_flash_direct_transfer_dir_option +{ + SPI_FLASH_DIRECT_TRANSFER_DIR_READ = 0x0, + SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE = 0x1 +} spi_flash_direct_transfer_dir_t; + +/** Structure to define an erase command and associated erase size. */ +typedef struct st_spi_flash_erase_command +{ + uint16_t command; ///< Erase command + uint32_t size; ///< Size of erase for associated command, set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE for chip erase +} spi_flash_erase_command_t; + +/** Structure to define a direct transfer. */ +typedef struct st_spi_flash_direct_transfer +{ + union + { + uint64_t data_u64; ///< Data (64-bit) + uint32_t data; ///< Data + }; + uint32_t address; ///< Starting address + uint16_t command; ///< Transfer command + uint8_t dummy_cycles; ///< Number of dummy cycles + uint8_t command_length; ///< Command length + uint8_t address_length; ///< Address length + uint8_t data_length; ///< Data length +} spi_flash_direct_transfer_t; + +/** User configuration structure used by the open function */ +typedef struct st_spi_flash_cfg +{ + spi_flash_protocol_t spi_protocol; ///< Initial SPI protocol. SPI protocol can be changed in @ref spi_flash_api_t::spiProtocolSet. + spi_flash_read_mode_t read_mode; ///< Read mode + spi_flash_address_bytes_t address_bytes; ///< Number of bytes used to represent the address + spi_flash_dummy_clocks_t dummy_clocks; ///< Number of dummy clocks to use for fast read operations + + /** Number of lines used to send address for page program command. This should either be 1 or match the number of lines used in + * the selected read mode. */ + spi_flash_data_lines_t page_program_address_lines; + uint8_t write_status_bit; ///< Which bit determines write status + uint8_t write_enable_bit; ///< Which bit determines write status + uint32_t page_size_bytes; ///< Page size in bytes (maximum number of bytes for page program). Used to specify single continuous write size (bytes) in case of OSPI RAM. + uint8_t page_program_command; ///< Page program command + uint8_t write_enable_command; ///< Command to enable write or erase, typically 0x06 + uint8_t status_command; ///< Command to read the write status + uint8_t read_command; ///< Read command - OSPI SPI mode only + uint8_t xip_enter_command; ///< Command to enter XIP mode + uint8_t xip_exit_command; ///< Command to exit XIP mode + uint8_t erase_command_list_length; ///< Length of erase command list + spi_flash_erase_command_t const * p_erase_command_list; ///< List of all erase commands and associated sizes + void const * p_extend; ///< Pointer to implementation specific extended configurations +} spi_flash_cfg_t; + +/** SPI flash control block. Allocate an instance specific control block to pass into the SPI flash API calls. + */ +typedef void spi_flash_ctrl_t; + +/** Status. */ +typedef struct st_spi_flash_status +{ + /** Whether or not a write is in progress. This is determined by reading the @ref spi_flash_cfg_t::write_status_bit + * from the @ref spi_flash_cfg_t::status_command. */ + bool write_in_progress; +} spi_flash_status_t; + +/** SPI flash implementations follow this API. */ +typedef struct st_spi_flash_api +{ + /** Open the SPI flash driver module. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_cfg Pointer to a configuration structure + **/ + fsp_err_t (* open)(spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg); + + /** Write raw data to the SPI flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src Pointer to raw data to write, must include any required command/address + * @param[in] bytes Number of bytes to write + * @param[in] read_after_write If true, the slave select remains asserted and the peripheral does not return + * to direct communications mode. If false, the slave select is deasserted and + * memory mapped access is possible after this function returns if the device + * is not busy. + **/ + fsp_err_t (* directWrite)(spi_flash_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes, + bool const read_after_write); + + /** Read raw data from the SPI flash. Must follow a call to @ref spi_flash_api_t::directWrite. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_dest Pointer to read raw data into + * @param[in] bytes Number of bytes to read + **/ + fsp_err_t (* directRead)(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Direct Read/Write raw data to the SPI flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_data Pointer to command, address and data values and lengths + * @param[in] direction Direct Read/Write + **/ + fsp_err_t (* directTransfer)(spi_flash_ctrl_t * const p_ctrl, spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + + /** Change the SPI protocol in the driver. The application must change the SPI protocol on the device. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] spi_protocol Desired SPI protocol + **/ + fsp_err_t (* spiProtocolSet)(spi_flash_ctrl_t * const p_ctrl, spi_flash_protocol_t spi_protocol); + + /** Program a page of data to the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src The memory address of the data to write to the flash device + * @param[in] p_dest The location in the flash device address space to write the data to + * @param[in] byte_count The number of bytes to write + **/ + fsp_err_t (* write)(spi_flash_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint8_t * const p_dest, + uint32_t byte_count); + + /** Erase a certain number of bytes of the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_device_address The location in the flash device address space to start the erase from + * @param[in] byte_count The number of bytes to erase. Set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE to erase entire + * chip. + **/ + fsp_err_t (* erase)(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); + + /** Get the write or erase status of the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_status Current status of the SPI flash device stored here. + **/ + fsp_err_t (* statusGet)(spi_flash_ctrl_t * const p_ctrl, spi_flash_status_t * const p_status); + + /** Enter XIP mode. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipEnter)(spi_flash_ctrl_t * const p_ctrl); + + /** Exit XIP mode. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipExit)(spi_flash_ctrl_t * const p_ctrl); + + /** Select the bank to access. See implementation for details. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] bank The bank number + **/ + fsp_err_t (* bankSet)(spi_flash_ctrl_t * const p_ctrl, uint32_t bank); + + /** AutoCalibrate the SPI flash driver module. Expected to be used when auto-calibrating OSPI RAM device. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* autoCalibrate)(spi_flash_ctrl_t * const p_ctrl); + + /** Close the SPI flash driver module. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* close)(spi_flash_ctrl_t * const p_ctrl); +} spi_flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_flash_instance +{ + spi_flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_flash_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SPI_FLASH_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_timer_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_timer_api.h new file mode 100644 index 000000000000..53bb979498d3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_timer_api.h @@ -0,0 +1,329 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TIMER_API_H +#define R_TIMER_API_H + +/*******************************************************************************************************************//** + * @defgroup TIMER_API Timer Interface + * @ingroup RENESAS_TIMERS_INTERFACES + * @brief Interface for timer functions. + * + * @section TIMER_API_SUMMARY Summary + * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output, + * and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered. + * + * If an instance supports output compare mode, it is provided in the extension configuration + * timer_on__cfg_t defined in r_.h. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_TIMER_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_timer_event +{ + TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around + TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only) + TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A + TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B + TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only + TIMER_EVENT_COMPARE_A, ///< A compare has occurred on signal A + TIMER_EVENT_COMPARE_B, ///< A compare has occurred on signal B + TIMER_EVENT_COMPARE_C, ///< A compare has occurred on signal C + TIMER_EVENT_COMPARE_D, ///< A compare has occurred on signal D + TIMER_EVENT_COMPARE_E, ///< A compare has occurred on signal E + TIMER_EVENT_COMPARE_F, ///< A compare has occurred on signal F + TIMER_EVENT_DEAD_TIME ///< Dead time event +} timer_event_t; +#endif + +/** Timer variant types. */ +typedef enum e_timer_variant +{ + TIMER_VARIANT_32_BIT, ///< 32-bit timer + TIMER_VARIANT_16_BIT ///< 16-bit timer +} timer_variant_t; + +/** Options for storing compare match value */ +typedef enum e_timer_compare_match +{ + TIMER_COMPARE_MATCH_A = 0U, ///< Compare match A value + TIMER_COMPARE_MATCH_B = 1U, ///< Compare match B value + TIMER_COMPARE_MATCH_C = 2U, ///< Compare match C value + TIMER_COMPARE_MATCH_D = 3U, ///< Compare match D value + TIMER_COMPARE_MATCH_E = 4U, ///< Compare match E value + TIMER_COMPARE_MATCH_F = 5U, ///< Compare match F value + TIMER_COMPARE_MATCH_G = 6U, ///< Compare match G value + TIMER_COMPARE_MATCH_H = 7U, ///< Compare match H value +} timer_compare_match_t; + +#ifndef BSP_OVERRIDE_TIMER_CALLBACK_ARGS_T + +/** Callback function parameter data */ +typedef struct st_timer_callback_args +{ + /** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */ + void * p_context; + timer_event_t event; ///< The event can be used to identify what caused the callback. + + /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */ + uint32_t capture; +} timer_callback_args_t; + +#endif + +/** Timer control block. Allocate an instance specific control block to pass into the timer API calls. + */ +typedef void timer_ctrl_t; + +#ifndef BSP_OVERRIDE_TIMER_STATE_T + +/** Possible status values returned by @ref timer_api_t::statusGet. */ +typedef enum e_timer_state +{ + TIMER_STATE_STOPPED = 0, ///< Timer is stopped + TIMER_STATE_COUNTING = 1, ///< Timer is running + TIMER_STATE_UNKNOWN = 2 ///< Timer state could not be defined +} timer_state_t; + +#endif + +#ifndef BSP_OVERRIDE_TIMER_MODE_T + +/** Timer operational modes */ +typedef enum e_timer_mode +{ + TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses. + TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses. + TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output. + TIMER_MODE_ONE_SHOT_PULSE, ///< Saw-wave one-shot pulse mode (fixed buffer operation). + TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output. + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output. + + /** + * Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does + * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be + * set once and only need to be updated when the application needs to change the duty cycle. + */ + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U +} timer_mode_t; + +#endif + +/** Direction of timer count */ +typedef enum e_timer_direction +{ + TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up + TIMER_DIRECTION_UP = 1 ///< Timer count goes down +} timer_direction_t; + +#ifndef BSP_OVERRIDE_TIMER_SOURCE_DIV_T + +/** Clock source divisors */ +typedef enum e_timer_source_div +{ + TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 + TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2 + TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4 + TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8 + TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16 + TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32 + TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64 + TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128 + TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256 + TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512 + TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024 + TIMER_SOURCE_DIV_8192 = 13, ///< Timer clock source divided by 8192 +} timer_source_div_t; +#endif + +/** Timer information structure to store various information for a timer resource */ +typedef struct st_timer_info +{ + timer_direction_t count_direction; ///< Clock counting direction of the timer. + uint32_t clock_frequency; ///< Clock frequency of the timer counter. + + /** Period in raw timer counts. + * @note For triangle wave PWM modes, the full period is double this value. + */ + uint32_t period_counts; +} timer_info_t; + +#ifndef BSP_OVERRIDE_TIMER_STATUS_T + +/** Current timer status. */ +typedef struct st_timer_status +{ + uint32_t counter; ///< Current counter value + timer_state_t state; ///< Current timer state (running or stopped) +} timer_status_t; + +#endif + +/** User configuration structure, used in open function */ +typedef struct st_timer_cfg +{ + timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t + + /* Period in raw timer counts. + * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period. + */ + uint32_t period_counts; ///< Period in raw timer counts + timer_source_div_t source_div; ///< Source clock divider + uint32_t duty_cycle_counts; ///< Duty cycle in counts + + /** Select a channel corresponding to the channel number of the hardware. */ + uint8_t channel; + uint8_t cycle_end_ipl; ///< Cycle end interrupt priority + IRQn_Type cycle_end_irq; ///< Cycle end interrupt + + /** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(timer_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} timer_cfg_t; + +/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */ +typedef struct st_timer_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); + + /** Start the counter. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* start)(timer_ctrl_t * const p_ctrl); + + /** Stop the counter. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl); + + /** Reset the counter to the initial value. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl); + + /** Enables input capture. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl); + + /** Disables input capture. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl); + + /** Set the time until the timer expires. See implementation for details of period update timing. + * + * + * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in + * @ref timer_api_t::open. + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] period Time until timer should expire. + */ + fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period); + + /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is + * reflected after the next timer expiration. + * + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] duty_cycle_counts Time until duty cycle should expire. + * @param[in] pin Which output pin to update. See implementation for details. + */ + fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); + + /** Set a compare match value in raw counts. + * + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] compare_match_value Timer value to trigger a compare match event. + * @param[in] match_channel Which channel to update. + */ + fsp_err_t (* compareMatchSet)(timer_ctrl_t * const p_ctrl, uint32_t const compare_match_value, + timer_compare_match_t const match_channel); + + /** Stores timer information in p_info. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_info Collection of information for this timer. + */ + fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); + + /** Get the current counter value and timer state and store it in p_status. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_status Current status of this timer. + */ + fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(timer_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *), + void * const p_context, timer_callback_args_t * const p_callback_memory); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* close)(timer_ctrl_t * const p_ctrl); +} timer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_timer_instance +{ + timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + timer_api_t const * p_api; ///< Pointer to the API structure for this instance +} timer_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup TIMER_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_transfer_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_transfer_api.h new file mode 100644 index 000000000000..dc8622325dc9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TRANSFER_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3 ///< Each transfer transfers a 64-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + void * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *), + void * const p_context, transfer_callback_args_t * const p_callback_memory); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_uart_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_uart_api.h new file mode 100644 index 000000000000..e0d7e0160da2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_uart_api.h @@ -0,0 +1,266 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_ZERO = 1U, ///< Zero parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; +#endif + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[out] p_info Pointer to UART information structure. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), + void * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); + + /** Suspend RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveSuspend)(uart_ctrl_t * const p_ctrl); + + /** Resume RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveResume)(uart_ctrl_t * const p_ctrl); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_wdt_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_wdt_api.h new file mode 100644 index 000000000000..d2887e2bdb9c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/api/r_wdt_api.h @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_MONITORING_INTERFACES + * @defgroup WDT_API WDT Interface + * @brief Interface for watch dog timer functions. + * + * @section WDT_API_Summary Summary + * The WDT interface for the Watchdog Timer (WDT) peripheral provides watchdog functionality including resetting the + * device or generating an interrupt. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDT_API_H +#define R_WDT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_WDT_TIMEOUT_T + +/** WDT time-out periods. */ +typedef enum e_wdt_timeout +{ + WDT_TIMEOUT_128 = 0, ///< 128 clock cycles + WDT_TIMEOUT_512, ///< 512 clock cycles + WDT_TIMEOUT_1024, ///< 1024 clock cycles + WDT_TIMEOUT_2048, ///< 2048 clock cycles + WDT_TIMEOUT_4096, ///< 4096 clock cycles + WDT_TIMEOUT_8192, ///< 8192 clock cycles + WDT_TIMEOUT_16384, ///< 16384 clock cycles +} wdt_timeout_t; +#endif + +#ifndef BSP_OVERRIDE_WDT_CLOCK_DIVISION_T + +/** WDT clock division ratio. */ +typedef enum e_wdt_clock_division +{ + WDT_CLOCK_DIVISION_1 = 0, ///< CLK/1 + WDT_CLOCK_DIVISION_4 = 1, ///< CLK/4 + WDT_CLOCK_DIVISION_16 = 2, ///< CLK/16 + WDT_CLOCK_DIVISION_32 = 3, ///< CLK/32 + WDT_CLOCK_DIVISION_64 = 4, ///< CLK/64 + WDT_CLOCK_DIVISION_128 = 15, ///< CLK/128 + WDT_CLOCK_DIVISION_256 = 5, ///< CLK/256 + WDT_CLOCK_DIVISION_512 = 6, ///< CLK/512 + WDT_CLOCK_DIVISION_2048 = 7, ///< CLK/2048 + WDT_CLOCK_DIVISION_8192 = 8, ///< CLK/8192 +} wdt_clock_division_t; +#endif + +#ifndef BSP_OVERRIDE_WDT_WINDOW_START_END_T + +/** WDT refresh permitted period window start position. */ +typedef enum e_wdt_window_start +{ + WDT_WINDOW_START_25 = 0, ///< Start position = 25% + WDT_WINDOW_START_50 = 1, ///< Start position = 50% + WDT_WINDOW_START_75 = 2, ///< Start position = 75% + WDT_WINDOW_START_100 = 3, ///< Start position = 100% +} wdt_window_start_t; + +/** WDT refresh permitted period window end position. */ +typedef enum e_wdt_window_end +{ + WDT_WINDOW_END_75 = 0, ///< End position = 75% + WDT_WINDOW_END_50 = 1, ///< End position = 50% + WDT_WINDOW_END_25 = 2, ///< End position = 25% + WDT_WINDOW_END_0 = 3, ///< End position = 0% +} wdt_window_end_t; +#endif + +/** WDT Counter underflow and refresh error control. */ +typedef enum e_wdt_reset_control +{ + WDT_RESET_CONTROL_NMI = 0, ///< NMI/IRQ request when counter underflows. + WDT_RESET_CONTROL_RESET = 1, ///< Reset request when counter underflows. +} wdt_reset_control_t; + +/** WDT Counter operation in sleep mode. */ +typedef enum e_wdt_stop_control +{ + WDT_STOP_CONTROL_DISABLE = 0, ///< Count will not stop when device enters sleep mode. + WDT_STOP_CONTROL_ENABLE = 1, ///< Count will automatically stop when device enters sleep mode. +} wdt_stop_control_t; + +/** WDT status */ +typedef enum e_wdt_status +{ + WDT_STATUS_NO_ERROR = 0, ///< No status flags set. + WDT_STATUS_UNDERFLOW = 1, ///< Underflow flag set. + WDT_STATUS_REFRESH_ERROR = 2, ///< Refresh error flag set. Refresh outside of permitted window. + WDT_STATUS_UNDERFLOW_AND_REFRESH_ERROR = 3, ///< Underflow and refresh error flags set. + WDT_STATUS_OVERFLOW = 4, ///< Overflow flag set. +} wdt_status_t; + +/** Callback function parameter data */ +typedef struct st_wdt_callback_args +{ + void * p_context; ///< Placeholder for user data. Set in @ref wdt_api_t::open function in @ref wdt_cfg_t. +} wdt_callback_args_t; + +/** WDT timeout data. Used to return frequency of WDT clock and timeout period */ +typedef struct st_wdt_timeout_values +{ + uint32_t clock_frequency_hz; ///< Frequency of watchdog clock after divider. + uint32_t timeout_clocks; ///< Timeout period in units of watchdog clock ticks. +} wdt_timeout_values_t; + +/** WDT control block. Allocate an instance specific control block to pass into the WDT API calls. + */ +typedef void wdt_ctrl_t; + +/** WDT configuration parameters. */ +typedef struct st_wdt_cfg +{ + wdt_timeout_t timeout; ///< Timeout period. + wdt_clock_division_t clock_division; ///< Clock divider. + wdt_window_start_t window_start; ///< Refresh permitted window start position. + wdt_window_end_t window_end; ///< Refresh permitted window end position. + wdt_reset_control_t reset_control; ///< Select NMI/IRQ or reset generated on underflow. + wdt_stop_control_t stop_control; ///< Select whether counter operates in sleep mode. + void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT ISR occurs. + + /** Placeholder for user data. Passed to the user callback in wdt_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Placeholder for user extension. +} wdt_cfg_t; + +/** WDT functions implemented at the HAL layer will follow this API. */ +typedef struct st_wdt_api +{ + /** Initialize the WDT in register start mode. In auto-start mode (Supported devices only) with NMI output it + * registers the NMI callback. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + + /** Refresh the watchdog timer. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* refresh)(wdt_ctrl_t * const p_ctrl); + + /** Read the status of the WDT. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_status Pointer to variable to return status information through. + */ + fsp_err_t (* statusGet)(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + + /** Clear the status flags of the WDT. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] status Status condition(s) to clear. + */ + fsp_err_t (* statusClear)(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + + /** Read the current WDT counter value. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_count Pointer to variable to return current WDT counter value. + */ + fsp_err_t (* counterGet)(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + + /** Read the watchdog timeout values. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_timeout Pointer to structure to return timeout values. + */ + fsp_err_t (* timeoutGet)(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the WDT control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_ctrl, void (* p_callback)(wdt_callback_args_t *), + void * const p_context, wdt_callback_args_t * const p_callback_memory); +} wdt_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_wdt_instance +{ + wdt_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + wdt_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + wdt_api_t const * p_api; ///< Pointer to the API structure for this instance +} wdt_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup WDT_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_features.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_features.h new file mode 100644 index 000000000000..ce795c1a8cc3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_features.h @@ -0,0 +1,301 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6W1 || BSP_MCU_GROUP_RA6W3 || BSP_MCU_GROUP_RA6U1 + #include "../../fsp/src/bsp_w/mcu/all/bsp_compiler_support.h" +#else + #include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CFLASH = 0, ///< Code Flash + FSP_IP_DFLASH = 1, ///< Data Flash + FSP_IP_RAM = 2, ///< RAM + FSP_IP_LVD = 3, ///< Low Voltage Detection + FSP_IP_CGC = 3, ///< Clock Generation Circuit + FSP_IP_LPM = 3, ///< Low Power Modes + FSP_IP_FCU = 4, ///< Flash Control Unit + FSP_IP_ICU = 6, ///< Interrupt Control Unit + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_DTC = 8, ///< Data Transfer Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_PFS = 10, ///< Pin Function Select + FSP_IP_ELC = 11, ///< Event Link Controller + FSP_IP_MPU = 13, ///< Memory Protection Unit + FSP_IP_MSTP = 14, ///< Module Stop + FSP_IP_MMF = 15, ///< Memory Mirror Function + FSP_IP_KEY = 16, ///< Key Interrupt Function + FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit + FSP_IP_DOC = 18, ///< Data Operation Circuit + FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator + FSP_IP_SCI = 20, ///< Serial Communications Interface + FSP_IP_IIC = 21, ///< I2C Bus Interface + FSP_IP_SPI = 22, ///< Serial Peripheral Interface + FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit + FSP_IP_SCE = 24, ///< Secure Cryptographic Engine + FSP_IP_SLCDC = 25, ///< Segment LCD Controller + FSP_IP_AES = 26, ///< Advanced Encryption Standard + FSP_IP_TRNG = 27, ///< True Random Number Generator + FSP_IP_FCACHE = 30, ///< Flash Cache + FSP_IP_SRAM = 31, ///< SRAM + FSP_IP_ADC = 32, ///< A/D Converter + FSP_IP_DAC = 33, ///< 12-Bit D/A Converter + FSP_IP_TSN = 34, ///< Temperature Sensor + FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit + FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator + FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator + FSP_IP_OPAMP = 38, ///< Operational Amplifier + FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter + FSP_IP_RTC = 40, ///< Real Time Clock + FSP_IP_WDT = 41, ///< Watch Dog Timer + FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer + FSP_IP_GPT = 43, ///< General PWM Timer + FSP_IP_POEG = 44, ///< Port Output Enable for GPT + FSP_IP_OPS = 45, ///< Output Phase Switch + FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer + FSP_IP_CAN = 48, ///< Controller Area Network + FSP_IP_IRDA = 49, ///< Infrared Data Association + FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface + FSP_IP_USBFS = 51, ///< USB Full Speed + FSP_IP_SDHI = 52, ///< SD/MMC Host Interface + FSP_IP_SRC = 53, ///< Sampling Rate Converter + FSP_IP_SSI = 54, ///< Serial Sound Interface + FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface + FSP_IP_ETHER = 64, ///< Ethernet MAC Controller + FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller + FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller + FSP_IP_PDC = 66, ///< Parallel Data Capture Unit + FSP_IP_GLCDC = 67, ///< Graphics LCD Controller + FSP_IP_DRW = 68, ///< 2D Drawing Engine + FSP_IP_JPEG = 69, ///< JPEG + FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter + FSP_IP_USBHS = 71, ///< USB High Speed + FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface + FSP_IP_CEC = 73, ///< HDMI CEC + FSP_IP_TFU = 74, ///< Trigonometric Function Unit + FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator + FSP_IP_CANFD = 76, ///< CAN-FD + FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT + FSP_IP_SAU = 78, ///< Serial Array Unit + FSP_IP_IICA = 79, ///< Serial Interface IICA + FSP_IP_UARTA = 80, ///< Serial Interface UARTA + FSP_IP_TAU = 81, ///< Timer Array Unit + FSP_IP_TML = 82, ///< 32-bit Interval Timer + FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator + FSP_IP_USBCC = 84, ///< USB Type-C Controller +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH + FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH + FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END + FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B + FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A + FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B + FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ + FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ + FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A + FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B + FSP_SIGNAL_AGT_INT, ///< AGT INT + FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR + FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END + FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW + FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR + FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX + FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX + FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX + FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX + FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP + FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST + FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 + FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 + FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD + FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT + FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT + FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT + FSP_SIGNAL_CTSU_END = 0, ///< CTSU END + FSP_SIGNAL_CTSU_READ, ///< CTSU READ + FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE + FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI + FSP_SIGNAL_DALI_CLI, ///< DALI CLI + FSP_SIGNAL_DALI_SDI, ///< DALI SDI + FSP_SIGNAL_DALI_BPI, ///< DALI BPI + FSP_SIGNAL_DALI_FEI, ///< DALI FEI + FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI + FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT + FSP_SIGNAL_DOC_INT = 0, ///< DOC INT + FSP_SIGNAL_DRW_INT = 0, ///< DRW INT + FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE + FSP_SIGNAL_DTC_END, ///< DTC END + FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT + FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 + FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 + FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS + FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT + FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT + FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL + FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE + FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL + FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE + FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL + FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE + FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL + FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE + FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL + FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE + FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL + FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE + FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR + FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI + FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT + FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 + FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 + FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A + FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B + FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C + FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D + FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E + FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F + FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW + FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW + FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A + FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B + FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE + FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 + FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 + FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 + FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 + FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 + FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 + FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 + FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 + FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 + FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 + FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 + FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 + FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 + FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 + FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 + FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 + FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL + FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI + FSP_SIGNAL_IIC_RXI, ///< IIC RXI + FSP_SIGNAL_IIC_TEI, ///< IIC TEI + FSP_SIGNAL_IIC_TXI, ///< IIC TXI + FSP_SIGNAL_IIC_WUI, ///< IIC WUI + FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 + FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 + FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 + FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 + FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B + FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C + FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D + FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E + FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW + FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI + FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI + FSP_SIGNAL_KEY_INT = 0, ///< KEY INT + FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END + FSP_SIGNAL_PDC_INT, ///< PDC INT + FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY + FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT + FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT + FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM + FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD + FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY + FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY + FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY + FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG + FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY + FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 + FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 + FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK + FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY + FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 + FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 + FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 + FSP_SIGNAL_SCI_AM = 0, ///< SCI AM + FSP_SIGNAL_SCI_ERI, ///< SCI ERI + FSP_SIGNAL_SCI_RXI, ///< SCI RXI + FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI + FSP_SIGNAL_SCI_TEI, ///< SCI TEI + FSP_SIGNAL_SCI_TXI, ///< SCI TXI + FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI + FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND + FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND + FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS + FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD + FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ + FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO + FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI + FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE + FSP_SIGNAL_SPI_RXI, ///< SPI RXI + FSP_SIGNAL_SPI_TEI, ///< SPI TEI + FSP_SIGNAL_SPI_TXI, ///< SPI TXI + FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END + FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY + FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL + FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW + FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW + FSP_SIGNAL_SSI_INT = 0, ///< SSI INT + FSP_SIGNAL_SSI_RXI, ///< SSI RXI + FSP_SIGNAL_SSI_TXI, ///< SSI TXI + FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI + FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ + FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 + FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 + FSP_SIGNAL_USB_INT, ///< USB INT + FSP_SIGNAL_USB_RESUME, ///< USB RESUME + FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW + FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A + FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B + FSP_SIGNAL_ULPT_INT, ///< ULPT INT +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_version.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_version.h new file mode 100644 index 000000000000..a73413122b74 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fsp_version.h @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_VERSION_H + #define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ + #include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + + #ifdef __cplusplus +extern "C" { + #endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ + #define FSP_VERSION_MAJOR (2U) + +/** FSP pack minor version. */ + #define FSP_VERSION_MINOR (0U) + +/** FSP pack patch version. */ + #define FSP_VERSION_PATCH (1U) + +/** FSP pack version build number (currently unused). */ + #define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ + #define FSP_VERSION_STRING ("2.0.1") + +/** Unique FSP version ID. */ + #define FSP_VERSION_BUILD_STRING ("Built with RAFW Flexible Software Package version 2.0.1") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** + * Code version parameters, little endian order. + */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/fw_version.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fw_version.h new file mode 100644 index 000000000000..f285b88e82ca --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/fw_version.h @@ -0,0 +1,3 @@ +#ifndef FIRMWARE_VERSION +#define FIRMWARE_VERSION "9092f23dda-1" "-e2studio" +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_adc_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_adc_w.h new file mode 100644 index 000000000000..a073bf767e72 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_adc_w.h @@ -0,0 +1,183 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ADC_W_H +#define R_ADC_W_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include +#include + +#include "bsp_api.h" +#include "r_adc_api.h" +#include "r_adc_w_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup ADC_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ADC_CH0_DMAC_SRC_ADDR (&AUXADC->FIFO0_DMA_DATA_REG) + +/*********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +/** DMA enable */ +typedef enum e_adc_w_dma_enable +{ + ADC_W_DMA_DISABLED = 0, /**< DMA disabled */ + ADC_W_DMA_ENABLED = 1, /**< DMA enabled */ +} adc_w_dma_enable_t; + +/** ADC Interrupt Mode Threshold */ +typedef enum e_adc_w_thd_interrupt_mode +{ + ADC_W_INTERRUPT_THD_NONE = 0x000, /**< Threshold interrupt is disabled */ + ADC_W_INTERRUPT_THD_OVER = 0x001, /**< An interrupt occurs when the conversion result exceeds the threshold. */ + ADC_W_INTERRUPT_THD_UNDER = 0x010, /**< An interrupt occurs when the conversion result is below the threshold. */ + ADC_W_INTERRUPT_THD_DIFF = 0x100, +} adc_w_thd_interrupt_mode_t; + +/** ADC Interrupt Mode FIFO */ +typedef enum e_adc_w_fifo_interrupt_mode +{ + ADC_W_INTERRUPT_FIFO_NONE = 0x00, /**< FIFO interrupt is disabled */ + ADC_W_INTERRUPT_FIFO_HALF = 0x01, /**< An interrupt occurs when the FIFO is filled with four data. */ + ADC_W_INTERRUPT_FIFO_FULL = 0x10, +} adc_w_fifo_interrupt_mode_t; + +/** ADC Sensor Wakeup Mode enable */ +typedef enum e_adc_w_sensorwakeup_enable +{ + ADC_W_SENSOR_WAKEUP_DISABLED = 0, /**< sensor wakeup disabled */ + ADC_W_SENSOR_WAKEUP_ENABLED = 1, /**< sensor wakeup enabled */ +} adc_w_sensorwakeup_enable_t; + +/** Threshold mode selection for sensor wakeup mode */ +typedef enum e_adc_w_sensorwakeup_thd_mode +{ + ADC_W_SENSOR_WAKEUP_THD_OVER = 0, /**< Over threshold */ + ADC_W_SENSOR_WAKEUP_THD_UNDER = 1, /**< Under threshold */ +} adc_w_sensorwakeup_thd_mode_t; + +/** Timer count clock source for sensor wakeup mode (base = 32.768KHz) */ +typedef enum e_adc_w_timer_count_clock_source +{ + ADC_W_TIMER_COUNT_SOURCE_8 = 0, /**< 7.81-msec period */ + ADC_W_TIMER_COUNT_SOURCE_31, /**< 31.25-msec period */ + ADC_W_TIMER_COUNT_SOURCE_62, /**< 62.5-msec period */ + ADC_W_TIMER_COUNT_SOURCE_250, /**< 250-msec period */ + ADC_W_TIMER_COUNT_SOURCE_1000, /**< 1000-msec period */ + ADC_W_TIMER_COUNT_SOURCE_4000, /**< 4000-msec period */ + ADC_W_TIMER_COUNT_SOURCE_16000, /**< 16000-msec period */ + ADC_W_TIMER_COUNT_SOURCE_64000, /**< 64,000-msec period */ +} adc_w_timer_count_clock_source_t; + +/** Sample number for average in sensor wakeup mode */ +typedef enum e_adc_w_sample_average +{ + ADC_W_SAMPLE_AVERAGE_4 = 0, /**< 4-sample processing */ + ADC_W_SAMPLE_AVERAGE_8, /**< 8-sample processing */ + ADC_W_SAMPLE_AVERAGE_16, /**< 16-sample processing */ + ADC_W_SAMPLE_AVERAGE_32, /**< 32-sample processing */ + ADC_W_SAMPLE_AVERAGE_64, /**< 64-sample processing */ + ADC_W_SAMPLE_AVERAGE_128, /**< 128-sample processing */ + ADC_W_SAMPLE_AVERAGE_256, /**< 256-sample processing */ + ADC_W_SAMPLE_AVERAGE_512, /**< 512-sample processing */ +} adc_w_sample_average_t; + +/** ADC_W active channel configuration */ +typedef struct st_adc_w_scan_cfg +{ + uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 3 is ch3. +} adc_w_scan_cfg_t; + +/** ADC chennel config structure */ +typedef struct st_adc_w_channel_cfg +{ + adc_w_fifo_interrupt_mode_t interrupt_mode_fifo; ///< FIFO interrupt settings(four data/none) + adc_w_thd_interrupt_mode_t interrupt_mode_thd; ///< Threshold interrupt setting(none/over/under) + adc_w_dma_enable_t dma_en; ///< Enable/disable DMA support + adc_w_sensorwakeup_enable_t sensorwakeup_en; ///< Enable/disable sensor wakeup mode + uint16_t thd_value; ///< Threshold Level for the channel + adc_w_sensorwakeup_thd_mode_t threshold_mode; ///< Use threshold as upper or lower limit +} adc_w_channel_cfg_t; + +/** ADC extended configuration data */ +typedef struct st_adc_w_extended_cfg +{ + uint16_t conversion_clockdiv; ///< Divider for conversion clock (fAD) setting + uint16_t upper_bound_limit; ///< Setting upper limit conversion value + uint16_t lower_bound_limit; ///< Setting lower limit conversion value + adc_w_channel_cfg_t const * p_channel_cfgs[BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS]; ///< Configuration for each channel, set to NULL if unused + adc_w_timer_count_clock_source_t timer_count_clock_source; ///< Setting lower limit conversion value + uint16_t timer_value; ///< Timer count clock source for sensor wakeup mode (base = 32.768KHz) + adc_w_sample_average_t sample_average; ///< Sample number for average in sensor wakeup mode +} adc_w_extended_cfg_t; + +/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ +typedef struct st_adc_w_instance_ctrl +{ + adc_cfg_t const * p_cfg; ///< Boolean to verify that the Unit has been initialized + void (* p_callback)(adc_callback_args_t *); ///< Pointer to callback that is called when an adc_w_event_t occurs. + void * p_context; ///< User defined context passed into callback function. + uint32_t initialized; ///< Initialized status of ADC_W. + uint32_t opened; ///< Open status of ADC_W. + uint32_t scan_mask; ///< Scan mask of enabled channels. + uint32_t scan_cfg_mask; ///< Scan mask of configured channels. +} adc_w_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const adc_api_t g_adc_on_adc_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg); +fsp_err_t R_ADC_W_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_scan_cfg); +fsp_err_t R_ADC_W_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info); +fsp_err_t R_ADC_W_ScanStart(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_W_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask); +fsp_err_t R_ADC_W_ScanStop(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_W_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status); +fsp_err_t R_ADC_W_Read(adc_ctrl_t * p_ctrl, adc_channel_t const channel_id, uint16_t * const p_data); +fsp_err_t R_ADC_W_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const channel_id, uint32_t * const p_data); +fsp_err_t R_ADC_W_Close(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_W_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset); +fsp_err_t R_ADC_W_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend); +fsp_err_t R_ADC_W_CallbackSet(adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void * const p_context, + adc_callback_args_t * const p_callback_memory); + +fsp_err_t R_ADC_W_SensorWakeupcfg(adc_ctrl_t * const p_ctrl); +fsp_err_t R_ADC_W_FifoRead(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); + +/*******************************************************************************************************************//** + * @} (end defgroup ADC_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ext_irq_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ext_irq_w.h new file mode 100644 index 000000000000..1c66bb633f20 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ext_irq_w.h @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup EXT_IRQ_W + * @{ + **********************************************************************************************************************/ + +#ifndef R_EXT_IRQ_W_H +#define R_EXT_IRQ_W_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_external_irq_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Extended EXT_IRQ interface configuration */ +typedef struct st_ext_irq_w_extended_cfg +{ + bsp_io_port_pin_t irq_pin; ///< IRQ pin +} ext_irq_w_extended_cfg_t; + +/** EXT_IRQ private control block. DO NOT MODIFY. Initialization occurs when @ref R_EXT_IRQ_W_ExternalIrqOpen is called. */ +typedef struct st_ext_irq_w_instance_ctrl +{ + uint32_t open; ///< Used to determine if channel control block is in use + IRQn_Type irq; ///< NVIC interrupt number + uint8_t channel; ///< Channel + + bsp_io_port_pin_t irq_pin; ///< IRQ pin + + void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. + + /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ + void * p_context; +} ext_irq_w_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const external_irq_api_t g_external_irq_on_ext_irq_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg); + +fsp_err_t R_EXT_IRQ_W_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_EXT_IRQ_W_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_EXT_IRQ_W_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void * const p_context, + external_irq_callback_args_t * const p_callback_memory); + +fsp_err_t R_EXT_IRQ_W_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup EXT_IRQ_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_EXT_IRQ_W_H diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_gpio_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_gpio_w.h new file mode 100644 index 000000000000..5060250eda21 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_gpio_w.h @@ -0,0 +1,435 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup GPIO_W + * @{ + **********************************************************************************************************************/ + +#ifndef R_GPIO_W_H +#define R_GPIO_W_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ioport_api.h" +#include "r_gpio_w_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define GPIO_W_PXX_MODE_REG(_port, _pin) BSP_IO_PXX_MODE_REG(_port, _pin) + +#if !defined(BSP_MCU_GROUP_RA6W1) + #define GPIO_W_MODE_REG_VALID_BITS_MSK (0x3F3F3FU) + #define GPIO_W_PRV_FUNC_BITS (0x003FU) + +/* Macro for toggle action triggered by event with initial level */ + #define TOGGLE_GPIO_EVENTx_MASK(event, level) ((uint32_t) GPIO_W_CFG_PORT_DIRECTION_OUTPUT | \ + (uint32_t) GPIO_W_CFG_ELC_TASK_GPIO_TOGGLE | \ + (uint32_t) event | \ + (uint32_t) (level << GPIO_W_PRV_LEVEL_OFFSET)) + +/* Macro for set action triggered by event */ + #define SET_GPIO_EVENTx_MASK(event) ((uint32_t) GPIO_W_CFG_PORT_DIRECTION_OUTPUT | \ + (uint32_t) GPIO_W_CFG_ELC_TASK_GPIO_SET | \ + (uint32_t) event | \ + (uint32_t) GPIO_W_CFG_PORT_OUTPUT_LOW) + +/* Macro for reset action triggered by event */ + #define RESET_GPIO_EVENTx_MASK(event) ((uint32_t) GPIO_W_CFG_PORT_DIRECTION_OUTPUT | \ + (uint32_t) GPIO_W_CFG_ELC_TASK_GPIO_RESET | \ + (uint32_t) event | \ + (uint32_t) GPIO_W_CFG_PORT_OUTPUT_HIGH) +#else + #define GPIO_W_PRV_MODE_BITS (0xFF7FU) + #define GPIO_W_PRV_FUNC_BITS (0x007FU) +#endif + +#define GPIO_W_PRV_LEVEL_BITS (0x400000U) +#define GPIO_W_PRV_LEVEL_OFFSET (22U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* TODO: This cannot be maintained, use similar solution as RA's BSP_OVERRIDE_IOPORT_PERIPHERAL_T. */ +/** Superset of all peripheral functions. */ +typedef enum e_gpio_w_peripheral +{ + GPIO_W_PERIPHERAL_DEBUG = 0, /**< Pin will function as a DEBUG pin (controlled by SYS_CTRL_REG[DEBUGGER_ENABLE]) */ + GPIO_W_PERIPHERAL_TRACE = 0, /**< Pin will function as a TRACE pin (controlled by DEBUG_REG[ETM_TRACE_MAP_ON_PINS_EN]) */ + GPIO_W_PERIPHERAL_ACOMP = 0, /**< Pin will function as an ACOMP Channel pin */ + GPIO_W_PERIPHERAL_QSPI = 0, /**< Pin will function as a QSPIC pin */ + +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + GPIO_W_PERIPHERAL_GPIO = 0, /**< GPIO */ + GPIO_W_PERIPHERAL_UART_RX = 1, /**< GPIO as UART RX */ + GPIO_W_PERIPHERAL_UART_TX = 2, /**< GPIO as UART TX */ + GPIO_W_PERIPHERAL_UART2_RX = 3, /**< GPIO as UART2 RX */ + GPIO_W_PERIPHERAL_UART2_TX = 4, /**< GPIO as UART2 TX */ + GPIO_W_PERIPHERAL_UART2_CTSN = 5, /**< GPIO as UART2 CTSN */ + GPIO_W_PERIPHERAL_UART2_RTSN = 6, /**< GPIO as UART2 RTSN */ + GPIO_W_PERIPHERAL_UART2_IRDA_RX = 7, /**< GPIO as IRDA RX */ + GPIO_W_PERIPHERAL_UART2_IRDA_TX = 8, /**< GPIO as IRDA TX*/ + GPIO_W_PERIPHERAL_UART3_RX = 9, /**< GPIO as UART3 RX */ + GPIO_W_PERIPHERAL_UART3_TX = 10, /**< GPIO as UART3 TX */ + GPIO_W_PERIPHERAL_UART3_CTSN = 11, /**< GPIO as UART3 CTSN */ + GPIO_W_PERIPHERAL_ISO_RST = 11, /**< GPIO as ISO7816 reset */ + GPIO_W_PERIPHERAL_UART3_RTSN = 12, /**< GPIO as UART3 RTSN */ + GPIO_W_PERIPHERAL_ISO_CARDINSERT = 12, /**< GPIO as ISO7816 card insert */ + GPIO_W_PERIPHERAL_UART4_RX = 13, /**< GPIO as UART4 RX */ + GPIO_W_PERIPHERAL_UART4_TX = 14, /**< GPIO as UART4 TX */ + GPIO_W_PERIPHERAL_UART4_CTSN = 15, /**< GPIO as UART4 CTSN */ + GPIO_W_PERIPHERAL_UART4_RTSN = 16, /**< GPIO as UART4 RTSN */ + GPIO_W_PERIPHERAL_ISO_CLK = 17, /**< GPIO as ISO CLK */ + GPIO_W_PERIPHERAL_ISO_DATA = 18, /**< GPIO as ISO DATA */ + GPIO_W_PERIPHERAL_SPI_DI = 19, /**< GPIO as SPI DI */ + GPIO_W_PERIPHERAL_SPI_DO = 20, /**< GPIO as SPI DO */ + GPIO_W_PERIPHERAL_SPI_CLK = 21, /**< GPIO as SPI CLK */ + GPIO_W_PERIPHERAL_SPI_CS = 22, /**< GPIO as SPI EN */ + GPIO_W_PERIPHERAL_SPI_CS2 = 23, /**< GPIO as SPI EN2 */ + GPIO_W_PERIPHERAL_SPI2_DI = 24, /**< GPIO as SPI2 DI */ + GPIO_W_PERIPHERAL_SPI2_DO = 25, /**< GPIO as SPI2 DO */ + GPIO_W_PERIPHERAL_SPI2_CLK = 26, /**< GPIO as SPI2 CLK */ + GPIO_W_PERIPHERAL_SPI2_CS = 27, /**< GPIO as SPI2 EN */ + GPIO_W_PERIPHERAL_SPI2_CS2 = 28, /**< GPIO as SPI2 EN2 */ + GPIO_W_PERIPHERAL_SPI3_DI = 29, /**< GPIO as SPI3 DI */ + GPIO_W_PERIPHERAL_SPI3_DO = 30, /**< GPIO as SPI3 DO */ + GPIO_W_PERIPHERAL_SPI3_CLK = 31, /**< GPIO as SPI3 CLK */ + GPIO_W_PERIPHERAL_SPI3_CS = 32, /**< GPIO as SPI3 EN */ + GPIO_W_PERIPHERAL_SPI3_CS2 = 33, /**< GPIO as SPI3 EN2 */ + GPIO_W_PERIPHERAL_I2C_SCL = 34, /**< GPIO as I2C SCL */ + GPIO_W_PERIPHERAL_I2C_SDA = 35, /**< GPIO as I2C SDA */ + GPIO_W_PERIPHERAL_I2C2_SCL = 36, /**< GPIO as I2C2 SCL */ + GPIO_W_PERIPHERAL_I2C2_SDA = 37, /**< GPIO as I2C2 SDA */ + GPIO_W_PERIPHERAL_I2C3_SCL = 38, /**< GPIO as I2C3 SCL */ + GPIO_W_PERIPHERAL_I2C3_SDA = 39, /**< GPIO as I2C3 SDA */ + GPIO_W_PERIPHERAL_I3C_SCL = 40, /**< GPIO as I3C SCL */ + GPIO_W_PERIPHERAL_I3C_SDA = 41, /**< GPIO as I3C SDA */ + GPIO_W_PERIPHERAL_USB_SOF = 42, /**< GPIO as USB SOF */ + GPIO_W_PERIPHERAL_CAN_RX = 43, /**< GPIO as CAN RX */ + GPIO_W_PERIPHERAL_CAN_TX = 44, /**< GPIO as CAN TX */ + GPIO_W_PERIPHERAL_ADC = 45, /**< GPIO as ADC (dedicated pin) */ + GPIO_W_PERIPHERAL_USB = 46, /**< GPIO as USB (dedicated pins) */ + GPIO_W_PERIPHERAL_IRGEN = 47, /**< GPIO as IR generator */ + GPIO_W_PERIPHERAL_KBSCN_COL = 48, /**< GPIO as Keyboard Scanner */ + GPIO_W_PERIPHERAL_PCM_DI = 49, /**< GPIO as PCM DI */ + GPIO_W_PERIPHERAL_PCM_DO = 50, /**< GPIO as PCM DO */ + GPIO_W_PERIPHERAL_PCM_FSC = 51, /**< GPIO as PCM FSC */ + GPIO_W_PERIPHERAL_PCM_CLK = 52, /**< GPIO as PCM CLK */ + GPIO_W_PERIPHERAL_PDM_DATA = 53, /**< GPIO as PDM DATA */ + GPIO_W_PERIPHERAL_PDM_CLK = 54, /**< GPIO as PDM CLK */ + GPIO_W_PERIPHERAL_TIMX_PWM = 55, /**< GPIO as TIMx PWM (dedicated pins) */ + GPIO_W_PERIPHERAL_TIMX_1SHOT_PULSE = 56, /**< GPIO as TIMx 1SHOT pulse (dedicated pins) */ + GPIO_W_PERIPHERAL_CLOCK = 57, /**< GPIO as CLOCK */ + GPIO_W_PERIPHERAL_COEX_EXT_ACT = 58, /**< GPIO as COEX EXT ACT */ + GPIO_W_PERIPHERAL_COEX_SMART_ACT = 59, /**< GPIO as COEX SMART ACT */ + GPIO_W_PERIPHERAL_COEX_SMART_PRI = 60, /**< GPIO as COEX SMART PRI */ + GPIO_W_PERIPHERAL_RF_DIAG = 61, /**< GPIO as RF DIAG (dedicated pins) */ + GPIO_W_PERIPHERAL_RFFE_SCLK = 62, /**< GPIO as RFFE SCLK */ + GPIO_W_PERIPHERAL_RFFE_SDATA = 63, /**< GPIO as RFFE SDATA */ +#elif BSP_MCU_GROUP_RA6B2 + GPIO_W_PERIPHERAL_GPIO = 0, /**< GPIO */ + GPIO_W_PERIPHERAL_UART_RX = 1, /**< GPIO as UART RX */ + GPIO_W_PERIPHERAL_UART_TX = 2, /**< GPIO as UART TX */ + GPIO_W_PERIPHERAL_UART2_RX = 3, /**< GPIO as UART2 RX */ + GPIO_W_PERIPHERAL_UART2_TX = 4, /**< GPIO as UART2 TX */ + GPIO_W_PERIPHERAL_UART2_CTSN = 5, /**< GPIO as UART2 CTSN */ + GPIO_W_PERIPHERAL_UART2_RTSN = 6, /**< GPIO as UART2 RTSN */ + GPIO_W_PERIPHERAL_UART2_IRDA_RX = 7, /**< GPIO as IRDA RX */ + GPIO_W_PERIPHERAL_UART2_IRDA_TX = 8, /**< GPIO as IRDA TX*/ + GPIO_W_PERIPHERAL_UART3_RX = 9, /**< GPIO as UART3 RX */ + GPIO_W_PERIPHERAL_UART3_TX = 10, /**< GPIO as UART3 TX */ + GPIO_W_PERIPHERAL_UART3_CTSN = 11, /**< GPIO as UART3 CTSN */ + GPIO_W_PERIPHERAL_UART3_RTSN = 12, /**< GPIO as UART3 RTSN */ + GPIO_W_PERIPHERAL_ISO_CLK = 13, /**< GPIO as ISO CLK */ + GPIO_W_PERIPHERAL_ISO_DATA = 14, /**< GPIO as ISO DATA */ + GPIO_W_PERIPHERAL_SPI_DI = 15, /**< GPIO as SPI DI */ + GPIO_W_PERIPHERAL_SPI_DO = 16, /**< GPIO as SPI DO */ + GPIO_W_PERIPHERAL_SPI_CLK = 17, /**< GPIO as SPI CLK */ + GPIO_W_PERIPHERAL_SPI_CS = 18, /**< GPIO as SPI EN */ + GPIO_W_PERIPHERAL_SPI_CS2 = 19, /**< GPIO as SPI EN2 */ + GPIO_W_PERIPHERAL_SPI2_DI = 20, /**< GPIO as SPI2 DI */ + GPIO_W_PERIPHERAL_SPI2_DO = 21, /**< GPIO as SPI2 DO */ + GPIO_W_PERIPHERAL_SPI2_CLK = 22, /**< GPIO as SPI2 CLK */ + GPIO_W_PERIPHERAL_SPI2_CS = 23, /**< GPIO as SPI2 EN */ + GPIO_W_PERIPHERAL_SPI2_CS2 = 24, /**< GPIO as SPI2 EN2 */ + GPIO_W_PERIPHERAL_SPI3_DI = 25, /**< GPIO as SPI3 DI */ + GPIO_W_PERIPHERAL_SPI3_DO = 26, /**< GPIO as SPI3 DO */ + GPIO_W_PERIPHERAL_SPI3_CLK = 27, /**< GPIO as SPI3 CLK */ + GPIO_W_PERIPHERAL_SPI3_CS = 28, /**< GPIO as SPI3 EN */ + GPIO_W_PERIPHERAL_SPI3_CS2 = 29, /**< GPIO as SPI3 EN2 */ + GPIO_W_PERIPHERAL_I2C_SCL = 30, /**< GPIO as I2C SCL */ + GPIO_W_PERIPHERAL_I2C_SDA = 31, /**< GPIO as I2C SDA */ + GPIO_W_PERIPHERAL_I2C2_SCL = 32, /**< GPIO as I2C2 SCL */ + GPIO_W_PERIPHERAL_I2C2_SDA = 33, /**< GPIO as I2C2 SDA */ + GPIO_W_PERIPHERAL_I3C_SCL = 34, /**< GPIO as I3C SCL */ + GPIO_W_PERIPHERAL_I3C_SDA = 35, /**< GPIO as I3C SDA */ + GPIO_W_PERIPHERAL_CAN_RX = 36, /**< GPIO as CAN RX */ + GPIO_W_PERIPHERAL_CAN_TX = 37, /**< GPIO as CAN TX */ + GPIO_W_PERIPHERAL_ADC = 38, /**< GPIO as ADC (dedicated pin) */ + GPIO_W_PERIPHERAL_IRGEN = 39, /**< GPIO as IR generator */ + GPIO_W_PERIPHERAL_KBSCN_COL = 40, /**< GPIO as Keyboard Scanner */ + GPIO_W_PERIPHERAL_PCM_DI = 41, /**< GPIO as PCM DI */ + GPIO_W_PERIPHERAL_PCM_DO = 42, /**< GPIO as PCM DO */ + GPIO_W_PERIPHERAL_PCM_FSC = 43, /**< GPIO as PCM FSC */ + GPIO_W_PERIPHERAL_PCM_CLK = 44, /**< GPIO as PCM CLK */ + GPIO_W_PERIPHERAL_PDM_DATA = 45, /**< GPIO as PDM DATA */ + GPIO_W_PERIPHERAL_PDM_CLK = 46, /**< GPIO as PDM CLK */ + GPIO_W_PERIPHERAL_TIMX_PWM = 47, /**< GPIO as TIMx PWM (dedicated pins) */ + GPIO_W_PERIPHERAL_TIMX_1SHOT_PULSE = 48, /**< GPIO as TIMx 1SHOT pulse (dedicated pins) */ + GPIO_W_PERIPHERAL_CLOCK = 49, /**< GPIO as CLOCK */ + GPIO_W_PERIPHERAL_COEX_EXT_ACT = 50, /**< GPIO as COEX EXT ACT */ + GPIO_W_PERIPHERAL_COEX_SMART_ACT = 51, /**< GPIO as COEX SMART ACT */ + GPIO_W_PERIPHERAL_COEX_SMART_PRI = 52, /**< GPIO as COEX SMART PRI */ + GPIO_W_PERIPHERAL_RF_DIAG = 53, /**< GPIO as RF DIAG (dedicated pins) */ +#elif BSP_MCU_GROUP_RA6W1 + GPIO_W_PERIPHERAL_GPIO = 0, /**< GPIO */ + GPIO_W_PERIPHERAL_UART_RX = 1, /**< GPIO as UART RX */ + GPIO_W_PERIPHERAL_UART_TX = 2, /**< GPIO as UART TX */ + GPIO_W_PERIPHERAL_UART_CTSN = 3, /**< GPIO as UART CTSN */ + GPIO_W_PERIPHERAL_UART_RTSN = 4, /**< GPIO as UART RTSN */ + GPIO_W_PERIPHERAL_UART_TXDOE = 5, /**< GPIO as UART TXDOE */ + GPIO_W_PERIPHERAL_UART2_RX = 6, /**< GPIO as UART2 RX */ + GPIO_W_PERIPHERAL_UART2_TX = 7, /**< GPIO as UART2 TX */ + GPIO_W_PERIPHERAL_UART2_CTSN = 8, /**< GPIO as UART2 CTSN */ + GPIO_W_PERIPHERAL_UART2_RTSN = 9, /**< GPIO as UART2 RTSN */ + GPIO_W_PERIPHERAL_UART2_TXDOE = 10, /**< GPIO as UART2 TXDOE */ + GPIO_W_PERIPHERAL_UART3_RX = 11, /**< GPIO as UART3 RX */ + GPIO_W_PERIPHERAL_UART3_TX = 12, /**< GPIO as UART3 TX */ + GPIO_W_PERIPHERAL_UART3_CTSN = 13, /**< GPIO as UART3 CTSN */ + GPIO_W_PERIPHERAL_UART3_RTSN = 14, /**< GPIO as UART3 RTSN */ + GPIO_W_PERIPHERAL_UART3_TXDOE = 15, /**< GPIO as UART3 TXDOE */ + GPIO_W_PERIPHERAL_SPI_DI = 16, /**< GPIO as SPI DI */ + GPIO_W_PERIPHERAL_SPI_DO = 17, /**< GPIO as SPI DO */ + GPIO_W_PERIPHERAL_SPI_CLK = 18, /**< GPIO as SPI CLK */ + GPIO_W_PERIPHERAL_SPI_CSN0 = 19, /**< GPIO as SPI CSN0 */ + GPIO_W_PERIPHERAL_SPI_CSN1 = 20, /**< GPIO as SPI CSN1 */ + GPIO_W_PERIPHERAL_SPI2_DI = 21, /**< GPIO as SPI2 DI */ + GPIO_W_PERIPHERAL_SPI2_DO = 22, /**< GPIO as SPI2 DO */ + GPIO_W_PERIPHERAL_SPI2_CLK = 23, /**< GPIO as SPI2 CLK */ + GPIO_W_PERIPHERAL_SPI2_CSN0 = 24, /**< GPIO as SPI2 CSN0 */ + GPIO_W_PERIPHERAL_SPI2_CSN1 = 25, /**< GPIO as SPI2 CSN1 */ + GPIO_W_PERIPHERAL_I2C_SCL = 26, /**< GPIO as I2C SCL */ + GPIO_W_PERIPHERAL_I2C_SDA = 27, /**< GPIO as I2C SDA */ + GPIO_W_PERIPHERAL_I2C2_SCL = 28, /**< GPIO as I2C2 SCL */ + GPIO_W_PERIPHERAL_I2C2_SDA = 29, /**< GPIO as I2C2 SDA */ + GPIO_W_PERIPHERAL_ADC = 30, /**< GPIO as ADC (dedicated pin) */ + GPIO_W_PERIPHERAL_PCM_DI = 31, /**< GPIO as PCM DI */ + GPIO_W_PERIPHERAL_PCM_DO = 32, /**< GPIO as PCM DO */ + GPIO_W_PERIPHERAL_PCM_FSC = 33, /**< GPIO as PCM FSC */ + GPIO_W_PERIPHERAL_PCM_CLK = 34, /**< GPIO as PCM CLK */ + GPIO_W_PERIPHERAL_DMICA_DI = 35, /**< GPIO as DMICA DI */ + GPIO_W_PERIPHERAL_DMIC_CLK = 36, /**< GPIO as DMIC CLK */ + GPIO_W_PERIPHERAL_MCLK = 37, /**< GPIO as MCLK */ + GPIO_W_PERIPHERAL_TIM_PWM = 38, /**< GPIO as TIM PWM */ + GPIO_W_PERIPHERAL_TIM2_PWM = 39, /**< GPIO as TIM2 PWM */ + GPIO_W_PERIPHERAL_TIM3_PWM = 40, /**< GPIO as TIM3 PWM */ + GPIO_W_PERIPHERAL_TIM4_PWM = 41, /**< GPIO as TIM4 PWM */ + GPIO_W_PERIPHERAL_TIM5_PWM = 42, /**< GPIO as TIM5 PWM */ + GPIO_W_PERIPHERAL_TIM6_PWM = 43, /**< GPIO as TIM6 PWM */ + GPIO_W_PERIPHERAL_TIM7_PWM = 44, /**< GPIO as TIM7 PWM */ + GPIO_W_PERIPHERAL_TIM8_PWM = 45, /**< GPIO as TIM8 PWM */ + GPIO_W_PERIPHERAL_TIM_1SHOT = 46, /**< GPIO as TIM 1SHOT */ + GPIO_W_PERIPHERAL_TIM2_1SHOT = 47, /**< GPIO as TIM2 1SHOT */ + GPIO_W_PERIPHERAL_TIM3_1SHOT = 48, /**< GPIO as TIM3 1SHOT */ + GPIO_W_PERIPHERAL_TIM4_1SHOT = 49, /**< GPIO as TIM4 1SHOT */ + GPIO_W_PERIPHERAL_TIM5_1SHOT = 50, /**< GPIO as TIM5 1SHOT */ + GPIO_W_PERIPHERAL_TIM6_1SHOT = 51, /**< GPIO as TIM6 1SHOT */ + GPIO_W_PERIPHERAL_TIM7_1SHOT = 52, /**< GPIO as TIM7 1SHOT */ + GPIO_W_PERIPHERAL_TIM8_1SHOT = 53, /**< GPIO as TIM8 1SHOT */ + GPIO_W_PERIPHERAL_CLOCK = 54, /**< GPIO as CLOCK */ + GPIO_W_PERIPHERAL_FEM_BS = 55, /**< GPIO as FEM_BS */ + GPIO_W_PERIPHERAL_FEM_CS = 56, /**< GPIO as FEM_CS */ + GPIO_W_PERIPHERAL_FEM_CTRL0 = 57, /**< GPIO as FEM CTRL0 */ + GPIO_W_PERIPHERAL_FEM_CTRL1 = 58, /**< GPIO as FEM CTRL1 */ + GPIO_W_PERIPHERAL_FEM_CTRL2 = 59, /**< GPIO as FEM CTRL2 */ + GPIO_W_PERIPHERAL_BT_COEX_CBT = 60, /**< GPIO as BT COEX CBT */ + GPIO_W_PERIPHERAL_BT_WLAN_ACT = 61, /**< GPIO as BT WLAN ACT */ + GPIO_W_PERIPHERAL_BT_ACT = 62, /**< GPIO as BT ACT */ + GPIO_W_PERIPHERAL_BT_PRI = 63, /**< GPIO as BT PRI */ + GPIO_W_PERIPHERAL_RF_SW1 = 64, /**< GPIO as RF SW1 */ + GPIO_W_PERIPHERAL_RF_SW2 = 65, /**< GPIO as RF SW2 */ + GPIO_W_PERIPHERAL_EXT_INTR = 66, /**< GPIO as EXT INTR */ + + GPIO_W_PERIPHERAL_SWCLK = 99, /**< GPIO as SWCLK */ + GPIO_W_PERIPHERAL_SWDIO = 100, /**< GPIO as SWDIO */ + GPIO_W_PERIPHERAL_WPROTECT = 101, /**< GPIO as WPROTECT */ + GPIO_W_PERIPHERAL_CDETECT = 102, /**< GPIO as CDETECT */ + GPIO_W_PERIPHERAL_ZB_WLAN_ACT = 103, /**< GPIO as ZB WLAN ACT */ + GPIO_W_PERIPHERAL_ZB_ACT = 104, /**< GPIO as ZB ACT */ + GPIO_W_PERIPHERAL_ZB_PRI = 105, /**< GPIO as ZB PRI */ + GPIO_W_PERIPHERAL_BTCOEX_ASC0 = 106, /**< GPIO as BTCOEX ASC0 */ + GPIO_W_PERIPHERAL_BTCOEX_ASC1 = 107, /**< GPIO as BTCOEX ASC1 */ + GPIO_W_PERIPHERAL_BTCOEX_ASC2 = 108, /**< GPIO as BTCOEX ASC2 */ +#elif BSP_MCU_GROUP_RA6W3 + GPIO_W_PERIPHERAL_GPIO = 0, /**< GPIO */ + GPIO_W_PERIPHERAL_UART2_TX = 1, /**< GPIO as UART2 TX */ + GPIO_W_PERIPHERAL_UART2_RX = 2, /**< GPIO as UART2 RX */ + GPIO_W_PERIPHERAL_UART2_RTSN = 3, /**< GPIO as UART2 RTSN */ + GPIO_W_PERIPHERAL_UART2_CTSN = 4, /**< GPIO as UART2 CTSN */ + GPIO_W_PERIPHERAL_UART3_TX = 5, /**< GPIO as UART3 TX */ + GPIO_W_PERIPHERAL_UART3_RX = 6, /**< GPIO as UART3 RX */ + GPIO_W_PERIPHERAL_UART3_RTSN = 7, /**< GPIO as UART3 RTSN */ + GPIO_W_PERIPHERAL_UART3_CTSN = 8, /**< GPIO as UART3 CTSN */ + GPIO_W_PERIPHERAL_UART4_TX = 9, /**< GPIO as UART4 TX */ + GPIO_W_PERIPHERAL_UART4_RX = 10, /**< GPIO as UART4 RX */ + GPIO_W_PERIPHERAL_UART4_RTSN = 11, /**< GPIO as UART4 RTSN */ + GPIO_W_PERIPHERAL_UART4_CTSN = 12, /**< GPIO as UART4 CTSN */ + GPIO_W_PERIPHERAL_I2C_SDA = 13, /**< GPIO as I2C SDA */ + GPIO_W_PERIPHERAL_I2C_SCL = 14, /**< GPIO as I2C SCL */ + GPIO_W_PERIPHERAL_I2C2_SDA = 15, /**< GPIO as I2C2 SDA */ + GPIO_W_PERIPHERAL_I2C2_SCL = 16, /**< GPIO as I2C2 SCL */ + GPIO_W_PERIPHERAL_SPI2_CLK = 17, /**< GPIO as SPI2 CLK */ + GPIO_W_PERIPHERAL_SPI2_DI = 18, /**< GPIO as SPI2 DI */ + GPIO_W_PERIPHERAL_SPI2_DO = 19, /**< GPIO as SPI2 DO */ + GPIO_W_PERIPHERAL_SPI2_CS = 20, /**< GPIO as SPI2 CS */ + GPIO_W_PERIPHERAL_SPI3_CLK = 21, /**< GPIO as SPI3 CLK */ + GPIO_W_PERIPHERAL_SPI3_DI = 22, /**< GPIO as SPI3 DI */ + GPIO_W_PERIPHERAL_SPI3_DO = 23, /**< GPIO as SPI3 DO */ + GPIO_W_PERIPHERAL_SPI3_CS = 24, /**< GPIO as SPI3 CS */ + GPIO_W_PERIPHERAL_TIM1_PWM = 25, /**< GPIO as TIM1 PWM */ + GPIO_W_PERIPHERAL_TIM2_PWM = 26, /**< GPIO as TIM2 PWM */ + GPIO_W_PERIPHERAL_TIM3_PWM = 27, /**< GPIO as TIM3 PWM */ + GPIO_W_PERIPHERAL_TIM4_PWM = 28, /**< GPIO as TIM4 PWM */ + GPIO_W_PERIPHERAL_TIM5_PWM = 29, /**< GPIO as TIM5 PWM */ + GPIO_W_PERIPHERAL_TIM6_PWM = 30, /**< GPIO as TIM6 PWM */ + GPIO_W_PERIPHERAL_TIM7_PWM = 31, /**< GPIO as TIM7 PWM */ + GPIO_W_PERIPHERAL_TIM8_PWM = 32, /**< GPIO as TIM8 PWM */ + GPIO_W_PERIPHERAL_TIM9_PWM = 33, /**< GPIO as TIM9 PWM */ + GPIO_W_PERIPHERAL_TIM10_PWM = 34, /**< GPIO as TIM10 PWM */ + GPIO_W_PERIPHERAL_TIM1_1SHOT_PULSE = 35, /**< GPIO as TIM1 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM2_1SHOT_PULSE = 36, /**< GPIO as TIM2 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM3_1SHOT_PULSE = 37, /**< GPIO as TIM3 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM4_1SHOT_PULSE = 38, /**< GPIO as TIM4 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM5_1SHOT_PULSE = 39, /**< GPIO as TIM5 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM6_1SHOT_PULSE = 40, /**< GPIO as TIM6 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM7_1SHOT_PULSE = 41, /**< GPIO as TIM7 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM8_1SHOT_PULSE = 42, /**< GPIO as TIM8 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM9_1SHOT_PULSE = 43, /**< GPIO as TIM9 1SHOT pulse */ + GPIO_W_PERIPHERAL_TIM10_1SHOT_PULSE = 44, /**< GPIO as TIM10 1SHOT pulse */ + GPIO_W_PERIPHERAL_USB_SOF = 45, /**< GPIO as USB SOF */ + GPIO_W_PERIPHERAL_ADC = 46, /**< GPIO as ADC (dedicated pin) */ + GPIO_W_PERIPHERAL_PCM_DI = 47, /**< GPIO as PCM DI */ + GPIO_W_PERIPHERAL_PCM_MCLK = 48, /**< GPIO as PCM ΜCLK */ + GPIO_W_PERIPHERAL_PCM_DO = 49, /**< GPIO as PCM DO */ + GPIO_W_PERIPHERAL_PCM_BCLK = 50, /**< GPIO as PCM ΒCLK */ + GPIO_W_PERIPHERAL_PCM_CLK = 51, /**< GPIO as PCM CLK */ + GPIO_W_PERIPHERAL_DMIC_CLK = 52, /**< GPIO as DMIC CLK */ + GPIO_W_PERIPHERAL_DMIC_DATA = 53, /**< GPIO as DMIC DATA */ + GPIO_W_PERIPHERAL_TEST_CLOCK = 54, /**< GPIO as TEST CLOCK */ + GPIO_W_PERIPHERAL_CMAC_DIAG = 55, /**< GPIO as CMAC DIAG */ + GPIO_W_PERIPHERAL_COEX_REQ = 56, /**< GPIO as COEX REQ */ + GPIO_W_PERIPHERAL_COEX_CNT = 57, /**< GPIO as COEX CNT */ + GPIO_W_PERIPHERAL_COEX_PRI = 58, /**< GPIO as COEX PRI */ +#endif +} gpio_w_peripheral_t; + +// TIN_HACK_WIFI - TEMP for keeping r_ble_gtl.c compatible with both rrq and da during the transition +#define IOPORT_CFG_IRQ_ENABLE GPIO_W_CFG_IRQ_ENABLE + +/** GPIO_W private control block. DO NOT MODIFY. Initialization occurs when R_GPIO_W_Open() is called. */ +typedef struct st_gpio_w_instance_ctrl +{ + uint32_t open; + void const * p_context; + volatile uint32_t * p_reg_p0_data; + volatile uint32_t * p_reg_p0_set_data; + volatile uint32_t * p_reg_p0_reset_data; + volatile uint32_t * p_reg_p0_00_mode; +} gpio_w_instance_ctrl_t; + +/* TIN-TODO: HW dependent types should be guarded with features, not device families. */ +#if !defined(BSP_MCU_GROUP_RA6W1) + +/** Pins power configuration structure */ +typedef struct e_pad_power_t +{ + uint32_t p0_pwr; /**< Pins output power for P0 */ + uint32_t p1_pwr; /**< Pins output power for P1 */ + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + uint16_t p2_pwr; /**< Pins output Power for P2 */ + #endif +} pad_power_t; + +/** Pins driving strength configuration structure */ +typedef struct e_pad_weak_t +{ + #if BSP_FEATURE_IO_HAS_WEAK_CONFIG_PER_PORT + uint32_t p0_pwr; /**< Pins driving strength for P0 */ + uint32_t p1_pwr; /**< Pins driving strength for P1 */ + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + uint32_t p2_pwr; /**< Pins driving strength for P2 */ + #endif + #else + uint32_t aggregate; + #endif +} pad_weak_t; + +/* TIN-TODO: Selecting a clock output is supported through GPIO_CLK_SEL_REG but was not implemented. */ +/** Map clock output to selectable pin structure */ +typedef struct e_sel_pin_clk_out_t +{ + bsp_io_clk_func_t clk_sel; /**< Select which clock to map */ + bool clk_en; /**< Enable mapping of the selected clock signal */ +} sel_pin_clk_out_t; + +/** Extended configuration struct */ +typedef struct st_gpio_w_extended_cfg +{ + pad_power_t power; /**< Pins power configuration */ + pad_weak_t weak_pad_power; /**< Pins driving strength configuration */ + bsp_io_clk_output_t fixed_pin_clk_out; /**< Map clock output to fixed pin */ + sel_pin_clk_out_t sel_pin_clk_out; /**< Map clock output to selectable pin */ +} gpio_w_extended_cfg_t; +#endif + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_gpio_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_GPIO_W_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_GPIO_W_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_GPIO_W_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_GPIO_W_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_GPIO_W_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_GPIO_W_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_GPIO_W_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_GPIO_W_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_GPIO_W_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_GPIO_W_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_GPIO_W_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_GPIO_W_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_GPIO_W_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup GPIO_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_GPIO_W_H diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_i2c_master_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_i2c_master_w.h new file mode 100644 index 000000000000..214b997d6f27 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_i2c_master_w.h @@ -0,0 +1,165 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup I2C_MASTER_W + * @{ + **********************************************************************************************************************/ + +#ifndef R_I2C_MASTER_W_H +#define R_I2C_MASTER_W_H + +#include "r_i2c_master_w_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** + * I2C high speed master code. + * This bit field holds the value of the I2C HS mode master code. + * HS-mode master codes are reserved 8-bit codes (00001xxx) + * that are not used for slave addressing or other purposes. + * Each master has its unique master code. + * Up to eight high-speed mode masters can be present on the same I2C bus system. + * Valid values are from 0 to 7. + * This can be written only when the I2C interface is disabled, + * which corresponds to the IC_ENABLE[0] register being set to 0. + * Writes at other times have no effect. + * + */ +#define I2C_MASTER_W_I2C1_MADDR 0x01 +#define I2C_MASTER_W_I2C2_MADDR 0x05 +#define I2C_MASTER_W_I2C3_MADDR 0x07 + +/** TX/RX FIFO depth */ +#define I2C_MASTER_W_FIFO_DEPTH (32) + +/** Offset to make the I2C HW channels 0-based for the r_i2c_master_w driver. */ +#if (BSP_FEATURE_I2C_VALID_CHANNEL_MASK & 0x1) + #define I2C_MASTER_W_CHANNEL_OFFSET 0 +#elif (BSP_FEATURE_I2C_VALID_CHANNEL_MASK & 0x2) + #define I2C_MASTER_W_CHANNEL_OFFSET 1 +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C interrupt source */ +typedef enum e_i2c_master_w_int +{ + I2C_MASTER_W_INT_RX_UNDERFLOW = I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk, ///< Attempt to read from empty RX FIFO has been made + I2C_MASTER_W_INT_RX_OVERFLOW = I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk, ///< RX FIFO is full but new data are incoming and being discarded + I2C_MASTER_W_INT_RX_FULL = I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk, ///< RX FIFO level is equal or above threshold + I2C_MASTER_W_INT_TX_OVERFLOW = I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk, ///< Attempt to write to TX FIFO which is already full + I2C_MASTER_W_INT_TX_EMPTY = I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk, ///< TX FIFO level is equal or below threshold + I2C_MASTER_W_INT_READ_REQUEST = I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk, ///< I2C master attempts to read data(slave only) + I2C_MASTER_W_INT_TX_ABORT = I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk, ///< TX cannot be completed + I2C_MASTER_W_INT_RX_DONE = I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk, ///< I2C master did not acknowledge transmitted byte(slave only) + I2C_MASTER_W_INT_ACTIVITY = I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk, ///< Any I2C activity occurred + I2C_MASTER_W_INT_STOP_DETECTED = I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk, ///< STOP condition occurred + I2C_MASTER_W_INT_START_DETECTED = I2C_I2C_INTR_STAT_REG_R_START_DET_Msk, ///< START/RESTART condition occurred + I2C_MASTER_W_INT_GENERAL_CALL = I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk ///< General Call address received(slave only) +} i2c_master_w_int_t; + +/** I2C clock settings */ +typedef struct i2c_master_w_clock_settings +{ + uint16_t scl_hcnt; ///< I2C clock (SCL) high count + uint16_t scl_lcnt; ///< I2C clock (SCL) low count +} i2c_master_w_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_i2c_master_w_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + + uint32_t open; // Flag to determine if the device is open + I2C_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + uint16_t p_transfer_api_tx_buff[I2C_MASTER_W_CFG_TRANSFER_API_TX_BUFFER_SIZE]; // Holds the data associated with the DTC/DMA transfer +#endif + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t nof_bytes; // Tracks the read bytes in a tranfer + uint32_t loaded; // Tracks the number of data bytes written to the register + + volatile bool read; // Holds the direction of the data byte transfer + volatile bool restart; // Holds whether or not the restart should be issued when done + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} i2c_master_w_instance_ctrl_t; + +/** R_I2C extended configuration */ +typedef struct st_i2c_master_w_extended_cfg +{ +#if I2C_MASTER_W_CFG_DMA_ENABLE + bool enable_dma_bursts_tx; ///< Enable DMA Burst TX Transactions when the transaction length is 4- or 8-byte aligned + bool enable_dma_bursts_rx; ///< Enable DMA Burst RX Transactions when the transaction length is 4- or 8-byte aligned +#endif + i2c_master_w_clock_settings_t clock_settings; ///< I2C Clock settings + bool select_divn; ///< Select the clock source (DIVN/DIV1 clock) + IRQn_Type gen_irq; ///< Generic I2C Interrupt IRQ number. + uint8_t gen_ipl; ///< Generic I2C Interrupt Priority. +} i2c_master_w_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_i2c_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); + +fsp_err_t R_I2C_MASTER_W_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_I2C_MASTER_W_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_I2C_MASTER_W_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_I2C_MASTER_W_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_I2C_MASTER_W_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_I2C_MASTER_W_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_I2C_MASTER_W_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_I2C_MASTER_W_H + +/*******************************************************************************************************************//** + * @} (end defgroup I2C_MASTER_W) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ospi_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ospi_w.h new file mode 100644 index 000000000000..5116043795f8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_ospi_w.h @@ -0,0 +1,1735 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup OSPI_W + * @{ + **********************************************************************************************************************/ + +#ifndef R_OSPI_W_H +#define R_OSPI_W_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ospi_w_cfg.h" +#include "r_spi_flash_api.h" + +#include "../../src/bsp/mcu/ra6w1/sdk_defs.h" +#if OSPI_W_CFG_DMAC_SUPPORT_ENABLE + #include "r_transfer_api.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define OSPI_W_STATREG_PR_CMD 0x01 +#define OSPI_W_READ_CMD 0x03 +#define OSPI_W_PAGEPR_CMD 0x02 +#define OSPI_W_STATREG_R_CMD 0x05 +#define OSPI_W_WREN_CMD 0x06 +#define OSPI_W_SECTOR_ERASE_CMD 0x20 +#define OSPI_W_RESET_EN_CMD 0x66 +#define OSPI_W_RESET_CMD 0x99 +#define OSPI_W_EXIT_DPD_CMD 0xAB +#define OSPI_W_EXIT_DPD_CMD_INV 0x54 +#define OSPI_W_DUMMY_CMD 0x00 +#define OSPI_W_QUAD_PAGEPR_CMD 0x33 +#define OSPI_W_QUAD_PAGEPR_CMD_2 0x38 +#define OSPI_W_SINGLE_ADDR_QUAD_PAGEPR_CMD 0x32 + +#define OSPI_W_AUTOMODE_BASE_ADD BSP_FEATURE_OSPI_W_DEVICE_0_START_ADDRESS // (0x2A000000) + +#define SPI_READ_STATUS_REG_CMD 0x05 +#define OSPI_WRITE_ENABLE_CMD 0x06 +#define OSPI_FAST_READ3B_CMD 0x0B +#define OSPI_FAST_READ4B_CMD 0x0C +#define OSPI_EXIT_CONTINUOUS_MODE_CMD (0xFF) + +#define OSPI_FLASH_PAGE_SIZE (0x100) +#define OSPI_FLASH_SECTOR_LENGTH (0x1000) +#define ON_STACK_BUFFER_SIZE 256 + +typedef union +{ + __IO uint32_t data32; + __IO uint16_t data16; + __IO uint8_t data8; +} ospi_w_data_t; + +typedef struct /*!< (@ 0x36000000) OQSPIF Structure */ +{ + __IOM uint32_t ospi_reserved0; + __IOM uint32_t ospi_reserved1; + __IOM uint32_t ospi_reserved2; + __IOM uint32_t ospi_reserved3; + __IOM uint32_t ospi_reserved4; + __IOM uint32_t ospi_reserved5; + __IOM ospi_w_data_t OQSPIF_WRITEDATA_REG; + __IOM ospi_w_data_t OQSPIF_READDATA_REG; + __IOM ospi_w_data_t OQSPIF_DUMMYDATA_REG; +} ospi_w_regs_t; + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* OQSPI Bus status */ +typedef enum +{ + OSPI_W_DEVICE_BUS_STATUS_IDLE = 0, /* The SPI Bus is idle */ + OSPI_W_DEVICE_BUS_STATUS_ACTIVE = 1, /* The SPI Bus is active. Read data, write data + * or dummy data activity is in progress.*/ +} ospi_w_device_bus_status; + +/** OSPI_W clock divider */ +typedef enum +{ + OSPI_W_DEVICE_CLK_DIV_1 = 0, /**< divide by 1 */ + OSPI_W_DEVICE_CLK_DIV_2 = 1, /**< divide by 2 */ + OSPI_W_DEVICE_CLK_DIV_4 = 2, /**< divide by 4 */ + OSPI_W_DEVICE_CLK_DIV_8 = 3 /**< divide by 8 */ +} ospi_w_device_clk_div; + +/** OSPI_W bus mode */ +typedef enum +{ + OSPI_W_DEVICE_BUS_MODE_NOT_SET = -1, /**< Bus mode not set */ + OSPI_W_DEVICE_BUS_MODE_SINGLE = 0, /**< Bus mode in single mode */ + OSPI_W_DEVICE_BUS_MODE_DUAL = 1, /**< Bus mode in dual mode */ + OSPI_W_DEVICE_BUS_MODE_QUAD = 2, /**< Bus mode in quad mode */ + OSPI_W_DEVICE_BUS_MODE_OCTA = 3 /**< Bus mode in octa mode */ +} ospi_w_device_bus_mode; + +/** OSPI_W memory access mode */ +typedef enum +{ + OSPI_W_DEVICE_ACCESS_MODE_MANUAL = 0, /**< Manual Mode is selected */ + OSPI_W_DEVICE_ACCESS_MODE_AUTO = 1 /**< Auto Mode is selected */ +} ospi_w_device_access_mode; + +/** OSPI_W clock mode */ +typedef enum +{ + OSPI_W_DEVICE_CLK_MODE_LOW = 0, /**< Mode 0: OSPI_SCK is low when OSPI_CS is high. */ + OSPI_W_DEVICE_CLK_MODE_HIGH = 1 /**< Mode 3: OSPI_SCK is high when OSPI_CS is high. */ +} ospi_w_device_clk_mode; + +/** OSPI_W pad direction */ +typedef enum +{ + OSPI_W_DEVICE_IO_DIR_AUTO_SEL = 0, /**< The OQSPI pad is determined by the controller. */ + OSPI_W_DEVICE_IO_DIR_OUTPUT = 1 /**< The OQSPI pad is output */ +} ospi_w_device_io_dir; + +/** OSPI_W IO2/IO3 pad value */ +typedef enum +{ + OSPI_W_DEVICE_IO_VALUE_LOW = 0, + OSPI_W_DEVICE_IO_VALUE_HIGH = 1, +} ospi_w_device_io_value; + +/** OSPI_W IO4-7 pads values */ +typedef enum +{ + OSPI_W_DEVICE_IO4_7_VALUE_0000 = 0, + OSPI_W_DEVICE_IO4_7_VALUE_1111 = 0xF, +} ospi_w_device_io4_7_value; + +/** OSPI_W HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers */ +typedef enum +{ + OSPI_W_DEVICE_HREADY_MODE_WAIT = 0, /**< Adds wait states via hready signal when an + * accessing the OSPIC_WRITEDATA, OSPIC_READDATA + * and OSPIC_DUMMYDATA registers. */ + OSPI_W_DEVICE_HREADY_MODE_NO_WAIT = 1 /**< Don't add wait states via the HREADY signal */ +} ospi_w_device_hready_mode; + +/** OSPI_W clock edge setting for the sampling of the incoming data when the read pipe is disabled */ +typedef enum +{ + OSPI_W_DEVICE_SAMPLING_EDGE_POS = 0, /**< The incoming data sampling is triggered by the + * positive edge of OSPI_W clock signal */ + OSPI_W_DEVICE_SAMPLING_EDGE_NEG = 1 /**< The incoming data sampling is triggered by the + * negative edge of OSPI_W clock signal */ +} ospi_w_device_sampling_edge; + +/** OSPI_W read pipe setting + * When read pipe is disabled the sampling clock is determined by @ref ospi_w_device_sampling_edge + * while when is enabled by @ref ospi_w_device_read_pipe_delay. In ASIC is always recommended to + * enable read pipe and set the @ref ospi_w_device_read_pipe_delay to the optimal value. + */ +typedef enum +{ + OSPI_W_DEVICE_READ_PIPE_DISABLE = 0, + OSPI_W_DEVICE_READ_PIPE_ENABLE = 1, +} ospi_w_device_read_pipe; + +/** OSPI_W Read pipe clock delay in relation to the falling edge of OSPI_SCK */ +typedef enum +{ + OSPI_W_DEVICE_READ_PIPE_DELAY_0 = 0, + OSPI_W_DEVICE_READ_PIPE_DELAY_1 = 1, + OSPI_W_DEVICE_READ_PIPE_DELAY_2 = 2, + OSPI_W_DEVICE_READ_PIPE_DELAY_3 = 3, + OSPI_W_DEVICE_READ_PIPE_DELAY_4 = 4, + OSPI_W_DEVICE_READ_PIPE_DELAY_5 = 5, + OSPI_W_DEVICE_READ_PIPE_DELAY_6 = 6, + OSPI_W_DEVICE_READ_PIPE_DELAY_7 = 7, +} ospi_w_device_read_pipe_delay; + +/* + * OSPI_W behavior in auto mode when the internal buffer is full and there are more data to be retrieved for the current burst + */ +typedef enum +{ + OSPI_W_DEVICE_FULL_BUFFER_MODE_BLOCK = 0, /* The access in the flash device is not + * terminated when the internal buffer has + * no empty space. In this case the OSPI_W + * clock is blocked until there is free + * space */ + OSPI_W_DEVICE_FULL_BUFFER_MODE_TERMINATE = 1, /* The access in the flash device is + * terminated when the internal buffer has + * no empty space. A new access in the + * flash device will be initiated when + * the requested addresses are not present + * in the internal buffer */ +} ospi_w_device_full_buffer_mode; + +/** OSPI_W memory address size */ +typedef enum +{ + OSPI_W_DEVICE_ADDR_SIZE_24 = 0, /**< 24 bits address */ + OSPI_W_DEVICE_ADDR_SIZE_32 = 1 /**< 32 bits address */ +} ospi_w_device_addr_size; + +/** OSPI_W number of bytes of the instruction code in automode */ +typedef enum +{ + OSPI_W_DEVICE_INSTRUCT_SZ_1_BYTE = 0, /**< The instruction code is one byte */ + OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES = 1, /**< The instruction code is two bytes. The second + * byte equals to the inverse value of the first + * byte */ +} ospi_w_device_instruct_sz; + +/** OSPI_W clock cycle where the bus switches to Hi-Z during the transmission of dummy bytes */ +typedef enum +{ + OSPI_W_DEVICE_DUMMY_MODE_LAST_CLK = 0, /**< Switch to Hi-Z on the last clock */ + OSPI_W_DEVICE_DUMMY_MODE_LAST_2_CLK = 1, /**< Switch to Hi-Z on the last two clocks */ +} ospi_w_device_dummy_mode; + +/* + * OSPI_W direction change method in manual mode + */ +typedef enum +{ + OSPI_W_DEVICE_DIR_CHANGE_MODE_EACH_ACCESS = 0, /* The bus direction switches to input + * after each access */ + OSPI_W_DEVICE_DIR_CHANGE_MODE_DUMMY_ACCESS = 1, /* The bus direction switches to input + * only after a dummy access */ +} ospi_w_device_dir_change_mode; + +/* + * OSPI_W AHB bus error response when a read is performed in the address space where the + * flash device is mapped and the Auto mode is not enabled + */ +typedef enum +{ + OSPI_W_DEVICE_MAPPED_ADDR_RD_ACC_RESPONSE_IGNORE = 0, /* The read access is ignored and + * there is no error due to the read + * access */ + OSPI_W_DEVICE_MAPPED_ADDR_RD_ACC_RESPONSE_AHB_ERROR = 1, /* Respond with an AHB bus error */ +} ospi_w_device_mapped_addr_rd_acc_response; + +/* + * OSPI_W burst length in automode when the read access in the AHB bus is an incremental + * burst of unspecified length + * + * This setting is useful in case that the masters that make use of the incremental burst + * of unspecified length, require no more than 8 bytes. Set this setting to @ref + * OSPI_W_DEVICE_BURST_LEN_LIMIT_8_BYTES in order to optimize the cache controller read access + * performance. + */ +typedef enum +{ + OSPI_W_DEVICE_BURST_LEN_LIMIT_UNSPECIFIED = 0, /* Unspecified length of the burst */ + OSPI_W_DEVICE_BURST_LEN_LIMIT_8_BYTES = 1, /* The length of the burst is considered + * as equal to 8 bytes. The access in the + * flash device will be implemented by the + * controller as one or more different + * bursts, until the AHB bus access to be + * completed. Each burst in the flash + * device will have maximum length of 8 + * bytes */ +} ospi_w_device_burst_len_limit; + +/** OSPI_W pads slew rate control */ +typedef enum +{ + OSPI_W_DEVICE_SLEW_RATE_0 = 0, /**< Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak) */ + OSPI_W_DEVICE_SLEW_RATE_1 = 1, /**< Rise = 2.0 V/ns, Fall = 2.3 V/ns */ + OSPI_W_DEVICE_SLEW_RATE_2 = 2, /**< Rise = 2.3 V/ns, Fall = 2.6 V/ns */ + OSPI_W_DEVICE_SLEW_RATE_3 = 3 /**< Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong) */ +} ospi_w_device_slew_rate; + +/** OSPI_W pads drive current */ +typedef enum +{ + OSPI_W_DEVICE_DRIVE_CURRENT_4 = 0, /**< 4 mA */ + OSPI_W_DEVICE_DRIVE_CURRENT_8 = 1, /**< 8 mA */ + OSPI_W_DEVICE_DRIVE_CURRENT_12 = 2, /**< 12 mA */ + OSPI_W_DEVICE_DRIVE_CURRENT_16 = 3, /**< 16 mA */ +} ospi_w_device_drive_current; + +/** OSPI_W extra byte setting in auto access mode */ +typedef enum +{ + OSPI_W_DEVICE_EXTRA_BYTE_DISABLE = 0, /**< Don't send the extra byte */ + OSPI_W_DEVICE_EXTRA_BYTE_ENABLE = 1, /**< Send the extra byte */ +} ospi_w_device_extra_byte; + +/* + * OSPI_W extra byte half setting in auto access mode + * + * This setting is out of scope if the extra byte is disabled or transferred in Octal mode. + * Especially in the latter case keep this setting disabled. + */ +typedef enum +{ + OSPI_W_DEVICE_EXTRA_BYTE_HALF_DISABLE = 0, /* Transmit the complete extra byte */ + OSPI_W_DEVICE_EXTRA_BYTE_HALF_ENABLE = 1, /* The output switches to Hi-Z during the + * transmission of bits [3:0] of the extra byte */ +} ospi_w_device_extra_byte_half; + +/** OSPI_W Instruction mode in auto access mode */ +typedef enum +{ + OSPI_W_DEVICE_INSTR_MODE_SEND_ANYTIME = 0, /**< Transmit instruction at any burst access */ + OSPI_W_DEVICE_INSTR_MODE_SEND_ONCE = 1 /**< Transmit instruction only in the first access + * after the selection of Auto Mode */ +} ospi_w_device_instr_mode; + +/* + * OSPI_W wrapping burst mode in auto access mode + */ +typedef enum +{ + OSPI_W_DEVICE_WRAP_MODE_INSTR = 0, /* The OSPIC_INST is the selected instruction at any + * access */ + OSPI_W_DEVICE_WRAP_MODE_INSTR_WRAP = 1, /* The OSPIC_INST_WB is the selected instruction at + * any wrapping burst access */ +} ospi_w_device_wrap_mode; + +/* + * OSPI_W data length of a wrapping burst in auto access mode + */ +typedef enum +{ + OSPI_W_DEVICE_WRAP_LEN_4BEAT = 0, /* 4 beat wrapping burst */ + OSPI_W_DEVICE_WRAP_LEN_8BEAT = 1, /* 8 beat wrapping burst */ + OSPI_W_DEVICE_WRAP_LEN_16BEAT = 2, /* 16 beat wrapping burst */ +} ospi_w_device_wrap_len; + +/* + * OSPI_W data size of a wrapping burst in auto access mode + */ +typedef enum +{ + OSPI_W_DEVICE_WRAP_SIZE_8BITS = 0, /* Byte access (8-bits) */ + OSPI_W_DEVICE_WRAP_SIZE_16BITS = 1, /* Half word access (16-bits) */ + OSPI_W_DEVICE_WRAP_SIZE_32BITS = 2, /* Word access (32-bits) */ +} ospi_w_device_wrap_size; + +/* + * OSPI_W bus idle state (OSPI_CS high) duration (in OSPI_SCK clock cycles) between two + * consecutive instructions + */ +typedef enum +{ + OSPI_W_DEVICE_IDLE_STATE_DURATION_0 = 0, + OSPI_W_DEVICE_IDLE_STATE_DURATION_1 = 1, + OSPI_W_DEVICE_IDLE_STATE_DURATION_2 = 2, + OSPI_W_DEVICE_IDLE_STATE_DURATION_3 = 3, +} ospi_w_device_idle_state_duration; + +/* + * OSPI_W device busy status setting + */ +typedef enum +{ + OSPI_W_DEVICE_BUSY_LOW = 0, /* The OQSPI device is busy when the corresponding bit is 0 */ + OSPI_W_DEVICE_BUSY_HIGH = 1 /* The OQSPI device is busy when the corresponding bit is 1 */ +} ospi_w_device_busy; + +/* + * Select OSPI_W counter for counting a delay between device Status Register read instruction + * and erase or erase/resume instruction + */ +typedef enum +{ + OSPI_W_DEVICE_READ_STATUS_REG_CNT_RESSTS = 0, /* The counter value is determined by the field + * OSPIC_RESSTS_DLY and is clocked by OSPI_CLK */ + OSPI_W_DEVICE_READ_STATUS_REG_CNT_RESSUS = 1 /* The counter value is determined by the field + * OSPIC_RESSUS_DLY field and is clocked by a + * 222 kHz clock */ +} ospi_w_device_read_status_reg_cnt; + +/* + * Defines the value that is transferred on the OSPI bus during the phase of the dummy bytes + */ +typedef enum +{ + OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL_UNCHANGED = 0, /* The controller keeps the data in the bus + * unchanged, until the bus direction + * changes to input mode */ + OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL_FORCED_ZERO = 1, /* Forces the dummy bytes to get the zero + * value as long as the bus direction is + * not in input mode. Only IO pins which + * are relevant with the transfer mode of + * the dummy bytes get the zero value + * (according to bus mode of the dummy + * phase). */ +} ospi_w_device_read_status_dummy_val; + +/* + * The status of sector/block erasing + */ +typedef enum +{ + OSPI_W_DEVICE_ERS_NO = 0, /* no erase */ + OSPI_W_DEVICE_ERS_PENDING = 1, /* pending erase request */ + OSPI_W_DEVICE_ERS_RUNNING = 2, /* erase procedure is running */ + OSPI_W_DEVICE_ERS_SUSPENDED = 3, /* suspended erase procedure */ + OSPI_W_DEVICE_ERS_FINISHING = 4 /* finishing the erase procedure */ +} ospi_w_device_ers; + +/* + * OSPI_W manual mode configuration structure + */ +typedef struct +{ + ospi_w_device_dir_change_mode dir_change_mode : 1; + ospi_w_device_mapped_addr_rd_acc_response mapped_addr_rd_acc_response : 1; +} ospi_w_device_manualmode_config_t; + +/* + * OSPI_W automode configuration structure + */ +typedef struct +{ + ospi_w_device_full_buffer_mode full_buffer_mode : 1; + ospi_w_device_instruct_sz instruct_size : 1; + ospi_w_device_burst_len_limit burst_len_limit : 1; +} ospi_w_device_automode_config_t; + +/** OSPI_W configuration structure */ +typedef struct +{ + ospi_w_device_clk_div clk_div : 2; ///< Clock divider value + ospi_w_device_bus_mode bus_mode : 3; ///< Read bus mode. + ospi_w_device_access_mode access_mode : 1; ///< Access mode. + ospi_w_device_clk_mode clock_mode : 1; ///< Clock mode + ospi_w_device_io_dir io2_dir : 1; ///< IO2 direction. + ospi_w_device_io_value io2_value : 1; ///< IO2 value. + ospi_w_device_io_dir io3_dir : 1; ///< IO3 direction. + ospi_w_device_io_value io3_value : 1; ///< IO3 value. + ospi_w_device_io_dir io4_7_dir : 1; ///< IO4-7 direction. + ospi_w_device_io4_7_value io4_7_value : 4; ///< IO4-7 value. + ospi_w_device_hready_mode hready_mode : 1; ///< HREADY mode. + ospi_w_device_sampling_edge sampling_edge : 1; ///< Sampling_edge. + ospi_w_device_read_pipe read_pipe : 1; ///< Read pipe setting. + ospi_w_device_read_pipe_delay read_pipe_delay : 3; ///< Read pipe delay value. + ospi_w_device_addr_size address_size : 1; ///< Flash address size. + ospi_w_device_dummy_mode dummy_mode : 1; ///< Dummy mode. + ospi_w_device_slew_rate slew_rate : 2; ///< Slew rate + ospi_w_device_drive_current drive_current : 2; ///< Drive current + ospi_w_device_manualmode_config_t manualmode_config; + ospi_w_device_automode_config_t automode_config; +} ospi_w_device_config_t; + +/** OSPI_W read instruction configuration structure (auto access mode) */ +typedef struct +{ + bool enable; /**< Enable read instruction */ + uint8_t instr; /**< Instruction code for Incremental + * Burst or Single read access. + * Also used when wrapping burst + * is not supported. */ + uint8_t instr_extra_byte; /**< Extra byte instruction. Usually + * the Mode Bits in Dual/Quad/ + * Octal SPI I/O instructions */ + ospi_w_device_bus_mode instr_bus_mode; /**< Bus mode during the instruction phase */ + ospi_w_device_bus_mode addr_bus_mode; /**< Bus mode during the address phase */ + ospi_w_device_bus_mode extra_byte_bus_mode; /**< Bus mode during the extra byte phase */ + ospi_w_device_bus_mode dummy_bus_mode; /**< Bus mode during the dummy phase */ + ospi_w_device_bus_mode data_bus_mode; /**< Bus mode during the data phase */ + ospi_w_device_extra_byte extra_byte_cfg; /**< Extra byte enable/disable */ + ospi_w_device_extra_byte_half extra_byte_half_cfg; /**< Enable/disable of extra byte half setting */ + uint8_t dummy_bytes; /**< The number of dummy bytes (0..32) */ + ospi_w_device_instr_mode instr_mode; + ospi_w_device_idle_state_duration idle_state_duration; +} ospi_w_device_read_instr_config_t; + +/* + * OSPI_W wrapping burst instruction configuration structure (auto access mode) + */ +typedef struct +{ + bool enable; /* Enable wrapping burst instruction */ + uint8_t instr; /* Wrapping burst instruction code */ + ospi_w_device_wrap_mode mode; /* Wrapping burst mode */ + ospi_w_device_wrap_len len; /* Wrapping burst length */ + ospi_w_device_wrap_size size; /* Wrapping burst size */ +} ospi_w_device_wrap_burst_instr_config_t; + +/** OSPI_W erase instruction configuration structure (auto access mode) */ +typedef struct +{ + bool enable; /**< Enable erase instruction */ + uint8_t instr; /**< Erase instruction code */ + ospi_w_device_bus_mode instr_bus_mode; /**< Bus mode during the instruction phase */ + ospi_w_device_bus_mode addr_bus_mode; /**< Bus mode during the address phase */ + uint8_t hclk_cycles; /**< The number of AMBA AHB hclk cycles + * (0..15) without memory read requests + * before the controller can execute + * erase or erase resume instructions */ + uint8_t cs_hi_cycles; /**< The minimum number of QSPI bus clock + * cycles (0..31) that OSPI_CS remains + * high after the execution of write + * enable, erase, erase suspend and + * erase resume instructions. */ +} ospi_w_device_erase_instr_config_t; + +/** OSPI_W read status instruction configuration structure (auto access mode) */ +typedef struct +{ + bool enable; /**< Enable read status instruction */ + uint8_t instr; /**< Read status instruction code */ + ospi_w_device_bus_mode instr_bus_mode; /**< Bus mode during the instruction phase */ + ospi_w_device_bus_mode receive_bus_mode; /**< Bus mode during the receive status phase */ + ospi_w_device_bus_mode dummy_bus_mode; /**< Bus mode during the dummy bytes phase */ + uint8_t busy_pos; /**< The position of the Busy bit in the + * status register (0 - 7) */ + ospi_w_device_busy busy_val; /**< Busy status setting */ + uint8_t read_stat_del; /**< The minimum time distance between the + * read status instruction and previous + * erase or erase/resume instructions. + * 0: don't wait. The controller can read + * the memory status register immediately. + * 1..63 - the controller waits at least + * this number of QSPI_CLK cycles before + * reading the memory status register + * following the end of a previous erase + * or erase resume */ + ospi_w_device_read_status_reg_cnt read_stat_reg_cnt; + uint8_t dummy_bytes; /**< The number of dummy bytes (0..16) */ + ospi_w_device_read_status_dummy_val dummy_val; /**< Dummy bytes value */ +} ospi_w_device_read_status_config_t; + +/** OSPI_W write enable instruction configuration structure (auto access mode) */ +typedef struct +{ + bool enable; /**< Enable write enable instruction */ + uint8_t instr; /**< Write enable instruction code */ + ospi_w_device_bus_mode instr_bus_mode; /**< Bus mode during the instruction phase */ +} ospi_w_device_write_enable_instr_config_t; + +/** OSPI_W erase suspend/resume instruction structure */ +typedef struct +{ + bool enable; /**< Enable erase suspend/resume instruction */ + uint8_t suspend_instr; /**< Erase suspend instruction code */ + uint8_t resume_instr; /**< Erase resume instruction code */ + ospi_w_device_bus_mode suspend_bus_mode; /**< Bus mode during the erase suspend + * instruction phase */ + ospi_w_device_bus_mode resume_bus_mode; /**< Bus mode during the erase resume + * instruction phase */ + uint8_t read_stat_del; /**< The minimum time distance between the + * read status instruction and the previous + * erase or erase/resume instructions. + * 0: don't wait. The controller can read + * the memory status register immediately. + * 1..255 - the controller waits at least + * this number of OSPI_CLK cycles before + * reading the memory status register */ +} ospi_w_device_suspend_resume_instr_config_t; + +/* + * OSPI_W instructions configuration structure in auto access mode + */ +typedef struct +{ + ospi_w_device_read_instr_config_t read_instr_cfg; + ospi_w_device_wrap_burst_instr_config_t wrap_burst_instr_cfg; + ospi_w_device_erase_instr_config_t erase_instr_cfg; + ospi_w_device_read_status_config_t read_status_instr_cfg; + ospi_w_device_write_enable_instr_config_t write_enable_instr_cfg; + ospi_w_device_suspend_resume_instr_config_t suspend_resume_instr_cfg; +} ospi_w_device_instr_config_t; + +/* + * OSPI_W AES-CTR decryption configuration structure + */ +typedef struct +{ + uint8_t nonce[8]; /*!< AES-CTR decryption nonce value */ + uint8_t key[32]; /*!< AES-CTR decryption key value */ + uint32_t start_addr; /*!< AES-CTR decryption start address */ + uint32_t end_addr; /*!< AES-CTR decryption end address */ +} ospi_w_device_aes_ctr_config_t; + +/* + * Size of Burst Break Sequence + * + */ +typedef enum +{ + OSPI_W_DEVICE_BREAK_SEQ_SIZE_1B = 0, /* One byte */ + OSPI_W_DEVICE_BREAK_SEQ_SIZE_2B = 1 /* Two bytes */ +} ospi_w_device_break_seq_size; + +/* + * Type of QSPI_CLK edge producing the QSPI_CS signal + * + */ +typedef enum +{ + OSPI_W_DEVICE_CS_MODE_RISING = 0, /* The QSPI_CS is produced with the rising edge of the QSPI_SCK */ + OSPI_W_DEVICE_CS_MODE_FALLING = 1 /* The QSPI_CS is produced with the falling edge of the QSPI_SCK */ +} ospi_w_device_cs_mode; + +/* OSPI Flash chip select */ +typedef enum e_ospi_w_chip_select +{ + OSPI_W_DEVICE_NUMBER_0 = 0U, ///< Device connected to Chip-Select 0 +} ospi_w_device_number_t; + +/* OSPI flash number of command code bytes. */ +typedef enum e_ospi_w_command_bytes +{ + OSPI_W_COMMAND_BYTES_1 = 1U, ///< Command codes are 1 byte long. + OSPI_W_COMMAND_BYTES_2 = 2U, ///< Command codes are 2 bytes long. +} ospi_w_command_bytes_t; + +/* OSPI frame to frame interval */ +typedef enum e_ospi_w_frame_interval_clocks +{ + OSPI_W_COMMAND_INTERVAL_CLOCKS_1 = 0U, ///< 1 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_2, ///< 2 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_3, ///< 3 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_4, ///< 4 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_5, ///< 5 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_6, ///< 6 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_7, ///< 7 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_8, ///< 8 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_9, ///< 9 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_10, ///< 10 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_11, ///< 11 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_12, ///< 12 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_13, ///< 13 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_14, ///< 14 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_15, ///< 15 interval clocks + OSPI_W_COMMAND_INTERVAL_CLOCKS_16, ///< 16 interval clocks +} ospi_w_command_interval_clocks_t; + +/* OSPI chip select de-assertion duration */ +typedef enum e_ospi_w_cs_pullup_clocks +{ + OSPI_W_COMMAND_CS_PULLUP_CLOCKS_NO_EXTENSION = 0U, ///< CS asserting No extension + OSPI_W_COMMAND_CS_PULLUP_CLOCKS_1, ///< CS asserting Extend 1 cycle +} ospi_w_command_cs_pullup_clocks_t; + +/* OSPI chip select assertion duration */ +typedef enum e_ospi_w_cs_pulldown_clocks +{ + OSPI_W_COMMAND_CS_PULLDOWN_CLOCKS_NO_EXTENSION = 0U, ///< CS negating No extension + OSPI_W_COMMAND_CS_PULLDOWN_CLOCKS_1, ///< CS negating Extend 1 cycle +} ospi_w_command_cs_pulldown_clocks_t; + +/* Prefetch function settings */ +typedef enum e_ospi_w_prefetch_function +{ + OSPI_W_PREFETCH_FUNCTION_DISABLE = 0x00, // Prefetch function disable + OSPI_W_PREFETCH_FUNCTION_ENABLE = 0x01, // Prefetch function enable +} ospi_w_prefetch_function_t; + +/* Combination function settings */ +typedef enum e_ospi_w_combination_function +{ + OSPI_W_COMBINATION_FUNCTION_DISABLE = 0x00, // Combination function disable + OSPI_W_COMBINATION_FUNCTION_4BYTE = 0x01, // Combine up to 4 bytes + OSPI_W_COMBINATION_FUNCTION_8BYTE = 0x03, // Combine up to 8 bytes + OSPI_W_COMBINATION_FUNCTION_12BYTE = 0x05, // Combine up to 12 bytes + OSPI_W_COMBINATION_FUNCTION_16BYTE = 0x07, // Combine up to 16 bytes + OSPI_W_COMBINATION_FUNCTION_20BYTE = 0x09, // Combine up to 20 bytes + OSPI_W_COMBINATION_FUNCTION_24BYTE = 0x0B, // Combine up to 24 bytes + OSPI_W_COMBINATION_FUNCTION_28BYTE = 0x0D, // Combine up to 28 bytes + OSPI_W_COMBINATION_FUNCTION_32BYTE = 0x0F, // Combine up to 32 bytes + OSPI_W_COMBINATION_FUNCTION_36BYTE = 0x11, // Combine up to 36 bytes + OSPI_W_COMBINATION_FUNCTION_40BYTE = 0x13, // Combine up to 40 bytes + OSPI_W_COMBINATION_FUNCTION_44BYTE = 0x15, // Combine up to 44 bytes + OSPI_W_COMBINATION_FUNCTION_48BYTE = 0x17, // Combine up to 48 bytes + OSPI_W_COMBINATION_FUNCTION_52BYTE = 0x19, // Combine up to 52 bytes + OSPI_W_COMBINATION_FUNCTION_56BYTE = 0x1B, // Combine up to 56 bytes + OSPI_W_COMBINATION_FUNCTION_60BYTE = 0x1D, // Combine up to 60 bytes + OSPI_W_COMBINATION_FUNCTION_64BYTE = 0x1F, // Combine up to 64 bytes + OSPI_W_COMBINATION_FUNCTION_2BYTE = 0x1FF, // Combine up to 2 bytes +} ospi_w_combination_function_t; + +/* Memory mapped timing */ +typedef struct st_ospi_w_timing_setting +{ + ospi_w_command_interval_clocks_t command_to_command_interval; // Interval between 2 consecutive commands + ospi_w_command_cs_pullup_clocks_t cs_pullup_lag; // Duration to de-assert CS line after the last command + ospi_w_command_cs_pulldown_clocks_t cs_pulldown_lead; // Duration to assert CS line before the first command +} ospi_w_timing_setting_t; + +/** Command set used for a protocol mode other than normal (1S-1S-1S) SPI. */ +typedef struct st_ospi_w_xspi_command_set +{ + spi_flash_protocol_t protocol; ///< Protocol mode associated with this command set. + ospi_w_command_bytes_t command_bytes; ///< Number of command bytes for each command code. + uint16_t read_command; ///< Read command. + uint16_t page_program_command; ///< Page program/write command. + uint16_t write_enable_command; ///< Command to enable write or erase, set to 0x00 to ignore. + uint16_t status_command; ///< Command to read the write status, set to 0x00 to ignore. + uint8_t read_dummy_cycles; ///< Dummy cycles to be inserted for read commands. + uint8_t program_dummy_cycles; ///< Dummy cycles to be inserted for page program commands. + uint8_t status_dummy_cycles; ///< Dummy cycles to be inserted for status read commands. + uint8_t erase_command_list_length; ///< Length of erase command list + spi_flash_erase_command_t const * p_erase_command_list; ///< List of all erase commands and associated sizes +} ospi_w_xspi_command_set_t; + +/** OSPI_W Extended configuration. */ +typedef struct st_ospi_w_extended_cfg +{ + ospi_w_device_number_t channel; ///< Device number to be used for memory device + ospi_w_timing_setting_t const * p_timing_settings; ///< Memory-mapped timing settings. + ospi_w_xspi_command_set_t const * p_xspi_command_set_list; ///< Additional protocol command sets; if additional protocol commands set are not used set this to NULL. + uint8_t xspi_command_set_list_length; ///< Number of additional protocol command set defined. + uint8_t * p_autocalibration_preamble_pattern_addr; ///< OctaFlash memory address holding the preamble pattern + uint8_t data_latch_delay_clocks; ///< Specify delay between OM_DQS and OM_DQS Strobe. Set to 0 to auto-calibrate. Typical value is 0x80. +#if OSPI_W_CFG_DMAC_SUPPORT_ENABLE + transfer_instance_t const * p_lower_lvl_transfer; ///< DMA Transfer instance used for data transmission +#endif + ospi_w_device_config_t * p_ospi_w_device_cfg; ///< OSPI_W HW configuration. + ospi_w_device_read_instr_config_t * p_read_instr_cfg; ///< Automode read instruction configuration. + ospi_w_device_wrap_burst_instr_config_t * p_wrap_burst_instr_cfg; ///< Wrap burst instruction configuration. + ospi_w_device_read_status_config_t * p_read_status_instr_cfg; ///< Automode read status instruction configuration. + ospi_w_device_erase_instr_config_t * p_erase_instr_cfg; ///< Automode erase instruction configuration. + ospi_w_device_write_enable_instr_config_t * p_write_enable_instr_cfg; ///< Automode write enable instruction configuration. + ospi_w_device_suspend_resume_instr_config_t * p_suspend_resume_instr_cfg; ///< Automode suspend and resume instruction configuration. +} ospi_w_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_ospi_w_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; ///< Pointer to initial configuration + uint32_t open; ///< Whether or not driver is open + spi_flash_protocol_t spi_protocol; ///< Current OSPI protocol selected + ospi_w_device_number_t channel; ///< Device number to be used for memory device + ospi_w_xspi_command_set_t const * p_cmd_set; ///< Command set for the active protocol mode. +} ospi_w_instance_ctrl_t; + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IS_OSPI_W_DEVICE_BUS_MODE(x) (((x) == OSPI_W_DEVICE_BUS_MODE_SINGLE) || \ + ((x) == OSPI_W_DEVICE_BUS_MODE_DUAL) || \ + ((x) == OSPI_W_DEVICE_BUS_MODE_QUAD) || \ + ((x) == OSPI_W_DEVICE_BUS_MODE_OCTA)) + +#define IS_OSPI_W_DEVICE_EXTRA_BYTE(x) (((x) == OSPI_W_DEVICE_EXTRA_BYTE_DISABLE) || \ + ((x) == OSPI_W_DEVICE_EXTRA_BYTE_ENABLE)) + +#define IS_OSPI_W_DEVICE_EXTRA_BYTE_HALF(x) (((x) == OSPI_W_DEVICE_EXTRA_BYTE_HALF_DISABLE) || \ + ((x) == OSPI_W_DEVICE_EXTRA_BYTE_HALF_ENABLE)) + +#define IS_OSPI_W_DEVICE_INSTR_MODE_SEND(x) (((x) == OSPI_W_DEVICE_INSTR_MODE_SEND_ANYTIME) || \ + ((x) == OSPI_W_DEVICE_INSTR_MODE_SEND_ONCE)) + +#define IS_OSPI_W_DEVICE_IDLE_STATE_DURATION(x) (((x) == OSPI_W_DEVICE_IDLE_STATE_DURATION_0) || \ + ((x) == OSPI_W_DEVICE_IDLE_STATE_DURATION_1) || \ + ((x) == OSPI_W_DEVICE_IDLE_STATE_DURATION_2) || \ + ((x) == OSPI_W_DEVICE_IDLE_STATE_DURATION_3)) + +#define IS_OSPI_W_DEVICE_WRAP_MODE(x) (((x) == OSPI_W_DEVICE_WRAP_MODE_INSTR) || \ + ((x) == OSPI_W_DEVICE_WRAP_MODE_INSTR_WRAP)) + +#define IS_OSPI_W_DEVICE_WRAP_LEN(x) (((x) == OSPI_W_DEVICE_WRAP_LEN_4BEAT) || \ + ((x) == OSPI_W_DEVICE_WRAP_LEN_8BEAT) || \ + ((x) == OSPI_W_DEVICE_WRAP_LEN_16BEAT)) + +#define IS_OSPI_W_DEVICE_WRAP_SIZE(x) (((x) == OSPI_W_DEVICE_WRAP_SIZE_8BITS) || \ + ((x) == OSPI_W_DEVICE_WRAP_SIZE_16BITS) || \ + ((x) == OSPI_W_DEVICE_WRAP_SIZE_32BITS)) + +#define IS_OSPI_W_DEVICE_BUSY(x) (((x) == OSPI_W_DEVICE_BUSY_LOW) || \ + ((x) == OSPI_W_DEVICE_BUSY_HIGH)) + +#define IS_OSPI_W_DEVICE_READ_STATUS_REG_CNT(x) (((x) == OSPI_W_DEVICE_READ_STATUS_REG_CNT_RESSTS) || \ + ((x) == OSPI_W_DEVICE_READ_STATUS_REG_CNT_RESSUS)) + +#define IS_OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL(x) (((x) == OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL_UNCHANGED) || \ + ((x) == OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL_FORCED_ZERO)) + +/* Enable OQSPI controller clock */ +__STATIC_FORCEINLINE void r_ospi_w_device_clock_enable (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, OQSPIF_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/* + * Disable OQSPI controller clock + */ +__STATIC_FORCEINLINE void r_ospi_w_device_clock_disable (void) +{ + GLOBAL_INT_DISABLE(); + REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, OQSPIF_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/* + * Enable CS on OQSPI bus in manual access mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_cs_enable (void) +{ + REG_SET_BIT(OQSPIF, OQSPIF_CTRLBUS_REG, OSPIC_EN_CS); +} + +/* + * Disable CS on OQSPI bus in manual access mode. + */ +__STATIC_FORCEINLINE void r_ospi_w_device_cs_disable (void) +{ + REG_SET_BIT(OQSPIF, OQSPIF_CTRLBUS_REG, OSPIC_DIS_CS); +} + +/* + * Disable CS on OQSPI bus in manual access mode. + */ +__STATIC_FORCEINLINE void r_ospi_w_device_cs_toggle (void) +{ + REG_SET_BIT(OQSPIF, OQSPIF_CTRLBUS_REG, OSPIC_DIS_CS); + REG_SET_BIT(OQSPIF, OQSPIF_CTRLBUS_REG, OSPIC_EN_CS); +} + +/* + * Get OSPI_W Bus status + * + * see also ospi_w_device_BUS_STATUS + */ +__STATIC_FORCEINLINE ospi_w_device_bus_status r_ospi_w_device_get_bus_status (void) +{ + return (ospi_w_device_bus_status) REG_GETF(OQSPIF, OQSPIF_STATUS_REG, OSPIC_BUSY); +} + +/* + * Set OSPI_W clock divider + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_div (ospi_w_device_clk_div div) +{ + GLOBAL_INT_DISABLE(); + CRG_TOP->CLK_AMBA_REG_b.OQSPIF_DIV = div; + GLOBAL_INT_RESTORE(); +} + +/* + * Get OSPI_W clock divider + */ +__STATIC_FORCEINLINE ospi_w_device_clk_div r_ospi_w_device_get_div (void) +{ + return (ospi_w_device_clk_div) REG_GETF(CRG_TOP, CLK_AMBA_REG, OQSPIF_DIV); +} + +/* + * Set OSPI_W bus mode in manual mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_bus_mode (ospi_w_device_bus_mode bus_mode) +{ + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(bus_mode)); + OQSPIF->OQSPIF_CTRLBUS_REG = 1 << bus_mode; +} + +/* + * Get OSPI_W bus mode in manual mode + */ +__STATIC_FORCEINLINE ospi_w_device_bus_mode r_ospi_w_device_get_bus_mode (void) +{ + ospi_w_device_bus_mode ret_bus_mode; + uint32_t bus_mode_reg = OQSPIF->OQSPIF_CTRLBUS_REG; + ret_bus_mode = + (bus_mode_reg == + (0x01 << + OSPI_W_DEVICE_BUS_MODE_OCTA)) ? OSPI_W_DEVICE_BUS_MODE_OCTA : (ospi_w_device_bus_mode) (bus_mode_reg >> 1); + + return ret_bus_mode; +} + +/* + * Set OSPI_W access mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_access_mode (ospi_w_device_access_mode access_mode) +{ + OQSPIF->OQSPIF_CTRLMODE_REG_b.OSPIC_AUTO_MD = access_mode; +} + +/* + * Get OSPI_W access mode + */ +__STATIC_FORCEINLINE ospi_w_device_access_mode r_ospi_w_device_get_access_mode (void) +{ + return (ospi_w_device_access_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_AUTO_MD); +} + +/* + * Set OSPI_W clock mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_clock_mode (ospi_w_device_clk_mode clk_mode) +{ + ASSERT_WARNING(clk_mode == OSPI_W_DEVICE_CLK_MODE_LOW || clk_mode == OSPI_W_DEVICE_CLK_MODE_HIGH); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_CLK_MD, clk_mode); +} + +/* + * Get OSPI_W clock mode + */ +__STATIC_FORCEINLINE ospi_w_device_clk_mode r_ospi_w_device_get_clock_mode (void) +{ + return (ospi_w_device_clk_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_CLK_MD); +} + +/* + * Set OSPI_IO2 direction + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io2_direction (ospi_w_device_io_dir dir) +{ + ASSERT_WARNING(dir == OSPI_W_DEVICE_IO_DIR_AUTO_SEL || dir == OSPI_W_DEVICE_IO_DIR_OUTPUT); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_OEN, dir); +} + +/* + * Get OSPI_IO2 direction + */ +__STATIC_FORCEINLINE ospi_w_device_io_dir r_ospi_w_device_get_io2_direction (void) +{ + return (ospi_w_device_io_dir) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_OEN); +} + +/* + * Set OSPI_IO3 direction + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io3_direction (ospi_w_device_io_dir dir) +{ + ASSERT_WARNING(dir == OSPI_W_DEVICE_IO_DIR_AUTO_SEL || dir == OSPI_W_DEVICE_IO_DIR_OUTPUT); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_OEN, dir); +} + +/* + * Get OSPI_IO3 direction + */ +__STATIC_FORCEINLINE ospi_w_device_io_dir r_ospi_w_device_get_io3_direction (void) +{ + return (ospi_w_device_io_dir) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_OEN); +} + +/* + * Set OSPI_IO4 - OSPI_IO7 direction + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io4_7_direction (ospi_w_device_io_dir dir) +{ + ASSERT_WARNING(dir == OSPI_W_DEVICE_IO_DIR_AUTO_SEL || dir == OSPI_W_DEVICE_IO_DIR_OUTPUT); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN, dir); +} + +/* + * Get OSPI_IO4 - OSPI_IO7 direction + */ +__STATIC_FORCEINLINE ospi_w_device_io_dir r_ospi_w_device_get_io4_7_direction (void) +{ + return (ospi_w_device_io_dir) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN); +} + +/* + * Set the value of OSPI_IO2 pad when OSPI_IO2 direction is output + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io2_value (ospi_w_device_io_value value) +{ + ASSERT_WARNING(value == OSPI_W_DEVICE_IO_VALUE_LOW || value == OSPI_W_DEVICE_IO_VALUE_HIGH); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_DAT, (uint32_t) value); +} + +/* + * Get the value of OSPI_IO2 pad when OSPI_IO2 direction is output + */ +__STATIC_FORCEINLINE ospi_w_device_io_value r_ospi_w_device_get_io2_value (void) +{ + return (ospi_w_device_io_value) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_DAT); +} + +/* + * Set the value of OSPI_IO3 pad when OSPI_IO3 direction is output + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io3_value (ospi_w_device_io_value value) +{ + ASSERT_WARNING(value == OSPI_W_DEVICE_IO_VALUE_LOW || value == OSPI_W_DEVICE_IO_VALUE_HIGH); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_DAT, (uint32_t) value); +} + +/* + * Get the value of OSPI_IO3 pad when OSPI_IO3 direction is output + */ +__STATIC_FORCEINLINE ospi_w_device_io_value r_ospi_w_device_get_io3_value (void) +{ + return (ospi_w_device_io_value) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_DAT); +} + +/* + * Set the value of OSPI_IO4-7 pads when OSPI_IO4-7 direction is output + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_io4_7_value (ospi_w_device_io4_7_value value) +{ + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_DAT, (uint32_t) value); +} + +/* + * Get the value of OSPI_IO4-7 pad when OSPI_IO4-7 direction is output + */ +__STATIC_FORCEINLINE ospi_w_device_io4_7_value r_ospi_w_device_get_io4_7_value (void) +{ + return (ospi_w_device_io4_7_value) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_DAT); +} + +/* + * Set OSPI_W HReady signal mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_hready_mode (ospi_w_device_hready_mode mode) +{ + ASSERT_WARNING(mode == OSPI_W_DEVICE_HREADY_MODE_WAIT || mode == OSPI_W_DEVICE_HREADY_MODE_NO_WAIT); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_HRDY_MD, mode); +} + +/* + * Get OSPI_W HReady signal mode + */ +__STATIC_FORCEINLINE ospi_w_device_hready_mode r_ospi_w_device_get_hready_mode (void) +{ + return (ospi_w_device_hready_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_HRDY_MD); +} + +/* + * Set OSPI_W read sampling edge + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_read_sampling_edge (ospi_w_device_sampling_edge edge) +{ + ASSERT_WARNING(edge == OSPI_W_DEVICE_SAMPLING_EDGE_POS || edge == OSPI_W_DEVICE_SAMPLING_EDGE_NEG); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RXD_NEG, edge); +} + +/* + * Get OSPI_W read sampling edge + */ +__STATIC_FORCEINLINE ospi_w_device_sampling_edge r_ospi_w_device_get_read_sampling_edge (void) +{ + return (ospi_w_device_sampling_edge) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RXD_NEG); +} + +/* + * Set OSPI_W data read pipe status + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_read_pipe (ospi_w_device_read_pipe read_pipe) +{ + ASSERT_WARNING(read_pipe == OSPI_W_DEVICE_READ_PIPE_DISABLE || + read_pipe == OSPI_W_DEVICE_READ_PIPE_ENABLE); + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RPIPE_EN, read_pipe); +} + +/* + * Get OSPI_W read pipe status + */ +__STATIC_FORCEINLINE ospi_w_device_read_pipe r_ospi_w_device_get_read_pipe (void) +{ + return (ospi_w_device_read_pipe) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RPIPE_EN); +} + +/* + * Set the OSPI_W read pipe clock delay + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_read_pipe_clock_delay (ospi_w_device_read_pipe_delay delay) +{ + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_PCLK_MD, delay); +} + +/* + * Get OSPI_W read pipe clock delay + */ +__STATIC_FORCEINLINE ospi_w_device_read_pipe_delay r_ospi_w_device_get_read_pipe_clock_delay (void) +{ + return (ospi_w_device_read_pipe_delay) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_PCLK_MD); +} + +/* + * Set OSPI_W full buffer mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_full_buffer_mode (ospi_w_device_full_buffer_mode full_buffer_mode) +{ + ASSERT_WARNING(full_buffer_mode == OSPI_W_DEVICE_FULL_BUFFER_MODE_BLOCK || + full_buffer_mode == OSPI_W_DEVICE_FULL_BUFFER_MODE_TERMINATE); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_BUF_LIM_EN, full_buffer_mode); +} + +/* + * Get OSPI_W full buffer mode + */ +__STATIC_FORCEINLINE ospi_w_device_full_buffer_mode r_ospi_w_device_get_full_buffer_mode (void) +{ + return (ospi_w_device_full_buffer_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_BUF_LIM_EN); +} + +/* + * Set OSPI_W address size + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_address_size (ospi_w_device_addr_size size) +{ + ASSERT_WARNING(size == OSPI_W_DEVICE_ADDR_SIZE_24 || size == OSPI_W_DEVICE_ADDR_SIZE_32); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_USE_32BA, size); +} + +/* + * Get OSPI_W address size + */ +__STATIC_FORCEINLINE ospi_w_device_addr_size r_ospi_w_device_get_address_size (void) +{ + return (ospi_w_device_addr_size) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_USE_32BA); +} + +/* + * Set OSPI_W instruction size in auto mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_instruction_size (ospi_w_device_instruct_sz instruct_sz) +{ + ASSERT_WARNING(instruct_sz == OSPI_W_DEVICE_INSTRUCT_SZ_1_BYTE || + instruct_sz == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_CMD_X2_EN, instruct_sz); +} + +/* + * Get OSPI_W instruction size in auto mode + */ +__STATIC_FORCEINLINE ospi_w_device_instruct_sz r_ospi_w_device_get_instruction_size (void) +{ + return (ospi_w_device_instruct_sz) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_CMD_X2_EN); +} + +/* + * Set OSPI_W dummy mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_dummy_mode (ospi_w_device_dummy_mode dummy_mode) +{ + ASSERT_WARNING(dummy_mode == OSPI_W_DEVICE_DUMMY_MODE_LAST_CLK || + dummy_mode == OSPI_W_DEVICE_DUMMY_MODE_LAST_2_CLK); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_DMY_MD, dummy_mode); +} + +/* + * Get OSPI_W dummy mode + */ +__STATIC_FORCEINLINE ospi_w_device_dummy_mode r_ospi_w_device_get_dummy_mode (void) +{ + return (ospi_w_device_dummy_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_DMY_MD); +} + +/* + * Set OSPI_W direction change mode in manual access mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_dir_change_mode (ospi_w_device_dir_change_mode dir_change_mode) +{ + ASSERT_WARNING(dir_change_mode == OSPI_W_DEVICE_DIR_CHANGE_MODE_EACH_ACCESS || + dir_change_mode == OSPI_W_DEVICE_DIR_CHANGE_MODE_DUMMY_ACCESS); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_MAN_DIRCHG_MD, dir_change_mode); +} + +/* + * Get OSPI_W direction change mode in manual access mode + */ +__STATIC_FORCEINLINE ospi_w_device_dir_change_mode r_ospi_w_device_get_dir_change_mode (void) +{ + return (ospi_w_device_dir_change_mode) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_MAN_DIRCHG_MD); +} + +/* + * Set OSPI_W AHB bus error response when a read is performed in the address space + * where the flash device is mapped and the Auto mode is not enabled + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_mapped_addr_read_access_response ( + ospi_w_device_mapped_addr_rd_acc_response read_access_response) +{ + ASSERT_WARNING(read_access_response == OSPI_W_DEVICE_MAPPED_ADDR_RD_ACC_RESPONSE_IGNORE || + read_access_response == OSPI_W_DEVICE_MAPPED_ADDR_RD_ACC_RESPONSE_AHB_ERROR); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RD_ERR_EN, read_access_response); +} + +/* + * Get OSPI_W AHB bus error response when a read is performed in the address space + * where the flash device is mapped and the Auto mode is not enabled + */ +__STATIC_FORCEINLINE ospi_w_device_mapped_addr_rd_acc_response r_ospi_w_device_get_mapped_addr_read_access_response ( + void) +{ + return (ospi_w_device_mapped_addr_rd_acc_response) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RD_ERR_EN); +} + +/* + * Set OSPI_W burst length in auto mode when the read access in the AHB bus is an + * incremental burst of unspecified length + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_burst_len_limit (ospi_w_device_burst_len_limit burst_len_limit) +{ + ASSERT_WARNING(burst_len_limit == OSPI_W_DEVICE_BURST_LEN_LIMIT_UNSPECIFIED || + burst_len_limit == OSPI_W_DEVICE_BURST_LEN_LIMIT_8_BYTES); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_INC_LIM_EN, burst_len_limit); +} + +/* + * Get OSPI_W burst length in auto mode when the read access in the AHB bus is an + * incremental burst of unspecified length + */ +__STATIC_FORCEINLINE ospi_w_device_burst_len_limit ospi_w_device_get_burst_len_limit (void) +{ + return (ospi_w_device_burst_len_limit) REG_GETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_INC_LIM_EN); +} + +/* + * Set slew rate of OSPI_W pads + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_slew_rate (ospi_w_device_slew_rate slew_rate) +{ + REG_SETF(OQSPIF, OQSPIF_GP_REG, OSPIC_PADS_SLEW, slew_rate); +} + +/* + * Get slew rate of OSPI_W pads + */ +__STATIC_FORCEINLINE ospi_w_device_slew_rate r_ospi_w_device_get_slew_rate (void) +{ + return (ospi_w_device_slew_rate) REG_GETF(OQSPIF, OQSPIF_GP_REG, OSPIC_PADS_SLEW); +} + +/* + * Set drive current of OSPI_W pads + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_drive_current (ospi_w_device_drive_current drive_current) +{ + REG_SETF(OQSPIF, OQSPIF_GP_REG, OSPIC_PADS_DRV, drive_current); +} + +/* + * Get drive current of OSPI_W pads + */ +__STATIC_FORCEINLINE ospi_w_device_drive_current r_ospi_w_device_get_drive_current (void) +{ + return (ospi_w_device_drive_current) REG_GETF(OQSPIF, OQSPIF_GP_REG, OSPIC_PADS_DRV); +} + +/* + * Set the number of dummy bytes in auto access mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_dummy_bytes (uint8_t dummy_bytes) +{ + ASSERT_WARNING(dummy_bytes <= 32); + + if (dummy_bytes == 0) + { + REG_CLR_BIT(OQSPIF, OQSPIF_BURSTCMDB_REG, OSPIC_DMY_EN); + } + else + { + REG_SETF(OQSPIF, OQSPIF_BURSTCMDB_REG, OSPIC_DMY_NUM, (uint32_t) (dummy_bytes - 1)); + REG_SET_BIT(OQSPIF, OQSPIF_BURSTCMDB_REG, OSPIC_DMY_EN); + } +} + +/* + * Get the number of dummy bytes in auto access mode + */ +__STATIC_FORCEINLINE uint8_t r_ospi_w_device_get_dummy_bytes (void) +{ + if (REG_GETF(OQSPIF, OQSPIF_BURSTCMDB_REG, OSPIC_DMY_EN) == 0) + { + return 0; + } + else + { + return (uint8_t) (REG_GETF(OQSPIF, OQSPIF_BURSTCMDB_REG, OSPIC_DMY_NUM) + 1); + } +} + +/* + * Set the number of dummy bytes during the read status instruction in auto access mode + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_read_status_dummy_bytes (uint8_t dummy_bytes) +{ + ASSERT_WARNING(dummy_bytes <= 16); + + if (dummy_bytes == 0) + { + REG_CLR_BIT(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_EN); + } + else + { + REG_SETF(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_NUM, (uint32_t) (dummy_bytes - 1)); + REG_SET_BIT(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_EN); + } +} + +/* + * Get the number of dummy bytes during the read status instruction in auto access mode + */ +__STATIC_FORCEINLINE uint8_t r_ospi_w_device_get_read_status_dummy_bytes (void) +{ + if (REG_GETF(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_EN) == 0) + { + return 0; + } + else + { + return (uint8_t) (REG_GETF(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_NUM) + 1); + } +} + +/* + * Generate 32 bits data transfer from the external device to the OSPI_W (manual mode) + */ +__STATIC_FORCEINLINE uint32_t r_ospi_w_device_read32 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + + return ospi_w_regs->OQSPIF_READDATA_REG.data32; +} + +/* + * Generate 16 bits data transfer from the external device to the OSPI_W (manual mode) + */ +__STATIC_FORCEINLINE uint16_t r_ospi_w_device_read16 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + + return ospi_w_regs->OQSPIF_READDATA_REG.data16; +} + +/* + * Generate 8 bits data transfer from the external device to the OSPI_W (manual mode) + */ +__STATIC_FORCEINLINE uint8_t r_ospi_w_device_read8 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + + return ospi_w_regs->OQSPIF_READDATA_REG.data8; +} + +/* + * Generate 32 bits data transfer from the OSPI_W to the external device (manual mode) + */ +__STATIC_FORCEINLINE void r_ospi_w_device_write32 (uint32_t data) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_WRITEDATA_REG.data32 = SWAP32(data); +} + +/* + * Generate 16 bits data transfer from the OSPI_W to the external device (manual mode) + */ +__STATIC_FORCEINLINE void r_ospi_w_device_write16 (uint16_t data) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_WRITEDATA_REG.data32 = SWAP16(data); +} + +/* + * Generate 8 bits data transfer from the OSPI_W to the external device (manual mode) + */ +__STATIC_FORCEINLINE void r_ospi_w_device_write8 (uint8_t data) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_WRITEDATA_REG.data8 = data; +} + +/* + * Generate clock pulses on the SPI bus for a 32-bit transfer + */ +__STATIC_FORCEINLINE void r_ospi_w_device_dummy32 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_DUMMYDATA_REG.data32 = 0; +} + +/* + * Generate clock pulses on the SPI bus for a 16-bit transfer + */ +__STATIC_FORCEINLINE void r_ospi_w_device_dummy16 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_DUMMYDATA_REG.data16 = 0; +} + +/* + * Generate clock pulses on the SPI bus for an 8-bit transfer + */ +__STATIC_FORCEINLINE void r_ospi_w_device_dummy8 (void) +{ + ospi_w_regs_t * ospi_w_regs = (ospi_w_regs_t *) (OQSPIF_BASE); + ospi_w_regs->OQSPIF_DUMMYDATA_REG.data8 = 0; +} + +/* + * OQSPI controller initialization function + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_init(const ospi_w_device_config_t * cfg); + +/* + * Read the OSPI_W registers and save the current controller's configuration + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_get_config(ospi_w_device_config_t * cfg); + +__STATIC_FORCEINLINE void r_ospi_w_device_read_instr_init (const ospi_w_device_read_instr_config_t + * read_instr_cfg) +{ + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_instr_cfg->instr_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_instr_cfg->addr_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_instr_cfg->extra_byte_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_instr_cfg->dummy_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_instr_cfg->data_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_EXTRA_BYTE(read_instr_cfg->extra_byte_cfg)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_EXTRA_BYTE_HALF(read_instr_cfg->extra_byte_half_cfg)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_INSTR_MODE_SEND(read_instr_cfg->instr_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_IDLE_STATE_DURATION(read_instr_cfg->idle_state_duration)); + + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_INST = read_instr_cfg->instr; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_EXT_BYTE = read_instr_cfg->instr_extra_byte; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_INST_TX_MD = read_instr_cfg->instr_bus_mode; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_ADR_TX_MD = read_instr_cfg->addr_bus_mode; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_EXT_TX_MD = read_instr_cfg->extra_byte_bus_mode; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_DMY_TX_MD = read_instr_cfg->dummy_bus_mode; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_DAT_RX_MD = read_instr_cfg->data_bus_mode; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_EXT_BYTE_EN = read_instr_cfg->extra_byte_cfg; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_EXT_HF_DS = read_instr_cfg->extra_byte_half_cfg; + r_ospi_w_device_set_dummy_bytes(read_instr_cfg->dummy_bytes); + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_INST_MD = read_instr_cfg->instr_mode; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_CS_HIGH_MIN = read_instr_cfg->idle_state_duration; +} + +__STATIC_FORCEINLINE void r_ospi_w_device_wrap_burst_instr_init (const ospi_w_device_wrap_burst_instr_config_t + * wrap_burst_instr_cfg) +{ + ASSERT_WARNING(IS_OSPI_W_DEVICE_WRAP_MODE(wrap_burst_instr_cfg->mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_WRAP_LEN(wrap_burst_instr_cfg->len)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_WRAP_SIZE(wrap_burst_instr_cfg->size)); + + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_INST_WB = wrap_burst_instr_cfg->instr; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_WRAP_MD = wrap_burst_instr_cfg->mode; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_WRAP_LEN = wrap_burst_instr_cfg->len; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_WRAP_SIZE = wrap_burst_instr_cfg->size; +} + +__STATIC_FORCEINLINE void r_ospi_w_device_erase_instr_init (const ospi_w_device_erase_instr_config_t + * erase_instr_cfg) +{ + OQSPIF->OQSPIF_ERASECMDA_REG_b.OSPIC_ERS_INST = erase_instr_cfg->instr; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_ERS_TX_MD = erase_instr_cfg->instr_bus_mode; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_EAD_TX_MD = erase_instr_cfg->addr_bus_mode; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_ERSRES_HLD = (uint32_t) (erase_instr_cfg->hclk_cycles & 0x0f); + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_ERS_CS_HI = (uint32_t) (erase_instr_cfg->cs_hi_cycles & 0x1f); +} + +__STATIC_FORCEINLINE void r_ospi_w_device_read_status_instr_init (const ospi_w_device_read_status_config_t + * read_status_cfg) +{ + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_status_cfg->instr_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_status_cfg->receive_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(read_status_cfg->dummy_bus_mode)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUSY(read_status_cfg->busy_val)); + ASSERT_WARNING(read_status_cfg->busy_pos < 8); + ASSERT_WARNING(read_status_cfg->read_stat_del < 64); + ASSERT_WARNING(IS_OSPI_W_DEVICE_READ_STATUS_REG_CNT(read_status_cfg->read_stat_reg_cnt)); + ASSERT_WARNING(IS_OSPI_W_DEVICE_READ_STATUS_DUMMY_VAL(read_status_cfg->dummy_val)); + + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RSTAT_INST = read_status_cfg->instr; + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RSTAT_TX_MD = read_status_cfg->instr_bus_mode; + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RSTAT_RX_MD = read_status_cfg->receive_bus_mode; + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RSTAT_DMY_TX_MD = read_status_cfg->dummy_bus_mode; + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_BUSY_POS = (uint32_t) (read_status_cfg->busy_pos & 0x07); + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_BUSY_VAL = read_status_cfg->busy_val; + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RESSTS_DLY = (uint32_t) (read_status_cfg->read_stat_del & 0x3F); + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_STSDLY_SEL = (uint32_t) (read_status_cfg->read_stat_reg_cnt & 0x01); + r_ospi_w_device_set_read_status_dummy_bytes(read_status_cfg->dummy_bytes); + OQSPIF->OQSPIF_STATUSCMD_REG_b.OSPIC_RSTAT_DMY_ZERO = read_status_cfg->dummy_val; +} + +__STATIC_FORCEINLINE void r_ospi_w_device_write_enable_instr_init (const ospi_w_device_write_enable_instr_config_t + * write_enable_cfg) +{ + ASSERT_WARNING(IS_OSPI_W_DEVICE_BUS_MODE(write_enable_cfg->instr_bus_mode)); + + OQSPIF->OQSPIF_ERASECMDA_REG_b.OSPIC_WEN_INST = write_enable_cfg->instr; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_WEN_TX_MD = write_enable_cfg->instr_bus_mode; +} + +__STATIC_FORCEINLINE void r_ospi_w_device_suspend_resume_instr_init (const ospi_w_device_suspend_resume_instr_config_t + * suspend_resume_cfg) +{ + OQSPIF->OQSPIF_ERASECMDA_REG_b.OSPIC_SUS_INST = suspend_resume_cfg->suspend_instr; + OQSPIF->OQSPIF_ERASECMDA_REG_b.OSPIC_RES_INST = suspend_resume_cfg->resume_instr; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_SUS_TX_MD = suspend_resume_cfg->suspend_bus_mode; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_RES_TX_MD = suspend_resume_cfg->resume_bus_mode; + OQSPIF->OQSPIF_ERASECMDB_REG_b.OSPIC_RESSUS_DLY = suspend_resume_cfg->read_stat_del; +} + +/* + * OSPI_W instructions initialization function (auto access mode) + * + * Use this function in order to initialize/setup the internal finite state machine + * of the OSPI_W which is responsible for implementing the required protocol in auto + * access mode. Instantiate a type ospi_w_device_instr_config_t struct, initialize it with + * the desired OSPI_W settings and call this function passing the pointer of the + * struct as input argument. Before calling this function the OSPI_W has to be + * initialized in auto mode by calling the refer r_ospi_w_device_init. + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_instr_init(const ospi_w_device_instr_config_t * oqspi_instr_cfg); + +/* + * Set the address of the block/sector that is requested to be erased. + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_erase_address (uint32_t erase_addr) +{ + OQSPIF->OQSPIF_ERASECTRL_REG_b.OSPIC_ERS_ADDR = (uint32_t) (erase_addr & 0xFFFFF); +} + +/* + * Trigger erase block/sector + */ +__STATIC_FORCEINLINE void r_ospi_w_device_trigger_erase (void) +{ + OQSPIF->OQSPIF_ERASECTRL_REG_b.OSPIC_ERASE_EN = 1; +} + +/* + * Get erase status + */ +__STATIC_FORCEINLINE ospi_w_device_ers r_ospi_w_device_get_erase_status (void) +{ + // Dummy access to OQSPIF_CHCKERASE_REG in order to trigger a read status command + OQSPIF->OQSPIF_CHCKERASE_REG_b.OSPIC_CHCKERASE = 0; + + return (ospi_w_device_ers) OQSPIF->OQSPIF_ERASECTRL_REG_b.OSPIC_ERS_STATE; +} + +/* + * Disable the erase resume procedure. The erase will not be resumed after the + * expiration of the OSPIC_ERSRES_HLD unless re-enabling the corresponding setting by + * calling r_ospi_w_device_enable_erase_resume(). + */ +__STATIC_FORCEINLINE void r_ospi_w_device_disable_erase_resume (void) +{ + OQSPIF->OQSPIF_ERASECTRL_REG_b.OSPIC_ERS_RES_DIS = 1; +} + +/* + * Enable the erase resume procedure + */ +__STATIC_FORCEINLINE void r_ospi_w_device_enable_erase_resume (void) +{ + OQSPIF->OQSPIF_ERASECTRL_REG_b.OSPIC_ERS_RES_DIS = 0; +} + +/* + * Erase block/sector of flash memory + * + * Before erasing the flash memory, it is mandatory to set up the erase instructions + * first by calling r_ospi_w_device_erase_instr_init(). + * + * Call r_ospi_w_device_get_erase_status() to check whether the erase operation has finished. + * + * Before switching the OSPI controller to manual mode check that + * r_ospi_w_device_get_erase_status() == ospi_w_device_ERS_NO. + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_erase_block(uint32_t addr); + +/* + * Enable the AES-CTR decryption + */ +__STATIC_FORCEINLINE void r_ospi_w_device_enable_aes_ctr (void) +{ + OQSPIF->OQSPIF_CTR_CTRL_REG_b.OSPIC_CTR_EN = 1; + __ISB(); +} + +/* + * Disable the AES-CTR decryption + */ +__STATIC_FORCEINLINE void r_ospi_w_device_disable_aes_ctr (void) +{ + OQSPIF->OQSPIF_CTR_CTRL_REG_b.OSPIC_CTR_EN = 0; + __ISB(); +} + +/* + * Set the nonce value used by AES-CTR decryption algorithm + * + * The OQSPI controller decrypts Flash contents on-the-fly using AES-CTR. AES-CTR uses + * a 16-byte counter block (CTRB). The first 8 bytes of CTRB consist of the NONCE while + * the other 8-bytes are produced automatically by the hardware. + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_set_aes_ctr_nonce(const uint8_t * nonce); + +/* + * Set the key for AES-CTR decryption + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_set_aes_ctr_key(const uint8_t * key); + +/* + * Set the OQSPI flash memory address range where its contents will be decrypted + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_aes_ctr_addr_range (uint32_t saddr, uint32_t eaddr) +{ + ASSERT_ERROR((eaddr > (saddr + 0x3FF)) || ((eaddr == 0x0) && (saddr == 0x0))); + + REG_SETF(OQSPIF, OQSPIF_CTR_SADDR_REG, OSPIC_CTR_SADDR, saddr >> 10); + REG_SETF(OQSPIF, OQSPIF_CTR_EADDR_REG, OSPIC_CTR_EADDR, eaddr >> 10); +} + +/* + * OQSPI controller AES-CTR decryption initialization function + */ +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_aes_ctr_init(const ospi_w_device_aes_ctr_config_t * cfg); + +/* + * Set an extra byte to use with read instructions + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_extra_byte (uint8_t extra_byte, + ospi_w_device_bus_mode bus_mode, + bool half_disable_out) +{ + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_EXT_BYTE = extra_byte; + OQSPIF->OQSPIF_BURSTCMDA_REG_b.OSPIC_EXT_TX_MD = bus_mode; + + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_EXT_BYTE_EN = 1; + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_EXT_HF_DS = half_disable_out; +} + +/* + * Set the number of clocks cycles that CS stays high between the transmissions of two + * different instructions + */ +__STATIC_FORCEINLINE void r_ospi_w_device_set_min_cs_high (uint8_t clock_count) +{ + ASSERT_WARNING(clock_count < 8); + OQSPIF->OQSPIF_BURSTCMDB_REG_b.OSPIC_CS_HIGH_MIN = (uint32_t) (clock_count & 0x07); +} + +/* + * Enable burst break sequence + */ +__STATIC_FORCEINLINE void r_ospi_w_device_burst_break_sequence_enable (uint16_t sequence, + ospi_w_device_bus_mode mode, + ospi_w_device_break_seq_size size, + bool dis_out) +{ + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_SEC_HF_DS = dis_out; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_SZ = size; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_TX_MD = mode; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_EN = 1; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_WRD = sequence; +} + +/* + * Disable burst break sequence + * + */ +__STATIC_FORCEINLINE void r_ospi_w_device_burst_break_sequence_disable (void) +{ + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_EN = 0; +} + +/* + * Defines the behavior of the controller when the internal buffer is full + * and there are more data to be retrieved for the current burst. + * It has meaning only for reads in auto mode. + */ +__STATIC_FORCEINLINE void r_ospi_w_device_buf_lim (bool enable) +{ + OQSPIF->OQSPIF_CTRLMODE_REG_b.OSPIC_BUF_LIM_EN = enable; +} + +/* + * Fast copy of a buffer to a FIFO + * Implementation of a fast copy of the contents of a buffer to a FIFO in assembly. All + * addresses are word aligned. + */ +__STATIC_FORCEINLINE void fast_write_to_fifo32 (uint32_t start, uint32_t end, uint32_t dest) +{ + __asm__ volatile ( "copy: \n" + " ldmia %[start]!, {r3} \n" + " str r3, [%[dest]] \n" + " cmp %[start], %[end] \n" + " blt copy \n" + : + : /* output */ + [start] "l" (start), [end] "r" (end), [dest] "l" (dest) : /* inputs (%0, %1, %2) */ + "r3"); /* registers that are destroyed */ +} + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern spi_flash_api_t g_ospi_w_on_spi_flash; + +/** @endcond */ +fsp_err_t R_OSPI_W_Open(spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg); +fsp_err_t R_OSPI_W_Close(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_W_DirectWrite(spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +fsp_err_t R_OSPI_W_DirectRead(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_OSPI_W_DirectTransfer(spi_flash_ctrl_t * const p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +fsp_err_t R_OSPI_W_SpiProtocolSet(spi_flash_ctrl_t * const p_ctrl, spi_flash_protocol_t spi_protocol); +fsp_err_t R_OSPI_W_XipEnter(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_W_XipExit(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_W_Write(spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +fsp_err_t R_OSPI_W_Erase(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); +fsp_err_t R_OSPI_W_StatusGet(spi_flash_ctrl_t * const p_ctrl, spi_flash_status_t * const p_status); +fsp_err_t R_OSPI_W_BankSet(spi_flash_ctrl_t * const _ctrl, uint32_t bank); +fsp_err_t R_OSPI_W_AutoCalibrate(spi_flash_ctrl_t * const p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup OSPI_W) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_qspi_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_qspi_w.h new file mode 100644 index 000000000000..9e2663cc7378 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_qspi_w.h @@ -0,0 +1,521 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_QSPI_W_H +#define R_QSPI_W_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_qspi_w_cfg.h" +#include "r_spi_flash_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup QSPI_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define QSPI_W_DEVICE_START_ADDRESS (BSP_FEATURE_QSPI_DEVICE_START_ADDRESS) +#define QSPI_W_DEVICE_START_ADDRESS_DATA (BSP_FEATURE_QSPI_DEVICE_START_ADDRESS_DATA) + +/* If Code Flash programming is enabled, then all API functions must execute out of RAM. */ +#define PLACE_IN_RAM_SECTION + +/* TODO: This needs to be added in r_spi_flash_api.h in the next FSP API Release */ +#define SPI_FLASH_DUMMY_CLOCKS_32 (32) ///< 32 dummy clocks + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Cache control. */ +typedef enum e_qspi_w_dcache +{ + QSPI_W_DCACHE_DISABLE, ///< Disable dcache. + QSPI_W_DCACHE_ENABLE, ///< Enable dcache. +} qspi_w_dcache_t; + +/** QSPI_W memory access mode. */ +typedef enum e_qspi_w_access_mode +{ + QSPI_W_ACCESS_MODE_MANUAL = 0, ///< Direct register access using the QSPI_W register file. + QSPI_W_ACCESS_MODE_AUTO = 1, ///< Up to 32 MB memory-mapped access with 3- and 4-byte addressing modes. +} qspi_w_access_mode_t; + +/** QSPI_W Bus mode. */ +typedef enum e_qspi_w_bus_mode +{ + QSPI_W_BUS_MODE_SINGLE, ///< Bus mode in single mode. + QSPI_W_BUS_MODE_DUAL, ///< Bus mode in dual mode. + QSPI_W_BUS_MODE_QUAD, ///< Bus mode in quad mode. +} qspi_w_bus_mode_t; + +/** QSPCLK divider. */ +typedef enum e_qspi_w_qspclk_div +{ + QSPI_W_QSPCLK_DIV_1 = 0x0, ///< QSPI_CLK = SYS_CLK / 1 + QSPI_W_QSPCLK_DIV_2 = 0x1, ///< QSPI_CLK = SYS_CLK / 2 +#if defined(BSP_MCU_GROUP_RA6W1) + QSPI_W_QSPCLK_DIV_4 = 0x2, ///< QSPI_CLK = SYS_CLK / 4 + QSPI_W_QSPCLK_DIV_8 = 0x3, ///< QSPI_CLK = SYS_CLK / 8 +#endif +} qspi_w_qspclk_div_t; + +/** The progress of sector/block erasing. */ +typedef enum e_qspi_w_ers +{ + QSPI_W_ERS_NO = 0, ///< No erase. + QSPI_W_ERS_PENDING = 1, ///< Pending erase request. + QSPI_W_ERS_RUNNING = 2, ///< Erase procedure is running. + QSPI_W_ERS_SUSPENDED = 3, ///< Suspended erase procedure. + QSPI_W_ERS_FINISHING = 4, ///< Finishing the erase procedure. +} qspi_w_ers_t; + +/** QSPI clock mode. */ +typedef enum e_qspi_w_clk_mode +{ + QSPI_W_CLK_MODE_LOW = 0, ///< Mode 0: QSPI_SCK is low when QSPI_CS is high. + QSPI_W_CLK_MODE_HIGH = 1, ///< Mode 3: QSPI_SCK is high when QSPI_CS is high. +} qspi_w_clk_mode_t; + +/** QSPIC pads drive current strength. */ +typedef enum e_qspi_w_drive_current +{ +#if defined(BSP_MCU_GROUP_RA6W1) + QSPI_W_DRIVE_CURRENT_2 = 0, ///< 2 mA. + QSPI_W_DRIVE_CURRENT_4 = 1, ///< 4 mA. + QSPI_W_DRIVE_CURRENT_8 = 2, ///< 8 mA. + QSPI_W_DRIVE_CURRENT_14 = 3, ///< 14 mA. +#else + QSPI_W_DRIVE_CURRENT_4 = 0, ///< 4 mA. + QSPI_W_DRIVE_CURRENT_8 = 1, ///< 8 mA. + QSPI_W_DRIVE_CURRENT_12 = 2, ///< 12 mA. + QSPI_W_DRIVE_CURRENT_16 = 3, ///< 16 mA. +#endif +} qspi_w_drive_current_t; + +/** + * QSPIC read pipe setting. + * + * When read pipe is disabled the sampling clock is determined by QSPI_W_SAMPLING_EDGE + * otherwise by QSPI_W_READ_PIPE_DELAY. + */ +typedef enum e_qspi_w_read_pipe +{ + QSPI_W_READ_PIPE_DISABLE = 0, ///< Disable read pipe delay. + QSPI_W_READ_PIPE_ENABLE = 1, ///< Enable read pipe delay. +} qspi_w_read_pipe_t; + +/** + * QSPIC Read pipe clock delay in relation to the falling edge of QSPI_SCK. + * + * The read pipe delay should be set based on the voltage level of the power rail V12. + */ +typedef enum e_qspi_w_read_pipe_delay +{ + QSPI_W_READ_PIPE_DELAY_0 = 0, ///< Set read pipe delay to 0. + QSPI_W_READ_PIPE_DELAY_1 = 1, ///< Set read pipe delay to 1. + QSPI_W_READ_PIPE_DELAY_2 = 2, ///< Set read pipe delay to 2. + QSPI_W_READ_PIPE_DELAY_3 = 3, ///< Set read pipe delay to 3. + QSPI_W_READ_PIPE_DELAY_4 = 4, ///< Set read pipe delay to 4. + QSPI_W_READ_PIPE_DELAY_5 = 5, ///< Set read pipe delay to 5. + QSPI_W_READ_PIPE_DELAY_6 = 6, ///< Set read pipe delay to 6. + QSPI_W_READ_PIPE_DELAY_7 = 7, ///< Set read pipe delay to 7. +} qspi_w_read_pipe_delay_t; + +/** QSPIC pads slew rate. */ +typedef enum e_qspi_w_slew_rate +{ +#if defined(BSP_MCU_GROUP_RA6W3) + QSPI_W_SLEW_RATE_0 = 0, ///< Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak). + QSPI_W_SLEW_RATE_1 = 1, ///< Rise = 2.0 V/ns, Fall = 2.3 V/ns. + QSPI_W_SLEW_RATE_2 = 2, ///< Rise = 2.3 V/ns, Fall = 2.6 V. + QSPI_W_SLEW_RATE_3 = 3, ///< Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong) +#else + QSPI_W_SLEW_RATE_FAST = 0, ///< Fast Slew Rate. + QSPI_W_SLEW_RATE_SLOW = 1, ///< Slower Slew Rate. +#endif +} qspi_w_slew_rate_t; + +/** + * QSPIC HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers. + * + * This configuration is useful when the frequency of the QSPI clock is much lower than + * the clock of the AMBA bus, in order to avoid locking the AMBA bus for a long time. + * When is set to QSPI_W_HREADY_MODE_WAIT there is no need to check the QSPIC_BUSY + * for detecting completion of the requested access. + */ +typedef enum e_qspi_w_hready_mode +{ + QSPI_W_HREADY_MODE_WAIT = 0, ///< Adds wait states via hready signal when accessing the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. + QSPI_W_HREADY_MODE_NO_WAIT = 1, ///< Don't add wait states via the HREADY signal. +} qspi_w_hready_mode_t; + +/** QSPIC instruction mode. */ +typedef enum e_qspi_w_instr_md +{ + QSPI_W_INSTR_MD_TX_AT_ANY_BURST_ACCESS = 0, ///< Transmit instruction at any burst access. + QSPI_W_INSTR_MD_TX_ONLY_IN_FIRST_ACCESS = 1, ///< Transmit instruction only in the first access after the selection of Auto Mode. +} qspi_w_instr_md_t; + +/** QSPIC wrap mode enable bit. */ +typedef enum e_qspi_w_wrap_md +{ + QSPI_W_WRAP_MD_SEL_INSTR = 0, ///< The QSPIC_INST is the selected instruction at any read access. + QSPI_W_WRAP_MD_SEL_INSTR_WB = 1, ///< The QSPIC_INST_WB is the selected instruction at any read wrapping burst access. +} qspi_w_wrap_md_t; + +/** QSPIC write wrapping burst will be implemented by using a special write instruction. */ +typedef enum e_qspi_w_wrap_wr_en +{ + QSPI_W_WRAP_WR_EN_INST = 0, ///< Select QSPIC_WR_INST. + QSPI_W_WRAP_WR_EN_INST_WB = 1, ///< Select QSPIC_WR_INST_WB. +} qspi_w_wrap_wr_en_t; + +/** QSPIC behavior when a read burst is terminated early in the AMBA bus. */ +typedef enum e_qspi_w_rd_bend_md +{ + QSPI_W_RD_BEND_MD_TERMINATE_ASAP = 0, ///< The corresponding read burst in the memory device will be terminated as soon as possible, based on the pipeline of the controller. + QSPI_W_RD_BEND_MD_TERMINATE_WHEN_DONE = 1, ///< The read burst in the memory device will be terminated only after filling the last position of the current read buffer. +} qspi_w_rd_bend_md_t; + +/** Set the read pipeline in burst mode while retrieving the data of the memory device. */ +typedef enum e_qspi_w_rd_rdb_en +{ + QSPI_W_RD_RDB_EN_MIN_CLK_PULSES = 0, ///< The controller will provide the minimum required number of clock pulses in the interface during the reading of the data. + QSPI_W_RD_RDB_EN_UNTIL_DONE = 1, ///< Set the read pipeline in burst mode while the data are retrieved of the memory device. +} qspi_w_rd_rdb_en_t; + +/** QSPIC extra byte setting in auto access mode. */ +typedef enum e_qspi_w_extra_byte +{ + QSPI_W_EXTRA_BYTE_DISABLE = 0, ///< Disable extra byte phase. + QSPI_W_EXTRA_BYTE_ENABLE = 1, ///< Enable extra byte phase. +} qspi_w_extra_byte_t; + +/** + * QSPIC extra byte half setting in auto access mode. + * + * This setting is out of scope if the extra byte is disabled. + */ +typedef enum e_qspi_w_extra_byte_half +{ + QSPI_W_EXTRA_BYTE_HALF_DISABLE = 0, ///< Transmit the complete extra byte. + QSPI_W_EXTRA_BYTE_HALF_ENABLE = 1, ///< The output switches to Hi-Z during the transmission of the low nibble of the extra byte. +} qspi_w_extra_byte_half_t; + +/** QSPIC break enable/disable. */ +typedef enum e_qspi_w_break +{ + QSPI_W_BREAK_DISABLE = 0, ///< Disable break command. + QSPI_W_BREAK_ENABLE = 1, ///< Enable break command. +} qspi_w_break_t; + +/** + * QSPIC Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0]). + * + * Setting this bit is only useful if QSPIC_BRK_EN =1 and QSPIC_BRK_SZ= 1. + */ +typedef enum e_qspi_w_break_sec_hf +{ + QSPI_W_BREAK_SEC_HF_DRIVE = 0, ///< The controller drives the SPI bus during the transmission of the QSPIC_BRK_WRD[3:0]. + QSPI_W_BREAK_SEC_HF_HIZ = 1, ///< The controller leaves the SPI bus in Hi-Z during the transmission of the QSPIC_BRK_WORD[3:0]. +} qspi_w_break_sec_hf_t; + +/** QSPIC tCEM enable/disable. */ +typedef enum e_qspi_w_t_cem +{ + QSPI_W_T_CEM_DISABLE = 0, ///< Disable tCEM control. + QSPI_W_T_CEM_ENABLE = 1, ///< Enable tCEM control. +} qspi_w_t_cem_t; + +/** Length of a burst operation for a QSPI RAM device. */ +typedef enum e_qspi_w_memblen_burst +{ + QSPI_W_MEMBLEN_BURST_INCR_UNSPECIFIED = 0, ///< The external memory device implements incremental burst of unspecified length. + QSPI_W_MEMBLEN_BURST_WRAP_4B, ///< The external memory device implements a wrapping burst of length 4 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_8B, ///< The external memory device implements a wrapping burst of length 8 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_16B, ///< The external memory device implements a wrapping burst of length 16 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_32B, ///< The external memory device implements a wrapping burst of length 32 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_64B, ///< The external memory device implements a wrapping burst of length 64 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_128B, ///< The external memory device implements a wrapping burst of length 128 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_256B, ///< The external memory device implements a wrapping burst of length 256 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_512B, ///< The external memory device implements a wrapping burst of length 512 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_1024B, ///< The external memory device implements a wrapping burst of length 1024 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_2048B, ///< The external memory device implements a wrapping burst of length 2048 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_4096B, ///< The external memory device implements a wrapping burst of length 4096 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_8192B, ///< The external memory device implements a wrapping burst of length 8192 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_16384B, ///< The external memory device implements a wrapping burst of length 16384 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_32768B, ///< The external memory device implements a wrapping burst of length 32768 bytes. + QSPI_W_MEMBLEN_BURST_WRAP_65536B, ///< The external memory device implements a wrapping burst of length 65536 bytes. +} qspi_w_memblen_burst_t; + +/** + * QSPI clock edge setting for the sampling of the incoming data when the read pipe is disabled. + */ +typedef enum e_qspi_w_sampling_edge +{ + QSPI_W_SAMPLING_EDGE_POS = 0, ///< The incoming data sampling is triggered by the positive edge of QSPI clock signal. + QSPI_W_SAMPLING_EDGE_NEG = 1, ///< The incoming data sampling is triggered by the negative edge of QSPI clock signal. +} qspi_w_sampling_edge_t; + +/** QSPI DDR or SDR mode. */ +typedef enum e_qspi_w_mode +{ + QSPI_W_MODE_DDR = 0, ///< QSPI DDR (double data rate) mode. + QSPI_W_MODE_SDR = 1, ///< QSPI SDR (single data rate) mode. +} qspi_w_mode_t; + +/** QSPI device busy status setting. */ +typedef enum e_qspi_w_busy_level +{ + QSPI_W_BUSY_LEVEL_LOW = 0, ///< The QSPI device is busy when the pin level bit is low. + QSPI_W_BUSY_LEVEL_HIGH = 1, ///< The QSPI device is busy when the pin level bit is high. +} qspi_w_busy_level_t; + +/** + * QSPIC timer which is used to count the delay that it has to wait before to read the Flash status register, + * after an erase or an erase resume command. + */ +typedef enum e_qspi_w_stsdly_sel +{ + QSPI_W_STSDLY_SEL_RESSTS_DLY = 0, ///< The delay is controlled by the QSPIC_RESSTS_DLY which counts on the QSPI_SCK clock. + QSPI_W_STSDLY_SEL_RESSUS_DLY = 1, ///< The delay is controlled by the QSPIC_RESSUS_DLY which counts on the 222 kHz clock. +} qspi_w_stsdly_sel_t; + +/** QSPIC value that is transferred on the SPI bus during the phase of the dummy bytes. */ +typedef enum e_qspi_w_dummy_value +{ + QSPI_W_RSTAT_DMY_ZERO_KEEP_UNCHANGED = 0, ///< The controller keeps the data in the bus unchanged, until to change the bus direction in input mode. + QSPI_W_RSTAT_DMY_ZERO_FORCE_ZERO = 1, ///< Forces the dummy bytes to get the zero value (only for the cycles that are not in input mode). +} qspi_w_dummy_value_t; + +/** Read instruction configuration structure (auto access mode). */ +typedef struct st_qspi_w_read_instr_cfg +{ + uint8_t opcode; ///< Read command opcode for Incremental Burst or Single read access. + uint8_t opcode_wb; ///< Read command opcode for Wrapping Burst. + uint8_t extra_byte_value; ///< Extra Byte value. + qspi_w_bus_mode_t opcode_bus_mode : 2; ///< Bus mode of the opcode phase. + qspi_w_bus_mode_t addr_bus_mode : 2; ///< Bus mode of the address phase. + qspi_w_bus_mode_t extra_byte_bus_mode : 2; ///< Bus mode of the extra byte phase. + qspi_w_bus_mode_t dummy_bus_mode : 2; ///< Bus mode of the dummy phase. + + qspi_w_bus_mode_t data_bus_mode : 2; ///< Bus mode of the data phase. + qspi_w_extra_byte_t extra_byte_en : 1; ///< Enable Extra Byte. + qspi_w_extra_byte_half_t extra_byte_half_cfg : 1; ///< Enable Extra Byte Half. + uint8_t dummy_bytes : 5; ///< The number of dummy bytes. Valid values are 0..31 i.e. 1..32 dummy bytes. + bool dummy_en; ///< Enable dummy bytes. + bool dummy_force; ///< On setting this bit the no: of dummy bytes is set to 3 always irrespective of value provided in dummy_bytes. + qspi_w_instr_md_t instr_md : 1; ///< Instruction mode. + qspi_w_wrap_md_t wrap_md : 1; ///< Wrap mode enable bit. + uint8_t wrap_blen : 3; ///< It describes the length in number of bytes of the selected wrapping burst(see also the register QSPIC_WRAP_MD). + uint8_t wrap_size : 2; ///< Selected data size of a wrapping burst. + qspi_w_wrap_wr_en_t wrap_wr_en : 1; ///< By setting (1) this bit, any write wrapping burst will be implemented by using a special write instruction. + uint8_t cs_high_min_cycles : 5; ///< The SPI bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles between two consecutive read commands. + qspi_w_rd_bend_md_t rd_bend_md : 1; ///< Defines the behavior of the controller when a read burst is terminated early in the AMBA bus. + qspi_w_rd_rdb_en_t rd_rdb_en : 1; ///< Write 1 to set the read pipeline in burst mode while are retrieved the data of the memory device. +} qspi_w_read_instr_cfg_t; + +/** QSPIC read status instruction configuration structure (auto access mode). */ +typedef struct st_qspi_w_read_status_instr_cfg +{ + uint8_t opcode; ///< Read Status command opcode. + qspi_w_bus_mode_t opcode_bus_mode : 2; ///< The bus mode of the opcode phase. + qspi_w_bus_mode_t receive_bus_mode : 2; ///< The bus mode of the receive data phase. + uint32_t busy_pos : 3; ///< The position of the Busy bit in the status register (0 - 7). + uint8_t delay_cycles : 7; ///< The minimum delay in clock cycles between a Read Status command and the previous Erase command. Usually NOT needed thus is set equal to 0. + qspi_w_stsdly_sel_t stsdly_sel : 1; ///< Select the timer which is used to count the delay before reading the flash status register, after an erase or an erase resume command. + qspi_w_busy_level_t busy_level : 1; ///< Busy bit level. + uint8_t rstat_dmy_num : 4; ///< Number of dummy bytes (minus 1). + qspi_w_bus_mode_t dummy_bus_mode : 2; ///< The bus mode of the dummy data phase. + qspi_w_dummy_value_t dummy_value : 1; ///< Define the value that is transferred on the SPI bus during the phase of the dummy bytes. + bool rstat_dmy_en; ///< Enables the transmission of dummy bytes, immediately after the instruction code of the read status command. + bool rstat_rdb_en; ///< If enabled, sets the read pipeline in burst mode while is retrieved the status of the memory device. + bool rstat_split_en; ///< If enabled, a long sequence for the continuous reading of the status register will be divided into individual accesses. + bool rstat_req; ///< If enabled, the value of the status register of the memory device will be retrieved. +} qspi_w_read_status_instr_cfg_t; + +/** QSPIC Erase instruction configuration structure (auto access mode). */ +typedef struct st_qspi_w_erase_instr_cfg +{ + qspi_w_bus_mode_t opcode_bus_mode : 2; ///< Bus mode of the opcode phase. + qspi_w_bus_mode_t addr_bus_mode : 2; ///< Bus mode of the address phase. + uint32_t hclk_cycles : 4; ///< The number of AMBA AHB hclk cycles (0..15) without memory read requests before executing an erase or erase resume command. Use this setting to delay one of the aforementioned commands otherwise keep it 0. + uint8_t opcode; ///< Erase command opcode. + uint8_t cs_idle_delay_cycles : 5; ///< The minimum CS idle delay in clock cycles (< 32) between a Write Enable, Erase, Erase Suspend or Erase Resume command and the next consecutive command. +} qspi_w_erase_instr_cfg_t; + +/** QSPIC Erase suspend/resume instruction structure (auto access mode). */ +typedef struct st_qspi_w_suspend_resume_instr_cfg +{ + qspi_w_bus_mode_t suspend_bus_mode : 2; ///< Bus mode during the erase suspend command phase. + qspi_w_bus_mode_t resume_bus_mode : 2; ///< Bus mode during the erase resume command phase. + uint8_t suspend_opcode; ///< Erase suspend instruction code. + uint8_t resume_opcode; ///< Erase resume instruction code. + uint8_t res_sus_latency_clk_cycles : 6; ///< The minimum required latency (clock cycles) between an erase resume and the next consequent erase suspend command. + uint8_t sussts_dly : 6; ///< Defines a timer that counts the minimum allowed delay between an erase suspend command and the next read status command. +} qspi_w_suspend_resume_instr_cfg_t; + +/** QSPIC Read break sequence structure (auto access mode). */ +typedef struct st_qspi_w_break_instr_cfg +{ + uint16_t break_opcode; ///< The code value of the read break instruction. + uint8_t break_sz : 4; ///< The size of Burst Break Sequence 1..16 bytes. + qspi_w_bus_mode_t break_tx_md : 2; ///< The mode of the QSPI Bus during the transmission of the burst break sequence. + qspi_w_break_sec_hf_t break_sec_hf : 1; ///< Disable output during the transmission of the second half. + qspi_w_break_t break_en : 1; ///< Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode. +} qspi_w_break_instr_cfg_t; + +/** QSPIC External memory burst length configuration. */ +typedef struct st_qspi_w_memblen_cfg +{ + qspi_w_memblen_burst_t memblen : 4; ///< In this register is defined the expected behavior of the external memory device regarding the length of a burst operation. + uint16_t tcem_cc : 12; ///< Defines the maximum allowed time tCEM for which the QSPIC_CS can stay active (when tcem_en=1). + qspi_w_t_cem_t tcem_en : 1; ///< This bit enables the controlling of the maximum time tCEM for which the QSPI_CS remains active (auto mode and PSRAM). + bool rd_lin_en : 1; ///< By setting (1) in this bit the access limits that are set with the QSPIC_MEMBLEN are ignored for the read operation. + bool keep_active : 1; ///< By setting (1) in this bit the controller will keep the access active in order to serve consecutive accesses, without toggling the chip select of the memory,when this is possible. + bool wcmd_hybrid : 1; ///< By setting (1) in this bit, the special commands that used during wrap bursts. + uint8_t dielen : 4; ///< The size of each die from which the memory device is consisted. + uint8_t active_thr : 4; ///< Defines the maximum number of AHB clock cycles for which the memory should stay without access, before the active access to be aborted. +} qspi_w_memblen_cfg_t; + +/** QSPIC Write instruction structure (manual & auto access mode). */ +typedef struct st_qspi_w_write_instr_cfg +{ + uint8_t write_opcode; ///< The code value of the write instruction. + uint8_t write_opcode_wb; ///< The code value of the write instruction in wrapping burst. + qspi_w_bus_mode_t opcode_bus_mode : 2; ///< Bus mode of the opcode phase. + qspi_w_bus_mode_t addr_bus_mode : 2; ///< Bus mode of the address phase. + qspi_w_bus_mode_t data_bus_mode : 2; ///< Bus mode of the data phase. + qspi_w_bus_mode_t dummy_bus_mode : 2; ///< Bus mode of the dummy data phase. + uint8_t dummy_bytes : 5; ///< The number of dummy bytes. Valid values are 0..31 i.e. 1..32 dummy bytes. + bool dummy_en; ///< Enable dummy bytes. + bool wdex_en; ///< If enabled wait until the write data to be available before to start sending the write command sequence. + uint8_t cs_hi_min_clk_cycles : 5; ///< After the execution of the write command, the QSPI_CS remains high for at least this number of QSPI_SCK clock cycles. + bool send_wen_req; ///< If enabled the controller will apply the write enable command. +} qspi_w_write_instr_cfg_t; + +/** QSPIC write enable instruction configuration structure (auto access mode). */ +typedef struct st_qspi_w_write_enable_instr_cfg +{ + qspi_w_bus_mode_t opcode_bus_mode : 2; ///< Bus mode of the opcode phase. + uint8_t opcode; ///< Write Enable command opcode. +} qspi_w_write_enable_instr_cfg_t; + +/** QSPIC Double Data Rate (DDR) configuration structure. */ +typedef struct st_qspi_w_ctrl_ddr_cfg +{ + uint32_t ctrl_ddra; ///< DDR Control register A. + uint32_t ctrl_ddrb; ///< DDR Control register B. +} qspi_w_ctrl_ddr_cfg_t; + +/** QSPIC Double Data Rate (DDR) configuration structure. */ +typedef struct st_qspi_w_extra_registers_cfg +{ + uint32_t ctrl_mr_reg; ///< Control MR register. + uint32_t drst_cmd_reg; ///< DRST command register. +} qspi_w_extra_registers_cfg_t; + +/** + * QSPI memory configuration structure. + * + * This struct is used to define a driver for a specific QSPI memory. + */ +typedef struct st_qspi_w_flash_cfg +{ + bool is_ram; ///< Is QSPIC interfaced with a PSRAM device. + qspi_w_clk_mode_t clk_mode : 1; ///< Clock Mode. + qspi_w_read_instr_cfg_t * p_read_instr_cfg; ///< Read instruction configuration struct. + qspi_w_erase_instr_cfg_t * p_erase_instr_cfg; ///< Erase instruction configuration struct. + qspi_w_suspend_resume_instr_cfg_t * p_suspend_resume_instr_cfg; ///< Program and erase suspend/resume instruction + ///< configuration struct. + qspi_w_write_enable_instr_cfg_t * p_write_enable_instr_cfg; ///< Write enable instruction configuration. + qspi_w_read_status_instr_cfg_t * p_read_status_instr_cfg; ///< Read status register instruction + ///< configuration struct. + qspi_w_write_instr_cfg_t * p_write_instr_cfg; ///< Write instruction configuration struct. + qspi_w_break_instr_cfg_t * p_break_instr_cfg; ///< Burst break instruction configuration struct. + qspi_w_memblen_cfg_t * p_memblen_cfg; ///< External memory burst length configuration struct. + qspi_w_ctrl_ddr_cfg_t * p_ctrl_ddr; ///< QSPI DDR Control registers configuration struct. + qspi_w_extra_registers_cfg_t * p_extra_regs; ///< QSPI Extra registers configuration struct. +} qspi_w_flash_cfg_t; + +/** Extended configuration for QSPIC. */ +typedef struct st_qspi_w_extended_cfg +{ + uint8_t channel; ///< Channel number to be used (0..1). + qspi_w_mode_t qspi_mode; ///< QSPI DDR or SDR mode. + qspi_w_qspclk_div_t qspclk_div; ///< QSPCLK divider. + qspi_w_drive_current_t qspi_drive_current; ///< Set the Drive Strength of the QSPI Controller. + qspi_w_slew_rate_t qspi_slew_rate; ///< Set the Slew Rate of the QSPI Controller. + qspi_w_flash_cfg_t const * p_qspi_flash_cfg; ///< Pointer to qspi controller configuration struct. + qspi_w_dcache_t qspi_dcache; ///< Data cache. +} qspi_w_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called. */ +typedef struct st_qspi_w_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; ///< Pointer to initial configuration. + spi_flash_data_lines_t data_lines; ///< Data lines. + uint32_t total_size_bytes; ///< Total size of the flash in bytes. + uint32_t open; ///< Whether or not driver is open. + bool xip_mode_is_enabled; ///< XiP mode is enabled or disabled. +} qspi_w_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_flash_api_t g_spi_flash_on_qspi_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_Close(spi_flash_ctrl_t * p_ctrl); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_DirectWrite(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_DirectRead(spi_flash_ctrl_t * p_ctrl, + uint8_t * const p_dest, + uint32_t const bytes); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_XipEnter(spi_flash_ctrl_t * p_ctrl); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_XipExit(spi_flash_ctrl_t * p_ctrl); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_Write(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_Erase(spi_flash_ctrl_t * p_ctrl, + uint8_t * const p_device_address, + uint32_t byte_count); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_DirectTransfer(spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +PLACE_IN_RAM_SECTION fsp_err_t R_QSPI_W_AutoCalibrate(spi_flash_ctrl_t * p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup QSPI_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_QSPI_W_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w.h new file mode 100644 index 000000000000..2e7226614e2d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w.h @@ -0,0 +1,209 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RTC_W_H +#define R_RTC_W_H + +/*******************************************************************************************************************//** + * @addtogroup RTC_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_rtc_w_cfg.h" +#include "r_rtc_api.h" +#include "r_rtc_w_helper.h" + +#if (BSP_CFG_RTOS == 2) +#include "FreeRTOS.h" +#include "semphr.h" + +#define RTC_W_LOCK_TYPE SemaphoreHandle_t +#define RTC_W_LOCK_INIT(p_ctrl) \ + (((p_ctrl)->calendar_time_lock = xSemaphoreCreateMutex()) != NULL ? FSP_SUCCESS : FSP_ERR_OUT_OF_MEMORY) +#define RTC_W_LOCK_DEINIT(p_ctrl) \ + do { vSemaphoreDelete((p_ctrl)->calendar_time_lock); (p_ctrl)->calendar_time_lock = NULL; } while (0) +#define RTC_W_LOCK_TAKE(p_ctrl) \ + do { (void) xSemaphoreTake((p_ctrl)->calendar_time_lock, portMAX_DELAY); } while (0) +#define RTC_W_LOCK_GIVE(p_ctrl) \ + do { (void) xSemaphoreGive((p_ctrl)->calendar_time_lock); } while (0) +#elif (BSP_CFG_RTOS == 3) +#include + +#define RTC_W_LOCK_TYPE struct rt_mutex +#define RTC_W_LOCK_INIT(p_ctrl) \ + (rt_mutex_init(&(p_ctrl)->calendar_time_lock, "rtc", RT_IPC_FLAG_PRIO) == RT_EOK ? FSP_SUCCESS : FSP_ERR_OUT_OF_MEMORY) +#define RTC_W_LOCK_DEINIT(p_ctrl) \ + do { rt_mutex_detach(&(p_ctrl)->calendar_time_lock); } while (0) +#define RTC_W_LOCK_TAKE(p_ctrl) \ + do { (void) rt_mutex_take(&(p_ctrl)->calendar_time_lock, RT_WAITING_FOREVER); } while (0) +#define RTC_W_LOCK_GIVE(p_ctrl) \ + do { (void) rt_mutex_release(&(p_ctrl)->calendar_time_lock); } while (0) +#else +#define RTC_W_LOCK_TYPE uint8_t +#define RTC_W_LOCK_INIT(p_ctrl) (FSP_ERR_UNSUPPORTED) +#define RTC_W_LOCK_DEINIT(p_ctrl) do { } while (0) +#define RTC_W_LOCK_TAKE(p_ctrl) do { } while (0) +#define RTC_W_LOCK_GIVE(p_ctrl) do { } while (0) +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "RTC" in ASCII, used to determine if device is open. */ +#define RTC_W_OPEN (0x00525444ULL) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** RTC extended configuration */ +typedef struct st_rtc_extended_cfg +{ + uint32_t reserved; ///< Reserved +} rtc_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref rtc_api_t::open is called */ +typedef struct st_rtc_w_ctrl +{ + uint32_t open; ///< Whether or not driver is open. + const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations. + RTC_W_LOCK_TYPE calendar_time_lock; ///< Lock for shared Calendar time data. +} rtc_w_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const rtc_api_t g_rtc_on_rtc_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_Open(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); +fsp_err_t R_RTC_W_Close(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_W_ClockSourceSet(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_W_CalendarTimeSet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_W_CalendarTimeGet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_W_CalendarAlarmSet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_W_CalendarAlarmGet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_W_PeriodicIrqRateSet(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); +fsp_err_t R_RTC_W_ErrorAdjustmentSet(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); +fsp_err_t R_RTC_W_InfoGet(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); +fsp_err_t R_RTC_W_PDCEventConfig(rtc_ctrl_t * const p_ctrl, uint16_t pdc_evt_period); +fsp_err_t R_RTC_W_MotorEventConfig(rtc_ctrl_t * const p_ctrl, uint16_t motor_evt_period); +fsp_err_t R_RTC_W_CallbackSet(rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void * const p_context, + rtc_callback_args_t * const p_callback_memory); +fsp_err_t R_RTC_W_TimeCaptureSet(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); +fsp_err_t R_RTC_W_TimeCaptureGet(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); + + +/*******************************************************************************************************************//** + * Get the system boot time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time Pointer to a time structure that contains the boot time. + * + * @retval FSP_SUCCESS Calendar Boot time get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarBootTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + +/*******************************************************************************************************************//** + * Set the timezone offset from GMT. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_timezone Pointer to a timezone to set (in seconds) + * + * @retval FSP_SUCCESS Calendar TimeZone set operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarTimeZoneSet (rtc_ctrl_t * const p_ctrl, long * p_timezone); + +/*******************************************************************************************************************//** + * Get the timezone offset from GMT. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_timezone Pointer to the current timezone (in seconds) + * + * @retval FSP_SUCCESS Calendar TimeZone get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarTimeZoneGet (rtc_ctrl_t * const p_ctrl, long * p_timezone); + +/*******************************************************************************************************************//** + * Get the GMT calendar time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time Pointer to GMT time + * + * @retval FSP_SUCCESS Calendar GMT time get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarGMTTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + +/*******************************************************************************************************************//** + * Compare a given time to the current time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time Pointer to the given time + * @param[out] p_comp Set to 'true' if the given time already passed (in compare to current time) + * and to 'false' otherwise. + * + * @retval FSP_SUCCESS Calendar Time Passed operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarTimePassed (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time, bool * p_comp); + +/*******************************************************************************************************************//** + * Convert rtc_time struct to a human readable string according to a given format (format example: "%Y.%m.%d %H:%M:%S") + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time Pointer to the time to convert to a string + * @param[out] str_buff_ptr Buffer to contain a string converted from p_time + * @param[out] maxsize Max size of str_buff_ptr + * @param[in] format Format string + * + * @retval FSP_SUCCESS Time to Str operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_Time2Str (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time, char * const str_buff_ptr, + size_t maxsize, char const * format); + +/*******************************************************************************************************************//** + * Get RTC_W control block. + * + * @retval p_ctrl Pointer to the RTC_W control block. +**********************************************************************************************************************/ +rtc_ctrl_t * R_RTC_W_GetCtrl(void); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_RTC_W_H + +/*******************************************************************************************************************//** + * @} (end addtogroup RTC_W) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w_helper.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w_helper.h new file mode 100644 index 000000000000..cd1ff2e0981c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_rtc_w_helper.h @@ -0,0 +1,103 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RTC_W_HELPER_H +#define R_RTC_W_HELPER_H + +#include +#include "bsp_api.h" +#include "sdk_defs.h" +#include "bsp_rtm.h" + +/** + **************************************************************************************** + * @brief Get timezone offset from GMT + * @return Returns a value of type time_t(long) that represents a timezone offset value. + **************************************************************************************** + */ +long ra6w1_Tzoff(void); + +/** + **************************************************************************************** + * @brief Set the timezone offset from GMT + * param[in] offset Set time zone offset value of type time_t(long) + **************************************************************************************** + */ +void ra6w1_SetTzoff(long offset); + +/// Convert time_t to tm as UTC time +#define gmtime(p) ra6w1_gmtime64(p) + +/// Convert tm structure to time_t +#define localtime(p) ra6w1_localtime64(p) + +/** + **************************************************************************************** + * @brief Get / Set current GMT time (for 64bit) & check and fix bsp system count wraparround. + * @param[in] p Set the time of p value to the current time.\n + * If NULL, no current time is set. + * @param[out] now Get the current time. + **************************************************************************************** + */ +void ra6w1_time64(__time64_t * p, __time64_t * now); + +/** + **************************************************************************************** + * @brief Convert __time64_t to tm as UTC time + * @param[in] tod Pointer to an object of type time_t that contains a time value.\n + * __time64_t is an alias of a fundamental arithmetic type capable of representing times as returned by function time. + * @return A pointer to a tm structure with its members filled with the values that correspond to the UTC time representation of tod. + **************************************************************************************** + */ +struct tm * ra6w1_gmtime64(const __time64_t * tod); + +/** + **************************************************************************************** + * @brief Convert __time64_t to tm as local time + * @param[in] tod Pointer to an object of type __time64_t that contains a time value.\n + * time_t is an alias of a fundamental arithmetic type capable of representing times as returned by function time. + * @return A pointer to a tm structure with its members filled with the values that correspond to the local time representation of tod. + **************************************************************************************** + */ +struct tm * ra6w1_localtime64(const __time64_t * tod); + +/** + **************************************************************************************** + * @brief Convert tm structure to __time64_t + * @param[in] t Pointer to a tm structure that contains a calendar gmt time broken down into its components (see struct tm) + * @param[out] now Returns the value of type __time64_t that represents the time described by the tm structure pointed by t + **************************************************************************************** + */ +void ra6w1_mktime64(struct tm * t, __time64_t * now); + +/** + **************************************************************************************** + * @brief Get elapsed time after RTOS boot(for 64bit) + * param[out] boottime Pointer to an object of type time_t that contains a time value. + **************************************************************************************** + */ +void __boottime(__time64_t * boottime); + +/** + **************************************************************************************** + * @brief Format time as string + * @param[out] ptr Pointer to the destination array where the resulting C string is copied. + * @param[in] maxsize Maximum number of characters to be copied to ptr, including the terminating null-character. + * @param[in] format C string containing any combination of regular characters and special format specifiers.\n + * These format specifiers are replaced by the function to the corresponding values to represent + * the time specified in timeptr. + * @param[in] t Pointer to struct tm to convert to a string + * @return If the length of the resulting C string, including the terminating null-character, doesn't exceed maxsize,\n + * the function returns the total number of characters copied to ptr (not including the terminating null-character).\n + * Otherwise, it returns zero, and the contents of the array pointed by ptr are indeterminate. + **************************************************************************************** + */ +size_t ra6w1_strftime(char * ptr, size_t maxsize, const char * format, const struct tm * t); + +void rtc_w_lock_take(void); +void rtc_w_lock_give(void); + +#endif // R_RTC_W_HELPER_H diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_spi_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_spi_w.h new file mode 100644 index 000000000000..7080be4e6942 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_spi_w.h @@ -0,0 +1,187 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SPI_W_H +#define R_SPI_W_H + +/*******************************************************************************************************************//** + * @addtogroup SPI_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" +#include "r_spi_w_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Offset to make the SPI HW channels 0-based for the r_spi driver. */ +#if (BSP_FEATURE_SPI_VALID_CHANNEL_MASK & 0x1) + #define SPI_W_CHANNEL_OFFSET 0 +#elif (BSP_FEATURE_SPI_VALID_CHANNEL_MASK & 0x2) + #define SPI_W_CHANNEL_OFFSET 1 +#endif + +#if BSP_MCU_GROUP_RA6W3 + /* Maximum Tx FIFO buffer size (SPI1) */ + #define SPI_W_TX_FIFO_MAX_SIZE_BYTE_SPI1 (256) + + /* Maximum Tx FIFO buffer size (SPI2, SPI3) */ + #define SPI_W_TX_FIFO_MAX_SIZE_BYTE (32) + + /* Maximum Rx FIFO buffer size (SPI1, SPI2, SPI3) */ + #define SPI_W_RX_FIFO_MAX_SIZE_BYTE (32) +#else + /* Maximum RX FIFO buffer size. */ + #define SPI_W_RX_FIFO_MAX_SIZE_BYTE (32) +#endif + +#if SPI_W_CFG_FAST_MODE_ENABLE +#define SPI_W_FAST_READ_HEADER_SIZE 8 +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** The Chip Select Line. */ +typedef enum e_spi_w_cs_select +{ + SPI_W_CS_SELECT_CS0 = 1, ///< Select CS0 + SPI_W_CS_SELECT_CS1 = 2, ///< Select CS1 +} spi_w_cs_select_t; + +/** Byte Swapping Enable/Disable. */ +typedef enum e_spi_w_byte_swap +{ + SPI_W_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers. + SPI_W_BYTE_SWAP_ENABLE, ///< Enable Byte swapping for 16/32-Bit transfers. +} spi_w_byte_swap_t; + +/** Capture data at current/next clock edge. */ +typedef enum e_spi_w_capture_edge +{ + SPI_W_CAPTURE_CURRENT_EDGE = 0, ///< SPI captures data at current clock edge. + SPI_W_CAPTURE_NEXT_EDGE, ///< SPI captures data at next clock edge. (only for Master mode & high bitrate). +} spi_w_capture_edge_t; + +/** Extended SPI interface configuration */ +typedef struct st_spi_w_extended_cfg +{ + spi_w_cs_select_t cs_select; ///< Select which slave to use: 0-CS0, 1-CS1. + spi_w_byte_swap_t byte_swap; ///< Select byte swap mode. + spi_w_capture_edge_t cap_edge; ///< Select capture clock edge. + uint32_t rx_fifo_lvl_thres; ///< Set fifo level threshold for rx. + uint32_t tx_fifo_lvl_thres; ///< Set fifo level threshold for tx. + uint8_t spck_div; ///< Register value for configuring the SPI Clock Divider. + uint8_t gen_ipl; ///< Generic interrupt priority. + IRQn_Type gen_irq; ///< Generic interrrupt IRQ number. +#if SPI_W_CFG_FAST_MODE_ENABLE + bool skip_disable; ///< SPI will not be disabled after a read/write cycle for fast reaction. +#endif + bool skip_busy_check; ///< If true, SPI will not check for busy state on read. +} spi_w_extended_cfg_t; + +#if SPI_W_CFG_FAST_MODE_ENABLE +/** Add descryption for fast mode */ +typedef enum e_spi_w_fast_mode +{ + SPI_W_FAST_MODE_OFF = 0, ///< Set SPI fast mode disable + SPI_W_FAST_MODE_ON ///< Set SPI fast mode for read sequence +} spi_w_fast_mode_t; +#endif + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ +typedef struct st_spi_w_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration. + SPI_Type * p_regs; ///< Base register for this channel. + void const * p_tx_data; ///< Buffer to transmit. + void * p_rx_data; ///< Buffer to receive. + uint32_t tx_count; ///< Number of Data Frames to transmit (8-bit, 16-bit, 32-bit). + uint32_t rx_count; ///< Number of Data Frames to receive (8-bit, 16-bit, 32-bit). + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit). + spi_bit_width_t bit_width; ///< Bits per Data frame. + uint32_t mask_width; ///< Bit width mask for data. + uint8_t wordsize; ///< Word size of current transmit. +#if SPI_W_CFG_FAST_MODE_ENABLE + uint8_t fast_mode_st; ///< State the data transfer mode. + uint32_t fast_max_count; ///< Number of Data Frames to transfer in fast mode. + uint8_t fast_mode_buffer[SPI_W_FAST_READ_HEADER_SIZE]; ///< Buffer receive header. +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} spi_w_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_spi_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); + +fsp_err_t R_SPI_W_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_W_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_W_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_W_Close(spi_ctrl_t * const p_api_ctrl); + +fsp_err_t R_SPI_W_CalculateBitrate(uint32_t bitrate, uint8_t * spck_div, uint8_t channel); + +fsp_err_t R_SPI_W_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory); + +#if SPI_W_CFG_FAST_MODE_ENABLE +fsp_err_t R_SPI_W_FastRead(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + uint32_t const max_count, + spi_bit_width_t const bit_width); +#endif + +/*******************************************************************************************************************//** + * @} (end ingroup SPI_W) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SPI_W_H diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_tim_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_tim_w.h new file mode 100644 index 000000000000..d1ef051614d8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_tim_w.h @@ -0,0 +1,254 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TIM_W_H +#define R_TIM_W_H + +/*******************************************************************************************************************//** + * @addtogroup TIM_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TIM_W_PWM_MAX (0xFFFFUL) +#define TIM_W_COUNTER_MAX_VALUE (0xFFFFFFFFU) + +#define TIM_W_TIM1 (0U) +#define TIM_W_TIM2 (1U) +#define TIM_W_TIM3 (2U) +#define TIM_W_TIM4 (3U) +#define TIM_W_TIM5 (4U) +#define TIM_W_TIM6 (5U) +#define TIM_W_TIM7 (6U) +#define TIM_W_TIM8 (7U) + +#define TIM_W_PWM_SYNC_TIMER2 (0b00000001) +#define TIM_W_PWM_SYNC_TIMER3 (0b00000010) +#define TIM_W_PWM_SYNC_TIMER4 (0b00000100) + +#if BSP_MCU_GROUP_RA6W3 + #define TIM_W_TIM9 (8U) + #define TIM_W_TIM10 (9U) + + #define TIM_W_CHANNEL_MAX (TIM_W_TIM10) + + #define TIM_W_PWM_SYNC_TIMER5 (0b00001000) + #define TIM_W_PWM_SYNC_TIMER6 (0b00010000) + #define TIM_W_PWM_SYNC_TIMER7 (0b00100000) + #define TIM_W_PWM_SYNC_TIMER8 (0b01000000) + #define TIM_W_PWM_SYNC_TIMER9 (0b10000000) +#elif defined(BSP_MCU_GROUP_RA6B1) || defined(BSP_MCU_GROUP_RA6U1) + #define TIM_W_PWM_SYNC_TIMER5 (0b00001000) + #define TIM_W_PWM_SYNC_TIMER6 (0b00010000) + #define TIM_W_PWM_SYNC_TIMER7 (0b00100000) + + #define TIM_W_CHANNEL_MAX (TIM_W_TIM8) +#else + #define TIM_W_CHANNEL_MAX (TIM_W_TIM8) +#endif + +#if BSP_FEATURE_TIM_W_LINEAR_SRC_DIV_STEP + #define TIM_W_SOURCE_DIV_MAX (TIMER_SOURCE_DIV_32) +#else + #define TIM_W_SOURCE_DIV_MAX (TIMER_SOURCE_DIV_256) +#endif + +/** Offset to make the TIM_W HW channels 0-based for the r_tim_w driver. */ +#if (BSP_FEATURE_TIM_W_VALID_CHANNEL_MASK & 0x1U) + #define TIM_W_CHANNEL_OFFSET (0U) +#elif (BSP_FEATURE_TIM_W_VALID_CHANNEL_MASK & 0x2U) + #define TIM_W_CHANNEL_OFFSET (1U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Count source clock */ +typedef enum e_tim_w_clock +{ + TIM_W_CLOCK_LP_CLK = 0, ///< Select LP Clk to supply timer + TIM_W_CLOCK_DIVN = 1, ///< Select Divn_clk clk to supply timer +} tim_w_clock_t; + +/** Trigger edge for pulse period measurement mode and event counting mode. */ +typedef enum e_tim_w_gpio_trigger +{ + TIM_W_GPIO_TRIGGER_DISABLED = 0, ///< Disable external trigger events + TIM_W_GPIO_TRIGGER_EDGE_RISING = 1, ///< Measurement starts or events are counted on rising edge + TIM_W_GPIO_TRIGGER_EDGE_FALLING = 2, ///< Measurement starts or events are counted on falling edge +} tim_w_gpio_trigger_t; + +#if !BSP_FEATURE_ELC_MISSING + +/** Tasks available for elc */ +typedef enum e_tim_w_elc_task +{ + TIM_W_ELC_DISABLED = 0U, ///< TIM_CLK_EN = 0 + TIM_W_ELC_START, ///< TIM_EN = 1 + TIM_W_ELC_STOP, ///< TIM_EN = 0 + TIM_W_ELC_COUNT_UP, ///< PULSE_CNT += 1, edge counter mode only + TIM_W_ELC_CLEAR, ///< TIM_TIMER_VALUE = initial count up/down value + TIM_W_ELC_ONESHOT_TRIGGER, ///< Trigger one-shot + TIM_W_ELC_CAPTURE, ///< Trigger a capture operation + TIM_W_ELC_PAUSE_RESUME, ///< Toggle TIM_PAUSE +} tim_w_elc_task_t; +#endif + +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + +/** Channel available operations */ +typedef enum e_tim_w_ccm_operation +{ + TIM_W_CCM_OPERATION_CAPTURE = 0, + TIM_W_CCM_OPERATION_COMPARE_MATCH = 1, +} tim_w_ccm_operation_t; +#endif + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_tim_w_instance_ctrl +{ + uint32_t open; ///< Whether or not channel is open + const timer_cfg_t * p_cfg; ///< Pointer to initial configurations + TIMER_Type * p_reg; ///< Base register for this channel + + void (* p_callback)(timer_callback_args_t *); ///< Pointer to callback + timer_callback_args_t * p_callback_memory; ///< Pointer to optional callback argument memory + void * p_context; ///< Pointer to context to be passed into callback function +} tim_w_instance_ctrl_t; + +/** Configuration structure for non-periodic Capture/CompareMatch channels. */ +typedef struct st_tim_w_operation_channel_cfg +{ +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + tim_w_ccm_operation_t operation; ///< Operation channel will be used as capture or compare match + uint32_t compare_value; ///< Select the operation channel's compare match value +#endif + bsp_io_port_pin_t capture_source; ///< Configuration for GPIOs used as a source for capture operation. + tim_w_gpio_trigger_t capture_trigger; + uint8_t ccm_operation_ipl; + IRQn_Type ccm_operation_irq; +} tim_w_operation_channel_cfg; + +/** Extended Configuration for Capture/Compare-Match Operations. */ +typedef struct st_tim_w_extended_ccm_cfg +{ + /** When set, first capture value is persistant, + * next captures on the same register will not overwrite the first value. + */ + bool single_capture_mode; + +#if BSP_FEATURE_TIM_W_SUPPORTS_SEQ_CAPTURES + + /** When set, sequential capturing is activated. + * When the number of capture triggers reaches this number, + * a generic irq will activate. Both gpio and elc can + * trigger sequential captures. + */ + uint8_t seq_captures; +#endif + +#if !BSP_FEATURE_ELC_MISSING + uint8_t elc_channel; ///< Channel used for ELC Capture. +#endif + + tim_w_operation_channel_cfg * p_ccm_channel_cfg; ///< Configuration Array of Operation Channels + uint8_t ccm_channel_size; ///< Number of Operation Channels used for Capture or Compare-Match operations. +} tim_w_extended_ccm_cfg; + +/** TIM_W extension configures the output pins for TIM_W. */ +typedef struct st_tim_w_extended_cfg +{ + bool free_run; ///< Free-running mode (up-count only) + tim_w_clock_t count_source; ///< Clock source supplied to timer + timer_direction_t direction; ///< Counter direction + +#if BSP_FEATURE_TIM_W_SUPPORTS_OVERFLOW_UNDERFLOW + uint8_t overflow_ipl; + IRQn_Type overflow_irq; + uint8_t underflow_ipl; + IRQn_Type underflow_irq; +#endif + + /* PWM Configuration Options */ + uint16_t pwm_sync_map; ///< Channels to be synchronously started with TIM on PWM mode + +#if !BSP_FEATURE_ELC_MISSING + + /* ELC Configuration Options */ + tim_w_elc_task_t elc_task; +#endif + + /* External GPIO used in One-Shot or Edge Detect Modes. */ + bsp_io_port_pin_t gpio_source; + + tim_w_gpio_trigger_t gpio_trigger; + + bool oneshot_switch_to_periodic; ///< Enable auto mode switch from oneshot to periodic when oneshot elapses + + /* Delay before oneshot pulse begins. + * If oneshot_switch_to_periodic is set, this delay also represents the period in periodic mode. + */ + uint32_t oneshot_delay; + + /* Configuration of advanced Capture/Compare-Match Operations */ + tim_w_extended_ccm_cfg * p_ccm_cfg; +} tim_w_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_tim_w; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_TIM_W_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_TIM_W_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_TIM_W_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_TIM_W_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_TIM_W_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_TIM_W_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TIM_W_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); +fsp_err_t R_TIM_W_SequentialCapturesGet(timer_ctrl_t * const p_ctrl, uint32_t * const p_captures); + +fsp_err_t R_TIM_W_PeriodSet_light(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); + +/*******************************************************************************************************************//** + * @} (end defgroup TIM_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_uart_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_uart_w.h new file mode 100644 index 000000000000..46efbecdbdce --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_uart_w.h @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_UART_W_H +#define R_UART_W_H + +/*******************************************************************************************************************//** + * @addtogroup UART_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_uart_api.h" +#include "r_uart_w_cfg.h" +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + #include "FreeRTOS.h" + #include "event_groups.h" + #endif +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define DEFAULT_UART_W_IRQ_PRIORITY 5 + +#if !BSP_MCU_GROUP_RA6W1 + #define UART1_CHANNEL_NUM 0 + #define UART2_CHANNEL_NUM 1 + #define UART3_CHANNEL_NUM 2 + #define UART4_CHANNEL_NUM 3 +#endif + +#if (BSP_FEATURE_UART_W_VALID_CHANNEL_MASK & 0x1) + #define UART_W_CHANNEL_OFFSET 0 +#elif (BSP_FEATURE_UART_W_VALID_CHANNEL_MASK & 0x2) + #define UART_W_CHANNEL_OFFSET 1 +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART flow control mode definition */ +typedef enum e_uart_w_auto_flow_control +{ + UART_W_AUTO_FLOW_CONTROL_DISABLED = 0, ///< Disable auto flow control + UART_W_AUTO_FLOW_CONTROL_ENABLED = 1, ///< Enable auto flow control +} uart_w_auto_flow_control_t; + +typedef enum e_uart_w_loop_back +{ + UART_W_LOOP_BACK_DISABLE = 0, ///< Disable loop back + UART_W_LOOP_BACK_ENABLE = 1, ///< Enable loop back +} uart_w_loop_back_t; + +typedef enum e_uart_w_fifo_enable +{ + UART_W_FIFO_DISABLE = 0, ///< Disable fifo + UART_W_FIFO_ENABLE = 1, ///< Enable fifo +} uart_w_fifo_enable_t; + +typedef enum e_uart_w_extended_data_bits +{ + UART_W_EXTENDED_DATA_BITS_DISABLE = 0, ///< Disable extended word length configuration + UART_W_EXTENDED_DATA_BITS_ENABLE = 1, ///< Enable extended word length configuration +} uart_w_extended_data_bits_t; + +/** UART Data bit length definition */ +typedef enum e_uart_w_data_bits +{ + UART_W_DATA_BITS_5 = 0U, ///< Data bits 5-bit + UART_W_DATA_BITS_6 = 1U, ///< Data bits 6-bit + UART_W_DATA_BITS_7 = 2U, ///< Data bits 7-bit + UART_W_DATA_BITS_8 = 3U, ///< Data bits 8-bit +} uart_w_data_bits_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_uart_w_rx_fifo_trigger +{ + UART_W_RX_FIFO_TRIGGER_EIGHTH = 0x0, ///< Received Data Available Interrupt when FIFO is 1/8 full + UART_W_RX_FIFO_TRIGGER_QUARTER = 0x1, ///< Received Data Available Interrupt when FIFO is 1/4 full + UART_W_RX_FIFO_TRIGGER_HALF = 0x2, ///< Received Data Available Interrupt when FIFO is 1/2 full + UART_W_RX_FIFO_TRIGGER_THREE_QUARTERS = 0x3, ///< Received Data Available Interrupt when FIFO is 3/4 full + UART_W_RX_FIFO_TRIGGER_SEVEN_EIGHTHS = 0x4, ///< Received Data Available Interrupt when FIFO is 7/8 full +} uart_w_rx_fifo_trigger_t; + +/** Transmit FIFO trigger configuration. */ +typedef enum e_uart_w_tx_fifo_trigger +{ + UART_W_TX_FIFO_TRIGGER_EIGHTH = 0x0, ///< Transmit Data Interrupt when FIFO is 1/8 full + UART_W_TX_FIFO_TRIGGER_QUARTER = 0x1, ///< Transmit Data Interrupt when FIFO is 1/4 full + UART_W_TX_FIFO_TRIGGER_HALF = 0x2, ///< Transmit Data Interrupt when FIFO is 1/2 full + UART_W_TX_FIFO_TRIGGER_THREE_QUARTERS = 0x3, ///< Transmit Data Interrupt when FIFO is 3/4 full + UART_W_TX_FIFO_TRIGGER_SEVEN_EIGHTHS = 0x4, ///< Transmit Data Interrupt when FIFO is 7/8 full +} uart_w_tx_fifo_trigger_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_uart_w_rs485_enable +{ + UART_W_RS485_DISABLE = 0, ///< RS-485 disabled. + UART_W_RS485_ENABLE = 1, ///< RS-485 enabled. +} uart_w_rs485_enable_t; + +/** UART channel control block. */ +typedef struct st_uart_w_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + /* FIFO depth of the UART channel */ + uint8_t fifo_depth; + + /* Used to determine if the channel is configured */ + uint32_t open; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + UART_Type * p_reg; + + /* Pointer to callback that is called when a uart_event_t occurs. */ + void (* p_callback)(uart_callback_args_t *); + + /* Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. */ + uart_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + + /* Timer handler for uart tx completion */ + TimerHandle_t uart_tx_done_timer; + + /* Flag that indicates that uart trnsmition is ongoing */ + bool tx_onging_flag; + #endif +#endif +} uart_w_instance_ctrl_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_uart_w_baud_setting_t +{ + uint32_t fra_baud; ///< Baud rate fractional part + uint32_t int_baud; ///< Baud rate integer part +} uart_w_baud_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_uart_w_extended_cfg +{ + uart_w_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + uart_w_loop_back_t loop_back_enable; ///< Enable loop back. + uart_w_fifo_enable_t fifo_enable; ///< Enable FIFO. + uart_w_rx_fifo_trigger_t rx_fifo_trigger; ///< RX FIFO trigger level. + uart_w_tx_fifo_trigger_t tx_fifo_trigger; ///< TX FIFO trigger level. + uart_w_auto_flow_control_t flow_control; ///< CTS/RTS function + uart_w_rs485_enable_t rs485_enable; ///< RS-485 settings. +#if !BSP_MCU_GROUP_RA6W1 + uart_w_extended_data_bits_t extended_data_bits_enable; ///< Enable extended data bits configuration. + uart_w_data_bits_t data_bits; ///< Data bit length (5, 6 or 7 or 8) + uint8_t gen_ipl; ///< Generic interrupt priority. + IRQn_Type gen_irq; +#endif ///< Generic interrupt IRQ number. +} uart_w_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_uart_w; + +/** @endcond */ + +fsp_err_t R_UART_W_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_UART_W_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_UART_W_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_UART_W_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_UART_W_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_UART_W_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_UART_W_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_UART_W_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); + +#if BSP_MCU_GROUP_RA6W1 +fsp_err_t R_UART_W_ConfSet(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_UART_W_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_UART_W_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +#endif + +fsp_err_t R_UART_W_BaudCalculate(uint32_t baudrate, uart_w_baud_setting_t * const p_baud_setting); +fsp_err_t R_UART_W_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +bool R_UART_W_IsWritting(uart_ctrl_t * const p_api_ctrl); +bool R_UART_W_IsOpened(uart_ctrl_t * const p_api_ctrl); + +#if !BSP_MCU_GROUP_RA6W1 +void hw_clk_enable_uart_w_clk(uint8_t channel); + +#endif + +/*******************************************************************************************************************/ /** + * @} (end addtogroup UART_W) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_wdog_w.h b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_wdog_w.h new file mode 100644 index 000000000000..c7b2ab7136e6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/inc/instances/r_wdog_w.h @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup WDOG_W + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDOG_W_H +#define R_WDOG_W_H + +#include "r_wdog_w_cfg.h" +#include "r_wdt_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define WDOG_W_TIMEOUT_MIN (1U) +#if defined(WDTSYS_WDTSYS_REG_WDTSYS_VAL_Msk) + #define WDOG_W_TIMEOUT_MAX WDTSYS_WDTSYS_REG_WDTSYS_VAL_Msk +#elif defined(SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk) + #define WDOG_W_TIMEOUT_MAX SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** WDOG_W private control block. DO NOT MODIFY. Initialization occurs when @ref wdt_api_t::open is called. */ +typedef struct st_wdog_w_instance_ctrl +{ + uint32_t wdt_open; // Indicates whether the open() API has been successfully called. + const wdt_cfg_t * p_cfg; // Pointer to initial configuration. + + uint32_t timeout; // Timeout value (may be modified after initial open). + void * p_context; // Placeholder for user data. Passed to the user callback in + // wdt_callback_args_t. + void (* p_callback)(wdt_callback_args_t * p_args); // Callback provided when a WDOG_W NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass + // arguments to a callback in non-secure memory. +} wdog_w_instance_ctrl_t; + +/** WDOG_W clock source options. */ +typedef enum e_wdog_w_clk_src +{ + WDOG_W_CLK_SRC_RCLP = 0, ///< Use RCLP as clock source. + WDOG_W_CLK_SRC_RCX = 1, ///< Use RCX as clock source. +} wdog_w_clk_src_t; + +/** WATCHDOG extended Configuration */ +typedef struct st_wdog_w_extended_cfg +{ + wdog_w_clk_src_t wdt_clk_src; ///< CLock source setting for WDT. +} wdog_w_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const wdt_api_t g_wdt_on_wdog_w; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_Refresh(wdt_ctrl_t * const p_ctrl); + +fsp_err_t R_WDOG_W_Open(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + +fsp_err_t R_WDOG_W_StatusClear(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + +fsp_err_t R_WDOG_W_StatusGet(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + +fsp_err_t R_WDOG_W_CounterGet(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + +fsp_err_t R_WDOG_W_TimeoutGet(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + +fsp_err_t R_WDOG_W_TimeoutSet(wdt_ctrl_t * const p_ctrl, uint32_t timeout); + +fsp_err_t R_WDOG_W_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory); + +fsp_err_t R_WDOG_W_Freeze(wdt_ctrl_t * const p_ctrl, bool freeze); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_WDOG_W_H + +/*******************************************************************************************************************//** + * @} (end addtogroup WDOG_W) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 000000000000..c69923618c24 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,202 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if BSP_MCU_GROUP_RA0E1 + #include "R7FA0E107.h" + #elif BSP_MCU_GROUP_RA0E2 + #include "R7FA0E209.h" + #elif BSP_MCU_GROUP_RA0L1 + #include "R7FA0L107.h" + #elif BSP_MCU_GROUP_RA2A1 + #include "R7FA2A1AB.h" + #elif BSP_MCU_GROUP_RA2A2 + #include "R7FA2A2AD.h" + #elif BSP_MCU_GROUP_RA2E1 + #include "R7FA2E1A9.h" + #elif BSP_MCU_GROUP_RA2E2 + #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2E3 + #include "R7FA2E307.h" + #elif BSP_MCU_GROUP_RA2L1 + #include "R7FA2L1AB.h" + #elif BSP_MCU_GROUP_RA2L2 + #include "R7FA2L209.h" + #elif BSP_MCU_GROUP_RA2T1 + #include "R7FA2T107.h" + #elif BSP_MCU_GROUP_RA4C1 + #include "R7FA4C1BD.h" + #elif BSP_MCU_GROUP_RA4E1 + #include "R7FA4E10D.h" + #elif BSP_MCU_GROUP_RA4E2 + #include "R7FA4E2B9.h" + #elif BSP_MCU_GROUP_RA4M1 + #include "R7FA4M1AB.h" + #elif BSP_MCU_GROUP_RA4M2 + #include "R7FA4M2AD.h" + #elif BSP_MCU_GROUP_RA4M3 + #include "R7FA4M3AF.h" + #elif BSP_MCU_GROUP_RA4T1 + #include "R7FA4T1BB.h" + #elif BSP_MCU_GROUP_RA4W1 + #include "R7FA4W1AD.h" + #elif BSP_MCU_GROUP_RA4L1 + #include "R7FA4L1BD.h" + #elif BSP_MCU_GROUP_RA6E1 + #include "R7FA6E10F.h" + #elif BSP_MCU_GROUP_RA6E2 + #include "R7FA6E2BB.h" + #elif BSP_MCU_GROUP_RA6M1 + #include "R7FA6M1AD.h" + #elif BSP_MCU_GROUP_RA6M2 + #include "R7FA6M2AF.h" + #elif BSP_MCU_GROUP_RA6M3 + #include "R7FA6M3AH.h" + #elif BSP_MCU_GROUP_RA6M4 + #include "R7FA6M4AF.h" + #elif BSP_MCU_GROUP_RA6M5 + #include "R7FA6M5BH.h" + #elif BSP_MCU_GROUP_RA6T1 + #include "R7FA6T1AD.h" + #elif BSP_MCU_GROUP_RA6T2 + #include "R7FA6T2BD.h" + #elif BSP_MCU_GROUP_RA6T3 + #include "R7FA6T3BB.h" + #elif BSP_MCU_GROUP_RA8D1 + #include "R7FA8D1BH.h" + #elif BSP_MCU_GROUP_RA8E1 + #include "R7FA8E1AF.h" + #elif BSP_MCU_GROUP_RA8E2 + #include "R7FA8E2AF.h" + #elif BSP_MCU_GROUP_RA8M1 + #include "R7FA8M1AH.h" + #elif BSP_MCU_GROUP_RA8P1 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8T1 + #include "R7FA8T1AH.h" + #elif BSP_MCU_GROUP_RA8T2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA6B1 + #if defined(BOARD_RA6B1_PRODK) + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/R7KA6B1BG.h" + #else + #if __has_include("../../../../../bsp_w/cmsis/Device/RENESAS/Include/D3108BA.h") + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/D3108BA.h" + #else + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/R7KA6B1BG.h" + #endif + #endif + #elif BSP_MCU_GROUP_RA6W1 + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/R7SA6W1CE.h" + #elif BSP_MCU_GROUP_RA6W3 + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/R7SA6W3xx.h" + #elif BSP_MCU_GROUP_RA6B2 + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/D3333.h" + #elif BSP_MCU_GROUP_RA6U1 + #if defined(BOARD_RA6U1_EK) + #include "../../../../../bsp_w/cmsis/Device/RENESAS/Include/R7KA6U1BG.h" + #endif + #else + #if __has_include("renesas_internal.h") + #include "renesas_internal.h" + #else + #warning "Unsupported MCU" + #endif + #endif + +/* + * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB + * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 + * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: + * + * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | + * |-----------|------------|------------------------| + * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | + * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | + * + * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ + * + * IAR is currently the only toolchain producing the correct __ARM_ARCH value. + * + *- See https://github.com/ARM-software/CMSIS_6/issues/159 + */ + #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 + #undef __ARM_ARCH + #define __ARM_ARCH 801 + #endif + + #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M4 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) + #define RENESAS_CORTEX_M23 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M33 + #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M85 + #else + #warning Unsupported Architecture + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 000000000000..30afe29e7e06 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h new file mode 100644 index 000000000000..faa8da1086db --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_EXCEPTIONS_H + #define BSP_EXCEPTIONS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + + #if !defined(BSP_API_OVERRIDE) + +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + #endif + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/R7SA6W1CE.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/R7SA6W1CE.h new file mode 100644 index 000000000000..339fa346ed65 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/R7SA6W1CE.h @@ -0,0 +1,34879 @@ +/* + * Copyright (C) 2024 Renesas Electronics Corporation. + * This computer program includes Confidential, Proprietary Information + * of Renesas Electronics Corporation. All Rights Reserved. + * + * @file /workspaces/ahwang/bbtester/development/software_include/D3095BA/DA1640x.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 31. October 2024 + * @note Generated by SVDConv V3.3.35 on Thursday, 31.10.2024 10:40:45 + * from File '/workspaces/ahwang/bbtester/development/software_include/D3095BA/datasheet_cmsis.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup DA1640x + * @{ + */ + +#ifndef DA1640X_H + #define DA1640X_H + + #ifdef __cplusplus +extern "C" { + #endif + + #ifndef CMSIS_STRIP_HEADER + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + * and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + * related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== DA1640x Specific Interrupt Numbers =========================================== */ + DMA_IRQn = 0, /*!< 0 General Purpose DMA interrupt request. */ + KDMA_IRQn = 1, /*!< 1 kDMA interrupt request */ + UART_IRQn = 2, /*!< 2 UART interrupt request. */ + UART2_IRQn = 3, /*!< 3 UART2 interrupt request. */ + UART3_IRQn = 4, /*!< 4 UART3 interrupt request. */ + I2C_IRQn = 5, /*!< 5 I2C interrupt request. */ + I2C2_IRQn = 6, /*!< 6 I2C2 interrupt request. */ + SPI_IRQn = 7, /*!< 7 SPI interrupt request. */ + SPI2_IRQn = 8, /*!< 8 SPI2 interrupt request. */ + DAI_TX_IRQn = 9, /*!< 9 DAI TX interrupt request. */ + DAI_RX_IRQn = 10, /*!< 10 DAI RX interrupt request. */ + SRC_IN_IRQn = 11, /*!< 11 SRC input interrupt request. */ + SRC_OUT_IRQn = 12, /*!< 12 SRC output interrupt request. */ + SDIO_IRQn = 13, /*!< 13 SDIO interrupt request. */ + SDIO_WKUP_IRQn = 14, /*!< 14 SDIO Wakeup interrupt request. */ + TDES_CBC_IRQn = 15, /*!< 15 TDES interrupt request. */ + PSK_SHA1_IRQn = 16, /*!< 16 PSK SHA1 interrupt request. */ + CLKCAL_IRQn = 18, /*!< 18 Clock Calibration interrupt request. */ + TIMER_IRQn = 19, /*!< 19 Timer interrupt request. */ + TIMER2_IRQn = 20, /*!< 20 Timer2 interrupt request. */ + TIMER3_IRQn = 21, /*!< 21 Timer3 interrupt request. */ + TIMER4_IRQn = 22, /*!< 22 Timer4 interrupt request. */ + TIMER5_IRQn = 23, /*!< 23 Timer5 interrupt request. */ + TIMER6_IRQn = 24, /*!< 24 Timer6 interrupt request. */ + TIMER7_IRQn = 25, /*!< 25 Timer7 interrupt request. */ + TIMER8_IRQn = 26, /*!< 26 Timer8 interrupt request. */ + CAPTIMER_IRQn = 27, /*!< 27 GPIO capture interrupt request. */ + SYSPLL_LOCK_IRQn = 28, /*!< 28 PLL480M lock interrupt request */ + AUX_ADC_IRQn = 29, /*!< 29 Aux ADC interrupt request */ + RTC_IF_EXTWK_IRQn = 30, /*!< 30 External wakeup interrupt request */ + RTC_IF_BLACK_IRQn = 31, /*!< 31 Voltage blackout interrupt request */ + RTC_IF_BROWN_IRQn = 32, /*!< 32 Voltage brownout interrupt request */ + RTC_IF_PCNT_IRQn = 33, /*!< 33 Pulse count interrupt request */ + RTC_IF_BCF_MSR_IRQn = 34, /*!< 34 Bus clock measure interrupt request */ + RTC_IF_RTC_ACC_IRQn = 35, /*!< 35 access to RTC Core interrupt request */ + RTC_IF_EXP_IRQn = 36, /*!< 36 RTC mirror Free running count interrupt request */ + RTC_IF_LMR_IRQn = 37, /*!< 37 FRC to mirroring, loading done interrupt request */ + MRM_IRQn = 38, /*!< 38 MRM */ + DCACHE_MRM_IRQn = 39, /*!< 39 Data cache Miss Rate Monitor interrupt request. */ + CC312_IRQn = 40, /*!< 40 CryptoCell-312 interrupt request. */ + GPIO_P0_IRQn = 41, /*!< 41 GPIO port 0 toggle interrupt request. */ + GPIO_P1_IRQn = 42, /*!< 42 GPIO port 1 toggle interrupt request. */ + FPLL_LOCK_IRQn = 43, /*!< 43 FPLL lock interrupt request */ + WIFI_HSU_IRQn = 44, /*!< 44 WIFI Hardware Security Unit interrupt request. */ + WIFI_MODEM_IRQn = 45, /*!< 45 WIFI Modem interrupt request. */ + WIFI_MACTIMER_IRQn = 46, /*!< 46 WIFI MAC TX/RX Timer interrupt request. */ + WIFI_MACOTHER_IRQn = 47, /*!< 47 WIFI MAC TX/RX misc interrupt request. */ + WIFI_MACRX_IRQn = 48, /*!< 48 WIFI MAC RX Trigger interrupt request. */ + WIFI_MACTX_IRQn = 49, /*!< 49 WIFI MAC TX Trigger interrupt request. */ + WIFI_MACPROT_IRQn = 50, /*!< 50 WIFI MAC Protocol Trigger interrupt request. */ + WIFI_MACINTGEN_IRQn = 51, /*!< 51 WIFI MAC General interrupt request. */ + WIFI_MACBCN_IRQn = 52, /*!< 52 WIFI MAC Beacon Reception interrupt request. */ + WIFI_RC_IRQn = 53, /*!< 53 WIFI Radio Controller interrupt request. */ + SDEMMC_IRQn = 54, /*!< 54 SDEMMC interrupt request. */ + SDEMMC_WKUP_IRQn = 55, /*!< 55 SDEMMC Wakeup interrupt request. */ + KDMA_CH0_IRQn = 60, /*!< 60 kDMA channel 0 interrupt request */ + KDMA_CH1_IRQn = 61, /*!< 61 kDMA channel 1 interrupt request */ + KDMA_CH2_IRQn = 62, /*!< 62 kDMA channel 2 interrupt request */ + KDMA_CH3_IRQn = 63, /*!< 63 kDMA channel 3 interrupt request */ + KDMA_CH4_IRQn = 64, /*!< 64 kDMA channel 4 interrupt request */ + KDMA_CH5_IRQn = 65, /*!< 65 kDMA channel 5 interrupt request */ + KDMA_CH6_IRQn = 66, /*!< 66 kDMA channel 6 interrupt request */ + KDMA_CH7_IRQn = 67, /*!< 67 kDMA channel 7 interrupt request */ + KDMA_CH8_IRQn = 68, /*!< 68 kDMA channel 8 interrupt request */ + KDMA_CH9_IRQn = 69, /*!< 69 kDMA channel 9 interrupt request */ + KDMA_CH10_IRQn = 70, /*!< 70 kDMA channel 10 interrupt request */ + KDMA_CH11_IRQn = 71 /*!< 71 kDMA channel 11 interrupt request */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0100U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #endif /*CMSIS_STRIP_HEADER*/ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ APU_AUD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief APU_AUD registers (APU_AUD) + */ + +typedef struct /*!< (@ 0x400E0400) APU_AUD Structure */ +{ + union + { + __IOM uint32_t APU_DMIC_CTRL_REG; /*!< (@ 0x00000000) DMIC delay and master mode control */ + + struct + { + __IOM uint32_t DMIC_MASTER_MODE : 1; /*!< [0..0] DMIC master mode0: Slave mode (DMICx_IN_DELAY)1: Master + * mode (DMICx_PHASE) */ + uint32_t : 15; + __IOM uint32_t DMIC1_IN_DELAY : 2; /*!< [17..16] DMIC1 input delay0: No delay1: 6ns2: 12ns3: 18ns */ + uint32_t : 14; + } APU_DMIC_CTRL_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t APU_DMIC_DIV_REG; /*!< (@ 0x0000000C) DMIC clock control */ + + struct + { + __IOM uint32_t DMIC1_CLK_EN : 1; /*!< [0..0] DMIC1 clock divider enable for sampling input data0: + * Disable1: Enable */ + uint32_t : 7; + __IOM uint32_t DMIC_DIV : 5; /*!< [12..8] DMIC out clock divider from AUD_CLK0x00: Divided by + * 320x02: Divided by 20x04: Divided by 4..0x1E: Divided by + * 30 */ + uint32_t : 3; + __IOM uint32_t DMIC1_PHASE : 5; /*!< [20..16] Clock phase shift to sampling DMIC1 input data0x00: + * Sampled at DMIC CLK0x01- (DMIC_DIV -2): Sampled at DMIC_CLK + * delayed with half of DMIC_PHASE cyclesOthers: Reserved */ + uint32_t : 11; + } APU_DMIC_DIV_REG_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t APU_MAIN_DIV_REG; /*!< (@ 0x00000024) Main divider control */ + + struct + { + __IOM uint32_t APU_MAIN_DIV : 12; /*!< [11..0] APU main divider0x0000: divided by 40960x0001: divided + * by 10x0002: divided by 20xFFFF: divided by 4095 */ + __IOM uint32_t APU_MAIN_DIV_EN : 1; /*!< [12..12] APU main divider enable0: Disable1: Enable */ + uint32_t : 19; + } APU_MAIN_DIV_REG_b; + }; + + union + { + __IOM uint32_t APU_SYNC_DIV_SEL_REG; /*!< (@ 0x00000028) APU SYNC control for APU SYNC DIV */ + + struct + { + __IOM uint32_t APU_SYNC_DIV_SEL : 2; /*!< [1..0] SYNC source selection for APU SYNC DIV0x00: SRC1_in_M0x01: + * SRC1_out_M0x02: DAI1_SYNC0x03: MAIN_DIVNote: Refer to the + * datasheet PCM_SYNC Matrix diagram for invalid combinations */ + uint32_t : 30; + } APU_SYNC_DIV_SEL_REG_b; + }; + + union + { + __IOM uint32_t APU_SYNC_DIV_REG; /*!< (@ 0x0000002C) APU SYNC divider control */ + + struct + { + __IOM uint32_t APU_SYNC_DIV : 5; /*!< [4..0] APU SYNC divider0x00: divided by 320x01: divided by 10x1F: + * divided by31 */ + uint32_t : 3; + __IOM uint32_t APU_SYNC_DIV_EN : 1; /*!< [8..8] APU SYNC divider enable0: Disable1: Enable */ + uint32_t : 23; + } APU_SYNC_DIV_REG_b; + }; +} APU_AUD_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ APU_DSP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief APU_DSP registers (APU_DSP) + */ + +typedef struct /*!< (@ 0x400E0800) APU_DSP Structure */ +{ + union + { + __IOM uint32_t APU_CTRL_REG; /*!< (@ 0x00000000) audio IP enable */ + + struct + { + __IOM uint32_t DAI1_EN : 1; /*!< [0..0] DAI1 enable in APU0: Disable1: Enable */ + uint32_t : 31; + } APU_CTRL_REG_b; + }; + + union + { + __IOM uint32_t APU_MUX_CTRL_REG; /*!< (@ 0x00000004) APU mux control */ + + struct + { + uint32_t : 24; + __IOM uint32_t APU_DSP_MUX_CTL : 8; /*!< [31..24] bus1_to_src = APU_DSP_MUX_CTL[0]bus2_to_src = APU_DSP_MUX_CTL[1]src_t + * _bus1 = APU_DSP_MUX_CTL[2]src_to_bus2 = APU_DSP_MUX_CTL[3]src_to_dai + * = APU_DSP_MUX_CTL[4]bus3_to_dai = APU_DSP_MUX_CTL[5]dai_to_src + * = APU_DSP_MUX_CTL[6]dai_to_bus3 = APU_DSP_MUX_CTL[7] */ + } APU_MUX_CTRL_REG_b; + }; + + union + { + __IOM uint32_t APU_SYNC_SRC1IN_SEL_REG; /*!< (@ 0x00000008) APU SYNC control for SRC1 IN */ + + struct + { + __IOM uint32_t SRC1_IN_A_SEL : 2; /*!< [1..0] SYNC source selection for SRC1_IN_A0x00: SRC1_in_M0x01: + * SRC1_out_M0x02: DAI1_SYNC0x03: SYNC_DIVNote: Refer to the + * datasheet APU_SYNC Matrix diagram for invalid combinations */ + uint32_t : 30; + } APU_SYNC_SRC1IN_SEL_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t APU_SYNC_SRC1OUT_SEL_REG; /*!< (@ 0x00000010) APU SYNC control for SRC1 OUT */ + + struct + { + __IOM uint32_t SRC1_OUT_A_SEL : 2; /*!< [1..0] SYNC source selection for SRC1_OUT_Asame as SRC1_IN_A_SEL */ + uint32_t : 30; + } APU_SYNC_SRC1OUT_SEL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t APU_PCM_CLK_REG; /*!< (@ 0x00000020) PCM clock enable */ + + struct + { + __IOM uint32_t PCM1_CLK_EN : 1; /*!< [0..0] DAI clock divider enable0: Disable1: Enable */ + uint32_t : 1; + __IOM uint32_t PCM_USE_FDIV : 1; /*!< [2..2] PCM_USE_FDIV */ + uint32_t : 29; + } APU_PCM_CLK_REG_b; + }; + + union + { + __IOM uint32_t APU_PCM1_DIV_REG; /*!< (@ 0x00000024) PCM clock divider control */ + + struct + { + __IOM uint32_t PCM1_DIV : 7; /*!< [6..0] PCM_DIV clock divider0x0: divide by 80x1: divide by 10x2: + * divide by 20x3: divide by 30x4: divide by 40x5: divide + * by 50x6: divide by 60x7: divide by 70x8-0x7F:reserved */ + uint32_t : 25; + } APU_PCM1_DIV_REG_b; + }; + + union + { + __IOM uint32_t APU_PCM1_FDIV_REG; /*!< (@ 0x00000028) APU_PCM1_FDIV_REG */ + + struct + { + __IOM uint32_t PCM1_FDIV : 32; /*!< [31..0] PCM1_FDIV */ + } APU_PCM1_FDIV_REG_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t APU_PCM1_FDIV_HIGH_REG; /*!< (@ 0x00000034) APU_PCM1_FDIV_HIGH_REG */ + + struct + { + __IOM uint32_t PCM1_FDIV_HIGH : 16; /*!< [15..0] PCM1_FDIV_HIGH */ + uint32_t : 16; + } APU_PCM1_FDIV_HIGH_REG_b; + }; +} APU_DSP_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ AUXADC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief AUXADC registers (AUXADC) + */ + +typedef struct /*!< (@ 0x40090500) AUXADC Structure */ +{ + union + { + __IOM uint32_t XADC12B_CTRL_REG; /*!< (@ 0x00000000) AuxADC 12b Control register */ + + struct + { + __IOM uint32_t ADC12B_RESET : 1; /*!< [0..0] ASIC Aux ADC12B control signal for Reset.0: no reset1: + * reset */ + __IOM uint32_t ADC12B_PWRDOEN : 1; /*!< [1..1] ASIC Aux ADC12B control signal for Power down.0: no power + * down1: power downFPGA Aux ADC12B Power on,0: power off1: + * power on */ + __IOM uint32_t ADC12B_CS : 3; /*!< [4..2] ASIC Aux ADC12B control signal.CS[2:0]: Select input + * pin,0: VIN11: VIN22: for ADC testFPGA Aux ADC7472 for 12-bit + * modebit[2] : XADC_AD7472_CS */ + __IOM uint32_t ADC12B_TRIM : 3; /*!< [7..5] ASIC Aux ADC12B control signal.TRIM[2:0]: Trim VREF Voltage. */ + __IOM uint32_t ADC12B_DATA_FORMAT : 1; /*!< [8..8] ASIC aux adc12b data format0: 2's complemnt1: offset + * binary */ + uint32_t : 23; + } XADC12B_CTRL_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SWITCHING_MODE_REG; /*!< (@ 0x00000008) Switching mode register */ + + struct + { + __IOM uint32_t SWITCHING_MODE : 9; /*!< [8..0] AUX ADC switching mode :if change setting value, should + * set "0x00" -> "0x1xx"[8] : switching auto enable[7] : 12-bit + * 4th enable[6] : 12-bit 3rd enable[5] : 12-bit 2nd enable[4] + * : 12-bit 1st enable */ + uint32_t : 23; + } SWITCHING_MODE_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_THR_INTR_MASK_REG; /*!< (@ 0x0000000C) Interrupt Mask register */ + + struct + { + __IOM uint32_t OVER_THR_FIFO0_MASK : 1; /*!< [0..0] Interrupt mask enable for FIFO0Refer to AX12B_INT_THR_OVER_REG */ + __IOM uint32_t OVER_THR_FIFO1_MASK : 1; /*!< [1..1] Interrupt mask enable for FIFO1Refer to AX12B_INT_THR_OVER_REG */ + __IOM uint32_t OVER_THR_FIFO2_MASK : 1; /*!< [2..2] Interrupt mask enable for FIFO2Refer to AX12B_INT_THR_OVER_REG */ + __IOM uint32_t OVER_THR_FIFO3_MASK : 1; /*!< [3..3] Interrupt mask enable for FIFO3Refer to AX12B_INT_THR_OVER_REG */ + __IOM uint32_t UNDER_THR_FIFO0_MASK : 1; /*!< [4..4] Interrupt mask enable for FIFO0Refer to AX12B_INT_THR_UNDER_REG */ + __IOM uint32_t UNDER_THR_FIFO1_MASK : 1; /*!< [5..5] Interrupt mask enable for FIFO1Refer to AX12B_INT_THR_UNDER_REG */ + __IOM uint32_t UNDER_THR_FIFO2_MASK : 1; /*!< [6..6] Interrupt mask enable for FIFO2Refer to AX12B_INT_THR_UNDER_REG */ + __IOM uint32_t UNDER_THR_FIFO3_MASK : 1; /*!< [7..7] Interrupt mask enable for FIFO3Refer to AX12B_INT_THR_UNDER_REG */ + __IOM uint32_t DIFF_THR_FIFO0_MASK : 1; /*!< [8..8] Interrupt mask enable for FIFO0Refer to AX12B_INT_THR_DIFF_REG */ + __IOM uint32_t DIFF_THR_FIFO1_MASK : 1; /*!< [9..9] Interrupt mask enable for FIFO1Refer to AX12B_INT_THR_DIFF_REG */ + __IOM uint32_t DIFF_THR_FIFO2_MASK : 1; /*!< [10..10] Interrupt mask enable for FIFO2Refer to AX12B_INT_THR_DIFF_REG */ + __IOM uint32_t DIFF_THR_FIFO3_MASK : 1; /*!< [11..11] Interrupt mask enable for FIFO3Refer to AX12B_INT_THR_DIFF_REG */ + uint32_t : 20; + } XADC12B_THR_INTR_MASK_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_THR_INTR_CLR_REG; /*!< (@ 0x00000010) Interrupt Clear register */ + + struct + { + __IOM uint32_t OVER_THR_FIFO0_CLR : 1; /*!< [0..0] Over Level interrupt clear of FIFO0 */ + __IOM uint32_t OVER_THR_FIFO1_CLR : 1; /*!< [1..1] Over Level interrupt clear of FIFO1 */ + __IOM uint32_t OVER_THR_FIFO2_CLR : 1; /*!< [2..2] Over Level interrupt clear of FIFO2 */ + __IOM uint32_t OVER_THR_FIFO3_CLR : 1; /*!< [3..3] Over Level interrupt clear of FIFO3 */ + __IOM uint32_t UNDER_THR_FIFO0_CLR : 1; /*!< [4..4] Under Level interrupt clear of FIFO0 */ + __IOM uint32_t UNDER_THR_FIFO1_CLR : 1; /*!< [5..5] Under Level interrupt clear of FIFO1 */ + __IOM uint32_t UNDER_THR_FIFO2_CLR : 1; /*!< [6..6] Under Level interrupt clear of FIFO2 */ + __IOM uint32_t UNDER_THR_FIFO3_CLR : 1; /*!< [7..7] Under Level interrupt clear of FIFO3 */ + __IOM uint32_t DIFF_THR_FIFO0_CLR : 1; /*!< [8..8] Threshold Difference interrupt clear of FIFO0 */ + __IOM uint32_t DIFF_THR_FIFO1_CLR : 1; /*!< [9..9] Threshold Difference interrupt clear of FIFO1 */ + __IOM uint32_t DIFF_THR_FIFO2_CLR : 1; /*!< [10..10] Threshold Difference interrupt clear of FIFO2 */ + __IOM uint32_t DIFF_THR_FIFO3_CLR : 1; /*!< [11..11] Threshold Difference interrupt clear of FIFO3 */ + uint32_t : 20; + } XADC12B_THR_INTR_CLR_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_FIFO_INTR_MASK_REG; /*!< (@ 0x00000014) FIFO level Interrupt Mask register */ + + struct + { + __IOM uint32_t HL_FIFO0_MASK : 1; /*!< [0..0] Interrupt mask for half level of FIFO 0 */ + __IOM uint32_t HL_FIFO1_MASK : 1; /*!< [1..1] Interrupt mask for half level of FIFO 1 */ + __IOM uint32_t HL_FIFO2_MASK : 1; /*!< [2..2] Interrupt mask for half level of FIFO 2 */ + __IOM uint32_t HL_FIFO3_MASK : 1; /*!< [3..3] Interrupt mask for half level of FIFO 3 */ + __IOM uint32_t FL_FIFO0_MASK : 1; /*!< [4..4] Interrupt mask for full level of FIFO 0 */ + __IOM uint32_t FL_FIFO1_MASK : 1; /*!< [5..5] Interrupt mask for full level of FIFO 1 */ + __IOM uint32_t FL_FIFO2_MASK : 1; /*!< [6..6] Interrupt mask for full level of FIFO 2 */ + __IOM uint32_t FL_FIFO3_MASK : 1; /*!< [7..7] Interrupt mask for full level of FIFO 3 */ + uint32_t : 24; + } XADC12B_FIFO_INTR_MASK_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_INTR_STATUS_REG; /*!< (@ 0x00000018) Interrupt Status register */ + + struct + { + __IM uint32_t HL_FIFO0_STS : 1; /*!< [0..0] Interrupt status for half level of FIFO 0 */ + __IM uint32_t HL_FIFO1_STS : 1; /*!< [1..1] Interrupt status for half level of FIFO 1 */ + __IM uint32_t HL_FIFO2_STS : 1; /*!< [2..2] Interrupt status for half level of FIFO 2 */ + __IM uint32_t HL_FIFO3_STS : 1; /*!< [3..3] Interrupt status for half level of FIFO 3 */ + __IM uint32_t FL_FIFO0_STS : 1; /*!< [4..4] Interrupt status for full level of FIFO 0 */ + __IM uint32_t FL_FIFO1_STS : 1; /*!< [5..5] Interrupt status for full level of FIFO 1 */ + __IM uint32_t FL_FIFO2_STS : 1; /*!< [6..6] Interrupt status for full level of FIFO 2 */ + __IM uint32_t FL_FIFO3_STS : 1; /*!< [7..7] Interrupt status for full level of FIFO 3 */ + __IM uint32_t OVER_THR_FIFO0_STS : 1; /*!< [8..8] Interrupt status for Threshold Over of FIFO 0 */ + __IM uint32_t OVER_THR_FIFO1_STS : 1; /*!< [9..9] Interrupt status for Threshold Over of FIFO 1 */ + __IM uint32_t OVER_THR_FIFO2_STS : 1; /*!< [10..10] Interrupt status for Threshold Over of FIFO 2 */ + __IM uint32_t OVER_THR_FIFO3_STS : 1; /*!< [11..11] Interrupt status for Threshold Over of FIFO 3 */ + __IM uint32_t UNDER_THR_FIFO0_STS : 1; /*!< [12..12] Interrupt status for Threshold Under of FIFO 0 */ + __IM uint32_t UNDER_THR_FIFO1_STS : 1; /*!< [13..13] Interrupt status for Threshold Under of FIFO 1 */ + __IM uint32_t UNDER_THR_FIFO2_STS : 1; /*!< [14..14] Interrupt status for Threshold Under of FIFO 2 */ + __IM uint32_t UNDER_THR_FIFO3_STS : 1; /*!< [15..15] Interrupt status for Threshold Under of FIFO 3 */ + __IM uint32_t DIFF_THR_FIFO0_STS : 1; /*!< [16..16] Interrupt status for Threshold Difference of FIFO 0 */ + __IM uint32_t DIFF_THR_FIFO1_STS : 1; /*!< [17..17] Interrupt status for Threshold Difference of FIFO 1 */ + __IM uint32_t DIFF_THR_FIFO2_STS : 1; /*!< [18..18] Interrupt status for Threshold Difference of FIFO 2 */ + __IM uint32_t DIFF_THR_FIFO3_STS : 1; /*!< [19..19] Interrupt status for Threshold Difference of FIFO 3 */ + uint32_t : 12; + } XADC12B_INTR_STATUS_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_DMA_EN_REG; /*!< (@ 0x0000001C) FIFO DMA enable register */ + + struct + { + __IOM uint32_t FIFO0_ENABLE : 1; /*!< [0..0] FIFO 0 DMA enable0: diable1: enable */ + __IOM uint32_t FIFO1_ENABLE : 1; /*!< [1..1] FIFO 1 DMA enable0: diable1: enable */ + __IOM uint32_t FIFO2_ENABLE : 1; /*!< [2..2] FIFO 2 DMA enable0: diable1: enable */ + __IOM uint32_t FIFO3_ENABLE : 1; /*!< [3..3] FIFO 3 DMA enable0: diable1: enable */ + uint32_t : 28; + } XADC12B_DMA_EN_REG_b; + }; + + union + { + __IOM uint32_t FIFO0_DMA_DATA_REG; /*!< (@ 0x00000020) ADC12b sample data register */ + + struct + { + __IM uint32_t FIFO0_DMA_DATA : 16; /*!< [15..0] FIFO0 DMA data,Intterupt indicate 4 consecutive sampled + * data */ + uint32_t : 16; + } FIFO0_DMA_DATA_REG_b; + }; + + union + { + __IOM uint32_t FIFO1_DMA_DATA_REG; /*!< (@ 0x00000024) ADC16b sample data register */ + + struct + { + __IM uint32_t FIFO1_DMA_DATA : 16; /*!< [15..0] FIFO1 DMA data,Intterupt indicate 4 consecutive sampled + * data */ + uint32_t : 16; + } FIFO1_DMA_DATA_REG_b; + }; + + union + { + __IOM uint32_t FIFO2_DMA_DATA_REG; /*!< (@ 0x00000028) ADC12b sample data register for FPGA */ + + struct + { + __IM uint32_t FIFO2_DMA_DATA : 16; /*!< [15..0] FIFO2 DMA data,Intterupt indicate 4 consecutive sampled + * data */ + uint32_t : 16; + } FIFO2_DMA_DATA_REG_b; + }; + + union + { + __IOM uint32_t FIFO3_DMA_DATA_REG; /*!< (@ 0x0000002C) ADC16b sample data register for FPGA */ + + struct + { + __IM uint32_t FIFO3_DMA_DATA : 16; /*!< [15..0] FIFO3 DMA data,Intterupt indicate 4 consecutive sampled + * data */ + uint32_t : 16; + } FIFO3_DMA_DATA_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_RM_SAMPLE_REG; /*!< (@ 0x00000030) Removing Sample register */ + + struct + { + uint32_t : 8; + __IOM uint32_t XADC12B_RM_SAMPLE : 8; /*!< [15..8] The number of removing initial samples of AuxAdc 12B */ + uint32_t : 16; + } XADC12B_RM_SAMPLE_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_ST_SAMPLE_REG; /*!< (@ 0x00000034) Sampleing interval register */ + + struct + { + uint32_t : 4; + __IOM uint32_t XADC12B_SP_INTERVAL : 4; /*!< [7..4] The number of sampling interval of aux adc12B in Auto + * switching mode0, 1 : internal none2~15 : N-1 interval sampling */ + uint32_t : 24; + } XADC12B_ST_SAMPLE_REG_b; + }; + + union + { + __IOM uint32_t XADC12B_INT_THR_OVER_REG; /*!< (@ 0x00000038) AuxADC 12b Over Threshold level register */ + + struct + { + __IOM uint32_t OVER_THR_EN : 1; /*!< [0..0] Over Threshold enable0: disable1: enable */ + __IOM uint32_t OVER_THR_VAL : 15; /*!< [15..1] Over Threshould value of interrupt */ + uint32_t : 16; + } XADC12B_INT_THR_OVER_REG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t XADC12B_INT_THR_UNDER_REG; /*!< (@ 0x00000040) AuxADC 12b Under Threshold level register */ + + struct + { + __IOM uint32_t UNDER_THR_EN : 1; /*!< [0..0] Under Threshold enable0: disable1: enable */ + __IOM uint32_t UNDER_THR_VAL : 15; /*!< [15..1] Under Threshould value of interrupt */ + uint32_t : 16; + } XADC12B_INT_THR_UNDER_REG_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t XADC12B_INT_THR_DIFF_REG; /*!< (@ 0x00000048) AuxADC 12b Difference Threshold level register */ + + struct + { + __IOM uint32_t DIFF_THR_EN : 1; /*!< [0..0] Difference Threshold enable0: disable1: enable */ + __IOM uint32_t DIFF_THR_VAL : 15; /*!< [15..1] Difference Threshould value of interrupt */ + uint32_t : 16; + } XADC12B_INT_THR_DIFF_REG_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t FIFO0_DATA_CURR_REG; /*!< (@ 0x00000050) AuxAdc 12b data register */ + + struct + { + __IM uint32_t FIFO0_CURR_DATA : 16; /*!< [15..0] Current FIFO 0 ADC data */ + uint32_t : 16; + } FIFO0_DATA_CURR_REG_b; + }; + + union + { + __IOM uint32_t FIFO1_DATA_CURR_REG; /*!< (@ 0x00000054) AuxAdc 16b data register */ + + struct + { + __IM uint32_t FIFO1_CURR_DATA : 16; /*!< [15..0] Current FIFO 1 ADC data */ + uint32_t : 16; + } FIFO1_DATA_CURR_REG_b; + }; + + union + { + __IOM uint32_t FIFO2_DATA_CURR_REG; /*!< (@ 0x00000058) AuxAdc 12b data register */ + + struct + { + __IM uint32_t FIFO2_CURR_DATA : 16; /*!< [15..0] Current FIFO 2 ADC data */ + uint32_t : 16; + } FIFO2_DATA_CURR_REG_b; + }; + + union + { + __IOM uint32_t FIFO3_DATA_CURR_REG; /*!< (@ 0x0000005C) AuxAdc 16b data register */ + + struct + { + __IM uint32_t FIFO3_CURR_DATA : 16; /*!< [15..0] Current FIFO 3 ADC data */ + uint32_t : 16; + } FIFO3_DATA_CURR_REG_b; + }; + + union + { + __IOM uint32_t TIMESTAMP_CTRL_REG; /*!< (@ 0x00000060) Time Stamp register */ + + struct + { + uint32_t : 8; + __IOM uint32_t TIMESTAMP_12B : 4; /*!< [11..8] Time Stamp base count level[11:8] : 12-bit ADC (default + * = 'd5) */ + uint32_t : 20; + } TIMESTAMP_CTRL_REG_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t FXADC_CLK_CTRL_REG; /*!< (@ 0x00000070) Clock control register for FPGA */ + + struct + { + uint32_t : 8; + __IOM uint32_t FXADC12B_CLK : 8; /*!< [15..8] just for FPGA version, 12-bit ADC model[15:12] : XADC_AD7472_CONVST0= + * PCLK/2, , 8=PCLK/512[11:8] : for XADC_AD7472_CLK0= PCLK, + * 1=PCLK/2, , 9=PCLK/512 */ + uint32_t : 16; + } FXADC_CLK_CTRL_REG_b; + }; +} AUXADC_Type; /*!< Size = 116 (0x74) */ + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CACHE registers (CACHE) + */ + +typedef struct /*!< (@ 0x0E010000) CACHE Structure */ +{ + union + { + __IOM uint32_t CACHE_CTRL1_REG; /*!< (@ 0x00000000) CACHE_CTRL1_REG */ + + struct + { + __IM uint32_t CACHE_FLUSH : 1; /*!< [0..0] CACHE_FLUSH */ + __IM uint32_t CACHE_RES1 : 1; /*!< [1..1] CACHE_RES1 */ + uint32_t : 30; + } CACHE_CTRL1_REG_b; + }; + + union + { + __IOM uint32_t CACHE_LNSIZECFG_REG; /*!< (@ 0x00000004) CACHE_LNSIZECFG_REG */ + + struct + { + __IM uint32_t CACHE_LINE : 2; /*!< [1..0] CACHE_LINE */ + uint32_t : 30; + } CACHE_LNSIZECFG_REG_b; + }; + + union + { + __IOM uint32_t CACHE_ASSOCCFG_REG; /*!< (@ 0x00000008) CACHE_ASSOCCFG_REG */ + + struct + { + __IM uint32_t CACHE_ASSOC : 2; /*!< [1..0] CACHE_ASSOC */ + uint32_t : 30; + } CACHE_ASSOCCFG_REG_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t CACHE_CTRL2_REG; /*!< (@ 0x00000020) Cache control register 2 (only Word (32-bits) + * access supported). */ + + struct + { + __IOM uint32_t CACHE_LEN : 12; /*!< [11..0] Length of OQSPI FLASH cacheable memory.N*64 KBytes. + * N = 0 to 2048, incl. 2048 (max. of 128 Mbytes).Setting + * CACHE_LEN=0 disables the caching.Note 1: The max. relevant + * CACHE_LEN setting depends on the chosen Flash region (program) + * size.Note 2: The first block (CACHE_LEN=1) includes the + * memory space specified by CACHE_FLASH_REG[FLASH_REGION_OFFSET]. */ + __IOM uint32_t CACHE_WEN : 1; /*!< [12..12] 0: Cache Data and TAG memory read only.1: Cache Data + * and TAG memory read/write.The Data and TAG memory are only + * updated by the cache controller.There is no HW protection + * to prevent unauthorized access by the ARM.Note 1: When + * accessing the memory mapped Cache Data and TAG memory (which + * is only allowed for debugging purposes) only 32 bits access + * is supported.Note 2: SYS_CTRL_REG[CACHERAM_MUX] must be + * set to '0' before accessing the memory mapped Cache Data + * and TAG memory.See also th */ + __IOM uint32_t CACHE_CGEN : 1; /*!< [13..13] 0: Cache controller clock gating is not enabled.1: + * Cache controller clock gating is enabled (enabling power + * saving). */ + __IOM uint32_t CACHE_CWF_DISABLE : 1; /*!< [14..14] 0: Default.1: The cache line refill is performed with + * INCR type burst and "Critical Word First" is disabled.Note:This + * bit is only relevant for executing from QSPI Flash (when + * set to '1' it will improve performance).This bit should + * be kept on '0' for executing from eFlash. */ + __IOM uint32_t CACHE_MHCLKEN_DISABLE : 1; /*!< [15..15] 0: Default.1: The "m_HCLK_EN" input is ignored and + * the controller avoids inserting m_HTRANS=BUSY because of + * wait states.Note:This bit is only relevant for executing + * from QSPI Flash (when set to '1' it will improve performance). + * This bit should be kept on '0' for executing from eFlash. */ + __IOM uint32_t CACHE_USE_FULL_DB_RANGE : 2; /*!< [17..16] 00: CACHERAM (mirrored) read/write and NO use of the + * full 184 bits databus (for executing program code or extension + * of the SysRAM with the Cache RAM).In this mode 8 bits, + * 16 bits and 32 bits write access is supported.01: CACHERAM + * (mirrored) read and use of the full 184 bits databus of + * 'SRAM_1_0' (for testing and debugging purposes).In this + * mode only 32 bits write access is supported.10: CACHERAM + * (mirrored) read and use of the full 184 bits databus of + * 'SRAM_3_2' (for testing and de */ + __IOM uint32_t CACHE_FLUSH_DISABLE : 1; /*!< [18..18] 0: Default.1: Flushing of the Cache memory is disabled + * when SYS_CTRL_REG[CACHERAM_MUX] is switched from '1' to + * '0'.Note: Setting this bit to '1' is only allowed for debugging + * purposes. */ + __IOM uint32_t CACHE_FLUSHED : 1; /*!< [19..19] 0: Cache is not flushed yet.1: Cache is flushed.Note + * 1: Setting and clearing of this (status) bit field is automatically + * done by the hardware. It is set on the falling edge and + * cleared on the rising edge of the (Cache Controller) CACHE_RAM_INIT + * signal.Note 2: When the Cache is flushed by disabling and + * enabling the Cache Controller with a SYS_CTRL_REG[CACHERAM_MUX] + * sequence of 1 -> 0 -> 1, the CACHE_FLUSHED bit can also + * be cleared first by the software (if needed) with writing + * a CACHE_CTRL */ + __IM uint32_t CACHE_RAM_INIT : 1; /*!< [20..20] Cache Controller RO status bit.0: Default.1: Set to + * '1' when SRAM is being initialized (i.e. being flushed).Note: + * The flushing of the cache memory takes 256 HCLK cycles. */ + __IM uint32_t CACHE_READY : 1; /*!< [21..21] Cache Controller RO status bit.0: Default.1: Set to + * '1' when CACHE_CTRL is enabled, initialized and immediately + * ready for a cacheable access to service. */ + __IOM uint32_t CACHE_ROM_REGION_EN : 1; /*!< [22..22] cache enable for the ROM region (0x0F02_0000 ~ 0x0F05_FFFF)this + * option is valid only if the cache is enabled. */ + uint32_t : 9; + } CACHE_CTRL2_REG_b; + }; + + union + { + __IOM uint32_t CACHE_CTRL3_REG; /*!< (@ 0x00000024) CACHE_CTRL3_REG */ + + struct + { + __IM uint32_t CACHE_ASSOCIATIVITY_RESET_VALUE : 2; /*!< [1..0] CACHE_ASSOCIATIVITY_RESET_VALUE */ + __IM uint32_t CACHE_LINE_SIZE_RESET_VALUE : 2; /*!< [3..2] CACHE_LINE_SIZE_RESET_VALUE */ + __IM uint32_t CACHE_RAM_SIZE_RESET_VALUE : 3; /*!< [6..4] CACHE_RAM_SIZE_RESET_VALUE */ + __IM uint32_t CACHE_CONTROLLER_RESET : 1; /*!< [7..7] CACHE_CONTROLLER_RESET */ + __IOM uint32_t CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS : 1; /*!< [8..8] CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS */ + uint32_t : 23; + } CACHE_CTRL3_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_HITS_REG; /*!< (@ 0x00000028) Cache MRM (Miss Rate Monitor) HITS register (only + * Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_HITS : 32; /*!< [31..0] Contains the amount of cache hits. */ + } CACHE_MRM_HITS_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_MISSES_REG; /*!< (@ 0x0000002C) Cache MRM (Miss Rate Monitor) MISSES register + * (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_MISSES : 32; /*!< [31..0] Contains the amount of cache misses. */ + } CACHE_MRM_MISSES_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_CTRL_REG; /*!< (@ 0x00000030) Cache MRM (Miss Rate Monitor) CONTROL register + * (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_START : 1; /*!< [0..0] 0: Freeze the "misses/hits" counters and reset the time + * interval counter to the programmed value in CACHE_MRM_TINT_REG.1: + * Enables the counters.Note: In case CACHE_MRM_CTRL_REG[MRM_START] + * is set to '1' and CACHE_MRM_TINT_REG (!=0) is used for + * the MRM interrupt generation, the time interval counter + * counts down (on a fixed reference clock of 32 MHz) until + * it's '0'. At that time CACHE_MRM_CTRL_REG[MRM_START] will + * be reset automatically to '0' by the MRM hardware and the + * MRM interrupt will be generate */ + __IOM uint32_t MRM_IRQ_MASK : 1; /*!< [1..1] 0: Disables interrupt generation.1: Enables interrupt + * generation.Note: The Cache MRM generates a pulse-sensitive + * interrupt towards the ARM processor, */ + __IOM uint32_t MRM_IRQ_TINT_STATUS : 1; /*!< [2..2] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the time interval counter reached + * the end (time interval != 0). */ + __IOM uint32_t MRM_IRQ_MISSES_THRES_STATUS : 1; /*!< [3..3] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the number of cache misses reached + * the programmed threshold (threshold != 0). */ + __IOM uint32_t MRM_IRQ_HITS_THRES_STATUS : 1; /*!< [4..4] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the number of cache hits reached the + * programmed threshold (threshold != 0). */ + uint32_t : 27; + } CACHE_MRM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_TINT_REG; /*!< (@ 0x00000034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register + * (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_TINT : 19; /*!< [18..0] Defines the time interval for the monitoring in (bus + * clock/4) clock cycles. See also the description of CACHE_MRM_CTRL_REG[MRM + * IRQ_TINT_STATUS].Note: When MRM_TINT=0 (unrealistic value), + * no interrupt will be generated. */ + uint32_t : 13; + } CACHE_MRM_TINT_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_MISSES_THRES_REG; /*!< (@ 0x00000038) Cache MRM (Miss Rate Monitor) THRESHOLD register + * (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_MISSES_THRES : 32; /*!< [31..0] Defines the misses threshold to trigger the interrupt + * generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_MISSES + * THRES_STATUS].Note: When MRM_MISSES_THRES=0 (unrealistic + * value), no interrupt will be generated. */ + } CACHE_MRM_MISSES_THRES_REG_b; + }; + + union + { + __IOM uint32_t CACHE_MRM_HITS_THRES_REG; /*!< (@ 0x0000003C) Cache MRM (Miss Rate Monitor) HITS THRESHOLD + * register (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t MRM_HITS_THRES : 32; /*!< [31..0] Defines the hits threshold to trigger the interrupt + * generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_HITS_T + * RES_STATUS].Note: When MRM_HITS_THRES=0 (unrealistic value), + * no interrupt will be generated. */ + } CACHE_MRM_HITS_THRES_REG_b; + }; + + union + { + __IOM uint32_t CACHE_FLASH_REG; /*!< (@ 0x00000040) Cache QSPI Flash program size and base address + * register (only Word (32-bits) access supported). */ + + struct + { + __IOM uint32_t FLASH_REGION_SIZE : 4; /*!< [3..0] Flash region size.Default value is '1' (0.5 MBytes).0 + * = 0.25 MBytes,1 = 0.5 MBytes,2 = 1 MBytes,3 = 2 MBytes,4 + * = 4 MBytes,5 = 8 MBytes,6 = 16 MBytes,7 = 32 MBytes,8 = + * 64 MBytes,9 = 128 MBytes.These register bits are retained.Note + * 1: The updated value takes effect only after a software + * reset.Note 2: See for the max. region (program) size the + * memory map. */ + __IOM uint32_t FLASH_REGION_OFFSET : 12; /*!< [15..4] Flash region offset address (in words).This value is + * added to the Flash (CPU) address bits [13:2].These register + * bits are retained.Note 1: The updated value takes effect + * only after a software reset. */ + __IOM uint32_t FLASH_REGION_BASE : 16; /*!< [31..16] These bits correspond with the Flash region base address + * bits [31:16].Default value is '0x1800'.The Flash region + * base address bits [31:27] are fixed to '0b00011', supporting + * the range of 0x1800-0x1FFF'.These register bits are retained.Note + * 1: The updated value takes effect only after a software + * reset.Note 2 The Flash region base address setting depends + * on the chosen Flash region size. */ + } CACHE_FLASH_REG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CACHE_MRM_HITS1WS_REG; /*!< (@ 0x00000048) Cache MRM (Miss Rate Monitor) HITS with 1 Wait + * State register (only Word (32-bits) access + * supported). */ + + struct + { + __IOM uint32_t MRM_HITS1WS : 32; /*!< [31..0] Contains the amount of cache hits. */ + } CACHE_MRM_HITS1WS_REG_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SWD_RESET_REG; /*!< (@ 0x00000050) SWD HW reset control register (only Word (32-bits) + * access supported). */ + + struct + { + __OM uint32_t SWD_HW_RESET_REQ : 1; /*!< [0..0] 0: default.1: HW reset request (from the debugger tool). + * The register is automatically reset with a HW_RESET.This + * bit can only be accessed by the debugger software and not + * by the application. */ + uint32_t : 31; + } SWD_RESET_REG_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t CACHE_CPU_M_HADDR_REG; /*!< (@ 0x00000060) CACHE_CPU_M_HADDR_REG */ + + struct + { + __IM uint32_t CACHE_CPU_M_HADDR : 32; /*!< [31..0] CACHE_CPU_M_HADDR */ + } CACHE_CPU_M_HADDR_REG_b; + }; + + union + { + __IOM uint32_t CACHE_M_HADDR_MAP0_REG; /*!< (@ 0x00000064) CACHE_M_HADDR_MAP0_REG */ + + struct + { + __IM uint32_t CACHE_M_HADDR_MAP0 : 32; /*!< [31..0] CACHE_M_HADDR_MAP0 */ + } CACHE_M_HADDR_MAP0_REG_b; + }; + + union + { + __IOM uint32_t CACHE_CTRLR_M_HADDR_REG; /*!< (@ 0x00000068) CACHE_CTRLR_M_HADDR_REG */ + + struct + { + __IM uint32_t CACHE_CTRLR_M_HADDR : 32; /*!< [31..0] CACHE_CTRLR_M_HADDR */ + } CACHE_CTRLR_M_HADDR_REG_b; + }; +} CACHE_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ CC312 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CC312 registers (CC312) + */ + +typedef struct /*!< (@ 0x400F0000) CC312 Structure */ +{ + union + { + __IOM uint32_t CC312_MEMORY_MAP0_REG; /*!< (@ 0x00000000) This register maps the virtual register R0 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP0 : 10; /*!< [10..1] Contains the physical address in memory to map the R0 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP0_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP1_REG; /*!< (@ 0x00000004) This register maps the virtual register R1 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP1 : 10; /*!< [10..1] Contains the physical address in memory to map the R1 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP1_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP2_REG; /*!< (@ 0x00000008) This register maps the virtual register R2 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP2 : 10; /*!< [10..1] Contains the physical address in memory to map the R2 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP2_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP3_REG; /*!< (@ 0x0000000C) This register maps the virtual register R3 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP3 : 10; /*!< [10..1] Contains the physical address in memory to map the R3 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP3_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP4_REG; /*!< (@ 0x00000010) This register maps the virtual register R4 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP4 : 10; /*!< [10..1] Contains the physical address in memory to map the R4 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP4_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP5_REG; /*!< (@ 0x00000014) This register maps the virtual register R5 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP5 : 10; /*!< [10..1] Contains the physical address in memory to map the R5 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP5_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP6_REG; /*!< (@ 0x00000018) This register maps the virtual register R6 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP6 : 10; /*!< [10..1] Contains the physical address in memory to map the R6 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP6_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP7_REG; /*!< (@ 0x0000001C) This register maps the virtual register R7 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP7 : 10; /*!< [10..1] Contains the physical address in memory to map the R7 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP7_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP8_REG; /*!< (@ 0x00000020) This register maps the virtual register R8 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP8 : 10; /*!< [10..1] Contains the physical address in memory to map the R8 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP8_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP9_REG; /*!< (@ 0x00000024) This register maps the virtual register R9 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP9 : 10; /*!< [10..1] Contains the physical address in memory to map the R9 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP9_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP10_REG; /*!< (@ 0x00000028) This register maps the virtual register R10 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP10 : 10; /*!< [10..1] Contains the physical address in memory to map the R10 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP10_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP11_REG; /*!< (@ 0x0000002C) This register maps the virtual register R11 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP11 : 10; /*!< [10..1] Contains the physical address in memory to map the R11 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP11_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP12_REG; /*!< (@ 0x00000030) This register maps the virtual register R12 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP12 : 10; /*!< [10..1] Contains the physical address in memory to map the R12 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP12_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP13_REG; /*!< (@ 0x00000034) This register maps the virtual register R13 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP13 : 10; /*!< [10..1] Contains the physical address in memory to map the R13 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP13_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP14_REG; /*!< (@ 0x00000038) This register maps the virtual register R14 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP14 : 10; /*!< [10..1] Contains the physical address in memory to map the R14 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP14_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP15_REG; /*!< (@ 0x0000003C) This register maps the virtual register R15 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP15 : 10; /*!< [10..1] Contains the physical address in memory to map the R15 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP15_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP16_REG; /*!< (@ 0x00000040) This register maps the virtual register R16 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP16 : 10; /*!< [10..1] Contains the physical address in memory to map the R16 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP16_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP17_REG; /*!< (@ 0x00000044) This register maps the virtual register R17 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP17 : 10; /*!< [10..1] Contains the physical address in memory to map the R17 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP17_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP18_REG; /*!< (@ 0x00000048) This register maps the virtual register R18 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP18 : 10; /*!< [10..1] Contains the physical address in memory to map the R18 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP18_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP19_REG; /*!< (@ 0x0000004C) This register maps the virtual register R19 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP19 : 10; /*!< [10..1] Contains the physical address in memory to map the R19 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP19_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP20_REG; /*!< (@ 0x00000050) This register maps the virtual register R20 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP20 : 10; /*!< [10..1] Contains the physical address in memory to map the R20 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP20_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP21_REG; /*!< (@ 0x00000054) This register maps the virtual register R21 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP21 : 10; /*!< [10..1] Contains the physical address in memory to map the R21 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP21_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP22_REG; /*!< (@ 0x00000058) This register maps the virtual register R22 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP22 : 10; /*!< [10..1] Contains the physical address in memory to map the R22 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP22_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP23_REG; /*!< (@ 0x0000005C) This register maps the virtual register R23 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP23 : 10; /*!< [10..1] Contains the physical address in memory to map the R23 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP23_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP24_REG; /*!< (@ 0x00000060) This register maps the virtual register R24 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP24 : 10; /*!< [10..1] Contains the physical address in memory to map the R24 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP24_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP25_REG; /*!< (@ 0x00000064) This register maps the virtual register R25 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP25 : 10; /*!< [10..1] Contains the physical address in memory to map the R25 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP25_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP26_REG; /*!< (@ 0x00000068) This register maps the virtual register R26 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP26 : 10; /*!< [10..1] Contains the physical address in memory to map the R26 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP26_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP27_REG; /*!< (@ 0x0000006C) This register maps the virtual register R27 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP27 : 10; /*!< [10..1] Contains the physical address in memory to map the R27 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP27_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP28_REG; /*!< (@ 0x00000070) This register maps the virtual register R28 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP28 : 10; /*!< [10..1] Contains the physical address in memory to map the R28 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP28_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP29_REG; /*!< (@ 0x00000074) This register maps the virtual register R29 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP29 : 10; /*!< [10..1] Contains the physical address in memory to map the R29 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP29_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP30_REG; /*!< (@ 0x00000078) This register maps the virtual register R30 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP30 : 10; /*!< [10..1] Contains the physical address in memory to map the R30 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP30_REG_b; + }; + + union + { + __IOM uint32_t CC312_MEMORY_MAP31_REG; /*!< (@ 0x0000007C) This register maps the virtual register R31 to + * a physical address in memory. */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_MEMORY_MAP31 : 10; /*!< [10..1] Contains the physical address in memory to map the R31 + * register to. */ + uint32_t : 21; + } CC312_MEMORY_MAP31_REG_b; + }; + + union + { + __IOM uint32_t CC312_OPCODE_REG; /*!< (@ 0x00000080) This register holds the PKA's OPCODE. */ + + struct + { + __IOM uint32_t CC312_TAG : 6; /*!< [5..0] Holds the opreation's tag or the operand C virtual address. */ + __IOM uint32_t CC312_REG_R : 6; /*!< [11..6] Result register virtual address 0-15. */ + __IOM uint32_t CC312_REG_B : 6; /*!< [17..12] Operand B virtual address 0-15. */ + __IOM uint32_t CC312_REG_A : 6; /*!< [23..18] Operand A virtual address 0-15. */ + __IOM uint32_t CC312_LEN : 3; /*!< [26..24] The length of the operation. The value serves as a + * pointer to PKA length register, for example, if the value + * is 0, PKA_L0 holds the size of the operation. */ + __IOM uint32_t CC312_PKA_OPCODE : 5; /*!< [31..27] Defines the PKA operation: @0x4 - Add,Inc @0x5 - Sub,Dec,Neg + * @0x6 - ModAdd,ModInc @0x7 - ModSub,ModDec,ModNeg @0x8 - + * AND,TST0,CLR0 @0x9 - OR,COPY,SET0 @0xa - XOR,FLIP0,INVERT,COMPARE + * @0xc - SHR0 @0xd - SHR1 @0xe - SHL0 @0xf - SHL1 @0x10 - + * MulLow @0x11 - ModMul @0x12 - ModMulN @0x13 - ModExp @0x14 + * - Division @0x15 - Div @0x16 - ModDiv @0x00 - Terminate */ + } CC312_OPCODE_REG_b; + }; + + union + { + __IOM uint32_t CC312_N_NP_T0_T1_ADDR_REG; /*!< (@ 0x00000084) This register maps N_NP_T0_T1 to a virtual address. */ + + struct + { + __IOM uint32_t CC312_N_VIRTUAL_ADDR : 5; /*!< [4..0] Virtual address of register N. */ + __IOM uint32_t CC312_NP_VIRTUAL_ADDR : 5; /*!< [9..5] Virtual address of register NP. */ + __IOM uint32_t CC312_T0_VIRTUAL_ADDR : 5; /*!< [14..10] Virtual address of temporary register number 0 */ + __IOM uint32_t CC312_T1_VIRTUAL_ADDR : 5; /*!< [19..15] Virtual address of temporary register number 1 */ + uint32_t : 12; + } CC312_N_NP_T0_T1_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_STATUS_REG; /*!< (@ 0x00000088) This register holds the PKA pipe status. */ + + struct + { + __IM uint32_t CC312_ALU_MSB_4BITS : 4; /*!< [3..0] The most significant 4-bits of the operand updated in + * shift operation. */ + __IM uint32_t CC312_ALU_LSB_4BITS : 4; /*!< [7..4] The least significant 4-bits of the operand updated in + * shift operation. */ + __IM uint32_t CC312_ALU_SIGN_OUT : 1; /*!< [8..8] Indicates the last operation's sign (MSB). */ + __IM uint32_t CC312_ALU_CARRY : 1; /*!< [9..9] Holds the carry of the last ALU operation. */ + __IM uint32_t CC312_ALU_CARRY_MOD : 1; /*!< [10..10] holds the carry of the last Modular operation. */ + __IM uint32_t CC312_ALU_SUB_IS_ZERO : 1; /*!< [11..11] Indicates the last subtraction operation's sign . */ + __IM uint32_t CC312_ALU_OUT_ZERO : 1; /*!< [12..12] Indicates if the result of ALU OUT is zero. */ + __IM uint32_t CC312_ALU_MODOVRFLW : 1; /*!< [13..13] Modular overflow flag. */ + __IM uint32_t CC312_DIV_BY_ZERO : 1; /*!< [14..14] Indication if the division is done by zero. */ + __IM uint32_t CC312_MODINV_OF_ZERO : 1; /*!< [15..15] Indicates the Modular inverse of zero. */ + __IM uint32_t CC312_LAST_OPCODE : 5; /*!< [20..16] Opcode of the last operation */ + uint32_t : 11; + } CC312_PKA_STATUS_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SW_RESET_REG; /*!< (@ 0x0000008C) Writing to this register triggers a software + * reset of the PKA. */ + + struct + { + __OM uint32_t CC312_PKA_SW_RESET : 1; /*!< [0..0] The reset mechanism takes about four PKA clock cycles + * until the reset line is deasserted */ + uint32_t : 31; + } CC312_PKA_SW_RESET_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L0_REG; /*!< (@ 0x00000090) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L0 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L0_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L1_REG; /*!< (@ 0x00000094) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L1 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L1_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L2_REG; /*!< (@ 0x00000098) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L2 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L2_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L3_REG; /*!< (@ 0x0000009C) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L3 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L3_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L4_REG; /*!< (@ 0x000000A0) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L4 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L4_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L5_REG; /*!< (@ 0x000000A4) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L5 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L5_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L6_REG; /*!< (@ 0x000000A8) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L6 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L6_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_L7_REG; /*!< (@ 0x000000AC) This register holds one of the optional size + * of the operation. */ + + struct + { + __IOM uint32_t CC312_PKA_L7 : 13; /*!< [12..0] Size of the operation in bytes. */ + uint32_t : 19; + } CC312_PKA_L7_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_PIPE_RDY_REG; /*!< (@ 0x000000B0) This register indicates whether the PKA pipe + * is ready to receive a new OPCODE. */ + + struct + { + __IM uint32_t CC312_PKA_PIPE_RDY : 1; /*!< [0..0] Indication whether PKA pipe is ready for new OPCODE. */ + uint32_t : 31; + } CC312_PKA_PIPE_RDY_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_DONE_REG; /*!< (@ 0x000000B4) This register indicates whether PKA operation + * is completed. */ + + struct + { + __IM uint32_t CC312_PKA_DONE : 1; /*!< [0..0] Indicates if PKA operation is completed, and pipe is + * empty. */ + uint32_t : 31; + } CC312_PKA_DONE_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_MON_SELECT_REG; /*!< (@ 0x000000B8) This register defines which PKA FSM monitor is + * being output. */ + + struct + { + __IOM uint32_t CC312_PKA_MON_SELECT : 4; /*!< [3..0] Defines which PKA FSM monitor is being output. */ + uint32_t : 28; + } CC312_PKA_MON_SELECT_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t CC312_PKA_VERSION_REG; /*!< (@ 0x000000C4) This register holds the pka version */ + + struct + { + __IM uint32_t CC312_PKA_VERSION : 32; /*!< [31..0] This is the PKA version */ + } CC312_PKA_VERSION_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t CC312_PKA_MON_READ_REG; /*!< (@ 0x000000D0) The PKA monitor bus register. */ + + struct + { + __IM uint32_t CC312_PKA_MON_READ : 32; /*!< [31..0] This is the PKA monitor bus register output */ + } CC312_PKA_MON_READ_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SRAM_ADDR_REG; /*!< (@ 0x000000D4) first address given to PKA SRAM for write transactions. */ + + struct + { + __OM uint32_t CC312_PKA_SRAM_ADDR : 32; /*!< [31..0] PKA SRAM write starting address */ + } CC312_PKA_SRAM_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SRAM_WDATA_REG; /*!< (@ 0x000000D8) Write data to PKA SRAM. */ + + struct + { + __OM uint32_t CC312_PKA_SRAM_WDATA : 32; /*!< [31..0] 32 bit write to PKA SRAM: triggers the SRAM write DMA + * address automatically incremented */ + } CC312_PKA_SRAM_WDATA_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SRAM_RDATA_REG; /*!< (@ 0x000000DC) Read data from PKA SRAM. */ + + struct + { + __IOM uint32_t CC312_PKA_SRAM_RDATA : 32; /*!< [31..0] 32 bit read from PKA SRAM: read - triggers the SRAM + * read DMA address automatically incremented */ + } CC312_PKA_SRAM_RDATA_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SRAM_WR_CLR_REG; /*!< (@ 0x000000E0) Write buffer clean. */ + + struct + { + __OM uint32_t CC312_PKA_SRAM_WR_CLR : 32; /*!< [31..0] Clear the write buffer. */ + } CC312_PKA_SRAM_WR_CLR_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_SRAM_RADDR_REG; /*!< (@ 0x000000E4) first address given to PKA SRAM for read transactions. */ + + struct + { + __OM uint32_t CC312_PKA_SRAM_RADDR : 32; /*!< [31..0] PKA SRAM read starting address */ + } CC312_PKA_SRAM_RADDR_REG_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CC312_PKA_WORD_ACCESS_REG; /*!< (@ 0x000000F0) This register holds the data written to PKA memory + * using the wop opcode. */ + + struct + { + __OM uint32_t CC312_PKA_WORD_ACCESS : 32; /*!< [31..0] 32 bit read/write data. */ + } CC312_PKA_WORD_ACCESS_REG_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t CC312_PKA_BUFF_ADDR_REG; /*!< (@ 0x000000F8) This register maps the virtual buffer registers + * to a physical address in memory. */ + + struct + { + __OM uint32_t CC312_PKA_BUF_ADDR : 12; /*!< [11..0] Contains the physical address in memory to map the buffer + * registers. */ + uint32_t : 20; + } CC312_PKA_BUFF_ADDR_REG_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t CC312_RNG_IMR_REG; /*!< (@ 0x00000100) Interrupt masking register. Consists of bit[31-16] + * - PRNG_IMR bit[15-0] - TRNG_IMR (Ws - PRNG + * bit exists only if PRNG_EXISTS flag) */ + + struct + { + __IOM uint32_t CC312_EHR_VALID_INT_MASK : 1; /*!< [0..0] 1'b1 - masks the EHR interrupt. No interrupt is generated. + * See RNG_ISR for explanation on this interrupt. */ + __IOM uint32_t CC312_AUTOCORR_ERR_INT_MASK : 1; /*!< [1..1] 1'b1 - masks the autocorrelation interrupt. No interrupt + * is generated. See RNG_ISR for explanation on this interrupt. */ + __IOM uint32_t CC312_CRNGT_ERR_INT_MASK : 1; /*!< [2..2] 1'b1 - masks the CRNGT error interrupt. No interrupt + * is generated. See RNG_ISR for explanation on this interrupt. */ + __IOM uint32_t CC312_VN_ERR_INT_MASK : 1; /*!< [3..3] 1'b1 - masks the Von-Neumann error interrupt. No interrupt + * is generated. See RNG_ISR for explanation on this interrupt. */ + __IOM uint32_t CC312_WATCHDOG_INT_MASK : 1; /*!< [4..4] 1'b1 - masks the watchdog interrupt. No interrupt is + * generated. See RNG_ISR for explanation on this interrupt. */ + __IOM uint32_t CC312_RNG_DMA_DONE_INT : 1; /*!< [5..5] 1'b1 - masks the RNG DMA completion interrupt. No interrupt + * is generated. See RNG_ISR for explanation on this interrupt. */ + uint32_t : 26; + } CC312_RNG_IMR_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_ISR_REG; /*!< (@ 0x00000104) Status register. If corresponding RNG_IMR bit + * is unmasked, an interrupt is generated. + * Consists of trng_isr and prng_isr bit[15-0] + * - TRNG bit[31-16] - PRNG */ + + struct + { + __IM uint32_t CC312_RNG_ISR_EHR_VALID : 1; /*!< [0..0] 1'b1 indicates that 192 bits have been collected in the + * TRNG and are ready to be read. */ + __IM uint32_t CC312_RNG_ISR_AUTOCORR_ERR : 1; /*!< [1..1] 1'b1 indicates Autocorrelation test failed four times + * in a row. When it set ,TRNG ceases to function until next + * reset. */ + __IM uint32_t CC312_RNG_ISR_CRNGT_ERR : 1; /*!< [2..2] 1'b1 indicates CRNGT in the TRNG test failed. Failure + * occurs when two consecutive blocks of 16 collected bits + * are equal. */ + __IM uint32_t CC312_RNG_ISR_VN_ERR : 1; /*!< [3..3] 1'b1 indicates Von Neumann error. Error in von Neumann + * occurs if 32 consecutive collected bits are identical, + * ZERO, or ONE. */ + uint32_t : 1; + __IM uint32_t CC312_RNG_ISR_DMA_DONE : 1; /*!< [5..5] 1'b1 indicates RNG DMA to SRAM is completed. */ + uint32_t : 10; + __IM uint32_t CC312_RNG_ISR_RESEEDING_DONE : 1; /*!< [16..16] 1'b1 indicates completion of reseeding algorithm with + * no errors. */ + __IM uint32_t CC312_RNG_ISR_INSTANTIATION_DONE : 1; /*!< [17..17] 1'b1 indicates completion of instantiation algorithm + * with no errors. */ + __IM uint32_t CC312_RNG_ISR_FINAL_UPDATE_DONE : 1; /*!< [18..18] 1'b1 indicates completion of final update algorithm. */ + __IM uint32_t CC312_RNG_ISR_OUTPUT_READY : 1; /*!< [19..19] 1'b1 indicates that the result of PRNG is valid and + * ready to be read. The result can be read from the RNG_READOUT + * register. */ + __IM uint32_t CC312_RNG_ISR_RESEED_CNTR_FULL : 1; /*!< [20..20] 1'b1 indicates that the reseed counter has reached + * 2^48, requiring to run the reseed algorithm before generating + * new random numbers. */ + __IM uint32_t CC312_RNG_ISR_RESEED_CNTR_TOP_40 : 1; /*!< [21..21] 1'b1 indicates that the top 40 bits of the reseed counter + * are set (that is the reseed counter is larger than 2^48-2^8). + * This is a recommendation for running the reseed algorithm + * before the counter reaches its max value. */ + __IM uint32_t CC312_RNG_ISR_PRNG_CRNGT_ERR : 1; /*!< [22..22] 1'b1 indicates CRNGT in the PRNG test failed. Failure + * occurs when two consecutive results of AES are equal */ + __IM uint32_t CC312_RNG_ISR_REQ_SIZE : 1; /*!< [23..23] 1'b1 indicates that the request size counter (which + * represents how many generations of random bits in the PRNG + * have been produced) has reached 2^12, thus requiring a + * working state update before generating new random numbers. */ + __IM uint32_t CC312_RNG_ISR_KAT_ERR : 1; /*!< [24..24] 1'b1 indicates that one of the KAT (Known Answer Tests) + * tests has failed. When set, the entire engine ceases to + * function. */ + __IM uint32_t CC312_RNG_ISR_WHICH_KAT_ERR : 2; /*!< [26..25] When the KAT_ERR bit is set, these bits represent which + * Known Answer Test had failed: @2'b00 - first test of instantiation + * @2'b01 - second test of instantiation @2'b10 - first test + * of reseeding @2'b11 - second test of reseeding */ + uint32_t : 5; + } CC312_RNG_ISR_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_ICR_REG; /*!< (@ 0x00000108) Interrupt/status bit clear Register. Consists + * of trng_icr and prng_icr bit[15-0] - TRNG + * bit[31-16] - PRNG */ + + struct + { + __OM uint32_t CC312_RNG_ICR_EHR_VALID : 1; /*!< [0..0] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_AUTOCORR_ERR : 1; /*!< [1..1] Cannot be cleared by SW! Only RNG reset clears this bit. */ + __OM uint32_t CC312_RNG_ICR_CRNGT_ERR : 1; /*!< [2..2] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_VN_ERR : 1; /*!< [3..3] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_RNG_WATCHDOG : 1; /*!< [4..4] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_RNG_DMA_DONE : 1; /*!< [5..5] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + uint32_t : 10; + __OM uint32_t CC312_RNG_ICR_RESEEDING_DONE : 1; /*!< [16..16] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_INSTANTIATION_DONE : 1; /*!< [17..17] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_FINAL_UPDATE_DONE : 1; /*!< [18..18] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_OUTPUT_READY : 1; /*!< [19..19] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_RESEED_CNTR_FULL : 1; /*!< [20..20] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_RESEED_CNTR_TOP_40 : 1; /*!< [21..21] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_PRNG_CRNGT_ERR : 1; /*!< [22..22] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_REQ_SIZE : 1; /*!< [23..23] Writing value 1'b1 - clears corresponding bit in RNG_ISR */ + __OM uint32_t CC312_RNG_ICR_KAT_ERR : 1; /*!< [24..24] Cannot be cleared by SW! Only RNG reset clears this + * bit. */ + __OM uint32_t CC312_RNG_ICR_WHICH_KAT_ERR : 2; /*!< [26..25] Cannot be cleared by SW! Only RNG reset clears this + * bit. */ + uint32_t : 5; + } CC312_RNG_ICR_REG_b; + }; + + union + { + __IOM uint32_t CC312_TRNG_CONFIG_REG; /*!< (@ 0x0000010C) This register handles TRNG configuration */ + + struct + { + __IOM uint32_t CC312_RND_SRC_SEL : 2; /*!< [1..0] Defines the length of the oscillator ring (= the number + * of inverters) out of four possible selections. */ + __IOM uint32_t CC312_SOP_SEL : 1; /*!< [2..2] Secure Output Port selection: @1'b1 - sop_data port reflects + * TRNG output (EHR_DATA). @1'b0 - sop_data port reflects + * PRNG output (RNG_READOUT). NOTE: Secure output is used + * for direct connection of the RNG block outputs to an engine + * input key. If CryptoCell does not include a HW PRNG - this + * field should be set to 1. */ + uint32_t : 29; + } CC312_TRNG_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t CC312_TRNG_VALID_REG; /*!< (@ 0x00000110) This register indicates that the TRNG data is + * valid. */ + + struct + { + __IM uint32_t CC312_TRNG_EHR_VALID : 1; /*!< [0..0] 1'b1 indicates that collection of bits in the TRNG is + * completed, and data can be read from the EHR_DATA register. */ + uint32_t : 31; + } CC312_TRNG_VALID_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_0_REG; /*!< (@ 0x00000114) This register contains the data collected in + * the TRNG[31_0]. NOTE: can only be set while + * in debug mode (rng_debug_enable input is + * set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_0 : 32; /*!< [31..0] Contains the data collected in the TRNG[31_0] . NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_1_REG; /*!< (@ 0x00000118) This register contains the data collected in + * the TRNG[63_32]. NOTE: can only be set while + * in debug mode (rng_debug_enable input is + * set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_1 : 32; /*!< [31..0] Contains the data collected in the TRNG[63_32]. NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_2_REG; /*!< (@ 0x0000011C) This register contains the data collected in + * the TRNG[95_64]. NOTE: can only be set while + * in debug mode (rng_debug_enable input is + * set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_2 : 32; /*!< [31..0] Contains the data collected in the TRNG[95_64]. NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_3_REG; /*!< (@ 0x00000120) This register contains the data collected in + * the TRNG[127_96]. NOTE: can only be set + * while in debug mode (rng_debug_enable input + * is set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_3 : 32; /*!< [31..0] Contains the data collected in the TRNG[127_96]. NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_4_REG; /*!< (@ 0x00000124) This register contains the data collected in + * the TRNG[159_128]. NOTE: can only be set + * while in debug mode (rng_debug_enable input + * is set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_4 : 32; /*!< [31..0] Contains the data collected in the TRNG[159_128]. NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_4_REG_b; + }; + + union + { + __IOM uint32_t CC312_EHR_DATA_5_REG; /*!< (@ 0x00000128) This register contains the data collected in + * the TRNG[191_160]. NOTE: can only be set + * while in debug mode (rng_debug_enable input + * is set). */ + + struct + { + __IM uint32_t CC312_EHR_DATA_5 : 32; /*!< [31..0] Contains the data collected in the TRNG[191_160]. NOTE: + * can only be set while in debug mode (rng_debug_enable input + * is set). */ + } CC312_EHR_DATA_5_REG_b; + }; + + union + { + __IOM uint32_t CC312_RND_SOURCE_ENABLE_REG; /*!< (@ 0x0000012C) This register holds the enable signal for the + * random source. */ + + struct + { + __IOM uint32_t CC312_RND_SRC_EN : 1; /*!< [0..0] Enable signal for the random source. */ + uint32_t : 31; + } CC312_RND_SOURCE_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_SAMPLE_CNT1_REG; /*!< (@ 0x00000130) Counts clocks between sampling of random bit. */ + + struct + { + __IOM uint32_t CC312_SAMPLE_CNTR1 : 32; /*!< [31..0] Sets the number of rng_clk cycles between two consecutive + * ring oscillator samples. NOTE: If the Von-Neumann is bypassed, + * the minimum value for sample counter must not be less than + * decimal seventeen. */ + } CC312_SAMPLE_CNT1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AUTOCORR_STATISTIC_REG; /*!< (@ 0x00000134) Statistics about autocorrelation test activations. */ + + struct + { + __IOM uint32_t CC312_AUTOCORR_TRYS : 14; /*!< [13..0] Count each time an autocorrelation test starts. Any + * write to the register resets the counter. Stops collecting + * statistics if one of the counters has reached the limit. */ + __IOM uint32_t CC312_AUTOCORR_FAILS : 8; /*!< [21..14] Count each time an autocorrelation test fails. Any + * write to the register resets the counter. Stops collecting + * statistics if one of the counters has reached the limit. */ + uint32_t : 10; + } CC312_AUTOCORR_STATISTIC_REG_b; + }; + + union + { + __IOM uint32_t CC312_TRNG_DEBUG_CONTROL_REG; /*!< (@ 0x00000138) This register is used to debug the TRNG */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC312_VNC_BYPASS : 1; /*!< [1..1] When this bit is set, the Von-Neumann balancer is bypassed + * (including the 32 consecutive bits test). NOTE: Can only + * be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW + * flag is defined, this bit can be set while not in debug + * mode. */ + __IOM uint32_t CC312_TRNG_CRNGT_BYPASS : 1; /*!< [2..2] When this bit is set, the CRNGT test in the TRNG is bypassed. + * NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN + * HW flag is defined, this bit can be set while not in debug + * mode. */ + __IOM uint32_t CC312_AUTO_CORRELATE_BYPASS : 1; /*!< [3..3] When this bit is set, the autocorrelation test in the + * TRNG module is bypassed. NOTE: Can only be set while in + * debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, + * this bit can be set while not in debug mode. */ + uint32_t : 28; + } CC312_TRNG_DEBUG_CONTROL_REG_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t CC312_RNG_SW_RESET_REG; /*!< (@ 0x00000140) Generate SW reset solely to RNG block. */ + + struct + { + __IOM uint32_t CC312_RNG_SW_RESET : 1; /*!< [0..0] Any value written (1'b0 or 1'b1) causes a reset cycle + * to the TRNG block. The reset mechanism takes about four + * RNG clock cycles until the reset line is de-asserted. */ + uint32_t : 31; + } CC312_RNG_SW_RESET_REG_b; + }; + __IM uint32_t RESERVED6[28]; + + union + { + __IOM uint32_t CC312_RNG_DEBUG_EN_INPUT_REG; /*!< (@ 0x000001B4) Defines the RNG in debug mode */ + + struct + { + __IM uint32_t CC312_RNG_DEBUG_EN : 1; /*!< [0..0] Reflects the rng_debug_enable input port */ + uint32_t : 31; + } CC312_RNG_DEBUG_EN_INPUT_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_BUSY_REG; /*!< (@ 0x000001B8) RNG busy indication */ + + struct + { + __IM uint32_t CC312_RNG_BUSY : 1; /*!< [0..0] Reflects rng_busy output port which Consists of trng_busy + * and prng_busy. */ + __IM uint32_t CC312_TRNG_BUSY : 1; /*!< [1..1] Reflects trng_busy. */ + __IM uint32_t CC312_PRNG_BUSY : 1; /*!< [2..2] Reflects prng_busy. */ + uint32_t : 29; + } CC312_RNG_BUSY_REG_b; + }; + + union + { + __IOM uint32_t CC312_RST_BITS_COUNTER_REG; /*!< (@ 0x000001BC) Resets the counter of collected bits in the TRNG */ + + struct + { + __OM uint32_t CC312_RST_BITS_COUNTER : 1; /*!< [0..0] Writing any value to this address resets the bits counter + * and trng valid registers. RND_SORCE_ENABLE register must + * be unset in order for reset to take place. */ + uint32_t : 31; + } CC312_RST_BITS_COUNTER_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_VERSION_REG; /*!< (@ 0x000001C0) This register holds the RNG version */ + + struct + { + __IM uint32_t CC312_EHR_WIDTH_192 : 1; /*!< [0..0] @1'b0 - 128 bit EHR @1'b1 - 192 bit EHR */ + __IM uint32_t CC312_CRNGT_EXISTS : 1; /*!< [1..1] @1'b0 - does not exist @1'b1 - exists */ + __IM uint32_t CC312_AUTOCORR_EXISTS : 1; /*!< [2..2] @1'b0 - does not exist @1'b1 - exists */ + __IM uint32_t CC312_TRNG_TESTS_BYPASS_EN : 1; /*!< [3..3] @1'b0 - trng tests bypass not enabled @1'b1 - trng tests + * bypass enabled */ + __IM uint32_t CC312_PRNG_EXISTS : 1; /*!< [4..4] @1'b0 - does not exist @1'b1 - exists */ + __IM uint32_t CC312_KAT_EXISTS : 1; /*!< [5..5] @1'b0 - does not exist @1'b1 - exists */ + __IM uint32_t CC312_RESEEDING_EXISTS : 1; /*!< [6..6] @1'b0 - does not exist @1'b1 - exists */ + __IM uint32_t CC312_RNG_USE_5_SBOXES : 1; /*!< [7..7] @1'b0 - 20 SBOX AES @1'b1 - 5 SBOX AES */ + uint32_t : 24; + } CC312_RNG_VERSION_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_CLK_ENABLE_REG; /*!< (@ 0x000001C4) Writing to this register enables/disables the + * RNG clock. */ + + struct + { + __OM uint32_t CC312_RNG_CLK_EN : 1; /*!< [0..0] Writing value 1'b1 enables RNG clock. */ + uint32_t : 31; + } CC312_RNG_CLK_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_DMA_ENABLE_REG; /*!< (@ 0x000001C8) Writing to this register enables/disables the + * RNG DMA. */ + + struct + { + __IOM uint32_t CC312_RNG_DMA_EN : 1; /*!< [0..0] Writing value 1'b1 enables RNG DMA to SRAM. The Value + * is cleared when DMA completes its operation. */ + uint32_t : 31; + } CC312_RNG_DMA_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_DMA_SRC_MASK_REG; /*!< (@ 0x000001CC) This register defines which ring-oscillator length + * should be used when using the RNG DMA. */ + + struct + { + __IOM uint32_t CC312_EN_SRC_SEL0 : 1; /*!< [0..0] Writing value 1'b1 enables SRC_SEL 0. */ + __IOM uint32_t CC312_EN_SRC_SEL1 : 1; /*!< [1..1] Writing value 1'b1 enables SRC_SEL 1. */ + __IOM uint32_t CC312_EN_SRC_SEL2 : 1; /*!< [2..2] Writing value 1'b1 enables SRC_SEL 2. */ + __IOM uint32_t CC312_EN_SRC_SEL3 : 1; /*!< [3..3] Writing value 1'b1 enables SRC_SEL 3. */ + uint32_t : 28; + } CC312_RNG_DMA_SRC_MASK_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_DMA_SRAM_ADDR_REG; /*!< (@ 0x000001D0) This register defines the start address of the + * DMA for the TRNG data. */ + + struct + { + __IOM uint32_t CC312_RNG_SRAM_DMA_ADDR : 11; /*!< [10..0] Defines the start address of the DMA for the TRNG data. */ + uint32_t : 21; + } CC312_RNG_DMA_SRAM_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_DMA_SAMPLES_NUM_REG; /*!< (@ 0x000001D4) This register defines the number of 192-bits + * samples that the DMA collects per RNG configuration. */ + + struct + { + __IOM uint32_t CC312_RNG_SAMPLES_NUM : 8; /*!< [7..0] Defines the number of 192-bits samples that the DMA collects + * per RNG configuration. */ + uint32_t : 24; + } CC312_RNG_DMA_SAMPLES_NUM_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_WATCHDOG_VAL_REG; /*!< (@ 0x000001D8) This register defines the maximum number of clock + * cycles per TRNG collection of 192 samples. + * If the number of cycles for a collection + * exceeds this threshold, TRNG signals an + * interrupt. */ + + struct + { + __IOM uint32_t CC312_RNG_WATCHDOG_VAL : 32; /*!< [31..0] Defines the maximum number of clock cycles per TRNG + * collection of 192 samples. If the number of cycles for + * a collection exceeds this threshold, TRNG signals an interrupt. */ + } CC312_RNG_WATCHDOG_VAL_REG_b; + }; + + union + { + __IOM uint32_t CC312_RNG_DMA_STATUS_REG; /*!< (@ 0x000001DC) This register holds the RNG DMA status. */ + + struct + { + __IM uint32_t CC312_RNG_DMA_BUSY : 1; /*!< [0..0] Indicates whether DMA is busy. */ + __IM uint32_t CC312_DMA_SRC_SEL : 2; /*!< [2..1] The active ring oscillator length using by DMA */ + __IM uint32_t CC312_NUM_OF_SAMPLES : 8; /*!< [10..3] Number of samples already collected in the current ring + * oscillator chain length. */ + uint32_t : 21; + } CC312_RNG_DMA_STATUS_REG_b; + }; + __IM uint32_t RESERVED7[104]; + + union + { + __IOM uint32_t CC312_CHACHA_CONTROL_REG_REG; /*!< (@ 0x00000380) CHACHA general configuration. */ + + struct + { + __IOM uint32_t CC312_CHACHA_OR_SALSA : 1; /*!< [0..0] Core: @1'b0 - ChaCha mode. @1'b1 - Salsa mode. */ + __IOM uint32_t CC312_INIT_FROM_HOST : 1; /*!< [1..1] Start init for new Message: @1'b0 - disable. @1'b1 - + * enable. */ + __IOM uint32_t CC312_CALC_KEY_FOR_POLY1305 : 1; /*!< [2..2] Only if ChaCha core: @1'b0 - disable. @1'b1 - enable. */ + __IOM uint32_t CC312_KEY_LEN : 1; /*!< [3..3] For All Core: @1'b0 - 256 bit. @1'b1 - 128 bit. */ + __IOM uint32_t CC312_NUM_OF_ROUNDS : 2; /*!< [5..4] The core of ChaCha is a hash function which based on + * rotation operations. The hash function consist in application + * of 20 rounds (default value). In additional, ChaCha have + * two variants (they work exactly as the original algorithm): + * ChaCha20/8 and ChaCha20/12 (using 8 and 12 rounds). Default + * value 00 @00 - 20 rounds @01 - 12 rounds @10 - 8 rounds + * @11 - N/A */ + uint32_t : 3; + __IOM uint32_t CC312_RESET_BLOCK_CNT : 1; /*!< [9..9] For new message */ + __IOM uint32_t CC312_USE_IV_96BIT : 1; /*!< [10..10] If use 96bit IV */ + uint32_t : 21; + } CC312_CHACHA_CONTROL_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_VERSION_REG; /*!< (@ 0x00000384) CHACHA Version */ + + struct + { + __IM uint32_t CC312_CHACHA_VERSION : 32; /*!< [31..0] no field description provided */ + } CC312_CHACHA_VERSION_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY0_REG; /*!< (@ 0x00000388) bits 255:224 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY0 : 32; /*!< [31..0] bits 255:224 of CHACHA Key */ + } CC312_CHACHA_KEY0_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY1_REG; /*!< (@ 0x0000038C) bits 223:192 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY1 : 32; /*!< [31..0] bits 223:192 of CHACHA Key */ + } CC312_CHACHA_KEY1_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY2_REG; /*!< (@ 0x00000390) bits191:160 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY2 : 32; /*!< [31..0] bits191:160 of CHACHA Key */ + } CC312_CHACHA_KEY2_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY3_REG; /*!< (@ 0x00000394) bits159:128 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY3 : 32; /*!< [31..0] bits 159:128 of CHACHA Key */ + } CC312_CHACHA_KEY3_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY4_REG; /*!< (@ 0x00000398) bits 127:96 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY4 : 32; /*!< [31..0] bits 127:96 of CHACHA Key */ + } CC312_CHACHA_KEY4_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY5_REG; /*!< (@ 0x0000039C) bits 95:64 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY5 : 32; /*!< [31..0] bits 95:64 of CHACHA Key */ + } CC312_CHACHA_KEY5_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY6_REG; /*!< (@ 0x000003A0) bits 63:32 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY6 : 32; /*!< [31..0] bits 63:32 of CHACHA Key */ + } CC312_CHACHA_KEY6_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_KEY7_REG; /*!< (@ 0x000003A4) bits 31:0 of CHACHA Key */ + + struct + { + __OM uint32_t CC312_CHACHA_KEY7 : 32; /*!< [31..0] bits 31:0 of CHACHA Key */ + } CC312_CHACHA_KEY7_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_IV_0_REG; /*!< (@ 0x000003A8) bits 31:0 of CHACHA_IV0 register */ + + struct + { + __IOM uint32_t CC312_CHACHA_IV_0 : 32; /*!< [31..0] bits 31:0 of CHACHA_IV0 register */ + } CC312_CHACHA_IV_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_IV_1_REG; /*!< (@ 0x000003AC) bits 31:0 of CHACHA_IV1 register */ + + struct + { + __IOM uint32_t CC312_CHACHA_IV_1 : 32; /*!< [31..0] bits 31:0 of CHACHA_IV1 register */ + } CC312_CHACHA_IV_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_BUSY_REG; /*!< (@ 0x000003B0) This register is set when the CHACHA/SALSA core + * is active */ + + struct + { + __IM uint32_t CC312_CHACHA_BUSY : 1; /*!< [0..0] CHACHA_BUSY Register. this register is set when the CHACHA/SALSA + * core is active */ + uint32_t : 31; + } CC312_CHACHA_BUSY_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_HW_FLAGS_REG; /*!< (@ 0x000003B4) This register holds the pre-synthesis HW flag + * configuration of the CHACHA/SALSA engine */ + + struct + { + __IM uint32_t CC312_CHACHA_EXISTS : 1; /*!< [0..0] If this flag is set, the Salsa/ChaCha engine include + * ChaCha implementation: @1'b0 - disable. @1'b1 - enable. */ + __IM uint32_t CC312_SALSA_EXISTS : 1; /*!< [1..1] If this flag is set, the Salsa/ChaCha engine include + * Salsa implementation: @1'b0 - disable. @1'b1 - enable. */ + __IM uint32_t CC312_FAST_CHACHA : 1; /*!< [2..2] If this flag is set, the next matrix calculated when + * the current one is written to data output path (same flag + * for Salsa core): @1'b0 - disable. @1'b1 - enable. */ + uint32_t : 29; + } CC312_CHACHA_HW_FLAGS_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_BLOCK_CNT_LSB_REG; /*!< (@ 0x000003B8) The two first words (n) in the last row of the + * cipher matrix are the block counter. At + * the end of each block (512b), the block_cnt + * for the next block is written by HW to the + * block_cnt_lsb and block_cnt_msb registers. + * Need reset block counter , if start new + * message. */ + + struct + { + __IOM uint32_t CC312_CHACHA_BLOCK_CNT_LSB : 32; /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_LSB register. This register + * holds the chacha block counter bits 31:0 */ + } CC312_CHACHA_BLOCK_CNT_LSB_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_BLOCK_CNT_MSB_REG; /*!< (@ 0x000003BC) The two first words (n) in the last row of the + * cipher matrix are the block counter. At + * the end of each block (512b), the block_cnt + * for the next block is written by HW to the + * block_cnt_lsb and block_cnt_msb registers. + * Need reset block counter , if start new + * message. */ + + struct + { + __IOM uint32_t CC312_CHACHA_BLOCK_CNT_MSB : 32; /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_MSB register. This register + * holds the chacha block counter bits 63:32 */ + } CC312_CHACHA_BLOCK_CNT_MSB_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_SW_RESET_REG; /*!< (@ 0x000003C0) Resets CHACHA/SALSA engine. */ + + struct + { + __OM uint32_t CC312_CHACH_SW_RESET : 1; /*!< [0..0] Writing to this address resets the only FSM of CHACHA + * engine. The reset takes 4 CORE_CLK cycles. */ + uint32_t : 31; + } CC312_CHACHA_SW_RESET_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY0_REG; /*!< (@ 0x000003C4) bits 255:224 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY0 : 32; /*!< [31..0] bits 255:224 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY0_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY1_REG; /*!< (@ 0x000003C8) bits 223:192 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY1 : 32; /*!< [31..0] bits 223:192 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY1_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY2_REG; /*!< (@ 0x000003CC) bits191:160 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY2 : 32; /*!< [31..0] bits191:160 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY2_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY3_REG; /*!< (@ 0x000003D0) bits159:128 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY3 : 32; /*!< [31..0] bits 159:128 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY3_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY4_REG; /*!< (@ 0x000003D4) bits 127:96 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY4 : 32; /*!< [31..0] bits 127:96 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY4_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY5_REG; /*!< (@ 0x000003D8) bits 95:64 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY5 : 32; /*!< [31..0] bits 95:64 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY5_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY6_REG; /*!< (@ 0x000003DC) bits 63:32 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY6 : 32; /*!< [31..0] bits 63:32 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY6_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_FOR_POLY_KEY7_REG; /*!< (@ 0x000003E0) bits 31:0 of CHACHA_FOR_POLY_KEY */ + + struct + { + __IM uint32_t CC312_CHACHA_FOR_POLY_KEY7 : 32; /*!< [31..0] bits 31:0 of CHACHA_FOR_POLY_KEY */ + } CC312_CHACHA_FOR_POLY_KEY7_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG; /*!< (@ 0x000003E4) CHACHA/SALSA DATA ORDER configuration. */ + + struct + { + __IOM uint32_t CC312_CHACHA_DIN_WORD_ORDER : 1; /*!< [0..0] Change the words order of the input data. @1'b0 - disable. + * @1'b1 - enable. (reverse each word in 128 bit input ( w0->w3, + * w1->w2, w2->w1,w3-w0)) */ + __IOM uint32_t CC312_CHACHA_DIN_BYTE_ORDER : 1; /*!< [1..1] Change the byte order of the input data. @1'b0 - disable. + * @1'b1 - enable. (reverse each byte in each word input (b0->b3, + * b1->b2, b2->b1,b3->b0)) */ + __IOM uint32_t CC312_CHACHA_CORE_MATRIX_LBE_ORDER : 1; /*!< [2..2] Change the quarter of a matrix order in core @1'b0 - + * disable. @1'b1 - enable. (reverse each quarter of a matrix + * (m[0-127]->m[384-511], m[128-255]->m[256-383], m[256-383]->m[128-255], + * m[384-511]->m[0-127])) */ + __IOM uint32_t CC312_CHACHA_DOUT_WORD_ORDER : 1; /*!< [3..3] Change the words order of the output data. @1'b0 - disable. + * @1'b1 - enable. (reverse each word in 128 bit output ( + * w0->w3, w1->w2, w2->w1,w3-w0)) */ + __IOM uint32_t CC312_CHACHA_DOUT_BYTE_ORDER : 1; /*!< [4..4] Change the byte order of the output data. @1'b0 - disable. + * @1'b1 - enable. (reverse each byte in each word output + * (b0->b3, b1->b2, b2->b1,b3->b0)) */ + uint32_t : 27; + } CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_CHACHA_DEBUG_REG_REG; /*!< (@ 0x000003E8) This register is used to debug the CHACHA engine */ + + struct + { + __IM uint32_t CC312_CHACHA_DEBUG_FSM_STATE : 2; /*!< [1..0] CHACHA_DEBUG_FSM_STATE @0x0 - IDLE_STATE @0x1 - INIT_STATE + * @0x2 - ROUNDS_STATE @0x3 - FINAL_STATE */ + uint32_t : 30; + } CC312_CHACHA_DEBUG_REG_REG_b; + }; + __IM uint32_t RESERVED8[5]; + + union + { + __IOM uint32_t CC312_AES_KEY_0_0_REG; /*!< (@ 0x00000400) bits 31:0 of AES Key0 (used as the AES key in + * non-tunneling operations, and as the first + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_0 : 32; /*!< [31..0] bits 31:0 of AES Key0. */ + } CC312_AES_KEY_0_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_1_REG; /*!< (@ 0x00000404) bits 63:32 of AES Key0 (used as the AES key in + * non-tunneling operations, and as the first + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_1 : 32; /*!< [31..0] bits 63:32 of AES Key0. */ + } CC312_AES_KEY_0_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_2_REG; /*!< (@ 0x00000408) bits 95:64 of AES Key0 (used as the AES key in + * non-tunneling operations, and as the first + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_2 : 32; /*!< [31..0] bits 95:64 of AES Key0. */ + } CC312_AES_KEY_0_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_3_REG; /*!< (@ 0x0000040C) bits 127:96 of AES Key0 (used as the AES key + * in non-tunneling operations, and as the + * first tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_3 : 32; /*!< [31..0] bits 127:96 of AES Key0. */ + } CC312_AES_KEY_0_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_4_REG; /*!< (@ 0x00000410) bits 159:128 of AES Key0 (used as the AES key + * in non-tunneling operations, and as the + * first tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_4 : 32; /*!< [31..0] bits 159:128 of AES Key0 . */ + } CC312_AES_KEY_0_4_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_5_REG; /*!< (@ 0x00000414) bits 191:160 of AES Key0 (used as the AES key + * in non-tunneling operations, and as the + * first tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_5 : 32; /*!< [31..0] bits 191:160 of AES Key0. */ + } CC312_AES_KEY_0_5_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_6_REG; /*!< (@ 0x00000418) bits 223:192 of AES Key0 (used as the AES key + * in non-tunneling operations, and as the + * first tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_6 : 32; /*!< [31..0] bits 223:192 of AES Key0. */ + } CC312_AES_KEY_0_6_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_0_7_REG; /*!< (@ 0x0000041C) bits 255:224 of AES Key0 (used as the AES key + * in non-tunneling operations, and as the + * first tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_0_7 : 32; /*!< [31..0] bits 255:224 of AES Key0. */ + } CC312_AES_KEY_0_7_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_0_REG; /*!< (@ 0x00000420) bits 31:0 of AES Key1 (used as the second AES + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_0 : 32; /*!< [31..0] bits 31:0 of AES Key1. */ + } CC312_AES_KEY_1_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_1_REG; /*!< (@ 0x00000424) bits 63:32 of AES Key1 (used as the second AES + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_1 : 32; /*!< [31..0] bits 63:32 of AES Key1. */ + } CC312_AES_KEY_1_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_2_REG; /*!< (@ 0x00000428) bits 95:64 of AES Key1 (used as the second AES + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_2 : 32; /*!< [31..0] bits 95:64 of AES Key1. */ + } CC312_AES_KEY_1_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_3_REG; /*!< (@ 0x0000042C) bits 127:96 of AES Key1 (used as the second AES + * tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_3 : 32; /*!< [31..0] bits 127:96 of AES Key1. */ + } CC312_AES_KEY_1_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_4_REG; /*!< (@ 0x00000430) bits 159:128 of AES Key1 (used as the second + * AES tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_4 : 32; /*!< [31..0] bits 159:128 of AES Key1. */ + } CC312_AES_KEY_1_4_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_5_REG; /*!< (@ 0x00000434) bits 191:160 of AES Key1 (used as the second + * AES tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_5 : 32; /*!< [31..0] bits 191:160 of AES Key1. */ + } CC312_AES_KEY_1_5_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_6_REG; /*!< (@ 0x00000438) bits 223:192 of AES Key1 (used as the second + * AES tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_6 : 32; /*!< [31..0] bits 223:192 of AES Key1. */ + } CC312_AES_KEY_1_6_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_KEY_1_7_REG; /*!< (@ 0x0000043C) bits 255:224 of AES Key1 (used as the second + * AES tunnel stage key in tunneling operations). */ + + struct + { + __OM uint32_t CC312_AES_KEY_1_7 : 32; /*!< [31..0] bits 255:224 of AES Key1. */ + } CC312_AES_KEY_1_7_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_0_0_REG; /*!< (@ 0x00000440) bits 31:0 of AES_IV0 register. AES IV0 is used + * as the AES IV (Initialization Value) register + * in non-tunneling operations, and as the + * first tunnel stage IV register in tunneling + * operations. The IV register should be loaded + * according to the AES mode: in AES CBC/CBC-MAC + * - the AES IV register should be loaded with + * the IV (initialization vector). in XTS-AES + * - the AES IV register should be loaded with + * the 'T' value (unless the HW T calculation + * mode is active, in which the 'T' value is + * calculated */ + + struct + { + __IOM uint32_t CC312_AES_IV_0_0 : 32; /*!< [31..0] bits 31:0 of AES_IV0 register. For the description of + * AES_IV0, see the AES_IV_0_0 register description */ + } CC312_AES_IV_0_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_0_1_REG; /*!< (@ 0x00000444) bits 63:32 of AES_IV0 128b register. For the + * description of AES_IV0, see the AES_IV_0_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_0_1 : 32; /*!< [31..0] bits 63:32 of AES_IV0 register. For the description + * of AES_IV0, see the AES_IV_0_0 register description */ + } CC312_AES_IV_0_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_0_2_REG; /*!< (@ 0x00000448) bits 95:64 of AES_IV0 128b register. For the + * description of AES_IV0, see the AES_IV_0_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_0_2 : 32; /*!< [31..0] bits 95:64 of AES_IV0 register. For the description + * of AES_IV0, see the AES_IV_0_0 register description */ + } CC312_AES_IV_0_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_0_3_REG; /*!< (@ 0x0000044C) bits 127:96 of AES_IV0 128b register. For the + * description of AES_IV0, see the AES_IV_0_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_0_3 : 32; /*!< [31..0] bits 127:96 of AES_IV0 register. For the description + * of AES_IV0, see the AES_IV_0_0 register description */ + } CC312_AES_IV_0_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_1_0_REG; /*!< (@ 0x00000450) bits 31:0 of AES_IV1 128b register. AES IV1 is + * used as the AES IV (Initialization Value) + * register as the second tunnel stage IV register + * in tunneling operations. The IV register + * should be loaded according to the AES mode: + * in AES CBC/CBC-MAC - the AES IV register + * should be loaded with the IV (initialization + * vector). in XTS-AES - the AES IV register + * should be loaded with the 'T' value (unless + * the HW T calculation mode is active, in + * which the 'T' value is calculated by the + * HW. */ + + struct + { + __IOM uint32_t CC312_AES_IV_1_0 : 32; /*!< [31..0] bits 31:0 of AES_IV1 register. For the description of + * AES_IV1, see the AES_IV_1_0 register description */ + } CC312_AES_IV_1_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_1_1_REG; /*!< (@ 0x00000454) bits 63:32 of AES_IV1 128b register. For the + * description of AES_IV1, see the AES_IV_1_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_1_1 : 32; /*!< [31..0] bits 63:32 of AES_IV1 register. For the description + * of AES_IV1, see the AES_IV_1_0 register description */ + } CC312_AES_IV_1_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_1_2_REG; /*!< (@ 0x00000458) bits 95:64 of AES_IV1 128b register. For the + * description of AES_IV1, see the AES_IV_1_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_1_2 : 32; /*!< [31..0] bits 95:64 of AES_IV1 register. For the description + * of AES_IV1, see the AES_IV_1_0 register description */ + } CC312_AES_IV_1_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_IV_1_3_REG; /*!< (@ 0x0000045C) bits 127:96 of AES_IV1 128b register. For the + * description of AES_IV1, see the AES_IV_1_0 + * register description */ + + struct + { + __IOM uint32_t CC312_AES_IV_1_3 : 32; /*!< [31..0] bits 127:96 of AES_IV1 register. For the description + * of AES_IV1, see the AES_IV_1_0 register description */ + } CC312_AES_IV_1_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CTR_0_0_REG; /*!< (@ 0x00000460) bits 31:0 of AES_CTR0 128b register. AES CTR0 + * is used as the AES CTR (counter) register + * in non-tunneling operations, and as the + * first tunnel stage CTR register in tunneling + * operations. The CTR register should be loaded + * according to the AES mode: in AES CTR/GCTR + * - the AES CTR register should be loaded + * with the counter value. in XTS-AES - the + * AES CTR register should be loaded with the + * 'i' value (in order to calculate the T value + * from it, if HW T calculation is supported). */ + + struct + { + __IOM uint32_t CC312_AES_CTR_0_0 : 32; /*!< [31..0] bits 31:0 of AES_CTR0 register. For the description + * of AES_CTR0, see the AES_CTR_0_0 register description */ + } CC312_AES_CTR_0_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CTR_0_1_REG; /*!< (@ 0x00000464) bits 63:32 of AES_CTR0 128b register. For the + * description of AES_CTR0, see the AES_CTR_0_0 + * register description. */ + + struct + { + __IOM uint32_t CC312_AES_CTR_0_1 : 32; /*!< [31..0] bits 63:32 of AES_CTR0 register. For the description + * of AES_CTR0, see the AES_CTR_0_0 register description */ + } CC312_AES_CTR_0_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CTR_0_2_REG; /*!< (@ 0x00000468) bits 95:64 of AES_CTR0 128b register. For the + * description of AES_CTR0, see the AES_CTR_0_0 + * register description. */ + + struct + { + __IOM uint32_t CC312_AES_CTR_0_2 : 32; /*!< [31..0] bits 95:64 of AES_CTR0 register. For the description + * of AES_CTR0, see the AES_CTR_0_0 register description */ + } CC312_AES_CTR_0_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CTR_0_3_REG; /*!< (@ 0x0000046C) bits 127:96 of AES_CTR0 128b register. For the + * description of AES_CTR0, see the AES_CTR_0_0 + * register description. */ + + struct + { + __IOM uint32_t CC312_AES_CTR_0_3 : 32; /*!< [31..0] bits 127:96 of AES_CTR0 register. For the description + * of AES_CTR0, see the AES_CTR_0_0 register description */ + } CC312_AES_CTR_0_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_BUSY_REG; /*!< (@ 0x00000470) This register is set when the AES core is active */ + + struct + { + __IM uint32_t CC312_AES_BUSY : 1; /*!< [0..0] AES_BUSY Register. this register is set when the AES + * core is active */ + uint32_t : 31; + } CC312_AES_BUSY_REG_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t CC312_AES_SK_REG; /*!< (@ 0x00000478) writing to this address causes sampling of the + * HW key to the AES_KEY0 register */ + + struct + { + __OM uint32_t CC312_AES_SK : 1; /*!< [0..0] writing to this address causes sampling of the HW key + * to the AES_KEY0 register */ + uint32_t : 31; + } CC312_AES_SK_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CMAC_INIT_REG; /*!< (@ 0x0000047C) Writing to this address triggers the AES engine + * generating of K1 and K2 for AES CMAC operations. + * Note: This is a special register, affected + * by internal logic. Test result of this register + * is NA. */ + + struct + { + __OM uint32_t CC312_AES_CMAC_INIT : 1; /*!< [0..0] Writing to this address starts the generating of K1 and + * K2 for AES CMAC operations */ + uint32_t : 31; + } CC312_AES_CMAC_INIT_REG_b; + }; + __IM uint32_t RESERVED10[13]; + + union + { + __IOM uint32_t CC312_AES_SK1_REG; /*!< (@ 0x000004B4) writing to this address causes sampling of the + * HW key to the AES_KEY1 register */ + + struct + { + __OM uint32_t CC312_AES_SK1 : 1; /*!< [0..0] writing to this address causes sampling of the HW key + * to the AES_KEY1 register */ + uint32_t : 31; + } CC312_AES_SK1_REG_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CC312_AES_REMAINING_BYTES_REG; /*!< (@ 0x000004BC) This register should be set with the amount of + * remaining bytes until the end of the current + * AES operation. The AES engine counts down + * from this value to determine the last / + * one before last blocks in AES CMAC, XTS + * AES and AES CCM. */ + + struct + { + __IOM uint32_t CC312_AES_REMAINING_BYTES : 32; /*!< [31..0] This register should be set with the amount of remaining + * bytes until the end of the current AES operation. The AES + * engine counts down from this value to determine the last + * / one before last blocks in AES CMAC, XTS AES and AES CCM. */ + } CC312_AES_REMAINING_BYTES_REG_b; + }; + + union + { + __IOM uint32_t CC312_AES_CONTROL_REG; /*!< (@ 0x000004C0) This register holds the configuration of the + * AES engine Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IOM uint32_t CC312_DEC_KEY0 : 1; /*!< [0..0] This field determines whether the AES performs Decrypt/Encrypt + * operations, in non-tunneling operations: @0 - Encrypt @1 + * - Decrypt */ + __IOM uint32_t CC312_MODE0_IS_CBC_CTS : 1; /*!< [1..1] If MODE_KEY0 is set to 3'b001 (CBC), and this field is + * set - the mode is CBC-CTS. In addition, If MODE_KEY0 is + * set to 3'b010 (CTR), and this field is set - the mode is + * GCTR. */ + __IOM uint32_t CC312_MODE_KEY0 : 3; /*!< [4..2] This field determines the AES mode in non tunneling operations, + * and the AES mode of the first stage in tunneling operations: + * @000 - ECB @001 - CBC @010 - CTR @011 - CBC MAC @100 - + * XEX/XTS @101 - XCBC-MAC @110 -OFB @111 - CMAC */ + __IOM uint32_t CC312_MODE_KEY1 : 3; /*!< [7..5] This field determines the AES mode of the second stage + * operation in tunneling operations: @000 - ECB @001 - CBC + * @010 - CTR @011 - CBC MAC @100 - XEX/XTS @101 - XCBC-MAC + * @110 -OFB @111 - CMAC */ + __IOM uint32_t CC312_CBC_IS_ESSIV : 1; /*!< [8..8] If MODE_KEY0 is set to 3'b001 (CBC), and this field is + * set - the mode is CBC-with ESSIV. */ + uint32_t : 1; + __IOM uint32_t CC312_AES_TUNNEL_IS_ON : 1; /*!< [10..10] This field determines whether the AES performs dual-tunnel + * operations or standard non-tunneling operations: @0 - standard + * non-tunneling operations @1 - tunneling operations. */ + __IOM uint32_t CC312_CBC_IS_BITLOCKER : 1; /*!< [11..11] If MODE_KEY0 is set to 3'b001 (CBC), and this field + * is set - the mode isBITLOCKER. */ + __IOM uint32_t CC312_NK_KEY0 : 2; /*!< [13..12] This field determines the AES Key length in non tunneling + * operations, and the AES key length of the first stage in + * tunneling operations: @00 - 128 bits key @01 - 192 bits + * key @10 - 256 bits key @11 - N/A */ + __IOM uint32_t CC312_NK_KEY1 : 2; /*!< [15..14] This field determines the AES key length of the second + * stage operation in tunneling operations: @00 - 128 bits + * key @01 - 192 bits key @10 - 256 bits key @11 - N/A */ + uint32_t : 6; + __IOM uint32_t CC312_AES_TUNNEL1_DECRYPT : 1; /*!< [22..22] This field determines whether the second tunnel stage + * performs encrypt or decrypt operation : @0 - the second + * tunnel stage performs encrypt operations. @1 - the second + * tunnel stage performs decrypt operations. */ + __IOM uint32_t CC312_AES_TUN_B1_USES_PADDED_DATA_IN : 1; /*!< [23..23] This field determines, for tunneling operations, the + * data that is fed to the second tunneling stage: @0 - the + * output of the first block (standard tunneling operation). + * @1- data_in after padding rather than the output of the + * first block. */ + __IOM uint32_t CC312_AES_TUNNEL0_ENCRYPT : 1; /*!< [24..24] This field determines whether the first tunnel stage + * performs encrypt or decrypt operation : @0 - the first + * tunnel stage performs decrypt operations. @1 - the first + * tunnel stage performs encrypt operations. */ + __IOM uint32_t CC312_AES_OUTPUT_MID_TUNNEL_DATA : 1; /*!< [25..25] This fields determines whether the AES output is the + * result of the first or second tunneling stage: @0 - The + * AES engine outputs the result of the second tunnel stage + * (standard tunneling). @1 - The AES engine outputs the result + * of the first tunnel stage. */ + __IOM uint32_t CC312_AES_TUNNEL_B1_PAD_EN : 1; /*!< [26..26] This field determines whether the input data to the + * second tunnel stage is padded with zeroes (according to + * the remaining_bytes value) or not: @0 - The data input + * to the second tunnel block is not padded with zeros. @1 + * - The data input to the second tunnel block is padded with + * zeros. */ + uint32_t : 1; + __IOM uint32_t CC312_AES_OUT_MID_TUN_TO_HASH : 1; /*!< [28..28] This field determines for AES-TO-HASH-AND-DOUT tunneling + * operations, whether the AES outputs to the HASH the result + * of the first or the second tunneling stage: @0 - The AES + * engine writes to the hash the result of the second tunnel + * stage. @1 - The AES engine writes to the hash the result + * of the first tunnel stage. */ + __IOM uint32_t CC312_AES_XOR_CRYPTOKEY : 1; /*!< [29..29] This field determines the value that is written to + * AES_KEY0, when AES_SK is kicked: @0 - The value that is + * written to AES_KEY0 is the value of the HW cryptokey, as + * is. @1 - The value that is written to AES_KEY0 is the value + * of the HW cryptokey xored with the current value of AES_KEY0. */ + uint32_t : 1; + __IOM uint32_t CC312_DIRECT_ACCESS : 1; /*!< [31..31] Using direct access and not the din-dout interface */ + } CC312_AES_CONTROL_REG_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t CC312_AES_HW_FLAGS_REG; /*!< (@ 0x000004C8) This register holds the pre-synthesis HW flag + * configuration of the AES engine */ + + struct + { + __IM uint32_t CC312_SUPPORT_256_192_KEY : 1; /*!< [0..0] the SUPPORT_256_192_KEY flag */ + __IM uint32_t CC312_AES_LARGE_RKEK : 1; /*!< [1..1] the AES_LARGE_RKEK flag */ + __IM uint32_t CC312_DPA_CNTRMSR_EXIST : 1; /*!< [2..2] the DPA_CNTRMSR_EXIST flag */ + __IM uint32_t CC312_CTR_EXIST : 1; /*!< [3..3] the CTR_EXIST flag */ + __IM uint32_t CC312_ONLY_ENCRYPT : 1; /*!< [4..4] the ONLY_ENCRYPT flag */ + __IM uint32_t CC312_USE_SBOX_TABLE : 1; /*!< [5..5] the USE_SBOX_TABLE flag */ + uint32_t : 2; + __IM uint32_t CC312_USE_5_SBOXES : 1; /*!< [8..8] the USE_5_SBOXES flag */ + __IM uint32_t CC312_AES_SUPPORT_PREV_IV : 1; /*!< [9..9] the AES_SUPPORT_PREV_IV flag */ + __IM uint32_t CC312_aes_tunnel_exists : 1; /*!< [10..10] the aes_tunnel_exists flag */ + __IM uint32_t CC312_SECOND_REGS_SET_EXIST : 1; /*!< [11..11] the SECOND_REGS_SET_EXIST flag */ + __IM uint32_t CC312_DFA_CNTRMSR_EXIST : 1; /*!< [12..12] the DFA_CNTRMSR_EXIST flag */ + uint32_t : 19; + } CC312_AES_HW_FLAGS_REG_b; + }; + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t CC312_AES_CTR_NO_INCREMENT_REG; /*!< (@ 0x000004D8) This register enables the AES CTR no increment + * mode (in which the counter mode is not incremented + * between 2 blocks) */ + + struct + { + __IOM uint32_t CC312_AES_CTR_NO_INCREMENT : 1; /*!< [0..0] This field enables the AES CTR "no increment" mode (in + * which the counter mode is not incremented between 2 blocks) */ + uint32_t : 31; + } CC312_AES_CTR_NO_INCREMENT_REG_b; + }; + __IM uint32_t RESERVED14[5]; + + union + { + __IOM uint32_t CC312_AES_DFA_IS_ON_REG; /*!< (@ 0x000004F0) This register disable/enable the AES dfa. Note: + * This is a special register, affected by + * internal logic. Test result of this register + * is NA. */ + + struct + { + __IOM uint32_t CC312_AES_DFA_IS_ON : 1; /*!< [0..0] writing to this register turns the DFA counter-measures + * on. this register exists only if DFA countermeasures are + * supported */ + uint32_t : 31; + } CC312_AES_DFA_IS_ON_REG_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t CC312_AES_DFA_ERR_STATUS_REG; /*!< (@ 0x000004F8) dfa error status register. */ + + struct + { + __IM uint32_t CC312_AES_DFA_ERR_STATUS : 1; /*!< [0..0] after a DFA violation this register is set and the AES + * block is disabled) until the next reset. this register + * only exists if DFA countermeasures is are supported */ + uint32_t : 31; + } CC312_AES_DFA_ERR_STATUS_REG_b; + }; + __IM uint32_t RESERVED16[10]; + + union + { + __IOM uint32_t CC312_AES_CMAC_SIZE0_KICK_REG; /*!< (@ 0x00000524) writing to this address triggers the AES engine + * to perform a CMAC operation with size 0. + * The CMAC result can be read from the AES_IV0 + * register. */ + + struct + { + __OM uint32_t CC312_AES_CMAC_SIZE0_KICK : 1; /*!< [0..0] writing to this address triggers the AES engine to perform + * a CMAC operation with size 0. The CMAC result can be read + * from the AES_IV0 register. */ + uint32_t : 31; + } CC312_AES_CMAC_SIZE0_KICK_REG_b; + }; + __IM uint32_t RESERVED17[70]; + + union + { + __IOM uint32_t CC312_HASH_H0_REG; /*!< (@ 0x00000640) H0 data. can only be written in the following + * HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 + * SHA384 SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H0 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H0_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H1_REG; /*!< (@ 0x00000644) H1 data. can only be written in the following + * HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 + * SHA384 SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H1 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H1_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H2_REG; /*!< (@ 0x00000648) H2 data. can only be written in the following + * HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 + * SHA384 SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H2 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H2_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H3_REG; /*!< (@ 0x0000064C) H3 data. can only be written in the following + * HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 + * SHA384 SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H3 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H3_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H4_REG; /*!< (@ 0x00000650) H4 data. can only be written in the following + * HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384 + * SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H4 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H4_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H5_REG; /*!< (@ 0x00000654) H5 data. can only be written in the following + * HASH_CONTROL modes: SHA224 SHA256 SHA384 + * SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H5 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H5_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H6_REG; /*!< (@ 0x00000658) H6 data. can only be written in the following + * HASH_CONTROL modes: SHA224 SHA256 SHA384 + * SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H6 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H6_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H7_REG; /*!< (@ 0x0000065C) H7 data. can only be written in the following + * HASH_CONTROL modes: SHA224 SHA256 SHA384 + * SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H7 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H7_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_H8_REG; /*!< (@ 0x00000660) H8 data. can only be written in the following + * HASH_CONTROL modes: SHA384 SHA512 */ + + struct + { + __IOM uint32_t CC312_HASH_H8 : 32; /*!< [31..0] 1) Write initial Hash value. 2) Read final Hash value + * - result. */ + } CC312_HASH_H8_REG_b; + }; + __IM uint32_t RESERVED18[8]; + + union + { + __IOM uint32_t CC312_AUTO_HW_PADDING_REG; /*!< (@ 0x00000684) HW padding automatically activated by engine. + * For the special case of ZERO bytes data + * vector this register should not be used! + * instead use HASH_PAD_CFG */ + + struct + { + __OM uint32_t CC312_AUTO_HW_PADDING_EN : 1; /*!< [0..0] 1'b1 - Enable Automatic HW padding (No need for SW intervention + * by writing PAD_CFG). Note: Not supported for 0 bytes ! + * Note: Disable this register when HASH op is done */ + uint32_t : 31; + } CC312_AUTO_HW_PADDING_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_XOR_DIN_REG; /*!< (@ 0x00000688) This register is always xored with the input + * to the hash engine,it should be '0' if xored + * is not reqiured . */ + + struct + { + __IOM uint32_t CC312_HASH_XOR_DATA : 32; /*!< [31..0] This register holds the value to be xor-ed with hash + * input data. */ + } CC312_HASH_XOR_DIN_REG_b; + }; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint32_t CC312_LOAD_INIT_STATE_REG; /*!< (@ 0x00000694) Indication to HASH that the following data is + * to be loaded into initial value registers + * in HASH(H0:H15) or IV to AES MAC */ + + struct + { + __OM uint32_t CC312_LOAD : 1; /*!< [0..0] Load data to initial state registers. digest/iv for hash/aes_mac. + * When done loading data this bit should be reset */ + uint32_t : 31; + } CC312_LOAD_INIT_STATE_REG_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint32_t CC312_HASH_SEL_AES_MAC_REG; /*!< (@ 0x000006A4) select the AES MAC module rather than the hash + * module */ + + struct + { + __OM uint32_t CC312_HASH_SEL_AES_MAC : 1; /*!< [0..0] @1'b0 - select the hash module @1'b1 - select the AES + * mac module */ + __OM uint32_t CC312_GHASH_SEL : 1; /*!< [1..1] @1'b0 - select the hash module @1'b1 - select the ghash + * module */ + uint32_t : 30; + } CC312_HASH_SEL_AES_MAC_REG_b; + }; + __IM uint32_t RESERVED21[66]; + + union + { + __IOM uint32_t CC312_HASH_VERSION_REG; /*!< (@ 0x000007B0) HASH VERSION Register */ + + struct + { + __IM uint32_t CC312_FIXES : 8; /*!< [7..0] no field description provided */ + __IM uint32_t CC312_MINOR_VERSION_NUMBER : 4; /*!< [11..8] minor version number */ + __IM uint32_t CC312_MAJOR_VERSION_NUMBER : 4; /*!< [15..12] major version number */ + uint32_t : 16; + } CC312_HASH_VERSION_REG_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t CC312_HASH_CONTROL_REG; /*!< (@ 0x000007C0) HASH_CONTROL Register. selects which HASH mode + * to run */ + + struct + { + __IOM uint32_t CC312_MODE_0_1 : 2; /*!< [1..0] bits 1:0 of the HASH mode field. The hash mode field + * possible values are: @4'b0000 - MD5 if present @4'b0001 + * - SHA-1 @4'b0010 - SHA-256 @4'b1010 - SHA-224 */ + uint32_t : 1; + __IOM uint32_t CC312_MODE_3 : 1; /*!< [3..3] bit 3 of the HASH mode field. The hash mode field possible + * values are:4'b0000 - MD5 if present 4'b0001 - SHA-1 4'b0010 + * - SHA-256 4'b1010 - SHA-224 */ + uint32_t : 28; + } CC312_HASH_CONTROL_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_PAD_EN_REG; /*!< (@ 0x000007C4) This register enables the hash hw padding . */ + + struct + { + __IOM uint32_t CC312_HASH_PAD_EN : 1; /*!< [0..0] 1 - Enable generation of padding by HW Pad block. 0 - + * Disable generation of padding by HW Pad block. */ + uint32_t : 31; + } CC312_HASH_PAD_EN_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_PAD_CFG_REG; /*!< (@ 0x000007C8) HASH_PAD_CFG Register. Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + uint32_t : 2; + __IOM uint32_t CC312_DO_PAD : 1; /*!< [2..2] Enable Padding generation. must be reset upon completion + * of padding. */ + uint32_t : 29; + } CC312_HASH_PAD_CFG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_CUR_LEN_0_REG; /*!< (@ 0x000007CC) This register hold the length of current hash + * operation bit 31:0. */ + + struct + { + __IOM uint32_t CC312_HASH_CUR_LEN_0 : 32; /*!< [31..0] Represent the current length of valid bits where digest + * need to be computed In Bytes. */ + } CC312_HASH_CUR_LEN_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_CUR_LEN_1_REG; /*!< (@ 0x000007D0) This register hold the length of current hash + * operation bit 63:32. */ + + struct + { + __IOM uint32_t CC312_HASH_CUR_LEN_1 : 32; /*!< [31..0] Represent the current length of valid bits where digest + * need to be computed In Bytes. */ + } CC312_HASH_CUR_LEN_1_REG_b; + }; + __IM uint32_t RESERVED23[2]; + + union + { + __IOM uint32_t CC312_HASH_PARAM_REG; /*!< (@ 0x000007DC) HASH_PARAM Register. */ + + struct + { + __IM uint32_t CC312_CW : 4; /*!< [3..0] Indicates the number of concurrent words the hash is + * using to compute signature. 1 - One concurrent w(t). 2 + * - Two concurrent w(t). */ + __IM uint32_t CC312_CH : 4; /*!< [7..4] Indicate if Hi adders are present for each Hi value or + * 1 adder is shared for all Hi. 0 - One Hi value is updated + * at a time 1 - All Hi values are updated at the same time. */ + __IM uint32_t CC312_DW : 4; /*!< [11..8] Determine the granularity of word size. 0 - 32 bit word + * data. 1 - 64 bit word data. */ + __IM uint32_t CC312_SHA_512_EXISTS : 1; /*!< [12..12] Indicate if SHA-512 is present in the design. By default + * SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are + * present only 1 - SHA-1 and all SHA-2 are present (SHA-256 + * SHA-512). */ + __IM uint32_t CC312_PAD_EXISTS : 1; /*!< [13..13] Indicate if pad block is present in the design. 0 - + * pad function is not supported by hardware. 1 - pad function + * is supported by hardware. */ + __IM uint32_t CC312_MD5_EXISTS : 1; /*!< [14..14] Indicate if MD5 is present in HW */ + __IM uint32_t CC312_HMAC_EXISTS : 1; /*!< [15..15] Indicate if HMAC logic is present in the design */ + __IM uint32_t CC312_SHA_256_EXISTS : 1; /*!< [16..16] Indicate if SHA-256 is present in the design */ + __IM uint32_t CC312_HASH_COMPARE_EXISTS : 1; /*!< [17..17] Indicate if COMPARE digest logic is present in the + * design */ + __IM uint32_t CC312_DUMP_HASH_TO_DOUT_EXISTS : 1; /*!< [18..18] Indicate if HASH to dout is present in the design */ + uint32_t : 13; + } CC312_HASH_PARAM_REG_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t CC312_HASH_AES_SW_RESET_REG; /*!< (@ 0x000007E4) HASH_AES_SW_RESET Register. */ + + struct + { + __OM uint32_t CC312_HASH_AES_SW_RESET : 1; /*!< [0..0] Hash receive reset internally. */ + uint32_t : 31; + } CC312_HASH_AES_SW_RESET_REG_b; + }; + + union + { + __IOM uint32_t CC312_HASH_ENDIANESS_REG; /*!< (@ 0x000007E8) This register hold the HASH_ENDIANESS configuration. */ + + struct + { + __IOM uint32_t CC312_ENDIAN : 1; /*!< [0..0] The default value is little-endian. The data and generation + * of padding can be swapped to be big-endian. */ + uint32_t : 31; + } CC312_HASH_ENDIANESS_REG_b; + }; + __IM uint32_t RESERVED25[9]; + + union + { + __IOM uint32_t CC312_AES_CLK_ENABLE_REG; /*!< (@ 0x00000810) The AES clock enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_AES_CLK_EN : 1; /*!< [0..0] @1'b1 - the AES clock is enabled. @1'b0 - the AES clock + * is disabled. */ + uint32_t : 31; + } CC312_AES_CLK_ENABLE_REG_b; + }; + __IM uint32_t RESERVED26; + + union + { + __IOM uint32_t CC312_HASH_CLK_ENABLE_REG; /*!< (@ 0x00000818) The HASH clock enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HASH_CLK_EN : 1; /*!< [0..0] @1'b1 - the HASH clock is enabled. @1'b0 - the HASH clock + * is disabled. */ + uint32_t : 31; + } CC312_HASH_CLK_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_PKA_CLK_ENABLE_REG; /*!< (@ 0x0000081C) The PKA clock enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_PKA_CLK_EN : 1; /*!< [0..0] @1'b1 - the PKA clock is enabled. @1'b0 - the PKA clock + * is disabled. */ + uint32_t : 31; + } CC312_PKA_CLK_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_DMA_CLK_ENABLE_REG; /*!< (@ 0x00000820) DMA_CLK enable register. Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_DMA_CLK_EN : 1; /*!< [0..0] @1'b1 - the DMA clock is enabled. @1'b0 - the DMA clock + * is disabled. */ + uint32_t : 31; + } CC312_DMA_CLK_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_CLK_STATUS_REG; /*!< (@ 0x00000824) The CryptoCell clocks' status register. Note: + * This is a special register, affected by + * internal logic. Test result of this register + * is NA. */ + + struct + { + __IM uint32_t CC312_AES_CLK_STATUS : 1; /*!< [0..0] @1'b1 - the AES clock is enabled. @1'b0 - the AES clock + * is disabled. */ + uint32_t : 1; + __IM uint32_t CC312_HASH_CLK_STATUS : 1; /*!< [2..2] @1'b1 - the HASH clock is enabled. @1'b0 - the HASH clock + * is disabled. */ + __IM uint32_t CC312_PKA_CLK_STATUS : 1; /*!< [3..3] @1'b1 - the PKA clock is enabled. @1'b0 - the PKA clock + * is disabled. */ + uint32_t : 3; + __IM uint32_t CC312_CHACHA_CLK_STATUS : 1; /*!< [7..7] @1'b1 - the CHACHA clock is enabled. @1'b0 - the CHACHA + * clock is disabled. */ + __IM uint32_t CC312_DMA_CLK_STATUS : 1; /*!< [8..8] @1'b1 - the DMA clock is enabled. @1'b0 - the DMA clock + * is disabled. */ + uint32_t : 23; + } CC312_CLK_STATUS_REG_b; + }; + __IM uint32_t RESERVED27[12]; + + union + { + __IOM uint32_t CC312_CHACHA_CLK_ENABLE_REG; /*!< (@ 0x00000858) CHACHA /SALSA clock enable register. Note: This + * is a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __OM uint32_t CC312_CHACHA_CLK_EN : 1; /*!< [0..0] @1'b1 - the CHACHA / SALSA clock is enabled. @1'b0 - + * the CHACHA / SALSA clock is disabled. */ + uint32_t : 31; + } CC312_CHACHA_CLK_ENABLE_REG_b; + }; + __IM uint32_t RESERVED28[41]; + + union + { + __IOM uint32_t CC312_CRYPTO_CTL_REG; /*!< (@ 0x00000900) Defines the cryptographic flow. */ + + struct + { + __OM uint32_t CC312_MODE : 5; /*!< [4..0] Determines the active cryptographic engine: @5'b0000 + * - BYPASS @5'b0001 - AES @5'b0010 - AES_TO_HASH @5'b0011 + * - AES_AND_HASH @5'b0100 - DES @5'b0101 - DES_TO_HASH @5'b0110 + * - DES_AND_HASH @5'b0111 - HASH @5'b1001 - AES_MAC_AND_BYPASS + * @5'b1010 - AES_TO_HASH_AND_DOUT @5'b1011 - Reserved @5'b1000 + * - Reserved */ + uint32_t : 27; + } CC312_CRYPTO_CTL_REG_b; + }; + __IM uint32_t RESERVED29[3]; + + union + { + __IOM uint32_t CC312_CRYPTO_BUSY_REG; /*!< (@ 0x00000910) This register is set when the cryptographic core + * is busy. */ + + struct + { + __IM uint32_t CC312_CRYPTO_BUSY : 1; /*!< [0..0] @1'b0 - Ready @1'b1 - Busy Asserted when AES_BUSY or + * DES_BUSY or HASH_BUSY are asserted or when the DIN FIFO + * is not empty. */ + uint32_t : 31; + } CC312_CRYPTO_BUSY_REG_b; + }; + __IM uint32_t RESERVED30[2]; + + union + { + __IOM uint32_t CC312_HASH_BUSY_REG; /*!< (@ 0x0000091C) This register is set when the Hash engine is + * busy. */ + + struct + { + __IM uint32_t CC312_HASH_BUSY : 1; /*!< [0..0] @1'b0 - Ready @1'b1 - Busy Asserted when hash engine + * is busy. */ + uint32_t : 31; + } CC312_HASH_BUSY_REG_b; + }; + __IM uint32_t RESERVED31[4]; + + union + { + __IOM uint32_t CC312_CONTEXT_ID_REG; /*!< (@ 0x00000930) A general RD/WR register. For Firmware use. */ + + struct + { + __IOM uint32_t CC312_CONTEXT_ID : 8; /*!< [7..0] Context ID */ + uint32_t : 24; + } CC312_CONTEXT_ID_REG_b; + }; + __IM uint32_t RESERVED32[11]; + + union + { + __IOM uint32_t CC312_GHASH_SUBKEY_0_0_REG; /*!< (@ 0x00000960) Bits 31:0 of GHASH Key0 (used as the GHASH module + * key). */ + + struct + { + __OM uint32_t CC312_GHASH_SUBKEY_0_0 : 32; /*!< [31..0] Bits 31:0 of GHASH Key0. */ + } CC312_GHASH_SUBKEY_0_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_SUBKEY_0_1_REG; /*!< (@ 0x00000964) Bits 63:32 of GHASH Key0 (used as the GHASH module + * key). */ + + struct + { + __OM uint32_t CC312_GHASH_SUBKEY_0_1 : 32; /*!< [31..0] Bits 63:32 of GHASH Key0. */ + } CC312_GHASH_SUBKEY_0_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_SUBKEY_0_2_REG; /*!< (@ 0x00000968) Bits 95:64 of GHASH Key0 (used as the GHASH module + * key). */ + + struct + { + __OM uint32_t CC312_GHASH_SUBKEY_0_2 : 32; /*!< [31..0] Bits 95:64 of GHASH Key0. */ + } CC312_GHASH_SUBKEY_0_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_SUBKEY_0_3_REG; /*!< (@ 0x0000096C) Bits 127:96 of GHASH Key0 (used as the GHASH + * module key). */ + + struct + { + __OM uint32_t CC312_GHASH_SUBKEY_0_3 : 32; /*!< [31..0] Bits 127:96 of GHASH Key0. */ + } CC312_GHASH_SUBKEY_0_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_IV_0_0_REG; /*!< (@ 0x00000970) Bits 31:0 of GHASH_IV0 register. GHASH IV0 is + * used as the GHASH IV (Initialization Value) + * register. */ + + struct + { + __IOM uint32_t CC312_GHASH_IV_0_0 : 32; /*!< [31..0] Bits 31:0 of GHASH_IV0 register of the GHASH module. + * For the description of GHASH_IV0, see the GHASH_0_0 register + * description */ + } CC312_GHASH_IV_0_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_IV_0_1_REG; /*!< (@ 0x00000974) Bits 63:32 of GHASH_IV0 register. GHASH IV0 is + * used as the GHASH IV (Initialization Value) + * register. */ + + struct + { + __IOM uint32_t CC312_GHASH_IV_0_1 : 32; /*!< [31..0] Bits 63:32 of GHASH_IV0 register of the GHASH module. + * For the description of GHASH_IV0, see the GHASH_0_0 register + * description */ + } CC312_GHASH_IV_0_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_IV_0_2_REG; /*!< (@ 0x00000978) Bits 95:64 of GHASH_IV0 register. GHASH IV0 is + * used as the GHASH IV (Initialization Value) + * register. */ + + struct + { + __IOM uint32_t CC312_GHASH_IV_0_2 : 32; /*!< [31..0] Bits 95:64 of GHASH_IV0 register of the GHASH module. + * For the description of GHASH_IV0, see the GHASH_0_0 register + * description */ + } CC312_GHASH_IV_0_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_IV_0_3_REG; /*!< (@ 0x0000097C) Bits 127:96 of GHASH_IV0 register. GHASH IV0 + * is used as the GHASH IV (Initialization + * Value) register. */ + + struct + { + __IOM uint32_t CC312_GHASH_IV_0_3 : 32; /*!< [31..0] Bits 127:96 of GHASH_IV0 register of the GHASH module. + * For the description of GHASH_IV0, see the GHASH_0_0 register + * description */ + } CC312_GHASH_IV_0_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_BUSY_REG; /*!< (@ 0x00000980) The GHASH module GHASH_BUSY Register. This register + * is set when the GHASH core is active. */ + + struct + { + __IM uint32_t CC312_GHASH_BUSY : 1; /*!< [0..0] GHASH_BUSY Register. this register is set when the GHASH + * core is active */ + uint32_t : 31; + } CC312_GHASH_BUSY_REG_b; + }; + + union + { + __IOM uint32_t CC312_GHASH_INIT_REG; /*!< (@ 0x00000984) Writing to this address sets the GHASH engine + * to be ready to a new GHASH operation. */ + + struct + { + __OM uint32_t CC312_GHASH_INIT : 1; /*!< [0..0] Writing to this address sets the GHASH engine to be ready + * to a new GHASH operation. */ + uint32_t : 31; + } CC312_GHASH_INIT_REG_b; + }; + __IM uint32_t RESERVED33[30]; + + union + { + __IOM uint32_t CC312_HOST_RGF_IRR_REG; /*!< (@ 0x00000A00) The Interrupt Request register. Each bit of this + * register holds the interrupt status of a + * single interrupt source. */ + + struct + { + uint32_t : 4; + __IM uint32_t CC312_SRAM_TO_DIN_INT : 1; /*!< [4..4] The SRAM to DIN DMA done interrupt status. This interrupt + * is asserted when all data was delivered to DIN buffer from + * SRAM. */ + __IM uint32_t CC312_DOUT_TO_SRAM_INT : 1; /*!< [5..5] The DOUT to SRAM DMA done interrupt status. This interrupt + * is asserted when all data was delivered to SRAM buffer + * from DOUT. */ + __IM uint32_t CC312_MEM_TO_DIN_INT : 1; /*!< [6..6] The memory to DIN DMA done interrupt status. This interrupt + * is asserted when all data was delivered to DIN buffer from + * memory. */ + __IM uint32_t CC312_DOUT_TO_MEM_INT : 1; /*!< [7..7] The DOUT to memory DMA done interrupt status. This interrupt + * is asserted when all data was delivered to memory buffer + * from DOUT. */ + __IM uint32_t CC312_AHB_ERR_INT : 1; /*!< [8..8] The AXI error interrupt status. */ + __IM uint32_t CC312_PKA_EXP_INT : 1; /*!< [9..9] The PKA end of operation interrupt status. */ + __IM uint32_t CC312_RNG_INT : 1; /*!< [10..10] The RNG interrupt status. */ + __IM uint32_t CC312_SYM_DMA_COMPLETED : 1; /*!< [11..11] The GPR interrupt status. */ + uint32_t : 20; + } CC312_HOST_RGF_IRR_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_RGF_IMR_REG; /*!< (@ 0x00000A04) The Interrupt Mask register. Each bit of this + * register holds the mask of a single interrupt + * source. */ + + struct + { + uint32_t : 4; + __IOM uint32_t CC312_SRAM_TO_DIN_MASK : 1; /*!< [4..4] The SRAM to DIN DMA done interrupt mask. */ + __IOM uint32_t CC312_DOUT_TO_SRAM_MASK : 1; /*!< [5..5] The DOUT to SRAM DMA done interrupt mask. */ + __IOM uint32_t CC312_MEM_TO_DIN_MASK : 1; /*!< [6..6] The memory to DIN DMA done interrupt mask. */ + __IOM uint32_t CC312_DOUT_TO_MEM_MASK : 1; /*!< [7..7] The DOUT to memory DMA done interrupt mask. */ + __IOM uint32_t CC312_AXI_ERR_MASK : 1; /*!< [8..8] The AXI error interrupt mask. */ + __IOM uint32_t CC312_PKA_EXP_MASK : 1; /*!< [9..9] The PKA end of operation interrupt mask. */ + __IOM uint32_t CC312_RNG_INT_MASK : 1; /*!< [10..10] The RNG interrupt mask. */ + __IOM uint32_t CC312_SYM_DMA_COMPLETED_MASK : 1; /*!< [11..11] The GPR interrupt mask. */ + uint32_t : 20; + } CC312_HOST_RGF_IMR_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_RGF_ICR_REG; /*!< (@ 0x00000A08) Interrupt Clear Register. */ + + struct + { + uint32_t : 4; + __OM uint32_t CC312_SRAM_TO_DIN_CLEAR : 1; /*!< [4..4] The SRAM to DIN DMA done interrupt clear. */ + __OM uint32_t CC312_DOUT_TO_SRAM_CLEAR : 1; /*!< [5..5] The DOUT to SRAM DMA done interrupt clear. */ + __OM uint32_t CC312_MEM_TO_DIN_CLEAR : 1; /*!< [6..6] The memory to DIN DMA done interrupt clear. */ + __OM uint32_t CC312_DOUT_TO_MEM_CLEAR : 1; /*!< [7..7] The DOUT to memory DMA done interrupt clear. */ + __OM uint32_t CC312_AXI_ERR_CLEAR : 1; /*!< [8..8] The AXI error interrupt clear. */ + __OM uint32_t CC312_PKA_EXP_CLEAR : 1; /*!< [9..9] The PKA end of operation interrupt clear. */ + __OM uint32_t CC312_RNG_INT_CLEAR : 1; /*!< [10..10] The RNG interrupt clear. */ + __OM uint32_t CC312_SYM_DMA_COMPLETED_CLEAR : 1; /*!< [11..11] The GPR interrupt clear. */ + uint32_t : 20; + } CC312_HOST_RGF_ICR_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_RGF_ENDIAN_REG; /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible + * registers. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + uint32_t : 3; + __IOM uint32_t CC312_DOUT_WR_BG : 1; /*!< [3..3] DOUT write endianness: @1'b0 - little endian @1'b1 - + * big endian */ + uint32_t : 3; + __IOM uint32_t CC312_DIN_RD_BG : 1; /*!< [7..7] DIN write endianness: @1'b0 - little endian @1'b1 - big + * endian */ + uint32_t : 3; + __IOM uint32_t CC312_DOUT_WR_WBG : 1; /*!< [11..11] DOUT write word endianness: @1'b0 - little endian @1'b1 + * - big endian */ + uint32_t : 3; + __IOM uint32_t CC312_DIN_RD_WBG : 1; /*!< [15..15] DIN write word endianness: @1'b0 - little endian @1'b1 + * - big endian */ + uint32_t : 16; + } CC312_HOST_RGF_ENDIAN_REG_b; + }; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint32_t CC312_HOST_RGF_SIGNATURE_REG; /*!< (@ 0x00000A24) This register holds the CryptoCell product signature. */ + + struct + { + __IM uint32_t CC312_HOST_SIGNATURE : 32; /*!< [31..0] Identification signature : always returns a fixed value, + * used by Host driver to verify CryptoCell presence at this + * address. */ + } CC312_HOST_RGF_SIGNATURE_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_BOOT_REG; /*!< (@ 0x00000A28) This register holds the values of CryptoCell's + * pre-synthesis flags */ + + struct + { + __IM uint32_t CC312_SYNTHESIS_CONFIG : 1; /*!< [0..0] POWER_GATING_EXISTS_LOCAL */ + __IM uint32_t CC312_LARGE_RKEK_LOCAL : 1; /*!< [1..1] LARGE_RKEK_LOCAL */ + __IM uint32_t CC312_HASH_IN_FUSES_LOCAL : 1; /*!< [2..2] HASH_IN_FUSES_LOCAL */ + __IM uint32_t CC312_EXT_MEM_SECURED_LOCAL : 1; /*!< [3..3] EXT_MEM_SECURED_LOCAL */ + uint32_t : 1; + __IM uint32_t CC312_RKEK_ECC_EXISTS_LOCAL_N : 1; /*!< [5..5] RKEK_ECC_EXISTS_LOCAL_N */ + __IM uint32_t CC312_SRAM_SIZE_LOCAL : 3; /*!< [8..6] SRAM_SIZE_LOCAL */ + __IM uint32_t CC312_DSCRPTR_EXISTS_LOCAL : 1; /*!< [9..9] DSCRPTR_EXISTS_LOCAL */ + __IM uint32_t CC312_PAU_EXISTS_LOCAL : 1; /*!< [10..10] PAU_EXISTS_LOCAL */ + __IM uint32_t CC312_RNG_EXISTS_LOCAL : 1; /*!< [11..11] RNG_EXISTS_LOCAL */ + __IM uint32_t CC312_PKA_EXISTS_LOCAL : 1; /*!< [12..12] PKA_EXISTS_LOCAL */ + __IM uint32_t CC312_RC4_EXISTS_LOCAL : 1; /*!< [13..13] RC4_EXISTS_LOCAL */ + __IM uint32_t CC312_SHA_512_PRSNT_LOCAL : 1; /*!< [14..14] SHA_512_PRSNT_LOCAL */ + __IM uint32_t CC312_SHA_256_PRSNT_LOCAL : 1; /*!< [15..15] SHA_256_PRSNT_LOCAL */ + __IM uint32_t CC312_MD5_PRSNT_LOCAL : 1; /*!< [16..16] MD5_PRSNT_LOCAL */ + __IM uint32_t CC312_HASH_EXISTS_LOCAL : 1; /*!< [17..17] HASH_EXISTS_LOCAL */ + __IM uint32_t CC312_C2_EXISTS_LOCAL : 1; /*!< [18..18] C2_EXISTS_LOCAL */ + __IM uint32_t CC312_DES_EXISTS_LOCAL : 1; /*!< [19..19] DES_EXISTS_LOCAL */ + __IM uint32_t CC312_AES_XCBC_MAC_EXISTS_LOCAL : 1; /*!< [20..20] AES_XCBC_MAC_EXISTS_LOCAL */ + __IM uint32_t CC312_AES_CMAC_EXISTS_LOCAL : 1; /*!< [21..21] AES_CMAC_EXISTS_LOCAL */ + __IM uint32_t CC312_AES_CCM_EXISTS_LOCAL : 1; /*!< [22..22] AES_CCM_EXISTS_LOCAL */ + __IM uint32_t CC312_AES_XEX_HW_T_CALC_LOCAL : 1; /*!< [23..23] AES_XEX_HW_T_CALC_LOCAL */ + __IM uint32_t CC312_AES_XEX_EXISTS_LOCAL : 1; /*!< [24..24] AES_XEX_EXISTS_LOCAL */ + __IM uint32_t CC312_CTR_EXISTS_LOCAL : 1; /*!< [25..25] CTR_EXISTS_LOCAL */ + __IM uint32_t CC312_AES_DIN_BYTE_RESOLUTION_LOCAL : 1; /*!< [26..26] AES_DIN_BYTE_RESOLUTION_LOCAL */ + __IM uint32_t CC312_TUNNELING_ENB_LOCAL : 1; /*!< [27..27] TUNNELING_ENB_LOCAL */ + __IM uint32_t CC312_SUPPORT_256_192_KEY_LOCAL : 1; /*!< [28..28] SUPPORT_256_192_KEY_LOCAL */ + __IM uint32_t CC312_ONLY_ENCRYPT_LOCAL : 1; /*!< [29..29] ONLY_ENCRYPT_LOCAL */ + __IM uint32_t CC312_AES_EXISTS_LOCAL : 1; /*!< [30..30] AES_EXISTS_LOCAL */ + uint32_t : 1; + } CC312_HOST_BOOT_REG_b; + }; + __IM uint32_t RESERVED35[3]; + + union + { + __IOM uint32_t CC312_HOST_CRYPTOKEY_SEL_REG; /*!< (@ 0x00000A38) AES hardware key select. Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_SEL_CRYPTO_KEY : 3; /*!< [2..0] Select the source of the HW key that is used by the AES + * engine: @3'h0 - RKEK @3'h1 -the Krtl. @3'h2 - the provision + * key KCP. @3'h3 - the code encryption key KCE. @3'h4 - the + * KPICV, The ICV provisioning key . @3'h5 - the code encryption + * key KCEICV NOTE: When "kprtl_lock" is set - kprtl will + * be masked (trying to load it will load zeros to the AES + * key register. When "kcertl_lock" is set - kcertl will be + * masked (trying to load it will load zeros to the AES key + * register. When scan_mode is asserted all the RTL */ + uint32_t : 29; + } CC312_HOST_CRYPTOKEY_SEL_REG_b; + }; + __IM uint32_t RESERVED36[15]; + + union + { + __IOM uint32_t CC312_HOST_CORE_CLK_GATING_ENABLE_REG; /*!< (@ 0x00000A78) This register enables the core clk gating by + * masking/enabling the cc_idle_state output + * signal. */ + + struct + { + __IOM uint32_t CC312_HOST_CORE_CLK_GATING_ENABLE : 1; /*!< [0..0] Enable the core clk gating, */ + uint32_t : 31; + } CC312_HOST_CORE_CLK_GATING_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_CC_IS_IDLE_REG; /*!< (@ 0x00000A7C) This register holds the idle indication of CC + * . Note: This is a special register, affected + * by internal logic. Test result of this register + * is NA. */ + + struct + { + __IM uint32_t CC312_HOST_CC_IS_IDLE : 1; /*!< [0..0] Read if CC is idle. */ + __IM uint32_t CC312_HOST_CC_IS_IDLE_EVENT : 1; /*!< [1..1] The event that indicates that CC is idle. */ + __IM uint32_t CC312_SYM_IS_BUSY : 1; /*!< [2..2] symetric flow is busy */ + __IM uint32_t CC312_AHB_IS_IDLE : 1; /*!< [3..3] ahb stste machine is idle */ + __IM uint32_t CC312_NVM_ARB_IS_IDLE : 1; /*!< [4..4] nvm arbiter is idle */ + __IM uint32_t CC312_NVM_IS_IDLE : 1; /*!< [5..5] nvm is idle */ + __IM uint32_t CC312_FATAL_WR : 1; /*!< [6..6] fatal write */ + __IM uint32_t CC312_RNG_IS_IDLE : 1; /*!< [7..7] rng is idle */ + __IM uint32_t CC312_PKA_IS_IDLE : 1; /*!< [8..8] pka is idle */ + __IM uint32_t CC312_CRYPTO_IS_IDLE : 1; /*!< [9..9] crypto flow is done */ + uint32_t : 22; + } CC312_HOST_CC_IS_IDLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_POWERDOWN_REG; /*!< (@ 0x00000A80) This register start the power-down sequence. + * Note: This is a special register, affected + * by internal logic. Test result of this register + * is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_POWERDOWN : 1; /*!< [0..0] Power down enable register. */ + uint32_t : 31; + } CC312_HOST_POWERDOWN_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_REMOVE_GHASH_ENGINE_REG; /*!< (@ 0x00000A84) These inputs are to be statically tied to 0 or + * 1 by the customers. When such an input is + * set, the matching engines inputs are tied + * to zero and its outputs are disconnected, + * so that the engine will be entirely removed + * by Synthesis */ + + struct + { + __IM uint32_t CC312_HOST_REMOVE_GHASH_ENGINE : 1; /*!< [0..0] Read the Remove_chacha_engine input */ + uint32_t : 31; + } CC312_HOST_REMOVE_GHASH_ENGINE_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_REMOVE_CHACHA_ENGINE_REG; /*!< (@ 0x00000A88) These inputs are to be statically tied to 0 or + * 1 by the customers. When such an input is + * set, the matching engines inputs are tied + * to zero and its outputs are disconnected, + * so that the engine will be entirely removed + * by Synthesis */ + + struct + { + __IM uint32_t CC312_HOST_REMOVE_CHACHA_ENGINE : 1; /*!< [0..0] Read the Remove_ghash_engine input */ + uint32_t : 31; + } CC312_HOST_REMOVE_CHACHA_ENGINE_REG_b; + }; + __IM uint32_t RESERVED37[29]; + + union + { + __IOM uint32_t CC312_AHBM_SINGLES_REG; /*!< (@ 0x00000B00) This register forces the ahb transactions to + * be always singles. */ + + struct + { + __IOM uint32_t CC312_AHB_SINGLES : 1; /*!< [0..0] Force ahb singles */ + uint32_t : 31; + } CC312_AHBM_SINGLES_REG_b; + }; + + union + { + __IOM uint32_t CC312_AHBM_HPROT_REG; /*!< (@ 0x00000B04) This register holds the ahb prot value */ + + struct + { + __IOM uint32_t CC312_AHB_PROT : 4; /*!< [3..0] The ahb prot value */ + uint32_t : 28; + } CC312_AHBM_HPROT_REG_b; + }; + + union + { + __IOM uint32_t CC312_AHBM_HMASTLOCK_REG; /*!< (@ 0x00000B08) This register holds ahb hmastlock value */ + + struct + { + __IOM uint32_t CC312_AHB_HMASTLOCK : 1; /*!< [0..0] The hmastlock value. */ + uint32_t : 31; + } CC312_AHBM_HMASTLOCK_REG_b; + }; + + union + { + __IOM uint32_t CC312_AHBM_HNONSEC_REG; /*!< (@ 0x00000B0C) This register holds ahb hnonsec value */ + + struct + { + __IOM uint32_t CC312_AHB_WRITE_HNONSEC : 1; /*!< [0..0] The hnonsec value for write transaction. */ + __IOM uint32_t CC312_AHB_READ_HNONSEC : 1; /*!< [1..1] The hnonsec value for read transaction. */ + uint32_t : 30; + } CC312_AHBM_HNONSEC_REG_b; + }; + __IM uint32_t RESERVED38[60]; + + union + { + __IOM uint32_t CC312_DIN_BUFFER_REG; /*!< (@ 0x00000C00) This address can be used by the CPU to write + * data directly to the DIN buffer to be sent + * to engines. */ + + struct + { + __OM uint32_t CC312_DIN_BUFFER_DATA : 32; /*!< [31..0] This register is mapped into 8 addresses in order to + * enable a CPU burst. */ + } CC312_DIN_BUFFER_REG_b; + }; + __IM uint32_t RESERVED39[7]; + + union + { + __IOM uint32_t CC312_DIN_MEM_DMA_BUSY_REG; /*!< (@ 0x00000C20) Indicates whether memory (AXI) source DMA (DIN) + * is busy. */ + + struct + { + __IM uint32_t CC312_DIN_MEM_DMA_BUSY : 1; /*!< [0..0] DIN memory DMA busy: @1'b1 - busy @1'b0 - not busy */ + uint32_t : 31; + } CC312_DIN_MEM_DMA_BUSY_REG_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t CC312_SRC_LLI_WORD0_REG; /*!< (@ 0x00000C28) This register is used in direct LLI mode - holds + * the location of the data source in the memory + * (AXI). */ + + struct + { + __OM uint32_t CC312_SRC_LLI_WORD0 : 32; /*!< [31..0] Source address within memory. */ + } CC312_SRC_LLI_WORD0_REG_b; + }; + + union + { + __IOM uint32_t CC312_SRC_LLI_WORD1_REG; /*!< (@ 0x00000C2C) This register is used in direct LLI mode - holds + * the number of bytes to be read from the + * memory (AXI). Writing to this register triggers + * the DMA. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __OM uint32_t CC312_SRC_LLI_BYTES_NUM : 30; /*!< [29..0] Total number of bytes to read using DMA in this entry */ + __OM uint32_t CC312_SRC_LLI_FIRST : 1; /*!< [30..30] 1'b1 - Indicates the first LLI entry */ + __OM uint32_t CC312_SRC_LLI_LAST : 1; /*!< [31..31] 1'b1 - Indicates the last LLI entry */ + } CC312_SRC_LLI_WORD1_REG_b; + }; + + union + { + __IOM uint32_t CC312_SRAM_SRC_ADDR_REG; /*!< (@ 0x00000C30) Location of data (start address) to be read from + * SRAM. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IOM uint32_t CC312_SRAM_SRC_ADDR : 32; /*!< [31..0] SRAM source base address of data */ + } CC312_SRAM_SRC_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_DIN_SRAM_BYTES_LEN_REG; /*!< (@ 0x00000C34) This register holds the size of the data (in + * bytes) to be read from the SRAM. Note: This + * is a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_DIN_SRAM_BYTES_LEN : 32; /*!< [31..0] Size of data to read from SRAM (bytes). This is the + * trigger to the SRAM SRC DMA. */ + } CC312_DIN_SRAM_BYTES_LEN_REG_b; + }; + + union + { + __IOM uint32_t CC312_DIN_SRAM_DMA_BUSY_REG; /*!< (@ 0x00000C38) This register holds the status of the SRAM DMA + * DIN. */ + + struct + { + __IM uint32_t CC312_DIN_SRAM_BUSY : 1; /*!< [0..0] DIN SRAM DMA busy: @1'b1 - busy @1'b0 - not busy */ + uint32_t : 31; + } CC312_DIN_SRAM_DMA_BUSY_REG_b; + }; + + union + { + __IOM uint32_t CC312_DIN_SRAM_ENDIANNESS_REG; /*!< (@ 0x00000C3C) This register defines the endianness of the DIN + * interface to SRAM. */ + + struct + { + __IOM uint32_t CC312_SRAM_DIN_ENDIANNESS : 1; /*!< [0..0] Defines the endianness of DIN interface to SRAM: @1'b1 + * - big-endianness @1'b0 - little endianness */ + uint32_t : 31; + } CC312_DIN_SRAM_ENDIANNESS_REG_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IOM uint32_t CC312_DIN_CPU_DATA_SIZE_REG; /*!< (@ 0x00000C48) This register hold the number of bytes to be + * transmited using external DMA Note: This + * is a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __OM uint32_t CC312_CPU_DIN_SIZE : 16; /*!< [15..0] When using external DMA, the size of transmited data + * in bytes should be written to this register. */ + uint32_t : 16; + } CC312_DIN_CPU_DATA_SIZE_REG_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t CC312_FIFO_IN_EMPTY_REG; /*!< (@ 0x00000C50) DIN FIFO empty indication */ + + struct + { + __IM uint32_t CC312_EMPTY : 1; /*!< [0..0] 1'b1 - FIFO empty */ + uint32_t : 31; + } CC312_FIFO_IN_EMPTY_REG_b; + }; + __IM uint32_t RESERVED43; + + union + { + __IOM uint32_t CC312_DIN_FIFO_RST_PNTR_REG; /*!< (@ 0x00000C58) Writing to this register resets the DIN_FIFO + * pointers. */ + + struct + { + __OM uint32_t CC312_RST : 1; /*!< [0..0] Writing any value to this address resets the DIN_FIFO + * pointers. */ + uint32_t : 31; + } CC312_DIN_FIFO_RST_PNTR_REG_b; + }; + __IM uint32_t RESERVED44[41]; + + union + { + __IOM uint32_t CC312_DOUT_BUFFER_REG; /*!< (@ 0x00000D00) CC312_DOUT_BUFFER_REG */ + + struct + { + __IM uint32_t CC312_DOUT_BUFFER_DATA : 32; /*!< [31..0] CC312_DOUT_BUFFER_DATA */ + } CC312_DOUT_BUFFER_REG_b; + }; + __IM uint32_t RESERVED45[7]; + + union + { + __IOM uint32_t CC312_DOUT_MEM_DMA_BUSY_REG; /*!< (@ 0x00000D20) DOUT memory DMA busy - Indicates that memory + * (AXI) destination DMA (DOUT) is busy, */ + + struct + { + __IM uint32_t CC312_DOUT_MEM_DMA_BUSY : 1; /*!< [0..0] DOUT memory DMA busy: @1'b1 - busy @1'b0 - not busy */ + uint32_t : 31; + } CC312_DOUT_MEM_DMA_BUSY_REG_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IOM uint32_t CC312_DST_LLI_WORD0_REG; /*!< (@ 0x00000D28) This register is used in direct LLI mode - holds + * the location of the data destination in + * the memory (AXI) */ + + struct + { + __OM uint32_t CC312_DST_LLI_WORD0 : 32; /*!< [31..0] Destination address within memory */ + } CC312_DST_LLI_WORD0_REG_b; + }; + + union + { + __IOM uint32_t CC312_DST_LLI_WORD1_REG; /*!< (@ 0x00000D2C) This register is used in direct LLI mode - holds + * the number of bytes to be written to the + * memory (AXI). Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IOM uint32_t CC312_DST_LLI_BYTES_NUM : 30; /*!< [29..0] Total byte number to be written by DMA in this entry */ + __IOM uint32_t CC312_DST_LLI_FIRST : 1; /*!< [30..30] 1'b1 - Indicates the first LLI entry */ + __IOM uint32_t CC312_DST_LLI_LAST : 1; /*!< [31..31] 1'b1 - Indicates the last LLI entry */ + } CC312_DST_LLI_WORD1_REG_b; + }; + + union + { + __IOM uint32_t CC312_SRAM_DEST_ADDR_REG; /*!< (@ 0x00000D30) Location of result to be sent to in SRAM Note: + * This is a special register, affected by + * internal logic. Test result of this register + * is NA. */ + + struct + { + __IOM uint32_t CC312_SRAM_DEST : 32; /*!< [31..0] SRAM destination base address for data. */ + } CC312_SRAM_DEST_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_DOUT_SRAM_BYTES_LEN_REG; /*!< (@ 0x00000D34) This register holds the size of the data (in + * bytes) to be written to the SRAM. Note: + * This is a special register, affected by + * internal logic. Test result of this register + * is NA. */ + + struct + { + __IOM uint32_t CC312_DOUT_SRAM_BYTES_LEN : 32; /*!< [31..0] Size of data to write to SRAM (bytes). This is the trigger + * to the SRAM DST DMA. */ + } CC312_DOUT_SRAM_BYTES_LEN_REG_b; + }; + + union + { + __IOM uint32_t CC312_DOUT_SRAM_DMA_BUSY_REG; /*!< (@ 0x00000D38) This register holds the status of the SRAM DMA + * DOUT. */ + + struct + { + __IM uint32_t CC312_DOUT_SRAM_BUSY : 1; /*!< [0..0] @1'b0 - all data was written to SRAM. @1'b1 - DOUT SRAM + * DMA busy. */ + uint32_t : 31; + } CC312_DOUT_SRAM_DMA_BUSY_REG_b; + }; + + union + { + __IOM uint32_t CC312_DOUT_SRAM_ENDIANNESS_REG; /*!< (@ 0x00000D3C) This register defines the endianness of the DOUT + * interface from SRAM. */ + + struct + { + __IOM uint32_t CC312_DOUT_SRAM_ENDIANNESS : 1; /*!< [0..0] Defines the endianness of DOUT interface from SRAM: @1'b1 + * - big-endianness @1'b0 - little endianness */ + uint32_t : 31; + } CC312_DOUT_SRAM_ENDIANNESS_REG_b; + }; + __IM uint32_t RESERVED47; + + union + { + __IOM uint32_t CC312_READ_ALIGN_LAST_REG; /*!< (@ 0x00000D44) Indication that the next read from the CPU is + * the last one. This is needed only when the + * data size is NOT modulo 4 (e.g. HASH padding). */ + + struct + { + __OM uint32_t CC312_READ_ALIGN_LAST : 1; /*!< [0..0] 1'b1 - Flush the read aligner content (used for reading + * the last data). */ + uint32_t : 31; + } CC312_READ_ALIGN_LAST_REG_b; + }; + __IM uint32_t RESERVED48[2]; + + union + { + __IOM uint32_t CC312_DOUT_FIFO_EMPTY_REG; /*!< (@ 0x00000D50) DOUT_FIFO_EMPTY Register. */ + + struct + { + __IM uint32_t CC312_DOUT_FIFO_EMPTY : 1; /*!< [0..0] @1'b0 - DOUT FIFO is not empty @1'b1 - DOUT FIFO is empty */ + uint32_t : 31; + } CC312_DOUT_FIFO_EMPTY_REG_b; + }; + __IM uint32_t RESERVED49[107]; + + union + { + __IOM uint32_t CC312_SRAM_DATA_REG; /*!< (@ 0x00000F00) READ WRITE DATA FROM SRAM Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_SRAM_DATA : 32; /*!< [31..0] 32 bit write or read from SRAM: read - triggers the + * SRAM read DMA address automatically incremented write - + * triggers the SRAM write DMA address automatically incremented */ + } CC312_SRAM_DATA_REG_b; + }; + + union + { + __IOM uint32_t CC312_SRAM_ADDR_REG; /*!< (@ 0x00000F04) first address given to SRAM DMA for read/write + * transactions from SRAM */ + + struct + { + __OM uint32_t CC312_SRAM_ADDR : 15; /*!< [14..0] SRAM starting address */ + uint32_t : 17; + } CC312_SRAM_ADDR_REG_b; + }; + + union + { + __IOM uint32_t CC312_SRAM_DATA_READY_REG; /*!< (@ 0x00000F08) The SRAM content is ready for read in SRAM_DATA. */ + + struct + { + __IM uint32_t CC312_SRAM_READY : 1; /*!< [0..0] SRAM content is ready for read in SRAM_DATA. */ + uint32_t : 31; + } CC312_SRAM_DATA_READY_REG_b; + }; + __IM uint32_t RESERVED50[49]; + + union + { + __IOM uint32_t CC312_PERIPHERAL_ID_4_REG; /*!< (@ 0x00000FD0) no register description provided */ + + struct + { + __IM uint32_t CC312_DES_2_JEP106 : 4; /*!< [3..0] Continuation Code. 0x4 for ARM products. */ + uint32_t : 28; + } CC312_PERIPHERAL_ID_4_REG_b; + }; + __IOM uint32_t CC312_PIDRESERVED0_REG; /*!< (@ 0x00000FD4) no register description provided */ + __IOM uint32_t CC312_PIDRESERVED1_REG; /*!< (@ 0x00000FD8) no register description provided */ + __IOM uint32_t CC312_PIDRESERVED2_REG; /*!< (@ 0x00000FDC) no register description provided */ + + union + { + __IOM uint32_t CC312_PERIPHERAL_ID_0_REG; /*!< (@ 0x00000FE0) no register description provided */ + + struct + { + __IM uint32_t CC312_PART_0 : 8; /*!< [7..0] Identification register part number, bits[7:0] */ + uint32_t : 24; + } CC312_PERIPHERAL_ID_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_PERIPHERAL_ID_1_REG; /*!< (@ 0x00000FE4) no register description provided */ + + struct + { + __IM uint32_t CC312_PART_1 : 4; /*!< [3..0] Identification register part number, bits[11:8] */ + __IM uint32_t CC312_DES_0_JEP106 : 4; /*!< [7..4] identification code, bits[3:0]. 0x3B for ARM products. */ + uint32_t : 24; + } CC312_PERIPHERAL_ID_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_PERIPHERAL_ID_2_REG; /*!< (@ 0x00000FE8) no register description provided */ + + struct + { + __IM uint32_t CC312_DES_1_JEP106 : 3; /*!< [2..0] identification code, bits[6:4]. 0x3B for ARM products. */ + __IM uint32_t CC312_JEDEC : 1; /*!< [3..3] constant 0x1. Indicates that a JEDEC assigned value is + * used. */ + __IM uint32_t CC312_REVISION : 4; /*!< [7..4] starts at zero and increments for every new IP release. */ + uint32_t : 24; + } CC312_PERIPHERAL_ID_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_PERIPHERAL_ID_3_REG; /*!< (@ 0x00000FEC) no register description provided */ + + struct + { + __IM uint32_t CC312_CMOD : 4; /*!< [3..0] Customer Modified, normally zero, but if a partner applies + * any changes themselves, they must change this value. */ + __IM uint32_t CC312_REVAND : 4; /*!< [7..4] starts at zero for every Revision, and increments if + * metal fixes are applied between 2 IP releases. */ + uint32_t : 24; + } CC312_PERIPHERAL_ID_3_REG_b; + }; + + union + { + __IOM uint32_t CC312_COMPONENT_ID_0_REG; /*!< (@ 0x00000FF0) no register description provided */ + + struct + { + __IM uint32_t CC312_PRMBL_0 : 8; /*!< [7..0] constant 0xD */ + uint32_t : 24; + } CC312_COMPONENT_ID_0_REG_b; + }; + + union + { + __IOM uint32_t CC312_COMPONENT_ID_1_REG; /*!< (@ 0x00000FF4) no register description provided */ + + struct + { + __IM uint32_t CC312_PRMBL_1 : 4; /*!< [3..0] constant 0x0 */ + __IM uint32_t CC312_CLASS : 4; /*!< [7..4] component type 0 0xF for Cryptocell */ + uint32_t : 24; + } CC312_COMPONENT_ID_1_REG_b; + }; + + union + { + __IOM uint32_t CC312_COMPONENT_ID_2_REG; /*!< (@ 0x00000FF8) no register description provided */ + + struct + { + __IM uint32_t CC312_PRMBL_2 : 8; /*!< [7..0] constant 0x5 */ + uint32_t : 24; + } CC312_COMPONENT_ID_2_REG_b; + }; + + union + { + __IOM uint32_t CC312_COMPONENT_ID_3_REG; /*!< (@ 0x00000FFC) no register description provided */ + + struct + { + __IM uint32_t CC312_PRMBL_3 : 8; /*!< [7..0] constant 0xB1 */ + uint32_t : 24; + } CC312_COMPONENT_ID_3_REG_b; + }; + __IM uint32_t RESERVED51[896]; + + union + { + __IOM uint32_t CC312_HOST_DCU_EN0_REG; /*!< (@ 0x00001E00) The DCU [31:0] enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_EN0 : 32; /*!< [31..0] Debug Control Unit (DCU) Enable bits. */ + } CC312_HOST_DCU_EN0_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_EN1_REG; /*!< (@ 0x00001E04) The DCU [63:32] enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_EN1 : 32; /*!< [31..0] Debug Control Unit (DCU) Enable bits. */ + } CC312_HOST_DCU_EN1_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_EN2_REG; /*!< (@ 0x00001E08) The DCU [95:64] enable register. Note: This is + * a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_EN2 : 32; /*!< [31..0] Debug Control Unit (DCU) Enable bits. */ + } CC312_HOST_DCU_EN2_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_EN3_REG; /*!< (@ 0x00001E0C) The DCU [1271:96] enable register. Note: This + * is a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_EN3 : 32; /*!< [31..0] Debug Control Unit (DCU) Enable bits. */ + } CC312_HOST_DCU_EN3_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_LOCK0_REG; /*!< (@ 0x00001E10) The DCU lock register.Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_LOCK0 : 32; /*!< [31..0] DCU_lock [31:0] register (a dedicated lock register + * per DCU bit). */ + } CC312_HOST_DCU_LOCK0_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_LOCK1_REG; /*!< (@ 0x00001E14) The DCU lock register.Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_LOCK1 : 32; /*!< [31..0] DCU_lock [63:32] register (a dedicated lock register + * per DCU bit). */ + } CC312_HOST_DCU_LOCK1_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_LOCK2_REG; /*!< (@ 0x00001E18) The DCU lock register.Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_LOCK2 : 32; /*!< [31..0] DCU_lock [95:64] register (a dedicated lock register + * per DCU bit). */ + } CC312_HOST_DCU_LOCK2_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_DCU_LOCK3_REG; /*!< (@ 0x00001E1C) The DCU lock register.Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_DCU_LOCK3 : 32; /*!< [31..0] DCU_lock [127:96] register (a dedicated lock register + * per DCU bit). */ + } CC312_HOST_DCU_LOCK3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG; /*!< (@ 0x00001E20) The DCU lock register. */ + + struct + { + __IM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK0 : 32; /*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will + * be a customer modifiable. */ + } CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG; /*!< (@ 0x00001E24) The "ICV_DCU_restriction_mask" parameter is read + * by FW during the secure debug verification + * to prevent OEM from setting specific DCUs + * that protect ICV secrets */ + + struct + { + __IM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK1 : 32; /*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that + * will be a customer modifiable. */ + } CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG; /*!< (@ 0x00001E28) The "ICV_DCU_restriction_mask" parameter is read + * by FW during the secure debug verification + * to prevent OEM from setting specific DCUs + * that protect ICV secrets */ + + struct + { + __IM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK2 : 32; /*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that + * will be a customer modifiable. */ + } CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG; /*!< (@ 0x00001E2C) The "ICV_DCU_restriction_mask" parameter is read + * by FW during the secure debug verification + * to prevent OEM from setting specific DCUs + * that protect ICV secrets */ + + struct + { + __IM uint32_t CC312_AO_ICV_DCU_RESTRICTION_MASK3 : 32; /*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that + * will be a customer modifiable. */ + } CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_CC_SEC_DEBUG_RESET_REG; /*!< (@ 0x00001E30) The reset-upon-debug indication */ + + struct + { + __IM uint32_t CC312_AO_CC_SEC_DEBUG_RESET : 1; /*!< [0..0] For resets Cerberus, and prevents loading the HW keys + * after that reset */ + uint32_t : 31; + } CC312_AO_CC_SEC_DEBUG_RESET_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_AO_LOCK_BITS_REG; /*!< (@ 0x00001E34) These masks will define, per LCS, which DCU bits + * will be tied to zero, even if the Host tries + * to set them. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IOM uint32_t CC312_HOST_FATAL_ERR : 1; /*!< [0..0] When the "FATAL_ERROR" register is asserted - HW keys + * will not be copied from OTP */ + __IOM uint32_t CC312_HOST_KPICV_LOCK : 1; /*!< [1..1] When this FW controlled register is set, the Kpicv HW + * key is masked (to zero). */ + __IOM uint32_t CC312_HOST_KCEICV_LOCK : 1; /*!< [2..2] When this FW controlled register is set, the Kceicv HW + * key is masked (to zero). */ + __IOM uint32_t CC312_HOST_KCP_LOCK : 1; /*!< [3..3] When this FW controlled register is set, the Kcp HW key + * is masked (to zero). */ + __IOM uint32_t CC312_HOST_KCE_LOCK : 1; /*!< [4..4] When this FW controlled register is set, the Kce HW key + * is masked (to zero). */ + __IOM uint32_t CC312_HOST_ICV_RMA_LOCK : 1; /*!< [5..5] The ICV_RMA_LOCK register is set-once (per POR). */ + __IOM uint32_t CC312_RESET_UPON_DEBUG_DISABLE : 1; /*!< [6..6] The RESET_UPON_DEBUG_DISABLE register is set-once (per + * POR). */ + __IOM uint32_t CC312_HOST_FORCE_DFA_ENABLE : 1; /*!< [7..7] When this FW controlled register is set, the AES DFA + * countermeasures are enabled/disabled (regardless of the + * AES_DFA_IS_ON register value). */ + __IOM uint32_t CC312_HOST_DFA_ENABLE_LOCK : 1; /*!< [8..8] When this FW control is set, the DFA_ENABLE register + * can't be written until the next POR. The DFA_ENABLE_LOCK + * register is set-once (per POR). */ + uint32_t : 23; + } CC312_HOST_AO_LOCK_BITS_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_APB_FILTERING_REG; /*!< (@ 0x00001E38) This register holds the AO_APB_FILTERING data. + * Note: This is a special register, affected + * by internal logic. Test result of this register + * is NA. */ + + struct + { + __IOM uint32_t CC312_ONLY_SEC_ACCESS_ALLOW : 1; /*!< [0..0] when this FW controlled register is set, the APB slave + * accepts only secure accesses */ + __IOM uint32_t CC312_ONLY_SEC_ACCESS_ALLOW_LOCK : 1; /*!< [1..1] when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED + * register can't be modified (until the next POR). */ + __IOM uint32_t CC312_ONLY_PRIV_ACCESS_ALLOW : 1; /*!< [2..2] when this FW controlled register is set, the APB slave + * accepts only privileged accesses */ + __IOM uint32_t CC312_ONLY_PRIV_ACCESS_ALLOW_LOCK : 1; /*!< [3..3] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO + * ED register can't be modified (until the next POR) */ + __IOM uint32_t CC312_APBC_ONLY_SEC_ACCESS_ALLOW : 1; /*!< [4..4] when this FW controlled register is set, the APB-C slave + * accepts only secure accesses */ + __IOM uint32_t CC312_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK : 1; /*!< [5..5] when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOW + * D register can't be modified (until the next POR). */ + __IOM uint32_t CC312_APBC_ONLY_PRIV_ACCESS_ALLOW : 1; /*!< [6..6] when this FW controlled register is set, the APB-C slave + * accepts only privileged accesses */ + __IOM uint32_t CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK : 1; /*!< [7..7] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO + * ED register can't be modified (until the next POR) */ + __IOM uint32_t CC312_APBC_ONLY_INST_ACCESS_ALLOW : 1; /*!< [8..8] when this FW controlled register is set, the APB-C slave + * accepts only instruction accesses */ + __IOM uint32_t CC312_APBC_ONLY_INST_ACCESS_ALLOW_LOCK : 1; /*!< [9..9] when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLO + * ED register can't be modified (until the next POR) */ + uint32_t : 22; + } CC312_AO_APB_FILTERING_REG_b; + }; + + union + { + __IOM uint32_t CC312_AO_CC_GPPC_REG; /*!< (@ 0x00001E3C) holds the AO_CC_GPPC value from AO Note: This + * is a special register, affected by internal + * logic. Test result of this register is NA. */ + + struct + { + __IM uint32_t CC312_AO_CC_GPPC : 8; /*!< [7..0] The AO_CC_GPPC value */ + uint32_t : 24; + } CC312_AO_CC_GPPC_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_RGF_CC_SW_RST_REG; /*!< (@ 0x00001E40) Writing to this register generates a general + * reset to CryptoCell. This reset takes about + * 4 core clock cycles. Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + __OM uint32_t CC312_HOST_RGF_CC_SW_RST : 1; /*!< [0..0] Writing '1' to this field generates a general reset to + * CryptoCell. */ + uint32_t : 31; + } CC312_HOST_RGF_CC_SW_RST_REG_b; + }; + __IM uint32_t RESERVED52[48]; + + union + { + __IOM uint32_t CC312_AIB_FUSE_PROG_COMPLETED_REG; /*!< (@ 0x00001F04) This register reflects the fuse_aib_prog_completed + * input, which indicates that the fuse programming + * was completed. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IM uint32_t CC312_AIB_FUSE_PROG_COMPLETED : 1; /*!< [0..0] Indicates if the fuse programming operation has been + * completed. */ + uint32_t : 31; + } CC312_AIB_FUSE_PROG_COMPLETED_REG_b; + }; + + union + { + __IOM uint32_t CC312_NVM_DEBUG_STATUS_REG; /*!< (@ 0x00001F08) AIB debug status register. Note: This is a special + * register, affected by internal logic. Test + * result of this register is NA. */ + + struct + { + uint32_t : 1; + __IM uint32_t CC312_NVM_SM : 3; /*!< [3..1] Main nvm fsm 3'b000 - IDLE 3'b001 - READ_DUMMY 3'b010 + * - READ_MAN_FLAG 3'b011 - READ_OEM_FLAG 3'b100 - READ_GPPC + * 3'b101 - DECODE 3'b110 - OTP_LCS_VALID 3'b111 - LCS_IS_VALID */ + uint32_t : 28; + } CC312_NVM_DEBUG_STATUS_REG_b; + }; + + union + { + __IOM uint32_t CC312_LCS_IS_VALID_REG; /*!< (@ 0x00001F0C) Indicates that the LCS register holds a valid + * value. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IM uint32_t CC312_LCS_IS_VALID : 1; /*!< [0..0] Indicates whether LCS is valid. */ + uint32_t : 31; + } CC312_LCS_IS_VALID_REG_b; + }; + + union + { + __IOM uint32_t CC312_NVM_IS_IDLE_REG; /*!< (@ 0x00001F10) Indicates that the LCS register holds a valid + * value. Note: This is a special register, + * affected by internal logic. Test result + * of this register is NA. */ + + struct + { + __IM uint32_t CC312_NVM_IS_IDLE_STATUS : 1; /*!< [0..0] Indicates whether the NVM manager finishes its operation, + * calculates the LCS, reads the HW keys, compares the number + * of zeros and clears the keys */ + uint32_t : 31; + } CC312_NVM_IS_IDLE_REG_b; + }; + + union + { + __IOM uint32_t CC312_LCS_REG_REG; /*!< (@ 0x00001F14) The lifecycle state register. Note: This is a + * special register, affected by internal logic. + * Test result of this register is NA. */ + + struct + { + __IM uint32_t CC312_LCS_REG : 3; /*!< [2..0] Indicates the LCS (Lifecycle State) value. 3'b000 - CM + * 3'b001 - DM 3'b101 - SE 3'b111 - RMA */ + uint32_t : 5; + __IM uint32_t CC312_ERROR_KDR_ZERO_CNT : 1; /*!< [8..8] Indication that the number of zeroes in the loaded KDR + * is not equal to the value set in the manufacture flag. */ + __IM uint32_t CC312_ERROR_PROV_ZERO_CNT : 1; /*!< [9..9] Indication that the number of zeroes in the loaded KCP + * is not equal to the value set in the OEM flag. */ + __IM uint32_t CC312_ERROR_KCE_ZERO_CNT : 1; /*!< [10..10] Indication that the number of zeroes in the loaded + * KCE is not equal to the value set in the OEM flag. */ + __IM uint32_t CC312_ERROR_KPICV_ZERO_CNT : 1; /*!< [11..11] Indication that the number of zeroes in the loaded + * KPICV is not equal to the value set in the manufacture + * flag. */ + __IM uint32_t CC312_ERROR_KCEICV_ZERO_CNT : 1; /*!< [12..12] Indication that the number of zeroes in the loaded + * KCEICV is not equal to the value set in the manufacture + * flag. */ + uint32_t : 19; + } CC312_LCS_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_SHADOW_KDR_REG_REG; /*!< (@ 0x00001F18) This register interface is used to update the + * RKEK(KDR) registers when the device is in + * CM or DM mode , it is Write-once (per warm + * boot) in RMA LCS, The RKEK is updated by + * shifting . */ + + struct + { + __OM uint32_t CC312_HOST_SHADOW_KDR_REG : 1; /*!< [0..0] This field is used to update the KDR registers when the + * device is in CM , DM or RMA mode, The KDR is updated by + * shifting . */ + uint32_t : 31; + } CC312_HOST_SHADOW_KDR_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_SHADOW_KCP_REG_REG; /*!< (@ 0x00001F1C) This register interface is used to update the + * KCP registers when the device is in CM or + * DM mode, The KCP is updated by shifting */ + + struct + { + __OM uint32_t CC312_HOST_SHADOW_KCP_REG : 1; /*!< [0..0] This field is used to update the KCP registers when the + * device is in CM or DM mode, The KCP is updated by shifting */ + uint32_t : 31; + } CC312_HOST_SHADOW_KCP_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_SHADOW_KCE_REG_REG; /*!< (@ 0x00001F20) This register interface is used to update the + * KCE registers when the device is in CM or + * DM mode, The KCE is updated by shifting */ + + struct + { + __OM uint32_t CC312_HOST_SHADOW_KCE_REG : 1; /*!< [0..0] This field is used to update the KCE registers when the + * device is in CM or DM mode, The KCE is updated by shifting */ + uint32_t : 31; + } CC312_HOST_SHADOW_KCE_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_SHADOW_KPICV_REG_REG; /*!< (@ 0x00001F24) This register interface is used to update the + * KPICV registers when the device is in CM + * or DM mode, The KPICV is updated by shifting */ + + struct + { + __OM uint32_t CC312_HOST_SHADOW_KPICV_REG : 1; /*!< [0..0] This field is used to update the KPICV registers when + * the device is in CM or DM mode, The KPICV is updated by + * shifting */ + uint32_t : 31; + } CC312_HOST_SHADOW_KPICV_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_HOST_SHADOW_KCEICV_REG_REG; /*!< (@ 0x00001F28) This register interface is used to update the + * KCEICV registers when the device is in CM + * or DM mode, The KCEICV is updated by shifting */ + + struct + { + __OM uint32_t CC312_HOST_SHADOW_KCEICV_REG : 1; /*!< [0..0] This field is used to update the KCEICV registers when + * the device is in CM or DM mode, The KCEICV is updated by + * shifting */ + uint32_t : 31; + } CC312_HOST_SHADOW_KCEICV_REG_REG_b; + }; + + union + { + __IOM uint32_t CC312_OTP_ADDR_WIDTH_DEF_REG; /*!< (@ 0x00001F2C) OTP_ADDR_WIDTH parameter, that will define the + * integrated OTP address width (address in + * words). The supported sizes are 6 (for 2 + * Kbits),7,8,9,11 (for 64 Kbits). The default + * value in the provided RTL will be 6. Note: + * This is a special register, affected by + * internal logic. Test result of this register + * is NA. */ + + struct + { + __IM uint32_t CC312_OTP_ADDR_WIDTH_DEF : 4; /*!< [3..0] Holds the OTP_ADDR_WIDTH_DEF value. */ + uint32_t : 28; + } CC312_OTP_ADDR_WIDTH_DEF_REG_b; + }; +} CC312_Type; /*!< Size = 7984 (0x1f30) */ + +/* =========================================================================================================================== */ +/* ================ CHIP_VERSION ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CHIP_VERSION registers (CHIP_VERSION) + */ + +typedef struct /*!< (@ 0x40070200) CHIP_VERSION Structure */ +{ + union + { + __IOM uint32_t CHIP_ID1_REG; /*!< (@ 0x00000000) Chip identification register 1. */ + + struct + { + __IM uint32_t CHIP_ID1 : 8; /*!< [7..0] First character of device type "3095" in ASCII. */ + uint32_t : 24; + } CHIP_ID1_REG_b; + }; + + union + { + __IOM uint32_t CHIP_ID2_REG; /*!< (@ 0x00000004) Chip identification register 2. */ + + struct + { + __IM uint32_t CHIP_ID2 : 8; /*!< [7..0] Second character of device type "3095" in ASCII. */ + uint32_t : 24; + } CHIP_ID2_REG_b; + }; + + union + { + __IOM uint32_t CHIP_ID3_REG; /*!< (@ 0x00000008) Chip identification register 3. */ + + struct + { + __IM uint32_t CHIP_ID3 : 8; /*!< [7..0] Third character of device type "3095"" in ASCII. */ + uint32_t : 24; + } CHIP_ID3_REG_b; + }; + + union + { + __IOM uint32_t CHIP_ID4_REG; /*!< (@ 0x0000000C) Chip identification register 4. */ + + struct + { + __IM uint32_t CHIP_ID4 : 8; /*!< [7..0] Fourth character of device type "3095" in ASCII. */ + uint32_t : 24; + } CHIP_ID4_REG_b; + }; + + union + { + __IOM uint32_t CHIP_SWC_REG; /*!< (@ 0x00000010) Software compatibility register. */ + + struct + { + __IM uint32_t CHIP_SWC : 4; /*!< [3..0] SoftWare Compatibility code.Integer (default = 0) which + * is incremented if a silicon change has impact on the CPU + * Firmware.Can be used by software developers to write silicon + * revision dependent code. */ + uint32_t : 28; + } CHIP_SWC_REG_b; + }; + + union + { + __IOM uint32_t CHIP_REVISION_REG; /*!< (@ 0x00000014) Chip revision register. */ + + struct + { + __IM uint32_t CHIP_REVISION : 8; /*!< [7..0] Chip version, corresponds with type number in ASCII.0x41 + * = 'A', 0x42 = 'B' */ + uint32_t : 24; + } CHIP_REVISION_REG_b; + }; + __IM uint32_t RESERVED[56]; + + union + { + __IOM uint32_t CHIP_TEST1_REG; /*!< (@ 0x000000F8) Chip test register 1. */ + + struct + { + __IM uint32_t CHIP_LAYOUT_REVISION : 8; /*!< [7..0] Chip layout revision, corresponds with type number in + * ASCII.0x41 = 'A', 0x43 = 'C', etc for the WLCSP package0x42 + * = 'B', 0x44 = 'D', etc for the VFBGA package */ + uint32_t : 24; + } CHIP_TEST1_REG_b; + }; + + union + { + __IOM uint32_t CHIP_TEST2_REG; /*!< (@ 0x000000FC) Chip test register 2. */ + + struct + { + __IM uint32_t CHIP_METAL_OPTION : 4; /*!< [3..0] Chip metal option value. */ + uint32_t : 28; + } CHIP_TEST2_REG_b; + }; +} CHIP_VERSION_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ CLKCAL_BIF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CLKCAL_BIF registers (CLKCAL_BIF) + */ + +typedef struct /*!< (@ 0x40090600) CLKCAL_BIF Structure */ +{ + union + { + __IOM uint32_t CLK_REF_SEL_REG; /*!< (@ 0x00000000) Select clock for oscillator calibration */ + + struct + { + __IOM uint32_t REF_CLK_SEL : 3; /*!< [2..0] Reference clock slection for calibration (N Counter)0: + * XTAL32K1: RCX32K2: SYS_HCLK3: AUD_CLK4: XTAL40M5: OSC_10MHz6-7: + * Reserved */ + __IOM uint32_t REF_CAL_START : 1; /*!< [3..3] Writing a '1' starts a calibration. This bit is cleared + * when calibration is finished, and CLK_REF_VAL is ready. */ + __IOM uint32_t EXT_CNT_EN_SEL : 1; /*!< [4..4] 0: Enable M Counter counter by N counter1: Enable M Counter + * by UART RX pin selected by PPA */ + __IOM uint32_t CAL_CLK_SEL : 3; /*!< [7..5] Select calibration clock input to be used in calibration: + * (M Counter)0: XTAL32K1: RCX32K2: SYS_HCLK3: AUD_CLK4: XTAL40M5: + * OSC_10M6-7: Reserved */ + uint32_t : 24; + } CLK_REF_SEL_REG_b; + }; + + union + { + __IOM uint32_t CLK_REF_CNT_REG; /*!< (@ 0x00000004) Count value for oscillator calibration */ + + struct + { + __IOM uint32_t REF_CNT_VAL : 16; /*!< [15..0] Indicates the calibration time, with a decrement counter + * to 1. */ + uint32_t : 16; + } CLK_REF_CNT_REG_b; + }; + + union + { + __IOM uint32_t CLK_REF_VAL_REG; /*!< (@ 0x00000008) DIVN reference cycles, lower 16 bits */ + + struct + { + __IM uint32_t XTAL_CNT_VAL : 32; /*!< [31..0] Returns the number of DIVN clock cycles counted during + * the calibration time, defined with REF_CNT_VAL */ + } CLK_REF_VAL_REG_b; + }; + + union + { + __IOM uint32_t CLK_CAL_IRQ_REG; /*!< (@ 0x0000000C) Select clock for oscillator calibration */ + + struct + { + __IOM uint32_t CLK_CAL_IRQ_EN : 1; /*!< [0..0] Enable clk calibration IRQ.0: Disabled.1*: Enabled.*Note: + * If IRQ feature is enabled, every calibration should be + * started by setting CLK_REF_SEL_REG[REF_CAL_START] to 1. */ + __IM uint32_t CLK_CAL_IRQ_STATUS : 1; /*!< [1..1] Shows the IRQ bit status. */ + __IOM uint32_t CLK_CAL_IRQ_CLR : 1; /*!< [2..2] Clear the IRQ.1: Clear the IRQ0: No effect.Read out 0 + * always. */ + uint32_t : 29; + } CLK_CAL_IRQ_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_0_REG; /*!< (@ 0x00000010) ADC_DIG_O_CALED_WEIGHT_I_0_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_0 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_0 */ + } ADC_DIG_O_CALED_WEIGHT_I_0_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_1_REG; /*!< (@ 0x00000014) ADC_DIG_O_CALED_WEIGHT_I_1_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_1 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_1 */ + } ADC_DIG_O_CALED_WEIGHT_I_1_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_2_REG; /*!< (@ 0x00000018) ADC_DIG_O_CALED_WEIGHT_I_2_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_2 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_2 */ + } ADC_DIG_O_CALED_WEIGHT_I_2_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_3_REG; /*!< (@ 0x0000001C) ADC_DIG_O_CALED_WEIGHT_I_3_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_3 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_3 */ + } ADC_DIG_O_CALED_WEIGHT_I_3_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_4_REG; /*!< (@ 0x00000020) ADC_DIG_O_CALED_WEIGHT_I_4_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_4 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_4 */ + } ADC_DIG_O_CALED_WEIGHT_I_4_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_5_REG; /*!< (@ 0x00000024) ADC_DIG_O_CALED_WEIGHT_I_5_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_5 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_5 */ + } ADC_DIG_O_CALED_WEIGHT_I_5_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_6_REG; /*!< (@ 0x00000028) ADC_DIG_O_CALED_WEIGHT_I_6_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_6 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_6 */ + } ADC_DIG_O_CALED_WEIGHT_I_6_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_7_REG; /*!< (@ 0x0000002C) ADC_DIG_O_CALED_WEIGHT_I_7_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_7 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_7 */ + } ADC_DIG_O_CALED_WEIGHT_I_7_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_8_REG; /*!< (@ 0x00000030) ADC_DIG_O_CALED_WEIGHT_I_8_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_8 : 32; /*!< [31..0] adc_dig_o_caled_weight_i_8 */ + } ADC_DIG_O_CALED_WEIGHT_I_8_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_I_9_REG; /*!< (@ 0x00000034) ADC_DIG_O_CALED_WEIGHT_I_9_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_i_9 : 27; /*!< [26..0] adc_dig_o_caled_weight_i_9 */ + uint32_t : 5; + } ADC_DIG_O_CALED_WEIGHT_I_9_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_0_REG; /*!< (@ 0x00000038) ADC_DIG_O_CALED_WEIGHT_Q_0_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_0 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_0 */ + } ADC_DIG_O_CALED_WEIGHT_Q_0_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_1_REG; /*!< (@ 0x0000003C) ADC_DIG_O_CALED_WEIGHT_Q_1_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_1 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_1 */ + } ADC_DIG_O_CALED_WEIGHT_Q_1_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_2_REG; /*!< (@ 0x00000040) ADC_DIG_O_CALED_WEIGHT_Q_2_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_2 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_2 */ + } ADC_DIG_O_CALED_WEIGHT_Q_2_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_3_REG; /*!< (@ 0x00000044) ADC_DIG_O_CALED_WEIGHT_Q_3_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_3 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_3 */ + } ADC_DIG_O_CALED_WEIGHT_Q_3_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_4_REG; /*!< (@ 0x00000048) ADC_DIG_O_CALED_WEIGHT_Q_4_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_4 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_4 */ + } ADC_DIG_O_CALED_WEIGHT_Q_4_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_5_REG; /*!< (@ 0x0000004C) ADC_DIG_O_CALED_WEIGHT_Q_5_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_5 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_5 */ + } ADC_DIG_O_CALED_WEIGHT_Q_5_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_6_REG; /*!< (@ 0x00000050) ADC_DIG_O_CALED_WEIGHT_Q_6_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_6 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_6 */ + } ADC_DIG_O_CALED_WEIGHT_Q_6_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_7_REG; /*!< (@ 0x00000054) ADC_DIG_O_CALED_WEIGHT_Q_7_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_7 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_7 */ + } ADC_DIG_O_CALED_WEIGHT_Q_7_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_8_REG; /*!< (@ 0x00000058) ADC_DIG_O_CALED_WEIGHT_Q_8_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_8 : 32; /*!< [31..0] adc_dig_o_caled_weight_q_8 */ + } ADC_DIG_O_CALED_WEIGHT_Q_8_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_O_CALED_WEIGHT_Q_9_REG; /*!< (@ 0x0000005C) ADC_DIG_O_CALED_WEIGHT_Q_9_REG */ + + struct + { + __IM uint32_t adc_dig_o_caled_weight_q_9 : 27; /*!< [26..0] adc_dig_o_caled_weight_q_9 */ + uint32_t : 5; + } ADC_DIG_O_CALED_WEIGHT_Q_9_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_0_REG; /*!< (@ 0x00000060) ADC_DIG_CAL_WEIGHT_I_0_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_0 : 32; /*!< [31..0] adc_dig_cal_weight_i_0 */ + } ADC_DIG_CAL_WEIGHT_I_0_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_1_REG; /*!< (@ 0x00000064) ADC_DIG_CAL_WEIGHT_I_1_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_1 : 32; /*!< [31..0] adc_dig_cal_weight_i_1 */ + } ADC_DIG_CAL_WEIGHT_I_1_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_2_REG; /*!< (@ 0x00000068) ADC_DIG_CAL_WEIGHT_I_2_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_2 : 32; /*!< [31..0] adc_dig_cal_weight_i_2 */ + } ADC_DIG_CAL_WEIGHT_I_2_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_3_REG; /*!< (@ 0x0000006C) ADC_DIG_CAL_WEIGHT_I_3_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_3 : 32; /*!< [31..0] adc_dig_cal_weight_i_3 */ + } ADC_DIG_CAL_WEIGHT_I_3_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_4_REG; /*!< (@ 0x00000070) ADC_DIG_CAL_WEIGHT_I_4_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_4 : 32; /*!< [31..0] adc_dig_cal_weight_i_4 */ + } ADC_DIG_CAL_WEIGHT_I_4_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_5_REG; /*!< (@ 0x00000074) ADC_DIG_CAL_WEIGHT_I_5_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_5 : 32; /*!< [31..0] adc_dig_cal_weight_i_5 */ + } ADC_DIG_CAL_WEIGHT_I_5_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_6_REG; /*!< (@ 0x00000078) ADC_DIG_CAL_WEIGHT_I_6_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_6 : 32; /*!< [31..0] adc_dig_cal_weight_i_6 */ + } ADC_DIG_CAL_WEIGHT_I_6_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_7_REG; /*!< (@ 0x0000007C) ADC_DIG_CAL_WEIGHT_I_7_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_7 : 32; /*!< [31..0] adc_dig_cal_weight_i_7 */ + } ADC_DIG_CAL_WEIGHT_I_7_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_8_REG; /*!< (@ 0x00000080) ADC_DIG_CAL_WEIGHT_I_8_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_8 : 32; /*!< [31..0] adc_dig_cal_weight_i_8 */ + } ADC_DIG_CAL_WEIGHT_I_8_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_I_9_REG; /*!< (@ 0x00000084) ADC_DIG_CAL_WEIGHT_I_9_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_i_9 : 27; /*!< [26..0] adc_dig_cal_weight_i_9 */ + uint32_t : 5; + } ADC_DIG_CAL_WEIGHT_I_9_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_0_REG; /*!< (@ 0x00000088) ADC_DIG_CAL_WEIGHT_Q_0_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_0 : 32; /*!< [31..0] adc_dig_cal_weight_q_0 */ + } ADC_DIG_CAL_WEIGHT_Q_0_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_1_REG; /*!< (@ 0x0000008C) ADC_DIG_CAL_WEIGHT_Q_1_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_1 : 32; /*!< [31..0] adc_dig_cal_weight_q_1 */ + } ADC_DIG_CAL_WEIGHT_Q_1_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_2_REG; /*!< (@ 0x00000090) ADC_DIG_CAL_WEIGHT_Q_2_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_2 : 32; /*!< [31..0] adc_dig_cal_weight_q_2 */ + } ADC_DIG_CAL_WEIGHT_Q_2_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_3_REG; /*!< (@ 0x00000094) ADC_DIG_CAL_WEIGHT_Q_3_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_3 : 32; /*!< [31..0] adc_dig_cal_weight_q_3 */ + } ADC_DIG_CAL_WEIGHT_Q_3_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_4_REG; /*!< (@ 0x00000098) ADC_DIG_CAL_WEIGHT_Q_4_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_4 : 32; /*!< [31..0] adc_dig_cal_weight_q_4 */ + } ADC_DIG_CAL_WEIGHT_Q_4_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_5_REG; /*!< (@ 0x0000009C) ADC_DIG_CAL_WEIGHT_Q_5_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_5 : 32; /*!< [31..0] adc_dig_cal_weight_q_5 */ + } ADC_DIG_CAL_WEIGHT_Q_5_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_6_REG; /*!< (@ 0x000000A0) ADC_DIG_CAL_WEIGHT_Q_6_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_6 : 32; /*!< [31..0] adc_dig_cal_weight_q_6 */ + } ADC_DIG_CAL_WEIGHT_Q_6_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_7_REG; /*!< (@ 0x000000A4) ADC_DIG_CAL_WEIGHT_Q_7_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_7 : 32; /*!< [31..0] adc_dig_cal_weight_q_7 */ + } ADC_DIG_CAL_WEIGHT_Q_7_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_8_REG; /*!< (@ 0x000000A8) ADC_DIG_CAL_WEIGHT_Q_8_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_8 : 32; /*!< [31..0] adc_dig_cal_weight_q_8 */ + } ADC_DIG_CAL_WEIGHT_Q_8_REG_b; + }; + + union + { + __IOM uint32_t ADC_DIG_CAL_WEIGHT_Q_9_REG; /*!< (@ 0x000000AC) ADC_DIG_CAL_WEIGHT_Q_9_REG */ + + struct + { + __IOM uint32_t adc_dig_cal_weight_q_9 : 27; /*!< [26..0] adc_dig_cal_weight_q_9 */ + uint32_t : 5; + } ADC_DIG_CAL_WEIGHT_Q_9_REG_b; + }; +} CLKCAL_BIF_Type; /*!< Size = 176 (0xb0) */ + +/* =========================================================================================================================== */ +/* ================ CRG_APU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRG_APU registers (CRG_APU) + */ + +typedef struct /*!< (@ 0x400E0000) CRG_APU Structure */ +{ + union + { + __IOM uint32_t APU_AUD_CLK_REG; /*!< (@ 0x00000000) AUD_CLK_DIV clock control */ + + struct + { + __IOM uint32_t AUD_CLK_DIV : 4; /*!< [3..0] AUD_CLK_DIV clock divider0x0: divided by 160x1: divided + * by 10x2: divided by 20x3: divided by 30x4: divided by 40x5: + * divided by 50x6: divided by 60x7: divided by 70x8: divided + * by 80x9: divided by 90xA: divided by 100xB: divided by + * 110xC: divided by 120xD: divided by 130xE: divided by 140xF: + * divided by 15 */ + __IOM uint32_t AUD_CLK_EN : 1; /*!< [4..4] AUD_CLK_DIV clock enable */ + uint32_t : 3; + __IOM uint32_t AUD_PCLK_DIV : 4; /*!< [11..8] APB-32A clock divider0x0: divided by 160x1: divided + * by 10x2: divided by 20x3: divided by 30x4: divided by 40x5: + * divided by 50x6: divided by 60x7: divided by 70x8: divided + * by 80x9: divided by 90xA: divided by 100xB: divided by + * 110xC: divided by 120xD: divided by 130xE: divided by 140xF: + * divided by 15 */ + uint32_t : 20; + } APU_AUD_CLK_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_CLK_REG; /*!< (@ 0x00000004) SRC_DIV clock control */ + + struct + { + __IOM uint32_t SRC_CLK_DIV : 4; /*!< [3..0] SRC_DIV clock divider0x0: divided by 160x1: divided by + * 10x2: divided by 20x3: divided by 30x4: divided by 40x5: + * divided by 50x6: divided by 60x7: divided by 70x8: divided + * by 80x9: divided by 90xA divided by 100xB: divided by 110xC: + * divided by 120xD: divided by 130xE: divided by 140xF: divided + * by 15 */ + __IOM uint32_t SRC_DMIC_CLK_EN : 1; /*!< [4..4] SRC DMIC clock enable0: Disabled1: Enabled */ + uint32_t : 2; + __IOM uint32_t SRC_CLK_EN : 1; /*!< [7..7] SRC clock enable0: Disabled1: Enabled */ + uint32_t : 24; + } APU_SRC_CLK_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t AUD_CLK_GATE_REG; /*!< (@ 0x0000000C) AUD_CLK_GATE control */ + + struct + { + uint32_t : 2; + __IOM uint32_t AUD_CLK_GATE_SEL : 1; /*!< [2..2] AUD_CLK_GATE enable selection0: Manual mode using AUD_CLK_GATE_EN1: + * APU START pulse triggered */ + __IM uint32_t AUD_CLK_GATE_STAT : 1; /*!< [3..3] AUD_CLK_GATE status0: AUD_CLK_GATE disabled1: AUD_CLK_GATE + * enabled */ + __IOM uint32_t AUD_CLK_GATE_OVR : 1; /*!< [4..4] AUD_CLK_GATE override0: Not override1: Override to 1 */ + __IOM uint32_t APU_RST : 1; /*!< [5..5] Centralized APU reset0: reset release1: reset active */ + uint32_t : 26; + } AUD_CLK_GATE_REG_b; + }; + + union + { + __IOM uint32_t APU_MCLK_CTRL_REG; /*!< (@ 0x00000010) MCLK DIV control */ + + struct + { + __IOM uint32_t MCLK_DIV : 7; /*!< [6..0] MCLK divider0: Divide by 1281: Divide by 1..127: Divide + * by 127 */ + __IOM uint32_t MCLK_EN : 1; /*!< [7..7] MCLK enable0: MCLK Disabled1: MCLK Enabled */ + __IOM uint32_t MCLK_SEL : 1; /*!< [8..8] MCLK source selection0: FPLL_CLK selected1: XTAL40M selected */ + __IOM uint32_t MCLK_INV : 1; /*!< [9..9] MCLK DIV output Inversion0: Not inversion1: Inversion */ + uint32_t : 22; + } APU_MCLK_CTRL_REG_b; + }; + + union + { + __IOM uint32_t APU_START_CTRL_REG; /*!< (@ 0x00000014) APU_START control */ + + struct + { + uint32_t : 8; + __IOM uint32_t APU_START : 1; /*!< [8..8] APU_START control0: Disable APU_START1: Enable APU_START */ + uint32_t : 23; + } APU_START_CTRL_REG_b; + }; +} CRG_APU_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ CRG_COM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRG_COM registers (CRG_COM) + */ + +typedef struct /*!< (@ 0x400C0200) CRG_COM Structure */ +{ + union + { + __IOM uint32_t PLL1_ARM_CTRL_REG; /*!< (@ 0x00000000) PLL Control register */ + + struct + { + __IOM uint32_t DPLL1_DIV_SEL : 6; /*!< [5..0] Loop divider settings?b'001111: divide 15b'010000: divide + * 16b'010001: divide 17b'010010: divide 18b'010011: divide + * 19b'010100: divide 20b'010101: divide 21b'010110: divide + * 22b'010111: divide 23b'011000: divide 24b'011001: divide + * 25b'011010: divide 26b'011011: divide 27b'011100: divide + * 28b'011101: divide 29b'011110: divide 30 */ + __IOM uint32_t DPLL1_VCO_SEL : 2; /*!< [7..6] Post divider settings?b'00: 1b'01: 1/2b'10: 1/4b'11: + * 1/8 */ + __IOM uint32_t DPLL1_EN : 1; /*!< [8..8] DPLL1 enable control0:disable1:enable, Active high */ + __IOM uint32_t DPLL1_SHORT_S : 2; /*!< [10..9] Lock detector cycle numberb'00: 1024b'01: 512b'10: 256b'11: + * 128 */ + __IOM uint32_t DPLL1_LF_RCTRL : 2; /*!< [12..11] DPLL1 Loop filter controlb'00: LF resistor max (minimum + * Loop BW)b11: LF resistor min (maximum Loop BW) */ + __IM uint32_t PLL_LOCK : 1; /*!< [13..13] PLL Lock Status */ + uint32_t : 18; + } PLL1_ARM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t XTAL40M_CTRL_REG; /*!< (@ 0x00000004) XTAL40M Control register */ + + struct + { + __IOM uint32_t XTAL40M_EN : 1; /*!< [0..0] 0: disable1: enable */ + __IOM uint32_t XTAL40M_RFEN : 1; /*!< [1..1] 0: disable1: enable */ + __IOM uint32_t XTAL40M_DPLL_EN : 1; /*!< [2..2] 0: disable1: enable */ + __IOM uint32_t XTAL40M_RFPLL_EN : 1; /*!< [3..3] 0: disable1: enable */ + __IOM uint32_t XTAL40M_FPLL_EN : 1; /*!< [4..4] 0: disable1: enable */ + __IOM uint32_t XTAL40M_TX_EN : 1; /*!< [5..5] 0: disable1: enable */ + __IOM uint32_t XTAL40M_ADCCLK_EN : 1; /*!< [6..6] 0: disable1: enable */ + uint32_t : 1; + __IOM uint32_t XTAL40_GAIN : 3; /*!< [10..8] XTAL core gain cotrol,After power on, need set 7 to + * 30: min7: max, (default code = 7) */ + uint32_t : 5; + __IOM uint32_t XTAL40M_CCTRL : 7; /*!< [22..16] 7bit ppm control, default 0 */ + __IM uint32_t XTAL40M_RDY : 1; /*!< [23..23] XTAL40M ready OK0: not OK1: Locked */ + uint32_t : 8; + } XTAL40M_CTRL_REG_b; + }; + + union + { + __IOM uint32_t MEMORY_CTRL_REG; /*!< (@ 0x00000008) LS/RME/RM register */ + + struct + { + __IOM uint32_t CPU_SRAM : 4; /*!< [3..0] main CPU SRAM,bit[3]; LS light sleepbit[2]: RME RM enablebit[1:0]: + * RM default 2'b11 (fastest) RM is toal 4bit but RM[3:2] + * is for test so set to '0' */ + __IOM uint32_t RET_MEM : 4; /*!< [7..4] Retention memory,refer to bit[3:0] description */ + __IOM uint32_t ROM : 4; /*!< [11..8] ROM,refer to bit[3:0] description */ + uint32_t : 4; + __IOM uint32_t PHY_MEM : 4; /*!< [19..16] PHY memory,refer to bit[3:0] description */ + __IOM uint32_t MAC_MEM : 4; /*!< [23..20] MAC memory,refer to bit[3:0] description */ + __IOM uint32_t SYS_CLK_MODE : 1; /*!< [24..24] sys_clk operating mode0: manual mode1: auto mode */ + uint32_t : 3; + __IOM uint32_t OTHER_MEM : 4; /*!< [31..28] Other memory,refer to bit[3:0] description */ + } MEMORY_CTRL_REG_b; + }; + + union + { + __IOM uint32_t EXT_INTB_CTRL_REG; /*!< (@ 0x0000000C) External interrupt control register */ + + struct + { + __IOM uint32_t INTR_POL : 1; /*!< [0..0] interrupt polarity0: low active1: high active */ + __IOM uint32_t INTR_MODE : 1; /*!< [1..1] interrupt mode0: Level mode1: Edge mode */ + __IOM uint32_t PULSE_DURATION : 6; /*!< [7..2] counter unit is clock HCLK_FR: pulse duration, increase + * 1 after reaching base_counter to 0xFF with clock HCLK_FR + * 0 is not permitted */ + uint32_t : 24; + } EXT_INTB_CTRL_REG_b; + }; + + union + { + __IOM uint32_t EXT_INTB_SET_REG; /*!< (@ 0x00000010) External interrupt set register */ + + struct + { + __IOM uint32_t INTR_SET : 1; /*!< [0..0] interrupt set */ + uint32_t : 31; + } EXT_INTB_SET_REG_b; + }; + + union + { + __IOM uint32_t NORMAL_TEST_CTRL_REG; /*!< (@ 0x00000014) Normal Test Control register */ + + struct + { + __IOM uint32_t PLL1 : 1; /*!< [0..0] PLL1 test mode */ + __IOM uint32_t FLASH : 1; /*!< [1..1] Flash test mode */ + uint32_t : 1; + __IOM uint32_t DEBUG_GPIO : 1; /*!< [3..3] Debug GPIO test mode */ + __IOM uint32_t EXT_RF : 1; /*!< [4..4] External RF test mode */ + __IOM uint32_t EXT_BB : 1; /*!< [5..5] External BB test mode */ + __IOM uint32_t ADC_DAC_LB : 1; /*!< [6..6] ADC via DAC loopback test mode */ + __IOM uint32_t AUXADC12B : 1; /*!< [7..7] AuxADC12B test mode */ + uint32_t : 1; + __IOM uint32_t IQ_ADC : 1; /*!< [9..9] IQ ADC test mode */ + __IOM uint32_t RTC : 1; /*!< [10..10] RTC test mode */ + __IOM uint32_t DEBUG_WIFI : 1; /*!< [11..11] Debug WiFi test mode */ + __IOM uint32_t IQ_SEL : 1; /*!< [12..12] IQ_sel control signal at IQ_ADC test mode */ + uint32_t : 19; + } NORMAL_TEST_CTRL_REG_b; + }; + + union + { + __IOM uint32_t POWER_MANAGE_REG; /*!< (@ 0x00000018) Power Manage register */ + + struct + { + uint32_t : 1; + __IOM uint32_t ISO_EN : 1; /*!< [1..1] RF I/F ISO cell enable :for RF block when enable set + * to '0' ,0: ISO (default)1: normal operation */ + __IOM uint32_t ISCO_EN : 1; /*!< [2..2] RF I/F ISCO cell enable 2 for Ready signal only for IQ + * ADC/DAC block */ + uint32_t : 29; + } POWER_MANAGE_REG_b; + }; + + union + { + __IOM uint32_t MON_RF_TEST_REG; /*!< (@ 0x0000001C) RF monitoring test register */ + + struct + { + __IOM uint32_t BB2RF_MUX_QN0 : 1; /*!< [0..0] BB2RF_MUX_QN0 */ + __IOM uint32_t BB2RF_MUX_QN1 : 1; /*!< [1..1] BB2RF_MUX_QN1 */ + __IOM uint32_t BB2RF_MUX_QP0 : 1; /*!< [2..2] BB2RF_MUX_QP0 */ + __IOM uint32_t BB2RF_MUX_QP1 : 1; /*!< [3..3] BB2RF_MUX_QP1 */ + __IOM uint32_t BB2RF_MUX_IN0 : 1; /*!< [4..4] BB2RF_MUX_IN0 */ + __IOM uint32_t BB2RF_MUX_IN1 : 1; /*!< [5..5] BB2RF_MUX_IN1 */ + __IOM uint32_t BB2RF_MUX_IP0 : 1; /*!< [6..6] BB2RF_MUX_IP0 */ + __IOM uint32_t BB2RF_MUX_IP1 : 1; /*!< [7..7] BB2RF_MUX_IP1 */ + __IOM uint32_t IQ2NDSW_SEL_QN : 1; /*!< [8..8] bb2ip3_iq2ndsw_sel_qpdior_ip123 : GPIO0~3 port connection0: + * aux ADC 1: ADC/DAC */ + __IOM uint32_t IQ2NDSW_SEL_QP : 1; /*!< [9..9] IQ2NDSW_SEL_QP */ + __IOM uint32_t IQ2NDSW_SEL_IN : 1; /*!< [10..10] IQ2NDSW_SEL_IN */ + __IOM uint32_t IQ2NDSW_SEL_IP : 1; /*!< [11..11] IQ2NDSW_SEL_IP */ + __IOM uint32_t IQ2NDSW_SEL_QN_EXT : 1; /*!< [12..12] bb2ip3_iq2ndsw_sel_qpdior_ip123 : GPIO0~3 port connection0: + * aux ADC 1: ADC/DAC */ + __IOM uint32_t IQ2NDSW_SEL_QP_EXT : 1; /*!< [13..13] IQ2NDSW_SEL_QP_EXT */ + __IOM uint32_t IQ2NDSW_SEL_IN_EXT : 1; /*!< [14..14] IQ2NDSW_SEL_IN_EXT */ + __IOM uint32_t IQ2NDSW_SEL_IP_EXT : 1; /*!< [15..15] IQ2NDSW_SEL_IP_EXT */ + __IOM uint32_t SEL_IQSEL_QN_SEN : 1; /*!< [16..16] SEL_IQSEL_QN_SEN */ + __IOM uint32_t SEL_IQSEL_QP_SEN : 1; /*!< [17..17] SEL_IQSEL_QP_SEN */ + __IOM uint32_t SEL_IQSEL_IN_SEN : 1; /*!< [18..18] SEL_IQSEL_IN_SEN */ + __IOM uint32_t SEL_IQSEL_IP_SEN : 1; /*!< [19..19] SEL_IQSEL_IP_SEN */ + __IOM uint32_t EN_IQSW_QN_EXTMODE : 1; /*!< [20..20] RX/TX IQ switch control1: output IF signal to external + * path */ + __IOM uint32_t EN_IQSW_QP_EXTMODE : 1; /*!< [21..21] RX/TX IQ switch control1: output IF signal to external + * path */ + __IOM uint32_t EN_IQSW_IN_EXTMODE : 1; /*!< [22..22] RX/TX IQ switch control1: output IF signal to external + * path */ + __IOM uint32_t EN_IQSW_IP_EXTMODE : 1; /*!< [23..23] RX/TX IQ switch control1: output IF signal to external + * path */ + uint32_t : 8; + } MON_RF_TEST_REG_b; + }; + + union + { + __IOM uint32_t IP1_BAND_GAP_REG; /*!< (@ 0x00000020) IP1 Band gap register */ + + struct + { + __IOM uint32_t LDO_MON_SEL : 3; /*!< [2..0] monitor select control at "IP1_LDO_TEST"0: GND,1: DAC_VDD2: + * SADC_AVDD3: SADC_DVDD4: FADC_AVDD5: FADC_DVDD6,7: don't + * use */ + uint32_t : 1; + __IOM uint32_t BG_VTRIM : 3; /*!< [6..4] Band gap output voltage trimming control0: min (default)7: + * max */ + uint32_t : 25; + } IP1_BAND_GAP_REG_b; + }; + + union + { + __IOM uint32_t IP4_POR_LDO_CTRL_REG; /*!< (@ 0x00000024) IP2 Band gap register */ + + struct + { + __IOM uint32_t IP4_POR_ADJVFR : 1; /*!< [0..0] Adjust VFR setting0: default */ + __IOM uint32_t IP4_POR_VDET_SEL : 1; /*!< [1..1] Detection power selection :0: detect 0.9V (default)1: + * detect 1.1V */ + uint32_t : 2; + __IOM uint32_t DIGTOP_LDO_CTRL : 3; /*!< [6..4] DIG_TOP_LDO output control0: 1.16V (Default), 1: 1.12V, + * 2: 1.07V, 3: 1.02V4: 0.98V, 5 :0.93V, 6: 0.88V, 7: 0.83V */ + uint32_t : 25; + } IP4_POR_LDO_CTRL_REG_b; + }; + + union + { + __IOM uint32_t IP2_BAND_GAP_REG; /*!< (@ 0x00000028) IP4 Por register */ + + struct + { + __IOM uint32_t IP4_VBG_TRIM : 3; /*!< [2..0] Band gap output voltage trimming control0: min (default)7: + * max */ + __IOM uint32_t IP2_POR_ADJVFR : 1; /*!< [3..3] Adjust VFR setting0: default */ + __IOM uint32_t IP2_POR_VDEL_SEL : 1; /*!< [4..4] Detection power selection0: detect 0.9V (default)1: detect + * 1.1V, */ + uint32_t : 27; + } IP2_BAND_GAP_REG_b; + }; + + union + { + __IOM uint32_t IP4_DCDC_DIG_REG; /*!< (@ 0x0000002C) IP4 DCDC dig register */ + + struct + { + __IOM uint32_t DCDC_DIG_TMF : 3; /*!< [2..0] Select the PWM frequency of the DCDC_ANA [TMF2_11V TMF1_11V + * TMF0_11V] LX_Frequency 000 : 1.9MHz, 001 : 2.7MHz, 010 + * : 3.4MHz, 011 : 4.1MHz, 100 : 4.7MHz, 101 : 5.2MHz (only + * for testing) 110 : 5.8MHz(only for testing), 111 : 6.3MHz + * (only for testing) */ + __IOM uint32_t DCDC_DIG_SUSPENDB : 1; /*!< [3..3] SUSPENDB_11V=0 and iload is less than 15mA, DCDC will + * enter to PFM mode.The PFM mode will have voltage ripple + * about 10mV */ + __IOM uint32_t DCDC_DIG_ADJ : 3; /*!< [6..4] Adjust the output voltage of the DCDC_ANA000 : 1.18V, + * 001 : 1.22V, 010 : 1.25V, 011 : 1.29V100 : 1.33V, 101 : + * 1.36V, 110 : 1.40V, 111 : 1.44V */ + __IOM uint32_t DCDC_DIG_CLIM_ENB : 1; /*!< [7..7] Current limit control pin.CLIM_ENB_12V =0: limit power + * current 500mA, CLIM_ENB_12V =1: limit power current 800mA */ + uint32_t : 24; + } IP4_DCDC_DIG_REG_b; + }; + + union + { + __IOM uint32_t IP4_DCDC_FEM_REG; /*!< (@ 0x00000030) DCDC FEM register */ + + struct + { + __IOM uint32_t DCDC_FEM_TMF : 3; /*!< [2..0] Select the PWM frequency of the DCDC_ANA000 : 1.94MHz, + * 001 : 2.77MHz, 010 : 3.5MHz,011 : 4.18MHz, 100 : 4.79MHz, + * 101 : 5.34MHz (only for testing)110 : 5.87MHz(only for + * testing), 111 : 6.37MHz (only for testing) */ + __IOM uint32_t DCDC_FEM_SUSPENDB : 1; /*!< [3..3] SUSPENDB_11V=0 and iload is less than 15mA, DCDC will + * enter to PFM mode.The PFM mode will have voltage ripple + * about 10mV */ + __IOM uint32_t DCDC_FEM_ADJ : 3; /*!< [6..4] Programmed output setting: D3095BA Version Voltage 000 + * : 1.1V, 001 : 1.15V, 010 : 1.2V, 011 : 1.25V 100 : 1.3V, + * 101 : 1.35V, 110 : 1.4V, 111 : 1.45V */ + __IOM uint32_t DCDC_FEM_CLIM_ENB : 1; /*!< [7..7] Current limit control pin.CLIM_ENB_12V =0: limit power + * current 500mA, CLIM_ENB_12V =1: limit power current 800mA */ + uint32_t : 24; + } IP4_DCDC_FEM_REG_b; + }; + + union + { + __IOM uint32_t LDO_CTRL_REG; /*!< (@ 0x00000034) LDO control register */ + + struct + { + __IOM uint32_t FLDO_VCTRL : 3; /*!< [2..0] Flash SDIO_LDO output control0: 1.7V1: 1.725V2: 1.75V3: + * 1.775V4: 1.8V (default)5: 1.00V6: 0.99V7: 0.97V */ + __IOM uint32_t IP2_BG_TRIM : 3; /*!< [5..3] Band gap output voltage trimming control0: min (default)7: + * max */ + uint32_t : 26; + } LDO_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DAC_10B_CFG_REG; /*!< (@ 0x00000038) DAC 10bit config register */ + + struct + { + __IOM uint32_t DAC_PD : 1; /*!< [0..0] Power Down Signal for DAC0: Normal1: Power Down (default) + * (IF PD is high, the DAC register code will be 0000000000) + * (IF PD is high, VOUTP_(I,Q) and VOUTN_(I,Q) will be pulled + * down) */ + __IOM uint32_t DAC_RESET : 1; /*!< [1..1] DAC Reset0: Normal1: Reset (default) (IF Reset=1,the + * DAC register code will be 0000000000) */ + __IOM uint32_t DAC_SUSPEND : 1; /*!< [2..2] SUSPEND0: Normal Mode1: Suspend Mode 2. pull down VOUTP_(I,Q) + * and VOUTN_(I,Q). */ + __IOM uint32_t DAC_PRBSEN : 1; /*!< [3..3] Pseudorandom binary sequence enable */ + __IOM uint32_t DAC_DRVSEL : 1; /*!< [4..4] Bias control bits for output buffer */ + uint32_t : 27; + } DAC_10B_CFG_REG_b; + }; + + union + { + __IOM uint32_t DAC_CTRL_REG; /*!< (@ 0x0000003C) DAC Control register */ + + struct + { + __IOM uint32_t DAC_EN : 1; /*!< [0..0] c_nco_dac_en :0: Disable1: Enable(Tone Generation) */ + __IOM uint32_t DAC_IN_SEL_I : 1; /*!< [1..1] c_nco_dac_in_sel_i :0: Cosine Wave1: Constant Value */ + __IOM uint32_t DAC_IN_SEL_Q : 1; /*!< [2..2] c_nco_dac_in_sel_q :0: Sine Wave1: Constant Value */ + uint32_t : 29; + } DAC_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DAC_GAIN_REG; /*!< (@ 0x00000040) DAC Gain register */ + + struct + { + __IOM uint32_t DAC_GAIN_I : 8; /*!< [7..0] test tone gain control (0 : 0%, 255 : 100%) */ + __IOM uint32_t DAC_GAIN_Q : 8; /*!< [15..8] test tone gain control (0 : 0%, 255 : 100%) */ + uint32_t : 16; + } DAC_GAIN_REG_b; + }; + + union + { + __IOM uint32_t DAC_FREQ_I_REG; /*!< (@ 0x00000044) DAC Frequency I register */ + + struct + { + __IOM uint32_t DAC_FREQ_I : 11; /*!< [10..0] nco accumulator value (value = [Ftone * 2^11] / fclock) */ + uint32_t : 21; + } DAC_FREQ_I_REG_b; + }; + + union + { + __IOM uint32_t DAC_FREQ_Q_REG; /*!< (@ 0x00000048) DAC Frequency Q register */ + + struct + { + __IOM uint32_t DAC_FREQ_Q : 11; /*!< [10..0] nco accumulator value (value = [Ftone * 2^11] / fclock) */ + uint32_t : 21; + } DAC_FREQ_Q_REG_b; + }; + + union + { + __IOM uint32_t FADC_CFG0_REG; /*!< (@ 0x0000004C) FADC 14b Config0 register */ + + struct + { + __IOM uint32_t FADC_PD : 1; /*!< [0..0] Power Down Signal for Dual-Channel. ADC0: Normal1: Power + * Down (default) */ + __IOM uint32_t FADC_SUSPEND : 1; /*!< [1..1] SUSPEND :0: Normal Mode (default)1: Suspend Mode (fast + * wake-up mode) */ + __IOM uint32_t FADC_RESET : 1; /*!< [2..2] ADC Reset :0: Normal1: Reset (default) */ + uint32_t : 29; + } FADC_CFG0_REG_b; + }; + + union + { + __IOM uint32_t FADC_CFG1_REG; /*!< (@ 0x00000050) FADC 14b Config1 register */ + + struct + { + __IOM uint32_t FADC_ASYNCDLY : 3; /*!< [2..0] Async-clock delay */ + uint32_t : 1; + __IOM uint32_t FADC_MCLKDELS : 3; /*!< [6..4] Main clock delay (sampling time period) */ + uint32_t : 1; + __IOM uint32_t FADC_COMPBIAS : 2; /*!< [9..8] Comparator Bias */ + uint32_t : 2; + __IOM uint32_t FADC_ADCBIAS : 4; /*!< [15..12] It sets the bias current of the IQADC reference. It + * consists of 2 branches, one for each I and Q. The current + * for each branch current is set as follows.0: N.A, 1: 0.615mA, + * 2: 1.230mA, 3:1.845mA, 4:2.460mA5:3.975mA, 6:3.690mA, 7: + * 4.305mA, 8:4.920mA, 9:5.535mA10:6.15mA, 11:6.765mA, 12:7.380mA, + * 13:7.995mA, 14:8.610mA, 15:9.225mA */ + __IOM uint32_t FADC_WKUPSUSP : 4; /*!< [19..16] Wake-up time (SUSPEND mode) */ + __IOM uint32_t FADC_WKUPPD : 4; /*!< [23..20] Wake-up time (PD mode) */ + __IOM uint32_t FADC_VCM_CTRL : 3; /*!< [26..24] RDAC common mode voltare : default 550mV (520mV~580mV) */ + uint32_t : 5; + } FADC_CFG1_REG_b; + }; + + union + { + __IOM uint32_t FADC_CAL1_REG; /*!< (@ 0x00000054) FADC 14b Calibration1 register */ + + struct + { + __IOM uint32_t C_DAC_GAIN : 8; /*!< [7..0] internal DAC input gain value = output*c_dac_gain / 256 + * average value is always middle(2048) */ + __IOM uint32_t C_NCO_FREQ : 13; /*!< [20..8] internal DAC input data sine frequency. */ + uint32_t : 3; + __IOM uint32_t C_DAC_CLK_FREQ : 3; /*!< [26..24] internal DAC input data frequency.0: 1MHz (main clock + * 1/40)1: 2MHz (1/20)2: 4MHz (1/10)3: 6.7MHz (1/6)4: 8MHz + * (1/5)5: 10MHz (1/4)6: 13.3MHz (1/3)7 : 20MHz (1/2) */ + __IOM uint32_t C_WEIGHT_WR : 1; /*!< [27..27] Initial with calibrated weight value (1 clock pulse)If + * c_weight_wr is 1, write calibrated weight to register */ + __IOM uint32_t C_OUT_MUTE : 1; /*!< [28..28] output data force to 0 ( for current test)0: o_dout + * is normal data1: o_dout is 0. */ + __IOM uint32_t C_CAL_START : 1; /*!< [29..29] calibration process start (more than 1 clock pulse) */ + __IOM uint32_t C_LVL_POLAR : 1; /*!< [30..30] input perturbation signal polarity0: ana_pert = 1 is + * -delta, ana_pert = 0 is +delta1: ana_pert = 1 is +delta, + * ana_pert = 0 is -delta */ + __IOM uint32_t C_ENABLE : 1; /*!< [31..31] digital logic enable If enable is 0, o_dout is i_ana_din[14:1] + * (each channel) If enable is 1, o_dout is weighted sum of + * i_ana_din */ + } FADC_CAL1_REG_b; + }; + + union + { + __IOM uint32_t FADC_CAL2_REG; /*!< (@ 0x00000058) FADC 14b Calibration2 register */ + + struct + { + __IOM uint32_t CND_ERROR_TH : 8; /*!< [7..0] calibration finish threshold value */ + __IOM uint32_t CND_CNT : 2; /*!< [9..8] calibration finish count :0: 200001: 300002: 500003: + * 1000000 */ + uint32_t : 2; + __IOM uint32_t CND_DONE : 4; /*!< [15..12] calibratio finish condition 000 : max error threshold + * 010 : calibration count 100 : avg error threshold */ + __IOM uint32_t SCALE_ERROR : 3; /*!< [18..16] monitoring error value scaling 0 : 2^-7 1 : 2^-8 2 + * : 2^-9 3 : 2^-10 4 : 2^-11 5 : 2^-12 6 : 2^-13 7 : 2^-14 */ + uint32_t : 1; + __IOM uint32_t SCALE_DELTA : 3; /*!< [22..20] monitoring delta value scaling 0 : 2^-5 1 : 2^-6 2 + * : 2^-7 3 : 2^-8 4 : 2^-9 5 : 2^-10 6 : 2^-11 7 : 2^-12 */ + uint32_t : 1; + __IOM uint32_t STEP_ERROR : 3; /*!< [26..24] error value update step size 0 : 2^-4 1 : 2^-5 2 : + * 2^-6 3 : 2^-7 4 : 2^-8 5 : 2^-9 6 : 2^-10 7 : 2^-11 */ + uint32_t : 1; + __IOM uint32_t STEP_DELTA : 3; /*!< [30..28] delta value update step size 0 : 2^-8 1 : 2^-9 2 : + * 2^-10 3 : 2^-11 4 : 2^-12 5 : 2^-13 6 : 2^-14 7 : 2^-15 */ + uint32_t : 1; + } FADC_CAL2_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FADC_CAL_DONE_I_REG; /*!< (@ 0x00000060) FADC 14b Calibration I done register */ + + struct + { + __IM uint32_t CAL_CNT_I : 16; /*!< [15..0] cal_cnt_i value after calibration done */ + __IM uint32_t CAL_DONE_Q : 1; /*!< [16..16] CAL_DONE_Q */ + __IM uint32_t CAL_DONE_I : 1; /*!< [17..17] CAL_DONE_I */ + uint32_t : 14; + } FADC_CAL_DONE_I_REG_b; + }; + + union + { + __IOM uint32_t FADC_CAL_DONE_Q_REG; /*!< (@ 0x00000064) FADC 14b Calibration Q done register */ + + struct + { + __IM uint32_t CAL_CNT_Q : 16; /*!< [15..0] cal_cnt_q value after calibration done */ + __IM uint32_t CAL_DONE_Q : 1; /*!< [16..16] CAL_DONE_Q */ + uint32_t : 15; + } FADC_CAL_DONE_Q_REG_b; + }; + + union + { + __IOM uint32_t FADC_DOUT_DELTA_REG; /*!< (@ 0x00000068) FADC 14b delta register */ + + struct + { + __IM uint32_t DELTA_Q : 16; /*!< [15..0] delta_q value */ + __IM uint32_t DELTA_I : 16; /*!< [31..16] delta _i value */ + } FADC_DOUT_DELTA_REG_b; + }; + + union + { + __IOM uint32_t FADC_DOUT_ERROR_REG; /*!< (@ 0x0000006C) FADC 14b error register */ + + struct + { + __IM uint32_t ERROR_Q : 8; /*!< [7..0] error_q value */ + __IM uint32_t ERROR_I : 8; /*!< [15..8] error_i value */ + uint32_t : 16; + } FADC_DOUT_ERROR_REG_b; + }; + + union + { + __IOM uint32_t XTAL32K_CTRL_REG; /*!< (@ 0x00000070) XTAL32K Control register */ + + struct + { + __IOM uint32_t XTAL32K_ENABLE : 1; /*!< [0..0] nco accumulator value (value = [Ftone * 2^11] / fclock) */ + uint32_t : 31; + } XTAL32K_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TEST_CFG_REG; /*!< (@ 0x00000074) Test Config register */ + + struct + { + __IOM uint32_t SEL_TST1_MUX : 4; /*!< [3..0] Async-clock delay */ + __IOM uint32_t SEL_TST2_MUX : 4; /*!< [7..4] reserved */ + __IOM uint32_t TST1_GPADC_EN : 1; /*!< [8..8] Main clock delay (sampling time period) */ + __IOM uint32_t TST2_GPADC_EN : 1; /*!< [9..9] reserved */ + __IOM uint32_t TST1_GPIO_EN : 1; /*!< [10..10] Comparator Bias */ + __IOM uint32_t TST2_GPIO_EN : 1; /*!< [11..11] reserved */ + __IOM uint32_t HPI_BURNIN_EN : 1; /*!< [12..12] ADC Bias */ + __IOM uint32_t TX_HPI_BURNIN_EN : 1; /*!< [13..13] Wake-up time (SUSPEND mode) */ + __IOM uint32_t TST_GPIO0_DIO2_EN : 1; /*!< [14..14] need to add description */ + __IOM uint32_t TST_GPIO1_DIO2_EN : 1; /*!< [15..15] need to add description */ + __IOM uint32_t CTRL_TX_ATTEN : 6; /*!< [21..16] Wake-up time (PD mode) */ + uint32_t : 10; + } TEST_CFG_REG_b; + }; + + union + { + __IOM uint32_t PAD_LATCH_EN_REG; /*!< (@ 0x00000078) PAD Latch Enable Control register */ + + struct + { + __IOM uint32_t SWD_LATCH_EN : 2; /*!< [1..0] Port SWD Pad latch enalbe, bit field is match SWD_[1:00]1: + * enable0: disable */ + __IOM uint32_t P0_LATCH_EN : 14; /*!< [15..2] Port P0 Pad latch enalbe, bit field is match P0_[13:00]1: + * enable0: disable */ + __IOM uint32_t P1_LATCH_EN : 16; /*!< [31..16] Port P1 Pad latch enalbe, bit field is match P1_[15:00]1: + * enable0: disable */ + } PAD_LATCH_EN_REG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PSRAM_DEBUG_REG; /*!< (@ 0x00000080) PSRAM Debug register */ + + struct + { + __IM uint32_t LATENCY_CNT : 5; /*!< [4..0] Latency count */ + uint32_t : 3; + __IM uint32_t PSRAM_STS_MON : 5; /*!< [12..8] PSRAM status monitoring */ + uint32_t : 19; + } PSRAM_DEBUG_REG_b; + }; +} CRG_COM_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ CRG_PER ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRG_PER registers (CRG_PER) + */ + +typedef struct /*!< (@ 0x40090400) CRG_PER Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLK_COM_REG; /*!< (@ 0x00000004) Peripheral divider register */ + + struct + { + __IOM uint32_t SPI_ENABLE : 1; /*!< [0..0] Enables the clock */ + uint32_t : 1; + __IOM uint32_t SPI2_ENABLE : 1; /*!< [2..2] Enables the clock */ + uint32_t : 1; + __IOM uint32_t I2C_ENABLE : 1; /*!< [4..4] Enables the clock */ + __IOM uint32_t I2C_CLK_SEL : 1; /*!< [5..5] Selects the clock source1 : DIVC clock0 : DIVN clock */ + __IOM uint32_t I2C2_ENABLE : 1; /*!< [6..6] Enables the clock */ + __IOM uint32_t I2C2_CLK_SEL : 1; /*!< [7..7] Selects the clock source1 : DIVC clock0 : DIVN clock */ + __IOM uint32_t AUXADC_ENABLE : 1; /*!< [8..8] Enables the clock */ + __IOM uint32_t UART_ENABLE : 1; /*!< [9..9] Enables the clock */ + __IOM uint32_t UART2_ENABLE : 1; /*!< [10..10] Enables the clock */ + __IOM uint32_t UART3_ENABLE : 1; /*!< [11..11] Enables the clock */ + __IOM uint32_t SDIO_ENABLE : 1; /*!< [12..12] Enables the clock */ + __IOM uint32_t SDEMMC_ENABLE : 1; /*!< [13..13] Enables the clock */ + uint32_t : 18; + } CLK_COM_REG_b; + }; + + union + { + __IOM uint32_t SET_CLK_COM_REG; /*!< (@ 0x00000008) Peripheral divider register SET register. Reads + * back 0x0000 */ + + struct + { + __IOM uint32_t SPI_ENABLE : 1; /*!< [0..0] Enables the clock */ + uint32_t : 1; + __IOM uint32_t SPI2_ENABLE : 1; /*!< [2..2] Enables the clock */ + uint32_t : 1; + __IOM uint32_t I2C_ENABLE : 1; /*!< [4..4] Enables the clock */ + __IOM uint32_t I2C_CLK_SEL : 1; /*!< [5..5] Selects the clock source1 : DIVC clock0 : DIVN clock */ + __IOM uint32_t I2C2_ENABLE : 1; /*!< [6..6] Enables the clock */ + __IOM uint32_t I2C2_CLK_SEL : 1; /*!< [7..7] Selects the clock source1 : DIVC clock0 : DIVN clock */ + __IOM uint32_t AUXADC_ENABLE : 1; /*!< [8..8] Enables the clock */ + __IOM uint32_t UART_ENABLE : 1; /*!< [9..9] Enables the clock */ + __IOM uint32_t UART2_ENABLE : 1; /*!< [10..10] Enables the clock */ + __IOM uint32_t UART3_ENABLE : 1; /*!< [11..11] Enables the clock */ + __IOM uint32_t SDIO_ENABLE : 1; /*!< [12..12] Enables the clock */ + __IOM uint32_t SDEMMC_ENABLE : 1; /*!< [13..13] Enables the clock */ + uint32_t : 18; + } SET_CLK_COM_REG_b; + }; + + union + { + __IOM uint32_t RESET_CLK_COM_REG; /*!< (@ 0x0000000C) Peripheral divider register RESET register. Reads + * back 0x0000 */ + + struct + { + __IOM uint32_t SPI_ENABLE : 1; /*!< [0..0] Enables the clock */ + uint32_t : 1; + __IOM uint32_t SPI2_ENABLE : 1; /*!< [2..2] Enables the clock */ + uint32_t : 1; + __IOM uint32_t I2C_ENABLE : 1; /*!< [4..4] Enables the clock */ + __IOM uint32_t I2C_CLK_SEL : 1; /*!< [5..5] Selects the clock source1 = DIVC clock0 = DIVN clock */ + __IOM uint32_t I2C2_ENABLE : 1; /*!< [6..6] Enables the clock */ + __IOM uint32_t I2C2_CLK_SEL : 1; /*!< [7..7] Selects the clock source1 = DIVC clock0 = DIVN clock */ + __IOM uint32_t AUXADC_ENABLE : 1; /*!< [8..8] Enables the clock */ + __IOM uint32_t UART_ENABLE : 1; /*!< [9..9] Enables the clock */ + __IOM uint32_t UART2_ENABLE : 1; /*!< [10..10] Enables the clock */ + __IOM uint32_t UART3_ENABLE : 1; /*!< [11..11] Enables the clock */ + __IOM uint32_t SDIO_ENABLE : 1; /*!< [12..12] Enables the clock */ + __IOM uint32_t SDEMMC_ENABLE : 1; /*!< [13..13] Enables the clock */ + uint32_t : 18; + } RESET_CLK_COM_REG_b; + }; +} CRG_PER_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ CRG_SYS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRG_SYS registers (CRG_SYS) + */ + +typedef struct /*!< (@ 0x40070500) CRG_SYS Structure */ +{ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t MEM_CLK_CTRL_REG; /*!< (@ 0x00000020) MEM_CLK_CTRL_REG */ + + struct + { + uint32_t : 4; + __IOM uint32_t CACHERAM_CLK_OFF : 1; /*!< [4..4] CACHERAM_CLK_OFF */ + __IOM uint32_t CACHERAM_CLK_DCG : 1; /*!< [5..5] CACHERAM_CLK_DCG */ + uint32_t : 26; + } MEM_CLK_CTRL_REG_b; + }; + + union + { + __IOM uint32_t HPI_CLK_CTRL_REG; /*!< (@ 0x00000024) HPI_CLK_CTRL_REG */ + + struct + { + __IOM uint32_t HPI_CLK_OFF : 1; /*!< [0..0] HPI_CLK_OFF */ + __IOM uint32_t HPI_CLK_DCG : 1; /*!< [1..1] HPI_CLK_DCG */ + uint32_t : 30; + } HPI_CLK_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CRYPTO_RAM_CTRL_REG; /*!< (@ 0x00000034) CRYPTO_RAM_CTRL_REG */ + + struct + { + __IOM uint32_t CRYPTORAM_MA_SAWL : 1; /*!< [0..0] CRYPTORAM_MA_SAWL */ + __IOM uint32_t CRYPTORAM_MA_WL : 1; /*!< [1..1] CRYPTORAM_MA_WL */ + __IOM uint32_t CRYPTORAM_MA_WRAS : 1; /*!< [2..2] CRYPTORAM_MA_WRAS */ + __IOM uint32_t CRYPTORAM_MA_WRASD : 1; /*!< [3..3] CRYPTORAM_MA_WRASD */ + uint32_t : 28; + } CRYPTO_RAM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CACHE_RAM_CTRL_REG; /*!< (@ 0x00000038) CACHE_RAM_CTRL_REG */ + + struct + { + __IOM uint32_t CACHERAM_MA_SAWL : 2; /*!< [1..0] CACHERAM_MA_SAWL */ + __IOM uint32_t CACHERAM_MA_WL : 2; /*!< [3..2] CACHERAM_MA_WL */ + __IOM uint32_t CACHERAM_MA_WRAS : 2; /*!< [5..4] CACHERAM_MA_WRAS */ + __IOM uint32_t CACHERAM_MA_WRASD : 1; /*!< [6..6] CACHERAM_MA_WRASD */ + uint32_t : 25; + } CACHE_RAM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_RAM_CTRL_REG; /*!< (@ 0x0000003C) DCACHE_RAM_CTRL_REG */ + + struct + { + __IOM uint32_t DCACHERAM_MA_SAWL : 1; /*!< [0..0] DCACHERAM_MA_SAWL */ + __IOM uint32_t DCACHERAM_MA_WL : 1; /*!< [1..1] DCACHERAM_MA_WL */ + __IOM uint32_t DCACHERAM_MA_WRAS : 1; /*!< [2..2] DCACHERAM_MA_WRAS */ + __IOM uint32_t DCACHERAM_MA_WRASD : 1; /*!< [3..3] DCACHERAM_MA_WRASD */ + uint32_t : 28; + } DCACHE_RAM_CTRL_REG_b; + }; +} CRG_SYS_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ CRG_TOP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRG_TOP registers (CRG_TOP) + */ + +typedef struct /*!< (@ 0x400C0000) CRG_TOP Structure */ +{ + union + { + __IOM uint32_t CLK_AMBA_REG; /*!< (@ 0x00000000) HCLK, PCLK, divider and clock gates */ + + struct + { + __IOM uint32_t HCLK_DIV : 3; /*!< [2..0] AHB interface and microprocessor clock. Source clock + * divided by:000 = divide hclk by 1001 = divide hclk by 2010 + * = divide hclk by 4011 = divide hclk by 8100 = divide hclk + * by 16101 = divide hclk by 32110 = divide hclk by 64111 + * = divide hclk by 128 */ + uint32_t : 3; + __IOM uint32_t PSK_CLK_ENABLE : 1; /*!< [6..6] Clock enable for AES crypto block */ + __IOM uint32_t TDES_ENABLE : 1; /*!< [7..7] Clock enable for TDES block */ + __IOM uint32_t OQSPIF_DIV : 2; /*!< [9..8] OQSPI divider00 = divide by 101 = divide by 210 = divide + * by 411 = divide by 8 */ + __IOM uint32_t OQSPIF_ENABLE : 1; /*!< [10..10] Clock enable for OQSPI controller */ + __IOM uint32_t QSPI2_DIV : 2; /*!< [12..11] QSPI divider00 = divide by 101 = divide by 210 = divide + * by 411 = divide by 8 */ + __IOM uint32_t QSPI2_ENABLE : 1; /*!< [13..13] Clock enable for QSPI RAM controller */ + __IOM uint32_t QSPI2_PULLUP_ENABLE : 1; /*!< [14..14] Pull-up enable when OQSPIF_D* pads are not output.0: + * disable1: The pads are pull-up (to VDDIO_18) */ + __IOM uint32_t QSPI2_PULLDN_ENABLE : 1; /*!< [15..15] Pull-down enable when OQSPIF_D* pads are not output.0: + * disable1: The pads are pull-down (to VSS) */ + __IOM uint32_t OQSPI_GPIO_MODE : 1; /*!< [16..16] If this bit is set, the upper 4 pins of the OQSPIF + * controller can be used as GPIO, P1_00 to P1_03.In this + * mode, the OQSPIF controller should be restricted to QUAD + * mode or less.Note: the supply remains V18F, so if the supply + * is off, the pads become floating. */ + __IOM uint32_t OQSPI_PULLUP_ENABLE : 1; /*!< [17..17] Pull-up enable when OQSPIF_D* pads are not output.0: + * disable1: The pads are pull-up (to VDDIO_18) */ + __IOM uint32_t OQSPI_PULLDN_ENABLE : 1; /*!< [18..18] Pull-down enable when OQSPIF_D* pads are not output.0: + * disable1: The pads are pull-down (to VSS) */ + __IOM uint32_t SYS_MEM_ENABLE : 1; /*!< [19..19] Clock enable for System Memory */ + __IOM uint32_t GEN_DMA_ENABLE : 1; /*!< [20..20] Clock enable for Gen DMA */ + __IOM uint32_t CC312_CLK_ENABLE : 1; /*!< [21..21] Clock enable for CC312 */ + __IOM uint32_t PHY_CLK_ENABLE : 1; /*!< [22..22] Clock enable for PHY Top */ + __IOM uint32_t PERI_CLK_ENABLE : 1; /*!< [23..23] Clock enable for Peripheral */ + __IOM uint32_t TIMER_CLK_ENABLE : 1; /*!< [24..24] Clock enable for Timer */ + __IOM uint32_t AUX_CLK_ENABLE : 1; /*!< [25..25] Clock enable for AUX */ + __IOM uint32_t SPI_CLK_ENABLE : 1; /*!< [26..26] Clock enable for SPI */ + __IOM uint32_t KDMA_CLK_ENABLE : 1; /*!< [27..27] Clock enable for kDMA */ + __IM uint32_t HCLK_DIV_SYNC : 3; /*!< [30..28] Actual applied AHB interface and microprocessor clock + * which synchronized to systick 1us */ + uint32_t : 1; + } CLK_AMBA_REG_b; + }; + + union + { + __IOM uint32_t SET_FREEZE_REG; /*!< (@ 0x00000004) Controls freezing of various timers/counters + * (incl. DMA and USB). */ + + struct + { + __IOM uint32_t FRZ_WKUPTIM : 1; /*!< [0..0] If '1', the Wake Up Timer is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM : 1; /*!< [1..1] If '1', the SW Timer is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM2 : 1; /*!< [2..2] If '1', the SW Timer2 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM3 : 1; /*!< [3..3] If '1', the SW Timer3 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM4 : 1; /*!< [4..4] If '1', the SW Timer4 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM5 : 1; /*!< [5..5] If '1', the SW Timer5 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM6 : 1; /*!< [6..6] If '1', the SW Timer6 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM7 : 1; /*!< [7..7] If '1', the SW Timer7 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM8 : 1; /*!< [8..8] If '1', the SW Timer8 is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_SYS_WDOG : 1; /*!< [9..9] If '1', the SYS SW Watchdog Timer is frozen, '0' is discarded. + * WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze + * function. */ + uint32_t : 1; + __IOM uint32_t FRZ_DMA : 1; /*!< [11..11] If '1', the DMA is frozen, '0' is discarded. */ + __IOM uint32_t FRZ_KDMA : 1; /*!< [12..12] If '1', the kDMA is frozen, '0' is discarded. */ + uint32_t : 19; + } SET_FREEZE_REG_b; + }; + + union + { + __IOM uint32_t RESET_FREEZE_REG; /*!< (@ 0x00000008) Controls unfreezing of various timers/counters + * (incl. DMA and USB). */ + + struct + { + __IOM uint32_t FRZ_WKUPTIM : 1; /*!< [0..0] If '1', the Wake Up Timer continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM : 1; /*!< [1..1] If '1', the SW Timer continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM2 : 1; /*!< [2..2] If '1', the SW Timer2 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM3 : 1; /*!< [3..3] If '1', the SW Timer3 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM4 : 1; /*!< [4..4] If '1', the SW Timer4 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM5 : 1; /*!< [5..5] If '1', the SW Timer5 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM6 : 1; /*!< [6..6] If '1', the SW Timer6 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM7 : 1; /*!< [7..7] If '1', the SW Timer7 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SWTIM8 : 1; /*!< [8..8] If '1', the SW Timer8 continues, '0' is discarded. */ + __IOM uint32_t FRZ_SYS_WDOG : 1; /*!< [9..9] If '1', the SYS SW Watchdog Timer continues, '0' is discarded. */ + uint32_t : 1; + __IOM uint32_t FRZ_DMA : 1; /*!< [11..11] If '1', the DMA continues, '0' is discarded. */ + __IOM uint32_t FRZ_KDMA : 1; /*!< [12..12] If '1', the kDMA continues, '0' is discarded. */ + uint32_t : 19; + } RESET_FREEZE_REG_b; + }; + + union + { + __IOM uint32_t RST_CTRL_REG; /*!< (@ 0x0000000C) Reset control register */ + + struct + { + __IOM uint32_t SYS_CACHE_FLUSH_WITH_SW_RESET : 1; /*!< [0..0] 0: Flush the System Cache memory only at HW reset.1: + * Flush the System Cache memory also at SW reset. */ + __IOM uint32_t PERI_RESET_REQ : 1; /*!< [1..1] PERI block reset request */ + __IOM uint32_t AUD_RESET_REQ : 1; /*!< [2..2] audio block reset request */ + __IOM uint32_t TIMER_RESET_REQ : 1; /*!< [3..3] timer block reset request */ + __IOM uint32_t MEM_RESET_REQ : 1; /*!< [4..4] memory control block reset request */ + uint32_t : 27; + } RST_CTRL_REG_b; + }; + + union + { + __IOM uint32_t RADIO_RESET_REG; /*!< (@ 0x00000010) Radio Reset request register */ + + struct + { + __IOM uint32_t PHYCORE_SW_RESET_REQ : 1; /*!< [0..0] Manual reset for PHY by Host (active Low)0 : reset1 : + * normalfor PHY core block */ + __IOM uint32_t PHYREG_HW_RESET_REQ : 1; /*!< [1..1] refer bit[0]for PHY REG block */ + __IOM uint32_t PHYCORE_HW_RESET_REQ : 1; /*!< [2..2] refer to bit[0]for PHY Core block */ + __IOM uint32_t MPIF_HW_RESET_REQ : 1; /*!< [3..3] refer to bit[0]for MPIF block */ + __IOM uint32_t WT_HW_RESET_REQ : 1; /*!< [4..4] refer to bit[0]for WTCLK block */ + __IOM uint32_t MACCORE_HW_RESET_REQ : 1; /*!< [5..5] refer to bit[0]for MAC core block */ + __IOM uint32_t MACPI_HW_RESET_REQ : 1; /*!< [6..6] refer to bit[0]for MAC Pi block */ + __IOM uint32_t SYSRST_RESET_REQ : 1; /*!< [7..7] refer to bit[0]for Sysrst of PHY block */ + uint32_t : 24; + } RADIO_RESET_REG_b; + }; + + union + { + __IOM uint32_t CLK_CTRL_REG; /*!< (@ 0x00000014) Clock control register */ + + struct + { + __IOM uint32_t SYS_CLK_SEL : 2; /*!< [1..0] SYS_CLK source selection1: XTAL40M2: LP CLK (32Khz)3: + * SYS-PLL */ + __IOM uint32_t PLL_CLK_SEL : 3; /*!< [4..2] PLL clock divider setting. PLL source = 480Mhz0: Do not + * set this value : descoped.1: Do not set this value : descoped.2: + * set to SYS_CLK=160Mhz3: set to SYS_CLK=137.14Mhz4: set + * to SYS_CLK=106Mhz */ + __IOM uint32_t PLL_SPI_CLK_SEL : 2; /*!< [6..5] to generate SPI_CLK for SPI block0: set to SPI_CLK=120Mhz1: + * set to SPI_CLK=96Mhz2: set to SPI_CLK=80Mhz3: set to SPI_CLK=53MhzNote + * : this clock is for SPI block itself, There is another + * divider block in SPI block. */ + __IOM uint32_t PLL_AUX_ENABLE : 1; /*!< [7..7] enable signal for Aux clock using PLL clock source.when + * '1', Aux clock counter starts to work. */ + __IOM uint32_t PLL_SPI_ENABLE : 1; /*!< [8..8] enable signal for SPI clock using PLL clock source.when + * '1', SPI clock counter starts to work. */ + __IOM uint32_t PLL_PERI_ENABLE : 1; /*!< [9..9] enable signal for peripheral clock using PLL clock source.when + * '1', peri clock counter starts to work. */ + __IOM uint32_t PLL_CPU_ENABLE : 1; /*!< [10..10] enable signal for CPU main clock using PLL clock source.when + * '1', CPU clock counter starts to work.Note: before set + * this bit, set the PLL_CLK_SEL bits in advance. */ + __IM uint32_t RUNNING_AT_LP_CLK : 1; /*!< [11..11] Indicates that either the LP_CLK is being used as clock */ + __IM uint32_t RUNNING_AT_XTAL40M : 1; /*!< [12..12] Indicates that the XTAL40M clock is used as clock */ + __IM uint32_t RUNNING_AT_PLL : 1; /*!< [13..13] Indicates that the PLL clock is used as clock, and + * may not be switched off */ + uint32_t : 18; + } CLK_CTRL_REG_b; + }; + + union + { + __IOM uint32_t SYS_CTRL_REG; /*!< (@ 0x00000018) System Control register */ + + struct + { + __IOM uint32_t REMAP_ADR0 : 3; /*!< [2..0] Controls which memory is located at address 0x0000 for + * execution.0x0: ROM0x2: QSPI FLASH cached (see also the + * CACHE_FLASH_REG.FLASH_REGION.* descriptions)Note 1: When + * REMAP_ADR0=0x2, address 0x0 is mapped to FLASH_REGION_BASE + + FLASH_REGION_OFFSET<<2. Note 2: When REMAP_ADR0=0x2, + + the CPU can only access the Flash region [FLASH_REGION_BASE + + FLASH_REGION_OFFSET<<2, FLASH_REGION_SIZE] from the 0x09000000 + + address range. The complete Flash can be accessed via the + + 0x29000000 address range */ + __IOM uint32_t REMAP_INTVECT : 1; /*!< [3..3] 0: Normal operation1: If ARM-M33 is in address range + * 0 to 0x1FF then the address is remapped to SYS-RAM 0x080A.FE00 + * to 0x080A.FFFF. This allows to put the interrupt vector + * table to be placed in RAM while executing from QSPI. */ + __IOM uint32_t DEBUGGER_ENABLE : 1; /*!< [4..4] M33 Debug Access Port enable. This bit can be set by + * the booter according to the OTP header. */ + __IOM uint32_t DRA_OFF : 1; /*!< [5..5] DRA_OFF */ + __IOM uint32_t CACHERAM_MUX : 1; /*!< [6..6] Controls accessibility of Cache RAM:0: the cache controller + * is bypassed, the cacheRAM is visible in the memory space1: + * the cache controller is enabled, the cacheRAM is not visible + * anymore in the memory space */ + __OM uint32_t SW_RESET : 1; /*!< [7..7] Writing a '1' to this bit will generate a SW_RESET. */ + uint32_t : 24; + } SYS_CTRL_REG_b; + }; + + union + { + __IOM uint32_t RETAIN_MEM_CTRL_REG; /*!< (@ 0x0000001C) Memory Control register */ + + struct + { + __IOM uint32_t SYS_RAM1_PWR_CTRL : 2; /*!< [1..0] Power state control of the individual RAMs. May only + * be changed when the memory is not accessed.When SYS_IS_UP:00: + * Normal operation01: Normal operation10: Retained (no access + * possible)11: Off (memory content corrupted)When SYS_IS_DOWN:00: + * Retained01: Off (memory content corrupted)10: Retained11: + * Off (memory content corrupted) */ + __IOM uint32_t SYS_RAM2_PWR_CTRL : 2; /*!< [3..2] SYS_RAM2 Control : refer to SYS_RAM1_PWR_CTRL */ + __IOM uint32_t SYS_RAM3_PWR_CTRL : 2; /*!< [5..4] SYS_RAM3 Control : refer to SYS_RAM1_PWR_CTRL */ + __IOM uint32_t CACHE_RETAIN : 1; /*!< [6..6] cache memory retain1 : retain0 : off */ + __IOM uint32_t DCACHE_RETAIN : 1; /*!< [7..7] dcache memory retain1 : retain0 : off */ + uint32_t : 24; + } RETAIN_MEM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t AUX_CLK_DIV_REG; /*!< (@ 0x00000020) AUX clock divider register */ + + struct + { + __IOM uint32_t CLK_DIV_AUXA : 10; /*!< [9..0] Last divider parameter to generate AuxADC input clock0 + * : 1/11 : 1/22 : 1/3n : 1/(n+1) */ + uint32_t : 22; + } AUX_CLK_DIV_REG_b; + }; + + union + { + __IOM uint32_t RESET_STAT_REG; /*!< (@ 0x00000024) Reset status register */ + + struct + { + __IOM uint32_t PORESET_STAT : 1; /*!< [0..0] Indicates that a PowerOn Reset has happened.All bitfields + * of RESET_STAT_REG should be read (in order to check the + * source of reset) and then cleared to '0', allowing thus + * the HW to automatically set to '1' the proper bitfields + * during the next reset event. */ + __IOM uint32_t HWRESET_STAT : 1; /*!< [1..1] Indicates that a HW Reset has happened */ + __IOM uint32_t SWRESET_STAT : 1; /*!< [2..2] Indicates that a SW Reset has happened */ + __IOM uint32_t SWD_HWRESET_STAT : 1; /*!< [3..3] Indicates that a write to SWD_RESET_REG has happened. + * Note that it is also set when a POReset has happened. */ + __IOM uint32_t M33_WDOG_STAT : 1; /*!< [4..4] Indicates that M33 Watchdog has reached -16 while counting + * down and triggered a HW reset. Note that it is also set + * when a POReset has happened. */ + uint32_t : 27; + } RESET_STAT_REG_b; + }; + + union + { + __IOM uint32_t PMU_CTRL_REG; /*!< (@ 0x00000028) Spare register */ + + struct + { + __IOM uint32_t PHY_SLEEP : 1; /*!< [0..0] WiFi : PHY block sleep control */ + __IOM uint32_t MAC_SLEEP : 1; /*!< [1..1] WiFi : Mac block sleep control */ + uint32_t : 30; + } PMU_CTRL_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SYS_STATUS_REG; /*!< (@ 0x00000034) system status read register */ + + struct + { + __IM uint32_t SYS_IS_DOWN : 1; /*!< [0..0] 1 indicates PD_SYS is powered down */ + __IM uint32_t SYS_IS_UP : 1; /*!< [1..1] 1 indicates PD_SYS is powered on */ + __IM uint32_t MAC_IS_DOWN : 1; /*!< [2..2] 1 indicates PD_MAC is powered down */ + __IM uint32_t MAC_IS_UP : 1; /*!< [3..3] 1 indicates PD_MAC is powered on */ + __IM uint32_t PHY_IS_DOWN : 1; /*!< [4..4] 1 indicates PD_MAC is powered down */ + __IM uint32_t PHY_IS_UP : 1; /*!< [5..5] 1 indicates PD_MAC is powered on */ + __IM uint32_t DBG_IS_ACTIVE : 1; /*!< [6..6] 1 indicates a debugger is attached */ + uint32_t : 25; + } SYS_STATUS_REG_b; + }; + + union + { + __IOM uint32_t RFMON_INT_REG; /*!< (@ 0x00000038) RFMON Interface CRG control register */ + + struct + { + __IOM uint32_t CLK_ENABLE : 1; /*!< [0..0] RFMON Interface clock enable. 0=disable, 1=enable */ + __IOM uint32_t CFG_RESET : 1; /*!< [1..1] RFMON Interface configure reset. If set, RFMON inteface + * block will be reset. */ + uint32_t : 30; + } RFMON_INT_REG_b; + }; +} CRG_TOP_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ DAI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DAI registers (DAI) + */ + +typedef struct /*!< (@ 0x400E0900) DAI Structure */ +{ + union + { + __IOM uint32_t DAI_ENABLE_REG; /*!< (@ 0x00000000) DAI_ENABLE_REG */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] EN */ + uint32_t : 31; + } DAI_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t DAI_MODE_REG; /*!< (@ 0x00000004) DAI mode */ + + struct + { + __IOM uint32_t MODE : 1; /*!< [0..0] Selects between Master and Slave clock generation for + * the digital audio interface (DAI).0: Slave mode (DAI receives + * clocks)1: Master Mode (DAI generates clocks) */ + uint32_t : 31; + } DAI_MODE_REG_b; + }; + + union + { + __IOM uint32_t DAI_SLOT_CNT_REG; /*!< (@ 0x00000008) DAI maximum slot number */ + + struct + { + __IOM uint32_t SLOT_CNT : 2; /*!< [1..0] Total number of slots0: no slots are enabled,1-2: number + * of slots3-31: reserved */ + uint32_t : 30; + } DAI_SLOT_CNT_REG_b; + }; + + union + { + __IOM uint32_t DAI_CONFIG_REG; /*!< (@ 0x0000000C) DAI configuration */ + + struct + { + __IOM uint32_t FORMAT : 2; /*!< [1..0] DAI frame format.0: I2S1: LJF(Left justified)2: RJF(Right + * justified)3: DSP */ + __IOM uint32_t FRAME_LEN : 3; /*!< [4..2] Frame length control for the internal clock generator. + * The DAI word clock is generated with a 50% duty cycle according + * to the applied frame length.This register is ignored when + * the DAI is in slave mode.0: 32bit1: 64bit2: 128bit3: 256bit4-7 + * : Reserved */ + uint32_t : 27; + } DAI_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t DAI_W_LEN_REG; /*!< (@ 0x00000010) DAI word length */ + + struct + { + __IOM uint32_t W_LEN : 2; /*!< [1..0] The width of the audio data sent and received over the + * DAI per Channel.0: 16bits per slot1: 20bits per slot2: + * 24bits per slot3: 32bits per slot */ + uint32_t : 30; + } DAI_W_LEN_REG_b; + }; + + union + { + __IOM uint32_t DAI_DATA_OUT_CTRL_REG; /*!< (@ 0x00000014) DAI output control */ + + struct + { + __IOM uint32_t BCLK_POL : 1; /*!< [0..0] The BCLK edge used to sample incoming data (DATA_IN). + * Outgoing data (DATA_OUT) is driven on the opposite edge.0: + * Rising1: Falling */ + __IOM uint32_t WCLK_POL : 1; /*!< [1..1] The WCLK edge defining the start of the PCM frame. NOTE: + * The edge is dependent on the DAI Format.0: Rising (LJF, + * RJF, DSP), Falling (I2S)1: Falling (LJF, RJF, DSP), Rising + * (I2S) */ + uint32_t : 1; + __IOM uint32_t DATA_OUT_EN : 2; /*!< [4..3] DAI output enable.0: Hi-Z (Data output is tristate)1: + * Hi-Z (Data output is tristate)2: Enabled (Data driven on + * all slots)3: TDM (Data driven only during enabled slots) */ + __IOM uint32_t TDM_EARLY_RLS : 1; /*!< [5..5] Configures the timing of the DAI data output in TDM mode.0: + * Normal (dai_dataout_oe is driven until the end of the slot)1: + * Early (dai_dataout_oe is deasserted half of BCLK earlier + * at the end of the slot) */ + uint32_t : 26; + } DAI_DATA_OUT_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DAI_DATA_OUT_TEST_REG; /*!< (@ 0x00000018) DAI_DATA_OUT_TEST_REG */ + + struct + { + uint32_t : 2; + __IOM uint32_t DATA_OUT_POL : 1; /*!< [2..2] DATA_OUT_POL */ + uint32_t : 29; + } DAI_DATA_OUT_TEST_REG_b; + }; + + union + { + __IOM uint32_t DAI_OFFSET_MSB_REG; /*!< (@ 0x0000001C) DAI offset control [11:8] */ + + struct + { + __IOM uint32_t OFFSET_MSB : 4; /*!< [3..0] Bits 11-8 of the 12-bit OFFSET, which is the number of + * BCLK cycles offset relative to the normal data formatting. + * The minimum offset value is 0, the maximum is equal to + * the applied frame length. */ + uint32_t : 28; + } DAI_OFFSET_MSB_REG_b; + }; + + union + { + __IOM uint32_t DAI_OFFSET_LSB_REG; /*!< (@ 0x00000020) DAI offset control [7:0] */ + + struct + { + __IOM uint32_t OFFSET_LSB : 8; /*!< [7..0] Bits 7-0 of the 12-bit OFFSET, which is the number of + * BCLK cycles offset relative to the normal data formatting. + * The minimum offset value is 0, the maximum is equal to + * the applied frame length. DAI_OFFSET_MSB_REG hold bits + * 11-8 */ + uint32_t : 24; + } DAI_OFFSET_LSB_REG_b; + }; + + union + { + __IOM uint32_t DAI_TX1_CH_REG; /*!< (@ 0x00000024) DAI slot number mapped to TX channel1 */ + + struct + { + __IOM uint32_t TX1_CH : 2; /*!< [1..0] DAI TX channel1 mapping to slots 1 - 160: Disable channel1-2: + * slots 1-163-32: Reserved */ + uint32_t : 30; + } DAI_TX1_CH_REG_b; + }; + + union + { + __IOM uint32_t DAI_TX2_CH_REG; /*!< (@ 0x00000028) DAI slot number mapped to TX channel2 */ + + struct + { + __IOM uint32_t TX2_CH : 2; /*!< [1..0] DAI TX channel2 mapping to slots 1 - 160: Disable channel1-2: + * slots 1-163-32: Reserved */ + uint32_t : 30; + } DAI_TX2_CH_REG_b; + }; + __IM uint32_t RESERVED[10]; + + union + { + __IOM uint32_t DAI_RX1_CH_REG; /*!< (@ 0x00000054) DAI slot number mapped to RX channel1 */ + + struct + { + __IOM uint32_t RX1_CH : 2; /*!< [1..0] DAI RX channel1 mapping to slots 1 - 160: Disable channel1-2: + * slots 1-163-32: Reserved */ + uint32_t : 30; + } DAI_RX1_CH_REG_b; + }; + + union + { + __IOM uint32_t DAI_RX2_CH_REG; /*!< (@ 0x00000058) DAI slot number mapped to RX channel2 */ + + struct + { + __IOM uint32_t RX2_CH : 2; /*!< [1..0] DAI RX channel2 mapping to slots 1 - 160: Disable channel1-2: + * slots 1-163-32: Reserved */ + uint32_t : 30; + } DAI_RX2_CH_REG_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t DAI_SYNC_WIN_REG; /*!< (@ 0x00000084) DAI_SYNC_WIN_REG */ + + struct + { + __IOM uint32_t SYNC_WIN_WIDTH : 5; /*!< [4..0] SYNC_WIN_WIDTH */ + uint32_t : 2; + __IOM uint32_t SYNC_WIN_MODE : 1; /*!< [7..7] SYNC_WIN_MODE */ + uint32_t : 24; + } DAI_SYNC_WIN_REG_b; + }; + + union + { + __IOM uint32_t DAI_TX1_REG; /*!< (@ 0x00000088) DAI TX1 Data */ + + struct + { + __IOM uint32_t TX1_REG : 32; /*!< [31..0] DAI TX1 Data register */ + } DAI_TX1_REG_b; + }; + + union + { + __IOM uint32_t DAI_TX2_REG; /*!< (@ 0x0000008C) DAI TX2 Data */ + + struct + { + __IOM uint32_t TX2_REG : 32; /*!< [31..0] DAI TX2 Data register */ + } DAI_TX2_REG_b; + }; + __IM uint32_t RESERVED2[10]; + + union + { + __IOM uint32_t DAI_RX1_REG; /*!< (@ 0x000000B8) DAI RX1 Data */ + + struct + { + __IM uint32_t RX1_REG : 32; /*!< [31..0] DAI RX1 Data register */ + } DAI_RX1_REG_b; + }; + + union + { + __IOM uint32_t DAI_RX2_REG; /*!< (@ 0x000000BC) DAI RX2 Data */ + + struct + { + __IM uint32_t RX2_REG : 32; /*!< [31..0] DAI RX2 Data register */ + } DAI_RX2_REG_b; + }; + __IM uint32_t RESERVED3[10]; + + union + { + __IOM uint32_t DAI_TX_MUX_REG; /*!< (@ 0x000000E8) DAI TX data selection */ + + struct + { + __IOM uint32_t DAI_TX1_SEL : 1; /*!< [0..0] DAI TX1 data selection0: DAI_TX1_REG1: DAI_TX1 (from + * SRC1_OUT1) */ + __IOM uint32_t DAI_TX2_SEL : 1; /*!< [1..1] DAI TX2 data selection0: DAI_TX2_REG1: DAI_TX2 (from + * SRC1_OUT2) */ + uint32_t : 30; + } DAI_TX_MUX_REG_b; + }; + + union + { + __IOM uint32_t DAI_SR_CONFIG_REG; /*!< (@ 0x000000EC) DAI Sample rate configuration */ + + struct + { + __IOM uint32_t DAI_SR : 5; /*!< [4..0] DAI sample rate (kHz)0x00: Reserved0x01: 80x02: 11.0250x03: + * 120x04: Reserved0x05: 160x06: 22.050x07: 240x08: Reserved0x09: + * 320x0A: 44.10x0B: 480x0C: Reserved0x0D: Reserved0x0E: 88.20x0F: + * 960x10: Reserved0x11: Reserved0x12: 176.40x13: 192Others: + * Reserved */ + uint32_t : 27; + } DAI_SR_CONFIG_REG_b; + }; +} DAI_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ DCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DCACHE registers (DCACHE) + */ + +typedef struct /*!< (@ 0x21000000) DCACHE Structure */ +{ + union + { + __IOM uint32_t DCACHE_CTRL_REG; /*!< (@ 0x00000000) Dcache Control Register */ + + struct + { + __IOM uint32_t DCACHE_LEN : 18; /*!< [17..0] Length of PSRAM cacheable memory.N*1 kB. N = 0 to 131072 + * (max. of 128 MB).Setting DCACHE_LEN = 0 disables the caching. */ + __IOM uint32_t DCACHE_ENABLE : 1; /*!< [18..18] Enable the dcache controller hardware block:0: Disabled, + * all AHB accesses towards the QSPI are bypassing the hardware + * block straight into the PSRAM.1: Enabled, all AHB access + * towards the QSPI within the cacheable region are cached. */ + __OM uint32_t DCACHE_INIT : 1; /*!< [19..19] Writing 1 to this field triggers an initialization + * of the cache (0s are written in the TAG area). Reading + * from this field always returns 0. */ + __OM uint32_t DCACHE_WFLUSH : 1; /*!< [20..20] Writing 1 to this field triggers a write flush of the + * "dirty" lines. All modified data in the "dirty" line are + * written back to the PSRAM. The corresponding "dirty" bits + * are cleared. Reading this bit returns 0. */ + __IM uint32_t DCACHE_READY : 1; /*!< [21..21] 0: DCACHE is not initialized yet.1: DCACHE initialization + * is completed. */ + __IOM uint32_t DCACHE_WFLUSHED : 1; /*!< [22..22] 0: DCACHE is not write flushed yet.1: DCACHE is write + * flushed.Note 1: Setting and clearing of this (status) bit + * field is automatically done by the hardware.Note 2: The + * CACHE_WFLUSHED bit can also be cleared first by the software + * by writing 0. */ + __IM uint32_t DCACHE_WBUFFER_EMPTY : 1; /*!< [23..23] Status of the write buffer.0: Write buffer is not empty.1: + * Write buffer is empty. */ + __IOM uint32_t DCACHE_WBUFFER_FLUSH : 1; /*!< [24..24] Write buffer flush.0: Write buffer is not flushed (default).1: + * Write buffer is flushed. */ + __IOM uint32_t DCACHE_DISABLE_CLKGATE : 1; /*!< [25..25] DCACHE_DISABLE_CLKGATE */ + uint32_t : 6; + } DCACHE_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_BASE_ADDR_REG; /*!< (@ 0x00000004) Dcache base address for cacheable region */ + + struct + { + __IOM uint32_t DCACHE_BASE_ADDR : 17; /*!< [16..0] Base of PSRAM cacheable memory.N*1 kB. N = 0 to 131072 + * (max. of 128 MB). */ + uint32_t : 15; + } DCACHE_BASE_ADDR_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_HITS_REG; /*!< (@ 0x00000008) Dcache MRM (Miss Rate Monitor) HITS Register */ + + struct + { + __IOM uint32_t MRM_HITS : 32; /*!< [31..0] Contain the amount of cache hits. */ + } DCACHE_MRM_HITS_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_MISSES_REG; /*!< (@ 0x0000000C) Dcache MRM (Miss Rate Monitor) MISSES Register */ + + struct + { + __IOM uint32_t MRM_MISSES : 32; /*!< [31..0] Contain the amount of cache misses. */ + } DCACHE_MRM_MISSES_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_EVICTS_REG; /*!< (@ 0x00000010) Dcache MRM (Miss Rate Monitor) EVICTS Register */ + + struct + { + __IOM uint32_t MRM_EVICTS : 32; /*!< [31..0] Contain the amount of cache evicts. */ + } DCACHE_MRM_EVICTS_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_CTRL_REG; /*!< (@ 0x00000014) Dcache MRM (Miss Rate Monitor) CONTROL Register */ + + struct + { + __IOM uint32_t MRM_START : 1; /*!< [0..0] 0: Freeze the "misses/hits" counters and reset the time + * interval counter to the programmed value in CACHE_MRM_TINT_REG.1: + * Enables the counters.Note: In case CACHE_MRM_CTRL_REG[MRM_START] + * is set to 1 and CACHE_MRM_TINT_REG (!=0) is used for the + * MRM interrupt generation, the time interval counter counts + * down (on a fixed reference clock of 16 MHz) until it is + * 0. At that time CACHE_MRM_CTRL_REG[MRM_START] is reset + * automatically to 0 by the MRM hardware and the MRM interrupt + * is generated. */ + __IOM uint32_t MRM_IRQ_MASK : 1; /*!< [1..1] 0: Disables interrupt generation.1: Enables interrupt + * generation.Note: The Cache MRM generates a pulse-sensitive + * interrupt towards the Am processor. */ + __IOM uint32_t MRM_IRQ_TINT_STATUS : 1; /*!< [2..2] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the time interval counter reached + * the end (time interval != 0). */ + __IOM uint32_t MRM_IRQ_MISSES_THRES_STATUS : 1; /*!< [3..3] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the number of cache misses reached + * the programmed threshold (threshold != 0). */ + __IOM uint32_t MRM_IRQ_HITS_THRES_STATUS : 1; /*!< [4..4] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the number of cache hits reached the + * programmed threshold (threshold != 0). */ + __IOM uint32_t MRM_IRQ_EVICTS_THRES_STATUS : 1; /*!< [5..5] 0: No interrupt is generated.1: Interrupt (pulse-sensitive) + * is generated because the number of cache evicts reached + * the programmed threshold (threshold != 0). */ + uint32_t : 26; + } DCACHE_MRM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_TINT_REG; /*!< (@ 0x00000018) Dcache MRM (Miss Rate Monitor) TIME INTERVAL + * Register */ + + struct + { + __IOM uint32_t MRM_TINT : 19; /*!< [18..0] Define the time interval for the monitoring in (bus + * clock/4) clock cycles.Also, see the description of CACHE_MRM_CTRL_REG[MRM + * IRQ_TINT_STATUS].Note: When MRM_TINT = 0 (unrealistic value), + * no interrupt is generated. */ + uint32_t : 13; + } DCACHE_MRM_TINT_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_MISSES_THRES_REG; /*!< (@ 0x0000001C) Dcache MRM (Miss Rate Monitor) THRESHOLD Register */ + + struct + { + __IOM uint32_t MRM_MISSES_THRES : 32; /*!< [31..0] Define the misses threshold to trigger the interrupt + * generation.Also, see the description of CACHE_MRM_CTRL_REG[MRM_IRQ_MISSES + * THRES_STATUS].Note: When MRM_MISSES_THRES = 0 (unrealistic + * value), no interrupt is generated. */ + } DCACHE_MRM_MISSES_THRES_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_HITS_THRES_REG; /*!< (@ 0x00000020) Dcache MRM (Miss Rate Monitor) HITS THRESHOLD + * Register */ + + struct + { + __IOM uint32_t MRM_HITS_THRES : 32; /*!< [31..0] Define the hits threshold to trigger the interrupt generation.Alos, + * see the description of CACHE_MRM_CTRL_REG[MRM_IRQ_HITS_THRES_STATUS].Note + * When MRM_HITS_THRES = 0 (unrealistic value), no interrupt + * is generated. */ + } DCACHE_MRM_HITS_THRES_REG_b; + }; + + union + { + __IOM uint32_t DCACHE_MRM_EVICTS_THRES_REG; /*!< (@ 0x00000024) Dcache MRM (Miss Rate Monitor) EVICTS THRESHOLD + * Register */ + + struct + { + __IOM uint32_t MRM_EVICTS_THRES : 32; /*!< [31..0] Define the hits threshold to trigger the interrupt generation.Also, + * see the description of CACHE_MRM_CTRL_REG[MRM_IRQ_EVICTS_THRES_STATUS].No + * e: When MRM_EVICTS_THRES = 0 (unrealistic value), no interrupt + * is generated. */ + } DCACHE_MRM_EVICTS_THRES_REG_b; + }; +} DCACHE_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA registers (DMA) + */ + +typedef struct /*!< (@ 0x40070700) DMA Structure */ +{ + union + { + __IOM uint32_t DMA0_A_START_REG; /*!< (@ 0x00000000) Start address A of DMA channel 0 */ + + struct + { + __IOM uint32_t DMA0_A_START : 32; /*!< [31..0] Source start address */ + } DMA0_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA0_B_START_REG; /*!< (@ 0x00000004) Start address B of DMA channel 0 */ + + struct + { + __IOM uint32_t DMA0_B_START : 32; /*!< [31..0] Destination start address */ + } DMA0_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA0_INT_REG; /*!< (@ 0x00000008) DMA receive interrupt register channel 0 */ + + struct + { + __IOM uint32_t DMA0_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA0_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA0_LEN_REG; /*!< (@ 0x0000000C) DMA receive length register channel 0 */ + + struct + { + __IOM uint32_t DMA0_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA0_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA0_CTRL_REG; /*!< (@ 0x00000010) Control register for the DMA channel 0 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers and 24/32-bit audio samples)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA0_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA0_IDX_REG; /*!< (@ 0x00000014) Index value of DMA channel 0 */ + + struct + { + __IM uint32_t DMA0_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA0_IDX_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t DMA1_A_START_REG; /*!< (@ 0x00000020) Start address A of DMA channel 1 */ + + struct + { + __IOM uint32_t DMA1_A_START : 32; /*!< [31..0] Source start address */ + } DMA1_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA1_B_START_REG; /*!< (@ 0x00000024) Start address B of DMA channel 1 */ + + struct + { + __IOM uint32_t DMA1_B_START : 32; /*!< [31..0] Destination start address */ + } DMA1_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA1_INT_REG; /*!< (@ 0x00000028) DMA receive interrupt register channel 1 */ + + struct + { + __IOM uint32_t DMA1_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA1_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA1_LEN_REG; /*!< (@ 0x0000002C) DMA receive length register channel 1 */ + + struct + { + __IOM uint32_t DMA1_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA1_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA1_CTRL_REG; /*!< (@ 0x00000030) Control register for the DMA channel 1 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA1_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA1_IDX_REG; /*!< (@ 0x00000034) Index value of DMA channel 1 */ + + struct + { + __IM uint32_t DMA1_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA1_IDX_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t DMA2_A_START_REG; /*!< (@ 0x00000040) Start address A of DMA channel 2 */ + + struct + { + __IOM uint32_t DMA2_A_START : 32; /*!< [31..0] Source start address */ + } DMA2_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA2_B_START_REG; /*!< (@ 0x00000044) Start address B of DMA channel 2 */ + + struct + { + __IOM uint32_t DMA2_B_START : 32; /*!< [31..0] Destination start address */ + } DMA2_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA2_INT_REG; /*!< (@ 0x00000048) DMA receive interrupt register channel 2 */ + + struct + { + __IOM uint32_t DMA2_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA2_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA2_LEN_REG; /*!< (@ 0x0000004C) DMA receive length register channel 2 */ + + struct + { + __IOM uint32_t DMA2_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA2_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA2_CTRL_REG; /*!< (@ 0x00000050) Control register for the DMA channel 2 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address0 = do not increment1 + * = increment according value of BW */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA2_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA2_IDX_REG; /*!< (@ 0x00000054) Index value of DMA channel 2 */ + + struct + { + __IM uint32_t DMA2_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA2_IDX_REG_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DMA3_A_START_REG; /*!< (@ 0x00000060) Start address A of DMA channel 3 */ + + struct + { + __IOM uint32_t DMA3_A_START : 32; /*!< [31..0] Source start address */ + } DMA3_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA3_B_START_REG; /*!< (@ 0x00000064) Start address B of DMA channel 3 */ + + struct + { + __IOM uint32_t DMA3_B_START : 32; /*!< [31..0] Destination start address */ + } DMA3_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA3_INT_REG; /*!< (@ 0x00000068) DMA receive interrupt register channel 3 */ + + struct + { + __IOM uint32_t DMA3_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA3_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA3_LEN_REG; /*!< (@ 0x0000006C) DMA receive length register channel 3 */ + + struct + { + __IOM uint32_t DMA3_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA3_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA3_CTRL_REG; /*!< (@ 0x00000070) Control register for the DMA channel 3 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA3_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA3_IDX_REG; /*!< (@ 0x00000074) Index value of DMA channel 3 */ + + struct + { + __IM uint32_t DMA3_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA3_IDX_REG_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t DMA4_A_START_REG; /*!< (@ 0x00000080) Start address A of DMA channel 4 */ + + struct + { + __IOM uint32_t DMA4_A_START : 32; /*!< [31..0] Source start address */ + } DMA4_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA4_B_START_REG; /*!< (@ 0x00000084) Start address B of DMA channel 4 */ + + struct + { + __IOM uint32_t DMA4_B_START : 32; /*!< [31..0] Destination start address */ + } DMA4_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA4_INT_REG; /*!< (@ 0x00000088) DMA receive interrupt register channel 4 */ + + struct + { + __IOM uint32_t DMA4_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA4_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA4_LEN_REG; /*!< (@ 0x0000008C) DMA receive length register channel 4 */ + + struct + { + __IOM uint32_t DMA4_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA4_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA4_CTRL_REG; /*!< (@ 0x00000090) Control register for the DMA channel 4 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA4_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA4_IDX_REG; /*!< (@ 0x00000094) Index value of DMA channel 4 */ + + struct + { + __IM uint32_t DMA4_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA4_IDX_REG_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t DMA5_A_START_REG; /*!< (@ 0x000000A0) Start address A of DMA channel 5 */ + + struct + { + __IOM uint32_t DMA5_A_START : 32; /*!< [31..0] Source start address */ + } DMA5_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA5_B_START_REG; /*!< (@ 0x000000A4) Start address B of DMA channel 5 */ + + struct + { + __IOM uint32_t DMA5_B_START : 32; /*!< [31..0] Destination start address */ + } DMA5_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA5_INT_REG; /*!< (@ 0x000000A8) DMA receive interrupt register channel 5 */ + + struct + { + __IOM uint32_t DMA5_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA5_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA5_LEN_REG; /*!< (@ 0x000000AC) DMA receive length register channel 5 */ + + struct + { + __IOM uint32_t DMA5_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA5_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA5_CTRL_REG; /*!< (@ 0x000000B0) Control register for the DMA channel 5 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA5_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA5_IDX_REG; /*!< (@ 0x000000B4) Index value of DMA channel 5 */ + + struct + { + __IM uint32_t DMA5_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA5_IDX_REG_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t DMA6_A_START_REG; /*!< (@ 0x000000C0) Start address A of DMA channel 6 */ + + struct + { + __IOM uint32_t DMA6_A_START : 32; /*!< [31..0] Source start address */ + } DMA6_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA6_B_START_REG; /*!< (@ 0x000000C4) Start address B of DMA channel 6 */ + + struct + { + __IOM uint32_t DMA6_B_START : 32; /*!< [31..0] Destination start address */ + } DMA6_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA6_INT_REG; /*!< (@ 0x000000C8) DMA receive interrupt register channel 6 */ + + struct + { + __IOM uint32_t DMA6_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA6_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA6_LEN_REG; /*!< (@ 0x000000CC) DMA receive length register channel 6 */ + + struct + { + __IOM uint32_t DMA6_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA6_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA6_CTRL_REG; /*!< (@ 0x000000D0) Control register for the DMA channel 6 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA6_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA6_IDX_REG; /*!< (@ 0x000000D4) Index value of DMA channel 6 */ + + struct + { + __IM uint32_t DMA6_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA6_IDX_REG_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DMA7_A_START_REG; /*!< (@ 0x000000E0) Start address A of DMA channel 7 */ + + struct + { + __IOM uint32_t DMA7_A_START : 32; /*!< [31..0] Source start address */ + } DMA7_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA7_B_START_REG; /*!< (@ 0x000000E4) Start address B of DMA channel 7 */ + + struct + { + __IOM uint32_t DMA7_B_START : 32; /*!< [31..0] Destination start address */ + } DMA7_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA7_INT_REG; /*!< (@ 0x000000E8) DMA receive interrupt register channel 7 */ + + struct + { + __IOM uint32_t DMA7_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA7_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA7_LEN_REG; /*!< (@ 0x000000EC) DMA receive length register channel 7 */ + + struct + { + __IOM uint32_t DMA7_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA7_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA7_CTRL_REG; /*!< (@ 0x000000F0) Control register for the DMA channel 7 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA7_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA7_IDX_REG; /*!< (@ 0x000000F4) Index value of DMA channel 7 */ + + struct + { + __IM uint32_t DMA7_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA7_IDX_REG_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint32_t DMA8_A_START_REG; /*!< (@ 0x00000100) Start address A of DMA channel 8 */ + + struct + { + __IOM uint32_t DMA8_A_START : 32; /*!< [31..0] Source start address */ + } DMA8_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA8_B_START_REG; /*!< (@ 0x00000104) Start address B of DMA channel 8 */ + + struct + { + __IOM uint32_t DMA8_B_START : 32; /*!< [31..0] Destination start address */ + } DMA8_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA8_INT_REG; /*!< (@ 0x00000108) DMA receive interrupt register channel 8 */ + + struct + { + __IOM uint32_t DMA8_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA8_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA8_LEN_REG; /*!< (@ 0x0000010C) DMA receive length register channel 8 */ + + struct + { + __IOM uint32_t DMA8_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA8_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA8_CTRL_REG; /*!< (@ 0x00000110) Control register for the DMA channel 8 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA8_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA8_IDX_REG; /*!< (@ 0x00000114) Index value of DMA channel 8 */ + + struct + { + __IM uint32_t DMA8_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA8_IDX_REG_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t DMA9_A_START_REG; /*!< (@ 0x00000120) Start address A of DMA channel 9 */ + + struct + { + __IOM uint32_t DMA9_A_START : 32; /*!< [31..0] Source start address */ + } DMA9_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA9_B_START_REG; /*!< (@ 0x00000124) Start address B of DMA channel 9 */ + + struct + { + __IOM uint32_t DMA9_B_START : 32; /*!< [31..0] Destination start address */ + } DMA9_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA9_INT_REG; /*!< (@ 0x00000128) DMA receive interrupt register channel 9 */ + + struct + { + __IOM uint32_t DMA9_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA9_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA9_LEN_REG; /*!< (@ 0x0000012C) DMA receive length register channel 9 */ + + struct + { + __IOM uint32_t DMA9_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA9_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA9_CTRL_REG; /*!< (@ 0x00000130) Control register for the DMA channel 9 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA9_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA9_IDX_REG; /*!< (@ 0x00000134) Index value of DMA channel 9 */ + + struct + { + __IM uint32_t DMA9_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA9_IDX_REG_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t DMA10_A_START_REG; /*!< (@ 0x00000140) Start address A of DMA channel 10 */ + + struct + { + __IOM uint32_t DMA10_A_START : 32; /*!< [31..0] Source start address */ + } DMA10_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA10_B_START_REG; /*!< (@ 0x00000144) Start address B of DMA channel 10 */ + + struct + { + __IOM uint32_t DMA10_B_START : 32; /*!< [31..0] Destination start address */ + } DMA10_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA10_INT_REG; /*!< (@ 0x00000148) DMA receive interrupt register channel 10 */ + + struct + { + __IOM uint32_t DMA10_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA10_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA10_LEN_REG; /*!< (@ 0x0000014C) DMA receive length register channel 10 */ + + struct + { + __IOM uint32_t DMA10_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA10_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA10_CTRL_REG; /*!< (@ 0x00000150) Control register for the DMA channel 10 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA10_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA10_IDX_REG; /*!< (@ 0x00000154) Index value of DMA channel 10 */ + + struct + { + __IM uint32_t DMA10_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA10_IDX_REG_b; + }; + __IM uint32_t RESERVED10[2]; + + union + { + __IOM uint32_t DMA11_A_START_REG; /*!< (@ 0x00000160) Start address A of DMA channel 11 */ + + struct + { + __IOM uint32_t DMA11_A_START : 32; /*!< [31..0] Source start address */ + } DMA11_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA11_B_START_REG; /*!< (@ 0x00000164) Start address B of DMA channel 11 */ + + struct + { + __IOM uint32_t DMA11_B_START : 32; /*!< [31..0] Destination start address */ + } DMA11_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA11_INT_REG; /*!< (@ 0x00000168) DMA receive interrupt register channel 11 */ + + struct + { + __IOM uint32_t DMA11_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA11_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA11_LEN_REG; /*!< (@ 0x0000016C) DMA receive length register channel 11 */ + + struct + { + __IOM uint32_t DMA11_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA11_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA11_CTRL_REG; /*!< (@ 0x00000170) Control register for the DMA channel 11 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA11_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA11_IDX_REG; /*!< (@ 0x00000174) Index value of DMA channel 11 */ + + struct + { + __IM uint32_t DMA11_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA11_IDX_REG_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t DMA12_A_START_REG; /*!< (@ 0x00000180) Start address A of DMA channel 12 */ + + struct + { + __IOM uint32_t DMA12_A_START : 32; /*!< [31..0] Source start address */ + } DMA12_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA12_B_START_REG; /*!< (@ 0x00000184) Start address B of DMA channel 12 */ + + struct + { + __IOM uint32_t DMA12_B_START : 32; /*!< [31..0] Destination start address */ + } DMA12_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA12_INT_REG; /*!< (@ 0x00000188) DMA receive interrupt register channel 12 */ + + struct + { + __IOM uint32_t DMA12_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA12_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA12_LEN_REG; /*!< (@ 0x0000018C) DMA receive length register channel 12 */ + + struct + { + __IOM uint32_t DMA12_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA12_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA12_CTRL_REG; /*!< (@ 0x00000190) Control register for the DMA channel 12 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA12_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA12_IDX_REG; /*!< (@ 0x00000194) Index value of DMA channel 12 */ + + struct + { + __IM uint32_t DMA12_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA12_IDX_REG_b; + }; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint32_t DMA13_A_START_REG; /*!< (@ 0x000001A0) Start address A of DMA channel 13 */ + + struct + { + __IOM uint32_t DMA13_A_START : 32; /*!< [31..0] Source start address */ + } DMA13_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA13_B_START_REG; /*!< (@ 0x000001A4) Start address B of DMA channel 13 */ + + struct + { + __IOM uint32_t DMA13_B_START : 32; /*!< [31..0] Destination start address */ + } DMA13_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA13_INT_REG; /*!< (@ 0x000001A8) DMA receive interrupt register channel 13 */ + + struct + { + __IOM uint32_t DMA13_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA13_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA13_LEN_REG; /*!< (@ 0x000001AC) DMA receive length register channel 13 */ + + struct + { + __IOM uint32_t DMA13_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA13_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA13_CTRL_REG; /*!< (@ 0x000001B0) Control register for the DMA channel 13 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA13_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA13_IDX_REG; /*!< (@ 0x000001B4) Index value of DMA channel 13 */ + + struct + { + __IM uint32_t DMA13_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA13_IDX_REG_b; + }; + __IM uint32_t RESERVED13[2]; + + union + { + __IOM uint32_t DMA14_A_START_REG; /*!< (@ 0x000001C0) Start address A of DMA channel 14 */ + + struct + { + __IOM uint32_t DMA14_A_START : 32; /*!< [31..0] Source start address */ + } DMA14_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA14_B_START_REG; /*!< (@ 0x000001C4) Start address B of DMA channel 14 */ + + struct + { + __IOM uint32_t DMA14_B_START : 32; /*!< [31..0] Destination start address */ + } DMA14_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA14_INT_REG; /*!< (@ 0x000001C8) DMA receive interrupt register channel 14 */ + + struct + { + __IOM uint32_t DMA14_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA14_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA14_LEN_REG; /*!< (@ 0x000001CC) DMA receive length register channel 14 */ + + struct + { + __IOM uint32_t DMA14_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA14_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA14_CTRL_REG; /*!< (@ 0x000001D0) Control register for the DMA channel 14 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA14_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA14_IDX_REG; /*!< (@ 0x000001D4) Index value of DMA channel 14 */ + + struct + { + __IM uint32_t DMA14_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA14_IDX_REG_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IOM uint32_t DMA15_A_START_REG; /*!< (@ 0x000001E0) Start address A of DMA channel 15 */ + + struct + { + __IOM uint32_t DMA15_A_START : 32; /*!< [31..0] Source start address */ + } DMA15_A_START_REG_b; + }; + + union + { + __IOM uint32_t DMA15_B_START_REG; /*!< (@ 0x000001E4) Start address B of DMA channel 15 */ + + struct + { + __IOM uint32_t DMA15_B_START : 32; /*!< [31..0] Destination start address */ + } DMA15_B_START_REG_b; + }; + + union + { + __IOM uint32_t DMA15_INT_REG; /*!< (@ 0x000001E8) DMA receive interrupt register channel 15 */ + + struct + { + __IOM uint32_t DMA15_INT : 16; /*!< [15..0] Number of transfers until an interrupt is generated. + * The interrupt is generated after a transfer, if DMAx_INT_REG + * is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. + * The bit-field DMA_IRQ_ENABLEx of DMA_INT_MASK_REG must + * be set to '1' to let the controller generate the interrupt. */ + uint32_t : 16; + } DMA15_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA15_LEN_REG; /*!< (@ 0x000001EC) DMA receive length register channel 15 */ + + struct + { + __IOM uint32_t DMA15_LEN : 16; /*!< [15..0] DMA channel's transfer length. DMAx_LEN of value 0, + * 1, 2, ... results into an actual transfer length of 1, + * 2, 3, ... */ + uint32_t : 16; + } DMA15_LEN_REG_b; + }; + + union + { + __IOM uint32_t DMA15_CTRL_REG; /*!< (@ 0x000001F0) Control register for the DMA channel 15 */ + + struct + { + __IOM uint32_t DMA_ON : 1; /*!< [0..0] 0 = DMA channel is off, clocks are disabled1 = DMA channel + * is enabled. This bit will be automatically cleared after + * the completion of a transfer, if circular mode is not enabled. + * In circular mode, this bit stays set.Note: If DMA_ON is + * disabled by SW while the DMA channel is active, it cannot + * be enabled again until the channel has completed the last + * on-going read-write cycle and has stopped. Thus, the SW + * has to check that the reading of DMAx_CTRL_REG. DMA_ON + * returns 0, before setting again the spe */ + __IOM uint32_t BW : 2; /*!< [2..1] Bus transfer width:00 = 1 Byte (suggested for peripherals + * like UART and 8-bit SPI)01 = 2 Bytes (suggested for peripherals + * like I2C and 16-bit SPI)10 = 4 Bytes (suggested for Memory-to-Memory + * transfers)11 = Reserved */ + __IOM uint32_t DREQ_MODE : 1; /*!< [3..3] 0 = DMA channel starts immediately1 = DMA channel must + * be triggered by peripheral DMA request (see also the description + * of DMA_REQ_MUX_REG) */ + __IOM uint32_t BINC : 1; /*!< [4..4] Enable increment of destination address.0 = do not increment + * (destination address stays the same during the transfer)1 + * = increment according to the value of BW bit-field (by + * 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t AINC : 1; /*!< [5..5] Enable increment of source address.0 = do not increment + * (source address stays the same during the transfer)1 = + * increment according to the value of BW bit-field (by 1, + * when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") */ + __IOM uint32_t CIRCULAR : 1; /*!< [6..6] 0 = Normal mode. The DMA channel stops after having completed + * the transfer of length determined by DMAx_LEN_REG. DMA_ON + * automatically deasserts when the transfer is completed.1 + * = Circular mode (applicable only if DREQ_MODE = '1'). In + * this mode, DMA_ON never deasserts, as the DMA channel automatically + * resets DMAx_IDX_REG and starts a new transfer. */ + __IOM uint32_t DMA_PRIO : 3; /*!< [9..7] The priority level determines which DMA channel will + * be granted access for transferring data, in case more than + * one channels are active and request the bus at the same + * time. The greater the value, the higher the priority. In + * specific:000 = lowest priority111 = highest priorityIf + * different channels with equal priority level values request + * the bus at the same time, an inherent priority mechanism + * is applied. According to this mechanism, if, for example, + * both the DMA0 and DMA1 channels have the s */ + __IOM uint32_t DMA_IDLE : 1; /*!< [10..10] 0 = Blocking mode, the DMA performs a fast back-to-back + * copy, disabling bus access for any bus master with lower + * priority.1 = Interrupting mode, the DMA inserts a wait + * cycle after each store allowing the CPU to steal cycles + * or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE + * is don't care. */ + __IOM uint32_t DMA_INIT : 1; /*!< [11..11] 0 = DMA performs copy A1 to B1, A2 to B2, etc ...1 + * = DMA performs copy of A1 to B1, B2, etc ...This feature + * is useful for memory initialization to any value. Thus, + * BINC must be set to '1', while AINC is don't care, as only + * one fetch from A is done. This process cannot be interrupted + * by other DMA channels. It is also noted that DMA_INIT should + * not be used when DREQ_MODE='1'. */ + __IOM uint32_t REQ_SENSE : 1; /*!< [12..12] 0 = DMA operates with level-sensitive peripheral requests + * (default)1 = DMA operates with (positive) edge-sensitive + * peripheral requests */ + __IOM uint32_t BURST_MODE : 2; /*!< [14..13] Enables the DMA read/write bursts, according to the + * following configuration:00 = Bursts are disabled01 = Bursts + * of 4 are enabled10 = Bursts of 8 are enabled11 = Reserved */ + __IOM uint32_t BUS_ERROR_DETECT : 1; /*!< [15..15] 0 = Ignores bus error response from the AHB bus, so + * DMA continues normally.1 = Detects the bus response and + * tracks any bus error may occur during the transfer. If + * a bus error is detected, the channel completes the current + * read-write DMA cycle (either in burst or single transfers + * mode) and then closes the transfer, de-asserting DMA_ON + * bit automatically.It is noted that the respective bus error + * detection status bit of DMA_INT_STATUS_REG is automatically + * cleared as soon as the channel is switched-on */ + __IOM uint32_t ADDR_INC : 3; /*!< [18..16] Address increment definition for the peripherals (BW + * 32bit only)000 : 4byte001 : 8byte010 : 12byte011 : 16byte100 + * : 20byte101 : 24byte110 : 28byte111 : 32byte */ + uint32_t : 13; + } DMA15_CTRL_REG_b; + }; + + union + { + __IOM uint32_t DMA15_IDX_REG; /*!< (@ 0x000001F4) Index value of DMA channel 15 */ + + struct + { + __IM uint32_t DMA15_IDX : 16; /*!< [15..0] This (read-only) register determines the data items + * already transferred by the DMA channel. Hence, if its value + * is 1, then the DMA channel has already copied one data + * item and it is currently performing the next copy. If its + * value is 2, then two items have already been copied and + * so on.When the transfer is completed (so when DMAx_CTRL_REG. + * DMA_ON has been cleared) and DMAx_CTRL_REG. CIRCULAR is + * not set, the register keeps its (last) value (which should + * be equal to DMAx_LEN_REG) and it is automaticall */ + uint32_t : 16; + } DMA15_IDX_REG_b; + }; + __IM uint32_t RESERVED15[2]; + + union + { + __IOM uint32_t DMA_REQ_MUX_REG; /*!< (@ 0x00000200) DMA channel assignments (Channel 0~3) */ + + struct + { + __IOM uint32_t DMA0_SEL : 5; /*!< [4..0] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 0.0x00: SPI_RX0x01: + * SPI_TX0x02: SPI2_RX0x03: SPI2_TX0x04: UART_RX0x05: UART_TX0x06: + * UART2_RX0x07: UART2_TX0x08: UART3RX0x09: UART3_TX0x0A: + * I2C_RX0x0B: I2C_TX0x0C: I2C2_RX0x0D: I2C2_TX0x0E: AUXADC<0>0x0F: + * AUXADC<1>0x10: AUXADC<2>0x11: AUXADC<3>0x12: SRC_IN0x13: + * SRC_OUT0x14: DAI_TX0x15: DAI_RXNote: If any of t */ + uint32_t : 3; + __IOM uint32_t DMA1_SEL : 5; /*!< [12..8] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 1.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA2_SEL : 5; /*!< [20..16] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 2.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA3_SEL : 5; /*!< [28..24] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 3See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + } DMA_REQ_MUX_REG_b; + }; + + union + { + __IOM uint32_t DMA_REQ_MUX2_REG; /*!< (@ 0x00000204) DMA channel assignments (Channel 4~7) */ + + struct + { + __IOM uint32_t DMA4_SEL : 5; /*!< [4..0] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 4.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA5_SEL : 5; /*!< [12..8] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 5.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA6_SEL : 5; /*!< [20..16] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 6.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA7_SEL : 5; /*!< [28..24] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 7.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + } DMA_REQ_MUX2_REG_b; + }; + + union + { + __IOM uint32_t DMA_REQ_MUX3_REG; /*!< (@ 0x00000208) DMA channel assignments (Channel 8~11) */ + + struct + { + __IOM uint32_t DMA8_SEL : 5; /*!< [4..0] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 8.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA9_SEL : 5; /*!< [12..8] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 9.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA10_SEL : 5; /*!< [20..16] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 10.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA11_SEL : 5; /*!< [28..24] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 11.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + } DMA_REQ_MUX3_REG_b; + }; + + union + { + __IOM uint32_t DMA_REQ_MUX4_REG; /*!< (@ 0x0000020C) DMA channel assignments (Channel 12~15) */ + + struct + { + __IOM uint32_t DMA12_SEL : 5; /*!< [4..0] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 12.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA13_SEL : 5; /*!< [12..8] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 13.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA14_SEL : 5; /*!< [20..16] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 14.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + __IOM uint32_t DMA15_SEL : 5; /*!< [28..24] Select which peripheral is mapped on the DMA channel.Here, + * the DMA request is mapped on channel 15.See DMA0_SEL for + * the peripherals' mapping. */ + uint32_t : 3; + } DMA_REQ_MUX4_REG_b; + }; + + union + { + __IOM uint32_t DMA_INT_STATUS_REG; /*!< (@ 0x00000210) DMA interrupt status register */ + + struct + { + __IM uint32_t DMA_IRQ_CH0 : 1; /*!< [0..0] 0 = IRQ on channel 0 is not set1 = IRQ on channel 0 is + * set */ + __IM uint32_t DMA_IRQ_CH1 : 1; /*!< [1..1] 0 = IRQ on channel 1 is not set1 = IRQ on channel 1 is + * set */ + __IM uint32_t DMA_IRQ_CH2 : 1; /*!< [2..2] 0 = IRQ on channel 2 is not set1 = IRQ on channel 2 is + * set */ + __IM uint32_t DMA_IRQ_CH3 : 1; /*!< [3..3] 0 = IRQ on channel 3 is not set1 = IRQ on channel 3 is + * set */ + __IM uint32_t DMA_IRQ_CH4 : 1; /*!< [4..4] 0 = IRQ on channel 4 is not set1 = IRQ on channel 4 is + * set */ + __IM uint32_t DMA_IRQ_CH5 : 1; /*!< [5..5] 0 = IRQ on channel 5 is not set1 = IRQ on channel 5 is + * set */ + __IM uint32_t DMA_IRQ_CH6 : 1; /*!< [6..6] 0 = IRQ on channel 6 is not set1 = IRQ on channel 6 is + * set */ + __IM uint32_t DMA_IRQ_CH7 : 1; /*!< [7..7] 0 = IRQ on channel 7 is not set1 = IRQ on channel 7 is + * set */ + __IM uint32_t DMA_IRQ_CH8 : 1; /*!< [8..8] 0 = IRQ on channel 8 is not set1 = IRQ on channel 8 is + * set */ + __IM uint32_t DMA_IRQ_CH9 : 1; /*!< [9..9] 0 = IRQ on channel 9 is not set1 = IRQ on channel 9 is + * set */ + __IM uint32_t DMA_IRQ_CH10 : 1; /*!< [10..10] 0 = IRQ on channel 10 is not set1 = IRQ on channel + * 10 is set */ + __IM uint32_t DMA_IRQ_CH11 : 1; /*!< [11..11] 0 = IRQ on channel 11 is not set1 = IRQ on channel + * 11 is set */ + __IM uint32_t DMA_IRQ_CH12 : 1; /*!< [12..12] 0 = IRQ on channel 12 is not set1 = IRQ on channel + * 12 is set */ + __IM uint32_t DMA_IRQ_CH13 : 1; /*!< [13..13] 0 = IRQ on channel 13 is not set1 = IRQ on channel + * 13 is set */ + __IM uint32_t DMA_IRQ_CH14 : 1; /*!< [14..14] 0 = IRQ on channel 14 is not set1 = IRQ on channel + * 14 is set */ + __IM uint32_t DMA_IRQ_CH15 : 1; /*!< [15..15] 0 = IRQ on channel 15 is not set1 = IRQ on channel + * 15 is set */ + __IM uint32_t DMA_BUS_ERR0 : 1; /*!< [16..16] 0 = No bus error response is detected for channel 01 + * = Bus error response detected for channel 0NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR1 : 1; /*!< [17..17] 0 = No bus error response is detected for channel 11 + * = Bus error response detected for channel 1NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR2 : 1; /*!< [18..18] 0 = No bus error response is detected for channel 21 + * = Bus error response detected for channel 2NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR3 : 1; /*!< [19..19] 0 = No bus error response is detected for channel 31 + * = Bus error response detected for channel 3NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR4 : 1; /*!< [20..20] 0 = No bus error response is detected for channel 41 + * = Bus error response detected for channel 4NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR5 : 1; /*!< [21..21] 0 = No bus error response is detected for channel 51 + * = Bus error response detected for channel 5NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR6 : 1; /*!< [22..22] 0 = No bus error response is detected for channel 61 + * = Bus error response detected for channel 6NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR7 : 1; /*!< [23..23] 0 = No bus error response is detected for channel 71 + * = Bus error response detected for channel 7NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR8 : 1; /*!< [24..24] 0 = No bus error response is detected for channel 81 + * = Bus error response detected for channel 8NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR9 : 1; /*!< [25..25] 0 = No bus error response is detected for channel 91 + * = Bus error response detected for channel 9NOTE: This bit-field + * is auto-clear and it is initialized to '0' as soon as a + * new transfer is started. */ + __IM uint32_t DMA_BUS_ERR10 : 1; /*!< [26..26] 0 = No bus error response is detected for channel 101 + * = Bus error response detected for channel 10NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + __IM uint32_t DMA_BUS_ERR11 : 1; /*!< [27..27] 0 = No bus error response is detected for channel 111 + * = Bus error response detected for channel 11NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + __IM uint32_t DMA_BUS_ERR12 : 1; /*!< [28..28] 0 = No bus error response is detected for channel 121 + * = Bus error response detected for channel 12NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + __IM uint32_t DMA_BUS_ERR13 : 1; /*!< [29..29] 0 = No bus error response is detected for channel 131 + * = Bus error response detected for channel 13NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + __IM uint32_t DMA_BUS_ERR14 : 1; /*!< [30..30] 0 = No bus error response is detected for channel 141 + * = Bus error response detected for channel 14NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + __IM uint32_t DMA_BUS_ERR15 : 1; /*!< [31..31] 0 = No bus error response is detected for channel 151 + * = Bus error response detected for channel 15NOTE: This + * bit-field is auto-clear and it is initialized to '0' as + * soon as a new transfer is started. */ + } DMA_INT_STATUS_REG_b; + }; + + union + { + __IOM uint32_t DMA_CLEAR_INT_REG; /*!< (@ 0x00000214) DMA clear interrupt register */ + + struct + { + __OM uint32_t DMA_RST_IRQ_CH0 : 1; /*!< [0..0] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 0 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH1 : 1; /*!< [1..1] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 1 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH2 : 1; /*!< [2..2] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 2 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH3 : 1; /*!< [3..3] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 3 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH4 : 1; /*!< [4..4] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 4 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH5 : 1; /*!< [5..5] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 5 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH6 : 1; /*!< [6..6] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 6 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH7 : 1; /*!< [7..7] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 7 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH8 : 1; /*!< [8..8] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 8 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH9 : 1; /*!< [9..9] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 9 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH10 : 1; /*!< [10..10] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 10 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH11 : 1; /*!< [11..11] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 11 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH12 : 1; /*!< [12..12] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 12 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH13 : 1; /*!< [13..13] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 13 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH14 : 1; /*!< [14..14] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 14 ; writing a 0 will have no effect */ + __OM uint32_t DMA_RST_IRQ_CH15 : 1; /*!< [15..15] Writing a 1 will reset the status bit of DMA_INT_STATUS_REG + * for channel 15 ; writing a 0 will have no effect */ + uint32_t : 16; + } DMA_CLEAR_INT_REG_b; + }; + + union + { + __IOM uint32_t DMA_INT_MASK_REG; /*!< (@ 0x00000218) DMA Interrupt mask register */ + + struct + { + __IOM uint32_t DMA_IRQ_ENABLE0 : 1; /*!< [0..0] 0 = disable interrupts on channel 01 = enable interrupts + * on channel 0 */ + __IOM uint32_t DMA_IRQ_ENABLE1 : 1; /*!< [1..1] 0 = disable interrupts on channel 11 = enable interrupts + * on channel 1 */ + __IOM uint32_t DMA_IRQ_ENABLE2 : 1; /*!< [2..2] 0 = disable interrupts on channel 21 = enable interrupts + * on channel 2 */ + __IOM uint32_t DMA_IRQ_ENABLE3 : 1; /*!< [3..3] 0 = disable interrupts on channel 31 = enable interrupts + * on channel 3 */ + __IOM uint32_t DMA_IRQ_ENABLE4 : 1; /*!< [4..4] 0 = disable interrupts on channel 41 = enable interrupts + * on channel 4 */ + __IOM uint32_t DMA_IRQ_ENABLE5 : 1; /*!< [5..5] 0 = disable interrupts on channel 51 = enable interrupts + * on channel 5 */ + __IOM uint32_t DMA_IRQ_ENABLE6 : 1; /*!< [6..6] 0 = disable interrupts on channel 61 = enable interrupts + * on channel 6 */ + __IOM uint32_t DMA_IRQ_ENABLE7 : 1; /*!< [7..7] 0 = disable interrupts on channel 71 = enable interrupts + * on channel 7 */ + __IOM uint32_t DMA_IRQ_ENABLE8 : 1; /*!< [8..8] 0 = disable interrupts on channel 81 = enable interrupts + * on channel 8 */ + __IOM uint32_t DMA_IRQ_ENABLE9 : 1; /*!< [9..9] 0 = disable interrupts on channel 91 = enable interrupts + * on channel 9 */ + __IOM uint32_t DMA_IRQ_ENABLE10 : 1; /*!< [10..10] 0 = disable interrupts on channel 101 = enable interrupts + * on channel 10 */ + __IOM uint32_t DMA_IRQ_ENABLE11 : 1; /*!< [11..11] 0 = disable interrupts on channel 111 = enable interrupts + * on channel 11 */ + __IOM uint32_t DMA_IRQ_ENABLE12 : 1; /*!< [12..12] 0 = disable interrupts on channel 121 = enable interrupts + * on channel 12 */ + __IOM uint32_t DMA_IRQ_ENABLE13 : 1; /*!< [13..13] 0 = disable interrupts on channel 131 = enable interrupts + * on channel 13 */ + __IOM uint32_t DMA_IRQ_ENABLE14 : 1; /*!< [14..14] 0 = disable interrupts on channel 141 = enable interrupts + * on channel 14 */ + __IOM uint32_t DMA_IRQ_ENABLE15 : 1; /*!< [15..15] 0 = disable interrupts on channel 151 = enable interrupts + * on channel 15 */ + uint32_t : 16; + } DMA_INT_MASK_REG_b; + }; +} DMA_Type; /*!< Size = 540 (0x21c) */ + +/* =========================================================================================================================== */ +/* ================ FPLL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief FPLL registers (FPLL) + */ + +typedef struct /*!< (@ 0x400C0300) FPLL Structure */ +{ + union + { + __IOM uint32_t PLLD_FBDIV_REG; /*!< (@ 0x00000000) FPLL feedback divider value register */ + + struct + { + __IOM uint32_t FBDIV : 20; /*!< [19..0] Feedback divider value. The value forms a 20-bit fixed + * point PLL multiplier in 7.13 format. */ + uint32_t : 12; + } PLLD_FBDIV_REG_b; + }; + + union + { + __IOM uint32_t PLLD_CTRL_REG; /*!< (@ 0x00000004) FPLL control register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CLKOUT_EN : 1; /*!< [1..1] PLL Bypass clock (XTAL40M) output enable0: FPLL Bypass + * clock disable1: FPLL Bypass clock enable */ + __IOM uint32_t BYPASS_SEL : 1; /*!< [2..2] This bit has become don't care.For XTAL bypass mode, + * set CLKOUT_EN=0. Set FPLL_EN=0, VCO_EN=0 for power saving, + * see datasheet text */ + __IOM uint32_t PFD_CP_EN : 1; /*!< [3..3] Enable PLL charge pump and PFD0: Disable PFD and charge + * pump1: Enable PFD and charge pump */ + __IOM uint32_t VCO_EN : 1; /*!< [4..4] Enables the PLL VCO0: FPLL VCO disable1: FPLL VCO enable */ + __IOM uint32_t FPLL_EN : 1; /*!< [5..5] FPLL enable0: Disable1: Enable */ + uint32_t : 26; + } PLLD_CTRL_REG_b; + }; + + union + { + __IOM uint32_t PLLD_CONFIG_REG; /*!< (@ 0x00000008) FPLL config register */ + + struct + { + __IOM uint32_t BIAS_HOLD : 1; /*!< [0..0] Controls a leaky pass gate to perform sample and hold + * for noise filtering in VCO0: bias current unfiltered1: + * bias voltage sampled */ + uint32_t : 4; + __IOM uint32_t INDIV : 3; /*!< [7..5] Frequency range of PLL reference clock (MHz)0: 2.5 to + * 51: 5 to 102: Reserved3: 10 to 204: Reserved5: 20 to 406: + * Reserved7: 40 to 54 */ + __IOM uint32_t OUTDIV : 2; /*!< [9..8] Output divider Selector0: gnd1: VCO/22: VCO/43: VCO/8 */ + uint32_t : 22; + } PLLD_CONFIG_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PLLD_STATUS_REG; /*!< (@ 0x00000010) FPLL status register */ + + struct + { + __IM uint32_t STA_RUNNING_AT_XTAL40M : 1; /*!< [0..0] PLL XTAL40M active actual status0: Bypass mode is not + * active1: Bypass mode is active, system clock is supplied + * by oscillator clock */ + __IM uint32_t STA_RUNNING_AT_FPLL : 1; /*!< [1..1] PLL FPLL active actual status0: PLL is not active1: PLL + * is active */ + __IM uint32_t STA_PLL_LOCK : 1; /*!< [2..2] PLL lock actual status0: PLL not in lock1: PLL acquired + * lock */ + uint32_t : 29; + } PLLD_STATUS_REG_b; + }; + + union + { + __IOM uint32_t PLLD_IRQ_REG; /*!< (@ 0x00000014) FPLL IRQ register */ + + struct + { + __IM uint32_t IRQ_PLL_LOST_LOCK : 1; /*!< [0..0] IInterrupt when PLL lost lock to reference clock.0:PLL + * not in lost lock1:PLL lost lock */ + __IM uint32_t IRQ_PLL_LOCK : 1; /*!< [1..1] Interrupt when PLL locked to reference clock0: PLL not + * in lock1: PLL acquired lock */ + uint32_t : 30; + } PLLD_IRQ_REG_b; + }; + + union + { + __IOM uint32_t PLLD_IRQ_CLR_REG; /*!< (@ 0x00000018) FPLL IRQ clear register */ + + struct + { + __IOM uint32_t CLR_IRQ_PLL_LOST_LOCK : 1; /*!< [0..0] 0: -1: Clear IRQ_PLL_LOST_LOCK */ + __IOM uint32_t CLR_IRQ_PLL_LOCK : 1; /*!< [1..1] 0: -1: Clear IRQ_PLL_LOCK */ + uint32_t : 30; + } PLLD_IRQ_CLR_REG_b; + }; + + union + { + __IOM uint32_t PLLD_IRQ_MASK_REG; /*!< (@ 0x0000001C) FPLL IRQ mask register */ + + struct + { + __IOM uint32_t MIRQ_PLL_LOST_LOCK : 1; /*!< [0..0] Mask for PLL lost lock interrupt0: EVT_PLL_LOST_LOCK + * interrupt not masked1: EVT_PLL_LOST_LOCK interrupt masked */ + __IOM uint32_t MIRQ_PLL_LOCK : 1; /*!< [1..1] Mask for PLL lock interrupt0: EVT_PLL_LOCK interrupt + * not masked1: EVT_PLL_LOCK interrupt masked */ + uint32_t : 30; + } PLLD_IRQ_MASK_REG_b; + }; + + union + { + __IOM uint32_t PLLD_TEST_REG; /*!< (@ 0x00000020) PLLD_TEST_REG */ + + struct + { + __IOM uint32_t SDM_ENABLE : 1; /*!< [0..0] SDM_ENABLE */ + __IOM uint32_t SDM_DITHER : 2; /*!< [2..1] SDM_DITHER */ + __IOM uint32_t ANA_TEST_SEL : 1; /*!< [3..3] ANA_TEST_SEL */ + __IOM uint32_t CP_BIAS : 1; /*!< [4..4] CP_BIAS */ + __IOM uint32_t CAL_EN : 1; /*!< [5..5] CAL_EN */ + uint32_t : 26; + } PLLD_TEST_REG_b; + }; + + union + { + __IOM uint32_t PLLD_VCO_TRIM_REG; /*!< (@ 0x00000024) PLLD_VCO_TRIM_REG */ + + struct + { + __IOM uint32_t CAL_VCO : 4; /*!< [3..0] CAL_VCO */ + uint32_t : 28; + } PLLD_VCO_TRIM_REG_b; + }; +} FPLL_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPIO registers (GPIO) + */ + +typedef struct /*!< (@ 0x400B0000) GPIO Structure */ +{ + union + { + __IOM uint32_t P0_DATA_REG; /*!< (@ 0x00000000) P0 Data input / output Register */ + + struct + { + __IOM uint32_t P0_DATA : 14; /*!< [13..0] Set P0 output register when written; Returns the value + * of P0 port when read */ + uint32_t : 18; + } P0_DATA_REG_b; + }; + + union + { + __IOM uint32_t P1_DATA_REG; /*!< (@ 0x00000004) P1 Data input / output Register */ + + struct + { + __IOM uint32_t P1_DATA : 16; /*!< [15..0] Set P1 output register when written; Returns the value + * of P1 port when read */ + uint32_t : 16; + } P1_DATA_REG_b; + }; + + union + { + __IOM uint32_t SW_DATA_REG; /*!< (@ 0x00000008) SW Data input / output Register */ + + struct + { + __IOM uint32_t SWD_DATA : 2; /*!< [1..0] Set SWD_[y] output register when written; Returns the + * value of SWD_[y] port when read */ + uint32_t : 30; + } SW_DATA_REG_b; + }; + + union + { + __IOM uint32_t P0_SET_DATA_REG; /*!< (@ 0x0000000C) P0 Set port pins Register */ + + struct + { + __OM uint32_t P0_SET : 14; /*!< [13..0] Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded;Reading + * returns 0 */ + uint32_t : 18; + } P0_SET_DATA_REG_b; + }; + + union + { + __IOM uint32_t P1_SET_DATA_REG; /*!< (@ 0x00000010) P1 Set port pins Register */ + + struct + { + __OM uint32_t P1_SET : 16; /*!< [15..0] Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded;Reading + * returns 0 */ + uint32_t : 16; + } P1_SET_DATA_REG_b; + }; + + union + { + __IOM uint32_t SW_SET_DATA_REG; /*!< (@ 0x00000014) SW Set port pins Register */ + + struct + { + __OM uint32_t SWD_SET : 2; /*!< [1..0] Writing a 1 to SWD_[y] sets SWD_[y] to 1. Writing 0 is + * discarded;Reading returns 0 */ + uint32_t : 30; + } SW_SET_DATA_REG_b; + }; + + union + { + __IOM uint32_t P0_RESET_DATA_REG; /*!< (@ 0x00000018) P0 Reset port pins Register */ + + struct + { + __OM uint32_t P0_RESET : 14; /*!< [13..0] Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded;Reading + * returns 0 */ + uint32_t : 18; + } P0_RESET_DATA_REG_b; + }; + + union + { + __IOM uint32_t P1_RESET_DATA_REG; /*!< (@ 0x0000001C) P1 Reset port pins Register */ + + struct + { + __OM uint32_t P1_RESET : 16; /*!< [15..0] Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded;Reading + * returns 0 */ + uint32_t : 16; + } P1_RESET_DATA_REG_b; + }; + + union + { + __IOM uint32_t SW_RESET_DATA_REG; /*!< (@ 0x00000020) SW Reset port pins Register */ + + struct + { + __OM uint32_t SWD_RESET : 2; /*!< [1..0] Writing a 1 to SWD_[y] sets SWD_[y] to 0. Writing 0 is + * discarded;Reading returns 0 */ + uint32_t : 30; + } SW_RESET_DATA_REG_b; + }; + + union + { + __IOM uint32_t P0_00_MODE_REG; /*!< (@ 0x00000024) P0_00 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] 0: GPIO (I/O)1: UART_RX (IA)2: UART_TX (OA)3: UART_CTSN + * (IA)4: UART_RTSN (OA)5: UART_TXDOE (OA)6: UART1_RX (IA)7: + * UART1_TX (OA)8: UART1_CTSN (IA)9: UART1_RTSN (OA)10: UART1_TXDOE + * (OA)11: UART2_RX (IA)12: UART2_TX (OA)13: UART2_CTSN (IA)14: + * UART2_RTSN (OA)15: UART2_TXDOE (OA)16: SPI_DI (IA)17: SPI_DO + * (OA)18: SPI_CLK (I/O)19: SPI_CSN0 (I/O)20: SPI_CSN1 (OA)21: + * SPI2_DI (IA)22: SPI2_DO (OA)23: SPI2_CLK (I/O)24: SP */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_00_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_01_MODE_REG; /*!< (@ 0x00000028) P0_01 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_01_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_02_MODE_REG; /*!< (@ 0x0000002C) P0_02 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selectedIn + * ADC mode, these bits are don't care */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_02_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_03_MODE_REG; /*!< (@ 0x00000030) P0_03 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_03_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_04_MODE_REG; /*!< (@ 0x00000034) P0_04 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_04_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_05_MODE_REG; /*!< (@ 0x00000038) P0_05 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_05_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_06_MODE_REG; /*!< (@ 0x0000003C) P0_06 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_06_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_07_MODE_REG; /*!< (@ 0x00000040) P0_07 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_07_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_08_MODE_REG; /*!< (@ 0x00000044) P0_08 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selectedIn + * ADC mode, these bits are don't care. */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_08_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_09_MODE_REG; /*!< (@ 0x00000048) P0_09 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_09_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_10_MODE_REG; /*!< (@ 0x0000004C) P0_10 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_10_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_11_MODE_REG; /*!< (@ 0x00000050) P0_11 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_11_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_12_MODE_REG; /*!< (@ 0x00000054) P0_12 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_12_MODE_REG_b; + }; + + union + { + __IOM uint32_t P0_13_MODE_REG; /*!< (@ 0x00000058) P0_13 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P0_13_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_00_MODE_REG; /*!< (@ 0x0000005C) P1_00 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_00_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_01_MODE_REG; /*!< (@ 0x00000060) P1_01 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_01_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_02_MODE_REG; /*!< (@ 0x00000064) P1_02 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_02_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_03_MODE_REG; /*!< (@ 0x00000068) P1_03 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_03_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_04_MODE_REG; /*!< (@ 0x0000006C) P1_04 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_04_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_05_MODE_REG; /*!< (@ 0x00000070) P1_05 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_05_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_06_MODE_REG; /*!< (@ 0x00000074) P1_06 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_06_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_07_MODE_REG; /*!< (@ 0x00000078) P1_07 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_07_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_08_MODE_REG; /*!< (@ 0x0000007C) P1_08 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_08_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_09_MODE_REG; /*!< (@ 0x00000080) P1_09 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_09_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_10_MODE_REG; /*!< (@ 0x00000084) P1_10 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_10_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_11_MODE_REG; /*!< (@ 0x00000088) P1_11 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_11_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_12_MODE_REG; /*!< (@ 0x0000008C) P1_12 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_12_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_13_MODE_REG; /*!< (@ 0x00000090) P1_13 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_13_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_14_MODE_REG; /*!< (@ 0x00000094) P1_14 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selectedIn + * ADC mode, these bits are don't care. */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_14_MODE_REG_b; + }; + + union + { + __IOM uint32_t P1_15_MODE_REG; /*!< (@ 0x00000098) P1_15 Mode Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } P1_15_MODE_REG_b; + }; + + union + { + __IOM uint32_t SW0_MODE_REG; /*!< (@ 0x0000009C) SWCLK pin Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } SW0_MODE_REG_b; + }; + + union + { + __IOM uint32_t SW1_MODE_REG; /*!< (@ 0x000000A0) SWDIO Data Register */ + + struct + { + __IOM uint32_t PID : 7; /*!< [6..0] See P0_00_MODE_REG[PID] */ + uint32_t : 1; + __IOM uint32_t PUPD : 2; /*!< [9..8] 00: Input, no resistors selected01: Input, pull-up selected10: + * Input, pull-down selected11: Output, no resistors selected */ + __IOM uint32_t PPOD : 1; /*!< [10..10] 0: Push pull1: Open drain */ + __IOM uint32_t IS : 1; /*!< [11..11] Standard PAD input selection0: CMOS input1: Schmitt + * input */ + __IOM uint32_t DS : 2; /*!< [13..12] Standard PAD drive strength0: 2 mA1: 4 mA2: 8 mA3: + * 14 mA */ + __IOM uint32_t SR : 1; /*!< [14..14] Standard PAD slew rate control0: fast slew rate1: slow + * slew rate */ + __IOM uint32_t POE : 1; /*!< [15..15] Standard PAD Parametric Output control, parametric + * inverted data0: disable1: enable */ + uint32_t : 16; + } SW1_MODE_REG_b; + }; + + union + { + __IOM uint32_t GPIO_CLK_SEL_REG; /*!< (@ 0x000000A4) Select which clock to map on ports P0/P1 */ + + struct + { + __IOM uint32_t FUNC_CLOCK_SEL : 3; /*!< [2..0] Select which clock to map when PID = FUNC_CLOCK.0x1 : + * xtal40m0x2 : rc10m0x3 : xtal32k0x4 : osc32k0x5 : fpll98m0x6 + * : dpll480m0x7 : divn_clkothers : Reserved */ + __IOM uint32_t FUNC_CLOCK_EN : 1; /*!< [3..3] If set, it enables the mapping of the selected clock + * signal, according to FUNC_CLOCK_SEL bit-field. */ + __IOM uint32_t XTAL40M_OUTPUT_EN : 1; /*!< [4..4] XTAL40M_CLK output enable bit-field. When set, it enables + * the mapping of xtal40m clock on dedicated GPIO (P0_11). + * The specific GPIO must be configured as GPIO output. */ + __IOM uint32_t RC10M_OUTPUT_EN : 1; /*!< [5..5] RC10M_CLK output enable bit-field. When set, it enables + * the mapping of rc10m clock on dedicated GPIO (P0_09). The + * specific GPIO must be configured as GPIO output. */ + __IOM uint32_t XTAL32K_OUTPUT_EN : 1; /*!< [6..6] XTAL32K output enable bit-field. When set, it enables + * the mapping of xtal32k clock on dedicated GPIO (P0_08). + * The specific GPIO must be configured as GPIO output. */ + __IOM uint32_t OSC32K_OUTPUT_EN : 1; /*!< [7..7] OSC32K output enable bit-field. When set, it enables + * the mapping of osc32k clock on dedicated GPIO (P0_12). + * The specific GPIO must be configured as GPIO output. */ + __IOM uint32_t FPLL98M_OUTPUT_EN : 1; /*!< [8..8] FPLL98M output enable bit-field. When set, it enables + * the mapping of fpll98m clock on dedicated GPIO (P0_10). + * The specific GPIO must be configured as GPIO output. */ + __IOM uint32_t DPLL480M_OUTPUT_EN : 1; /*!< [9..9] DPLL480M output enable bit-field. When set, it enables + * the mapping of dpll480m clock on dedicated GPIO (P0_13). + * The specific GPIO must be configured as GPIO output. */ + __IOM uint32_t MCLK_OUTPUT_EN : 1; /*!< [10..10] MCLK output enable bit-field. When set, it enables + * the mapping of MCLK clock on dedicated GPIO (P1_11). The + * specific GPIO must be configured as GPIO output. */ + uint32_t : 21; + } GPIO_CLK_SEL_REG_b; + }; + + union + { + __IOM uint32_t EMMC_MODE_REG; /*!< (@ 0x000000A8) OQSPI PAD control Register */ + + struct + { + __IOM uint32_t EMMC_ENABLE : 1; /*!< [0..0] EMMC / GPIO PADs Mode enable0: GPIO mode (default)1: + * eMMC mode with {P1_[3:0], P1_[15:10]} or P0_[13:4] */ + __IOM uint32_t EMMC_PORT_SEL : 1; /*!< [1..1] eMMC Port selection when set to high SDIO_ENABLE0: eMMC + * Port P0_[13:4]1: eMMC Port P1_[3:0] and P1_[15:10] (default) */ + __IOM uint32_t EMMC_OCTA_MODE : 1; /*!< [2..2] EMMC Octa Mode enable0: eMMC Quad mode (default)1: eMMC + * Octa mode with P1_[3:0] or P0_[7:4] */ + __IOM uint32_t EMMC_CD_SEL : 1; /*!< [3..3] EMMC Card Detect selection0: CD signal from register + * set value1: CD signal from PIN */ + __IOM uint32_t EMMC_WP_SEL : 1; /*!< [4..4] EMMC Write Protect selection0: WP signal from register + * set value1: WP signal from PIN */ + __IOM uint32_t EMMC_CD_VAL : 1; /*!< [5..5] EMMC Card Detect value */ + __IOM uint32_t EMMC_WP_VAL : 1; /*!< [6..6] EMMC Write Protect value */ + __IOM uint32_t EMMC_CLKIN_SEL : 1; /*!< [7..7] EMMC rxclk_in selection0: clkout signal1: clkout_inv + * signal */ + __IOM uint32_t EMMC_PULL_EN : 10; /*!< [17..8] eMMC PADS Mode Pull Enable1: Pull enalbe0: PUll disablebit[8]: + * eMMC_CLK Padbit[9]: eMMC_CMD Padbit[10]: eMMC_DIO0 Padbit[11]: + * eMMC_DIO1 Padbit[12]: eMMC_DIO2 Padbit[13]: eMMC_DIO3 Padbit[14]: + * eMMC_DIO4 Padbit[15]: eMMC_DIO5 Padbit[16]: eMMC_DIO6 Padbit[17]: + * eMMC_DIO7 Pad */ + uint32_t : 2; + __IOM uint32_t EMMC_PULL_SEL : 10; /*!< [29..20] eMMC PADS Mode Pull Selection1: Pull-Up0: PUll-Downbit[20]: + * eMMC_CLK Padbit[21]: eMMC_CMD Padbit[22]: eMMC_DIO0 Padbit[23]: + * eMMC_DIO1 Padbit[24]: eMMC_DIO2 Padbit[25]: eMMC_DIO3 Padbit[26]: + * eMMC_DIO4 Padbit[27]: eMMC_DIO5 Padbit[28]: eMMC_DIO6 Padbit[29]: + * eMMC_DIO7 Pad */ + uint32_t : 2; + } EMMC_MODE_REG_b; + }; + + union + { + __IOM uint32_t SDIO_MODE_REG; /*!< (@ 0x000000AC) QSPI PAD Control Register */ + + struct + { + __IOM uint32_t SDIO_PAD_ENABLE : 1; /*!< [0..0] SDIO / GPIO PADs Mode enable0: GPIO mode1: SDIO mode */ + __IOM uint32_t SDIO_PORT_SEL : 1; /*!< [1..1] SDIO Port selection when set to high SDIO_ENABLE0: SDIO + * Port P0_[13:8]1: SDIO Port P1_[15:10] */ + __IOM uint32_t CFG_DRV : 2; /*!< [3..2] SDIO PADS Mode drive strength0: 2 mA@ 3.3V1: 4 mA@ 3.3V2: + * 8 mA@ 3.3V3: 14 mA@ 3.3V */ + __IOM uint32_t SDIO_PULL_EN : 6; /*!< [9..4] SDIO PADS Mode Pull Enable1: Pull enalbe0: PUll disablebit[4]: + * SDIO_CLK Padbit[5]: SDIO_CMD Padbit[6]: SDIO_DIO0 Padbit[7]: + * SDIO_DIO1 Padbit[8]: SDIO_DIO2 Padbit[9]: SDIO_DIO3 Pad */ + __IOM uint32_t SDIO_PULL_SEL : 6; /*!< [15..10] SDIO PADS Mode Pull Selection1: Pull-Up0: PUll-Downbit[10]: + * SDIO_CLK Padbit[11]: SDIO_CMD Padbit[12]: SDIO_DIO0 Padbit[13]: + * SDIO_DIO1 Padbit[14]: SDIO_DIO2 Padbit[15]: SDIO_DIO3 Pad */ + uint32_t : 16; + } SDIO_MODE_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GPIO_INT_SEL_P0_REG; /*!< (@ 0x000000C0) select which inputs from P0 port can trigger + * wkup counter */ + + struct + { + __IOM uint32_t GPIO_SELECT_P0 : 14; /*!< [13..0] 0: input P0_xx is not enabled for wakeup event1: input + * P0_xx is enabled for wakeup event */ + uint32_t : 18; + } GPIO_INT_SEL_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_SEL_P1_REG; /*!< (@ 0x000000C4) select which inputs from P1 port can trigger + * wkup counter */ + + struct + { + __IOM uint32_t GPIO_SELECT_P1 : 16; /*!< [15..0] 0: input P1_xx is not enabled for wakeup event1: input + * P1_xx is enabled for wakeup event */ + uint32_t : 16; + } GPIO_INT_SEL_P1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_POL_P0_REG; /*!< (@ 0x000000C8) select the sesitivity polarity for each P0 input */ + + struct + { + __IOM uint32_t GPIO_POL_P0 : 14; /*!< [13..0] 0: enabled input P0_xx will give an event if that input + * goes high1: enabled input P0_xx will give an event if that + * input goes low */ + uint32_t : 18; + } GPIO_INT_POL_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_POL_P1_REG; /*!< (@ 0x000000CC) select the sesitivity polarity for each P1 input */ + + struct + { + __IOM uint32_t GPIO_POL_P1 : 16; /*!< [15..0] 0: enabled input P1_xx will give an event if that input + * goes high1: enabled input P1_xx will give an event if that + * input goes low */ + uint32_t : 16; + } GPIO_INT_POL_P1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_STS_P0_REG; /*!< (@ 0x000000D0) Event status register for P0 */ + + struct + { + __IM uint32_t GPIO_STAT_P0 : 14; /*!< [13..0] Contains the latched value of any toggle of the GPIOs + * Port P0. WKUP_STAT_P0[0] -> P0_00. */ + uint32_t : 18; + } GPIO_INT_STS_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_STS_P1_REG; /*!< (@ 0x000000D4) Event status register for P1 */ + + struct + { + __IM uint32_t GPIO_STAT_P1 : 16; /*!< [15..0] Contains the latched value of any toggle of the GPIOs + * Port P1. WKUP_STAT_P1[0] -> P1_00. */ + uint32_t : 16; + } GPIO_INT_STS_P1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_CLR_P0_REG; /*!< (@ 0x000000D8) Clear event register for P0 */ + + struct + { + __OM uint32_t GPIO_CLEAR_P0 : 14; /*!< [13..0] Clear latched value of the GPIOs P0 when corresponding + * bit is 1 */ + uint32_t : 18; + } GPIO_INT_CLR_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_INT_CLR_P1_REG; /*!< (@ 0x000000DC) Clear event register for P1 */ + + struct + { + __OM uint32_t GPIO_CLEAR_P1 : 16; /*!< [15..0] Clear latched value of the GPIOs P1 when corresponding + * bit is 1 */ + uint32_t : 16; + } GPIO_INT_CLR_P1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_SEL_P0_REG; /*!< (@ 0x000000E0) Enable fast wakeup and enable GPIO_P0_IRQ */ + + struct + { + __IOM uint32_t GPIO_SEL_P0 : 14; /*!< [13..0] 0:No GPIO_P0_IRQ on input P0_x.Fast wakeup is not enabled + * if the corresponding WKUP_SEL1_GPIO_P0_REG[x] is 0 too.1:GPIO_P0_IRQ + * will be generated on P0_x input event. If WKUP_SEL1_GPIO_P0_REG[x] + * is 0, IRQ generation is level sensitive. If WKUP_SEL1_GPIO_P0_REG[x] + * is 1, IRQ generation is edge sensitive (only if there is + * a change on P0_x input).Fast wakeup from the corresponding + * P0_x input is enabled. */ + uint32_t : 18; + } GPIO_SEL_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_SEL_P1_REG; /*!< (@ 0x000000E4) Enable fast wakeup and enable GPIO_P1_IRQ */ + + struct + { + __IOM uint32_t GPIO_SEL_P1 : 16; /*!< [15..0] 0:No GPIO_P1_IRQ on input P1_x.Fast wakeup is not enabled + * if the corresponding WKUP_SEL1_GPIO_P1_REG[x] is 0 too.1:GPIO_P1_IRQ + * will be generated on P1_x input event. If WKUP_SEL1_GPIO_P1_REG[x] + * is 0, IRQ generation is level sensitive. If WKUP_SEL1_GPIO_P1_REG[x] + * is 1, IRQ generation is edge sensitive (only if there is + * a change on P1_x input).Fast wakeup from the corresponding + * P1_x input is enabled. */ + uint32_t : 16; + } GPIO_SEL_P1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_SEL1_P0_REG; /*!< (@ 0x000000E8) Configure to generate level or edge sensitive + * IRQ on P0 events */ + + struct + { + __IOM uint32_t GPIO_SEL1_P0 : 14; /*!< [13..0] 0 (level sensitive):If WKUP_SEL_GPIO_P0_REG[x] is 1, + * generate GPIO_P0_IRQ based on P0_x level.Fast wakeup is + * not enabled if the corresponding WKUP_SEL_GPIO_P0_REG[x] + * is 0 too.1 (edge sensitive):If WKUP_SEL_GPIO_P0_REG[x] + * is 1, GPIO_P0_IRQ will be generated only on rising/falling + * (defined by WKUP_POL_P0_REG) edge on P0_x.Fast wakeup from + * the corresponding P0_x input is enabled. */ + uint32_t : 18; + } GPIO_SEL1_P0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_SEL1_P1_REG; /*!< (@ 0x000000EC) Configure to generate level or edge sensitive + * IRQ on P1 events */ + + struct + { + __IOM uint32_t GPIO_SEL1_P1 : 16; /*!< [15..0] 0 (level sensitive):If WKUP_SEL_GPIO_P1_REG[x] is 1, + * generate GPIO_P1_IRQ based on P1_x level.Fast wakeup is + * not enabled if the corresponding WKUP_SEL_GPIO_P1_REG[x] + * is 0 too.1 (edge sensitive):If WKUP_SEL_GPIO_P1_REG[x] + * is 1, GPIO_P1_IRQ will be generated only on rising/falling + * (defined by WKUP_POL_P1_REG) edge on P1_x.Fast wakeup from + * the corresponding P1_x input is enabled. */ + uint32_t : 16; + } GPIO_SEL1_P1_REG_b; + }; + __IM uint32_t RESERVED1[68]; + + union + { + __IOM uint32_t BIST_CTRL_REG; /*!< (@ 0x00000200) BIST_CTRL_REG */ + + struct + { + __IOM uint32_t BIST_CONFIG : 2; /*!< [1..0] BIST_CONFIG */ + __IOM uint32_t RAM_BIST_PATTERN : 2; /*!< [3..2] RAM_BIST_PATTERN */ + __IOM uint32_t RAMBIST_REPEAT : 1; /*!< [4..4] RAMBIST_REPEAT */ + __IOM uint32_t FAST_ADDRESS : 1; /*!< [5..5] FAST_ADDRESS */ + __IOM uint32_t ADDRESS_SCRAMBLING : 1; /*!< [6..6] ADDRESS_SCRAMBLING */ + __IOM uint32_t SHOW_BIST : 1; /*!< [7..7] SHOW_BIST */ + uint32_t : 24; + } BIST_CTRL_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_ENABLE1_REG; /*!< (@ 0x00000204) RAMBIST_ENABLE1_REG */ + + struct + { + __IOM uint32_t MROM_BIST_ENABLE : 1; /*!< [0..0] MROM_BIST_ENABLE */ + __IOM uint32_t SYSRAM0_BIST_ENABLE : 1; /*!< [1..1] SYSRAM0_BIST_ENABLE */ + __IOM uint32_t SYSRAM1_BIST_ENABLE : 1; /*!< [2..2] SYSRAM1_BIST_ENABLE */ + __IOM uint32_t SYSRAM2_BIST_ENABLE : 1; /*!< [3..3] SYSRAM2_BIST_ENABLE */ + __IOM uint32_t SYSRAM3_BIST_ENABLE : 1; /*!< [4..4] SYSRAM3_BIST_ENABLE */ + __IOM uint32_t SYSRAM4_BIST_ENABLE : 1; /*!< [5..5] SYSRAM4_BIST_ENABLE */ + __IOM uint32_t SYSRAM5_BIST_ENABLE : 1; /*!< [6..6] SYSRAM5_BIST_ENABLE */ + __IOM uint32_t RETMEM_BIST_ENABLE : 1; /*!< [7..7] RETMEM_BIST_ENABLE */ + __IOM uint32_t AGCRAM_BIST_ENABLE : 1; /*!< [8..8] AGCRAM_BIST_ENABLE */ + __IOM uint32_t CC312RAM_BIST_ENABLE : 1; /*!< [9..9] CC312RAM_BIST_ENABLE */ + __IOM uint32_t KEYSTG0_BIST_ENABLE : 1; /*!< [10..10] KEYSTG0_BIST_ENABLE */ + __IOM uint32_t KEYSTG1_BIST_ENABLE : 1; /*!< [11..11] KEYSTG1_BIST_ENABLE */ + __IOM uint32_t MIBRAM_BIST_ENABLE : 1; /*!< [12..12] MIBRAM_BIST_ENABLE */ + __IOM uint32_t MACTX_BIST_ENABLE : 1; /*!< [13..13] MACTX_BIST_ENABLE */ + __IOM uint32_t MACRX_BIST_ENABLE : 1; /*!< [14..14] MACRX_BIST_ENABLE */ + __IOM uint32_t SBOXRAM_BIST_ENABLE : 1; /*!< [15..15] SBOXRAM_BIST_ENABLE */ + __IOM uint32_t MPIFTX_BIST_ENABLE : 1; /*!< [16..16] MPIFTX_BIST_ENABLE */ + __IOM uint32_t MPIFRX_BIST_ENABLE : 1; /*!< [17..17] MPIFRX_BIST_ENABLE */ + __IOM uint32_t LDPCTX_BIST_ENABLE : 1; /*!< [18..18] LDPCTX_BIST_ENABLE */ + __IOM uint32_t BFMEE_BIST_ENABLE : 1; /*!< [19..19] BFMEE_BIST_ENABLE */ + __IOM uint32_t RADAR_BIST_ENABLE : 1; /*!< [20..20] RADAR_BIST_ENABLE */ + __IOM uint32_t FFTMEM0_BIST_ENABLE : 1; /*!< [21..21] FFTMEM0_BIST_ENABLE */ + __IOM uint32_t FFTMEM1_BIST_ENABLE : 1; /*!< [22..22] FFTMEM1_BIST_ENABLE */ + __IOM uint32_t FFTMEM2_BIST_ENABLE : 1; /*!< [23..23] FFTMEM2_BIST_ENABLE */ + __IOM uint32_t FFTMEM3_BIST_ENABLE : 1; /*!< [24..24] FFTMEM3_BIST_ENABLE */ + __IOM uint32_t FFTMEM4_BIST_ENABLE : 1; /*!< [25..25] FFTMEM4_BIST_ENABLE */ + __IOM uint32_t FFTMEM5_BIST_ENABLE : 1; /*!< [26..26] FFTMEM5_BIST_ENABLE */ + __IOM uint32_t FFTMEM6_BIST_ENABLE : 1; /*!< [27..27] FFTMEM6_BIST_ENABLE */ + __IOM uint32_t LDPC0_CR_BIST_ENABLE : 1; /*!< [28..28] LDPC0_CR_BIST_ENABLE */ + __IOM uint32_t LDPC0_VR_BIST_ENABLE : 1; /*!< [29..29] LDPC0_VR_BIST_ENABLE */ + __IOM uint32_t LDPC0_VMX10_BIST_ENABLE : 1; /*!< [30..30] LDPC0_VMX10_BIST_ENABLE */ + __IOM uint32_t LDPC0_VMX32_BIST_ENABLE : 1; /*!< [31..31] LDPC0_VMX32_BIST_ENABLE */ + } RAMBIST_ENABLE1_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_ENABLE2_REG; /*!< (@ 0x00000208) RAMBIST_ENABLE2_REG */ + + struct + { + __IOM uint32_t LDPC0_VMX54_BIST_ENABLE : 1; /*!< [0..0] LDPC0_VMX54_BIST_ENABLE */ + __IOM uint32_t LDPC0_VMY10_BIST_ENABLE : 1; /*!< [1..1] LDPC0_VMY10_BIST_ENABLE */ + __IOM uint32_t LDPC0_VMY32_BIST_ENABLE : 1; /*!< [2..2] LDPC0_VMY32_BIST_ENABLE */ + __IOM uint32_t LDPC0_VMY54_BIST_ENABLE : 1; /*!< [3..3] LDPC0_VMY54_BIST_ENABLE */ + __IOM uint32_t LDPC0_HDXY_BIST_ENABLE : 1; /*!< [4..4] LDPC0_HDXY_BIST_ENABLE */ + __IOM uint32_t BDFD1_RAM_BIST_ENABLE : 1; /*!< [5..5] BDFD1_RAM_BIST_ENABLE */ + __IOM uint32_t EMMCRAM_BIST_ENABLE : 1; /*!< [6..6] EMMCRAM_BIST_ENABLE */ + __IOM uint32_t SDIO_RAM_BIST_ENABLE : 1; /*!< [7..7] SDIO_RAM_BIST_ENABLE */ + __IOM uint32_t CACHE_MEM10_BIST_ENABLE : 1; /*!< [8..8] CACHE_MEM10_BIST_ENABLE */ + __IOM uint32_t DCACHE_DATA_RAM_BIST_ENABLE : 1; /*!< [9..9] DCACHE_DATA_RAM_BIST_ENABLE */ + __IOM uint32_t DCACHE_TAG_RAM_BIST_ENABLE : 1; /*!< [10..10] DCACHE_TAG_RAM_BIST_ENABLE */ + uint32_t : 21; + } RAMBIST_ENABLE2_REG_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t RAMBIST_STATUS1_REG; /*!< (@ 0x00000210) RAMBIST_STATUS1_REG */ + + struct + { + __IM uint32_t RAM_GRP1_BIST_BUSY : 32; /*!< [31..0] RAM_GRP1_BIST_BUSY */ + } RAMBIST_STATUS1_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_STATUS2_REG; /*!< (@ 0x00000214) RAMBIST_STATUS2_REG */ + + struct + { + __IM uint32_t RAM_GRP2_BIST_BUSY : 32; /*!< [31..0] RAM_GRP2_BIST_BUSY */ + } RAMBIST_STATUS2_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_STATUS3_REG; /*!< (@ 0x00000218) RAMBIST_STATUS3_REG */ + + struct + { + __IM uint32_t RAM_GRP3_BIST_BUSY : 4; /*!< [3..0] RAM_GRP3_BIST_BUSY */ + uint32_t : 28; + } RAMBIST_STATUS3_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_RESULT1_REG; /*!< (@ 0x0000021C) RAMBIST_RESULT1_REG */ + + struct + { + __IM uint32_t RAM_GRP1_BIST_FAIL : 32; /*!< [31..0] RAM_GRP1_BIST_FAIL */ + } RAMBIST_RESULT1_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_RESULT2_REG; /*!< (@ 0x00000220) RAMBIST_RESULT2_REG */ + + struct + { + __IM uint32_t RAM_GRP2_BIST_FAIL : 32; /*!< [31..0] RAM_GRP2_BIST_FAIL */ + } RAMBIST_RESULT2_REG_b; + }; + + union + { + __IOM uint32_t RAMBIST_RESULT3_REG; /*!< (@ 0x00000224) RAMBIST_RESULT3_REG */ + + struct + { + __IM uint32_t RAM_GRP3_BIST_FAIL : 4; /*!< [3..0] RAM_GRP3_BIST_FAIL */ + uint32_t : 28; + } RAMBIST_RESULT3_REG_b; + }; + + union + { + __IOM uint32_t ROMBIST_RESULT_REG; /*!< (@ 0x00000228) ROMBIST_RESULT_REG */ + + struct + { + __IM uint32_t ROMBIST_RESULT : 32; /*!< [31..0] ROMBIST_RESULT */ + } ROMBIST_RESULT_REG_b; + }; + + union + { + __IOM uint32_t TEST_CTRL_REG; /*!< (@ 0x0000022C) TEST_CTRL_REG */ + + struct + { + __IOM uint32_t SHOW_CLOCKS : 1; /*!< [0..0] SHOW_CLOCKS */ + __IOM uint32_t RFPT_ENABLE : 1; /*!< [1..1] RFPT_ENABLE */ + __IOM uint32_t RTC_MONITOR_EN : 1; /*!< [2..2] RTC_MONITOR_EN */ + __IOM uint32_t IQADC_TEST_EN : 1; /*!< [3..3] IQADC_TEST_EN */ + __IOM uint32_t IQDAC_TEST_EN : 1; /*!< [4..4] IQDAC_TEST_EN */ + __IOM uint32_t AUXADC_TEST_EN : 1; /*!< [5..5] AUXADC_TEST_EN */ + __IOM uint32_t RFMON_TBUS_SEL : 2; /*!< [7..6] RFMON_TBUS_SEL */ + __IOM uint32_t RTC_SCAN_TEST_EN : 1; /*!< [8..8] RTC_SCAN_TEST_EN */ + __IOM uint32_t ADCSEN_SCAN_TEST_EN : 1; /*!< [9..9] ADCSEN_SCAN_TEST_EN */ + __IOM uint32_t LD_SCAN_TEST_EN : 1; /*!< [10..10] LD_SCAN_TEST_EN */ + __IOM uint32_t LOCAL_SCAN_TEST_EN : 1; /*!< [11..11] LOCAL_SCAN_TEST_EN */ + __IOM uint32_t AFC_SCAN_TEST_EN : 1; /*!< [12..12] AFC_SCAN_TEST_EN */ + __IOM uint32_t FILCAL_SCAN_TEST_EN : 1; /*!< [13..13] FILCAL_SCAN_TEST_EN */ + __IOM uint32_t UPSAM_5G0_1_SCAN_TEST_EN : 1; /*!< [14..14] UPSAM_5G0_1_SCAN_TEST_EN */ + __IOM uint32_t UPSAM_5G0_2_SCAN_TEST_EN : 1; /*!< [15..15] UPSAM_5G0_2_SCAN_TEST_EN */ + __IOM uint32_t UPSAM_2G4_1_SCAN_TEST_EN : 1; /*!< [16..16] UPSAM_2G4_1_SCAN_TEST_EN */ + __IOM uint32_t UPSAM_2G4_2_SCAN_TEST_EN : 1; /*!< [17..17] UPSAM_2G4_2_SCAN_TEST_EN */ + __IOM uint32_t POLARTX_SCAN_TEST_EN : 1; /*!< [18..18] POLARTX_SCAN_TEST_EN */ + __IOM uint32_t RF_ONLY_MODE_EN : 1; /*!< [19..19] RF_ONLY_MODE_EN */ + __IOM uint32_t RF_ONLY_MODE_SEL : 1; /*!< [20..20] RF_ONLY_MODE_SEL */ + uint32_t : 11; + } TEST_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TEST_CTRL2_REG; /*!< (@ 0x00000230) TEST_CTRL2_REG */ + + struct + { + __IOM uint32_t SCAN_CONTROL : 6; /*!< [5..0] SCAN_CONTROL */ + uint32_t : 26; + } TEST_CTRL2_REG_b; + }; +} GPIO_Type; /*!< Size = 564 (0x234) */ + +/* =========================================================================================================================== */ +/* ================ GPREG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPREG registers (GPREG) + */ + +typedef struct /*!< (@ 0x40070300) GPREG Structure */ +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t DEBUG_REG; /*!< (@ 0x00000008) Various debug information register. */ + + struct + { + __IOM uint32_t SYS_CPU_FREEZE_EN : 1; /*!< [0..0] 1: Enable Freezing on-chip peripherals (see Note 2) by + * the SYS CPU (ARM CM33).Default '1', freezing of the on-chip + * peripherals is enabled when the Cortex-M33 is halted in + * DEBUG State.If '0', freezing of the on-chip peripherals + * is only depending on [RE]SET_FREEZE_REG except the system + * watchdog timer. The system watchdog timer is always frozen + * when the Cortex-M33 is halted in DEBUG State.Note 1: This + * bit is retained.Note 2: See [RE]SET_FREEZE_REG for the + * specific on-chip peripherals. */ + __IM uint32_t SYS_CPU_IS_HALTED : 1; /*!< [1..1] 1: SYS CPU (ARM CM33) is halted. */ + __IOM uint32_t SYS_CPUWAIT : 1; /*!< [2..2] 1: Stall the processor core out of reset (always after + * a wake-up). Debugger access continue when the core is stalled. + * When set to '0' again the core resumes instruction execution.Note: + * This bit is retained. */ + __IOM uint32_t SYS_CPUWAIT_ON_JTAG : 1; /*!< [3..3] 1: Stall the processor core out of reset (only after + * a wake-up from JTAG). Debugger access continue when the + * core is stalled. When set to '0' again the core resumes + * instruction execution.This feature is independent of the + * PDC (Power Domain Controller) settings. If this bit is + * set and there is SW/JTAG activity during deep sleep, the + * SYS CPU is stalled after the wake-up.Note: This bit is + * retained. */ + __IOM uint32_t ETM_TRACE_MAP_ON_PINS_EN : 1; /*!< [4..4] 1: ETM/TPIU Trace signals mapped on GPIO pins is enabled. */ + uint32_t : 27; + } DEBUG_REG_b; + }; + + union + { + __IOM uint32_t GP_STATUS_REG; /*!< (@ 0x0000000C) General purpose system status register. */ + + struct + { + __IOM uint32_t CAL_PHASE : 1; /*!< [0..0] If '1', it designates that the chip is in Calibration + * Phase i.e. the OTP has been initially programmed but no + * Calibration has occurred. */ + uint32_t : 31; + } GP_STATUS_REG_b; + }; +} GPREG_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ HW_ACC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief HW_ACC registers (HW_ACC) + */ + +typedef struct /*!< (@ 0x40032000) HW_ACC Structure */ +{ + union + { + __IOM uint32_t PRNG_REQ_CLR_REG; /*!< (@ 0x00000000) Clear Request to load the seed value of PRNG, + * active high with auto clear function */ + + struct + { + __OM uint32_t PRNG_REQ_CLR : 1; /*!< [0..0] Clear Request to load the seed value of PRNG, active + * high with auto clear function */ + __OM uint32_t PRNG_REQ_GET : 1; /*!< [1..1] Get Request to obtain a new pseudo-random number in PRNG, + * active high with auto clear function */ + uint32_t : 30; + } PRNG_REQ_CLR_REG_b; + }; + + union + { + __IOM uint32_t PRNG_OP_EN_REG; /*!< (@ 0x00000004) Operation Enable of PRNG */ + + struct + { + __IOM uint32_t PRNG_OP_EN : 1; /*!< [0..0] Operation Enable of PRNG */ + uint32_t : 31; + } PRNG_OP_EN_REG_b; + }; + + union + { + __IOM uint32_t PRNG_PAR_TYPE_REG; /*!< (@ 0x00000008) Parallel Type of PRNG */ + + struct + { + __IOM uint32_t PRNG_PAR_TYPE : 2; /*!< [1..0] Parallel Type of PRNG00 : 8 bits01 : 16 bits10 : 32 bits */ + uint32_t : 30; + } PRNG_PAR_TYPE_REG_b; + }; + + union + { + __IOM uint32_t PRNG_SEED_REG; /*!< (@ 0x0000000C) reverse enable of seed value */ + + struct + { + __IOM uint32_t PRNG_SEED_VAL : 31; /*!< [30..0] seed value of PRNG */ + uint32_t : 1; + } PRNG_SEED_REG_b; + }; + + union + { + __IOM uint32_t PRNG_REG_CAL_VAL; /*!< (@ 0x00000010) PRNG calculation value */ + + struct + { + __IM uint32_t PRNG_CAL_VAL_REG : 32; /*!< [31..0] PRNG_CAL_VAL_REG */ + } PRNG_REG_CAL_VAL_b; + }; + __IM uint32_t RESERVED[59]; + + union + { + __IOM uint32_t CRC_REQ_CTRL_REG; /*!< (@ 0x00000100) Stop Request of CRC Calculation, active high + * with auto clear function */ + + struct + { + __OM uint32_t CRC_REQ_CLR : 1; /*!< [0..0] Clear Request of CRC Calculation, active high with auto + * clear function */ + __OM uint32_t CRC_REQ_START : 1; /*!< [1..1] Start Request of CRC Calculation, active high with auto + * clear function */ + __OM uint32_t CRC_REQ_STOP : 1; /*!< [2..2] Stop Request of CRC Calculation, active high with auto + * clear function */ + uint32_t : 29; + } CRC_REQ_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CRC_OP_EN_REG; /*!< (@ 0x00000104) Operation Enable of CRC Calculation */ + + struct + { + __IOM uint32_t CRC_OP_EN : 1; /*!< [0..0] Operation Enable of CRC Calculation */ + uint32_t : 31; + } CRC_OP_EN_REG_b; + }; + + union + { + __IOM uint32_t CRC_CONFIG_REG; /*!< (@ 0x00000108) Configuration of CRC Calculation Input data */ + + struct + { + __IOM uint32_t CRC_PATH_SEL : 5; /*!< [4..0] Path Selection of CRC Calculation0x00 : OQSPI0x01 : DMA0x02 + * : MAC_DMA0x03 : AHB_SYS */ + uint32_t : 3; + __IOM uint32_t CRC_ACC_TYPE : 1; /*!< [8..8] Access Type of CRC Calculation0 : Read access1 : Write + * access */ + __IOM uint32_t CRC_PAR_TYPE : 2; /*!< [10..9] Parallel Type of CRC Calculation00 : 8 bits01 : 16 bits10 + * : 32 bits */ + uint32_t : 1; + __IOM uint32_t CRC_ENDIAN_TYPE : 1; /*!< [12..12] Bit Endian Type (Reverse Bit)0 : Big Endian (Same In/output)1 + * : Little EndianWhen CRC_PAR_TYPE=0, 0->1->2->3->4->5->6->7When + * CRC_PAR_TYPE=1, 0->1->2->...->13->14->15When CRC_PAR_TYPE=2, + * 0->1->2->...->29->30->31 */ + __IOM uint32_t CRC_SWAP_EN : 1; /*!< [13..13] Input Data Swap Enable0 : Normal1 : Byte Swap */ + uint32_t : 2; + __IOM uint32_t CRC_MST_TYPE : 5; /*!< [20..16] Master Type of CRC Calculation for slave path selection + * in Master Checking Enable0x00 : OQSPI0x01 : DMA0x02 : MAC_DMA0x03 + * : AHB_SYS */ + uint32_t : 3; + __IOM uint32_t CRC_CHK_ADDR : 1; /*!< [24..24] Address Checking Enable of CRC Calculation */ + __IOM uint32_t CRC_CHK_MST : 1; /*!< [25..25] Master Checking Enable of CRC Calculation for slave + * path selection */ + __IOM uint32_t CRC_OP_TYPE : 2; /*!< [27..26] Operation Type of CRC Calculation0 : CRC-321 : CRC-32C2 + * : CRC-16 CCITT3 : CRC-16 IBM */ + uint32_t : 4; + } CRC_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t CRC_SEED_VAL_REG; /*!< (@ 0x0000010C) CRC seed value */ + + struct + { + __IOM uint32_t CRC_SEED_VAL : 32; /*!< [31..0] CRC seed value */ + } CRC_SEED_VAL_REG_b; + }; + + union + { + __IOM uint32_t CRC_ADDR_MIN_REG; /*!< (@ 0x00000110) Minimum address to check the bus address range */ + + struct + { + __IOM uint32_t CRC_ADDR_MIN : 32; /*!< [31..0] Minimum address to check the bus address range */ + } CRC_ADDR_MIN_REG_b; + }; + + union + { + __IOM uint32_t CRC_ADDR_MAX_REG; /*!< (@ 0x00000114) Maximum address to check the bus address range */ + + struct + { + __IOM uint32_t CRC_ADDR_MAX : 32; /*!< [31..0] Maximum address to check the bus address range */ + } CRC_ADDR_MAX_REG_b; + }; + + union + { + __IOM uint32_t CRC_PSEUDO_VAL_REG; /*!< (@ 0x00000118) CRC pseudo value to accumulate manually */ + + struct + { + __IOM uint32_t CRC_PSEUDO_VAL : 32; /*!< [31..0] CRC pseudo value to accumulate manually */ + } CRC_PSEUDO_VAL_REG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CRC_CAL_VAL_REG; /*!< (@ 0x00000120) CRC calculation value */ + + struct + { + __IM uint32_t CRC_CAL_VAL : 32; /*!< [31..0] CRC calculation value */ + } CRC_CAL_VAL_REG_b; + }; + + union + { + __IOM uint32_t CRC_STA_REG; /*!< (@ 0x00000124) Status of CRC Calculation */ + + struct + { + uint32_t : 24; + __IM uint32_t CRC_CAL_STA : 2; /*!< [25..24] Status of CRC Calculation0 : Idle1 : Busy2 : Stop3 + * : Error */ + uint32_t : 6; + } CRC_STA_REG_b; + }; + + union + { + __IOM uint32_t CRC_CAL_VAL_REV_REG; /*!< (@ 0x00000128) CRC calculation reversed value */ + + struct + { + __IM uint32_t CRC_CAL_VAL_REV : 32; /*!< [31..0] CRC calculation reversed value */ + } CRC_CAL_VAL_REV_REG_b; + }; + __IM uint32_t RESERVED2[53]; + + union + { + __IOM uint32_t CRC_1_REQ_CTRL_REG; /*!< (@ 0x00000200) Stop Request of CRC Calculation, active high + * with auto clear function */ + + struct + { + __OM uint32_t CRC_1_REQ_CLR : 1; /*!< [0..0] Clear Request of CRC Calculation, active high with auto + * clear function */ + __OM uint32_t CRC_1_REQ_START : 1; /*!< [1..1] Start Request of CRC Calculation, active high with auto + * clear function */ + __OM uint32_t CRC_1_REQ_STOP : 1; /*!< [2..2] Stop Request of CRC Calculation, active high with auto + * clear function */ + uint32_t : 29; + } CRC_1_REQ_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_OP_EN_REG; /*!< (@ 0x00000204) Operation Enable of CRC Calculation */ + + struct + { + __IOM uint32_t CRC_1_OP_EN : 1; /*!< [0..0] Operation Enable of CRC Calculation */ + uint32_t : 31; + } CRC_1_OP_EN_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_CONFIG_REG; /*!< (@ 0x00000208) Configuration of CRC Calculation Input data */ + + struct + { + __IOM uint32_t CRC_1_PATH_SEL : 5; /*!< [4..0] Path Selection of CRC Calculation0x00 : OQSPI0x01 : DMA0x02 + * : MAC_DMA0x03 : AHB_SYS */ + uint32_t : 3; + __IOM uint32_t CRC_1_ACC_TYPE : 1; /*!< [8..8] Access Type of CRC Calculation0 : Read access1 : Write + * access */ + __IOM uint32_t CRC_1_PAR_TYPE : 2; /*!< [10..9] Parallel Type of CRC Calculation00 : 8 bits01 : 16 bits10 + * : 32 bits */ + uint32_t : 1; + __IOM uint32_t CRC_1_ENDIAN_TYPE : 1; /*!< [12..12] Bit Endian Type (Reverse Bit)0 : Big Endian (Same In/output)1 + * : Little EndianWhen CRC_PAR_TYPE=0, 0->1->2->3->4->5->6->7When + * CRC_PAR_TYPE=1, 0->1->2->...->13->14->15When CRC_PAR_TYPE=2, + * 0->1->2->...->29->30->31 */ + __IOM uint32_t CRC_1_SWAP_EN : 1; /*!< [13..13] Input Data Swap Enable0 : Normal1 : Byte Swap */ + uint32_t : 2; + __IOM uint32_t CRC_1_MST_TYPE : 5; /*!< [20..16] Master Type of CRC Calculation for slave path selection + * in Master Checking Enable0x00 : OQSPI0x01 : DMA0x02 : MAC_DMA0x03 + * : AHB_SYS */ + uint32_t : 3; + __IOM uint32_t CRC_1_CHK_ADDR : 1; /*!< [24..24] Address Checking Enable of CRC Calculation */ + __IOM uint32_t CRC_1_CHK_MST : 1; /*!< [25..25] Master Checking Enable of CRC Calculation for slave + * path selection */ + __IOM uint32_t CRC_1_OP_TYPE : 2; /*!< [27..26] Operation Type of CRC Calculation0 : CRC-321 : CRC-32C2 + * : CRC-16 CCITT3 : CRC-16 IBM */ + uint32_t : 4; + } CRC_1_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_SEED_VAL_REG; /*!< (@ 0x0000020C) CRC seed value */ + + struct + { + __IOM uint32_t CRC_1_SEED_VAL : 32; /*!< [31..0] CRC seed value */ + } CRC_1_SEED_VAL_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_ADDR_MIN_REG; /*!< (@ 0x00000210) Minimum address to check the bus address range */ + + struct + { + __IOM uint32_t CRC_1_ADDR_MIN : 32; /*!< [31..0] Minimum address to check the bus address range */ + } CRC_1_ADDR_MIN_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_ADDR_MAX_REG; /*!< (@ 0x00000214) Maximum address to check the bus address range */ + + struct + { + __IOM uint32_t CRC_1_ADDR_MAX : 32; /*!< [31..0] Maximum address to check the bus address range */ + } CRC_1_ADDR_MAX_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_PSEUDO_VAL_REG; /*!< (@ 0x00000218) CRC pseudo value to accumulate manually */ + + struct + { + __IOM uint32_t CRC_1_PSEUDO_VAL : 32; /*!< [31..0] CRC pseudo value to accumulate manually */ + } CRC_1_PSEUDO_VAL_REG_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t CRC_1_CAL_VAL_REG; /*!< (@ 0x00000220) CRC calculation value */ + + struct + { + __IM uint32_t CRC_1_CAL_VAL : 32; /*!< [31..0] CRC calculation value */ + } CRC_1_CAL_VAL_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_STA_REG; /*!< (@ 0x00000224) Status of CRC Calculation */ + + struct + { + uint32_t : 24; + __IM uint32_t CRC_1_CAL_STA : 2; /*!< [25..24] Status of CRC Calculation0 : Idle1 : Busy2 : Stop3 + * : Error */ + uint32_t : 6; + } CRC_1_STA_REG_b; + }; + + union + { + __IOM uint32_t CRC_1_CAL_VAL_REV_REG; /*!< (@ 0x00000228) CRC calculation reversed value */ + + struct + { + __IM uint32_t CRC_1_CAL_VAL_REV : 32; /*!< [31..0] CRC calculation reversed value */ + } CRC_1_CAL_VAL_REV_REG_b; + }; + __IM uint32_t RESERVED4[53]; + + union + { + __IOM uint32_t HW_CHS_REQ_CTRL_REG; /*!< (@ 0x00000300) Request of TCP CheckSum */ + + struct + { + __OM uint32_t HW_CHS_REQ_CLR : 1; /*!< [0..0] Clear Request of HW CheckSum, active high with auto clear + * function */ + __OM uint32_t HW_CHS_REQ_START : 1; /*!< [1..1] Start Request of HW CheckSum, active high with auto clear + * function */ + uint32_t : 30; + } HW_CHS_REQ_CTRL_REG_b; + }; + + union + { + __IOM uint32_t HW_CHS_OP_EN_REG; /*!< (@ 0x00000304) Operation Enable of TCP CheckSum */ + + struct + { + __IOM uint32_t HW_CHS_OP_EN : 1; /*!< [0..0] Operation Enable of HW CheckSum */ + uint32_t : 31; + } HW_CHS_OP_EN_REG_b; + }; + + union + { + __IOM uint32_t HW_CHS_CONFIG_REG; /*!< (@ 0x00000308) Configuration of TCP CheckSum */ + + struct + { + __IOM uint32_t HW_CHS_PATH_SEL : 5; /*!< [4..0] Path Selection of HW CheckSum0x00 : CPUS0x01 : DMA0x02 + * : RESERVED */ + uint32_t : 4; + __IOM uint32_t HW_CHS_PAR_TYPE : 2; /*!< [10..9] Parallel Type of HW CheckSum00 : Reserved01 : 16 bits10 + * : 32 bits */ + uint32_t : 5; + __IOM uint32_t HW_CHS_MST_TYPE : 5; /*!< [20..16] Master Type of HW CheckSum for slave path selection + * in Master Checking Enable0x00 : CPUS0x01 : DMA0x02 : RESERVED */ + uint32_t : 3; + __IOM uint32_t HW_CHS_CHK_ADDR : 1; /*!< [24..24] Address Checking Enable of HW CheckSum */ + uint32_t : 7; + } HW_CHS_CONFIG_REG_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t HW_CHS_ADDR_MIN_REG; /*!< (@ 0x00000310) Minimum address to check the bus address range */ + + struct + { + __IOM uint32_t HW_CHS_ADDR_MIN : 32; /*!< [31..0] Minimum address to check the bus address range */ + } HW_CHS_ADDR_MIN_REG_b; + }; + + union + { + __IOM uint32_t HW_CHS_ADDR_MAX_REG; /*!< (@ 0x00000314) Maximum address to check the bus address range */ + + struct + { + __IOM uint32_t HW_CHS_ADDR_MAX : 32; /*!< [31..0] Maximum address to check the bus address range */ + } HW_CHS_ADDR_MAX_REG_b; + }; + __IOM uint32_t HW_CHS_PSEUDO_VAL_REG; /*!< (@ 0x00000318) TCS pseudo value to accumulate manually */ + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t HW_CHS_CAL_VAL_REG; /*!< (@ 0x00000320) TCP CheckSum calculation Value */ + + struct + { + __IM uint32_t HW_CHS_CAL_VAL : 16; /*!< [15..0] HW CheckSum calculation Value */ + uint32_t : 16; + } HW_CHS_CAL_VAL_REG_b; + }; + + union + { + __IOM uint32_t HW_CHS_CAL_STA_REG; /*!< (@ 0x00000324) Status of TCP CheckSum calculation */ + + struct + { + __IM uint32_t HW_CHS_CAL_NUM : 20; /*!< [19..0] Number of HW CheckSum calculation bytes (Max. 1M Bytes) */ + uint32_t : 4; + __IM uint32_t HW_CHS_CAL_STA : 2; /*!< [25..24] Status of HW CheckSum calculation0 : Idle1 : Busy2 + * : Stop3 : Error */ + uint32_t : 6; + } HW_CHS_CAL_STA_REG_b; + }; +} HW_ACC_Type; /*!< Size = 808 (0x328) */ + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C registers (I2C) + */ + +typedef struct /*!< (@ 0x40090000) I2C Structure */ +{ + union + { + __IOM uint32_t I2C_CON_REG; /*!< (@ 0x00000000) I2C Control Register */ + + struct + { + __IOM uint32_t I2C_MASTER_MODE : 1; /*!< [0..0] This bit controls whether the controller master is enabled.0 + * = Master disabled1 = Master enabledSoftware should ensure + * that if this bit is written with '1' then bit 6 should + * also be written with a '1'. */ + __IOM uint32_t I2C_SPEED : 2; /*!< [2..1] These bits control at which speed the controller operates.1 + * = Standard mode (100 kbit/s)2 = Fast mode (400 kbit/s)3 + * = High speed mode */ + __IOM uint32_t I2C_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, this bit controls whether the + * controller responds to 7- or 10-bit addresses.0 = 7-bit + * addressing1 = 10-bit addressing */ + __IOM uint32_t I2C_10BITADDR_MASTER : 1; /*!< [4..4] Control whether the controller starts its transfers in + * 7- or 10-bit addressing mode when acting as a master.0 + * = 7-bit addressing1 = 10-bit addressing */ + __IOM uint32_t I2C_RESTART_EN : 1; /*!< [5..5] Determine whether RESTART conditions may be sent when + * acting as a master.0 = Disable1 = Enable */ + __IOM uint32_t I2C_SLAVE_DISABLE : 1; /*!< [6..6] Slave enabled or disabled after reset is applied, which + * means software does not have to configure the slave.0 = + * Slave is enabled.1 = Slave is disabled.Software should + * ensure that if this bit is written with '0', then bit 0 + * should also be written with a '0'. */ + __IOM uint32_t I2C_STOP_DET_IFADDRESSED : 1; /*!< [7..7] 1 = Slave issues STOP_DET intr only if addressed.0 = + * Slave issues STOP_DET intr always.During a general call + * address, this slave does not issue the STOP_DET interrupt + * if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds + * to the general call address by generating ACK. The STOP_DET + * interrupt is generated only when the transmitted address + * matches the slave address (SAR). */ + __IOM uint32_t I2C_TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the generation of the TX_EMPTY interrupt + * as described in the IC_RAW_INTR_STAT register.1 = Controlled + * generation of TX_EMPTY interrupt.0 = Default behaviour + * of TX_EMPTY interrupt. */ + __IOM uint32_t I2C_RX_FIFO_FULL_HLD_CTRL : 1; /*!< [9..9] This bit controls whether DW_apb_i2c should hold the + * bus when the RX FIFO is physically full to its RX_BUFFER_DEPTH.1 + * = Hold bus when RX_FIFO is full.0 = Overflow when RX_FIFO + * is full. */ + __IM uint32_t I2C_STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode:1 = Issue the STOP_DET interrupt only + * when master is active.0 = Issue the STOP_DET irrespective + * of whether master is active or not. */ + uint32_t : 21; + } I2C_CON_REG_b; + }; + + union + { + __IOM uint32_t I2C_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */ + + struct + { + __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any master transaction. + * When transmitting a General Call, these bits are ignored. + * To generate a START BYTE, the CPU needs to write only once + * into these bits.Note: If the IC_TAR and IC_SAR are the + * same, loopback exists but the FIFOs are shared between + * master and slave, so full loopback is not feasible. Only + * one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit + * to only a slave.Write to this register succeed */ + __IOM uint32_t GC_OR_START : 1; /*!< [10..10] On readIf bit 11 (SPECIAL) is set to 1, then this bit + * indicates whether a General Call or START byte command + * is to be performed by the controller.0 = General Call Address + * - after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit + * 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller + * remains in General Call mode until the SPECIAL bit value + * (bit 11) is cleared.1 = START BYTEOn write1 = START byte + * transmission0 = */ + __IOM uint32_t SPECIAL : 1; /*!< [11..11] On readThis bit indicates whether software performs + * a General Call or START BYTE command.0 = Ignore bit 10 + * GC_OR_START and use IC_TAR normally.1 = Perform special + * I2C command as specified in GC_OR_START bit.On write1 = + * Enables programming of GENERAL_CALL or START_BYTE transmission.0 + * = Disables programming of GENERAL_CALL or START_BYTE transmission.Write + * to this register succeed only when IC_ENABLE[0] is set + * to 0. */ + uint32_t : 20; + } I2C_TAR_REG_b; + }; + + union + { + __IOM uint32_t I2C_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */ + + struct + { + __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the I2C is operating + * as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + * This register can be written only when the I2C interface + * is disabled, which corresponds to the IC_ENABLE register + * being set to 0. Write at other times have no effect.Write + * to this register succeed only when IC_ENABLE[0] is set + * to 0. */ + uint32_t : 22; + } I2C_SAR_REG_b; + }; + + union + { + __IOM uint32_t I2C_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ + + struct + { + __IOM uint32_t I2C_IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value of the I2C HS mode master + * code. HS-mode master codes are reserved 8-bit codes (00001xxx) + * that are not used for slave addressing or other purposes. + * Each master has its unique master code; up to eight high-speed + * mode masters can be present on the same I2C bus system. + * Valid values are from 0 to 7. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the IC_ENABLE[0] register being set to 0. Write at other + * times have no effect. */ + uint32_t : 29; + } I2C_HS_MADDR_REG_b; + }; + + union + { + __IOM uint32_t I2C_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ + + struct + { + __IOM uint32_t I2C_DAT : 8; /*!< [7..0] This register contains the data to be transmitted or + * received on the I2C bus. If you are writing to this register + * and want to perform a read, bits 7:0 (DAT) are ignored + * by the controller. However, when you read this register, + * these bits return the value of data received on the controller's + * interface. */ + __OM uint32_t I2C_CMD : 1; /*!< [8..8] This bit controls whether a read or a write is performed. + * This bit does not control the direction when the I2C Ctrl + * acts as a slave. It controls only the direction when it + * acts as a master.1 = Read0 = WriteWhen a command is entered + * in the TX FIFO, this bit distinguishes the write and read + * commands. In slave-receiver mode, this bit is a "don't + * care" because writes to this register are not required. + * In slave-transmitter mode, a "0" indicates that CPU data + * is to be transmitted and as DAT or IC_D */ + __OM uint32_t I2C_STOP : 1; /*!< [9..9] This bit controls whether a STOP is issued after the + * byte is sent or received.1 = STOP is issued after this + * byte, regardless of whether or not the TX FIFO is empty. + * If the TX FIFO is not empty, the master immediately tries + * to start a new transfer by issuing a START and arbitrating + * for the bus.0 = STOP is not issued after this byte, regardless + * of whether or not the TX FIFO is empty. If the TX FIFO + * is not empty, the master continues the current transfer + * by sending/receiving data bytes according to */ + __OM uint32_t I2C_RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is issued before + * the byte is sent or received. 1 = If IC_RESTART_EN is 1, + * a RESTART is issued before the data is sent/received (according + * to the value of CMD), regardless of whether or not the + * transfer direction is changing from the previous command; + * if IC_RESTART_EN is 0, a STOP followed by a START is issued + * instead.0 = If IC_RESTART_EN is 1, a RESTART is issued + * only if the transfer direction is changing from the previous + * command; if IC_RESTART_EN is 0, a STOP */ + uint32_t : 21; + } I2C_DATA_CMD_REG_b; + }; + + union + { + __IOM uint32_t I2C_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high-period count for standard speed. + * This register can be written only when the I2C interface + * is disabled which corresponds to the IC_ENABLE register + * being set to 0. Write at other times have no effect.The + * minimum valid value is 6; hardware prevents values less + * than this being written, and if attempted results in 6 + * being set.NOTE: This register must not be program */ + uint32_t : 16; + } I2C_SS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low period count for standard speed.This + * register can be written only when the I2C interface is + * disabled which corresponds to the I2C_ENABLE register being + * set to 0. Write at other times have no effect.The minimum + * valid value is 8; hardware prevents values less than this + * being written, and if attempted, results in 8 being set. */ + uint32_t : 16; + } I2C_SS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high-period count for fast speed. It + * is used in high-speed mode to send the Master Code and + * START BYTE or General CALL. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the I2C_ENABLE register being set to 0. Writes at other + * times have no effect.The minimum valid value is 6; hardware + * prevents values less than this being written */ + uint32_t : 16; + } I2C_FS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low-period count for fast speed. It + * is used in high-speed mode to send the Master Code and + * START BYTE or General CALL. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the I2C_ENABLE register being set to 0. Write at other + * times have no effect.The minimum valid value is 8; hardware + * prevents values less than this being written, */ + uint32_t : 16; + } I2C_FS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high period count for high speed. See + * "IC_CLK Frequency Configuration".The SCL High time depends + * on the loading of the bus. For 100 pF loading, the SCL + * High time is 60 ns; for 400 pF loading, the SCL High time + * is 120 ns. This register goes away and becomes read-only + * returning 0s if IC_MAX_SPEED_MODE != high.This register + * can be written only when the I2C interface i */ + uint32_t : 16; + } I2C_HS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low period count for high speed. For + * more information, see "IC_CLK Frequency Configuration".The + * SCL low time depends on the loading of the bus. For 100 + * pF loading, the SCL low time is 160 ns; for 400 pF loading, + * the SCL low time is 320 ns. This register goes away and + * becomes read-only returning 0s if IC_MAX_SPEED_MODE != + * high.This register can be written only when */ + uint32_t : 16; + } I2C_HS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + + struct + { + __IM uint32_t R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer + * when it is empty by reading from the IC_DATA_CMD register. + * If the module is disabled (I2C_ENABLE[0]=0), this bit keeps + * its level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to 32 + * and an additional byte is received from an external I2C + * device. The controller acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the + * module is disabled (I2C_ENABLE[0]=0), this bit keeps its + * level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the + * RX_TL threshold in the I2C_RX_TL register. It is automatically + * cleared by hardware when buffer level goes below the threshold. + * If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is + * not full. So this bit is cleared once, the I2C_ENABLE bit + * 0 is programmed with a 0 regardless of the activity that + * continues. */ + __IM uint32_t R_TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled + * to 32 and the processor attempts to issue another I2C command + * by writing to the IC_DATA_CMD register. When the module + * is disabled, this bit keeps its level until the master + * or slave state machines go into idle, and when ic_en goes + * to 0, this interrupt is cleared */ + __IM uint32_t R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or + * below the threshold value set in the I2C_TX_TL register. + * It is automatically cleared by hardware when the buffer + * level goes above the threshold. When the IC_ENABLE bit + * 0 is 0, the TX FIFO is flushed and held in reset. There + * the TX FIFO looks like it has no data within it, so this + * bit is set to 1, provided there is activity in the master + * or slave state machines. When there is no longer activity, + * then with ic_en=0, this bit is set to 0. */ + __IM uint32_t R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when the controller is acting as + * a slave and another I2C master is attempting to read data + * from the controller. The controller holds the I2C bus in + * a wait state (SCL=0) until this interrupt is serviced, + * which means that the slave has been addressed by a remote + * master that is asking for data to be transferred. The processor + * must respond to this interrupt and then write the requested + * data to the I2C_DATA_CMD register. This bit is set to 0 + * just after the processor reads the I2C_CLR_RD_R */ + __IM uint32_t R_TX_ABRT : 1; /*!< [6..6] This bit indicates if the controller, as an I2C transmitter, + * is unable to complete the intended actions on the contents + * of the transmit FIFO. This situation can occur both as + * an I2C master or an I2C slave, and is referred to as a + * "transmit abort".When this bit is set to 1, the I2C_TX_ABRT_SOURCE + * register indicates the reason why the transmit abort takes + * places.NOTE: The controller flushes/resets/empties the + * TX FIFO whenever this bit is set. The TX FIFO remains in + * this flushed state until the regi */ + __IM uint32_t R_RX_DONE : 1; /*!< [7..7] When the controller is acting as a slave-transmitter, + * this bit is set to 1 if the master does not acknowledge + * a transmitted byte. This occurs on the last byte of the + * transmission, indicating that the transmission is done. */ + __IM uint32_t R_ACTIVITY : 1; /*!< [8..8] This bit captures I2C Ctrl activity and stays set until + * it is cleared. There are four ways to clear it:=> Disabling + * the I2C Ctrl=> Reading the IC_CLR_ACTIVITY register=> Reading + * the IC_CLR_INTR register=> System resetOnce this bit is + * set, it stays set unless one of the four methods is used + * to clear it. Even if the controller module is idle, this + * bit remains set until cleared, indicating that there was + * activity on the bus. */ + __IM uint32_t R_STOP_DET : 1; /*!< [9..9] Indicate whether a STOP condition has occurred on the + * I2C interface regardless of whether controller is operating + * in slave or master mode. */ + __IM uint32_t R_START_DET : 1; /*!< [10..10] Indicate whether a START or RESTART condition has occurred + * on the I2C interface regardless of whether controller is + * operating in slave or master mode. */ + __IM uint32_t R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and + * it is acknowledged. It stays set until it is cleared either + * by disabling controller or when the CPU reads bit 0 of + * the I2C_CLR_GEN_CALL register. The controller stores the + * received data in the RX buffer. */ + __IM uint32_t R_RESTART_DET : 1; /*!< [12..12] Indicate whether a RESTART condition has occurred on + * the I2C interface when DW_apb_i2c is operating in Slave + * mode and the slave is being addressed.Enabled only when + * IC_SLV_RESTART_DET_EN=1.Note: However, in high-speed mode + * or during a START BYTE transfer, the RESTART comes before + * the address field as per the I2C protocol. In this case, + * the slave is not the addressed slave when the RESTART is + * issued, therefore DW_apb_i2c does not generate the RESTART_DET + * interrupt. */ + __IM uint32_t R_MASTER_ON_HOLD : 1; /*!< [13..13] Indicate whether master is holding the bus and TX FIFO + * is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and + * IC_EMPTYFIFO_HOLD_MASTER_EN=1. */ + __IM uint32_t R_SCL_STUCK_AT_LOW : 1; /*!< [14..14] 1 = R_SCL_STUCK_AT_LOW interrupt is active.0 = R_SCL_STUCK_AT_LOW + * interrupt is inactive. */ + uint32_t : 17; + } I2C_INTR_STAT_REG_b; + }; + + union + { + __IOM uint32_t I2C_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + + struct + { + __IOM uint32_t M_RX_UNDER : 1; /*!< [0..0] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_OVER : 1; /*!< [1..1] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_FULL : 1; /*!< [2..2] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_OVER : 1; /*!< [3..3] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_EMPTY : 1; /*!< [4..4] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RD_REQ : 1; /*!< [5..5] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_ABRT : 1; /*!< [6..6] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_DONE : 1; /*!< [7..7] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_ACTIVITY : 1; /*!< [8..8] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_STOP_DET : 1; /*!< [9..9] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_START_DET : 1; /*!< [10..10] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_GEN_CALL : 1; /*!< [11..11] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RESTART_DET : 1; /*!< [12..12] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_MASTER_ON_HOLD : 1; /*!< [13..13] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] M_SCL_STUCK_AT_LOW Register field Reserved bits. */ + uint32_t : 17; + } I2C_INTR_MASK_REG_b; + }; + + union + { + __IOM uint32_t I2C_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ + + struct + { + __IM uint32_t RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer + * when it is empty by reading from the IC_DATA_CMD register. + * If the module is disabled (I2C_ENABLE[0]=0), this bit keeps + * its level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to 32 + * and an additional byte is received from an external I2C + * device. The controller acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the + * module is disabled (I2C_ENABLE[0]=0), this bit keeps its + * level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the + * RX_TL threshold in the I2C_RX_TL register. It is automatically + * cleared by hardware when buffer level goes below the threshold. + * If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is + * not full. So this bit is cleared once the I2C_ENABLE bit + * 0 is programmed with a 0, regardless of the activity that + * continues. */ + __IM uint32_t TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled + * to 32 and the processor attempts to issue another I2C command + * by writing to the IC_DATA_CMD register. When the module + * is disabled, this bit keeps its level until the master + * or slave state machines go into idle, and when ic_en goes + * to 0, this interrupt is cleared . */ + __IM uint32_t TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or + * below the threshold value set in the I2C_TX_TL register. + * It is automatically cleared by hardware when the buffer + * level goes above the threshold. When the IC_ENABLE bit + * 0 is 0, the TX FIFO is flushed and held in reset. There + * the TX FIFO looks like it has no data within it, so this + * bit is set to 1, provided there is activity in the master + * or slave state machines. When there is no longer activity, + * then with ic_en=0, this bit is set to 0. */ + __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when I2C Ctrl is acting as a slave + * and another I2C master is attempting to read data from + * the controller. The controller holds the I2C bus in a wait + * state (SCL=0) until this interrupt is serviced, which means + * that the slave has been addressed by a remote master that + * is asking for data to be transferred. The processor must + * respond to this interrupt and then write the requested + * data to the I2C_DATA_CMD register. This bit is set to 0 + * just after the processor reads the I2C_CLR_RD_REQ reg */ + __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if the controller, as an I2C transmitter, + * is unable to complete the intended actions on the contents + * of the transmit FIFO. This situation can occur both as + * an I2C master or an I2C slave, and is referred to as a + * "transmit abort".When this bit is set to 1, the I2C_TX_ABRT_SOURCE + * register indicates the reason why the transmit abort takes + * places.NOTE: The controller flushes/resets/empties the + * TX FIFO whenever this bit is set. The TX FIFO remains in + * this flushed state until the regi */ + __IM uint32_t RX_DONE : 1; /*!< [7..7] When the controller is acting as a slave-transmitter, + * this bit is set to 1 if the master does not acknowledge + * a transmitted byte. This occurs on the last byte of the + * transmission, indicating that the transmission is done. */ + __IM uint32_t ACTIVITY : 1; /*!< [8..8] This bit captures I2C Ctrl activity and stays set until + * it is cleared. There are four ways to clear it:=> Disabling + * the I2C Ctrl=> Reading the IC_CLR_ACTIVITY register=> Reading + * the IC_CLR_INTR register=> System resetOnce this bit is + * set, it stays set unless one of the four methods is used + * to clear it. Even if the controller module is idle, this + * bit remains set until cleared, indicating that there was + * activity on the bus. */ + __IM uint32_t STOP_DET : 1; /*!< [9..9] Indicate whether a STOP condition has occurred on the + * I2C interface regardless of whether controller is operating + * in slave or master mode. */ + __IM uint32_t START_DET : 1; /*!< [10..10] Indicate whether a START or RESTART condition has occurred + * on the I2C interface regardless of whether controller is + * operating in slave or master mode. */ + __IM uint32_t GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and + * it is acknowledged. It stays set until it is cleared either + * by disabling controller or when the CPU reads bit 0 of + * the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received + * data in the Rx buffer. */ + __IM uint32_t RESTART_DET : 1; /*!< [12..12] Indicate whether a RESTART condition has occurred on + * the I2C interface when DW_apb_i2c is operating in Slave + * mode and the slave is being addressed.Enabled only when + * IC_SLV_RESTART_DET_EN=1.Note: However, in high-speed mode + * or during a START BYTE transfer, the RESTART comes before + * the address field as per the I2C protocol. In this case, + * the slave is not the addressed slave when the RESTART is + * issued, therefore DW_apb_i2c does not generate the RESTART_DET + * interrupt. */ + __IM uint32_t MASTER_ON_HOLD : 1; /*!< [13..13] ndicate whether master is holding the bus and TX FIFO + * is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and + * IC_EMPTYFIFO_HOLD_MASTER_EN=1. */ + __IM uint32_t SCL_STUCK_AT_LOW : 1; /*!< [14..14] CL_STUCK_AT_LOW Register field Reserved bits. */ + uint32_t : 17; + } I2C_RAW_INTR_STAT_REG_b; + }; + + union + { + __IOM uint32_t I2C_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + + struct + { + __IOM uint32_t RX_TL : 5; /*!< [4..0] Receive FIFO Threshold Level Controls the level of entries + * (or above) that triggers the RX_FULL interrupt (bit 2 in + * I2C_RAW_INTR_STAT register). The valid range is 0-31, with + * the additional restriction that hardware does not allow + * this value to be set to a value larger than the depth of + * the buffer. If an attempt is made to do that, the actual + * value set will be the maximum depth of the buffer. A value + * of 0 sets the threshold for 1 entry, and a value of 31 + * sets the threshold for 32 entries. */ + uint32_t : 27; + } I2C_RX_TL_REG_b; + }; + + union + { + __IOM uint32_t I2C_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TX_TL : 5; /*!< [4..0] Transmit FIFO Threshold Level Controls the level of entries + * (or below) that trigger the TX_EMPTY interrupt (bit 4 in + * I2C_RAW_INTR_STAT register). The valid range is 0-31, with + * the additional restriction that it may not be set to value + * larger than the depth of the buffer. If an attempt is made + * to do that, the actual value set will be the maximum depth + * of the buffer. A value of 0 sets the threshold for 0 entries, + * and a value of 31 sets the threshold for 32 entries. */ + uint32_t : 27; + } I2C_TX_TL_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + + struct + { + __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined interrupt, all + * individual interrupts, and the I2C_TX_ABRT_SOURCE register. + * This bit does not clear hardware clearable interrupts but + * software clearable interrupts. See Bit 9 of the I2C_TX_ABRT_SOURCE + * register for an exception to clearing I2C_TX_ABRT_SOURCE. */ + uint32_t : 31; + } I2C_CLR_INTR_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear the RX_UNDER interrupt (bit + * 0) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_RX_UNDER_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the RX_OVER interrupt (bit + * 1) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_RX_OVER_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + + struct + { + __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the TX_OVER interrupt (bit + * 3) of the I2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_TX_OVER_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + + struct + { + __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the RD_REQ interrupt (bit + * 5) of the I2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_RD_REQ_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + + struct + { + __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT interrupt (bit + * 6) of theIC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE + * register. This also releases the TX FIFO from the flushed/reset + * state, allowing more writes to the TX FIFO. See Bit 9 of + * the I2C_TX_ABRT_SOURCE register for an exception to clearing + * IC_TX_ABRT_SOURCE. */ + uint32_t : 31; + } I2C_CLR_TX_ABRT_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the RX_DONE interrupt (bit + * 7) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_RX_DONE_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + + struct + { + __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears the ACTIVITY interrupt if + * the I2C is not active anymore. If the I2C module is still + * active on the bus, the ACTIVITY interrupt bit continues + * to be set. It is automatically cleared by hardware if the + * module is disabled and if there is no further activity + * on the bus. The value read from this register to get status + * of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT + * register. */ + uint32_t : 31; + } I2C_CLR_ACTIVITY_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + + struct + { + __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear the STOP_DET interrupt (bit + * 9) of the IC_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_STOP_DET_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + + struct + { + __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear the START_DET interrupt (bit + * 10) of the IC_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_START_DET_REG_b; + }; + + union + { + __IOM uint32_t I2C_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + + struct + { + __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear the GEN_CALL interrupt (bit + * 11) ofI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C_CLR_GEN_CALL_REG_b; + }; + + union + { + __IOM uint32_t I2C_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */ + + struct + { + __IOM uint32_t I2C_EN : 1; /*!< [0..0] Control whether the controller is enabled.0 = Disable + * the controller (TX and RX FIFOs are held in an erased state)1 + * = Enable the controllerSoftware can disable the controller + * while it is active. However, it is important that care + * be taken to ensure that the controller is disabled properly. + * When the controller is disabled, the following occurs:* + * The TX FIFO and RX FIFO get flushed.* Status bits in the + * IC_INTR_STAT register are still active until the controller + * goes into IDLE state. */ + __IOM uint32_t I2C_ABORT : 1; /*!< [1..1] The software can abort the I2C transfer in master mode + * by setting this bit. The software can set this bit only + * when ENABLE is already set; otherwise, the controller ignores + * any write to ABORT bit. The software cannot clear the ABORT + * bit once set. In response to an ABORT, the controller issues + * a STOP and flushes the TX FIFO after completing the current + * transfer, then sets the TX_ABORT interrupt after the abort + * operation. The ABORT bit is cleared automatically after + * the abort operation. */ + __IOM uint32_t I2C_TX_CMD_BLOCK : 1; /*!< [2..2] In Master mode:1 = Block the transmission of data on + * I2C bus even if TX FIFO has data to transmit.0.= The transmission + * of data starts on I2C bus automatically as soon as the + * first data is available in the TX FIFO. */ + uint32_t : 29; + } I2C_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t I2C_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */ + + struct + { + __IM uint32_t I2C_ACTIVITY : 1; /*!< [0..0] I2C Activity Status. */ + __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO Not Full. Set when the transmit FIFO contains + * one or more empty locations, and is cleared when the FIFO + * is full.0 = Transmit FIFO is full.1 = Transmit FIFO is + * not full. */ + __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty. When the transmit FIFO + * is completely empty, this bit is set. When it contains + * one or more valid entries, this bit is cleared. This bit + * field does not request an interrupt.0 = Transmit FIFO is + * not empty.1 = Transmit FIFO is empty. */ + __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO Not Empty. This bit is set when the receive + * FIFO contains one or more entries; it is cleared when the + * receive FIFO is empty.0 = Receive FIFO is empty.1 = Receive + * FIFO is not empty. */ + __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO Completely Full. When the receive FIFO is + * completely full, this bit is set. When the receive FIFO + * contains one or more empty location, this bit is cleared.0 + * = Receive FIFO is not full.1 = Receive FIFO is full. */ + __IM uint32_t MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status. When the Master Finite State + * Machine (FSM) is not in the IDLE state, this bit is set.0 + * = Master FSM is in IDLE state so the Master part of the + * controller is not Active.1 = Master FSM is not in IDLE + * state so the Master part of the controller is Active. */ + __IM uint32_t SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status. When the Slave Finite State + * Machine (FSM) is not in the IDLE state, this bit is set.0 + * = Slave FSM is in IDLE state so the Slave part of the controller + * is not Active.1 = Slave FSM is not in IDLE state so the + * Slave part of the controller is Active. */ + __IM uint32_t MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The DW_apb_i2c master stalls the write transfer when + * TX FIFO is empty, and the the last byte does not have the + * Stop bit set. This bit indicates the BUS hold when the + * master holds the bus because of the TX FIFO being empty, + * and the the previous transferred command does not have + * the Stop bit set.1 = Master holds the bus due to TX FIFO + * is empty.0 = Master is not holding the bus or Bus hold + * is not due to TX FIFO is empty. */ + __IM uint32_t MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold in Master mode due to + * RX FIFO is Full and additional byte is received.1 = Master + * holds the bus due to RX FIFO is full.0 = Master is not + * holding the bus or Bus hold is not due to RX FIFO is full. */ + __IM uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS Hold in Slave mode for the + * Read request when the TX FIFO is empty. The Bus is in hold + * until the TX FIFO has data to Transmit for the read request.1 + * = Slave holds the bus due to TX FIFO is empty.0 = Slave + * is not holding the bus or Bus hold is not due to TX FIFO + * is empty. */ + __IM uint32_t LV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS Hold in Slave mode due to + * RX FIFO is Full and an additional byte has been received.1 + * = Slave holds the bus due to Rx FIFO is full.0 = Slave + * is not holding the bus or Bus hold is not due to Rx FIFO + * is full. */ + uint32_t : 21; + } I2C_STATUS_REG_b; + }; + + union + { + __IOM uint32_t I2C_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + + struct + { + __IM uint32_t TXFLR : 6; /*!< [5..0] Transmit FIFO Level. Contain the number of valid data + * entries in the transmit FIFO. Size is constrained by the + * TXFLR value. */ + uint32_t : 26; + } I2C_TXFLR_REG_b; + }; + + union + { + __IOM uint32_t I2C_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + + struct + { + __IM uint32_t RXFLR : 6; /*!< [5..0] Receive FIFO Level. Contain the number of valid data + * entries in the receive FIFO. Size is constrained by the + * RXFLR value. */ + uint32_t : 26; + } I2C_RXFLR_REG_b; + }; + + union + { + __IOM uint32_t I2C_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + + struct + { + __IOM uint32_t I2C_SDA_TX_HOLD : 16; /*!< [15..0] Set the required SDA hold time in units of ic_clk period + * when transmitting. */ + __IOM uint32_t I2C_SDA_RX_HOLD : 8; /*!< [23..16] Set the required SDA hold time in units of ic_clk period + * when receiving. */ + uint32_t : 8; + } I2C_SDA_HOLD_REG_b; + }; + + union + { + __IOM uint32_t I2C_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ + + struct + { + __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] Master-Transmitter or Master-Receiver: Master is in 7-bit + * addressing mode and the address sent was not acknowledged + * by any slave.1 = This abort is generated because of NOACK + * for 7-bit address.0 = This abort is not generated. */ + __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< [1..1] Master-Transmitter or Master-Receiver: Master is in 10-bit + * address mode and the first 10-bit address byte was not + * acknowledged by any slave.1 = Byte 1 of 10-bit address + * not ACKed by any slave.0 = This abort is not generated. */ + __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< [2..2] Master-Transmitter or Master-Receiver: Master is in 10-bit + * address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave.1 = Byte 2 of + * 10-bit address not ACKed by any slave.0 = This abort is + * not generated. */ + __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< [3..3] Master-Transmitter: This is a master-mode only bit. Master + * has received an acknowledgement for the address, but when + * it sent data byte(s) following the address, it did not + * receive an acknowledge from the remote slave(s).1 = Transmitted + * data not ACKed by addressed slave.0 = Transmitted data + * non-ACKed by addressed slave-scenario not present. */ + __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< [4..4] Master-Transmitter: The controller in master mode sent + * a General Call and no slave on the bus acknowledged the + * General Call.1 = GCALL not ACKed by any slave.0 = GCALL + * not ACKed by any slave-scenario not present. */ + __IM uint32_t ABRT_GCALL_READ : 1; /*!< [5..5] Master-Transmitter: The controller in master mode sent + * a General Call but the user programmed the byte following + * the General Call to be a read from the bus (IC_DATA_CMD[9] + * is set to 1).1 = GCALL is followed by read from bus.0 = + * GCALL is followed by read from bus-scenario not present. */ + __IM uint32_t ABRT_HS_ACKDET : 1; /*!< [6..6] Master: Master is in High Speed mode and the High Speed + * Master code was acknowledged (wrong behavior).1 = HS Master + * code ACKed in HS Mode.0 = HS Master code ACKed in HS Mode- + * scenario not present. */ + __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< [7..7] Master: Master has sent a START Byte and the START Byte + * was acknowledged (wrong behavior). 1 = ACK detected for + * START byte.0 = ACK detected for START byte- scenario not + * present. */ + __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< [8..8] Master-Transmitter or Master-Receiver: The restart is + * disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user + * is trying to use the master to transfer data in High Speed + * mode.1 = User trying to switch Master to HS mode when RESTART + * disabled.0 = User trying to switch Master to HS mode when + * RESTART disabled- scenario not present. */ + __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] Master: To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT + * must be fixed first; restart must be enabled (I2C_CON[5]=1), + * the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START + * bit must be cleared (I2C_TAR[10]). Once the source of the + * ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared + * in the same manner as other bits in this register. If the + * source of the ABRT_SBYTE_NORSTRT is not fixed before attempting + * to clear this bit, bit 9 clears for one cycle and then + * gets re-asserted. 1: The res */ + __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] Master-Receiver: The restart is disabled (IC_RESTART_EN + * bit (I2C_CON[5]) = 0) and the master sends a read command + * in 10-bit addressing mode.1 = Master trying to read in + * 10-bit addressing mode when RESTART disabled.0 = Master + * not trying to read in 10-bit addressing mode when RESTART + * disabled. */ + __IM uint32_t ABRT_MASTER_DIS : 1; /*!< [11..11] Master-Transmitter or Master-Receiver: User tries to + * initiate a Master operation with the Master mode disabled.1 + * = User intitating master operation when MASTER disable.0 + * = User initiating master operation when MASTER disabled- + * scenario not present. */ + __IM uint32_t ARB_LOST : 1; /*!< [12..12] Master-Transmitter or Slave-Transmitter: Master has + * lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also + * set, then the slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same time.1 = Master + * or Slave-Transmitter lost arbitration.0 = Master or Slave-Transmitter + * lost arbitration- scenario not present. */ + __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] Slave-Transmitter: Slave has received a read command + * and some data exists in the TX FIFO so the slave issues + * a TX_ABRT interrupt to flush old data in TX FIFO.1 = Slave + * flushes existing data in TX-FIFO upon getting read command.0 + * = Slave flushes existing data in TX-FIFO upon getting read + * command- scenario not present. */ + __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< [14..14] Slave-Transmitter: Slave lost the bus while transmitting + * data to a remote master. I2C_TX_ABRT_SOURCE[12] is set + * at the same time. Note: Even though the slave never "owns" + * the bus, something could go wrong on the bus. This is a + * fail safe check. For instance, during a data transmission + * at the low-to-high transition of SCL, if what is on the + * data bus is not what is supposed to be transmitted, then + * the controller no longer own the bus.1 = Slave lost arbitration + * to remote master.0 = Slave lost arbitra */ + __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] Slave-Transmitter: When the processor side responds + * to a slave mode request for data to be transmitted to a + * remote master and a user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD + * register.1 = Slave trying to transmit to remote master + * in read mode.0 = Slave trying to transmit to remote master + * in read mode- scenario not present. */ + __IM uint32_t ABRT_USER_ABRT : 1; /*!< [16..16] Master-Transmitter: This is a master-mode-only bit. + * Master has detected the transfer abort (IC_ENABLE[1]). */ + uint32_t : 15; + } I2C_TX_ABRT_SOURCE_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t I2C_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */ + + struct + { + __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA Enable. This bit enables/disables the receive + * FIFO DMA channel.0 = Receive DMA disabled.1 = Receive DMA + * enabled. */ + __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable. This bit enables/disables the transmit + * FIFO DMA channel.0 = Transmit DMA disabled.1 = Transmit + * DMA enabled. */ + uint32_t : 30; + } I2C_DMA_CR_REG_b; + }; + + union + { + __IOM uint32_t I2C_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + + struct + { + __IOM uint32_t DMATDL : 5; /*!< [4..0] Transmit Data Level. This bit field controls the level + * at which a DMA request is made by the transmit logic. It + * is equal to the watermark level; that is, the dma_tx_req + * signal is generated when the number of valid data entries + * in the transmit FIFO is equal to or below this field value, + * and TDMAE = 1. */ + uint32_t : 27; + } I2C_DMA_TDLR_REG_b; + }; + + union + { + __IOM uint32_t I2C_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + + struct + { + __IOM uint32_t DMARDL : 5; /*!< [4..0] Receive Data Level. This bit field controls the level + * at which a DMA request is made by the receive logic. The + * watermark level = DMARDL+1; that is, dma_rx_req is generated + * when the number of valid data entries in the receive FIFO + * is equal to or more than this field value + 1, and RDMAE + * =1. For instance, when DMARDL is 0, then dma_rx_req is + * asserted when 1 or more data entries are present in the + * receive FIFO. */ + uint32_t : 27; + } I2C_DMA_RDLR_REG_b; + }; + + union + { + __IOM uint32_t I2C_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */ + + struct + { + __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] SDA Setup.This register controls the amount of time delay + * (number of I2C clock periods) between the rising edge of + * SCL and SDA changing by holding SCL low when I2C block + * services a read request while operating as a slave-transmitter. + * The relevant I2C requirement is tSU:DAT (note 4) as detailed + * in the I2C Bus Specification. This register must be programmed + * with a value equal to or greater than 2.It is recommended + * that if the required delay is 1000 ns, then for an I2C + * frequency of 10 MHz, IC_SDA_SE */ + uint32_t : 24; + } I2C_SDA_SETUP_REG_b; + }; + + union + { + __IOM uint32_t I2C_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */ + + struct + { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call. When set to 1, I2C Ctrl responds with + * a ACK (by asserting ic_data_oe) when it receives a General + * Call. When set to 0, the controller does not generate General + * Call interrupts.1 = Generate ACK for a General Call.0 = + * Generate NACK for General Call. */ + uint32_t : 31; + } I2C_ACK_GENERAL_CALL_REG_b; + }; + + union + { + __IOM uint32_t I2C_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */ + + struct + { + __IM uint32_t IC_EN : 1; /*!< [0..0] ic_en Status. This bit always reflects the value driven + * on the output port ic_en. When read as 1, the controller + * is deemed to be in an enabled state.When read as 0, the + * controller is deemed completely inactive.NOTE: The CPU + * can safely read this bit anytime. When this bit is read + * as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) + * and SLV_DISABLED_WHILE_BUSY (bit 1).1 = I2C enabled.0 = + * I2C disabled. */ + __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] Slave Disabled While Busy (Transmit, Receive). This bit + * indicates if a potential or active Slave operation has + * aborted due to the setting of the IC_ENABLE register from + * 1 to 0. This bit is set when the CPU writes a 0 to the + * IC_ENABLE register while:(a) I2C Ctrl is receiving the + * address byte of the Slave-Transmitter operation from a + * remote master; OR,(b) address and data bytes of the Slave-Receiver + * operation from a remote master. When read as 1, the controller + * is deemed to have forced a NACK durin */ + __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost. This bit indicates if a Slave-Receiver + * operation is aborted with at least one data byte received + * from an I2C transfer due to the setting of IC_ENABLE from + * 1 to 0. When read as 1, the controller is deemed to have + * actively engaged in an aborted I2C transfer (with matching + * address) and the data phase of the I2C transfer is entered, + * even though a data byte is responded with a NACK. NOTE: + * If the remote I2C master terminates the transfer with a + * STOP condition before the controller has */ + uint32_t : 29; + } I2C_ENABLE_STATUS_REG_b; + }; + + union + { + __IOM uint32_t I2C_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */ + + struct + { + __IOM uint32_t I2C_FS_SPKLEN : 8; /*!< [7..0] This register must be set before any I2C bus transaction + * can take place to ensure stable operation. This register + * sets the duration, measured in ic_clk cycles, of the longest + * spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written + * only when the I2C interface is disabled which corresponds + * to the IC_ENABLE register being set to 0. Write at other + * times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, */ + uint32_t : 24; + } I2C_IC_FS_SPKLEN_REG_b; + }; + + union + { + __IOM uint32_t I2C_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */ + + struct + { + __IOM uint32_t I2C_HS_SPKLEN : 8; /*!< [7..0] This register must be set before any I2C bus transaction + * can take place to ensure stable operation. This register + * sets the duration, measured in ic_clk cycles, of the longest + * spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written + * only when the I2C interface is disabled which corresponds + * to the IC_ENABLE[0] register being set to 0. Write at other + * times have no effect.The minimum valid value is 1; hardware + * prevents values less than this being wr */ + uint32_t : 24; + } I2C_IC_HS_SPKLEN_REG_b; + }; + __IM uint32_t RESERVED1[19]; + + union + { + __IOM uint32_t I2C_COMP_PARAM1_REG; /*!< (@ 0x000000F4) I2C_COMP_PARAM1_REG */ + + struct + { + __IM uint32_t IC_COMP_PARAM1 : 32; /*!< [31..0] IC_COMP_PARAM1 */ + } I2C_COMP_PARAM1_REG_b; + }; + + union + { + __IOM uint32_t I2C_COMP_VERSION_REG; /*!< (@ 0x000000F8) I2C_COMP_VERSION_REG */ + + struct + { + __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] IC_COMP_VERSION */ + } I2C_COMP_VERSION_REG_b; + }; + + union + { + __IOM uint32_t I2C_COMP_TYPE_REG; /*!< (@ 0x000000FC) I2C_COMP_TYPE_REG */ + + struct + { + __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] IC_COMP_TYPE */ + } I2C_COMP_TYPE_REG_b; + }; +} I2C_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ I2C2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C2 registers (I2C2) + */ + +typedef struct /*!< (@ 0x40090100) I2C2 Structure */ +{ + union + { + __IOM uint32_t I2C2_CON_REG; /*!< (@ 0x00000000) I2C Control Register */ + + struct + { + __IOM uint32_t I2C_MASTER_MODE : 1; /*!< [0..0] This bit controls whether the controller master is enabled.0 + * = Master disabled1 = Master enabledSoftware should ensure + * that if this bit is written with '1' then bit 6 should + * also be written with a '1'. */ + __IOM uint32_t I2C_SPEED : 2; /*!< [2..1] These bits control at which speed the controller operates.1 + * = Standard mode (100 kbit/s)2 = Fast mode (400 kbit/s)3 + * = High speed mode */ + __IOM uint32_t I2C_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, this bit controls whether the + * controller responds to 7- or 10-bit addresses.0 = 7-bit + * addressing1 = 10-bit addressing */ + __IOM uint32_t I2C_10BITADDR_MASTER : 1; /*!< [4..4] Control whether the controller starts its transfers in + * 7- or 10-bit addressing mode when acting as a master.0 + * = 7-bit addressing1 = 10-bit addressing */ + __IOM uint32_t I2C_RESTART_EN : 1; /*!< [5..5] Determine whether RESTART conditions may be sent when + * acting as a master.0 = Disable1 = Enable */ + __IOM uint32_t I2C_SLAVE_DISABLE : 1; /*!< [6..6] Slave enabled or disabled after reset is applied, which + * means software does not have to configure the slave.0 = + * Slave is enabled.1 = Slave is disabled.Software should + * ensure that if this bit is written with '0', then bit 0 + * should also be written with a '0'. */ + __IOM uint32_t I2C_STOP_DET_IFADDRESSED : 1; /*!< [7..7] 1 = Slave issues STOP_DET intr only if addressed.0 = + * Slave issues STOP_DET intr always.During a general call + * address, this slave does not issue the STOP_DET interrupt + * if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds + * to the general call address by generating ACK. The STOP_DET + * interrupt is generated only when the transmitted address + * matches the slave address (SAR). */ + __IOM uint32_t I2C_TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the generation of the TX_EMPTY interrupt + * as described in the IC_RAW_INTR_STAT register.1 = Controlled + * generation of TX_EMPTY interrupt.0 = Default behaviour + * of TX_EMPTY interrupt. */ + __IOM uint32_t I2C_RX_FIFO_FULL_HLD_CTRL : 1; /*!< [9..9] This bit controls whether DW_apb_i2c should hold the + * bus when the RX FIFO is physically full to its RX_BUFFER_DEPTH.1 + * = Hold bus when RX_FIFO is full.0 = Overflow when RX_FIFO + * is full. */ + __IM uint32_t I2C_STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode:1 = Issue the STOP_DET interrupt only + * when master is active.0 = Issue the STOP_DET irrespective + * of whether master is active or not. */ + uint32_t : 21; + } I2C2_CON_REG_b; + }; + + union + { + __IOM uint32_t I2C2_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */ + + struct + { + __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any master transaction. + * When transmitting a General Call, these bits are ignored. + * To generate a START BYTE, the CPU needs to write only once + * into these bits.Note: If the IC_TAR and IC_SAR are the + * same, loopback exists but the FIFOs are shared between + * master and slave, so full loopback is not feasible. Only + * one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit + * to only a slave.Write to this register succeed */ + __IOM uint32_t GC_OR_START : 1; /*!< [10..10] On readIf bit 11 (SPECIAL) is set to 1, then this bit + * indicates whether a General Call or START byte command + * is to be performed by the controller.0 = General Call Address + * - after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit + * 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller + * remains in General Call mode until the SPECIAL bit value + * (bit 11) is cleared.1 = START BYTEOn write1 = START byte + * transmission0 = */ + __IOM uint32_t SPECIAL : 1; /*!< [11..11] On readThis bit indicates whether software performs + * a General Call or START BYTE command.0 = Ignore bit 10 + * GC_OR_START and use IC_TAR normally.1 = Perform special + * I2C command as specified in GC_OR_START bit.On write1 = + * Enables programming of GENERAL_CALL or START_BYTE transmission.0 + * = Disables programming of GENERAL_CALL or START_BYTE transmission.Write + * to this register succeed only when IC_ENABLE[0] is set + * to 0. */ + uint32_t : 20; + } I2C2_TAR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */ + + struct + { + __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the I2C is operating + * as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + * This register can be written only when the I2C interface + * is disabled, which corresponds to the IC_ENABLE register + * being set to 0. Write at other times have no effect.Write + * to this register succeed only when IC_ENABLE[0] is set + * to 0. */ + uint32_t : 22; + } I2C2_SAR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ + + struct + { + __IOM uint32_t I2C_IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value of the I2C HS mode master + * code. HS-mode master codes are reserved 8-bit codes (00001xxx) + * that are not used for slave addressing or other purposes. + * Each master has its unique master code; up to eight high-speed + * mode masters can be present on the same I2C bus system. + * Valid values are from 0 to 7. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the IC_ENABLE[0] register being set to 0. Write at other + * times have no effect. */ + uint32_t : 29; + } I2C2_HS_MADDR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ + + struct + { + __IOM uint32_t I2C_DAT : 8; /*!< [7..0] This register contains the data to be transmitted or + * received on the I2C bus. If you are writing to this register + * and want to perform a read, bits 7:0 (DAT) are ignored + * by the controller. However, when you read this register, + * these bits return the value of data received on the controller's + * interface. */ + __OM uint32_t I2C_CMD : 1; /*!< [8..8] This bit controls whether a read or a write is performed. + * This bit does not control the direction when the I2C Ctrl + * acts as a slave. It controls only the direction when it + * acts as a master.1 = Read0 = WriteWhen a command is entered + * in the TX FIFO, this bit distinguishes the write and read + * commands. In slave-receiver mode, this bit is a "don't + * care" because writes to this register are not required. + * In slave-transmitter mode, a "0" indicates that CPU data + * is to be transmitted and as DAT or IC_D */ + __OM uint32_t I2C_STOP : 1; /*!< [9..9] This bit controls whether a STOP is issued after the + * byte is sent or received.1 = STOP is issued after this + * byte, regardless of whether or not the TX FIFO is empty. + * If the TX FIFO is not empty, the master immediately tries + * to start a new transfer by issuing a START and arbitrating + * for the bus.0 = STOP is not issued after this byte, regardless + * of whether or not the TX FIFO is empty. If the TX FIFO + * is not empty, the master continues the current transfer + * by sending/receiving data bytes according to */ + __OM uint32_t I2C_RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is issued before + * the byte is sent or received. 1 = If IC_RESTART_EN is 1, + * a RESTART is issued before the data is sent/received (according + * to the value of CMD), regardless of whether or not the + * transfer direction is changing from the previous command; + * if IC_RESTART_EN is 0, a STOP followed by a START is issued + * instead.0 = If IC_RESTART_EN is 1, a RESTART is issued + * only if the transfer direction is changing from the previous + * command; if IC_RESTART_EN is 0, a STOP */ + uint32_t : 21; + } I2C2_DATA_CMD_REG_b; + }; + + union + { + __IOM uint32_t I2C2_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high-period count for standard speed. + * This register can be written only when the I2C interface + * is disabled which corresponds to the IC_ENABLE register + * being set to 0. Write at other times have no effect.The + * minimum valid value is 6; hardware prevents values less + * than this being written, and if attempted results in 6 + * being set.NOTE: This register must not be program */ + uint32_t : 16; + } I2C2_SS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low period count for standard speed.This + * register can be written only when the I2C interface is + * disabled which corresponds to the I2C_ENABLE register being + * set to 0. Write at other times have no effect.The minimum + * valid value is 8; hardware prevents values less than this + * being written, and if attempted, results in 8 being set. */ + uint32_t : 16; + } I2C2_SS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high-period count for fast speed. It + * is used in high-speed mode to send the Master Code and + * START BYTE or General CALL. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the I2C_ENABLE register being set to 0. Writes at other + * times have no effect.The minimum valid value is 6; hardware + * prevents values less than this being written */ + uint32_t : 16; + } I2C2_FS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low-period count for fast speed. It + * is used in high-speed mode to send the Master Code and + * START BYTE or General CALL. This register can be written + * only when the I2C interface is disabled, which corresponds + * to the I2C_ENABLE register being set to 0. Write at other + * times have no effect.The minimum valid value is 8; hardware + * prevents values less than this being written, */ + uint32_t : 16; + } I2C2_FS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ + + struct + { + __IOM uint32_t IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock high period count for high speed. See + * "IC_CLK Frequency Configuration".The SCL High time depends + * on the loading of the bus. For 100 pF loading, the SCL + * High time is 60 ns; for 400 pF loading, the SCL High time + * is 120 ns. This register goes away and becomes read-only + * returning 0s if IC_MAX_SPEED_MODE != high.This register + * can be written only when the I2C interface i */ + uint32_t : 16; + } I2C2_HS_SCL_HCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ + + struct + { + __IOM uint32_t IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction + * can take place to ensure proper I/O timing. This register + * sets the SCL clock low period count for high speed. For + * more information, see "IC_CLK Frequency Configuration".The + * SCL low time depends on the loading of the bus. For 100 + * pF loading, the SCL low time is 160 ns; for 400 pF loading, + * the SCL low time is 320 ns. This register goes away and + * becomes read-only returning 0s if IC_MAX_SPEED_MODE != + * high.This register can be written only when */ + uint32_t : 16; + } I2C2_HS_SCL_LCNT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + + struct + { + __IM uint32_t R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer + * when it is empty by reading from the IC_DATA_CMD register. + * If the module is disabled (I2C_ENABLE[0]=0), this bit keeps + * its level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to 32 + * and an additional byte is received from an external I2C + * device. The controller acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the + * module is disabled (I2C_ENABLE[0]=0), this bit keeps its + * level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the + * RX_TL threshold in the I2C_RX_TL register. It is automatically + * cleared by hardware when buffer level goes below the threshold. + * If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is + * not full. So this bit is cleared once, the I2C_ENABLE bit + * 0 is programmed with a 0 regardless of the activity that + * continues. */ + __IM uint32_t R_TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled + * to 32 and the processor attempts to issue another I2C command + * by writing to the IC_DATA_CMD register. When the module + * is disabled, this bit keeps its level until the master + * or slave state machines go into idle, and when ic_en goes + * to 0, this interrupt is cleared */ + __IM uint32_t R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or + * below the threshold value set in the I2C_TX_TL register. + * It is automatically cleared by hardware when the buffer + * level goes above the threshold. When the IC_ENABLE bit + * 0 is 0, the TX FIFO is flushed and held in reset. There + * the TX FIFO looks like it has no data within it, so this + * bit is set to 1, provided there is activity in the master + * or slave state machines. When there is no longer activity, + * then with ic_en=0, this bit is set to 0. */ + __IM uint32_t R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when the controller is acting as + * a slave and another I2C master is attempting to read data + * from the controller. The controller holds the I2C bus in + * a wait state (SCL=0) until this interrupt is serviced, + * which means that the slave has been addressed by a remote + * master that is asking for data to be transferred. The processor + * must respond to this interrupt and then write the requested + * data to the I2C_DATA_CMD register. This bit is set to 0 + * just after the processor reads the I2C_CLR_RD_R */ + __IM uint32_t R_TX_ABRT : 1; /*!< [6..6] This bit indicates if the controller, as an I2C transmitter, + * is unable to complete the intended actions on the contents + * of the transmit FIFO. This situation can occur both as + * an I2C master or an I2C slave, and is referred to as a + * "transmit abort".When this bit is set to 1, the I2C_TX_ABRT_SOURCE + * register indicates the reason why the transmit abort takes + * places.NOTE: The controller flushes/resets/empties the + * TX FIFO whenever this bit is set. The TX FIFO remains in + * this flushed state until the regi */ + __IM uint32_t R_RX_DONE : 1; /*!< [7..7] When the controller is acting as a slave-transmitter, + * this bit is set to 1 if the master does not acknowledge + * a transmitted byte. This occurs on the last byte of the + * transmission, indicating that the transmission is done. */ + __IM uint32_t R_ACTIVITY : 1; /*!< [8..8] This bit captures I2C Ctrl activity and stays set until + * it is cleared. There are four ways to clear it:=> Disabling + * the I2C Ctrl=> Reading the IC_CLR_ACTIVITY register=> Reading + * the IC_CLR_INTR register=> System resetOnce this bit is + * set, it stays set unless one of the four methods is used + * to clear it. Even if the controller module is idle, this + * bit remains set until cleared, indicating that there was + * activity on the bus. */ + __IM uint32_t R_STOP_DET : 1; /*!< [9..9] Indicate whether a STOP condition has occurred on the + * I2C interface regardless of whether controller is operating + * in slave or master mode. */ + __IM uint32_t R_START_DET : 1; /*!< [10..10] Indicate whether a START or RESTART condition has occurred + * on the I2C interface regardless of whether controller is + * operating in slave or master mode. */ + __IM uint32_t R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and + * it is acknowledged. It stays set until it is cleared either + * by disabling controller or when the CPU reads bit 0 of + * the I2C_CLR_GEN_CALL register. The controller stores the + * received data in the RX buffer. */ + __IM uint32_t R_RESTART_DET : 1; /*!< [12..12] Indicate whether a RESTART condition has occurred on + * the I2C interface when DW_apb_i2c is operating in Slave + * mode and the slave is being addressed.Enabled only when + * IC_SLV_RESTART_DET_EN=1.Note: However, in high-speed mode + * or during a START BYTE transfer, the RESTART comes before + * the address field as per the I2C protocol. In this case, + * the slave is not the addressed slave when the RESTART is + * issued, therefore DW_apb_i2c does not generate the RESTART_DET + * interrupt. */ + __IM uint32_t R_MASTER_ON_HOLD : 1; /*!< [13..13] Indicate whether master is holding the bus and TX FIFO + * is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and + * IC_EMPTYFIFO_HOLD_MASTER_EN=1. */ + __IM uint32_t R_SCL_STUCK_AT_LOW : 1; /*!< [14..14] 1 = R_SCL_STUCK_AT_LOW interrupt is active.0 = R_SCL_STUCK_AT_LOW + * interrupt is inactive. */ + uint32_t : 17; + } I2C2_INTR_STAT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + + struct + { + __IOM uint32_t M_RX_UNDER : 1; /*!< [0..0] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_OVER : 1; /*!< [1..1] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_FULL : 1; /*!< [2..2] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_OVER : 1; /*!< [3..3] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_EMPTY : 1; /*!< [4..4] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RD_REQ : 1; /*!< [5..5] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_TX_ABRT : 1; /*!< [6..6] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RX_DONE : 1; /*!< [7..7] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_ACTIVITY : 1; /*!< [8..8] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_STOP_DET : 1; /*!< [9..9] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_START_DET : 1; /*!< [10..10] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_GEN_CALL : 1; /*!< [11..11] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_RESTART_DET : 1; /*!< [12..12] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IOM uint32_t M_MASTER_ON_HOLD : 1; /*!< [13..13] These bits mask their corresponding interrupt status + * bits in the I2C_INTR_STAT register. */ + __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] M_SCL_STUCK_AT_LOW Register field Reserved bits. */ + uint32_t : 17; + } I2C2_INTR_MASK_REG_b; + }; + + union + { + __IOM uint32_t I2C2_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ + + struct + { + __IM uint32_t RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer + * when it is empty by reading from the IC_DATA_CMD register. + * If the module is disabled (I2C_ENABLE[0]=0), this bit keeps + * its level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to 32 + * and an additional byte is received from an external I2C + * device. The controller acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the + * module is disabled (I2C_ENABLE[0]=0), this bit keeps its + * level until the master or slave state machines go into + * idle, and when ic_en goes to 0, this interrupt is cleared. */ + __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the + * RX_TL threshold in the I2C_RX_TL register. It is automatically + * cleared by hardware when buffer level goes below the threshold. + * If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is + * not full. So this bit is cleared once the I2C_ENABLE bit + * 0 is programmed with a 0, regardless of the activity that + * continues. */ + __IM uint32_t TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled + * to 32 and the processor attempts to issue another I2C command + * by writing to the IC_DATA_CMD register. When the module + * is disabled, this bit keeps its level until the master + * or slave state machines go into idle, and when ic_en goes + * to 0, this interrupt is cleared . */ + __IM uint32_t TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or + * below the threshold value set in the I2C_TX_TL register. + * It is automatically cleared by hardware when the buffer + * level goes above the threshold. When the IC_ENABLE bit + * 0 is 0, the TX FIFO is flushed and held in reset. There + * the TX FIFO looks like it has no data within it, so this + * bit is set to 1, provided there is activity in the master + * or slave state machines. When there is no longer activity, + * then with ic_en=0, this bit is set to 0. */ + __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when I2C Ctrl is acting as a slave + * and another I2C master is attempting to read data from + * the controller. The controller holds the I2C bus in a wait + * state (SCL=0) until this interrupt is serviced, which means + * that the slave has been addressed by a remote master that + * is asking for data to be transferred. The processor must + * respond to this interrupt and then write the requested + * data to the I2C_DATA_CMD register. This bit is set to 0 + * just after the processor reads the I2C_CLR_RD_REQ reg */ + __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if the controller, as an I2C transmitter, + * is unable to complete the intended actions on the contents + * of the transmit FIFO. This situation can occur both as + * an I2C master or an I2C slave, and is referred to as a + * "transmit abort".When this bit is set to 1, the I2C_TX_ABRT_SOURCE + * register indicates the reason why the transmit abort takes + * places.NOTE: The controller flushes/resets/empties the + * TX FIFO whenever this bit is set. The TX FIFO remains in + * this flushed state until the regi */ + __IM uint32_t RX_DONE : 1; /*!< [7..7] When the controller is acting as a slave-transmitter, + * this bit is set to 1 if the master does not acknowledge + * a transmitted byte. This occurs on the last byte of the + * transmission, indicating that the transmission is done. */ + __IM uint32_t ACTIVITY : 1; /*!< [8..8] This bit captures I2C Ctrl activity and stays set until + * it is cleared. There are four ways to clear it:=> Disabling + * the I2C Ctrl=> Reading the IC_CLR_ACTIVITY register=> Reading + * the IC_CLR_INTR register=> System resetOnce this bit is + * set, it stays set unless one of the four methods is used + * to clear it. Even if the controller module is idle, this + * bit remains set until cleared, indicating that there was + * activity on the bus. */ + __IM uint32_t STOP_DET : 1; /*!< [9..9] Indicate whether a STOP condition has occurred on the + * I2C interface regardless of whether controller is operating + * in slave or master mode. */ + __IM uint32_t START_DET : 1; /*!< [10..10] Indicate whether a START or RESTART condition has occurred + * on the I2C interface regardless of whether controller is + * operating in slave or master mode. */ + __IM uint32_t GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and + * it is acknowledged. It stays set until it is cleared either + * by disabling controller or when the CPU reads bit 0 of + * the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received + * data in the Rx buffer. */ + __IM uint32_t RESTART_DET : 1; /*!< [12..12] Indicate whether a RESTART condition has occurred on + * the I2C interface when DW_apb_i2c is operating in Slave + * mode and the slave is being addressed.Enabled only when + * IC_SLV_RESTART_DET_EN=1.Note: However, in high-speed mode + * or during a START BYTE transfer, the RESTART comes before + * the address field as per the I2C protocol. In this case, + * the slave is not the addressed slave when the RESTART is + * issued, therefore DW_apb_i2c does not generate the RESTART_DET + * interrupt. */ + __IM uint32_t MASTER_ON_HOLD : 1; /*!< [13..13] ndicate whether master is holding the bus and TX FIFO + * is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and + * IC_EMPTYFIFO_HOLD_MASTER_EN=1. */ + __IM uint32_t SCL_STUCK_AT_LOW : 1; /*!< [14..14] CL_STUCK_AT_LOW Register field Reserved bits. */ + uint32_t : 17; + } I2C2_RAW_INTR_STAT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + + struct + { + __IOM uint32_t RX_TL : 5; /*!< [4..0] Receive FIFO Threshold Level Controls the level of entries + * (or above) that triggers the RX_FULL interrupt (bit 2 in + * I2C_RAW_INTR_STAT register). The valid range is 0-31, with + * the additional restriction that hardware does not allow + * this value to be set to a value larger than the depth of + * the buffer. If an attempt is made to do that, the actual + * value set will be the maximum depth of the buffer. A value + * of 0 sets the threshold for 1 entry, and a value of 31 + * sets the threshold for 32 entries. */ + uint32_t : 27; + } I2C2_RX_TL_REG_b; + }; + + union + { + __IOM uint32_t I2C2_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TX_TL : 5; /*!< [4..0] Transmit FIFO Threshold Level Controls the level of entries + * (or below) that trigger the TX_EMPTY interrupt (bit 4 in + * I2C_RAW_INTR_STAT register). The valid range is 0-31, with + * the additional restriction that it may not be set to value + * larger than the depth of the buffer. If an attempt is made + * to do that, the actual value set will be the maximum depth + * of the buffer. A value of 0 sets the threshold for 0 entries, + * and a value of 31 sets the threshold for 32 entries. */ + uint32_t : 27; + } I2C2_TX_TL_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + + struct + { + __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined interrupt, all + * individual interrupts, and the I2C_TX_ABRT_SOURCE register. + * This bit does not clear hardware clearable interrupts but + * software clearable interrupts. See Bit 9 of the I2C_TX_ABRT_SOURCE + * register for an exception to clearing I2C_TX_ABRT_SOURCE. */ + uint32_t : 31; + } I2C2_CLR_INTR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear the RX_UNDER interrupt (bit + * 0) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_RX_UNDER_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the RX_OVER interrupt (bit + * 1) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_RX_OVER_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + + struct + { + __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the TX_OVER interrupt (bit + * 3) of the I2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_TX_OVER_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + + struct + { + __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the RD_REQ interrupt (bit + * 5) of the I2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_RD_REQ_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + + struct + { + __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT interrupt (bit + * 6) of theIC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE + * register. This also releases the TX FIFO from the flushed/reset + * state, allowing more writes to the TX FIFO. See Bit 9 of + * the I2C_TX_ABRT_SOURCE register for an exception to clearing + * IC_TX_ABRT_SOURCE. */ + uint32_t : 31; + } I2C2_CLR_TX_ABRT_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + + struct + { + __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the RX_DONE interrupt (bit + * 7) of theI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_RX_DONE_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + + struct + { + __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears the ACTIVITY interrupt if + * the I2C is not active anymore. If the I2C module is still + * active on the bus, the ACTIVITY interrupt bit continues + * to be set. It is automatically cleared by hardware if the + * module is disabled and if there is no further activity + * on the bus. The value read from this register to get status + * of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT + * register. */ + uint32_t : 31; + } I2C2_CLR_ACTIVITY_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + + struct + { + __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear the STOP_DET interrupt (bit + * 9) of the IC_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_STOP_DET_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + + struct + { + __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear the START_DET interrupt (bit + * 10) of the IC_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_START_DET_REG_b; + }; + + union + { + __IOM uint32_t I2C2_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + + struct + { + __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear the GEN_CALL interrupt (bit + * 11) ofI2C_RAW_INTR_STAT register. */ + uint32_t : 31; + } I2C2_CLR_GEN_CALL_REG_b; + }; + + union + { + __IOM uint32_t I2C2_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */ + + struct + { + __IOM uint32_t I2C_EN : 1; /*!< [0..0] Control whether the controller is enabled.0 = Disable + * the controller (TX and RX FIFOs are held in an erased state)1 + * = Enable the controllerSoftware can disable the controller + * while it is active. However, it is important that care + * be taken to ensure that the controller is disabled properly. + * When the controller is disabled, the following occurs:* + * The TX FIFO and RX FIFO get flushed.* Status bits in the + * IC_INTR_STAT register are still active until the controller + * goes into IDLE state. */ + __IOM uint32_t I2C_ABORT : 1; /*!< [1..1] The software can abort the I2C transfer in master mode + * by setting this bit. The software can set this bit only + * when ENABLE is already set; otherwise, the controller ignores + * any write to ABORT bit. The software cannot clear the ABORT + * bit once set. In response to an ABORT, the controller issues + * a STOP and flushes the TX FIFO after completing the current + * transfer, then sets the TX_ABORT interrupt after the abort + * operation. The ABORT bit is cleared automatically after + * the abort operation. */ + __IOM uint32_t I2C_TX_CMD_BLOCK : 1; /*!< [2..2] In Master mode:1 = Block the transmission of data on + * I2C bus even if TX FIFO has data to transmit.0.= The transmission + * of data starts on I2C bus automatically as soon as the + * first data is available in the TX FIFO. */ + uint32_t : 29; + } I2C2_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t I2C2_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */ + + struct + { + __IM uint32_t I2C_ACTIVITY : 1; /*!< [0..0] I2C Activity Status. */ + __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO Not Full. Set when the transmit FIFO contains + * one or more empty locations, and is cleared when the FIFO + * is full.0 = Transmit FIFO is full.1 = Transmit FIFO is + * not full. */ + __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty. When the transmit FIFO + * is completely empty, this bit is set. When it contains + * one or more valid entries, this bit is cleared. This bit + * field does not request an interrupt.0 = Transmit FIFO is + * not empty.1 = Transmit FIFO is empty. */ + __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO Not Empty. This bit is set when the receive + * FIFO contains one or more entries; it is cleared when the + * receive FIFO is empty.0 = Receive FIFO is empty.1 = Receive + * FIFO is not empty. */ + __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO Completely Full. When the receive FIFO is + * completely full, this bit is set. When the receive FIFO + * contains one or more empty location, this bit is cleared.0 + * = Receive FIFO is not full.1 = Receive FIFO is full. */ + __IM uint32_t MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status. When the Master Finite State + * Machine (FSM) is not in the IDLE state, this bit is set.0 + * = Master FSM is in IDLE state so the Master part of the + * controller is not Active.1 = Master FSM is not in IDLE + * state so the Master part of the controller is Active. */ + __IM uint32_t SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status. When the Slave Finite State + * Machine (FSM) is not in the IDLE state, this bit is set.0 + * = Slave FSM is in IDLE state so the Slave part of the controller + * is not Active.1 = Slave FSM is not in IDLE state so the + * Slave part of the controller is Active. */ + __IM uint32_t MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The DW_apb_i2c master stalls the write transfer when + * TX FIFO is empty, and the the last byte does not have the + * Stop bit set. This bit indicates the BUS hold when the + * master holds the bus because of the TX FIFO being empty, + * and the the previous transferred command does not have + * the Stop bit set.1 = Master holds the bus due to TX FIFO + * is empty.0 = Master is not holding the bus or Bus hold + * is not due to TX FIFO is empty. */ + __IM uint32_t MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold in Master mode due to + * RX FIFO is Full and additional byte is received.1 = Master + * holds the bus due to RX FIFO is full.0 = Master is not + * holding the bus or Bus hold is not due to RX FIFO is full. */ + __IM uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS Hold in Slave mode for the + * Read request when the TX FIFO is empty. The Bus is in hold + * until the TX FIFO has data to Transmit for the read request.1 + * = Slave holds the bus due to TX FIFO is empty.0 = Slave + * is not holding the bus or Bus hold is not due to TX FIFO + * is empty. */ + __IM uint32_t LV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS Hold in Slave mode due to + * RX FIFO is Full and an additional byte has been received.1 + * = Slave holds the bus due to Rx FIFO is full.0 = Slave + * is not holding the bus or Bus hold is not due to Rx FIFO + * is full. */ + uint32_t : 21; + } I2C2_STATUS_REG_b; + }; + + union + { + __IOM uint32_t I2C2_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + + struct + { + __IM uint32_t TXFLR : 6; /*!< [5..0] Transmit FIFO Level. Contain the number of valid data + * entries in the transmit FIFO. Size is constrained by the + * TXFLR value. */ + uint32_t : 26; + } I2C2_TXFLR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + + struct + { + __IM uint32_t RXFLR : 6; /*!< [5..0] Receive FIFO Level. Contain the number of valid data + * entries in the receive FIFO. Size is constrained by the + * RXFLR value. */ + uint32_t : 26; + } I2C2_RXFLR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + + struct + { + __IOM uint32_t I2C_SDA_TX_HOLD : 16; /*!< [15..0] Set the required SDA hold time in units of ic_clk period + * when transmitting. */ + __IOM uint32_t I2C_SDA_RX_HOLD : 8; /*!< [23..16] Set the required SDA hold time in units of ic_clk period + * when receiving. */ + uint32_t : 8; + } I2C2_SDA_HOLD_REG_b; + }; + + union + { + __IOM uint32_t I2C2_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ + + struct + { + __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] Master-Transmitter or Master-Receiver: Master is in 7-bit + * addressing mode and the address sent was not acknowledged + * by any slave.1 = This abort is generated because of NOACK + * for 7-bit address.0 = This abort is not generated. */ + __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< [1..1] Master-Transmitter or Master-Receiver: Master is in 10-bit + * address mode and the first 10-bit address byte was not + * acknowledged by any slave.1 = Byte 1 of 10-bit address + * not ACKed by any slave.0 = This abort is not generated. */ + __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< [2..2] Master-Transmitter or Master-Receiver: Master is in 10-bit + * address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave.1 = Byte 2 of + * 10-bit address not ACKed by any slave.0 = This abort is + * not generated. */ + __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< [3..3] Master-Transmitter: This is a master-mode only bit. Master + * has received an acknowledgement for the address, but when + * it sent data byte(s) following the address, it did not + * receive an acknowledge from the remote slave(s).1 = Transmitted + * data not ACKed by addressed slave.0 = Transmitted data + * non-ACKed by addressed slave-scenario not present. */ + __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< [4..4] Master-Transmitter: The controller in master mode sent + * a General Call and no slave on the bus acknowledged the + * General Call.1 = GCALL not ACKed by any slave.0 = GCALL + * not ACKed by any slave-scenario not present. */ + __IM uint32_t ABRT_GCALL_READ : 1; /*!< [5..5] Master-Transmitter: The controller in master mode sent + * a General Call but the user programmed the byte following + * the General Call to be a read from the bus (IC_DATA_CMD[9] + * is set to 1).1 = GCALL is followed by read from bus.0 = + * GCALL is followed by read from bus-scenario not present. */ + __IM uint32_t ABRT_HS_ACKDET : 1; /*!< [6..6] Master: Master is in High Speed mode and the High Speed + * Master code was acknowledged (wrong behavior).1 = HS Master + * code ACKed in HS Mode.0 = HS Master code ACKed in HS Mode- + * scenario not present. */ + __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< [7..7] Master: Master has sent a START Byte and the START Byte + * was acknowledged (wrong behavior). 1 = ACK detected for + * START byte.0 = ACK detected for START byte- scenario not + * present. */ + __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< [8..8] Master-Transmitter or Master-Receiver: The restart is + * disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user + * is trying to use the master to transfer data in High Speed + * mode.1 = User trying to switch Master to HS mode when RESTART + * disabled.0 = User trying to switch Master to HS mode when + * RESTART disabled- scenario not present. */ + __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] Master: To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT + * must be fixed first; restart must be enabled (I2C_CON[5]=1), + * the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START + * bit must be cleared (I2C_TAR[10]). Once the source of the + * ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared + * in the same manner as other bits in this register. If the + * source of the ABRT_SBYTE_NORSTRT is not fixed before attempting + * to clear this bit, bit 9 clears for one cycle and then + * gets re-asserted. 1: The res */ + __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] Master-Receiver: The restart is disabled (IC_RESTART_EN + * bit (I2C_CON[5]) = 0) and the master sends a read command + * in 10-bit addressing mode.1 = Master trying to read in + * 10-bit addressing mode when RESTART disabled.0 = Master + * not trying to read in 10-bit addressing mode when RESTART + * disabled. */ + __IM uint32_t ABRT_MASTER_DIS : 1; /*!< [11..11] Master-Transmitter or Master-Receiver: User tries to + * initiate a Master operation with the Master mode disabled.1 + * = User intitating master operation when MASTER disable.0 + * = User initiating master operation when MASTER disabled- + * scenario not present. */ + __IM uint32_t ARB_LOST : 1; /*!< [12..12] Master-Transmitter or Slave-Transmitter: Master has + * lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also + * set, then the slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same time.1 = Master + * or Slave-Transmitter lost arbitration.0 = Master or Slave-Transmitter + * lost arbitration- scenario not present. */ + __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] Slave-Transmitter: Slave has received a read command + * and some data exists in the TX FIFO so the slave issues + * a TX_ABRT interrupt to flush old data in TX FIFO.1 = Slave + * flushes existing data in TX-FIFO upon getting read command.0 + * = Slave flushes existing data in TX-FIFO upon getting read + * command- scenario not present. */ + __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< [14..14] Slave-Transmitter: Slave lost the bus while transmitting + * data to a remote master. I2C_TX_ABRT_SOURCE[12] is set + * at the same time. Note: Even though the slave never "owns" + * the bus, something could go wrong on the bus. This is a + * fail safe check. For instance, during a data transmission + * at the low-to-high transition of SCL, if what is on the + * data bus is not what is supposed to be transmitted, then + * the controller no longer own the bus.1 = Slave lost arbitration + * to remote master.0 = Slave lost arbitra */ + __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] Slave-Transmitter: When the processor side responds + * to a slave mode request for data to be transmitted to a + * remote master and a user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD + * register.1 = Slave trying to transmit to remote master + * in read mode.0 = Slave trying to transmit to remote master + * in read mode- scenario not present. */ + __IM uint32_t ABRT_USER_ABRT : 1; /*!< [16..16] Master-Transmitter: This is a master-mode-only bit. + * Master has detected the transfer abort (IC_ENABLE[1]). */ + uint32_t : 15; + } I2C2_TX_ABRT_SOURCE_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t I2C2_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */ + + struct + { + __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA Enable. This bit enables/disables the receive + * FIFO DMA channel.0 = Receive DMA disabled.1 = Receive DMA + * enabled. */ + __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable. This bit enables/disables the transmit + * FIFO DMA channel.0 = Transmit DMA disabled.1 = Transmit + * DMA enabled. */ + uint32_t : 30; + } I2C2_DMA_CR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + + struct + { + __IOM uint32_t DMATDL : 5; /*!< [4..0] Transmit Data Level. This bit field controls the level + * at which a DMA request is made by the transmit logic. It + * is equal to the watermark level; that is, the dma_tx_req + * signal is generated when the number of valid data entries + * in the transmit FIFO is equal to or below this field value, + * and TDMAE = 1. */ + uint32_t : 27; + } I2C2_DMA_TDLR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + + struct + { + __IOM uint32_t DMARDL : 5; /*!< [4..0] Receive Data Level. This bit field controls the level + * at which a DMA request is made by the receive logic. The + * watermark level = DMARDL+1; that is, dma_rx_req is generated + * when the number of valid data entries in the receive FIFO + * is equal to or more than this field value + 1, and RDMAE + * =1. For instance, when DMARDL is 0, then dma_rx_req is + * asserted when 1 or more data entries are present in the + * receive FIFO. */ + uint32_t : 27; + } I2C2_DMA_RDLR_REG_b; + }; + + union + { + __IOM uint32_t I2C2_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */ + + struct + { + __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] SDA Setup.This register controls the amount of time delay + * (number of I2C clock periods) between the rising edge of + * SCL and SDA changing by holding SCL low when I2C block + * services a read request while operating as a slave-transmitter. + * The relevant I2C requirement is tSU:DAT (note 4) as detailed + * in the I2C Bus Specification. This register must be programmed + * with a value equal to or greater than 2.It is recommended + * that if the required delay is 1000 ns, then for an I2C + * frequency of 10 MHz, IC_SDA_SE */ + uint32_t : 24; + } I2C2_SDA_SETUP_REG_b; + }; + + union + { + __IOM uint32_t I2C2_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */ + + struct + { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call. When set to 1, I2C Ctrl responds with + * a ACK (by asserting ic_data_oe) when it receives a General + * Call. When set to 0, the controller does not generate General + * Call interrupts.1 = Generate ACK for a General Call.0 = + * Generate NACK for General Call. */ + uint32_t : 31; + } I2C2_ACK_GENERAL_CALL_REG_b; + }; + + union + { + __IOM uint32_t I2C2_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */ + + struct + { + __IM uint32_t IC_EN : 1; /*!< [0..0] ic_en Status. This bit always reflects the value driven + * on the output port ic_en. When read as 1, the controller + * is deemed to be in an enabled state.When read as 0, the + * controller is deemed completely inactive.NOTE: The CPU + * can safely read this bit anytime. When this bit is read + * as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) + * and SLV_DISABLED_WHILE_BUSY (bit 1).1 = I2C enabled.0 = + * I2C disabled. */ + __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] Slave Disabled While Busy (Transmit, Receive). This bit + * indicates if a potential or active Slave operation has + * aborted due to the setting of the IC_ENABLE register from + * 1 to 0. This bit is set when the CPU writes a 0 to the + * IC_ENABLE register while:(a) I2C Ctrl is receiving the + * address byte of the Slave-Transmitter operation from a + * remote master; OR,(b) address and data bytes of the Slave-Receiver + * operation from a remote master. When read as 1, the controller + * is deemed to have forced a NACK durin */ + __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost. This bit indicates if a Slave-Receiver + * operation is aborted with at least one data byte received + * from an I2C transfer due to the setting of IC_ENABLE from + * 1 to 0. When read as 1, the controller is deemed to have + * actively engaged in an aborted I2C transfer (with matching + * address) and the data phase of the I2C transfer is entered, + * even though a data byte is responded with a NACK. NOTE: + * If the remote I2C master terminates the transfer with a + * STOP condition before the controller has */ + uint32_t : 29; + } I2C2_ENABLE_STATUS_REG_b; + }; + + union + { + __IOM uint32_t I2C2_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */ + + struct + { + __IOM uint32_t I2C_FS_SPKLEN : 8; /*!< [7..0] This register must be set before any I2C bus transaction + * can take place to ensure stable operation. This register + * sets the duration, measured in ic_clk cycles, of the longest + * spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written + * only when the I2C interface is disabled which corresponds + * to the IC_ENABLE register being set to 0. Write at other + * times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, */ + uint32_t : 24; + } I2C2_IC_FS_SPKLEN_REG_b; + }; + + union + { + __IOM uint32_t I2C2_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */ + + struct + { + __IOM uint32_t I2C_HS_SPKLEN : 8; /*!< [7..0] This register must be set before any I2C bus transaction + * can take place to ensure stable operation. This register + * sets the duration, measured in ic_clk cycles, of the longest + * spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written + * only when the I2C interface is disabled which corresponds + * to the IC_ENABLE[0] register being set to 0. Write at other + * times have no effect.The minimum valid value is 1; hardware + * prevents values less than this being wr */ + uint32_t : 24; + } I2C2_IC_HS_SPKLEN_REG_b; + }; + __IM uint32_t RESERVED1[19]; + + union + { + __IOM uint32_t I2C2_COMP_PARAM1_REG; /*!< (@ 0x000000F4) I2C2_COMP_PARAM1_REG */ + + struct + { + __IM uint32_t IC_COMP_PARAM1 : 32; /*!< [31..0] IC_COMP_PARAM1 */ + } I2C2_COMP_PARAM1_REG_b; + }; + + union + { + __IOM uint32_t I2C2_COMP_VERSION_REG; /*!< (@ 0x000000F8) I2C2_COMP_VERSION_REG */ + + struct + { + __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] IC_COMP_VERSION */ + } I2C2_COMP_VERSION_REG_b; + }; + + union + { + __IOM uint32_t I2C2_COMP_TYPE_REG; /*!< (@ 0x000000FC) I2C2_COMP_TYPE_REG */ + + struct + { + __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] IC_COMP_TYPE */ + } I2C2_COMP_TYPE_REG_b; + }; +} I2C2_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ KDMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief KDMA registers (KDMA) + */ + +typedef struct /*!< (@ 0x40070A00) KDMA Structure */ +{ + union + { + __IOM uint32_t KDMA_ENABLE_REG; /*!< (@ 0x00000000) Enable kDMA */ + + struct + { + __IOM uint32_t DMA_ENABLE : 1; /*!< [0..0] Write 1 : Enable DMAWrite 0 : Disable DMA */ + uint32_t : 31; + } KDMA_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t KDMA_RESET_REG; /*!< (@ 0x00000004) Software reset of kDMA */ + + struct + { + __IOM uint32_t DMA_RESET : 1; /*!< [0..0] Write 1 : Reset DMA, and automatically return to 0 */ + uint32_t : 31; + } KDMA_RESET_REG_b; + }; + + union + { + __IOM uint32_t KDMA_CFG_DESCRIPTOR_ADDR_REG; /*!< (@ 0x00000008) Base address of first task descriptor memory + * area */ + + struct + { + __IOM uint32_t CFG_DESCRIPTOR_ADDR : 32; /*!< [31..0] Base address of first task descriptor memory area */ + } KDMA_CFG_DESCRIPTOR_ADDR_REG_b; + }; + + union + { + __IOM uint32_t KDMA_CHANNEL_ENABLE_REG; /*!< (@ 0x0000000C) Enable the channel of kDMA */ + + struct + { + __IOM uint32_t CHANNEL_ENABLE : 12; /*!< [11..0] Enable DMA channel(1 : enable channel, 0 : disable channel) */ + uint32_t : 20; + } KDMA_CHANNEL_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t KDMA_IRQ_DONE_TYPE_REG; /*!< (@ 0x00000010) dma_done Interrupt type */ + + struct + { + __IOM uint32_t CHANNEL0_DONE_TYPE : 2; /*!< [1..0] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL1_DONE_TYPE : 2; /*!< [3..2] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL2_DONE_TYPE : 2; /*!< [5..4] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL3_DONE_TYPE : 2; /*!< [7..6] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL4_DONE_TYPE : 2; /*!< [9..8] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL5_DONE_TYPE : 2; /*!< [11..10] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL6_DONE_TYPE : 2; /*!< [13..12] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL7_DONE_TYPE : 2; /*!< [15..14] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL8_DONE_TYPE : 2; /*!< [17..16] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL9_DONE_TYPE : 2; /*!< [19..18] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL10_DONE_TYPE : 2; /*!< [21..20] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + __IOM uint32_t CHANNEL11_DONE_TYPE : 2; /*!< [23..22] dma_done interrupt type0 : dma_done interrupt enable + * when DMA chain is done1 : dma_done interrupt enable when + * DMA task is done2 : dma_done interrupt enable when REQ_MODE + * = 0 and arbitration period is ended3 : Reserved */ + uint32_t : 8; + } KDMA_IRQ_DONE_TYPE_REG_b; + }; + + union + { + __IOM uint32_t KDMA_SW_REQUEST_REG; /*!< (@ 0x00000014) kDMA software request */ + + struct + { + __OM uint32_t SW_REQUEST : 12; /*!< [11..0] Write 1 : send request signal, and automatically return + * to 0 */ + uint32_t : 20; + } KDMA_SW_REQUEST_REG_b; + }; + + union + { + __IOM uint32_t KDMA_IRQ_DONE_REG; /*!< (@ 0x00000018) Indicator of which channel invokes kdma_done */ + + struct + { + __IM uint32_t IRQ_DONE : 12; /*!< [11..0] Indicator of which channel invokes dma_done */ + uint32_t : 20; + } KDMA_IRQ_DONE_REG_b; + }; + + union + { + __IOM uint32_t KDMA_IRQ_DONE_CLR_REG; /*!< (@ 0x0000001C) Clear KDMA_IRQ_DONE */ + + struct + { + __OM uint32_t IRQ_DONE_CLR : 12; /*!< [11..0] Write 1 : clear KDMA_IRQ_DONE, and automatically return + * to 0 */ + uint32_t : 20; + } KDMA_IRQ_DONE_CLR_REG_b; + }; + + union + { + __IOM uint32_t KDMA_IRQ_ERR_REG; /*!< (@ 0x00000020) Indicator of which channel invokes kdma_err */ + + struct + { + __IM uint32_t IRQ_ERR : 12; /*!< [11..0] Indicator of which channel invokes dma_err */ + uint32_t : 20; + } KDMA_IRQ_ERR_REG_b; + }; + + union + { + __IOM uint32_t KDMA_IRQ_ERR_CLR_REG; /*!< (@ 0x00000024) Clear KDMA_IRQ_ERR */ + + struct + { + __OM uint32_t IRQ_ERR_CLR : 12; /*!< [11..0] Write 1 : clear KDMA_IRQ_ERR, and automatically return + * to 0 */ + uint32_t : 20; + } KDMA_IRQ_ERR_CLR_REG_b; + }; + + union + { + __IOM uint32_t KDMA_STATUS_REG; /*!< (@ 0x00000028) Current status of kDMA */ + + struct + { + __IM uint32_t PENDING_CH : 12; /*!< [11..0] Currently pending channel number */ + uint32_t : 4; + __IM uint32_t CURRENT_ACTIVE_CH : 4; /*!< [19..16] Currently active channel number */ + __IM uint32_t CURRENT_STATE : 4; /*!< [23..20] Current state on FSM */ + uint32_t : 8; + } KDMA_STATUS_REG_b; + }; + + union + { + __IOM uint32_t KDMA_STATUS_DESC_ADDR_REG; /*!< (@ 0x0000002C) Address of current task descriptor */ + + struct + { + __IM uint32_t ADDRESS : 32; /*!< [31..0] Address of current task descriptor */ + } KDMA_STATUS_DESC_ADDR_REG_b; + }; + + union + { + __IOM uint32_t KDMA_STATUS_COUNTER_REG; /*!< (@ 0x00000030) Counters of current DMA task */ + + struct + { + __IM uint32_t TRANSFER_DONE_COUNTER : 15; /*!< [14..0] The number of done transfer in current arbitration period */ + __IM uint32_t TRANSFER_LAST_FLAG : 1; /*!< [15..15] The flag to check whether the transfer is last in current + * arbitration period */ + __IM uint32_t ARB_DONE_COUNTER : 15; /*!< [30..16] The number of done arbitration period in current task */ + __IM uint32_t ARB_LAST_FLAG : 1; /*!< [31..31] The flag to check whether the arbitration is last period + * in current task */ + } KDMA_STATUS_COUNTER_REG_b; + }; + + union + { + __IOM uint32_t KDMA_STATUS_DESC_REG; /*!< (@ 0x00000034) Current task descriptor */ + + struct + { + __IM uint32_t TASK_DESCRIPTOR : 32; /*!< [31..0] Current task descriptor */ + } KDMA_STATUS_DESC_REG_b; + }; + + union + { + __IOM uint32_t KDMA_STATUS_DESC_ADDR_PRE_REG; /*!< (@ 0x00000038) Address of previous task descriptor */ + + struct + { + __IM uint32_t ADDRESS : 32; /*!< [31..0] Address of previous task descriptor */ + } KDMA_STATUS_DESC_ADDR_PRE_REG_b; + }; + + union + { + __IOM uint32_t KDMA_AHB_HPROT_3_TO_0_REG; /*!< (@ 0x0000003C) HPROT signal of AHB bus (Channel 0~3) */ + + struct + { + __IOM uint32_t CH0_DST_HPROT : 4; /*!< [3..0] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH0_SRC_HPROT : 4; /*!< [7..4] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH1_DST_HPROT : 4; /*!< [11..8] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH1_SRC_HPROT : 4; /*!< [15..12] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH2_DST_HPROT : 4; /*!< [19..16] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH2_SRC_HPROT : 4; /*!< [23..20] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH3_DST_HPROT : 4; /*!< [27..24] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH3_SRC_HPROT : 4; /*!< [31..28] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + } KDMA_AHB_HPROT_3_TO_0_REG_b; + }; + + union + { + __IOM uint32_t KDMA_AHB_HPROT_7_TO_4_REG; /*!< (@ 0x00000040) HPROT signal of AHB bus (Channel 4~7) */ + + struct + { + __IOM uint32_t CH4_DST_HPROT : 4; /*!< [3..0] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH4_SRC_HPROT : 4; /*!< [7..4] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH5_DST_HPROT : 4; /*!< [11..8] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH5_SRC_HPROT : 4; /*!< [15..12] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH6_DST_HPROT : 4; /*!< [19..16] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH6_SRC_HPROT : 4; /*!< [23..20] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH7_DST_HPROT : 4; /*!< [27..24] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH7_SRC_HPROT : 4; /*!< [31..28] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + } KDMA_AHB_HPROT_7_TO_4_REG_b; + }; + + union + { + __IOM uint32_t KDMA_AHB_HPROT_11_TO_8_REG; /*!< (@ 0x00000044) HPROT signal of AHB bus (Channel 8~11) */ + + struct + { + __IOM uint32_t CH8_DST_HPROT : 4; /*!< [3..0] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH8_SRC_HPROT : 4; /*!< [7..4] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH9_DST_HPROT : 4; /*!< [11..8] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH9_SRC_HPROT : 4; /*!< [15..12] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH10_DST_HPROT : 4; /*!< [19..16] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH10_SRC_HPROT : 4; /*!< [23..20] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH11_DST_HPROT : 4; /*!< [27..24] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + __IOM uint32_t CH11_SRC_HPROT : 4; /*!< [31..28] HPROT signal of AHB bus[3] : Modifiable (1: Cacheable, + * 0: Non-cacheable)[2] : Bufferable (1: Bufferable, 0: Non-bufferable)[1] + * : Privileged (1: Privileged, 0: User access)[0] : Data/Opcode + * (1: Data access, 0: Opcode fetch) */ + } KDMA_AHB_HPROT_11_TO_8_REG_b; + }; + + union + { + __IOM uint32_t KDMA_LLI_COUNTER_REG; /*!< (@ 0x00000048) kDMA software request */ + + struct + { + __IM uint32_t LLI_COUNTER : 16; /*!< [15..0] Total LLI count for the last transfer done, reset when + * the next transfer is started */ + __IM uint32_t LAST_DONE_CHANNEL : 4; /*!< [19..16] Last transfer done channel number, reset when the next + * transfer is started */ + uint32_t : 12; + } KDMA_LLI_COUNTER_REG_b; + }; +} KDMA_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ MEMCTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MEMCTRL registers (MEMCTRL) + */ + +typedef struct /*!< (@ 0x400B0800) MEMCTRL Structure */ +{ + union + { + __IOM uint32_t MEMCTRL_STALL_REG; /*!< (@ 0x00000000) Maximum Stall cycles Control Register */ + + struct + { + __IOM uint32_t AHB_CPUC_MAX_STALL : 4; /*!< [3..0] Maximum allowed number of stall cycles for the CPUC AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t AHB_CPUS_MAX_STALL : 4; /*!< [7..4] Maximum allowed number of stall cycles for the CPUS AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t AHB_DMA_MAX_STALL : 4; /*!< [11..8] Maximum allowed number of stall cycles for the DMA AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t WIFI_MAC_MAX_STALL : 4; /*!< [15..12] Maximum allowed number of stall cycles for the Wi-Fi + * MAC AHB interface. If exceeded, the interface will get + * high priority. Valid for a single access so the next access + * (of a burst) might end up in the queue for the same number + * of wait cycles.0: don't use, not feasible and can block + * other interfaces1: max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t WIFI_HSU_MAX_STALL : 4; /*!< [19..16] Maximum allowed number of stall cycles for the Wi-Fi + * HSU AHB interface. If exceeded, the interface will get + * high priority. Valid for a single access so the next access + * (of a burst) might end up in the queue for the same number + * of wait cycles.0: don't use, not feasible and can block + * other interfaces1: max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t CIS_MAX_STALL : 4; /*!< [23..20] Maximum allowed number of stall cycles for the SDIO + * CIS interface. If exceeded, the interface will get high + * priority. Valid for a single access so the next access + * (of a burst) might end up in the queue for the same number + * of wait cycles.0: don't use, not feasible and can block + * other interfaces1: max 1 stall cycle15: max 15 stall cycles */ + uint32_t : 8; + } MEMCTRL_STALL_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_STATUS_REG; /*!< (@ 0x00000004) RAM cells Status Register */ + + struct + { + __IOM uint32_t RAM0_OFF_BUT_ACCESS : 1; /*!< [0..0] Reading a '1' indicates RAM0 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM1_OFF_BUT_ACCESS : 1; /*!< [1..1] Reading a '1' indicates RAM1 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM2_OFF_BUT_ACCESS : 1; /*!< [2..2] Reading a '1' indicates RAM2 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM3_OFF_BUT_ACCESS : 1; /*!< [3..3] Reading a '1' indicates RAM3 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM4_OFF_BUT_ACCESS : 1; /*!< [4..4] Reading a '1' indicates RAM4 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM5_OFF_BUT_ACCESS : 1; /*!< [5..5] Reading a '1' indicates RAM5 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM6_OFF_BUT_ACCESS : 1; /*!< [6..6] Reading a '1' indicates RAM6 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM7_OFF_BUT_ACCESS : 1; /*!< [7..7] Reading a '1' indicates RAM7 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM8_OFF_BUT_ACCESS : 1; /*!< [8..8] Reading a '1' indicates RAM8 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM9_OFF_BUT_ACCESS : 1; /*!< [9..9] Reading a '1' indicates RAM9 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM10_OFF_BUT_ACCESS : 1; /*!< [10..10] Reading a '1' indicates RAM10 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM11_OFF_BUT_ACCESS : 1; /*!< [11..11] Reading a '1' indicates RAM11 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM12_OFF_BUT_ACCESS : 1; /*!< [12..12] Reading a '1' indicates RAM12 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM13_OFF_BUT_ACCESS : 1; /*!< [13..13] Reading a '1' indicates RAM13 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM14_OFF_BUT_ACCESS : 1; /*!< [14..14] Reading a '1' indicates RAM14 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM15_OFF_BUT_ACCESS : 1; /*!< [15..15] Reading a '1' indicates RAM15 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM16_OFF_BUT_ACCESS : 1; /*!< [16..16] Reading a '1' indicates RAM16 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM17_OFF_BUT_ACCESS : 1; /*!< [17..17] Reading a '1' indicates RAM17 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM18_OFF_BUT_ACCESS : 1; /*!< [18..18] Reading a '1' indicates RAM18 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM19_OFF_BUT_ACCESS : 1; /*!< [19..19] Reading a '1' indicates RAM19 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM20_OFF_BUT_ACCESS : 1; /*!< [20..20] Reading a '1' indicates RAM20 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM21_OFF_BUT_ACCESS : 1; /*!< [21..21] Reading a '1' indicates RAM21 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM22_OFF_BUT_ACCESS : 1; /*!< [22..22] Reading a '1' indicates RAM22 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM23_OFF_BUT_ACCESS : 1; /*!< [23..23] Reading a '1' indicates RAM23 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + uint32_t : 8; + } MEMCTRL_STATUS_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_PRIO_ARB_REG; /*!< (@ 0x00000008) Priority Control Register for RAM cells from + * 0 to 23 */ + + struct + { + __IOM uint32_t PRIO_ARB_CPUC_RAM : 2; /*!< [1..0] Priority of RAM0~RAM23 for the CPUC AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_CPUS_RAM : 2; /*!< [3..2] Priority of RAM0~RAM23 for the CPUS AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_DMA_RAM : 2; /*!< [5..4] Priority of RAM0~RAM23 for the DMA AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_WIFI_MAC_RAM : 2; /*!< [7..6] Priority of RAM0~RAM23 for the Wi-Fi MAC AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_WIFI_HSU_RAM : 2; /*!< [9..8] Priority of RAM0~RAM23 for the Wi-Fi HSU AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_CIS_RAM : 2; /*!< [11..10] Priority of RAM0~RAM23 for the SDIO CIS interface.00: + * low priority01: mid priority (default)1x: highest */ + uint32_t : 20; + } MEMCTRL_PRIO_ARB_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_STATIC_CLK_OFF_REG; /*!< (@ 0x0000000C) Memory Static Clock Off register */ + + struct + { + __IOM uint32_t SRAM0 : 1; /*!< [0..0] Static clock off - SRAM0 */ + __IOM uint32_t SRAM1 : 1; /*!< [1..1] Static clock off - SRAM1 */ + __IOM uint32_t SRAM2 : 1; /*!< [2..2] Static clock off - SRAM2 */ + __IOM uint32_t SRAM3 : 1; /*!< [3..3] Static clock off - SRAM3 */ + __IOM uint32_t SRAM4 : 1; /*!< [4..4] Static clock off - SRAM4 */ + __IOM uint32_t SRAM5 : 1; /*!< [5..5] Static clock off - SRAM5 */ + __IOM uint32_t SRAM6 : 1; /*!< [6..6] Static clock off - SRAM6 */ + __IOM uint32_t SRAM7 : 1; /*!< [7..7] Static clock off - SRAM7 */ + __IOM uint32_t SRAM8 : 1; /*!< [8..8] Static clock off - SRAM8 */ + __IOM uint32_t SRAM9 : 1; /*!< [9..9] Static clock off - SRAM9 */ + __IOM uint32_t SRAM10 : 1; /*!< [10..10] Static clock off - SRAM10 */ + __IOM uint32_t SRAM11 : 1; /*!< [11..11] Static clock off - SRAM11 */ + __IOM uint32_t SRAM12 : 1; /*!< [12..12] Static clock off - SRAM12 */ + __IOM uint32_t SRAM13 : 1; /*!< [13..13] Static clock off - SRAM13 */ + __IOM uint32_t SRAM14 : 1; /*!< [14..14] Static clock off - SRAM14 */ + __IOM uint32_t SRAM15 : 1; /*!< [15..15] Static clock off - SRAM15 */ + __IOM uint32_t SRAM16 : 1; /*!< [16..16] Static clock off - SRAM16 */ + __IOM uint32_t SRAM17 : 1; /*!< [17..17] Static clock off - SRAM17 */ + __IOM uint32_t SRAM18 : 1; /*!< [18..18] Static clock off - SRAM18 */ + __IOM uint32_t SRAM19 : 1; /*!< [19..19] Static clock off - SRAM19 */ + __IOM uint32_t SRAM20 : 1; /*!< [20..20] Static clock off - SRAM20 */ + __IOM uint32_t SRAM21 : 1; /*!< [21..21] Static clock off - SRAM21 */ + __IOM uint32_t SRAM22 : 1; /*!< [22..22] Static clock off - SRAM22 */ + __IOM uint32_t SRAM23 : 1; /*!< [23..23] Static clock off - SRAM23 */ + uint32_t : 8; + } MEMCTRL_STATIC_CLK_OFF_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_DYNAMIC_CLK_ON_REG; /*!< (@ 0x00000010) Memory Dynamic Clock On register */ + + struct + { + __IOM uint32_t AHB2MEM : 1; /*!< [0..0] Dynamic clock on - AHB2MEM */ + __IOM uint32_t ARBITER : 1; /*!< [1..1] Dynamic clock on - Arbiters */ + uint32_t : 1; + __IOM uint32_t MMI2MEM : 1; /*!< [3..3] Dynamic clock on - MMI2MEM */ + uint32_t : 1; + __IOM uint32_t MEM_UNIT : 1; /*!< [5..5] Dynamic clock on - Memory Units */ + uint32_t : 26; + } MEMCTRL_DYNAMIC_CLK_ON_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_MST_CLK_EN_REG; /*!< (@ 0x00000014) Memory Master Clock En register */ + + struct + { + __IOM uint32_t MST_CPUC_CLK_EN : 1; /*!< [0..0] Clock Enable for memctrl's master - CPUCIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_CPUS_CLK_EN : 1; /*!< [1..1] Clock Enable for memctrl's master - CPUSIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_DMA_CLK_EN : 1; /*!< [2..2] Clock Enable for memctrl's master - DMAIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_WIFI_MAC_CLK_EN : 1; /*!< [3..3] Clock Enable for memctrl's master - Wi-Fi MACIf this + * value is 0, memctrl's master to memory interface conversion + * block's clock is off. */ + __IOM uint32_t MST_WIFI_HSU_CLK_EN : 1; /*!< [4..4] Clock Enable for memctrl's master - Wi-Fi HSUIf this + * value is 0, memctrl's master to memory interface conversion + * block's clock is off. */ + __IOM uint32_t MST_CIS_CLK_EN : 1; /*!< [5..5] Clock Enable for memctrl's master - SDIO CISIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + uint32_t : 26; + } MEMCTRL_MST_CLK_EN_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_SYS_ARB_REG; /*!< (@ 0x00000018) APB_SYS ICM Priority level */ + + struct + { + __IOM uint32_t APB_AHB_DMA_PRIO : 1; /*!< [0..0] priority AHB_DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t APB_AHB_CPUS_PRIO : 1; /*!< [1..1] priority AHB_CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } MEMCTRL_SYS_ARB_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_AUD_ARB_REG; /*!< (@ 0x0000001C) APB_AUDIO ICM Priority level */ + + struct + { + __IOM uint32_t APB_AHB_DMA_PRIO : 1; /*!< [0..0] priority AHB_DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t APB_AHB_CPUS_PRIO : 1; /*!< [1..1] priority AHB_CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } MEMCTRL_AUD_ARB_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_CC312_ARB_REG; /*!< (@ 0x00000020) APB_CC312 ICM Priority level */ + + struct + { + __IOM uint32_t APB_AHB_DMA_PRIO : 1; /*!< [0..0] priority AHB_DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t APB_AHB_CPUS_PRIO : 1; /*!< [1..1] priority AHB_CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } MEMCTRL_CC312_ARB_REG_b; + }; + + union + { + __IOM uint32_t MEMCTRL_CIS_BASE_ADDR_REG; /*!< (@ 0x00000024) MEMCTRL_CIS_BASE_ADDR_REG */ + + struct + { + __IOM uint32_t MEM_CIS_BASE_ADDR : 23; /*!< [22..0] Base address of SDIO CIS interface.Full_32bit_address + * = { MEM_CIS_BASE_ADDR[22:0], cis_addr[6:0], 2'b00 };So + * Full_32bit_address [31:9] = MEM_CIS_BASE_ADDR[22:0];ex1) + * When MEM_CIS_BASE_ADDR[22:0] = 0x10057E (reset value)Then + * Full_32bit_address base address by MEM_CIS_BASE_ADDR is + * 0x200A_FC00.Full_32bit_address = 0x200A_FC00 When cis_addr[6:0] + * = 0x00.Full_32bit_address = 0x200A_FDFC When cis_addr[6:0] + * = 0x7F.So, Full_32bit_address range is 0x200AFC00 ~ 0x200AFDFF.ex2 */ + uint32_t : 9; + } MEMCTRL_CIS_BASE_ADDR_REG_b; + }; +} MEMCTRL_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ OQSPIF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief OQSPIF registers (OQSPIF) + */ + +typedef struct /*!< (@ 0x29000000) OQSPIF Structure */ +{ + union + { + __IOM uint32_t OQSPIF_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for the Manual mode */ + + struct + { + __OM uint32_t OSPIC_SET_SINGLE : 1; /*!< [0..0] Write 1 to set the bus mode in Single SPI mode, when + * the controller is in Manual mode. */ + __OM uint32_t OSPIC_SET_DUAL : 1; /*!< [1..1] Write 1 to set the bus mode in Dual mode, when the controller + * is in Manual mode. */ + __OM uint32_t OSPIC_SET_QUAD : 1; /*!< [2..2] Write 1 to set the bus mode in Quad mode, when the controller + * is in Manual mode. */ + __OM uint32_t OSPIC_SET_OCTAL : 1; /*!< [3..3] Write 1 to set the bus mode in Octal mode, when the controller + * is in Manual mode. */ + __OM uint32_t OSPIC_EN_CS : 1; /*!< [4..4] Write 1 to enable the chip select (active low), when + * the controller is in Manual mode. */ + __OM uint32_t OSPIC_DIS_CS : 1; /*!< [5..5] Write 1 to disable the chip select (active low), when + * the controller is in Manual mode. */ + uint32_t : 26; + } OQSPIF_CTRLBUS_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTRLMODE_REG; /*!< (@ 0x00000004) Mode Control register */ + + struct + { + __IOM uint32_t OSPIC_AUTO_MD : 1; /*!< [0..0] Mode of operation.0: Manual mode is selected.1: Auto + * mode is selected.While erasing, the OSPIC_AUTO_MD goes + * in Read-only mode (see OSPIC_ERASE_EN). */ + __IOM uint32_t OSPIC_CLK_MD : 1; /*!< [1..1] Mode of the generated OSPI_SCK clock.0: Use Mode 0 for + * the OSPI_CLK. The OSPI_SCK is low when OSPI_CS is high.1: + * Use Mode 3 for the OSPI_CLK. The OSPI_SCK is high when + * OSPI_CS is high. */ + __IOM uint32_t OSPIC_IO2_OEN : 1; /*!< [2..2] Force the output enable of the OSPI_IO2. Set this bit + * to 1 only in SPI or Dual SPI mode to control the /WP signal. + * When the Quad or Octal SPI is enabled in the flash device, + * set this bit to zero.0: The OSPI_IO2 pad direction is decided + * by the controller.1: The OSPI_IO2 pad is output. The output + * value is defined by the OSPIC_IO2_DAT. */ + __IOM uint32_t OSPIC_IO3_OEN : 1; /*!< [3..3] Force the output enable of the OSPI_IO3. Set this bit + * to 1 only in SPI or Dual SPI mode to control the /HOLD + * signal. When the Quad or Octal SPI is enabled in the flash + * device, set this bit to zero.0: The OSPI_IO3 pad direction + * is decided by the controller.1: The OSPI_IO3 pad is output. + * The output value is defined by the OSPIC_IO3_DAT. */ + __IOM uint32_t OSPIC_IO2_DAT : 1; /*!< [4..4] The value of OSPI_IO2 pad if OSPI_IO2_OEN is 1. */ + __IOM uint32_t OSPIC_IO3_DAT : 1; /*!< [5..5] The value of OSPI_IO3 pad if OSPI_IO3_OEN is 1. */ + __IOM uint32_t OSPIC_HRDY_MD : 1; /*!< [6..6] This configuration bit is useful when the frequency of + * the OSPI clock is lower than that of the AMBA bus, to avoid + * locking the AMBA bus for an extended period.0: Add wait + * states through hready signal when an access is performed + * on the OSPIC_CTRLBUS_REG, OSPIC_WRITEDATA, OSPIC_READDATA + * and OSPIC_DUMMYDATA registers. It is not needed to check + * the OSPIC_BUSY of the OSPIC_STATUS_REG.1: The controller + * does not add wait states through the hready signal when + * is performed access on the OSPIC_CTRLBUS_REG, */ + __IOM uint32_t OSPIC_RXD_NEG : 1; /*!< [7..7] Define the clock edge that is used for the capturing + * of the received data, when the read pipe is not active + * (OSPIC_RPIPE_EN = 0).0: Sampling of the received data with + * the positive edge of the OSPI_SCK.1: Sampling of the received + * data with the negative edge of the OSPI_SCK.The internal + * OSPI_SCK clock that is used by the controller for the capturing + * of the received data has a skew in respect of the OSPI_SCK + * that is received by the external memory device.To improve + * the timing requirements of the */ + __IOM uint32_t OSPIC_RPIPE_EN : 1; /*!< [8..8] Control the use of the data read pipe.0: The read pipe + * is disabled. The sampling clock is defined according to + * the OSPIC_RXD_NEG setting.1: The read pipe is enabled. + * The delay of the sampling clock is defined according to + * the OSPICI_PCLK_MD setting (recommended). */ + __IOM uint32_t OSPIC_PCLK_MD : 3; /*!< [11..9] Read pipe clock delay relative to the falling edge of + * OSPI_SCK.See OSPI Timing for timing parameters and recommended + * 0-7 values. */ + __IOM uint32_t OSPIC_BUF_LIM_EN : 1; /*!< [12..12] This bit has meaning only for the read in Auto mode. + * Defines the behavior of the controller when the internal + * buffer is full and there are more data to be retrieved + * for the current burst.0: The access in the flash device + * is not terminated when the internal buffer has no empty + * space. In this case the OSPI_SCK clock is blocked until + * to free space in the internal buffer.1: The access in the + * flash device is terminated when the internal buffer has + * no empty space. A new access in the flash device is in */ + __IOM uint32_t OSPIC_USE_32BA : 1; /*!< [13..13] Controls the length of the address that the external + * memory device uses.0: The external memory device uses 24 + * bits address.1: The external memory device uses 32 bits + * address.The controller uses this bit in order to decide + * the number of the address bytes that has to transfer to + * the external device during Auto mode. */ + __IOM uint32_t OSPIC_CMD_X2_EN : 1; /*!< [14..14] Define the number of bytes that consist the instruction + * code in the command sequences that produced by the OSPIC + * during Auto mode.0: The instruction code is one byte only.1: + * The instruction code is two bytes. The second byte of the + * instruction code is the inverse of the first byte.The command + * sequence that is produced by the OSPIC_BURSTBRK_REG is + * not affected by this setting. */ + __IOM uint32_t OSPIC_DMY_MD : 1; /*!< [15..15] Define the clock cycle where the bus turns in Hi-Z + * during the transmission of dummy bytes. This is applicable + * in both Manual and Auto mode.0: The bus becomes Hi-Z on + * the last clock.1: The bus becomes Hi-Z on the last two + * clocks. */ + __IOM uint32_t OSPIC_MAN_DIRCHG_MD : 1; /*!< [16..16] Selection of the direction change method in Manual + * mode.0: The bus direction goes to input after each access.1: + * The bus direction goes to input only after a dummy access. */ + __IOM uint32_t OSPIC_RD_ERR_EN : 1; /*!< [17..17] Controls the generation of AHB bus error response when + * a read is performed in the address space where the flash + * device is mapped and Auto mode is not enabled.0: The controller + * ignores the access. There is no error response due to the + * read access.1: The controller responds with an AHB error + * response. */ + __IOM uint32_t OSPIC_INC_LIM_EN : 1; /*!< [18..18] This bit has meaning only for the read in Auto mode + * and only when the read access in the AHB bus is an incremental + * burst of unspecified length.0: The length of the burst + * is considered as unspecified. The access in the flash device + * is implemented as is defined by the OSPIC BUF_LIM_EN bit.1: + * The length of the burst is considered as equal to 8 bytes. + * The access in the flash device is implemented by the controller + * as one or more different bursts, until to be served the + * access in the AHB bus. Each bur */ + uint32_t : 8; + __IOM uint32_t OSPIC_IO_UH_OEN : 1; /*!< [27..27] Forces the output enable for the upper half of the + * OSPI bus (OSPI_IO4-7). Set this bit to 1 only in SPI, Dual + * or Quad SPI mode to control the upper half of the OSPI + * bus. When the Octal SPI is enabled in the flash device, + * set this bit to zero.0: The OSPI_IO4-7 pad direction is + * decided by the controller.1: The OSPI_IO4-7 pad are outputs. + * The output values are defined by the corresponding OSPIC_IO_UH_DAT + * bits. */ + __IOM uint32_t OSPIC_IO_UH_DAT : 4; /*!< [31..28] The value of OSPI_IO4-7 pads if OSPI_IO_UH_OEN is 1. */ + } OQSPIF_CTRLMODE_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_RECVDATA_REG; /*!< (@ 0x00000008) Received data for the Manual mode */ + + struct + { + __IM uint32_t OSPIC_RECVDATA : 32; /*!< [31..0] This register contains the received data when the OSPIC_READDATA_REG + * register is used in Manual mode, to retrieve data from + * the external memory device and OSPIC_HRDY_MD=1 && OSPIC_BUSY=0. */ + } OQSPIF_RECVDATA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register + * A) */ + + struct + { + __IOM uint32_t OSPIC_INST : 8; /*!< [7..0] Instruction value for Incremental Burst or Single read + * access. This value is the selected instruction at the cases + * of incremental burst or single read access. Also this value + * is used when a wrapping burst is not supported (OSPIC_WRAP_MD) */ + __IOM uint32_t OSPIC_INST_WB : 8; /*!< [15..8] Instruction value for Wrapping Burst. This value is + * the selected instruction when OSPIC_WRAP_MD is equal to + * 1 and the access is a wrapping burst of length and size + * described by the bit fields OSPIC_WRAP_LEN and OSPIC_WRAP_SIZE + * respectively. */ + __IOM uint32_t OSPIC_EXT_BYTE : 8; /*!< [23..16] The value of an extra byte which is transferred after + * address (only if OSPIC_EXT_BYTE_EN= 1). Usually it is the + * Mode Bits in Dual/Quad/Octal SPI I/O instructions. */ + __IOM uint32_t OSPIC_INST_TX_MD : 2; /*!< [25..24] It describes the mode of the SPI bus during the Instruction + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_ADR_TX_MD : 2; /*!< [27..26] It describes the mode of the SPI bus during the address + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_EXT_TX_MD : 2; /*!< [29..28] It describes the mode of the SPI bus during the Extra + * bytes phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_DMY_TX_MD : 2; /*!< [31..30] It describes the mode of the SPI bus during the Dummy + * bytes phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + } OQSPIF_BURSTCMDA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register + * B) */ + + struct + { + __IOM uint32_t OSPIC_DAT_RX_MD : 2; /*!< [1..0] It describes the mode of the SPI bus during the data + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_EXT_BYTE_EN : 1; /*!< [2..2] Extra byte enable0: Do not send the OSPIC_EXT_BYTE1: + * Send the OSPIC_EXT_BYTE */ + __IOM uint32_t OSPIC_EXT_HF_DS : 1; /*!< [3..3] Extra half disable output.0: If OSPIC_EXT_BYTE_EN=1, + * then transmit the complete OSPIC_EXT_BYTE.1: If OSPIC_EXT_BYTE_EN=1, + * then the output is disabled (Hi-Z) during the transmission + * of bits [3:0] of OSPIC_EXT_BYTE.This setting has no meaning + * if the extra byte is transferred in Octal mode. In this + * case keep this bit to zero value. */ + __IOM uint32_t OSPIC_DMY_NUM : 5; /*!< [8..4] Number of dummy bytes (minus 1). Can be set 1-32 dummy + * bytes (o-31 values). The dummy bytes are appied only when + * OSPIC_DMY_EN=1. */ + __IOM uint32_t OSPIC_DMY_EN : 1; /*!< [9..9] Dummy bytes enable0: Do not send the dummy bytes1: Send + * the dummy bytes. The number of the dummy bytes is defined + * by the OSPIC_DMY_NUM. */ + __IOM uint32_t OSPIC_INST_MD : 1; /*!< [10..10] Instruction mode0: Transmit instruction at any burst + * access.1: Transmit instruction only in the first access + * after the selection of Auto mode. */ + __IOM uint32_t OSPIC_WRAP_MD : 1; /*!< [11..11] Wrap mode0: The OSPIC_INST is the selected instruction + * at any access.1: The OSPIC_INST_WB is the selected instruction + * at any wrapping burst access of length and size described + * by the registers OSPIC_WRAP_LEN and OSPIC_WRAP_SIZE respectively. + * In all other cases the OSPIC_INST is the selected instruction. + * Use this feature only when the serial FLASH memory supports + * a special instruction for wrapping burst access. */ + __IOM uint32_t OSPIC_WRAP_LEN : 2; /*!< [13..12] It describes the selected length of a wrapping burst + * (OSPIC_WRAP_MD).0x0: 4-beat wrapping burst0x1: 8-beat wrapping + * burst0x2: 16-beat wrapping burst0x3: Reserved */ + __IOM uint32_t OSPIC_WRAP_SIZE : 2; /*!< [15..14] It describes the selected data size of a wrapping burst + * (OSPIC_WRAP_MD).0x0: Byte access (8-bit)0x1: Half word + * access (16-bit)0x2: Word access (32-bit)0x3: Reserved */ + __IOM uint32_t OSPIC_CS_HIGH_MIN : 3; /*!< [18..16] Between the transmissions of two different instructions + * to the flash memory, the SPI bus stays in idle state (OSPI_CS + * high) for at least this number of OSPI_SCK clock cycles. + * See the OSPIC_ERS_CS_HI register for some exceptions. */ + uint32_t : 13; + } OQSPIF_BURSTCMDB_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_STATUS_REG; /*!< (@ 0x00000014) The status register of the OSPI controller */ + + struct + { + __IM uint32_t OSPIC_BUSY : 1; /*!< [0..0] The status of the SPI Bus.0: The SPI Bus is idle1: The + * SPI Bus is active. Read data, write data or dummy data + * activity is in progress.Has meaning only in Manual mode + * and only when OSPIC_HRDY_MD = 1. */ + uint32_t : 31; + } OQSPIF_STATUS_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode */ + + struct + { + __OM uint32_t OSPIC_WRITEDATA : 32; /*!< [31..0] Writing to this register is generating a data transfer + * from the controller to the external memory device. The + * data written in this register, is then transferred to the + * memory using the selected mode of the SPI bus (Single SPI, + * Dual SPI, Quad SPI or Octal SPI). The data size of the + * access to this register can be 32-bit/16-bit/8-bit and + * is equal to the number of the transferred bits.This register + * has meaning only when the controller is in Manual mode. */ + } OQSPIF_WRITEDATA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode */ + + struct + { + __IM uint32_t OSPIC_READDATA : 32; /*!< [31..0] A read access at this register generates a data transfer + * from the external memory device to the OSPIC controller. + * The data is transferred using the selected mode of the + * SPI bus (Single SPI, Dual SPI, Quad SPI or Octal SPI). + * The data size of the access to this register can be 32-bit/16-bit/8-bit + * and is equal to the number of the transferred bits.This + * register has meaning only when the controller is in Manual + * mode. */ + } OQSPIF_READDATA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode */ + + struct + { + __OM uint32_t OSPIC_DUMMYDATA : 32; /*!< [31..0] Writing to this register generates a number of clock + * pulses to the SPI bus. During the last clock of this activity + * in the SPI bus, the OSPI_IOx data pads are in Hi-Z state + * (see also the OSPIC_DMY_MD). The data size of the access + * to this register can be 32-bit/16-bit/8-bit. The number + * of generated pulses is equal to: (size of AHB bus access)/(size + * of SPI bus). The size of SPI bus is equal to 1, 2, 4 or + * 8 for Single, Dual, Quad or Octal SPI mode respectively.This + * register has meaning only when the cont */ + } OQSPIF_DUMMYDATA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_ERASECTRL_REG; /*!< (@ 0x00000024) OSPI Erase control register */ + + struct + { + uint32_t : 4; + __IOM uint32_t OSPIC_ERS_ADDR : 20; /*!< [23..4] Defines the address of the block/sector that is requested + * to be erased.If OSPIC_USE_32BA = 0 (24 bits addressing), + * bits OSPIC_ERASECTRL_REG[23-12] determine the block/sector + * address bits [23-12]. The OSPIC_ERASECTRL_REG[11-4] are + * ignored by the controller.If OSPIC_USE_32BA = 1 (32 bits + * addressing) bits OSPIC_ERASECTRL_REG[23-4] determine the + * block/sectors address bits [31:12] */ + __IOM uint32_t OSPIC_ERASE_EN : 1; /*!< [24..24] During Manual mode (OSPIC_AUTO_MD = 0). This bit is + * in Read-only mode.During Auto mode (OSPIC_AUTO_MD = 1). + * To request the erasing of the block/sector (OSPIC_ERS_ADDR, + * 12'b0) write 1 to this bit. This bit is cleared automatically + * with the end of the erasing. Until the end of erasing the + * OSPIC_ERASE_EN remains in Read-only mode. During the same + * time interval the controller remains in Auto mode (OSPIC_AUTO_MD + * goes in Read-only mode). */ + __IM uint32_t OSPIC_ERS_STATE : 3; /*!< [27..25] It shows the progress of sector/block erasing (read-only).0x0: + * No Erase.0x1: Pending erase request0x2: Erase procedure + * is running0x3: Suspended Erase procedure0x4: Finishing + * the Erase procedure0x5..0x7: Reserved */ + __IOM uint32_t OSPIC_ERS_RES_DIS : 1; /*!< [28..28] This configuration bit has meaning when an erase is + * suspended. Normally the erase is resumed when the flash + * stays idle (without read accesses) for a predefined number + * of clock cycles (see OSPIC_ERASECMDB_REG [OSPIC_ERSRES_HLD]). + * By setting this bit the execution of the erase resume process + * can be postponed.0: A suspended erase is resumed based + * on the setting in the OSPIC_ERSRES_HLD.1: The erase is + * not resumed even after the expiration of the OSPIC_ERSRES_HLD. + * The erase can be resumed again only w */ + uint32_t : 3; + } OQSPIF_ERASECTRL_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register + * A) */ + + struct + { + __IOM uint32_t OSPIC_ERS_INST : 8; /*!< [7..0] The code value of the erase instruction. */ + __IOM uint32_t OSPIC_WEN_INST : 8; /*!< [15..8] The code value of the write enable instruction. */ + __IOM uint32_t OSPIC_SUS_INST : 8; /*!< [23..16] The code value of the erase suspend instruction. */ + __IOM uint32_t OSPIC_RES_INST : 8; /*!< [31..24] The code value of the erase resume instruction */ + } OQSPIF_ERASECMDA_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register + * B) */ + + struct + { + __IOM uint32_t OSPIC_ERS_TX_MD : 2; /*!< [1..0] The mode of the OSPI Bus during the instruction phase + * of the erase instruction.0x0: Single0x1: Dual0x2: Quad0x3: + * Octal */ + __IOM uint32_t OSPIC_WEN_TX_MD : 2; /*!< [3..2] The mode of the OSPI Bus during the transmission of the + * write enable instruction.0x0: Single0x1: Dual0x2: Quad0x3: + * Octal */ + __IOM uint32_t OSPIC_SUS_TX_MD : 2; /*!< [5..4] The mode of the OSPI Bus during the transmission of the + * suspend instruction.0x0: Single0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_RES_TX_MD : 2; /*!< [7..6] The mode of the OSPI Bus during the transmission of the + * resume instruction.0x0: Single0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_EAD_TX_MD : 2; /*!< [9..8] The mode of the OSPI Bus during the address phase of + * the erase instruction.0x0: Single0x1: Dual0x2: Quad0x3: + * Octal */ + __IOM uint32_t OSPIC_ERS_CS_HI : 5; /*!< [14..10] After the execution of instructions: write enable, + * erase, erase suspend and erase resume, the OSPI_CS remains + * high for at least this number of OSPI bus clock cycles. */ + uint32_t : 1; + __IOM uint32_t OSPIC_ERSRES_HLD : 4; /*!< [19..16] The controller must stay without flash memory reading + * requests for this number of AMBA hclk clock cycles, before + * to perform the command of erase or erase resume.15 - 0 */ + uint32_t : 4; + __IOM uint32_t OSPIC_RESSUS_DLY : 8; /*!< [31..24] Defines a timer that counts the minimum allowed delay + * between an erase suspend command and the previous erase + * resume command (or the initial erase command).0: Do not + * wait. The controller starts immediately to suspend the + * erase procedure.1..255: The controller waits for at least + * this number of 222 kHz clock cycles before the suspension + * of erasing. Time starts counting after the end of the previous + * erase resume command (or the initial erase command). */ + } OQSPIF_ERASECMDB_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_ERASECMDC_REG; /*!< (@ 0x00000030) The way of erasing in Auto mode (command register + * C) */ + + struct + { + __IOM uint32_t OSPIC_SUSSTS_DLY : 6; /*!< [5..0] Defines a timer that counts the minimum allowed delay + * between an erase suspend command and the next read status + * command.0: Do not wait. The controller starts immediately + * to read the status of the flash device.1..63: The controller + * waits for at least this number of 222 kHz clock cycles + * before to read the status of the flash device. Time starts + * counting when the erase resume command is applied. */ + uint32_t : 26; + } OQSPIF_ERASECMDC_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_BURSTBRK_REG; /*!< (@ 0x00000034) Read break sequence in Auto mode */ + + struct + { + __IOM uint32_t OSPIC_BRK_WRD : 16; /*!< [15..0] This is the value of a special command (read burst break + * sequence) that is applied by the controller to the external + * memory device, to force the memory device to abandon the + * continuous Read mode. */ + __IOM uint32_t OSPIC_BRK_SZ : 4; /*!< [19..16] The size of Burst Break Sequence0: One byte (Send OSPIC_BRK_WRD[15:8] + * 1: Two bytes (Send OSPIC_BRK_WRD[15:0])2-15: Three up to + * 16 bytes are transferred. All the bytes that are transferred, + * have the value of the OSPIC_BRK_WRD[15:8], except of the + * last byte that is the OSPIC_BRK_WRD[7:0]. */ + __IOM uint32_t OSPIC_BRK_TX_MD : 2; /*!< [21..20] The mode of the OSPI Bus during the transmission of + * the burst break sequence.0x0: Single0x1: Dual0x2: Quad0x3: + * Octal */ + __IOM uint32_t OSPIC_SEC_HF_DS : 1; /*!< [22..22] Disables output during the transmission of the second + * half (OSPIC_BRK_WRD[3:0]). Setting this bit is only useful + * if OSPIC_BRK_EN =1 and OSPIC_BRK_SZ >= 1. It is not applicable + * when the sequence is transferred in Octal mode (OSPIC_BRK_TX_MD=3).0: + * The controller drives the OSPI bus during the transmission + * of the OSPIC_BRK_WRD[3:0].1: The controller leaves the + * OSPI bus in Hi-Z during the transmission of the OSPIC_BRK_WORD[3:0]. */ + __IOM uint32_t OSPIC_BRK_EN : 1; /*!< [23..23] Controls the application of a special command (read + * burst break sequence) that is used to force the device + * to abandon the continuous Read mode.0: The special command + * is not applied1: The special command is appliedThis special + * command is applied by the controller to the external device + * under the following conditions:- The controller is in Auto + * mode.- The OSPIC_INST_MD = 1.- The previous command that + * is applied in the external device was read.-The controller + * wants to apply to th */ + uint32_t : 8; + } OQSPIF_BURSTBRK_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_STATUSCMD_REG; /*!< (@ 0x00000038) The way of reading the status of external device + * in Auto mode */ + + struct + { + __IOM uint32_t OSPIC_RSTAT_INST : 8; /*!< [7..0] The code value of the read status instruction. It is + * transmitted during the instruction phase of the read status + * instruction. */ + __IOM uint32_t OSPIC_RSTAT_TX_MD : 2; /*!< [9..8] The mode of the OSPI Bus during the instruction phase + * of the read status instruction.0x0: Single0x1: Dual0x2: + * Quad0x3: Octal */ + __IOM uint32_t OSPIC_RSTAT_RX_MD : 2; /*!< [11..10] The mode of the OSPI Bus during the receive status + * phase of the read status instruction0x0: Single0x1: Dual0x2: + * Quad0x3: Octal */ + __IOM uint32_t OSPIC_BUSY_POS : 3; /*!< [14..12] It describes who from the bits of status represents + * the Busy bit (7 - 0). */ + __IOM uint32_t OSPIC_BUSY_VAL : 1; /*!< [15..15] Defines the value of the Busy bit which means that + * the flash is busy.0: The flash is busy when the Busy bit + * is equal to 0.1: The flash is busy when the Busy bit is + * equal to 1. */ + __IOM uint32_t OSPIC_RESSTS_DLY : 6; /*!< [21..16] Defines a timer that counts the minimum required delay + * between the reading of the status register and of the previous + * erase or erase resume instruction.0: Do not wait. The controller + * starts reading the Flash memory status register immediately.1..63: + * The controller waits for at least this number of OSPI_CLK + * cycles and afterwards it starts to reading the Flash memory + * status register. The timer starts to count after the end + * of the previous erase or erase resume command.The actual + * timer that is u */ + __IOM uint32_t OSPIC_STSDLY_SEL : 1; /*!< [22..22] Defines the timer which is used to count the delay + * that it has to wait before to read the FLASH Status Register, + * after an erase or an erase resume command.0: The delay + * is controlled by the OSPIC_RESSTS_DLY which counts on the + * OSPI_CLK clock.1: The delay is controlled by the OSPIC_RESSUS_DLY + * which counts on the 222 kHz clock. */ + __IOM uint32_t OSPIC_RSTAT_DMY_EN : 1; /*!< [23..23] Enables the transmission of dummy bytes, immediately + * after the instruction code of the read status command.0: + * Do not send the dummy bytes1: Send the dummy bytes. The + * number of the dummy bytes is defined by the OSPIC_RSTAT_DMY_NUM. */ + __IOM uint32_t OSPIC_RSTAT_DMY_NUM : 4; /*!< [27..24] Number of dummy bytes (minus 1). Can be set 1-6 dummy + * bytes (values 0 up to 15). The dummy bytes are applied + * only when OSPIC_RSTAT_DMY_EN=1. */ + __IOM uint32_t OSPIC_RSTAT_DMY_TX_MD : 2; /*!< [29..28] It describes the mode of the OSPI bus during the dummy + * bytes phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Octal */ + __IOM uint32_t OSPIC_RSTAT_DMY_ZERO : 1; /*!< [30..30] Defines the value of that is transferred on the OSPI + * bus during the phase of the dummy bytes.0: The controller + * keeps the data on the bus unchanged until the bus direction + * is changed in Input mode.1: Forces the dummy bytes to get + * the zero value (only for the cycles that are not in Input + * mode). Only the IO pins that are related with the Transfer + * mode of the dummy bytes (OSPIC_RSTAT_DMY_TX_MD) get zero + * value. */ + uint32_t : 1; + } OQSPIF_STATUSCMD_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CHCKERASE_REG; /*!< (@ 0x0000003C) Check erase progress in Auto mode */ + + struct + { + __OM uint32_t OSPIC_CHCKERASE : 32; /*!< [31..0] Writing any value to this register during erasing, forces + * the controller to read the flash memory status register. + * Depending on the value of the Busy bit, it updates the + * OSPIC_ERASE_EN. */ + } OQSPIF_CHCKERASE_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_GP_REG; /*!< (@ 0x00000040) OSPI General Purpose control register */ + + struct + { + uint32_t : 1; + __IOM uint32_t OSPIC_PADS_DRV : 2; /*!< [2..1] OQSPI pads drive current0: 2 mA1: 4 mA2: 8 mA3: 14 mA */ + __IOM uint32_t OSPIC_PADS_SLEW : 2; /*!< [4..3] QSPI pads slew rate control. Indicative values under + * certain conditions:0: Rise=1.7 V/ns, Fall=1.9 V/ns (weak)1: + * Rise=2.0 V/ns, Fall=2.3 V/ns2: Rise=2.3 V/ns, Fall=2.6 + * V/ns3: Rise=2.4 V/ns, Fall=2.7 V/ns (strong)Conditions: + * FLASH pin capacitance 6 pF, Vcc=1.8V, T=25C and Idrive=16mA. */ + uint32_t : 27; + } OQSPIF_GP_REG_b; + }; + __IM uint32_t RESERVED[47]; + + union + { + __IOM uint32_t OQSPIF_CTR_CTRL_REG; /*!< (@ 0x00000100) Control register for the decryption engine of + * the OSPIC */ + + struct + { + __IOM uint32_t OSPIC_CTR_EN : 1; /*!< [0..0] Controls the AES-CTR decryption feature of the OSPIC, + * which enables the decryption (on-the-fly) of the data that + * is retrieved from the flash memory device.0: The AES-CTR + * decryption is disabled.1: The controller decrypts the content + * of the flash memory device that is placed in the address + * space that is defined by the OSPIC_CTR_SADDR_REG and OSPIC_CTR_EADDR_REG + * registers. The data that is placed outside the previous + * space, is not decrypted by the OSPIC. The decryption is + * performed by using the AES- */ + uint32_t : 31; + } OQSPIF_CTR_CTRL_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_SADDR_REG; /*!< (@ 0x00000104) Start address of the encrypted content in the + * OSPI flash */ + + struct + { + uint32_t : 10; + __IOM uint32_t OSPIC_CTR_SADDR : 22; /*!< [31..10] Defines the bits [31:10] of the start address in the + * flash memory, where an encrypted image is placed. The bits + * [9:0] are considered always as zero. This has meaning only + * when the decryption is active. See also the register OSPIC_CTR_CTRL_REG[O + * PIC_CTR_EN]. */ + } OQSPIF_CTR_SADDR_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_EADDR_REG; /*!< (@ 0x00000108) End address of the encrypted content in the OSPI + * flash */ + + struct + { + uint32_t : 10; + __IOM uint32_t OSPIC_CTR_EADDR : 22; /*!< [31..10] Defines the bits [31:10] of the end address in the + * flash memory, where an encrypted image is placed. The bits + * [9:0] are considered always as 0x3ff. This has meaning + * only when the decryption is active. See also the register + * OSPIC_CTR_CTRL_REG[OSPIC_CTR_EN]. */ + } OQSPIF_CTR_EADDR_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_NONCE_0_3_REG; /*!< (@ 0x0000010C) Nonce bytes 0 to 3 for the AES-CTR algorithm */ + + struct + { + __IOM uint32_t OSPIC_CTR_NONCE_0_3 : 32; /*!< [31..0] Defines the 8 bytes of the nonce value (N0 - N7) that + * is used by the AES-CTR algorithm to construct the counter + * block (CTRB). The total size of the counter block is 128 + * bits or 16 bytes :CTRB0 CTRB1 CTRB2 CTRB3...CTRB14 CTRB15.The + * first 8 bytes (CTRB0 - CTRB7) of the counter block consisted + * by the nonce value.The next 8 bytes of the counter block + * (CTRB8-CTRB15), are produced automatically by the hardware + * based on the address offset inside the encrypted image, + * from where are retrieved the requ */ + } OQSPIF_CTR_NONCE_0_3_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_NONCE_4_7_REG; /*!< (@ 0x00000110) Nonce bytes 4 to 7 for the AES-CTR algorithm */ + + struct + { + __IOM uint32_t OSPIC_CTR_NONCE_4_7 : 32; /*!< [31..0] See the description in the OSPIC_NONCE_0_3. */ + } OQSPIF_CTR_NONCE_4_7_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_0_3_REG; /*!< (@ 0x00000114) Key bytes 0 to 3 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_0_3 : 32; /*!< [31..0] Defines the key that is used by the AES-CTR algorithm, + * when the on-the-fly decryption is enabled ( OSPIC_CTR_CTRL_REG[OSPIC_CTR_ + * N] = 1 ). The size of the decryption key is 256 bits or + * 32 bytes :K0 K1 K2 K3...K30 K31.The mapping of the bytes + * to the corresponding OSPIC_CTR_KEY_X_Y_REG registers is + * the following :{K0, K1, K2, K3} = OSPIC_CTR_KEY_0_3_REG[31:0]{K4, + * K5, K6, K7} = OSPIC_CTR_KEY_4_7_REG[31:0]{K8, K9, K10, + * K11} = OSPIC_CTR_KEY_8_11_REG[31:0]{K12, K13, K14, K15} + * = OSPIC_CT */ + } OQSPIF_CTR_KEY_0_3_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_4_7_REG; /*!< (@ 0x00000118) Key bytes 4 to 7 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_4_7 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_4_7_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_8_11_REG; /*!< (@ 0x0000011C) Key bytes 8 to 11 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_8_11 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_8_11_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_12_15_REG; /*!< (@ 0x00000120) Key bytes 12 to 15 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_12_15 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_12_15_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_16_19_REG; /*!< (@ 0x00000124) Key bytes 16 to 19 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_16_19 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_16_19_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_20_23_REG; /*!< (@ 0x00000128) Key bytes 20 to 23 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_20_23 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_20_23_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_24_27_REG; /*!< (@ 0x0000012C) Key bytes 24 to 27 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_24_27 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_24_27_REG_b; + }; + + union + { + __IOM uint32_t OQSPIF_CTR_KEY_28_31_REG; /*!< (@ 0x00000130) Key bytes 28 to 31 for the AES-CTR algorithm */ + + struct + { + __OM uint32_t OSPIC_CTR_KEY_28_31 : 32; /*!< [31..0] See the description in the OSPIC_CTR_KEY_0_3. */ + } OQSPIF_CTR_KEY_28_31_REG_b; + }; +} OQSPIF_Type; /*!< Size = 308 (0x134) */ + +/* =========================================================================================================================== */ +/* ================ OTPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief OTPC registers (OTPC) + */ + +typedef struct /*!< (@ 0x400F3000) OTPC Structure */ +{ + union + { + __IOM uint32_t OTPC_MODE_REG; /*!< (@ 0x00000000) Mode register */ + + struct + { + __IOM uint32_t OTPC_MODE_MODE : 3; /*!< [2..0] Defines the mode of operation of the OTPC controller. + * The encoding of the modes is as follows:0x0: DSTBY. The + * OTP memory is in deep standby mode (power supply ON and + * internal LDO OFF).0x1: STBY. The OTP memory is powered + * (power supply ON and internal LDO ON, but is not selected).0x2: + * READ. The OTP memory is in the normal read mode.0x3: PROG. + * The OTP memory is in programming mode.0x4: PVFY. The OTP + * memory is in programming verification mode (margin read + * after programming).0x5: RINI */ + uint32_t : 1; + __IOM uint32_t OTPC_MODE_USE_TST_ROW : 1; /*!< [4..4] Selects the memory area of the OTP cell that will be + * used.0 - Uses the main memory area of the OTP cell1 - Uses + * the test row of the OTP cellThe value of this configuration + * field can be modified only when the controller is in an + * inactive mode (DSTBY or STBY). The selection will take + * effect at the next programming or reading mode that will + * be enabled. */ + uint32_t : 1; + __IOM uint32_t OTPC_MODE_PRG_SEL : 2; /*!< [7..6] Defines the part of the OTP cell that is programmed by + * the controller during the PROG mode, for each program request + * that is applied.0x0 : Both normal and redundancy arrays + * are programmed. This is the normal way of programming.0x1 + * : Only the normal array is programmed.0x2 : Only the redundancy + * array is programmed.0x3 : ReservedThe value of this configuration + * field can be modified only when the controller is in an + * inactive mode (DSTBY or STBY). The setting will take effect + * when will be */ + uint32_t : 24; + } OTPC_MODE_REG_b; + }; + + union + { + __IOM uint32_t OTPC_STAT_REG; /*!< (@ 0x00000004) Status register */ + + struct + { + __IM uint32_t OTPC_STAT_PRDY : 1; /*!< [0..0] Indicates the state of the programming process.0: The + * controller is busy. A programming is in progress.1: The + * logic which performs programming is idle. */ + __IM uint32_t OTPC_STAT_PBUF_EMPTY : 1; /*!< [1..1] Indicates the status of the programming buffer (PBUF).0 + * : The PBUF contains the address and the data of a programming + * request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should + * not be written as long as this status bit is zero.1 : The + * PBUF is empty and a new programming request can be registered + * in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG + * registers.This status bit gets the value zero every time + * where a programming is triggered by the OTPC_PADDR_REG + * (only if the PROG mode is */ + __IM uint32_t OTPC_STAT_MRDY : 1; /*!< [2..2] Indicates the progress of the transition from a mode + * of operation to a new mode of operation.0 : There is a + * transition in progress in a new mode of operation . Wait + * until the transition to be completed.1 : The transition + * to the new mode of operation has been completed. The function + * that has been enabled by the new mode can be used. A new + * mode can be applied.This status bit gets the value zero + * every time where the OTPC_MODE_REG[MODE] is changing. Do + * not try to use or change any function of the */ + uint32_t : 29; + } OTPC_STAT_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t OTPC_TIM1_REG; /*!< (@ 0x00000010) Various timing parameters of the OTP cell. */ + + struct + { + __IOM uint32_t OTPC_TIM1_CC_T_1US : 8; /*!< [7..0] The number of hclk_c clock periods (minus one) that give + * a time interval equal to 1us. This setting affects all + * the timing parameters that refer to microseconds, due to + * that defines the correspondence of a microsecond to a number + * of hclk_c clock cycles. */ + __IOM uint32_t OTPC_TIM1_CC_T_20NS : 3; /*!< [10..8] The number of hclk_c clock periods (minus one) that + * give a time interval that is at least higher than 20 ns. */ + uint32_t : 1; + __IOM uint32_t OTPC_TIM1_CC_T_RD : 4; /*!< [15..12] The number of hclk_c clock periods (minus one) that + * give a time interval at least higher than 100ns. This timing + * parameter refers to the access time of the OTP memory. */ + __IOM uint32_t OTPC_TIM1_US_T_PL : 4; /*!< [19..16] The number of microseconds (minus one) that are required + * until to be enabled the LDO of the OTP. It must be at least + * 10us. */ + __IOM uint32_t OTPC_TIM1_US_T_CS : 4; /*!< [23..20] The number of microseconds (minus one) that are required + * after the selection of the OTP memory, until to be ready + * for any kind of read. It must be at least 10us. */ + __IOM uint32_t OTPC_TIM1_US_T_CSP : 7; /*!< [30..24] The number of microseconds (minus one) that are required + * after the selection of the OTP memory, until to be ready + * for programming. It must be :- at least 10us- no more than + * 100us */ + uint32_t : 1; + } OTPC_TIM1_REG_b; + }; + + union + { + __IOM uint32_t OTPC_TIM2_REG; /*!< (@ 0x00000014) Various timing parameters of the OTP cell. */ + + struct + { + __IOM uint32_t OTPC_TIM2_US_T_PW : 5; /*!< [4..0] The number of microseconds (minus one) that lasts the + * programming of each bit. It must be :- at least 10us- no + * more than 20us */ + __IOM uint32_t OTPC_TIM2_US_T_PWI : 3; /*!< [7..5] The number of microseconds (minus one) between two consecutive + * programming pulses. It must be :- at least 1us- no more + * than 5us */ + __IOM uint32_t OTPC_TIM2_US_T_PPR : 7; /*!< [14..8] The number of microseconds (minus one) for recovery + * after a programming sequence. It must be :- at least 5us- + * no more than 100us */ + uint32_t : 1; + __IOM uint32_t OTPC_TIM2_US_T_PPS : 5; /*!< [20..16] The number of microseconds (minus one) that are required + * after the enabling of the programming in the OTP memory + * and before to be applied the first programming pulse. It + * must be :- at least 10us- no more than 20us */ + __IOM uint32_t OTPC_TIM2_US_T_VDS : 3; /*!< [23..21] The number of microseconds (minus one) that are required + * after the enabling of the power supply of the OTP memory + * and before to become ready for the enabling of the internal + * LDO. It must be at least 1us. */ + __IOM uint32_t OTPC_TIM2_US_T_PPH : 5; /*!< [28..24] The number of microseconds (minus one) that are required + * after the last programming pulse and before to be disabled + * the programming mode in the OTP memory. It must be:- at + * least 5us- no more than 20us */ + __IOM uint32_t OTPC_TIM2_US_T_SAS : 2; /*!< [30..29] The number of microseconds (minus one) that are required + * after the exit from the deep sleep standby mode and before + * to become ready to enter in an active mode (reading or + * programming). It must be at least 2us. */ + __IOM uint32_t OTPC_TIM2_US_ADD_CC_EN : 1; /*!< [31..31] Adds an additional hclk_c clock cycle at all the time + * intervals that count in microseconds.0 : The extra hclk_c + * clock cycle is not applied1 : The extra hclk_c clock cycle + * is applied */ + } OTPC_TIM2_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t OTPC_TEST_REG; /*!< (@ 0x00000020) Test register for the ECC logic */ + + struct + { + __IOM uint32_t OTPC_TEST_MODE : 2; /*!< [1..0] Enables the test modes of the OTP cell. The value of + * this configuration field can be modified only when the + * controller is in an inactive mode (DSTBY or STBY).0: Normal + * operation.1: Need to Set together with OTPC_TEST_ECC_MAN. + * The ECC logic of the OTP cell is disabled. During programming + * the ECC bits should be provided by the user with the help + * of the OTPC_TEST_ECC_IN register. During reading the ECC + * correction is disabled and the raw data are retrieved from + * the OTP cell.2: The test mode for t */ + __IOM uint32_t OTPC_TEST_ECC_EN_DE : 1; /*!< [2..2] Selection of the ECC function that is tested when the + * ECC test mode is enabled (OTPC_TEST_MODE=2). This register + * has no meaning when the ECC test mode is not enabled.0: + * The ECC decoding function is selected. The OTPC_PWORD_REG + * holds the 32 bits input data of the ECC logic and the OTPC_TEST_ECC_IN + * the 6 bits of the ECC parity bits. The output data of the + * ECC logic can be retrieved by performing a normal read + * from an arbitrary address of the OTP cell. The retrieved + * data will be corrected by the ECC log */ + uint32_t : 5; + __IOM uint32_t OTPC_TEST_ECC_IN : 6; /*!< [13..8] This register holds the extra 6 bits for the ECC that + * should be provided to the OTP cell in the following cases:- + * The ECC logic is disabled (OTPC_TEST_MODE=1) and programming + * is applied in the OTP cell. The content of the OTPC_TEST_ECC_IN + * will be programmed in the OTP cell in the place of the + * ECC parity bits, together with the data of the OTPC_PWORD_REG. + * The OTPC_TEST_ECC_IN should be filled with the corresponding + * data before to be configured the address in the OTPC_PADDR_REG.- + * The ECC test mode */ + uint32_t : 2; + __IM uint32_t OTPC_TEST_ECC_OUT : 6; /*!< [21..16] The 6 bits output that represent the ECC syndrome or + * the ECC parity bits. The register is updated after any + * read that is performed from the OTP cell. The parity bits + * are retrieved only in the following cases:- The ECC is + * disabled (OTPC_TEST_MODE=1) and a reading is performed + * from the OTP cell. The register will capture the raw data + * of the ECC parity bits that contained in the OTP cell array.- + * The ECC test mode is enabled and the encoding mode is tested + * (OTPC_TEST_MODE=2 and OTPC_TEST_ECC_EN_DE = */ + uint32_t : 2; + __IM uint32_t OTPC_TEST_ECC_ERR : 1; /*!< [24..24] Error indication from the ECC logic of the OTP cell. + * The register is updated after any read that is performed + * from the OTP cell.0: There is no error in the data processed + * by the ECC logic.1: A single bit error has been detected + * in the data processed by the ECC logic. */ + uint32_t : 6; + __IOM uint32_t OTPC_TEST_ECC_MAN : 1; /*!< [31..31] Enable ECC Manual Mode0 : ECC Auto Mode1 : ECC Manual + * Mode by OTP_TEST_MODE[0] */ + } OTPC_TEST_REG_b; + }; + + union + { + __IOM uint32_t OTPC_TEST_PWORD_REG; /*!< (@ 0x00000024) OTPC_TEST_PWORD_REG */ + + struct + { + __IOM uint32_t OTPC_TEST_PWORD : 32; /*!< [31..0] OTPC_TEST_PWORD */ + } OTPC_TEST_PWORD_REG_b; + }; +} OTPC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ PSK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PSK registers (PSK) + */ + +typedef struct /*!< (@ 0x40031000) PSK Structure */ +{ + union + { + __IOM uint32_t PSK_SHA1_CTRL_REG; /*!< (@ 0x00000000) CTRL_REG */ + + struct + { + __IOM uint32_t PSK_SHA1_Enable : 1; /*!< [0..0] Enable */ + __IOM uint32_t PSK_SHA1_Start : 1; /*!< [1..1] Start */ + uint32_t : 14; + __IOM uint32_t PSK_SHA1_Iteration : 16; /*!< [31..16] Iteration */ + } PSK_SHA1_CTRL_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV1_0_REG; /*!< (@ 0x00000004) IHV_1[31:0] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV1_0 : 32; /*!< [31..0] PSK_SHA1_IHV1_0 */ + } PSK_SHA1_IHV1_0_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV1_1_REG; /*!< (@ 0x00000008) IHV_1[63:32] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV1_1 : 32; /*!< [31..0] PSK_SHA1_IHV1_1 */ + } PSK_SHA1_IHV1_1_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV1_2_REG; /*!< (@ 0x0000000C) IHV_1[95:64] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV1_2 : 32; /*!< [31..0] PSK_SHA1_IHV1_2 */ + } PSK_SHA1_IHV1_2_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV1_3_REG; /*!< (@ 0x00000010) IHV_1[127:96] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV1_3 : 32; /*!< [31..0] PSK_SHA1_IHV1_3 */ + } PSK_SHA1_IHV1_3_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV1_4_REG; /*!< (@ 0x00000014) IHV_1[159:128] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV1_4 : 32; /*!< [31..0] PSK_SHA1_IHV1_4 */ + } PSK_SHA1_IHV1_4_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV2_0_REG; /*!< (@ 0x00000018) IHV_2[31:0] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV2_0 : 32; /*!< [31..0] PSK_SHA1_IHV2_0 */ + } PSK_SHA1_IHV2_0_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV2_1_REG; /*!< (@ 0x0000001C) IHV_2[63:32] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV2_1 : 32; /*!< [31..0] PSK_SHA1_IHV2_1 */ + } PSK_SHA1_IHV2_1_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV2_2_REG; /*!< (@ 0x00000020) IHV_2[95:64] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV2_2 : 32; /*!< [31..0] PSK_SHA1_IHV2_2 */ + } PSK_SHA1_IHV2_2_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV2_3_REG; /*!< (@ 0x00000024) IHV_2[127:96] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV2_3 : 32; /*!< [31..0] PSK_SHA1_IHV2_3 */ + } PSK_SHA1_IHV2_3_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_IHV2_4_REG; /*!< (@ 0x00000028) IHV_2[159:128] */ + + struct + { + __IOM uint32_t PSK_SHA1_IHV2_4 : 32; /*!< [31..0] PSK_SHA1_IHV2_4 */ + } PSK_SHA1_IHV2_4_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DATA_0_REG; /*!< (@ 0x0000002C) data[31:0] */ + + struct + { + __IOM uint32_t PSK_SHA1_DATA_0 : 32; /*!< [31..0] PSK_SHA1_DATA_0 */ + } PSK_SHA1_DATA_0_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DATA_1_REG; /*!< (@ 0x00000030) data[63:32] */ + + struct + { + __IOM uint32_t PSK_SHA1_DATA_1 : 32; /*!< [31..0] PSK_SHA1_DATA_1 */ + } PSK_SHA1_DATA_1_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DATA_2_REG; /*!< (@ 0x00000034) data[95:64] */ + + struct + { + __IOM uint32_t PSK_SHA1_DATA_2 : 32; /*!< [31..0] PSK_SHA1_DATA_2 */ + } PSK_SHA1_DATA_2_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DATA_3_REG; /*!< (@ 0x00000038) data[127:96] */ + + struct + { + __IOM uint32_t PSK_SHA1_DATA_3 : 32; /*!< [31..0] PSK_SHA1_DATA_3 */ + } PSK_SHA1_DATA_3_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DATA_4_REG; /*!< (@ 0x0000003C) data[159:128] */ + + struct + { + __IOM uint32_t PSK_SHA1_DATA_4 : 32; /*!< [31..0] PSK_SHA1_DATA_4 */ + } PSK_SHA1_DATA_4_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DIGEST_0_REG; /*!< (@ 0x00000040) digest[31:0] */ + + struct + { + __IOM uint32_t PSK_SHA1_DIGEST_0 : 32; /*!< [31..0] PSK_SHA1_DIGEST_0 */ + } PSK_SHA1_DIGEST_0_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DIGEST_1_REG; /*!< (@ 0x00000044) digest[63:32] */ + + struct + { + __IOM uint32_t PSK_SHA1_DIGEST_1 : 32; /*!< [31..0] PSK_SHA1_DIGEST_1 */ + } PSK_SHA1_DIGEST_1_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DIGEST_2_REG; /*!< (@ 0x00000048) digest[95:64] */ + + struct + { + __IOM uint32_t PSK_SHA1_DIGEST_2 : 32; /*!< [31..0] PSK_SHA1_DIGEST_2 */ + } PSK_SHA1_DIGEST_2_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DIGEST_3_REG; /*!< (@ 0x0000004C) digest[127:96] */ + + struct + { + __IOM uint32_t PSK_SHA1_DIGEST_3 : 32; /*!< [31..0] PSK_SHA1_DIGEST_3 */ + } PSK_SHA1_DIGEST_3_REG_b; + }; + + union + { + __IOM uint32_t PSK_SHA1_DIGEST_4_REG; /*!< (@ 0x00000050) digest[159:128] */ + + struct + { + __IOM uint32_t PSK_SHA1_DIGEST_4 : 32; /*!< [31..0] PSK_SHA1_DIGEST_4 */ + } PSK_SHA1_DIGEST_4_REG_b; + }; +} PSK_Type; /*!< Size = 84 (0x54) */ + +/* =========================================================================================================================== */ +/* ================ QSPIC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief QSPIC registers (QSPIC) + */ + +typedef struct /*!< (@ 0x22000000) QSPIC Structure */ +{ + union + { + __IOM uint32_t QSPIC_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for Manual mode */ + + struct + { + __OM uint32_t QSPIC_SET_SINGLE : 1; /*!< [0..0] Write 1 to set the bus mode in Single SPI mode when the + * controller is in Manual mode. */ + __OM uint32_t QSPIC_SET_DUAL : 1; /*!< [1..1] Write 1 to set the bus mode in Dual mode when the controller + * is in Manual mode. */ + __OM uint32_t QSPIC_SET_QUAD : 1; /*!< [2..2] Write 1 to set the bus mode in Quad mode when the controller + * is in Manual mode. */ + __OM uint32_t QSPIC_EN_CS : 1; /*!< [3..3] Write 1 to enable the chip select (active low) when the + * controller is in Manual mode. */ + __OM uint32_t QSPIC_DIS_CS : 1; /*!< [4..4] Write 1 to disable the chip select (active low) when + * the controller is in Manual mode. */ + uint32_t : 27; + } QSPIC_CTRLBUS_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_CTRLMODE_REG; /*!< (@ 0x00000004) Mode Control Register */ + + struct + { + __IOM uint32_t QSPIC_AUTO_MD : 1; /*!< [0..0] Mode of operation.0: Manual mode is selected.1: Auto + * Mmde is selected.During an erasing, the QSPIC_AUTO_MD goes + * in read-only mode (see QSPIC_ERASE_EN). */ + __IOM uint32_t QSPIC_CLK_MD : 1; /*!< [1..1] Mode of the generated QSPI_SCK clock.0: Use Mode 0 for + * the QSPI_CLK. The QSPI_SCK is low when QSPI_CS is high.1: + * Use Mode 3 for the QSPI_CLK. The QSPI_SCK is high when + * QSPI_CS is high.See also the QSPIC_CS_MD register and the + * QSPIC_CLK_FREE_EN register. */ + __IOM uint32_t QSPIC_IO2_OEN : 1; /*!< [2..2] QSPI_IO2 output enable. Use this only in SPI or Dual + * SPI mode to control /WP signal. When the Auto Mode is selected + * (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this + * bit to zero.0: The QSPI_IO2 pad is input.1: The QSPI_IO2 + * pad is output. */ + __IOM uint32_t QSPIC_IO3_OEN : 1; /*!< [3..3] QSPI_IO3 output enable. Use this only in SPI or Dual + * SPI mode to control/hold signal. When the Auto Mode is + * selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, + * set this bit to zero.0: The QSPI_IO3 pad is input.1: The + * QSPI_IO3 pad is output. */ + __IOM uint32_t QSPIC_IO2_DAT : 1; /*!< [4..4] The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1. */ + __IOM uint32_t QSPIC_IO3_DAT : 1; /*!< [5..5] The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1. */ + __IOM uint32_t QSPIC_HRDY_MD : 1; /*!< [6..6] This configuration bit is useful when the frequency of + * the QSPI clock is much lower than the clock of the AMBA + * bus in order not to lock the AMBA bus for a long time.0: + * Adds wait states via hready signal when an access is performed + * on QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA + * registers. It is not necessary to check the QSPIC_BUSY + * of the QSPIC_STATUS_REG.1: The controller does not add + * wait states via the hready signal when the access is performed + * on QSPIC_WRITEDATA, QSPIC_READDATA and QSP */ + __IOM uint32_t QSPIC_RXD_NEG : 1; /*!< [7..7] Define the clock edge that is used for the capturing + * of the received data when the read pipe is not active (QSPIC_RPIPE_EN + * = 0).0: Sampling of the received data with the positive + * edge of the QSPI_SCK.1: Sampling of the received data with + * the negative edge of the QSPI_SCK.The internal QSPI_SCK + * clock that is used by the controller for the capturing + * of the received data has a skew in respect of the QSPI_SCK + * that is received by the external memory device. To improve + * the timing requirements of the */ + __IOM uint32_t QSPIC_RPIPE_EN : 1; /*!< [8..8] Control the use of the data read pipe.0: The read pipe + * is disabled, the sampling clock is defined according to + * the QSPIC_RXD_NEG setting.1: The read pipe is enabled. + * The delay of the sampling clock is defined according to + * the QSPI_PCLK_MD setting (Recommended). */ + __IOM uint32_t QSPIC_PCLK_MD : 3; /*!< [11..9] Control the read pipe clock delay relative to the falling + * edge of QSPI_SCK. Refer to QSPI Timing for timing parameters. */ + __IOM uint32_t QSPIC_FORCENSEQ_EN : 1; /*!< [12..12] Control the way in which a burst request from the AMBA + * bus is addressed by the QSPI controller.0: The controller + * translates a burst access on the AMBA bus as a burst access + * on the QSPI bus. That results to the minimum number of + * command/address phases.1: The controller splits a burst + * access on the AMBA bus into a number of single accesses + * on the QSPI bus. That results to a separate command for + * each beat of the burst. For example, a 4-beat word incremental + * AMBA read access is split into four differ */ + __IOM uint32_t QSPIC_USE_32BA : 1; /*!< [13..13] Control the length of the address that the external + * memory device uses.0: The external memory device uses 24 + * bits address.1: The external memory device uses 32 bits + * address.The controller uses this bit to decide the number + * of the address bytes that has to transfer to the external + * device during Auto mode. */ + __IOM uint32_t QSPIC_SRAM_EN : 1; /*!< [14..14] Define the type of the external device that is connected + * on the QSPIC controller.0: The external memory device is + * a serial Flash.1: The external memory device is a serial + * SRAM.When the external device is a serial SRAM, the erase + * suspend/ resume functionality of the controller is disabled. + * In this case the writing of the QSPIC_ERASECTRL_REG[QSPIC_ERASE_EN] + * bit has no effect. Also, the memory space where the external + * device is mapped is considered as writable. */ + __IOM uint32_t QSPIC_CS_MD : 1; /*!< [15..15] Control the clock edge with which is produced the QSPI_CS + * signal.0: The QSPI_CS is produced with the rising edge + * of the QSPI_SCK. The QSPI_SCK is always inactive while + * the QSPI_CS is high.1: The QSPI_CS is produced with the + * falling edge of the QSPI_SCK. The behavior of the QSPI_SCK + * while the QSPI_CS is high is controlled by the QSPIC_CLK_FREE_EN. */ + __IOM uint32_t QSPIC_CLK_FREE_EN : 1; /*!< [16..16] Control the behavior of the QSPI_SCK when the QSPI_CS + * is high and QSPIC_CS_MD = 1.0: Produces one QSPI_SCK clock + * pulse after each 0 to 1 transition in the QSPI_CS.1: The + * QSPI_SCK clock remains always active, while the QSPI_CS + * is inactive.This setting has meaning only when the QSPIC_CS_MD + * = 1. */ + uint32_t : 15; + } QSPIC_CTRLMODE_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_RECVDATA_REG; /*!< (@ 0x00000008) Received data for Manual mode */ + + struct + { + __IM uint32_t QSPIC_RECVDATA : 32; /*!< [31..0] This register contains the received data when the QSPIC_READDATA_REG + * register is used in Manual mode, to retrieve data from + * the external memory device and QSPIC_HRDY_MD = 1 and QSPIC_BUSY + * = 0. */ + } QSPIC_RECVDATA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register + * A) */ + + struct + { + __IOM uint32_t QSPIC_INST : 8; /*!< [7..0] Instruction Value for Incremental Burst or Single read + * access. This value is the selected instruction at the cases + * of incremental burst or single read access. Also this value + * is used when a wrapping burst is not supported (QSPIC_WRAP_MD) */ + __IOM uint32_t QSPIC_INST_WB : 8; /*!< [15..8] Instruction Value for Wrapping Burst. This value is + * the selected instruction when QSPIC_WRAP_MD is equal to + * 1 and the access is a wrapping burst of length and size + * described by the bit fields QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE + * respectively. */ + __IOM uint32_t QSPIC_EXT_BYTE : 8; /*!< [23..16] The value of an extra byte which is transferred after + * address (only if QSPIC_EXT_BYTE_EN = 1). Usually this is + * the Mode Bits in Dual/Quad SPI I/O instructions. */ + __IOM uint32_t QSPIC_INST_TX_MD : 2; /*!< [25..24] It describes the mode of the SPI bus during the instruction + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + __IOM uint32_t QSPIC_ADR_TX_MD : 2; /*!< [27..26] It describes the mode of the SPI bus during the address + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + __IOM uint32_t QSPIC_EXT_TX_MD : 2; /*!< [29..28] It describes the mode of the SPI bus during the Extra + * Byte phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + __IOM uint32_t QSPIC_DMY_TX_MD : 2; /*!< [31..30] It describes the mode of the SPI bus during the Dummy + * bytes phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + } QSPIC_BURSTCMDA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register + * B) */ + + struct + { + __IOM uint32_t QSPIC_DAT_RX_MD : 2; /*!< [1..0] It describes the mode of the SPI bus during the data + * phase.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + __IOM uint32_t QSPIC_EXT_BYTE_EN : 1; /*!< [2..2] Extra Byte Enable0: Do not Send QSPIC_EXT_BYTE1: Send + * QSPIC_EXT_BYTE */ + __IOM uint32_t QSPIC_EXT_HF_DS : 1; /*!< [3..3] Extra Half Disable Output.0: If QSPIC_EXT_BYTE_EN = 1, + * then transmit the complete QSPIC_EXT_BYTE.1: If QSPIC_EXT_BYTE_EN + * = 1, then disable (Hi-Z) output during the transmission + * of bits [3:0] of QSPIC_EXT_BYTE. */ + __IOM uint32_t QSPIC_DMY_NUM : 2; /*!< [5..4] Number of Dummy Bytes0x0: Zero Dummy Bytes (Do not Send + * Dummy Bytes)0x1: Send 1 Dummy Byte0x2: Send 2 Dummy Bytes0x3: + * Send 4 Dummy BytesWhen QSPIC_DMY_FORCE is enabled, the + * QSPIC_DMY_NUM is overruled. In this case the number of + * dummy bytes is defined by QSPIC_DMY_FORCE and is equal + * to 3, independent of the value of QSPIC_DMY_NUM. */ + __IOM uint32_t QSPIC_INST_MD : 1; /*!< [6..6] Instruction mode0: Transmit instruction at any burst + * access.1: Transmit instruction only in the first access + * after the selection of Auto mode. */ + __IOM uint32_t QSPIC_WRAP_MD : 1; /*!< [7..7] Wrap mode0: The QSPIC_INST is the selected instruction + * at any access.1: The QSPIC_INST_WB is the selected instruction + * at any wrapping burst access of length and size described + * by the registers QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. + * In all other cases the QSPIC_INST is the selected instruction. + * Use this feature only when the serial Flash memory supports + * a special instruction for wrapping burst access. */ + __IOM uint32_t QSPIC_WRAP_LEN : 2; /*!< [9..8] It describes the selected length of a wrapping burst + * (QSPIC_WRAP_MD).0x0: 4 beat wrapping burst0x1: 8 beat wrapping + * burst0x2: 16 beat wrapping burst0x3: Reserved */ + __IOM uint32_t QSPIC_WRAP_SIZE : 2; /*!< [11..10] It describes the selected data size of a wrapping burst + * (QSPIC_WRAP_MD).0x0: Byte access (8-bits)0x1: Half word + * access (16 bits)0x2: Word access (32-bits)0x3: Reserved */ + __IOM uint32_t QSPIC_CS_HIGH_MIN : 3; /*!< [14..12] Between the transmission of two different instructions + * to the flash memory, the QSPI Bus stays in idle state (QSPI_CS + * high) for at least this number of QSPI_SCK clock cycles. + * See the QSPIC_ERS_CS_HI and the QSPIC_WR_CS_HIGH_MIN registers + * for some exceptions. */ + __IOM uint32_t QSPIC_DMY_FORCE : 1; /*!< [15..15] By setting this bit, the number of dummy bytes is forced + * to be equal to 3. In this case the QSPIC_DMY_NUM field + * is overruled and has no function.0: The number of dummy + * bytes is controlled by the QSPIC_DMY_NUM field.1: Three + * dummy bytes are used. The QSPIC_DMY_NUM is overruled. */ + uint32_t : 16; + } QSPIC_BURSTCMDB_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_STATUS_REG; /*!< (@ 0x00000014) The status register of the QSPI controller */ + + struct + { + __IM uint32_t QSPIC_BUSY : 1; /*!< [0..0] The status of the SPI Bus.0: The SPI Bus is idle1: The + * SPI Bus is active. Read data, write data or dummy data + * activity is in progress.This register has meaning only + * in Manual mode and only when QSPIC_HRDY_MD = 1. */ + uint32_t : 31; + } QSPIC_STATUS_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for Manual mode */ + + struct + { + __OM uint32_t QSPIC_WRITEDATA : 32; /*!< [31..0] Writing to this register generates a data transfer from + * the controller to the external memory device. The data + * written in this register is then transferred to the memory + * using the selected mode of the SPI Bus (SPI, Dual SPI, + * Quad SPI). The data size of the access to this register + * can be 32-bits/16-bits/8-bits and is equal to the number + * of the transferred bits.This register has meaning only + * when the controller is in Manual mode. */ + } QSPIC_WRITEDATA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for Manual mode */ + + struct + { + __IM uint32_t QSPIC_READDATA : 32; /*!< [31..0] A read access at this register generates a data transfer + * from the external memory device to the QSPIC controller. + * The data is transferred using the selected mode of the + * SPI Bus (SPI, Dual SPI, Quad SPI). The data size of the + * access to this register can be 32-bits/16-bits/8-bits and + * is equal to the number of the transferred bits.This register + * has meaning only when the controller is in Manual mode. */ + } QSPIC_READDATA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for Manual mode */ + + struct + { + __OM uint32_t QSPIC_DUMMYDATA : 32; /*!< [31..0] Writing to this register generates a number of clock + * pulses to the SPI Bus. During the last clock of this activity + * in the SPI Bus, the QSPI_IOx data pads are in Hi-Z state. + * The data size of the access to this register can be 32-bits/16-bits/8-bit + * . The number of generated pulses is equal to: (size of + * AHB bus access)/(size of SPI bus). The size of SPI Bus + * is equal to 1, 2, or 4 for Single, Dual, or Quad SPI mode + * respectively.This register has meaning only when the controller + * is in Manual mode. */ + } QSPIC_DUMMYDATA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_ERASECTRL_REG; /*!< (@ 0x00000024) Erase control register */ + + struct + { + uint32_t : 4; + __IOM uint32_t QSPIC_ERS_ADDR : 20; /*!< [23..4] Defines the address of the block/sector that is requested + * to be erased.If QSPIC_USE_32BA = 0 (24 bits addressing), + * bits QSPIC_ERASECTRL_REG[23-12] determine the block/sector + * address bits [23-12].QSPIC_ERASECTRL_REG[11-4] are ignored + * by the controller.If QSPIC_USE_32BA = 1 (32 bits addressing) + * bits QSPIC_ERASECTRL_REG[23-4] determine the block/sectors + * address bits [31:12] */ + __IOM uint32_t QSPIC_ERASE_EN : 1; /*!< [24..24] This bit has meaning only when the external device + * is a serial Flash (QSPIC_SRAM_EN = 0).During Manual mode + * (QSPIC_AUTO_MD = 0): This bit is in read-only mode.During + * Auto mode (QSPIC_AUTO_MD = 1): To request the erasing of + * the block/sector (QSPIC_ERS_ADDR, 12'b0), write 1 to this + * bit. This bit is cleared automatically with the end of + * erasing. Until the end of erasing the QSPIC_ERASE_EN remains + * in read-only mode. During the same period of time, the + * controller remains in Auto mode (QSPIC_AUTO_MD go */ + __IM uint32_t QSPIC_ERS_STATE : 3; /*!< [27..25] It shows the progress of sector/block erasing (read-only)0x0: + * No Erase0x1: Pending erase request0x2: Erase procedure + * is running0x3: Suspended Erase procedure0x4: Finishing + * the Erase procedure0x5...0x7: Reserved */ + uint32_t : 4; + } QSPIC_ERASECTRL_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register + * A) */ + + struct + { + __IOM uint32_t QSPIC_ERS_INST : 8; /*!< [7..0] The code value of the erase instruction. */ + __IOM uint32_t QSPIC_WEN_INST : 8; /*!< [15..8] The code value of the write enable instruction. */ + __IOM uint32_t QSPIC_SUS_INST : 8; /*!< [23..16] The code value of the erase suspend instruction. */ + __IOM uint32_t QSPIC_RES_INST : 8; /*!< [31..24] The code value of the erase resume instruction. */ + } QSPIC_ERASECMDA_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register + * B) */ + + struct + { + __IOM uint32_t QSPIC_ERS_TX_MD : 2; /*!< [1..0] The mode of the SPI Bus during the instruction phase + * of the erase instruction0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_WEN_TX_MD : 2; /*!< [3..2] The mode of the SPI Bus during the transmission of the + * write enable instruction.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_SUS_TX_MD : 2; /*!< [5..4] The mode of the SPI Bus during the transmission of the + * suspend instruction.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_RES_TX_MD : 2; /*!< [7..6] The mode of the SPI Bus during the transmission of the + * resume instruction.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_EAD_TX_MD : 2; /*!< [9..8] The mode of the SPI Bus during the address phase of the + * erase instruction.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_ERS_CS_HI : 5; /*!< [14..10] After the execution of instructions: write enable, + * erase, erase suspend and erase resume, the QSPI_CS remains + * high for at least this number of QSPI_SCK clock cycles. */ + uint32_t : 1; + __IOM uint32_t QSPIC_ERSRES_HLD : 4; /*!< [19..16] The controller must stay without Flash memory reading + * requests for this number of AMBA hclk clock cycles, before + * to perform the command of erase or erase resume. Allowable + * range: 0xF - 0x0 */ + uint32_t : 4; + __IOM uint32_t QSPIC_RESSUS_DLY : 6; /*!< [29..24] Defines a timer that counts the minimum allowed delay + * between an erase suspend command and the previous erase + * resume command (or the initial erase command).0x00: Do + * not wait. The controller starts immediately to suspend + * the erase procedure.0x01..0x3F: The controller waits for + * at least this number of 288 kHz clock cycles before the + * suspension of erasing. Time starts counting after the end + * of the previous erase resume command (or the initial erase + * command). */ + uint32_t : 2; + } QSPIC_ERASECMDB_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_BURSTBRK_REG; /*!< (@ 0x00000030) Read break sequence in Auto mode */ + + struct + { + __IOM uint32_t QSPIC_BRK_WRD : 16; /*!< [15..0] This is the value of a special command (read break sequence) + * that is applied by the controller to the external memory + * device, to force the memory device to abandon the continuous + * read mode. */ + __IOM uint32_t QSPIC_BRK_EN : 1; /*!< [16..16] Controls the application of a special command (read + * break sequence) that is used to force the device to abandon + * the continuous read mode.0: The special command is not + * applied1: The special command is appliedThis special command + * is applied by the controller to the external device under + * the following conditions:- the controller is in Auto mode- + * the QSPIC_INST_MD = 1- the previous command that has been + * applied in the external device was read- the controller + * want to apply to the e */ + __IOM uint32_t QSPIC_BRK_SZ : 1; /*!< [17..17] The size of the read break sequence.0: One byte (Send + * QSPIC_BRK_WRD[15:8])1: Two bytes (Send QSPIC_BRK_WRD[15:0]) */ + __IOM uint32_t QSPIC_BRK_TX_MD : 2; /*!< [19..18] The mode of the SPI Bus during the transmission of + * the read break sequence.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_SEC_HF_DS : 1; /*!< [20..20] Disable output during the transmission of the second + * half (QSPIC_BRK_WRD[3:0]). Setting this bit is only useful + * if QSPIC_BRK_EN = 1 and QSPIC_BRK_SZ = 1.0: The controller + * drives the SPI Bus during the transmission of the QSPIC_BRK_WRD[3:0].1: + * The controller leaves the SPI Bus in Hi-Z during the transmission + * of the QSPIC_BRK_WORD[3:0]. */ + uint32_t : 11; + } QSPIC_BURSTBRK_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_STATUSCMD_REG; /*!< (@ 0x00000034) The way of reading the status of external device + * in Auto mode */ + + struct + { + __IOM uint32_t QSPIC_RSTAT_INST : 8; /*!< [7..0] The code value of the read status instruction.It is transmitted + * during the instruction phase of the read status instruction. */ + __IOM uint32_t QSPIC_RSTAT_TX_MD : 2; /*!< [9..8] The mode of the SPI Bus during the instruction phase + * of the read status instruction.0x0: Single SPI0x1: Dual0x2: + * Quad0x3: Reserved */ + __IOM uint32_t QSPIC_RSTAT_RX_MD : 2; /*!< [11..10] The mode of the SPI Bus during the reception phase + * of the read status instruction, where the value of status + * register is retrieved.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_BUSY_POS : 3; /*!< [14..12] Defines the bit of the Flash status register which + * represents the Busy bit (0x7 - 0x0). */ + __IOM uint32_t QSPIC_BUSY_VAL : 1; /*!< [15..15] Defines the value of the Busy bit which means that + * the Flash is busy.0: The Flash is busy when the Busy bit + * is equal to 0.1: The Flash is busy when the Busy bit is + * equal to 1. */ + __IOM uint32_t QSPIC_RESSTS_DLY : 6; /*!< [21..16] Defines the timer that counts the minimum required + * delay between the reading of the status register and of + * the previous erase or erase resume instruction.0x00: Do + * not wait. The controller starts to reading the Flash memory + * status register immediately.0x01...0x3F: The controller + * waits for at least this number of QSPI_CLK cycles and afterwards + * it starts to reading the Flash memory status register. + * The timer starts to count after the end of the previous + * erase or erase resume command.The actual t */ + __IOM uint32_t QSPIC_STSDLY_SEL : 1; /*!< [22..22] Defines the timer which is used to count the delay + * that it has to wait before to read the Flash Status Register, + * after an erase or an erase resume command.0: The delay + * is controlled by the QSPIC_RESSTS_DLY which counts on the + * QSPI clock.1: The delay is controlled by the QSPIC_RESSUS_DLY + * which counts on the 288 kHz clock. */ + uint32_t : 9; + } QSPIC_STATUSCMD_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_CHCKERASE_REG; /*!< (@ 0x00000038) Check erase progress in Auto mode */ + + struct + { + __OM uint32_t QSPIC_CHCKERASE : 32; /*!< [31..0] Writing any value to this register during erasing, forces + * the controller to read the Flash memory status register. + * Depending on the value of the Busy bit, it updates the + * QSPIC_ERASE_EN.This register has meaning only when the + * controller is in Auto mode and there is an erase in progress + * (QSPIC_ERASE_EN = 1). It has no meaning when the external + * device is a serial SRAM. */ + } QSPIC_CHCKERASE_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_GP_REG; /*!< (@ 0x0000003C) General Purpose control register */ + + struct + { + __IOM uint32_t QSPIC_SELECT : 1; /*!< [0..0] QSPIC enable0: not active1: active */ + __IOM uint32_t QSPIC_PADS_DRV : 2; /*!< [2..1] QSPIC pads drive current0: 2 mA1: 4 mA2: 8 mA3: 14 mA */ + __IOM uint32_t QSPIC_PADS_SLEW : 2; /*!< [4..3] QSPIC pads slew rate control00: fast slew rate11: slow + * slew rate */ + uint32_t : 27; + } QSPIC_GP_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_AWRITECMD_REG; /*!< (@ 0x00000040) The way of writing in Auto mode when the external + * device is a serial SRAM */ + + struct + { + __IOM uint32_t QSPIC_WR_INST : 8; /*!< [7..0] This is the value of the instruction that is used to + * be programmed the external SRAM device. */ + __IOM uint32_t QSPIC_WR_INST_TX_MD : 2; /*!< [9..8] The mode of the SPI Bus during the instruction phase + * of the write command.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_WR_ADR_TX_MD : 2; /*!< [11..10] The mode of the SPI Bus during the address phase of + * the write command.0x0: Single SPI0x1: Dual0x2: Quad0x3: + * Reserved */ + __IOM uint32_t QSPIC_WR_DAT_TX_MD : 2; /*!< [13..12] The mode of the SPI Bus during the data phase of the + * write command.0x0: Single SPI0x1: Dual0x2: Quad0x3: Reserved */ + __IOM uint32_t QSPIC_WR_CS_HIGH_MIN : 5; /*!< [18..14] After the execution of the write command, the QSPI_CS + * remains high for at least this number of QSPI_SCK clock + * cycles. */ + uint32_t : 13; + } QSPIC_AWRITECMD_REG_b; + }; + + union + { + __IOM uint32_t QSPIC_MEMBLEN_REG; /*!< (@ 0x00000044) External memory burst length configuration */ + + struct + { + __IOM uint32_t QSPIC_MEMBLEN : 3; /*!< [2..0] In this register, the expected behavior of the external + * memory device regarding the length of a burst operation + * is defined:0x0: The external memory device is capable to + * implement incremental burst of unspecified length.0x1: + * The external memory device implements a wrapping burst + * of length 4 bytes.0x2: The external memory device implements + * a wrapping burst of length 8 bytes.0x3: The external memory + * device implements a wrapping burst of length 16 bytes.0x4: + * The external memory device imp */ + __IOM uint32_t QSPIC_T_CEM_EN : 1; /*!< [3..3] This bit enables the controlling of the maximum time + * tCEM for which the QSPI_CS remains active. It has meaning + * only when Auto mode is active (QSPIC_AUTO_MD = 1) and the + * external device is a serial SRAM (QSPIC_SRAM_EN = 1). In + * the case where the external device is a serial Flash (QSPIC_SRAM_EN + * = 0) or the controller is in Manual mode (QSPIC_AUTO_MD + * = 0), this field has no any effect.This feature is useful + * when the external serial device is a dynamic RAM that requires + * refresh. If the refresh is applied */ + __IOM uint32_t QSPIC_T_CEM_CC : 10; /*!< [13..4] Defines the maximum allowed time tCEM for which the + * QSPIC_CS can stay active (QSPI_CS = 0). It has meaning + * only when QSPIC_T_CEM_EN is equal to 1. See also the description + * of the QSPIC_T_CEM_EN for more details.The tCEM is expressed + * in number of QSPI clock cycles and can be calculated as + * follows:tCEM/(qspi_clock_period)If the result of the above + * equation is higher than 0x3FF, use the value 0x3FF. */ + uint32_t : 18; + } QSPIC_MEMBLEN_REG_b; + }; +} QSPIC_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ RETMEMCTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief RETMEMCTRL registers (RETMEMCTRL) + */ + +typedef struct /*!< (@ 0x400B0900) RETMEMCTRL Structure */ +{ + union + { + __IOM uint32_t RETMEMCTRL_STALL_REG; /*!< (@ 0x00000000) Maximum Stall cycles Control Register */ + + struct + { + __IOM uint32_t AHB_CPUC_MAX_STALL : 4; /*!< [3..0] Maximum allowed number of stall cycles for the CPUC AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t AHB_CPUS_MAX_STALL : 4; /*!< [7..4] Maximum allowed number of stall cycles for the CPUS AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + __IOM uint32_t AHB_DMA_MAX_STALL : 4; /*!< [11..8] Maximum allowed number of stall cycles for the DMA AHB + * interface. If exceeded, the interface will get high priority. + * Valid for a single access so the next access (of a burst) + * might end up in the queue for the same number of wait cycles.0: + * don't use, not feasible and can block other interfaces1: + * max 1 stall cycle15: max 15 stall cycles */ + uint32_t : 20; + } RETMEMCTRL_STALL_REG_b; + }; + + union + { + __IOM uint32_t RETMEMCTRL_STATUS_REG; /*!< (@ 0x00000004) RAM cells Status Register */ + + struct + { + __IOM uint32_t RAM0_OFF_BUT_ACCESS : 1; /*!< [0..0] Reading a '1' indicates RAM0 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + __IOM uint32_t RAM1_OFF_BUT_ACCESS : 1; /*!< [1..1] Reading a '1' indicates RAM1 was off but still access + * was performed.Writing a '1' will clear the status back + * to '0'. */ + uint32_t : 30; + } RETMEMCTRL_STATUS_REG_b; + }; + + union + { + __IOM uint32_t RETMEMCTRL_PRIO_ARB_REG; /*!< (@ 0x00000008) Priority Control Register for RAM cells from + * 0 to 23 */ + + struct + { + __IOM uint32_t PRIO_ARB_CPUC_RAM : 2; /*!< [1..0] Priority of RAM0~RAM23 for the CPUC AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_CPUS_RAM : 2; /*!< [3..2] Priority of RAM0~RAM23 for the CPUS AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + __IOM uint32_t PRIO_ARB_DMA_RAM : 2; /*!< [5..4] Priority of RAM0~RAM23 for the DMA AHB interface.00: + * low priority01: mid priority (default)1x: highest */ + uint32_t : 26; + } RETMEMCTRL_PRIO_ARB_REG_b; + }; + + union + { + __IOM uint32_t RETMEMCTRL_STATIC_CLK_OFF_REG; /*!< (@ 0x0000000C) Memory Static Clock Off register */ + + struct + { + __IOM uint32_t SRAM0 : 1; /*!< [0..0] Static clock off - SRAM0 */ + __IOM uint32_t SRAM1 : 1; /*!< [1..1] Static clock off - SRAM1 */ + __IOM uint32_t SRAM2 : 1; /*!< [2..2] Static clock off - SRAM2 */ + uint32_t : 29; + } RETMEMCTRL_STATIC_CLK_OFF_REG_b; + }; + + union + { + __IOM uint32_t RETMEMCTRL_DYNAMIC_CLK_ON_REG; /*!< (@ 0x00000010) Memory Dynamic Clock On register */ + + struct + { + __IOM uint32_t AHB2MEM : 1; /*!< [0..0] Dynamic clock on - AHB2MEM */ + __IOM uint32_t ARBITER : 1; /*!< [1..1] Dynamic clock on - Arbiters */ + uint32_t : 1; + __IOM uint32_t MMI2MEM : 1; /*!< [3..3] Dynamic clock on - MMI2MEM */ + uint32_t : 1; + __IOM uint32_t MEM_UNIT : 1; /*!< [5..5] Dynamic clock on - Memory Units */ + uint32_t : 26; + } RETMEMCTRL_DYNAMIC_CLK_ON_REG_b; + }; + + union + { + __IOM uint32_t RETMEMCTRL_MST_CLK_EN_REG; /*!< (@ 0x00000014) Memory Master Clock En register */ + + struct + { + __IOM uint32_t MST_CPUC_CLK_EN : 1; /*!< [0..0] Clock Enable for memctrl's master - CPUCIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_CPUS_CLK_EN : 1; /*!< [1..1] Clock Enable for memctrl's master - CPUSIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_DMA_CLK_EN : 1; /*!< [2..2] Clock Enable for memctrl's master - DMAIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + __IOM uint32_t MST_M33_MTB_CLK_EN : 1; /*!< [3..3] Clock Enable for memctrl's master - M33 MTBIf this value + * is 0, memctrl's master to memory interface conversion block's + * clock is off. */ + uint32_t : 28; + } RETMEMCTRL_MST_CLK_EN_REG_b; + }; +} RETMEMCTRL_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ RFMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief RFMON registers (RFMON) + */ + +typedef struct /*!< (@ 0x40070600) RFMON Structure */ +{ + union + { + __IOM uint32_t RFMON_CTRL_REG; /*!< (@ 0x00000000) RFMON_CTRL_REG */ + + struct + { + __IOM uint32_t RFMON_PACK_EN : 1; /*!< [0..0] RFMON_PACK_EN */ + __IOM uint32_t RFMON_CIRC_EN : 1; /*!< [1..1] RFMON_CIRC_EN */ + __IOM uint32_t RFMON_BREQ_FORCE : 1; /*!< [2..2] RFMON_BREQ_FORCE */ + __IOM uint32_t RFMON_READ_FORCE : 1; /*!< [3..3] RFMON_READ_FORCE */ + uint32_t : 28; + } RFMON_CTRL_REG_b; + }; + + union + { + __IOM uint32_t RFMON_ADDR_REG; /*!< (@ 0x00000004) RFMON_ADDR_REG */ + + struct + { + uint32_t : 2; + __IOM uint32_t RFMON_ADDR : 30; /*!< [31..2] RFMON_ADDR */ + } RFMON_ADDR_REG_b; + }; + + union + { + __IOM uint32_t RFMON_LEN_REG; /*!< (@ 0x00000008) RFMON_LEN_REG */ + + struct + { + __IOM uint32_t RFMON_LEN : 17; /*!< [16..0] RFMON_LEN */ + uint32_t : 15; + } RFMON_LEN_REG_b; + }; + + union + { + __IOM uint32_t RFMON_STAT_REG; /*!< (@ 0x0000000C) RFMON_STAT_REG */ + + struct + { + __IM uint32_t RFMON_ACTIVE : 1; /*!< [0..0] RFMON_ACTIVE */ + __IOM uint32_t RFMON_OFLOW_STK : 1; /*!< [1..1] RFMON_OFLOW_STK */ + uint32_t : 30; + } RFMON_STAT_REG_b; + }; + + union + { + __IOM uint32_t RFMON_CRV_ADDR_REG; /*!< (@ 0x00000010) RFMON_CRV_ADDR_REG */ + + struct + { + uint32_t : 2; + __IM uint32_t RFMON_CRV_ADDR : 30; /*!< [31..2] RFMON_CRV_ADDR */ + } RFMON_CRV_ADDR_REG_b; + }; + + union + { + __IOM uint32_t RFMON_CRV_LEN_REG; /*!< (@ 0x00000014) RFMON_CRV_LEN_REG */ + + struct + { + __IM uint32_t RFMON_CRV_LEN : 17; /*!< [16..0] RFMON_CRV_LEN */ + uint32_t : 15; + } RFMON_CRV_LEN_REG_b; + }; +} RFMON_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief RTC registers (RTC) + */ + +typedef struct /*!< (@ 0x40038000) RTC Structure */ +{ + union + { + __IOM uint32_t RTC_REQ_REG; /*!< (@ 0x00000000) RTC Request register */ + + struct + { + __OM uint32_t RTC_REQ_CLR : 1; /*!< [0..0] Clear Request of the RTC Interface, active high with + * auto clear function */ + __OM uint32_t RTC_REQ_CLR_MR : 1; /*!< [1..1] Clear Request of the mirroring FRC, active high with + * auto clear function */ + __OM uint32_t RTC_REQ_CLR_IRQ : 1; /*!< [2..2] Clear Request of the RTC IRQ Status, active high with + * auto clear function */ + __OM uint32_t RTC_REQ_LOAD_MR : 1; /*!< [3..3] Load Request of the FRC to mirroring, active high with + * auto clear function by loading done interrupt */ + uint32_t : 28; + } RTC_REQ_REG_b; + }; + + union + { + __IOM uint32_t RTC_MIRROR_REG; /*!< (@ 0x00000004) RTC Enable Mirror register */ + + struct + { + __IOM uint32_t RTC_OP_EN : 1; /*!< [0..0] Operation Enable of the RTC Interface */ + __IOM uint32_t RTC_MR_EN : 1; /*!< [1..1] Monitoring Enable of the RTC Free-Running-Counter(FRC) */ + uint32_t : 30; + } RTC_MIRROR_REG_b; + }; + + union + { + __IOM uint32_t RTC_IF_REG; /*!< (@ 0x00000008) RTC Interface register */ + + struct + { + __IOM uint32_t RTC_IF_0_DL : 4; /*!< [3..0] First logic zero duration length for RTC interface signals + * (wr_en or rd_en)0 : 1 cycle1 : 2 cycles...F : 16 cycles */ + __IOM uint32_t RTC_IF_1_DL : 4; /*!< [7..4] First logic high duration length for RTC interface signals + * (wr_en or rd_en)0 : 1 cycle1 : 2 cycles...F : 16 cycles */ + __IOM uint32_t RTC_IF_2_DL : 4; /*!< [11..8] Second logic zero duration length for RTC interface + * signals (wr_en or rd_en)0 : 1 cycle1 : 2 cycles...F : 16 + * cycles */ + uint32_t : 4; + __IOM uint32_t RTC_IF_0_DL_EN : 1; /*!< [16..16] Operation Enable of the first logic zero duration */ + __IOM uint32_t RTC_IF_1_DL_EN : 1; /*!< [17..17] Operation Enable of the first logic high duration */ + __IOM uint32_t RTC_IF_2_DL_EN : 1; /*!< [18..18] Operation Enable of the second logic zero duration */ + uint32_t : 5; + __IOM uint32_t RTC_IF_TYPE : 1; /*!< [24..24] Operation Type of the RTC Interface Clock (wr_en or + * rd_en)0 : falling edge of the bus clock (HCLK)1 : rising + * edge of the bus clock (HCLK) */ + uint32_t : 7; + } RTC_IF_REG_b; + }; + + union + { + __IOM uint32_t RTC_IRQ_EN_REG; /*!< (@ 0x0000000C) RTC Interrupt enable register */ + + struct + { + __IOM uint32_t RTC_IRQ_EN : 2; /*!< [1..0] Mask Enable of the RTC Interface's interrupt outputbit[1] + * : Access Done of the Edge Enablebit[0] : Loading Done of + * the Free-Running-Counter to mirroring */ + uint32_t : 30; + } RTC_IRQ_EN_REG_b; + }; + + union + { + __IOM uint32_t RTC_CLK_INV_REG; /*!< (@ 0x00000010) RTC Clock inverse register */ + + struct + { + __IOM uint32_t RTC_CLK_INV : 1; /*!< [0..0] RTC clock (32.768 KHz) inversion0 : bypass1 : inversion */ + uint32_t : 31; + } RTC_CLK_INV_REG_b; + }; + + union + { + __IOM uint32_t RTC_CLK_GR_CYC_REG; /*!< (@ 0x00000014) RTC Clock cycle register */ + + struct + { + __IOM uint32_t RTC_CLK_GR_CYC : 4; /*!< [3..0] Glitch Removal Cycles of RTC Clock (32.768 KHz)Delay + * cells or D-F/Fs type ? */ + uint32_t : 28; + } RTC_CLK_GR_CYC_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RTC_EDGE_REG; /*!< (@ 0x0000001C) RTC Edge mode register */ + + struct + { + __IOM uint32_t RTC_EDGE_EN : 2; /*!< [1..0] Edge Enable to access RTC Core Registers in manual modebit[1] + * : Rising edge enablebit[0] : Falling edge enable */ + uint32_t : 6; + __IOM uint32_t RTC_EDGE_AUTO_N : 1; /*!< [8..8] Automatic edge enable to access RTC Core Registers(active + * low)0 : automatic1 : manual (for debug) */ + uint32_t : 23; + } RTC_EDGE_REG_b; + }; + + union + { + __IOM uint32_t RTC_IRQ_STATUS_REG; /*!< (@ 0x00000020) RTC Interrupt Status register */ + + struct + { + __IM uint32_t RTC_IRQ_STATUS : 2; /*!< [1..0] Interrupt Status of the RTC Interfacebit[1] : Access + * Done of the Edge Enablebit[0] : Loading Done of the Free-Running-Counter + * to mirroring */ + uint32_t : 30; + } RTC_IRQ_STATUS_REG_b; + }; + + union + { + __IOM uint32_t RTC_MR_SEL_8040_REG; /*!< (@ 0x00000024) RTC Selection Mirror register */ + + struct + { + __IM uint32_t RTC_MR_SEL_8040 : 1; /*!< [0..0] Mirroring Register of the RTC SEL_8040 signal */ + uint32_t : 31; + } RTC_MR_SEL_8040_REG_b; + }; + + union + { + __IOM uint32_t RTC_MR_FRC0_REG; /*!< (@ 0x00000028) RTC FreeRun Counter0 Mirror register */ + + struct + { + __IM uint32_t RTC_MR_FRC0 : 32; /*!< [31..0] Mirroring Registers of the RTC Free-Running-Counter[31:0] */ + } RTC_MR_FRC0_REG_b; + }; + + union + { + __IOM uint32_t RTC_MR_FRC1_REG; /*!< (@ 0x0000002C) RTC FreeRun Counter1 Mirror register */ + + struct + { + __IM uint32_t RTC_MR_FRC1 : 4; /*!< [3..0] Mirroring Registers of the RTC Free-Running-Counter[35:32] */ + uint32_t : 28; + } RTC_MR_FRC1_REG_b; + }; + + union + { + __IOM uint32_t RTC_FRC_STATUS_REG; /*!< (@ 0x00000030) RTC FRC Status register */ + + struct + { + __IM uint32_t RTC_FRC_STATUS : 3; /*!< [2..0] Free-Running-Counter Status of the RTC Interfacebit[2] + * : FRC valid data 0 : valid 1 : not validbit[1:0] : retry + * number of the current FRC read access 0 : direct 1 : 1 + * retry 2 : 2 retry (happen to glitch or not) 3 : 3 retry + * (happen to glitch or not) */ + uint32_t : 29; + } RTC_FRC_STATUS_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t BCFM_REQ_CLR_IRQ_REG; /*!< (@ 0x00000040) BCFM_REQ_CLR_IRQ_REG */ + + struct + { + __OM uint32_t BCFM_REQ_START : 1; /*!< [0..0] Start Request to measure the bus clock frequency, active + * high with auto clear function by operation done interrupt */ + __OM uint32_t BCFM_REQ_CLR_IRQ : 1; /*!< [1..1] Clear Request of the BCFM IRQ Status and BCFM Core, active + * high with auto clear function */ + uint32_t : 30; + } BCFM_REQ_CLR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t BCFM_OP_EN_REG; /*!< (@ 0x00000044) BCFM_OP_EN_REG */ + + struct + { + __IOM uint32_t BCFM_OP_EN : 1; /*!< [0..0] Operation Enable of the bus clock frequency measurement */ + uint32_t : 31; + } BCFM_OP_EN_REG_b; + }; + + union + { + __IOM uint32_t BCFM_TOT_CYC_REG; /*!< (@ 0x00000048) BCFM_TOT_CYC_REG */ + + struct + { + __IOM uint32_t BCFM_TOT_CYC : 16; /*!< [15..0] Total cycles of Xtal 32.768 KHz to measure the bus clock + * frequency0 : 1 cycle1 : 2 cycles...n : n+1 cycles */ + uint32_t : 16; + } BCFM_TOT_CYC_REG_b; + }; + + union + { + __IOM uint32_t BCFM_IRQ_EN_REG; /*!< (@ 0x0000004C) BCFM_IRQ_EN_REG */ + + struct + { + __IOM uint32_t BCFM_IRQ_EN : 1; /*!< [0..0] Mask Enable of the BCFM's interrupt output[0] : BCFM + * : Operation Done */ + uint32_t : 31; + } BCFM_IRQ_EN_REG_b; + }; + + union + { + __IOM uint32_t BCFM_IRQ_STATUS_REG; /*!< (@ 0x00000050) BCFM_IRQ_STATUS_REG */ + + struct + { + __IM uint32_t BCFM_IRQ_STATUS : 1; /*!< [0..0] Interrupt Status of the BCFM1 : BCFM Operation Done */ + uint32_t : 31; + } BCFM_IRQ_STATUS_REG_b; + }; + + union + { + __IOM uint32_t BCFM_OP_STATUS_REG; /*!< (@ 0x00000054) BCFM_OP_STATUS_REG */ + + struct + { + __IM uint32_t BCFM_OP_STATUS : 2; /*!< [1..0] Operation Status of the BCFM0 : Idle1 : Waiting2 : Running3 + * : End */ + uint32_t : 30; + } BCFM_OP_STATUS_REG_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t RTC_EXP_CLR_IRQ_REG; /*!< (@ 0x00000060) RTC Exp Interrupt clear register */ + + struct + { + __OM uint32_t RTC_EXP_START : 1; /*!< [0..0] Start Request to operate RTC EXP IRQ, active high with + * auto clear function by operation done interrupt */ + __OM uint32_t RTC_EXP_CLR_IRQ : 1; /*!< [1..1] Clear Request of the RTC EXP IRQ Status, active high + * with auto clear function */ + uint32_t : 30; + } RTC_EXP_CLR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t RTC_EXP_IRQ_EN_REG; /*!< (@ 0x00000064) RTC Exp Interrupt enable register */ + + struct + { + __IOM uint32_t RTC_EXP_IRQ_EN : 3; /*!< [2..0] Enable of Interrupt Operation for the RTC Expiration + * Timerbit[2] : At the time of setting RTC_EXP_START, the + * interrupt occurs when the RTC mirror FRC is bigger than + * the threshold value.bit[1] : Interrupt occurs when RTC + * mirror FRC is turn aroundbit[0] : Interrupt occurs when + * RTC mirror FRC is equal to threshold value. */ + uint32_t : 29; + } RTC_EXP_IRQ_EN_REG_b; + }; + + union + { + __IOM uint32_t RTC_EXP_TH0_REG; /*!< (@ 0x00000068) RTC Exp Theshold0 register */ + + struct + { + __IOM uint32_t RTC_EXP_TH0 : 32; /*!< [31..0] Threshold value [31:0] to trigger the interrupt for + * the Expiration Timer */ + } RTC_EXP_TH0_REG_b; + }; + + union + { + __IOM uint32_t RTC_EXP_TH1_REG; /*!< (@ 0x0000006C) RTC Exp Theshold1 register */ + + struct + { + __IOM uint32_t RTC_EXP_TH1 : 4; /*!< [3..0] Threshold value [35:32] to trigger the interrupt for + * the Expiration Timer */ + uint32_t : 28; + } RTC_EXP_TH1_REG_b; + }; + + union + { + __IOM uint32_t RTC_EXP_OP_STS_REG; /*!< (@ 0x00000070) RTC Exp OP Status register */ + + struct + { + __IM uint32_t RTC_EXP_IRQ_STATUS : 3; /*!< [2..0] RTC_EXP_IRQ_STATUS */ + uint32_t : 5; + __IM uint32_t RTC_EXP_OP_STATUS : 1; /*!< [8..8] Operation Status of the RTC Expiration Timer0 : idle1 + * : running when RTC mirror FRC is equal to threshold value. */ + uint32_t : 23; + } RTC_EXP_OP_STS_REG_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t RTC_ACC_REQ_REG; /*!< (@ 0x00000080) RTC Access Request clear register */ + + struct + { + __OM uint32_t RTC_ACC_REQ_START : 1; /*!< [0..0] Start Request of the AHB Master to access the RTC Core + * manually, active high with auto clear function by operation + * done */ + __OM uint32_t RTC_ACC_REQ_CLR : 1; /*!< [1..1] Clear Request of the AHB Master to access the RTC Core, + * active high with auto clear function */ + uint32_t : 30; + } RTC_ACC_REQ_REG_b; + }; + + union + { + __IOM uint32_t RTC_ACC_AUTO_EN_REG; /*!< (@ 0x00000084) RTC Access Auto mode register */ + + struct + { + __IOM uint32_t RTC_ACC_AUTO_EN : 1; /*!< [0..0] Automatic Operation Enable of the AHB Master by CPU WatchDog */ + uint32_t : 31; + } RTC_ACC_AUTO_EN_REG_b; + }; + + union + { + __IOM uint32_t RTC_ACC_OP_TYPE_REG; /*!< (@ 0x00000088) RTC Access OP type register */ + + struct + { + __IOM uint32_t RTC_ACC_OP_TYPE : 3; /*!< [2..0] Operation Enable Type to access the RTC Corebit[2] : + * read enable to hold previouly values (wired and)bit[1] + * : read enable to hold previouly values (wired or)bit[0] + * : write enable to save wanted values */ + uint32_t : 29; + } RTC_ACC_OP_TYPE_REG_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t RTC_ACC_ADDR_REG; /*!< (@ 0x00000090) RTC Access Address register */ + + struct + { + __IOM uint32_t RTC_ACC_ADDR : 7; /*!< [6..0] Address to access the RTC Core */ + uint32_t : 25; + } RTC_ACC_ADDR_REG_b; + }; + + union + { + __IOM uint32_t RTC_ACC_WDATA_REG; /*!< (@ 0x00000094) RTC Access Write Data register */ + + struct + { + __IOM uint32_t RTC_ACC_WDATA : 32; /*!< [31..0] Write Data to access the RTC Core */ + } RTC_ACC_WDATA_REG_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t RTC_ACC_BUSY_REG; /*!< (@ 0x000000A0) RTC Access Busy register */ + + struct + { + __IM uint32_t RTC_ACC_BUSY : 1; /*!< [0..0] Operation Status of the AHB Bus Master0 : Idle1 : Busy */ + uint32_t : 31; + } RTC_ACC_BUSY_REG_b; + }; + __IM uint32_t RESERVED6[23]; + + union + { + __IOM uint32_t WAKEUP_CNT_0_REG; /*!< (@ 0x00000100) Wakeup Counter0 register */ + + struct + { + __IOM uint32_t WAKEUP_CNT_0 : 32; /*!< [31..0] count_value [31:0] :down count : using mask_en */ + } WAKEUP_CNT_0_REG_b; + }; + + union + { + __IOM uint32_t WAKEUP_CNT_1_REG; /*!< (@ 0x00000104) Wakeup Counter1 register */ + + struct + { + __IOM uint32_t WAKEUP_CNT_1 : 4; /*!< [3..0] count_value [35:32] :down count : using mask_en */ + uint32_t : 28; + } WAKEUP_CNT_1_REG_b; + }; + + union + { + __IOM uint32_t GPIO_WAKEUP0_REG; /*!< (@ 0x00000108) DWAKEUP0 register */ + + struct + { + __IOM uint32_t GPIO_WAKEUP_EDGE_INVERSION_SEL : 11; /*!< [10..0] edge sel : inversion of selected signal by [26:16] of + * DWAKEUP1_REG 0 : high active 1 : low active */ + uint32_t : 21; + } GPIO_WAKEUP0_REG_b; + }; + + union + { + __IOM uint32_t GPIO_WAKEUP1_REG; /*!< (@ 0x0000010C) DWAKEUP1 register */ + + struct + { + __IM uint32_t GPIO_WAKEUP_SRC : 11; /*!< [10..0] GPIO wake up source [10:0] */ + uint32_t : 5; + __IOM uint32_t GPIO_WAKEUP_EN_SEL : 11; /*!< [26..16] wakeup enable of selected signal : matching same bit + * number[16] : GPIO_P0_00[17] : GPIO_P0_08[18] : GPIO_P0_09[19] + * : GPIO_P0_10[20] : GPIO_P0_11[21] : GPIO_P0_12[22] : GPIO_P0_13[23] + * : GPIO_P1_10[24] : GPIO_P1_11[25] : GPIO_P1_12[26] : GPIO_P1_13 */ + uint32_t : 5; + } GPIO_WAKEUP1_REG_b; + }; + + union + { + __IOM uint32_t ENABLE_CTRL_REG; /*!< (@ 0x00000110) Enable_control register */ + + struct + { + __IOM uint32_t SLEEP3_EN : 1; /*!< [0..0] Power down enable : this bit becomes SLEEP3 mode enable + * bit. */ + __IOM uint32_t WATCHDOG_OUT_INT_EN : 1; /*!< [1..1] WatchDog Enable :It should be set to enable after setting + * WDOG_COUNTER_BIT_POS_REG register (0x015C). */ + __IOM uint32_t BROWN_OUT_LOW_INT_EN : 1; /*!< [2..2] Brown out detector interrupt enable when falling edge */ + __IOM uint32_t BROWN_OUT_HIGH_INT_EN : 1; /*!< [3..3] Brown out detector interrupt enable when rising edge */ + __IOM uint32_t REAL_CNT_LOAD : 1; /*!< [4..4] CLOCK ENABLE for adc sensor and pulse cnt functions */ + __IOM uint32_t DIG_LDO_DELAY : 2; /*!< [6..5] DIG LDO turn on time delay logic00 : 2 clocks behind + * dcdc_ana01 : 4 clocks delay10 : 8 clocks delay11 : 10 clocks + * delay */ + uint32_t : 1; + __IOM uint32_t SLEEP4_EN : 1; /*!< [8..8] SLEEP4 mode enable bit, cleared by HW automatically */ + __IOM uint32_t SLEEP5_EN : 1; /*!< [9..9] SLEEP5 mode enable bit, cleared by HW automatically */ + __IOM uint32_t BLACK_OUT_LOW_INT_EN : 1; /*!< [10..10] Black out detector interrupt enable when falling edge */ + __IOM uint32_t BLACK_OUT_HIGH_INT_EN : 1; /*!< [11..11] Black out detector interrupt enable when rising edge */ + uint32_t : 20; + } ENABLE_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CLK_XTAL32K_REG; /*!< (@ 0x00000114) XTAL32Khz Control register */ + + struct + { + __IOM uint32_t PDB_OSC_EN : 1; /*!< [0..0] PDB_OSC32kHz Oscillator Power on/off (active high) (default:1) */ + __IOM uint32_t XTAL_BAT_EN : 1; /*!< [1..1] EN_XTAL_BAT32kHz Crystal Power on/off (active high) (default:1) */ + __IOM uint32_t XTAL_CLK_SEL : 2; /*!< [3..2] CLK_SEL[1:0]Select clock source (default 32kHz OSC.)0 + * : 32kHz OSC. 1 : 32kHz Crystal 2 : for Test */ + __IOM uint32_t XR_BAT_EN : 1; /*!< [4..4] EN_XR_BATExternal resistor enable 0 : Internal resistor + * used, (default)1 : External resistor used (It is possible + * to input 10MHz Ext RTC) */ + __IOM uint32_t XTAL_LDO_CTRL : 3; /*!< [7..5] XTAL_LDO_CTRL BIT */ + __IOM uint32_t XTAL_LDO_I_CTRL : 2; /*!< [9..8] XTAL_LDO_I_CTRL BIT */ + __IOM uint32_t VBAT_BIAS_I_CTRL : 1; /*!< [10..10] VBAT_BIAS_I_CTRL BIT */ + uint32_t : 21; + } CLK_XTAL32K_REG_b; + }; + + union + { + __IOM uint32_t RTM_CONTROL_REG; /*!< (@ 0x00000118) RTM Control register */ + + struct + { + __IOM uint32_t RTM_CTRL_PDB_ISO : 1; /*!< [0..0] PDB_ISO - default 1 1 : Isolation cell disable, Access + * to RTM,0 : Isolation cell enable, Not access to RTM */ + __IOM uint32_t RTM_INFO : 1; /*!< [1..1] RTM_INFORM */ + __IOM uint32_t RTM_CTRL_PDP_ISO_SHARED_IO : 1; /*!< [2..2] PDB_ISO_shared_io - default 01: isolation cell disable + * access to GPIO4~7Note : [24] when SEN_VDD, bit[2] should + * be set as well */ + __IOM uint32_t RTM_CTRL_PWR_DN_INFO : 4; /*!< [6..3] power down information */ + uint32_t : 1; + __IOM uint32_t RTM_CTRL_RET_SLR : 3; /*!< [10..8] RET_SLR[2:0] Retention Sleep Enable : shutdown mode + * - contents are lost. */ + __IOM uint32_t RTM_CTRL_RET_RET : 3; /*!< [13..11] RET_RET[2:0] Retention memory retention signal enable */ + uint32_t : 2; + __IOM uint32_t RTM_CTRL_IO_RETEN_CTRL : 5; /*!< [20..16] IO retention control bit[20] : reton_vbat : P0_00 ~ + * P0_03[19] : reton_fdio : P1_00 ~ P1_09[18] : reton_dio2 + * : P1_10 ~ P1_15, SWCLK,SWDIO[17] : reton_dio1_2 : P0_08 + * ~ P0_13[16] : reton_dio1_1 : P0_04 ~ P0_07l */ + uint32_t : 11; + } RTM_CONTROL_REG_b; + }; + + union + { + __IOM uint32_t DCDC_CNTL_OFF_REG; /*!< (@ 0x0000011C) DCDC Control Off register */ + + struct + { + __IOM uint32_t DCDC_PWR_OFF : 1; /*!< [0..0] DCDC1.2 power off, when set '1', DCDC1.2 Off */ + __IOM uint32_t DCDC_AUTO_PWR_ON_EN : 1; /*!< [1..1] Auto Power On Enable ( activate function of the SW POR + * Reset) */ + uint32_t : 30; + } DCDC_CNTL_OFF_REG_b; + }; + + union + { + __IOM uint32_t LDO_ENABLE_REG; /*!< (@ 0x00000120) LDO Enable register */ + + struct + { + __IOM uint32_t LDO_EN_PDB_XTAL_NOISE_REDU : 1; /*!< [0..0] PDB_XTAL_NOISE_REDU : XTAL noise reduction (active high) + * (default = 0) :It should be turn on before RF_CS on. make + * turn on with RF_LDO_ON concurrently.It is reset to 0 when + * sleep mode.(This field is nois reduction filter enable. + * XTAL40M is turned on when DCDC on state.) */ + __IOM uint32_t EN_FDIO_PULLDN : 1; /*!< [1..1] pull down switch for FDIO_LDO */ + __IOM uint32_t LDO_EN_LDO_PLL1 : 1; /*!< [2..2] LDO_PLL1,It is reset 0 when sleep mode */ + __IOM uint32_t LDO_EN_OTP_PWRPRDY : 1; /*!< [3..3] OTP_PWRPRDY - otp power ready */ + __IOM uint32_t LDO_EN_PDB_IP3_OTP : 1; /*!< [4..4] PDB_IP3_OTP : OTP power switch default 1 */ + __IOM uint32_t LDO_EN_PDB_ULDO : 1; /*!< [5..5] It turns on uLDO once OTP is not ready or uLDO manual + * control is not activated.0: uLDO is turned offonce OTP + * is not ready and uLDO manual control is not activated.1: + * uLDO is turned on once OTP is not ready or uLDO manual + * control is not activated. */ + __IOM uint32_t LDO_EN_DCDC_CNTL_XTAL : 1; /*!< [6..6] It turns on the LDO for the 40MHz crystal.0: Off, 1: + * On */ + __IOM uint32_t LDO_EN_DIG_LDO_CNTL : 1; /*!< [7..7] DIG_LDO_CNTL */ + __IOM uint32_t LDO_EN_PDB_RF_LDO : 1; /*!< [8..8] PDB_RF_LDO (default = 0)It is substiute signal of the + * PDB_DCDC_ANA in Tin.It is reset 0 when sleep mode. */ + __IOM uint32_t LDO_EN_PDB_IP1_LDO : 1; /*!< [9..9] PDB_IP1_LDO : when sleep mode, reset to 0 (IQADC/DAC + * power cont) */ + __IOM uint32_t LDO_EN_FLASH_DIO_MANUAL_MODE : 1; /*!< [10..10] Flash_DIO LDO manual mode enable bit 0:auto mode, 1:manual + * mode */ + __IOM uint32_t LDO_EN_FLASH_DIO_MANUAL_VAL : 1; /*!< [11..11] Flash_DIO LDO manual mode valueif set bit[10] to 1, + * transfer a value of the bit[11] */ + __IOM uint32_t LDO_EN_RESET_12V_HOLD_EN : 1; /*!< [12..12] RESET_12V hold enable :if set to 1, hold reset signal + * to 1 in the BB */ + __IOM uint32_t LDO_EN_BOOST_PWR_OFF : 1; /*!< [13..13] Change the function of this bit : default 00 : xtal40Mhz + * supplies to dcore1 : OSC10Mhz supplies to dcore */ + __IOM uint32_t LDO_EN_DCDC_CTRL_OFF : 1; /*!< [14..14] It forcibly turns off the DCDC_ANA. It should be activated + * to operatate in normal mode.0: DCDC_ANA is controlled by + * hardware.1: DCDC_ANA is forcibly turend off. */ + __IOM uint32_t FLASH_LDO_AUTO_OFF : 1; /*!< [15..15] Flash LDO off when next wakeup, HW does not turn on + * the Flash LDO enable at the next wakeup.0: on1: off */ + __IOM uint32_t EN_ST_PAD_DCDC_BYP : 1; /*!< [16..16] bypass control of soft start (pa_dcdc) */ + __IOM uint32_t EN_DCDC_PA : 1; /*!< [17..17] enable of dcdc_pa */ + __IOM uint32_t CTRL_ST_PA_DCDC : 5; /*!< [22..18] soft start duration time for dcdc_pa */ + __IOM uint32_t EN_LP_DIG_LDO : 1; /*!< [23..23] enable for LP_DIG_LDO (Active high) */ + __IOM uint32_t CFG_LPDIGLDO_I : 2; /*!< [25..24] current control for LP_DIG_LDO (50/75/100/125nA) */ + __IOM uint32_t CFG_LPDIG_LDO_V : 4; /*!< [29..26] Reference V (to LPDIG), 0.8 ~ 1.16V (0.025V step (default + * : 1.1V) */ + uint32_t : 2; + } LDO_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t CNT_TESTI_REG; /*!< (@ 0x00000124) Counter Testi register */ + + struct + { + __IOM uint32_t IP3_PWR_ON_REG : 1; /*!< [0..0] IP3_PWR_ON=PD_SEN power control signaldefualt : 1 (power + * on) */ + __IOM uint32_t BR_TESTI_REG : 1; /*!< [1..1] BR/BL Int test enable bit.1 : BR/BL On signal can be + * get via P0_08 */ + uint32_t : 3; + __IM uint32_t I_SIGNAL : 1; /*!< [5..5] read only : I_SIGNAL of pulse Cnt input for testing */ + __IM uint32_t EXT_INT_BL : 1; /*!< [6..6] read only : BL Int */ + __IM uint32_t EXT_INT_BR : 1; /*!< [7..7] read only : BR Int */ + __IOM uint32_t AUXADC12_CS : 3; /*!< [10..8] AuxADC12_CS [2:0] */ + __IOM uint32_t EN_DPLL_CLK_BYPASS : 1; /*!< [11..11] AuxADC12_CS [2:0] */ + uint32_t : 4; + __IOM uint32_t EN_RTC_GPO_SW_VBAT : 1; /*!< [16..16] GPIO GPO(SEN_OUT) function enable (Active high) */ + __IOM uint32_t EN_XTAL40M_LDO_MON : 1; /*!< [17..17] monitor path enable for XTAL40M_LDO (Active high) */ + __IOM uint32_t EN_DFT_NBIAS : 1; /*!< [18..18] nbias manual enable for DRA test mode */ + __IOM uint32_t DFT_SEL_ANA_BGR : 2; /*!< [20..19] DFT_SEL_ANA_BGR */ + __IOM uint32_t EN_NBIAS_TRIM : 1; /*!< [21..21] trimming enable for nBIAS (Active high) */ + __IOM uint32_t EN_DFT_VDDD_RET : 1; /*!< [22..22] DfT path enable for vref of uLDO (Active high) */ + __IOM uint32_t EN_DFT_VREF : 1; /*!< [23..23] DfT path enable for vref of nBIAS (Active high) */ + __IOM uint32_t TRIM_NBIAS_I : 4; /*!< [27..24] current trim control for nBIAS */ + __IOM uint32_t EN_LP_DIG_LDO_MON : 1; /*!< [28..28] monitor path enable for LP_DIG_LDO (Active high) */ + __IOM uint32_t EN_LDO_ADCSEN_MON : 1; /*!< [29..29] monitor path enable for adcsen_LDO (Active high) */ + __IOM uint32_t EN_LDO_DPLL_MON : 1; /*!< [30..30] monitor path enable for DPLL480M_LDO (Active high) */ + __IM uint32_t DFT_NBIAS_TRIM : 1; /*!< [31..31] Comp output for trim */ + } CNT_TESTI_REG_b; + }; + + union + { + __IOM uint32_t WAKEUP_SRC_CLR_SIG_REG; /*!< (@ 0x00000128) Wakeup source clear signal register */ + + struct + { + __IOM uint32_t GPIO_WAKE_UP_DETECT : 1; /*!< [0..0] GPIO Wake Up signal detect : refer to GPIO_WAKEUP1_REG */ + __IOM uint32_t FRC_COMPARE_DETECT : 1; /*!< [1..1] FRC compare detect */ + __IOM uint32_t POR_INDICATOR : 1; /*!< [2..2] POR indicator */ + __IOM uint32_t WATCHDOG_DETECT : 1; /*!< [3..3] WatchDog detect */ + __IOM uint32_t ADC_DETECT : 1; /*!< [4..4] sensor(ADC) detect */ + __IOM uint32_t PULSE_CNT_DETECT : 1; /*!< [5..5] Pulse CNT detect */ + __IOM uint32_t TIMER_IRQ_DETECT : 1; /*!< [6..6] timers irq detected in sleep4/5.Oring : timers irq/wdog_nmi_sync/mac_ti + * er_irq */ + uint32_t : 1; + __IM uint32_t ADC_WAKEUP_STATUS : 4; /*!< [11..8] ADC Sensor WakeUp status [11] : Sensor WakeUp 3 [10] + * : Sensor WakeUp 2 [ 9] : Sensor WakeUp 1 [ 8] : Sensor + * WakeUp 0 */ + uint32_t : 20; + } WAKEUP_SRC_CLR_SIG_REG_b; + }; + + union + { + __IOM uint32_t RCX32K_REG; /*!< (@ 0x0000012C) RCX32K trim register */ + + struct + { + __IOM uint32_t TRIM_RCX32K_ROSC : 14; /*!< [13..0] rcx32k trimming (resistor),12bit */ + __IOM uint32_t CFG_TEST_HI : 2; /*!< [15..14] trimmng control */ + __IOM uint32_t TRIM_RCX32K_COSC : 2; /*!< [17..16] rcx32k trimming (capacitor), 2bit */ + uint32_t : 14; + } RCX32K_REG_b; + }; + + union + { + __IOM uint32_t LDO_ENABLE2_REG; /*!< (@ 0x00000130) uLDO Enable register */ + + struct + { + __IOM uint32_t RTC_XTAL40M_EN : 1; /*!< [0..0] XTAL40M IP enable signal */ + __IOM uint32_t ULDO_MAN_CONT : 1; /*!< [1..1] uLDO manual control enable signal0 : off1 : manual control + * en, when 1, UDLO_MAN_CONT_VALUE signal goes to PDB_uLDO */ + __IOM uint32_t ULDO_MAN_CONT_VALUE : 1; /*!< [2..2] when UDLO_MAN_CONT =1 , this bit goes to en_pdb_uldo_3V3. */ + __IOM uint32_t EN_TST_GPIO0 : 1; /*!< [3..3] GPIO to GPADC connection control ma tp P0_050 : open1 + * : short */ + __IOM uint32_t EN_TST_GPIO1 : 1; /*!< [4..4] GPIO to GPADC connection control ma tp P0_060 : open1 + * : short */ + __IOM uint32_t EN_TST_GPIO2 : 1; /*!< [5..5] GPIO to GPADC connection control ma tp P0_070 : open1 + * : short */ + __IOM uint32_t EN_TST_GPIO3 : 1; /*!< [6..6] GPIO to GPADC connection control ma tp P0_040 : open1 + * : short */ + __IOM uint32_t EN_TST_INT : 1; /*!< [7..7] test enable bit for internal test logic */ + uint32_t : 24; + } LDO_ENABLE2_REG_b; + }; + + union + { + __IOM uint32_t CNT_BASE_TESTI_REG; /*!< (@ 0x00000134) Counter Value read register */ + + struct + { + __IM uint32_t TIN_CNT_BASE : 5; /*!< [4..0] Counter reset value = h14 for testing */ + __IM uint32_t TIN_CNT_TEST1 : 5; /*!< [9..5] Counter read value for testing 1 */ + __IM uint32_t TIN_CNT_TEST2 : 5; /*!< [14..10] Counter read value for testing2 */ + uint32_t : 17; + } CNT_BASE_TESTI_REG_b; + }; + + union + { + __IOM uint32_t FRC_CNT_0_REG; /*!< (@ 0x00000138) FRC Counter0 register */ + + struct + { + __IM uint32_t FRC_CNT_0 : 32; /*!< [31..0] RTC Free runing count read value[31:0] : down count + * : use mask_en */ + } FRC_CNT_0_REG_b; + }; + + union + { + __IOM uint32_t FRC_CNT_1_REG; /*!< (@ 0x0000013C) FRC Counter1 register */ + + struct + { + __IM uint32_t FRC_CNT_1 : 4; /*!< [3..0] RTC Free runing count read value[35:32] : down count + * : use mask_en */ + uint32_t : 28; + } FRC_CNT_1_REG_b; + }; + + union + { + __IOM uint32_t READ_STATUS_REG; /*!< (@ 0x00000140) Read Status register */ + + struct + { + __IM uint32_t WAKE_UP_SOURCE__RD_STATUS : 1; /*!< [0..0] wake up source */ + __IM uint32_t X12_CLK_RD_STATUS : 1; /*!< [1..1] X12_Clk */ + uint32_t : 1; + __IM uint32_t XTAL_RDY_BAT_RD_STATUS : 1; /*!< [3..3] XTAL_RDY_BAT */ + __IM uint32_t WTEMPEQCOMPWKCNT_RD_STATUS : 1; /*!< [4..4] wTempEqCompWkCnt */ + __IM uint32_t OTP_RDY_RD_STATUS : 1; /*!< [5..5] wTempEqCompBit7Cnt */ + __IM uint32_t RESET_POSITION_RD_STATUS : 1; /*!< [6..6] wTempEqCompBit6Cnt */ + __IM uint32_t WWATCHDOGCLK_RD_STATUS : 1; /*!< [7..7] wWatchDogClk */ + __IM uint32_t XTAL40M_RDY_VBAT_RD_STATUS : 1; /*!< [8..8] XTAL40M_RDY_VBAT */ + __IM uint32_t RF_LDO_RDY_VBAT_RD_STATUS : 1; /*!< [9..9] RF_LDO_RDY_VBAT */ + __IM uint32_t DIG_LDO_RDY_VBAT_RD_STATUS : 1; /*!< [10..10] DIG_LDO_RDY_VBAT */ + __IM uint32_t F_LDO_RDY_RD_STATUS : 1; /*!< [11..11] F_LDO_RDY */ + __IM uint32_t DCDC_RDY_VBAT_RD_STATUS : 1; /*!< [12..12] DCDC_RDY_VBAT */ + __IM uint32_t IP1_LDO_RDY_VBAT_RD_STATUS : 1; /*!< [13..13] IP1_LDO_RDY_VBAT */ + __IM uint32_t LP_DIG_LDO_OK_RD_STATUS : 1; /*!< [14..14] LP_DIG_LDO_FLAG signal */ + __IM uint32_t DCDC_PA_OK_RD_STATUS : 1; /*!< [15..15] Flag_dcdc_pa_ok signal */ + uint32_t : 16; + } READ_STATUS_REG_b; + }; + + union + { + __IOM uint32_t ULDO_CONT_REG; /*!< (@ 0x00000144) uLDO Control register */ + + struct + { + __IOM uint32_t RTC_CLK_INVERSION : 1; /*!< [0..0] RTC clock inversion : 0 : bypass 1 : inversion */ + __IOM uint32_t PDB_TEST_BUF : 1; /*!< [1..1] PDB_TEST_BUF : IP2 test buffer enable */ + uint32_t : 2; + __IOM uint32_t RTC_ULDO_VCTRL : 4; /*!< [7..4] It determines the voltage level of the uLDO. the default + * value is '1' and 1.14V.0:1.16V, 1:1.14V, 2:1.12V, 3:1.1V, + * 4:107V, 5:1.04V, 6:1.02V, 7:1.00V,8:0.97V, 9:0.95V, 10:0.93V, + * 11:0.90V, 12:0.88V, 13:0.86V, 14:0.93V, 15:0.80V */ + __IOM uint32_t RTC_ULDO_HICTRL : 2; /*!< [9..8] It turns on the 6uA bleeding current in the uLDO. The + * bleeding current setting is automatically changed to ULDO_HICTRL_SLP + * during sleep mode.0: Turn off the bleeding current1~3: + * Turn on the bleeding current */ + __IOM uint32_t RTC_ULDO_LICTRL : 2; /*!< [11..10] RTC_uLDO_LICTRL default : 2'b01 */ + __IOM uint32_t RTC_XTAL32K_ICTRL : 2; /*!< [13..12] RTC_XTAL32K_ICTRL default : 2'b01 */ + __IOM uint32_t RTC_OSC32K_ICTRL : 2; /*!< [15..14] RTC_OSC32K_ICTRL default : 2'b00 */ + __IOM uint32_t RTC_XTAL32K_GM : 2; /*!< [17..16] RTC_XTAL32K_GM default : 2'b11 */ + __IM uint32_t FLAG_DVDD_POR : 1; /*!< [18..18] DVDD POR OK Flag */ + __IM uint32_t FLAG_LDODCDC_POR : 1; /*!< [19..19] LDO DCDC POR OK Flag */ + __IM uint32_t FLAG_RCORE_POR : 1; /*!< [20..20] Rcore POR OK Flag */ + __IM uint32_t FLAG_SEN_DVDD_POR : 1; /*!< [21..21] SEN DVDD Por OK flag */ + __IM uint32_t FLAG_ADCSEN_LDO : 1; /*!< [22..22] ADCSEN LDO OK flag */ + __IM uint32_t FLAG_DPLL_LDO : 1; /*!< [23..23] DPLL LDO OK flag */ + __IOM uint32_t DCDC_ST_CTRL_4_0 : 5; /*!< [28..24] DCDC_ST_CTRL[4:0] default */ + __IOM uint32_t DCDC_ST_BYP : 1; /*!< [29..29] DCDC_ST_BYP bit */ + uint32_t : 2; + } ULDO_CONT_REG_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t BOR_CIRCUIT_REG; /*!< (@ 0x0000014C) BOR circuit */ + + struct + { + __IOM uint32_t BL_OUT_CTRL : 4; /*!< [3..0] Black out control : When CTRL is 0, V_HtoL(AVR) : 1.232 + * V_LtoH(AVR) : 1.405 Hysteresis(AVR) : 0.173When CTRL is + * 1, V_HtoL(AVR) : 1.412 V_LtoH(AVR) : 1.516 Hysteresis(AVR) + * : 0.104When CTRL is 2, V_HtoL(AVR) : 1.523 V_LtoH(AVR) + * : 1.619 Hysteresis(AVR) : 0.096 (BlackOut Default)When + * CTRL is 3, V_HtoL(AVR) : 1.618 V_LtoH(AVR) : 1.715 Hysteresis(AVR) + * : 0.097When CTRL is 4, V_HtoL(AVR) : 1.733 V_LtoH(AVR) + * : 1.827 Hysteresis(AVR) : 0.095When CTRL is 5, V_HtoL(AVR) + * : 1.826 V_LtoH(AV */ + __IOM uint32_t BR_OUT_CTRL : 4; /*!< [7..4] Brown out control */ + __IOM uint32_t BL_OUT_EN : 1; /*!< [8..8] Black out enable */ + __IOM uint32_t BR_OUT_EN : 1; /*!< [9..9] Brown out enable */ + __IOM uint32_t RF_LO_CAL_ENABLE : 1; /*!< [10..10] RF LO calibration enable for 5G */ + __IOM uint32_t BL_HYS_CTRL : 1; /*!< [11..11] Black out Hysterisys Control */ + __IOM uint32_t BR_HYS_CTRL : 1; /*!< [12..12] Brown out Hysterisys Control */ + __IM uint32_t BL_STATUS_READ : 1; /*!< [13..13] Black out status read */ + __IM uint32_t BR_STATUS_READ : 1; /*!< [14..14] Brown out status read */ + uint32_t : 17; + } BOR_CIRCUIT_REG_b; + }; + + union + { + __IOM uint32_t TEST_ULDO_SLP_CTRL_REG; /*!< (@ 0x00000150) Test Control register */ + + struct + { + __IOM uint32_t TEST_SEL_8040 : 3; /*!< [2..0] sel_8040 : debug port ? signal out */ + __IOM uint32_t TEST_SENSOR_OUTPUT_MUX_1 : 1; /*!< [3..3] sensor output port mux : 0 : SS_EN auto mode, sensor + * out 1 : SS_EN manual mode, A_FLASH_EN reg_60[7] for SS_EN + * output */ + __IOM uint32_t TEST_SENSOR_OUTPUT_MUX_0 : 1; /*!< [4..4] sensor output port mux : 1 : sensor out 0 : RTC_CNT_OUT + * (boost DCDC control) */ + __IOM uint32_t TEST_DW_WAKE_UP_RST_CTRL : 1; /*!< [5..5] dw_wake_up sub module reset control( reset : low active)default + * : 1 */ + __IOM uint32_t TEST_SS_EN_SEL : 2; /*!< [7..6] SS_EN output selection for testing.00 : RTC_CNT_OUT (default)01 + * : POR - test purpose10 : Brown Out signal - test purpose11 + * : Black Out singal - test purpose */ + __IOM uint32_t ULDO_VCTRL_SLP : 4; /*!< [11..8] uLDO control signal for Sleep mode (default : 4'b1100)when + * sleep mode, this value is applied to uLDO */ + __IOM uint32_t ULDO_HICTRL_SLP : 2; /*!< [13..12] It determines whether the 6uA bleeding current in the + * uLDO is on or off during sleep mode0: Turn off the bleeding + * current during sleep mode.1~3: Turn on the 6uA bleeding + * current during sleep mode. */ + uint32_t : 18; + } TEST_ULDO_SLP_CTRL_REG_b; + }; + + union + { + __IOM uint32_t IP4_FLDO_BG_CONT_REG; /*!< (@ 0x00000154) FLDO BandGap Control register */ + + struct + { + __IOM uint32_t FLDO_VCTRL0 : 1; /*!< [0..0] Flash LDO Voltage Control0 */ + __IOM uint32_t FLDO_VCTRL1 : 1; /*!< [1..1] Flash LDO Voltage Control1 */ + __IOM uint32_t FLDO_VCTRL2 : 1; /*!< [2..2] Flash LDO Voltage Control2 */ + __IOM uint32_t VBG_TRIM0 : 1; /*!< [3..3] VBG Trim0 */ + __IOM uint32_t VBG_TRIM1 : 1; /*!< [4..4] VBG Trim1 */ + __IOM uint32_t VBG_TRIM2 : 1; /*!< [5..5] VBG Trim2 */ + uint32_t : 2; + __IOM uint32_t F_DIO_ST_CTRL : 4; /*!< [11..8] Flash DIO control */ + __IOM uint32_t F_DIO_ST_BYP_EN : 1; /*!< [12..12] Flash DIO Bypass enable */ + uint32_t : 19; + } IP4_FLDO_BG_CONT_REG_b; + }; + + union + { + __IOM uint32_t WAKEUP_SRC_CLR_REG; /*!< (@ 0x00000158) Wakeup source clear signal read register */ + + struct + { + __IM uint32_t WAKEUP_GPIOWKCLR : 1; /*!< [0..0] ExtWkClr */ + __IM uint32_t WAKEUP_EQCLR : 1; /*!< [1..1] EqClr */ + __IM uint32_t WAKEUP_PORCLR : 1; /*!< [2..2] PorClr */ + __IM uint32_t WAKEUP_WATCHDOGCLR : 1; /*!< [3..3] WatchDogClr */ + __IM uint32_t WAKEUP_SENSOR_DETECT_CLEAR : 1; /*!< [4..4] sensor detect clear */ + __IM uint32_t WAKEUP_PULSE_CNT_DETECT_CLEAR : 1; /*!< [5..5] pulse cnt detect clear */ + __IM uint32_t WAKEUP_TIMER_IRQ_DETECT_CLEAR : 1; /*!< [6..6] timers irq detect clear */ + uint32_t : 25; + } WAKEUP_SRC_CLR_REG_b; + }; + + union + { + __IOM uint32_t WDOG_CNT_BIT_POS_REG; /*!< (@ 0x0000015C) Watchdog Counter bit position register */ + + struct + { + __IOM uint32_t FRC35_14_BIT_SEL : 5; /*!< [4..0] FRC[35:14] bit selection */ + __IM uint32_t WATCHDOG_CNT_READ_VAL : 2; /*!< [6..5] WatchDog Count read value */ + uint32_t : 25; + } WDOG_CNT_BIT_POS_REG_b; + }; + + union + { + __IOM uint32_t XADC12_CNTL_REG; /*!< (@ 0x00000160) AuxADC12 Control register */ + + struct + { + __IOM uint32_t AUXADC12_RESET : 1; /*!< [0..0] AuxADC12_RESET */ + __IOM uint32_t AUXADC12_PDB : 1; /*!< [1..1] AuxADC12_PDB */ + uint32_t : 2; + __IOM uint32_t AUXADC12_TRIM : 3; /*!< [6..4] AuxADC12_TRIM [2:0] */ + __IOM uint32_t SS_EN_OUTPUT_VAL : 1; /*!< [7..7] SS_EN output value @Test Control[4] */ + __IOM uint32_t AUXADC12_ICOMP : 2; /*!< [9..8] AuxADC12_ICOMP [1:0] */ + __IOM uint32_t AUXADC12_ICOMPS : 2; /*!< [11..10] AuxADC12_ICOMPS [1:0] */ + __IOM uint32_t AUXADC12_IVREF : 2; /*!< [13..12] AuxADC12_IVREF [1:0] */ + __IOM uint32_t AUXADC12_BITNUM : 2; /*!< [15..14] AuxADC12_BITNUM [1:0] */ + uint32_t : 16; + } XADC12_CNTL_REG_b; + }; + + union + { + __IOM uint32_t XADC12_THR01_REG; /*!< (@ 0x00000164) AuxADC12 Threshold Level2 register */ + + struct + { + __IOM uint32_t XADC12_THR_LEVEL0_CH0 : 12; /*!< [11..0] Threshold Level0[11:0] for Channel-0 */ + __IOM uint32_t XADC12_THR_CONFIG_CH0 : 2; /*!< [13..12] Threshold mode selection00: Over threshold01: Under + * threshold10: Different threshold */ + uint32_t : 2; + __IOM uint32_t XADC12_THR_LEVEL1_CH2 : 12; /*!< [27..16] Threshold Level1[11:0] for Channel-1 */ + __IOM uint32_t XADC12_THR_CONFIG_CH1 : 2; /*!< [29..28] Threshold mode selection00: Over threshold01: Under + * threshold10: Different threshold */ + uint32_t : 2; + } XADC12_THR01_REG_b; + }; + + union + { + __IOM uint32_t XADC12_THR23_REG; /*!< (@ 0x00000168) AuxADC12 Threshold Level1 register */ + + struct + { + __IOM uint32_t XADC12_THR_LEVEL2_CH2 : 12; /*!< [11..0] Threshold Level2[11:0] for Channel-2 */ + __IOM uint32_t XADC12_THR_CONFIG_CH2 : 2; /*!< [13..12] Threshold mode selection00: Over threshold01: Under + * threshold10: Different threshold */ + uint32_t : 2; + __IOM uint32_t XADC12_THR_LEVEL3_CH3 : 12; /*!< [27..16] Threshold Level3[11:0] for Channel-3 */ + __IOM uint32_t XADC12_THR_CONFIG_CH3 : 2; /*!< [29..28] Threshold mode selection00: Over threshold01: Under + * threshold10: Different threshold */ + uint32_t : 2; + } XADC12_THR23_REG_b; + }; + + union + { + __IOM uint32_t XADC12_SP_NUM_REG; /*!< (@ 0x0000016C) AuxADC12 Sample Number regster */ + + struct + { + __IOM uint32_t ADC_SMLP_NUM_AVR : 3; /*!< [2..0] sample number for average (sample count = 2n+2) 000 = + * 4-sample processing 001 = 8-sample processing 111 = 512-sample + * processing */ + __IOM uint32_t ADC_SAMPLE_RANGE_SEL : 5; /*!< [7..3] ADC sample select range - value of ADC data summation + * in any timing range */ + uint32_t : 24; + } XADC12_SP_NUM_REG_b; + }; + + union + { + __IOM uint32_t XADC12_TIMER_SET_REG; /*!< (@ 0x00000170) AuxADC12 Timer Set register */ + + struct + { + __IOM uint32_t AX12B_TIMER_VAL : 4; /*!< [3..0] REG_AX12B_TIMER_SET[3:0] Timer value (main_cnt) - periodic + * cycle = X12_Clk x main_cnt - valid range = 0x0 ~ 0xF, max + * value = 0xF @bit[6:4] 3'b000 : range = 7.8 ~ 124.8msec + * 3'b001 : range = 15.6 ~ 250.0msec 3'b010 : range = 62.5 + * ~ 1000.0msec 3'b011 : range = 250 ~ 4,000msec 3'b100 : + * range = 1,000 ~ 16,000msec 3'b101 : range = 4,000 ~ 64,000msec + * (max. 64sec) 3'b110 : range = 16,000 ~ 256,000msec (max. + * 4.2min) 3'b111 : range = */ + __IOM uint32_t X12_CLK_TMR_CNT_SRC : 3; /*!< [6..4] X12_Clk : timer count clock source (base = 32.768KHz) + * 3'b000 = 7.81-msec period 3'b001 = 31.25-msec period 3'b010 + * = 62.5-msec period 3'b011 = 250-msec period 3'b100 = 1000-msec + * period 3'b101 = 4000-msec period 3'b110 = 16000-msec period + * 3'b111 = 64,000-msec period */ + __IOM uint32_t SENSOR_DETECT_ACT : 1; /*!< [7..7] Sensor detect activate 1 = Sensor mode enable 0 = Normal + * mode */ + __IOM uint32_t IP3_ACTIVATE_TMR_VAL : 6; /*!< [13..8] IP3_ACTIVATE timer value : IP3 Power on time (sub_cnt) + * : delta T = N x X12_Clk + 8/32.768KHz x sub_cnt valid range + * = 0x00 ~ 0x3B, max. = 0x3B */ + uint32_t : 2; + __IOM uint32_t EXT_SEN_ACTIVATE_TMR_VAL : 4; /*!< [19..16] EXT_SEN_ACTIVATE timer value : External sensor on time + * : should be set under REG_AX12B_TIMER_SET[3:0] value valid + * range N = 0x0 ~ 0xE, max. = 0xE */ + uint32_t : 4; + __IOM uint32_t ASWCH_CTRL : 5; /*!< [28..24] ASWCH_CTRL [28] : Auto-switch activate [27:24] : channel + * selection [27]=Ch-3, [26]=Ch-2, [25]=Ch-1, [24]=Ch-0 */ + uint32_t : 3; + } XADC12_TIMER_SET_REG_b; + }; + + union + { + __IOM uint32_t COMP_INT_REG; /*!< (@ 0x00000174) Compare Interrupt register */ + + struct + { + __IOM uint32_t OSC_15M_ENABLE : 1; /*!< [0..0] OSC_15Mhz Enable : default enable 1due to prevent glitch + * attack, OSC15Mhz turns on by HW. */ + __IOM uint32_t CNT_ENABLE : 1; /*!< [1..1] Pulse counter Enable */ + __IOM uint32_t CNT_RST : 1; /*!< [2..2] Pulse counter Reset */ + __IOM uint32_t EDGE_SEL : 1; /*!< [3..3] count up edge 0: rising 1: falling */ + __IOM uint32_t G_FILTER_EN : 1; /*!< [4..4] ignore short glitch0: disable1: enable */ + uint32_t : 3; + __IOM uint32_t G_FILTER_THR : 5; /*!< [12..8] filtering threshold */ + uint32_t : 1; + __IOM uint32_t INT_EN : 1; /*!< [14..14] Interrupt Enable 0: disable 1: enable */ + __IOM uint32_t INT_CLR : 1; /*!< [15..15] Interrupt clear */ + __IOM uint32_t PULSE_SELECT : 4; /*!< [19..16] Input source Selection for PulseCnt0 : GPIO_P0_001 + * : GPIO_P0_082 : GPIO_P0_093 : GPIO_P0_104 : GPIO_P0_115 + * : GPIO_P0_126 : GPIO_P0_137 : GPIO_P1_108 : GPIO_P1_119 + * : GPIO_P1_1210 : GPIO_P1_13 */ + __IOM uint32_t CLK_SEL : 1; /*!< [20..20] Pulse counter operation clock select bit0 : 32Khz1 + * : 15Mhz */ + uint32_t : 2; + __IM uint32_t COMPINT : 1; /*!< [23..23] Interrtup threshold ? Counter Compare Value */ + uint32_t : 8; + } COMP_INT_REG_b; + }; + + union + { + __IOM uint32_t INT_THR_REG; /*!< (@ 0x00000178) Interrupt Threshold register */ + + struct + { + __IOM uint32_t INT_THR : 32; /*!< [31..0] Interrupt threshold */ + } INT_THR_REG_b; + }; + + union + { + __IOM uint32_t PULSE_CNT_REG; /*!< (@ 0x0000017C) Pulse Counter register */ + + struct + { + __IM uint32_t PULSE_CNT : 32; /*!< [31..0] counter value at the present */ + } PULSE_CNT_REG_b; + }; +} RTC_Type; /*!< Size = 384 (0x180) */ + +/* =========================================================================================================================== */ +/* ================ SDEMMC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SDEMMC registers (SDEMMC) + */ + +typedef struct /*!< (@ 0x40011000) SDEMMC Structure */ +{ + union + { + __IOM uint32_t SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG; /*!< (@ 0x00000000) SDEMMC_SDMA_SYSTEM_ADDRESS_ARGUMENT2_REG : SDMA_System_Address_ + * rgument2 */ + + struct + { + __IOM uint32_t SDMA_System_Address_Argument2 : 32; /*!< [31..0] This register contains the physical system memoryaddress + * used for DMA transfers or the second argument for the Auto + * CMD23.(1) SDMA System AddressThis register contains the + * system memory address fora SDMA transfer. When the Host + * Controller stops aSDMA transfer, this register shall point + * to the systemaddress of the next contiguous data position. + * It canbe accessed only if no transaction is executing (i.e.,after + * a transaction has stopped). Read operationsduring transfers + * m */ + } SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_BLOCK_REG; /*!< (@ 0x00000004) SDEMMC_BLOCK_REG : BlockSize_BlockCount */ + + struct + { + __IOM uint32_t TransferBlockSize : 12; /*!< [11..0] This register specifies the block size for block datatransfers + * for CMD17, CMD18, CMD24, CMD25, andCMD53. It can be accessed + * only if no transaction isexecuting (i.e after a transaction + * has stopped). Readoperations during transfer return an + * invalid value andwrite operations shall be ignored.0000h + * - No Data Transfer0001h - 1 Byte0002h - 2 Bytes0003h - + * 3 Bytes0004h - 4 Bytes--- ---01FFh - 511 Bytes0200h - 512 + * Bytes--- ---0800h - 2048 Bytes */ + __IOM uint32_t HostSDMABufferBoundry : 3; /*!< [14..12] To perform long DMA transfer, System Address register + * shall be updated at every system boundary during DMA transfer. + * These bits specify the size ofcontiguous buffer in the + * system memory. The DMAtransfer shall wait at the every + * boundary specified bythese fields and the HC generates + * the DMA Interruptto request the HD to update the System + * Address register.These bits shall support when the DMA + * Support inthe Capabilities register is set to 1 and this + * function isactive when the DMA */ + uint32_t : 1; + __IOM uint32_t BlockCountForCurrentTransfer : 16; /*!< [31..16] This register is enabled whenBlock Count Enable in + * the Transfer Mode register is set to 1 andis valid only + * for multiple blocktransfers. The HC decrementsthe block + * count after each blocktransfer and stops when thecount + * reaches zero. It can beaccessed only if no transaction + * isexecuting (i.e. after a transactionhas stopped). Read + * operationsduring transfer return an invalidvalue and write + * operations shallbe ignored.When saving transfer context + * asa resul */ + } SDEMMC_BLOCK_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC__ARGU_1_REG; /*!< (@ 0x00000008) SDEMMC_ARGUMENT1_REG : Argument1 */ + + struct + { + __IOM uint32_t Argument1 : 32; /*!< [31..0] The SD Command Argument isspecified as bit39-8 of Command-Format. */ + } SDEMMC__ARGU_1_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_TRANSFERMODE_COMMAND_REG; /*!< (@ 0x0000000C) SDEMMC_TRANSFERMODE_COMMAND_REG : TransferMode_Command */ + + struct + { + __IOM uint32_t DMAEnable : 1; /*!< [0..0] DMA can be enabled only if DMA Support bit in theCapabilities + * register is set. If this bit is set to 1, a DMAoperation + * shall begin when the HD writes to the upperbyte of Command + * register (00Fh).0 - Disable1 - Enable */ + __IOM uint32_t BlockCountEnable : 1; /*!< [1..1] This bit is used to enable the Block count register, + * whichis only relevant for multiple block transfers. When + * this bitis 0, the Block Count register is disabled, which + * is usefulin executing an infinite transfer.0 - Disable1 + * - Enable */ + __IOM uint32_t AutoCMDEnable : 2; /*!< [3..2] This field determines use of auto command functions00b + * - Auto Command Disabled01b - Auto CMD12 Enable10b - Auto + * CMD23 Enable11b - ReservedThere are two methods to stop + * Multiple-block read andwrite operation.(1) Auto CMD12 EnableMultiple-bloc + * read and write commands for memoryrequire CMD12 to stop + * the operation. When this field isset to 01b, the Host Controller + * issues CMD12 automatically when last block transfer is + * completed. Auto CMD12error is indicated to the */ + __IOM uint32_t DataTransferDirectionSelect : 1; /*!< [4..4] This bit defines the direction of data transfers.0 - + * Write (Host to Card)1 - Read (Card to Host) */ + __IOM uint32_t MultiSingleBlockSelect : 1; /*!< [5..5] This bit enables multiple block data transfers.0 - Single + * Block1 - Multiple Block */ + uint32_t : 10; + __IOM uint32_t ResponseTypeSelect : 2; /*!< [17..16] Response Type Select00 - No Response01 - Response length + * 13610 - Response length 4811 - Response length 48 checkBusy + * after response */ + uint32_t : 1; + __IOM uint32_t CommandCRCCheckEnable : 1; /*!< [19..19] If this bit is set to 1, the HC shallcheck the CRC + * field in theresponse. If an error is detected, itis reported + * as a Command CRCError. If this bit is set to 0, the CRCfield + * is not checked.0 - Disable1 - Enabl */ + __IOM uint32_t CommandIndexCheckEnable : 1; /*!< [20..20] If this bit is set to 1, the HC shallcheck the index + * field in theresponse to see if it has the samevalue as + * the command index. If it isnot, it is reported as a CommandIndex + * Error. If this bit is set to 0, theIndex field is not checked.0 + * - Disable1 - Enable */ + __IOM uint32_t DataPresentSelect : 1; /*!< [21..21] This bit is set to 1 to indicate thatdata is present + * and shall be transferred using the DAT line. If is setto + * 0 for the following:1. Commands using only CMD line(ex. + * CMD52)2. Commands with no data transferbut using busy signal + * on DAT[0]line (R1b or R5b ex. CMD38)3. Resume Command0 + * - No Data Present1 - Data Present */ + uint32_t : 1; + __IOM uint32_t CommandType : 1; /*!< [23..23] There are three types of specialcommands. Suspend, + * Resume andAbort. These bits shall bet set to00b for all + * other commands.Suspend CommandIf the Suspend command succeeds, + * the HC shall assume theSD Bus has been released andthat + * it is possible to issue the nextcommand which uses the + * DAT line.The HC shall de-assert Read Waitfor read transactions + * and stopchecking busy for write transactions. The Interrupt + * cycle shallstart, in 4-bit mode. If the Suspendcomman */ + __IOM uint32_t CommandIndex : 6; /*!< [29..24] This bit shall be set to the command number (CMD0-63, + * ACMD0-63) */ + uint32_t : 2; + } SDEMMC_TRANSFERMODE_COMMAND_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_RESPONSE0_REG; /*!< (@ 0x00000010) SDEMMC_RESPONSE0_REG : Response */ + + struct + { + __IM uint32_t Reponse0 : 32; /*!< [31..0] Reponse0 */ + } SDEMMC_RESPONSE0_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_RESPONSE1_REG; /*!< (@ 0x00000014) SDEMMC_RESPONSE1_REG : Response */ + + struct + { + __IM uint32_t Reponse1 : 32; /*!< [31..0] Reponse1 */ + } SDEMMC_RESPONSE1_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_RESPONSE2_REG; /*!< (@ 0x00000018) SDEMMC_RESPONSE2_REG : Response */ + + struct + { + __IM uint32_t Reponse2 : 32; /*!< [31..0] Reponse2 */ + } SDEMMC_RESPONSE2_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_RESPONSE3_REG; /*!< (@ 0x0000001C) SDEMMC_RESPONSE3_REG : Response */ + + struct + { + __IM uint32_t Reponse3 : 32; /*!< [31..0] Reponse3 */ + } SDEMMC_RESPONSE3_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_BUFFERDATAPORT_REG; /*!< (@ 0x00000020) SDEMMC_BUFFERDATAPORT_REG : BufferDataPort */ + + struct + { + __IOM uint32_t BufferData : 32; /*!< [31..0] BufferData */ + } SDEMMC_BUFFERDATAPORT_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_PRESENTSTATE_REG; /*!< (@ 0x00000024) SDEMMC_PRESENTSTATE_REG : PresentState */ + + struct + { + __IM uint32_t CommandInhibitCMD : 1; /*!< [0..0] CommandInhibitCMD */ + __IM uint32_t CommandInhibitDAT : 1; /*!< [1..1] CommandInhibitDAT */ + __IM uint32_t DATLineActive : 1; /*!< [2..2] DATLineActive */ + __IM uint32_t ReTuningRequest : 1; /*!< [3..3] ReTuningRequest */ + uint32_t : 4; + __IM uint32_t WriteTransferActive : 1; /*!< [8..8] WriteTransferActive */ + __IM uint32_t ReadTransferActive : 1; /*!< [9..9] ReadTransferActive */ + __IM uint32_t BufferWriteEnable : 1; /*!< [10..10] BufferWriteEnable */ + __IM uint32_t BufferReadEnable : 1; /*!< [11..11] BufferReadEnable */ + uint32_t : 4; + __IM uint32_t CardInserted : 1; /*!< [16..16] CardInserted */ + __IM uint32_t CardStateStable : 1; /*!< [17..17] CardStateStable */ + __IM uint32_t CardDetectPinLevel : 1; /*!< [18..18] CardDetectPinLevel */ + __IM uint32_t WriteProtectSwitchPinLevel : 1; /*!< [19..19] WriteProtectSwitchPinLevel */ + __IM uint32_t DAT3TO0LineSignalLevel : 4; /*!< [23..20] DAT3TO0LineSignalLevel */ + __IM uint32_t CMDLineSignalLevel : 1; /*!< [24..24] CMDLineSignalLevel */ + uint32_t : 7; + } SDEMMC_PRESENTSTATE_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_HOST_CTRL_1_REG; /*!< (@ 0x00000028) SDEMMC_HOSTCONTROL1_REG : HostControl1 */ + + struct + { + __IOM uint32_t LEDControl : 1; /*!< [0..0] LEDControl */ + __IOM uint32_t DataTransferWidth : 1; /*!< [1..1] DataTransferWidth */ + __IOM uint32_t HighSpeedEnable : 1; /*!< [2..2] HighSpeedEnable */ + __IOM uint32_t DMASelect : 2; /*!< [4..3] DMASelect */ + __IOM uint32_t ExtendedDataTransferWidth : 1; /*!< [5..5] ExtendedDataTransferWidth */ + __IOM uint32_t CardDetectTestLevel : 1; /*!< [6..6] CardDetectTestLevel */ + __IOM uint32_t CardDetectSignalSelection : 1; /*!< [7..7] CardDetectSignalSelection */ + __IOM uint32_t SDBusPower : 1; /*!< [8..8] SDBusPower */ + __IOM uint32_t SDBusVoltageSelect : 3; /*!< [11..9] SDBusVoltageSelect */ + __IOM uint32_t HardwareRst : 1; /*!< [12..12] HardwareRst */ + uint32_t : 3; + __IOM uint32_t StopAtBlockGapRequest : 1; /*!< [16..16] StopAtBlockGapRequest */ + __IOM uint32_t ContinueRequest : 1; /*!< [17..17] ContinueRequest */ + __IOM uint32_t ReadWaitControl : 1; /*!< [18..18] ReadWaitControl */ + __IOM uint32_t InterruptAtBlockGap : 1; /*!< [19..19] InterruptAtBlockGap */ + __IOM uint32_t SpiMode : 1; /*!< [20..20] SpiMode */ + __IOM uint32_t BootEn : 1; /*!< [21..21] BootEn */ + __IOM uint32_t AltBootEn : 1; /*!< [22..22] AltBootEn */ + __IOM uint32_t BootAckChk : 1; /*!< [23..23] BootAckChk */ + __IOM uint32_t WakeupEventEnableOnCardInterrupt : 1; /*!< [24..24] WakeupEventEnableOnCardInterrupt */ + __IOM uint32_t WakeupEventEnableOnSDCardInsertion : 1; /*!< [25..25] WakeupEventEnableOnSDCardInsertion */ + __IOM uint32_t WakeupEventEnableOnSDCardRemoval : 1; /*!< [26..26] WakeupEventEnableOnSDCardRemoval */ + uint32_t : 5; + } SDEMMC_HOST_CTRL_1_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC__CLK__CTRL__REG; /*!< (@ 0x0000002C) SDEMMC_CLOCKCONTROL_REG : ClockControl */ + + struct + { + __IOM uint32_t InternalClockEnable : 1; /*!< [0..0] InternalClockEnable */ + __IM uint32_t InternalClockStable : 1; /*!< [1..1] InternalClockStable */ + __IOM uint32_t SDClockEnable : 1; /*!< [2..2] SDClockEnable */ + uint32_t : 2; + __IOM uint32_t ClockGeneratorSelect : 1; /*!< [5..5] ClockGeneratorSelect */ + __IOM uint32_t UpperBitsofSDCLKFrequencySelect : 2; /*!< [7..6] UpperBitsofSDCLKFrequencySelect */ + __IOM uint32_t SDCLKFrequencySelect : 8; /*!< [15..8] SDCLKFrequencySelect */ + __IOM uint32_t DataTimeoutCounterValue : 4; /*!< [19..16] DataTimeoutCounterValue */ + uint32_t : 4; + __IOM uint32_t SoftwareResetForAll : 1; /*!< [24..24] SoftwareResetForAll */ + __IOM uint32_t SoftwareResetForCMDLine : 1; /*!< [25..25] SoftwareResetForCMDLine */ + __IOM uint32_t SoftwareResetForDATLine : 1; /*!< [26..26] SoftwareResetForDATLine */ + uint32_t : 5; + } SDEMMC__CLK__CTRL__REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_NORMAL_ITNR_STATUS_REG; /*!< (@ 0x00000030) SDEMMC_NORMALINTERRUPTSTATUS_REG : NormalInterruptStatus */ + + struct + { + __IOM uint32_t CommandComplete : 1; /*!< [0..0] CommandComplete */ + __IOM uint32_t TransferComplete : 1; /*!< [1..1] TransferComplete */ + __IOM uint32_t BlockGapEvent : 1; /*!< [2..2] BlockGapEvent */ + __IOM uint32_t DMAInterrupt : 1; /*!< [3..3] DMAInterrupt */ + __IOM uint32_t BufferWriteReady : 1; /*!< [4..4] BufferWriteReady */ + __IOM uint32_t BufferReadReady : 1; /*!< [5..5] BufferReadReady */ + __IOM uint32_t CardInsertion : 1; /*!< [6..6] CardInsertion */ + __IOM uint32_t CardRemoval : 1; /*!< [7..7] CardRemoval */ + __IM uint32_t CardInterrupt : 1; /*!< [8..8] CardInterrupt */ + __IM uint32_t INT_A : 1; /*!< [9..9] INT_A */ + __IM uint32_t INT_B : 1; /*!< [10..10] INT_B */ + __IM uint32_t INT_C : 1; /*!< [11..11] INT_C */ + __IM uint32_t ReTuningEvent : 1; /*!< [12..12] ReTuningEvent */ + __IM uint32_t BootAckRcv : 1; /*!< [13..13] BootAckRcv */ + __IM uint32_t BootTerminateInterrupt : 1; /*!< [14..14] BootTerminateInterrupt */ + __IM uint32_t ErrorInterrupt : 1; /*!< [15..15] ErrorInterrupt */ + __IOM uint32_t CommandTimeoutError : 1; /*!< [16..16] CommandTimeoutError */ + __IOM uint32_t CommandCRCError : 1; /*!< [17..17] CommandCRCError */ + __IOM uint32_t CommandEndBitError : 1; /*!< [18..18] CommandEndBitError */ + __IOM uint32_t CommandIndexError : 1; /*!< [19..19] CommandIndexError */ + __IOM uint32_t DataTimeoutError : 1; /*!< [20..20] DataTimeoutError */ + __IOM uint32_t DataCRCError : 1; /*!< [21..21] DataCRCError */ + __IOM uint32_t DataEndBitError : 1; /*!< [22..22] DataEndBitError */ + __IOM uint32_t CurrentLimitError : 1; /*!< [23..23] CurrentLimitError */ + __IOM uint32_t AutoCMDError : 1; /*!< [24..24] AutoCMDError */ + __IOM uint32_t ADMAError : 1; /*!< [25..25] ADMAError */ + __IOM uint32_t TuningError : 1; /*!< [26..26] TuningError */ + __IOM uint32_t VendorSpecificError : 5; /*!< [31..27] VendorSpecificError */ + } SDEMMC_NORMAL_ITNR_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_NORMAL_ITNR_STATUS_EN_REG; /*!< (@ 0x00000034) SDEMMC_NORMALINTERRUPTSTATUSENABLE_REG : NormalInterruptStatusE + * able */ + + struct + { + __IOM uint32_t CommandCompleteStatusEnb : 1; /*!< [0..0] CommandCompleteStatusEnb */ + __IOM uint32_t TransferCompleteStatusEnb : 1; /*!< [1..1] TransferCompleteStatusEnb */ + __IOM uint32_t BlockGapEventStatusEnb : 1; /*!< [2..2] BlockGapEventStatusEnb */ + __IOM uint32_t DMAInterruptStatusEnb : 1; /*!< [3..3] DMAInterruptStatusEnb */ + __IOM uint32_t BufferWriteReadyStatusEnb : 1; /*!< [4..4] BufferWriteReadyStatusEnb */ + __IOM uint32_t BufferReadReadyStatusEnb : 1; /*!< [5..5] BufferReadReadyStatusEnb */ + __IOM uint32_t CardInsertionStatusEnb : 1; /*!< [6..6] CardInsertionStatusEnb */ + __IOM uint32_t CardRemovalStatusEnb : 1; /*!< [7..7] CardRemovalStatusEnb */ + __IOM uint32_t CardInterruptStatusEnb : 1; /*!< [8..8] CardInterruptStatusEnb */ + __IOM uint32_t INT_AStatusEnb : 1; /*!< [9..9] INT_AStatusEnb */ + __IOM uint32_t INT_BStatusEnb : 1; /*!< [10..10] INT_BStatusEnb */ + __IOM uint32_t INT_CStatusEnb : 1; /*!< [11..11] INT_CStatusEnb */ + __IOM uint32_t ReTuningEventStatusEnable : 1; /*!< [12..12] ReTuningEventStatusEnable */ + __IOM uint32_t BootAckRcvStatusEnb : 1; /*!< [13..13] BootAckRcvStatusEnb */ + __IOM uint32_t BootTerminateInterruptStatusEnb : 1; /*!< [14..14] BootTerminateInterruptStatusEnb */ + __IM uint32_t FixedTo0 : 1; /*!< [15..15] FixedTo0 */ + __IOM uint32_t CommandTimeoutErrorStatusEnb : 1; /*!< [16..16] CommandTimeoutErrorStatusEnb */ + __IOM uint32_t CommandCRCErrorStatusEnb : 1; /*!< [17..17] CommandCRCErrorStatusEnb */ + __IOM uint32_t CommandEndBitErrorStatusEnb : 1; /*!< [18..18] CommandEndBitErrorStatusEnb */ + __IOM uint32_t CommandIndexErrorStatusEnb : 1; /*!< [19..19] CommandIndexErrorStatusEnb */ + __IOM uint32_t DataTimeoutErrorStatusEnb : 1; /*!< [20..20] DataTimeoutErrorStatusEnb */ + __IOM uint32_t DataCRCErrorStatusEnb : 1; /*!< [21..21] DataCRCErrorStatusEnb */ + __IOM uint32_t DataEndBitErrorStatusEnb : 1; /*!< [22..22] DataEndBitErrorStatusEnb */ + __IOM uint32_t CurrentLimitErrorStatusEnb : 1; /*!< [23..23] CurrentLimitErrorStatusEnb */ + __IOM uint32_t AutoCMDErrorStatusEnb : 1; /*!< [24..24] AutoCMDErrorStatusEnb */ + __IOM uint32_t ADMAErrorStatusEnb : 1; /*!< [25..25] ADMAErrorStatusEnb */ + __IOM uint32_t TuningErrorStatusEnb : 1; /*!< [26..26] TuningErrorStatusEnb */ + __IOM uint32_t VendorSpecificErrorStatusEnb : 5; /*!< [31..27] VendorSpecificErrorStatusEnb */ + } SDEMMC_NORMAL_ITNR_STATUS_EN_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG; /*!< (@ 0x00000038) SDEMMC_NORMALINTERRUPTSIGNALENABLE_REG : NormalInterruptSignalE + * able */ + + struct + { + __IOM uint32_t CommandCompleteSignalEnb : 1; /*!< [0..0] CommandCompleteSignalEnb */ + __IOM uint32_t TransferCompleteSignalEnb : 1; /*!< [1..1] TransferCompleteSignalEnb */ + __IOM uint32_t BlockGapEventSignalEnb : 1; /*!< [2..2] BlockGapEventSignalEnb */ + __IOM uint32_t DMAInterruptSignalEnb : 1; /*!< [3..3] DMAInterruptSignalEnb */ + __IOM uint32_t BufferWriteReadySignalEnb : 1; /*!< [4..4] BufferWriteReadySignalEnb */ + __IOM uint32_t BufferReadReadySignalEnb : 1; /*!< [5..5] BufferReadReadySignalEnb */ + __IOM uint32_t CardInsertionSignalEnb : 1; /*!< [6..6] CardInsertionSignalEnb */ + __IOM uint32_t CardRemovalSignalEnb : 1; /*!< [7..7] CardRemovalSignalEnb */ + __IOM uint32_t CardInterruptSignalEnb : 1; /*!< [8..8] CardInterruptSignalEnb */ + __IOM uint32_t INT_ASignalEnb : 1; /*!< [9..9] INT_ASignalEnb */ + __IOM uint32_t INT_BSignalEnb : 1; /*!< [10..10] INT_BSignalEnb */ + __IOM uint32_t INT_CSignalEnb : 1; /*!< [11..11] INT_CSignalEnb */ + __IOM uint32_t ReTuningEventSignalEnable : 1; /*!< [12..12] ReTuningEventSignalEnable */ + __IOM uint32_t BootAckRcvSignalEnable : 1; /*!< [13..13] BootAckRcvSignalEnable */ + __IOM uint32_t BootTerminateInterruptSignalEnable : 1; /*!< [14..14] BootTerminateInterruptSignalEnable */ + __IM uint32_t FixedTo0 : 1; /*!< [15..15] FixedTo0 */ + __IOM uint32_t CommandTimeoutErrorSignalEnb : 1; /*!< [16..16] CommandTimeoutErrorSignalEnb */ + __IOM uint32_t CommandCRCErrorSignalEnb : 1; /*!< [17..17] CommandCRCErrorSignalEnb */ + __IOM uint32_t CommandEndBitErrorSignalEnb : 1; /*!< [18..18] CommandEndBitErrorSignalEnb */ + __IOM uint32_t CommandIndexErrorSignalEnb : 1; /*!< [19..19] CommandIndexErrorSignalEnb */ + __IOM uint32_t DataTimeoutErrorSignalEnb : 1; /*!< [20..20] DataTimeoutErrorSignalEnb */ + __IOM uint32_t DataCRCErrorSignalEnb : 1; /*!< [21..21] DataCRCErrorSignalEnb */ + __IOM uint32_t DataEndBitErrorSignalEnb : 1; /*!< [22..22] DataEndBitErrorSignalEnb */ + __IOM uint32_t CurrentLimitErrorSignalEnb : 1; /*!< [23..23] CurrentLimitErrorSignalEnb */ + __IOM uint32_t AutoCMDErrorSignalEnb : 1; /*!< [24..24] AutoCMDErrorSignalEnb */ + __IOM uint32_t ADMAErrorSignalEnb : 1; /*!< [25..25] ADMAErrorSignalEnb */ + __IOM uint32_t TuningErrorSignalEnb : 1; /*!< [26..26] TuningErrorSignalEnb */ + __IOM uint32_t VendorSpecificErrorSignalEnb : 5; /*!< [31..27] VendorSpecificErrorSignalEnb */ + } SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_AUTOCMDERRORSTATUS_REG; /*!< (@ 0x0000003C) SDEMMC_AUTOCMDERRORSTATUS_REG : AutoCMDErrorStatus */ + + struct + { + __IM uint32_t AutoCMD12NotExecuted : 1; /*!< [0..0] AutoCMD12NotExecuted */ + __IM uint32_t AutoCMDTimeoutError : 1; /*!< [1..1] AutoCMDTimeoutError */ + __IM uint32_t AutoCMDCRCError : 1; /*!< [2..2] AutoCMDCRCError */ + __IM uint32_t AutoCMDEndBitError : 1; /*!< [3..3] AutoCMDEndBitError */ + __IM uint32_t AutoCMDIndexError : 1; /*!< [4..4] AutoCMDIndexError */ + uint32_t : 2; + __IM uint32_t CommandNotIssuedByAutoCMD12Error : 1; /*!< [7..7] CommandNotIssuedByAutoCMD12Error */ + uint32_t : 8; + __IOM uint32_t UHSModeSelect : 3; /*!< [18..16] UHSModeSelect */ + __IOM uint32_t SignalingEnable1_8V : 1; /*!< [19..19] SignalingEnable1_8V */ + __IOM uint32_t DriveStrengthSelect : 2; /*!< [21..20] DriveStrengthSelect */ + __IOM uint32_t ExecuteTuning : 1; /*!< [22..22] ExecuteTuning */ + __IOM uint32_t SamplingClockSelect : 1; /*!< [23..23] SamplingClockSelect */ + uint32_t : 6; + __IOM uint32_t AsynchronousInterruptEnable : 1; /*!< [30..30] AsynchronousInterruptEnable */ + __IOM uint32_t PresetValueEnable : 1; /*!< [31..31] PresetValueEnable */ + } SDEMMC_AUTOCMDERRORSTATUS_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_CAPABILITIES0_REG; /*!< (@ 0x00000040) SDEMMC_CAPABILITIES0_REG : Capabilities0 */ + + struct + { + __IM uint32_t TimeoutClockFrequency : 6; /*!< [5..0] TimeoutClockFrequency */ + uint32_t : 1; + __IM uint32_t TimeoutClockUnit : 1; /*!< [7..7] TimeoutClockUnit */ + __IM uint32_t BaseClockFrequencyForSDClock : 8; /*!< [15..8] BaseClockFrequencyForSDClock */ + __IM uint32_t MaxBlockLength : 2; /*!< [17..16] MaxBlockLength */ + __IM uint32_t SupportforEmbeddedDevice8bit : 1; /*!< [18..18] SupportforEmbeddedDevice8bit */ + __IM uint32_t ADMA2Support : 1; /*!< [19..19] ADMA2Support */ + uint32_t : 1; + __IM uint32_t HighSpeedSupport : 1; /*!< [21..21] HighSpeedSupport */ + __IM uint32_t SDMASupport : 1; /*!< [22..22] SDMASupport */ + __IM uint32_t SuspendResumeSupport : 1; /*!< [23..23] SuspendResumeSupport */ + __IM uint32_t VoltageSupport33V : 1; /*!< [24..24] VoltageSupport33V */ + __IM uint32_t VoltageSupport30V : 1; /*!< [25..25] VoltageSupport30V */ + __IM uint32_t VoltageSupport18V : 1; /*!< [26..26] VoltageSupport18V */ + uint32_t : 1; + __IM uint32_t SystemBusSupport64bit : 1; /*!< [28..28] SystemBusSupport64bit */ + __IM uint32_t AsynchronousInterruptSupport : 1; /*!< [29..29] AsynchronousInterruptSupport */ + __IM uint32_t SlotType : 2; /*!< [31..30] SlotType */ + } SDEMMC_CAPABILITIES0_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_CAPABILITIES1_REG; /*!< (@ 0x00000044) SDEMMC_CAPABILITIES1_REG : Capabilities1 */ + + struct + { + __IM uint32_t SDR50Support : 1; /*!< [0..0] SDR50Support */ + __IM uint32_t SDR104Support : 1; /*!< [1..1] SDR104Support */ + __IM uint32_t DDR50Support : 1; /*!< [2..2] DDR50Support */ + uint32_t : 1; + __IM uint32_t DriverTypeASupport : 1; /*!< [4..4] DriverTypeASupport */ + __IM uint32_t DriverTypeCSupport : 1; /*!< [5..5] DriverTypeCSupport */ + __IM uint32_t DriverTypeDSupport : 1; /*!< [6..6] DriverTypeDSupport */ + uint32_t : 1; + __IM uint32_t TimerCountforReTuning : 4; /*!< [11..8] TimerCountforReTuning */ + uint32_t : 1; + __IM uint32_t UseTuningforSDR50 : 1; /*!< [13..13] UseTuningforSDR50 */ + __IM uint32_t ReTuningModes : 2; /*!< [15..14] ReTuningModes */ + __IM uint32_t ClockMultiplier : 8; /*!< [23..16] ClockMultiplier */ + uint32_t : 8; + } SDEMMC_CAPABILITIES1_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_MAX_CUR_CAPABILITIES_REG; /*!< (@ 0x00000048) SDEMMC_MAXIMUMCURRENTCAPABILITIES_REG : MaximumCurrentCapabilit + * es */ + + struct + { + __IM uint32_t MaximumCurrentFor3_3V : 8; /*!< [7..0] MaximumCurrentFor3_3V */ + __IM uint32_t MaximumCurrentFor3_0V : 8; /*!< [15..8] MaximumCurrentFor3_0V */ + __IM uint32_t MaximumCurrentFor1_8V : 8; /*!< [23..16] MaximumCurrentFor1_8V */ + uint32_t : 8; + } SDEMMC_MAX_CUR_CAPABILITIES_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SDEMMC_FORCE_EVENET_ERRSTAT_REG; /*!< (@ 0x00000050) SDEMMC_FORCEEVENTFORAUTOCMDERRORSTATUS_REG : + * ForceEventforAutoCMDErrorStatus */ + + struct + { + __OM uint32_t ForceEventForAutoCMD12NotExec : 1; /*!< [0..0] ForceEventForAutoCMD12NotExec */ + __OM uint32_t ForceEventForAutoCMDTimeout : 1; /*!< [1..1] ForceEventForAutoCMDTimeout */ + __OM uint32_t ForceEventForAutoCMDCRC : 1; /*!< [2..2] ForceEventForAutoCMDCRC */ + __OM uint32_t ForceEventForAutoCMDEndBit : 1; /*!< [3..3] ForceEventForAutoCMDEndBit */ + __OM uint32_t ForceEventForAutoCMDIndex : 1; /*!< [4..4] ForceEventForAutoCMDIndex */ + uint32_t : 2; + __OM uint32_t ForceEventForCommandNotIssuedByAutoCMD12Error : 1; /*!< [7..7] ForceEventForCommandNotIssuedByAutoCMD12Error */ + uint32_t : 8; + __OM uint32_t ForceEventForCommandTimeoutError : 1; /*!< [16..16] ForceEventForCommandTimeoutError */ + __OM uint32_t ForceEventForCommandCRCError : 1; /*!< [17..17] ForceEventForCommandCRCError */ + __OM uint32_t ForceEventForCommandEndBitError : 1; /*!< [18..18] ForceEventForCommandEndBitError */ + __OM uint32_t ForceEventForCommandIndexError : 1; /*!< [19..19] ForceEventForCommandIndexError */ + __OM uint32_t ForceEventForDataTimeoutError : 1; /*!< [20..20] ForceEventForDataTimeoutError */ + __OM uint32_t ForceEventForDataCRCError : 1; /*!< [21..21] ForceEventForDataCRCError */ + __OM uint32_t ForceEventForDataEndBitError : 1; /*!< [22..22] ForceEventForDataEndBitError */ + __OM uint32_t ForceEventForCurrentLimitError : 1; /*!< [23..23] ForceEventForCurrentLimitError */ + __OM uint32_t ForceEventForAutoCMDError : 1; /*!< [24..24] ForceEventForAutoCMDError */ + __OM uint32_t ForceEventForADMAError : 1; /*!< [25..25] ForceEventForADMAError */ + __OM uint32_t ForceEventForVendorSpecificError : 6; /*!< [31..26] ForceEventForVendorSpecificError */ + } SDEMMC_FORCE_EVENET_ERRSTAT_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_ADMAERRORSTATUS_REG; /*!< (@ 0x00000054) SDEMMC_ADMAERRORSTATUS_REG : ADMAErrorStatus */ + + struct + { + __IM uint32_t ADMAErrorState : 2; /*!< [1..0] ADMAErrorState */ + __IM uint32_t LengthMismatchError : 1; /*!< [2..2] LengthMismatchError */ + uint32_t : 29; + } SDEMMC_ADMAERRORSTATUS_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_ADMA_SYS_ADDR_LOW_REG; /*!< (@ 0x00000058) SDEMMC_ADMASYSTEMADDRESSLOWBITS_REG : ADMASystemAddressLowbits */ + + struct + { + __IOM uint32_t ADMASystemAddress : 32; /*!< [31..0] ADMASystemAddress */ + } SDEMMC_ADMA_SYS_ADDR_LOW_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_ADMA_SYS_ADDR_UPPER_REG; /*!< (@ 0x0000005C) SDEMMC_ADMASYSTEMADDRESSUPPERBITS_REG : ADMASystemAddressUpperb + * ts */ + + struct + { + __IOM uint32_t ADMASystemAddressUpperbits : 32; /*!< [31..0] ADMASystemAddressUpperbits */ + } SDEMMC_ADMA_SYS_ADDR_UPPER_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_PRESETVALUE0_REG; /*!< (@ 0x00000060) SDEMMC_PRESETVALUE0_REG : PresetValueInit_DefSpeed */ + + struct + { + __IM uint32_t InitSDCLKFrequenceSelectValue : 10; /*!< [9..0] InitSDCLKFrequenceSelectValue */ + __IM uint32_t InitClockGeneratorSelectValue : 1; /*!< [10..10] InitClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t InitDriveStrengthSelectValue : 2; /*!< [15..14] InitDriveStrengthSelectValue */ + __IM uint32_t DefSpdSDCLKFrequenceSelectValue : 10; /*!< [25..16] DefSpdSDCLKFrequenceSelectValue */ + __IM uint32_t DefSpdClockGeneratorSelectValue : 1; /*!< [26..26] DefSpdClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t DefSpdDriveStrengthSelectValue : 2; /*!< [31..30] DefSpdDriveStrengthSelectValue */ + } SDEMMC_PRESETVALUE0_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_PRESETVALUE1_REG; /*!< (@ 0x00000064) SDEMMC_PRESETVALUE1_REG : PresetValueHighSpd_SDR12 */ + + struct + { + __IM uint32_t HighSpdSDCLKFrequenceSelectValue : 10; /*!< [9..0] HighSpdSDCLKFrequenceSelectValue */ + __IM uint32_t HighSpdClockGeneratorSelectValue : 1; /*!< [10..10] HighSpdClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t HighSpdDriveStrengthSelectValue : 2; /*!< [15..14] HighSpdDriveStrengthSelectValue */ + __IM uint32_t SDR12SDCLKFrequenceSelectValue : 10; /*!< [25..16] SDR12SDCLKFrequenceSelectValue */ + __IM uint32_t SDR12ClockGeneratorSelectValue : 1; /*!< [26..26] SDR12ClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t SDR12DriveStrengthSelectValue : 2; /*!< [31..30] SDR12DriveStrengthSelectValue */ + } SDEMMC_PRESETVALUE1_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_PRESETVALUE2_REG; /*!< (@ 0x00000068) SDEMMC_PRESETVALUE2_REG : PresetValueSDR25_SDR50 */ + + struct + { + __IM uint32_t SDR25SDCLKFrequenceSelectValue : 10; /*!< [9..0] SDR25SDCLKFrequenceSelectValue */ + __IM uint32_t SDR25ClockGeneratorSelectValue : 1; /*!< [10..10] SDR25ClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t SDR25DriveStrengthSelectValue : 2; /*!< [15..14] SDR25DriveStrengthSelectValue */ + __IM uint32_t SDR50SDCLKFrequenceSelectValue : 10; /*!< [25..16] SDR50SDCLKFrequenceSelectValue */ + __IM uint32_t SDR50ClockGeneratorSelectValue : 1; /*!< [26..26] SDR50ClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t SDR50DriveStrengthSelectValue : 2; /*!< [31..30] SDR50DriveStrengthSelectValue */ + } SDEMMC_PRESETVALUE2_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_PRESETVALUE3_REG; /*!< (@ 0x0000006C) SDEMMC_PRESETVALUE3_REG : PresetValueSDR104_DDR50 */ + + struct + { + __IM uint32_t SDR104SDCLKFrequenceSelectValue : 10; /*!< [9..0] SDR104SDCLKFrequenceSelectValue */ + __IM uint32_t SDR104ClockGeneratorSelectValue : 1; /*!< [10..10] SDR104ClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t SDR104DriveStrengthSelectValue : 2; /*!< [15..14] SDR104DriveStrengthSelectValue */ + __IM uint32_t DDR50SDCLKFrequenceSelectValue : 10; /*!< [25..16] DDR50SDCLKFrequenceSelectValue */ + __IM uint32_t DDR50ClockGeneratorSelectValue : 1; /*!< [26..26] DDR50ClockGeneratorSelectValue */ + uint32_t : 3; + __IM uint32_t DDR50DriveStrengthSelectValue : 2; /*!< [31..30] DDR50DriveStrengthSelectValue */ + } SDEMMC_PRESETVALUE3_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_BOOTTIMEOUT_CTRL__REG; /*!< (@ 0x00000070) SDEMMC_BOOTTIMEOUTCONTROL_REG : BootTimeoutControl */ + + struct + { + __IOM uint32_t BootDataTimeoutCounterValue : 32; /*!< [31..0] BootDataTimeoutCounterValue */ + } SDEMMC_BOOTTIMEOUT_CTRL__REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_DEBUGSELECTION_REG; /*!< (@ 0x00000074) SDEMMC_DEBUGSELECTION_REG : DebugSelection */ + + struct + { + __IOM uint32_t DebugSel : 1; /*!< [0..0] DebugSel */ + uint32_t : 31; + } SDEMMC_DEBUGSELECTION_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_VENDOR_REG; /*!< (@ 0x00000078) SDEMMC_VENDOR_REG : Vendor */ + + struct + { + __IOM uint32_t AutoGateSDCLK : 1; /*!< [0..0] AutoGateSDCLK */ + __IOM uint32_t Delay_cmdin_datin_dis : 1; /*!< [1..1] Delay_cmdin_datin_dis */ + uint32_t : 30; + } SDEMMC_VENDOR_REG_b; + }; + __IM uint32_t RESERVED1[25]; + + union + { + __IOM uint32_t SDEMMC_SHAREDBUS_CTRL__REG; /*!< (@ 0x000000E0) SDEMMC_SHAREDBUSCONTROL_REG : SharedBusControl */ + + struct + { + __IM uint32_t NumberOfClockPins : 3; /*!< [2..0] NumberOfClockPins */ + uint32_t : 1; + __IM uint32_t NumberOfInterruptInputPins : 2; /*!< [5..4] NumberOfInterruptInputPins */ + uint32_t : 2; + __IM uint32_t BusWidthPreset : 7; /*!< [14..8] BusWidthPreset */ + uint32_t : 1; + __IOM uint32_t ClockPinSelect : 3; /*!< [18..16] ClockPinSelect */ + uint32_t : 1; + __IOM uint32_t InterruptPinSelect : 3; /*!< [22..20] InterruptPinSelect */ + uint32_t : 1; + __IOM uint32_t BackEndPowerControl : 7; /*!< [30..24] BackEndPowerControl */ + uint32_t : 1; + } SDEMMC_SHAREDBUS_CTRL__REG_b; + }; + __IM uint32_t RESERVED2[6]; + + union + { + __IOM uint32_t SDEMMC_SLOT_ITNR_STATUS_REG; /*!< (@ 0x000000FC) SDEMMC_SLOTINTERRUPTSTATUS_REG : SlotInterruptStatus */ + + struct + { + __IM uint32_t InterruptSignalForEachSlot : 8; /*!< [7..0] InterruptSignalForEachSlot */ + __IM uint32_t VendorVersionNumber : 8; /*!< [15..8] VendorVersionNumber */ + __IM uint32_t SpecificationVersionNumber : 8; /*!< [23..16] SpecificationVersionNumber */ + uint32_t : 8; + } SDEMMC_SLOT_ITNR_STATUS_REG_b; + }; + __IM uint32_t RESERVED3[192]; + + union + { + __IOM uint32_t SDEMMC_GLB_ITNR_STATUS_REG; /*!< (@ 0x00000400) SDEMMC_GLOBALINTERRUPTSTATUS_REG : GlobalInterruptStatus */ + + struct + { + uint32_t : 1; + __IOM uint32_t IntSrcXD : 1; /*!< [1..1] IntSrcXD */ + __IOM uint32_t IntSrcSD : 1; /*!< [2..2] IntSrcSD */ + uint32_t : 29; + } SDEMMC_GLB_ITNR_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_GLB_ITNR_STATUS_EN_REG; /*!< (@ 0x00000404) SDEMMC_GLOBALINTERRUPTSTATUSENABLE_REG : GlobalInterruptStatusE + * able */ + + struct + { + uint32_t : 1; + __IOM uint32_t IntSrcXD : 1; /*!< [1..1] IntSrcXD */ + __IOM uint32_t IntSrcSD : 1; /*!< [2..2] IntSrcSD */ + uint32_t : 29; + } SDEMMC_GLB_ITNR_STATUS_EN_REG_b; + }; + + union + { + __IOM uint32_t SDEMMC_GLB_ITNR_SIGNAL_EN_REG; /*!< (@ 0x00000408) SDEMMC_GLOBALINTERRUPTSIGNALENABLE_REG : GlobalInterruptSignalE + * able */ + + struct + { + uint32_t : 1; + __IOM uint32_t IntSrcXD : 1; /*!< [1..1] IntSrcXD */ + __IOM uint32_t IntSrcSD : 1; /*!< [2..2] IntSrcSD */ + uint32_t : 29; + } SDEMMC_GLB_ITNR_SIGNAL_EN_REG_b; + }; +} SDEMMC_Type; /*!< Size = 1036 (0x40c) */ + +/* =========================================================================================================================== */ +/* ================ SDIO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SDIO registers (SDIO) + */ + +typedef struct /*!< (@ 0x40010000) SDIO Structure */ +{ + union + { + __IOM uint32_t SDIO_CLOCK_WAKEUP_REG; /*!< (@ 0x00000000) Clock Wakeup */ + + struct + { + __IOM uint32_t AUTO_CLK_ENABLE : 1; /*!< [0..0] When this bit is programmed to 1, SDIO_AHB Controllercontrols + * the ahb_clk_wkup signal depending on the datatransfer activity + * on the bus automatically. */ + __IOM uint32_t MANUAL_CLK_ENABLE : 1; /*!< [1..1] 1 - The ahb_clk_wkup signal is always high indicating + * tothe ARM for keeping the clock active. This is used to + * allowmanual mode from SD Host. */ + uint32_t : 30; + } SDIO_CLOCK_WAKEUP_REG_b; + }; + + union + { + __IOM uint32_t SDIO_CCCR_REG; /*!< (@ 0x00000004) CCCR */ + + struct + { + __IOM uint32_t CCCR_REVISION : 4; /*!< [3..0] CCCR Format Version number.These 4-bits contains the + * version of the CCCR and FBR format that this card supports.00h + * CCCR/FBR Version 1.00 CCCR/FBR01h Version 1.1002h CCCR/FBR + * Version 2.00 CCCR/FBR03h Version 3.0004h-0Fh Reserved for + * Future Use. */ + __IOM uint32_t SDIO_REVISION : 4; /*!< [7..4] SDIO Specification Revision number.These 4-bits contain + * the version of the SDIO specification that this card supports.00h + * SDIO Specification Version 1.0001h SDIO Specification Version + * 1.1002h SDIO Specification Version 1.20 (Unreleased)03h + * SDIO Specification Version2.0004h SDIO Specification Version3.0005h-0Fh + * Reserved for Future Use. */ + __IOM uint32_t SD_REVISION : 4; /*!< [11..8] SD Format Revision.These 4-bits contain the version + * of the SD Physical specification that this card supports.00h + * SD Physical Specification 1.0101h SD Specification 1.10 + * Physical02h SD Physical Specification 2.0003h SD Physical + * Specification 3.0004h-0Fh Reserved for Future Use. */ + __IOM uint32_t SCSI : 1; /*!< [12..12] Support Continuous SPI interrupt. */ + __IOM uint32_t SDC : 1; /*!< [13..13] This flag bit reports the card?s ability to execute + * CMD52 while data transfer is in progress. */ + __IOM uint32_t SMB : 1; /*!< [14..14] This flag bit reports the card's ability to execute + * CMD53 in Block Mode. */ + __IOM uint32_t SRW : 1; /*!< [15..15] This flag bit reports the card's ability to Support + * the Read Wait Control (RWC) operation. */ + __IM uint32_t SBS : 1; /*!< [16..16] This flag bit reports the card's ability to Support + * the Suspend/Resume operations at the request of the Host.If + * this bit is set all functions except 0 will accept a request + * to suspend operations and esume under host control. */ + __IOM uint32_t S4MI : 1; /*!< [17..17] This flag reports the SDIO card's ability to generate + * interrupts during a 4-bit multi block data transfer. */ + __IOM uint32_t LSC : 1; /*!< [18..18] If this bit is set, it indicates that the SDIO card + * is a low speed device. If this bit is cleared the SDIO + * card is a full speed device. */ + __IOM uint32_t FOURBLS : 1; /*!< [19..19] This bit denotes that the SDIO card is a low speed + * card and supports 4-bit data transfer. */ + __IOM uint32_t SMPC : 1; /*!< [20..20] This bit tells the host if the card supports master + * power control.SMPC = 0. The total card current is less + * than 200mA, even if all functions areactive(IOEx = 1) EMPC,SPS + * and EPS shall be zero.SMPC = 1. The total card current + * may exeed 200mA. EMPC,SPS and EPS are available */ + __IOM uint32_t SHS : 1; /*!< [21..21] Support high speed - This flag bit reports thecard?s + * ability to operate in high speed mode. */ + __IM uint32_t CMD_INDEX : 6; /*!< [27..22] These 6 bit register contains the commandindex value + * for the command?s issued on the sd side. */ + uint32_t : 4; + } SDIO_CCCR_REG_b; + }; + + union + { + __IOM uint32_t SDIO_ADMA_SYSTEM_ADDRESS_REG; /*!< (@ 0x00000008) This register holds descriptor Pointer of the + * Descriptor table.At the start of ADMA ARM + * shall program start address of the Descriptor + * table. */ + + struct + { + uint32_t : 28; + __IOM uint32_t ADMA_SYSTEM_ADDRESS : 4; /*!< [31..28] This register holds descriptor Pointer of the Descriptor + * table.At the start of ADMA ARM shall program start address + * of the Descriptor table. */ + } SDIO_ADMA_SYSTEM_ADDRESS_REG_b; + }; + + union + { + __IOM uint32_t SDIO_CARDRDY_REG; /*!< (@ 0x0000000C) Card Ready */ + + struct + { + __IM uint32_t CARD_RDY : 1; /*!< [0..0] Card ready bit indicates Power on reset is synchronously + * deasserted on SD clock domain.This bit is set to 1 after + * power on reset indicating that the SDIO_AHB Controller + * is ready to program. */ + uint32_t : 31; + } SDIO_CARDRDY_REG_b; + }; + + union + { + __IOM uint32_t SDIO_FUNRDY_REG; /*!< (@ 0x00000010) Function Ready */ + + struct + { + __IOM uint32_t CARD_RDY : 1; /*!< [0..0] ARM Processor set this bit to indicate function is ready + * to operate. */ + uint32_t : 31; + } SDIO_FUNRDY_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_FN0_INT_ENABLE_REG; /*!< (@ 0x00000014) Function 0 interrupt enable */ + + struct + { + __IOM uint32_t AHBSOFT_RST_EN : 1; /*!< [0..0] Interrupt enable for cmd52 soft reset interrupt. */ + __IOM uint32_t VOLT_SWITCH_CMD_EN : 1; /*!< [1..1] 1 - volt switch cmd interrupt is enabled0 - volt switch + * cmd interrupt is disabled */ + __IOM uint32_t CMD19_RD_STRT_EN : 1; /*!< [2..2] 1 - cmd19 rd start interrupt is enabled0 - cmd19 rd start + * interrupt is disabled */ + __IOM uint32_t CMD19_RD_TRN_OVR_EN : 1; /*!< [3..3] 1 - cmd19 rd trans over interrupt is enabled0 - cmd19 + * rd trans over interrupt is disabled */ + __IOM uint32_t FN0_WR_STRT_EN : 1; /*!< [4..4] 1 - fn0 write start interrupt is enabled0 - fn0 write + * start interrupt is disabled */ + __IOM uint32_t FN0_WR_TRN_OVR_EN : 1; /*!< [5..5] 1 - fn0 write trn over interrupt is enabled0 - fn0 write + * trn over interrupt is disabled */ + __IOM uint32_t FN0_RD_STRT_EN : 1; /*!< [6..6] 1 - fn0 read start interrupt is enabled0 - fn0 read start + * interrupt is disabled */ + __IOM uint32_t FN0_RD_OVR_EN : 1; /*!< [7..7] 1 - fn0 read trn over interrupt is enabled0 - fn0 read + * trn over interrupt is disabled */ + __IOM uint32_t FN0_RD_ERR_EN : 1; /*!< [8..8] 1 - fn0 read trn err interrupt is enabled0 - fn0 read + * trn err interrupt is disabled */ + __IOM uint32_t FN0_ADMA_END_EN : 1; /*!< [9..9] 1 - fn0_adma_end_bit interrupt is enabled0 - fn0_adma_end_bit + * interrupt is disabled */ + __IOM uint32_t FN0_ADMA_INT_EN : 1; /*!< [10..10] 1 - fn0_adma_int interrupt is enabled0 - fn0_adma_int + * interrupt is disabled */ + __IOM uint32_t FN0_ADMA_ERR_EN : 1; /*!< [11..11] 1 - fn0_adma_err interrupt is enabled0 - fn0_adma_err + * interrupt is disabled */ + uint32_t : 20; + } SDIO_AHB_FN0_INT_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_FN0_INT_REG; /*!< (@ 0x00000018) Function 0 interrupt */ + + struct + { + __IOM uint32_t AHBSOFT_RST : 1; /*!< [0..0] This soft reset interrupt will be asserted to ARM when + * host issues cmd52 soft reset for SDIO controller. */ + __IOM uint32_t VOLT_SWITCH_CMD : 1; /*!< [1..1] This bit is set by Arasan SDIO_AHB bridge when SD Host + * issues cmd11. */ + __IOM uint32_t CMD19_RD_STRT : 1; /*!< [2..2] This bit is set when SD Host issues cmd19. */ + __IOM uint32_t CMD19_RD_TRN_OVR : 1; /*!< [3..3] This bit is set when cmd19 read transaction is over. */ + __IOM uint32_t FN0_WR_STRT : 1; /*!< [4..4] This bit is set when the SD Host issues CMD53 Fun0 write + * command (For ARM side transaction).This bit is set by SDIO + * AHB bridge */ + __IOM uint32_t FN0_WR_TRN_OVR : 1; /*!< [5..5] This interrupt corresponds to the interrupt issued by + * SD DMA after it completes the write operation of a Function0 + * ARM side transaction.Until this bit is cleared, busy signal + * will be asserted in dat0 line, the SD DMA engine is prevented + * from performing an AHB write access from a new cmd53 write/read.No + * valid data in the fifo is overwritten. */ + __IOM uint32_t FN0_RD_STRT : 1; /*!< [6..6] This bit is set when the SD Host issues CMD53 Fun0 read + * command(ARM side transaction).This bit is set by SDIO AHB + * bridge */ + __IOM uint32_t FN0_RD_OVR : 1; /*!< [7..7] This interrupt corresponds to the interrupt issued by + * SD DMA after it completes the read operation of a Function0. */ + __IOM uint32_t FN0_RD_ERR : 1; /*!< [8..8] This interrupt is issued if SD Host issue abort command + * during function 0 read transaction. */ + __IOM uint32_t FN0_ADMA_END : 1; /*!< [9..9] This bit is set when the adma endbit is set during descriptor + * fetch indicate end of fetch.Then ARM processor ready for + * next fetch (with new updated address) */ + __IOM uint32_t FN0_ADMA_INT : 1; /*!< [10..10] This bit is set by Arasan SDIO_AHB bridge when int + * bit is set in the attribute field during fetch operation. */ + __IOM uint32_t FN0_ADMA_ERR : 1; /*!< [11..11] This bit is set by Arasan SDIO_AHB bridge when ARM + * sets valid bit as 0 in the attribute field during fetch + * operation. */ + uint32_t : 20; + } SDIO_AHB_FN0_INT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_SOFT_RST_AHB_REG; /*!< (@ 0x0000001C) Soft Reset */ + + struct + { + __IOM uint32_t AHBSOFT_VALID : 1; /*!< [0..0] When ARM receives cmd52_rst interrupt it clears the interrupt + * and set this bit to 1.After that the controller asserts + * rstsoft_ahb_n for 1 AHB clk and clear the AHB domain flops. */ + uint32_t : 31; + } SDIO_SOFT_RST_AHB_REG_b; + }; + + union + { + __IOM uint32_t SDIO_GLB_INT_ENA_REG; /*!< (@ 0x00000020) Global Interrupt Enable */ + + struct + { + __IOM uint32_t FN0_INT_TO_ARM_EN : 1; /*!< [0..0] 1 - Interrupt asserted from AHB fn0 interrupt Register + * enabled.0 - Interrupt asserted from AHB fn0 interrupt Register + * masked. */ + __IOM uint32_t FN1_INT_TO_ARM_EN : 1; /*!< [1..1] 1 - Interrupt asserted from AHB fn1 interrupt Register + * enabled.0 - Interrupt asserted from AHB fn1 interrupt Register + * masked. */ + uint32_t : 30; + } SDIO_GLB_INT_ENA_REG_b; + }; + + union + { + __IOM uint32_t SDIO_GLB_INT_STS_REG; /*!< (@ 0x00000024) Global Interrupt Enable */ + + struct + { + __IOM uint32_t FN0_INT_TO_ARM : 1; /*!< [0..0] Interrupt asserted from AHB fn0 interrupt Register */ + __IOM uint32_t FN1_INT_TO_ARM : 1; /*!< [1..1] Interrupt asserted from AHB fn1 interrupt Register */ + uint32_t : 30; + } SDIO_GLB_INT_STS_REG_b; + }; + + union + { + __IOM uint32_t SDIO_CSA_POINTER_REG; /*!< (@ 0x00000028) CSA pointer */ + + struct + { + __IM uint32_t CSA_POINTER : 24; /*!< [23..0] CSA pointer updated by SD Host. */ + uint32_t : 8; + } SDIO_CSA_POINTER_REG_b; + }; + + union + { + __IOM uint32_t SDIO_IO_ACC_MODE_REG; /*!< (@ 0x0000002C) IO access mode */ + + struct + { + __IOM uint32_t SSDR50 : 1; /*!< [0..0] This bit indicates support of SDR50.Support bit of SDR500b: + * SDR50 is not supported1b: SDR50 is supported */ + __IOM uint32_t SSDR104 : 1; /*!< [1..1] This bit indicates support of SDR104.Support bit of SDR1040b: + * SDR104 is not supported1b: SDR104 is supported */ + __IOM uint32_t SDDR50 : 1; /*!< [2..2] This bit indicates support of DDR50.Support bit of DDR500b: + * DDR50 is not supported1b: DDR50 is supported */ + __IOM uint32_t SDTA : 1; /*!< [3..3] This bit indicates support of Driver Type A.Support bit + * of SDR500b: Driver Type A is not supported1b: Driver Type + * A is supported */ + __IOM uint32_t SDTC : 1; /*!< [4..4] This bit indicates support of Driver Type C.Support bit + * of SDR500b: Driver Type C is not 1b: Drive1b: Driver Type + * C is supported */ + __IOM uint32_t SDTD : 1; /*!< [5..5] This bit indicates support of Driver Type D.Support bit + * of SDR500b: Driver Type D is not supported1b: Driver Type + * D is supported */ + __IOM uint32_t SAI : 1; /*!< [6..6] Support bit of Asynchronous Interrupt.If the card supports + * asynchronous interrupt in SD 4-bit mode (interrupt can + * be asserted without SD clock during specified period), + * this bit is set to 1. */ + uint32_t : 25; + } SDIO_IO_ACC_MODE_REG_b; + }; + + union + { + __IOM uint32_t SDIO_LAST_FETCH_ADDR_REG; /*!< (@ 0x00000030) This register holds descriptor Pointer of the + * Descriptor table.At the start of ADMA ARM + * shall program start address of the Descriptor + * table. */ + + struct + { + __IM uint32_t LAST_FETCH_ADDR : 32; /*!< [31..0] This register holds descriptor Pointer of the Descriptor + * table.At the start of ADMA ARM shall program start address + * of the Descriptor table. */ + } SDIO_LAST_FETCH_ADDR_REG_b; + }; + + union + { + __IOM uint32_t SDIO_UHS_SUPPORT_REG; /*!< (@ 0x00000034) UHS Support */ + + struct + { + __IOM uint32_t UHS_SUPPORT : 1; /*!< [0..0] This bit is set by the ARM to indicate the card supports + * the UHS mode for SD3.0 support.which requires 1.8v signal.Setting + * this to one will also make S18A bit to one in R4 Response */ + __IOM uint32_t DDR_DLY_SELECT : 1; /*!< [1..1] This bit field indicates delay select value for DDR mode + * read transaction.0 - 1.5 ns delay value1 - 3 ns delay value */ + __IOM uint32_t CARD_VOLT_ACCEPTED : 1; /*!< [2..2] This bit is set by ARM and it indicates card switched + * to 1.8v successfully */ + __IOM uint32_t SD_CLK_LINE_SWITCHED : 1; /*!< [3..3] This bit is set by ARM and it indicates sd_clk line is + * switched to 1.8v successfully */ + __IOM uint32_t SD_CMD_LINE_SWITCHED : 1; /*!< [4..4] This bit is set by ARM and it indicates cmd line switched + * to 1.8v successfully */ + uint32_t : 27; + } SDIO_UHS_SUPPORT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_CLK_DELAY_TIMER_REG; /*!< (@ 0x00000038) This value used as wait time for the Controller + * before releasing cmd, data line for cmd11 + * voltage switch. */ + + struct + { + __IOM uint32_t CLK_DELAY_TIMER : 32; /*!< [31..0] This value used as wait time for the Controller before + * releasing cmd, data line for cmd11 voltage switch. */ + } SDIO_CLK_DELAY_TIMER_REG_b; + }; + + union + { + __IOM uint32_t SDIO_POWER_CONTROL_REG; /*!< (@ 0x0000003C) Power Control */ + + struct + { + __IM uint32_t EMPC : 1; /*!< [0..0] EMPC=0(default): The total card current shall be less + * than 200mAEMPC=1: The total card current may exceed 200mA. */ + __IM uint32_t EPS_FUN1 : 1; /*!< [1..1] EPS=0(default): The function operates in Higher Cur- + * rent ModeThe maximum current for the function shall be + * given in TPLFE_HP_MAX_PWR_3.3VEPS=1: The function works + * in Lower Current ModeThe maximum current for the function + * shall be given in TPLFE_LP_MAX_PWR_3.3V. */ + uint32_t : 6; + __IOM uint32_t POWERDOWN_REQUEST : 1; /*!< [8..8] It should write to initiate power down sequence, which + * the IP should start writing the register values into the + * RAM */ + __IOM uint32_t FASTINIT_REQUEST : 1; /*!< [9..9] It should write for waking the IP up from power down + * mode. This will indicate that the chip has received a wakeup + * request and the IP has to retain the register values from + * the retention RAM */ + uint32_t : 22; + } SDIO_POWER_CONTROL_REG_b; + }; + + union + { + __IOM uint32_t SDIO_POWER_STATE_REG; /*!< (@ 0x00000040) Power State */ + + struct + { + __IM uint32_t PWR_STATE_FN1 : 4; /*!< [3..0] If PS[3:0] is set to 0, TPL_CODE CISTPL_FUNCE(22h) extension + * 01h is used and the card power is con- trolled by EMPC + * andEPS (SDIO Version 2.00 Compatible).Power State control + * is defined by SDIO Version 3.00 and is effective when EMPC + * is set to 1 and PS[3:0] is set to larger than 0. In this + * case, a list of card sup- ported power states (current) + * is described in the Fun1 CIS tuple */ + uint32_t : 28; + } SDIO_POWER_STATE_REG_b; + }; + __IM uint32_t RESERVED[48]; + + union + { + __IOM uint32_t SDIO_OCR_REG; /*!< (@ 0x00000104) OCR */ + + struct + { + __IOM uint32_t OCR : 24; /*!< [23..0] IO Operational condition register is programmed by the + * ARM which is used to match with theoperating voltage range + * of the SD Host. */ + uint32_t : 8; + } SDIO_OCR_REG_b; + }; + + union + { + __IOM uint32_t SDIO_INTERRUPT_REG; /*!< (@ 0x00000108) Interrupt Identification */ + + struct + { + __IOM uint32_t READ_DATA_READY_INT : 1; /*!< [0..0] Read Ready Interrupt:If set to 1, it indicates that the + * ARM has data ready to send to the SD Host.The bit remains + * set to 1 until the SD Host writes 1 to the corresponding + * bit in the Interrupt identification register.This bit is + * set to one whenever ARM sets the read_data_rdy bit in read_data_rdy + * register. */ + __IOM uint32_t READ_ERROR : 1; /*!< [1..1] Read Error InterruptIf set to 1, it indicates that the + * ARM has send an error response during data transaction + * and the host has to retry the same transaction to prevent + * data loss. */ + __IOM uint32_t MESSAGE_FROM_ARM : 1; /*!< [2..2] ARM Message InterruptIf set to 1, it indicates that the + * ARM has programmed the ARM General Purpose Register (Message + * from ARM to SD Host).On receiving this Interrupt, the SD + * Host will read the ARM General purpose register to find + * the message from ARM. */ + __IOM uint32_t ACK_TO_SD_HOST : 1; /*!< [3..3] Acknowledgment to SD Host. If set to 1, it indicates + * that the ARM has read the message. */ + uint32_t : 4; + __IOM uint32_t READ_DATA_READY_INT_EN : 1; /*!< [8..8] 1 - Read data ready interrupt is enabled0 - Read data + * ready interrupt is disabled */ + __IOM uint32_t READ_ERROR_EN : 1; /*!< [9..9] 1 - Read error interrupt is enabled0 - Read error interrupt + * is disabled */ + __IOM uint32_t MESSAGE_FROM_ARM_EN : 1; /*!< [10..10] 1 - Message from ARM interrupt is enabled0 - Message + * from ARM interrupt is disabled */ + __IOM uint32_t ACK_TO_SD_HOST_EN : 1; /*!< [11..11] 1 - Ack to SD Host interrupt is enabled0 - Ack to SD + * Host interrupt is disabled */ + uint32_t : 20; + } SDIO_INTERRUPT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_TRANSCOUNT_REG; /*!< (@ 0x0000010C) AHB transaction counter */ + + struct + { + __IOM uint32_t AHB_XFER_CNT : 21; /*!< [20..0] This register contains the transfer count value programmable + * by ARM for a read transaction. */ + uint32_t : 11; + } SDIO_AHB_TRANSCOUNT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_SDIOTRANSCOUNT_REG; /*!< (@ 0x00000110) AHB SDIO transaction counter */ + + struct + { + __IM uint32_t XFER_CNT_REG : 21; /*!< [20..0] SDIO_AHB bridge writes the number of bytes transferred + * to ARM processor during write transfer. */ + uint32_t : 11; + } SDIO_AHB_SDIOTRANSCOUNT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_FN1_INT_REG; /*!< (@ 0x00000114) Function 1 interrupt */ + + struct + { + __IOM uint32_t FN1_WR_OVER : 1; /*!< [0..0] This interrupt corresponds to the interrupt issued by + * SD DMA after it completes the write operation of a Function1.Until + * this bit is cleared, busy signal will be asserted in data + * line, the SD DMA engine is prevented from performing an + * AHB write access from a new cmd53 write/read.No valid data + * in the fifo is overwritten. */ + __IOM uint32_t FN1_RD_OVER : 1; /*!< [1..1] This interrupt corresponds to the interrupt issued by + * SD DMA after it completes the read operation of a Function1. */ + __IOM uint32_t FN1_RD_ERROR : 1; /*!< [2..2] This interrupt is issued if SD Host issue abort command + * during function 1 read transaction. */ + __IOM uint32_t FUN1_RST : 1; /*!< [3..3] IOEx,is a CCCR bit (Enable Functionx). If host disable + * IOEx bit in CCCR register, this interrupt is asserted to + * inform the ARM, that funx is disabled by the host.This + * is used for per function reset error recovery and this + * signal will not affect the flops inside the IP. */ + __IOM uint32_t SD_HOST_FN1_MSG_RDY : 1; /*!< [4..4] SD Host Message InterruptIf set to 1, it indicates that + * the SD Host has programmed the SD Host General Purpose + * Register (Message from SD Host to ARM).On receiving this + * Interrupt, the ARM will read the SD Host General purpose + * register to find the message from SD Host. */ + __IOM uint32_t FN1_ACK_TO_ARM : 1; /*!< [5..5] Acknowledgment to ARM. If set to 1, it indicates that + * the SD Host has read the message. */ + __IOM uint32_t FN1_SDIO_RD_START : 1; /*!< [6..6] This bit is set when the SD Host issues CMD53 read com- + * mand. This bit is set by SDIO AHB bridge */ + __IOM uint32_t FN1_SDIO_WR_START : 1; /*!< [7..7] This bit is set when the SD Host issues CMD53 write com- + * mand. This bit is set by SDIO AHB bridge */ + __IOM uint32_t ADMA_END_INT : 1; /*!< [8..8] This bit is set when the adma endbit is set during descriptor + * fetch indicate end of fetch. Then ARM processor ready for + * next fetch (with new updated address) */ + __IOM uint32_t FN1_SUSPEND : 1; /*!< [9..9] This bit is set when suspend command is issued for the + * function1. */ + __IOM uint32_t RESUME : 1; /*!< [10..10] This bit is set when resume command is issued for the + * function1. */ + __IOM uint32_t ADMA_INT : 1; /*!< [11..11] This bit is set by Arasan SDIO_AHB bridge when int + * bit is set in the attribute field during fetch operation. */ + __IOM uint32_t ADMA_ERR : 1; /*!< [12..12] This bit is set by Arasan SDIO_AHB bridge when ARM + * sets valid bit as 0 in the attribute field during fetch + * operation. */ + __IOM uint32_t FUN1_EN : 1; /*!< [13..13] This bit is set by Arasan SDIO_AHB bridge when SD Host + * enables the function enable bit in CCCR register. */ + uint32_t : 18; + } SDIO_AHB_FN1_INT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_AHB_FN1_INT_ENABLE_REG; /*!< (@ 0x00000118) Function 1 interrupt enable */ + + struct + { + __IOM uint32_t FN1_WR_OVER_EN : 1; /*!< [0..0] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_RD_OVER_EN : 1; /*!< [1..1] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_RD_ERROR_EN : 1; /*!< [2..2] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FUN1_RST_EN : 1; /*!< [3..3] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t SD_HOST_FN1_MSG_RDY_EN : 1; /*!< [4..4] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_ACK_TO_ARM_EN : 1; /*!< [5..5] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_SDIO_RD_START_EN : 1; /*!< [6..6] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_SDIO_WR_START_EN : 1; /*!< [7..7] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t ADMA_END_INT_EN : 1; /*!< [8..8] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FN1_SUSPEND_EN : 1; /*!< [9..9] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t RESUME_EN : 1; /*!< [10..10] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t ADMA_INT_EN : 1; /*!< [11..11] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t ADMA_ERR_EN : 1; /*!< [12..12] 1 - interrupt is enabled0 - interrupt is disabled */ + __IOM uint32_t FUN1_EN_INT_EN : 1; /*!< [13..13] 1 - interrupt is enabled0 - interrupt is disabled */ + uint32_t : 18; + } SDIO_AHB_FN1_INT_ENABLE_REG_b; + }; + + union + { + __IOM uint32_t SDIO_FBR_REG; /*!< (@ 0x0000011C) FBR */ + + struct + { + __IOM uint32_t IO_DEVICE_CODE1 : 4; /*!< [3..0] This value denotes the SDIO standard Inter- face supported + * by this function (function 1).0 - No SDIO standard Interface + * supported bythis function. */ + __IOM uint32_t FUN_CSA_SUP : 1; /*!< [4..4] CSA support bit1 - CSA Supported.0 - CSA is not Supported. */ + __IOM uint32_t EXTENDED_IO_DEVICE_CODE1 : 8; /*!< [12..5] This is the Extension of the Standard I/O Device Code + * for Function 1. */ + __IOM uint32_t SDIO_SPS : 1; /*!< [13..13] Function1 supports high power. */ + uint32_t : 18; + } SDIO_FBR_REG_b; + }; + + union + { + __IOM uint32_t SDIO_IOR_REG; /*!< (@ 0x00000120) IOR */ + + struct + { + __IOM uint32_t IOR_REG : 1; /*!< [0..0] set this bit to indicate that the function is ready.This + * is used to set IOR1 bit in cccr */ + uint32_t : 31; + } SDIO_IOR_REG_b; + }; + + union + { + __IOM uint32_t SDIO_SD_HOST_GP_REG; /*!< (@ 0x00000124) SD Host General Purpose Register */ + + struct + { + __IM uint32_t SD_HOST_GP : 32; /*!< [31..0] SD Host General Purpose Register.An Interrupt will be + * asserted to the ARM, whenever SD Host writes into this + * register indicating that there is a message for ARM. */ + } SDIO_SD_HOST_GP_REG_b; + }; + + union + { + __IOM uint32_t SDIO_ARM_GP_REG; /*!< (@ 0x00000128) ARM General Purpose Register */ + + struct + { + __OM uint32_t ARM_GP : 32; /*!< [31..0] ARM General Purpose Register.An Interrupt will be asserted + * to the SD Host, whenever ARM writes into this register + * indicating that there is a message for SD Host. */ + } SDIO_ARM_GP_REG_b; + }; + + union + { + __IOM uint32_t SDIO_RDDATRDY_REG; /*!< (@ 0x0000012C) Read Data Ready */ + + struct + { + __IOM uint32_t FN1_RDDATRDY : 1; /*!< [0..0] ARM sets this bit to indicate that the function1 read + * data is ready.This bit is auto cleared. If ARM sets this + * bit to 1 then it should wait for the fn_read_over or fn_rd_error + * interrupt. */ + uint32_t : 31; + } SDIO_RDDATRDY_REG_b; + }; + + union + { + __IOM uint32_t SDIO_BLKSIZE_REG; /*!< (@ 0x00000130) Block Size */ + + struct + { + __IM uint32_t BLK_SIZE : 12; /*!< [11..0] Block Size Register. The Arasan SDIO-AHB Controller + * read this register based on the block size programmed by + * the SD host */ + __IM uint32_t SIN_MUL_BLK : 1; /*!< [12..12] This bit indicates current transaction is Block/Byte + * mode transaction.For cmd 53 block mode this value is 1. + * For cmd53 byte mode this value is 0 */ + uint32_t : 19; + } SDIO_BLKSIZE_REG_b; + }; + + union + { + __IOM uint32_t SDIO_ARGUMENT_REG; /*!< (@ 0x00000134) Argument */ + + struct + { + __IM uint32_t ARG_REG : 32; /*!< [31..0] IO transaction:[8:0] -> Byte/Block count In case of + * Block mode it indicates Block count value. In case of Byte + * mode it indicates Byte count value. [25:9] -> Register + * address field in CMD53.[26] -> Opcode[27] -> Blockmode. + * 1 - Block mode. 0 - Byte mode.[30:28] -> Function Number + * field in CMD53[31] -> R/W flag field in CMD53. 1 -> Write + * CMD53. 0 -> Read CMD53 */ + } SDIO_ARGUMENT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_WRBLKCNT_REG; /*!< (@ 0x00000138) Write Block Count */ + + struct + { + __IOM uint32_t WR_BLK_CNT : 16; /*!< [15..0] This register has the value of how many blocks are transferred + * from SD Host to ARM.On receiving fn1_wr_over, ARM should + * clear this register. */ + uint32_t : 16; + } SDIO_WRBLKCNT_REG_b; + }; + + union + { + __IOM uint32_t SDIO_RDBLKCNT_REG; /*!< (@ 0x0000013C) Read Block Count */ + + struct + { + __IOM uint32_t RD_BLK_CNT : 16; /*!< [15..0] This register has the value of how many blocks are transferred + * from ARM to SD Host.On receiving the fn1_read_over interrupt, + * ARM should clear this register */ + uint32_t : 16; + } SDIO_RDBLKCNT_REG_b; + }; +} SDIO_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SPI registers (SPI) + */ + +typedef struct /*!< (@ 0x40090200) SPI Structure */ +{ + union + { + __IOM uint32_t SPI_CTRL_REG; /*!< (@ 0x00000000) Spi control register */ + + struct + { + __IOM uint32_t SPI_EN : 1; /*!< [0..0] 0 = SPI module is disable1 = SPI module is enable */ + __IOM uint32_t SPI_TX_EN : 1; /*!< [1..1] 0 = TX path is disabled1 = TX path is enabled */ + __IOM uint32_t SPI_RX_EN : 1; /*!< [2..2] 0 = RX path is disabled1 = RX path is enabledNote: if + * spi mode=1 or spi mode=3 readonly is not supported */ + __IOM uint32_t SPI_DMA_TX_EN : 1; /*!< [3..3] applicable only when SPI_TX_EN=10 = No DMA request for + * TX1 = DMA request when SPI_STATUS_TX_EMPTY='1' */ + __IOM uint32_t SPI_DMA_RX_EN : 1; /*!< [4..4] applicable only when SPI_RX_EN=10 = No DMA request for + * RX1 = DMA request when SPI_STATUS_RX_FULL='1' */ + __IOM uint32_t SPI_FIFO_RESET : 1; /*!< [5..5] 0 = Fifo normal operation1 = Fifo in reset state */ + __IOM uint32_t SPI_CAPTURE_AT_NEXT_EDGE : 1; /*!< [6..6] 0 = SPI captures data at correct clock edge1 = SPI captures + * data at next clock edge. (only for Master mode and high + * clock) */ + __IOM uint32_t SPI_SWAP_BYTES : 1; /*!< [7..7] 0 = normal operation1 = LSB and MSB are swaped in APB + * interfaceIn case of 8bit spi interface, DMA/SPI can be + * configured in 16bit mode to off load the bus. Enabling + * SPI_SWAP_BYTES bytes will read/wrte correctly */ + uint32_t : 24; + } SPI_CTRL_REG_b; + }; + + union + { + __IOM uint32_t SPI_CONFIG_REG; /*!< (@ 0x00000004) Spi control register */ + + struct + { + __IOM uint32_t SPI_MODE : 2; /*!< [1..0] Define the spi mode (CPOL, CPHA)0 = new data on falling, + * capture on rising, clk low in idle state1 = new data on + * rising, capture on falling, Clk low in idle state2 = new + * data on rising, capture on falling, Clk high in idle state3 + * = new data on falling, capture on rising Clk high in idle + * state */ + __IOM uint32_t SPI_WORD_LENGTH : 5; /*!< [6..2] Define the spi word length = 1+ SPI_WORD_LENGTH (range + * 4 to 32)Note: should be changed with SPI_EN=0 */ + __IOM uint32_t SPI_SLAVE_EN : 1; /*!< [7..7] 0 = SPI module master mode1 = SPI module slave mode */ + uint32_t : 24; + } SPI_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t SPI_CLOCK_REG; /*!< (@ 0x00000008) Spi clock register */ + + struct + { + __IOM uint32_t SPI_CLK_DIV : 7; /*!< [6..0] Applicable only in master modeDefines the spi clock frequency + * in master only modeSPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) + * when SPI_CLK_DIV not 0x7Fif SPI_CLK_DIV=0x7F then SPI_CLK=module_clk */ + uint32_t : 25; + } SPI_CLOCK_REG_b; + }; + + union + { + __IOM uint32_t SPI_FIFO_CONFIG_REG; /*!< (@ 0x0000000C) Spi fifo configuration register */ + + struct + { + __IOM uint32_t SPI_TX_TL : 8; /*!< [7..0] Transmit FIFO threshold level in bytes. Control the level + * of bytes in fifo that triggers the TX_EMPTY interrupt. + * IRQ is occurred when fifo level is less or equal to SPI_TX_TL. + * Valid FIFO level is from 0 to 32 */ + __IOM uint32_t SPI_RX_TL : 8; /*!< [15..8] Receive FIFO threshold level in bytes. Control the level + * of bytes in fifo that triggers the RX_FULL interrupt. IRQ + * is occurred when fifo level is more or equal to SPI_RX_TL+1. + * Valid FIFO level is from 0 to 32 */ + uint32_t : 16; + } SPI_FIFO_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t SPI_IRQ_MASK_REG; /*!< (@ 0x00000010) Spi interrupt mask register */ + + struct + { + __IOM uint32_t SPI_IRQ_MASK_TX_EMPTY : 1; /*!< [0..0] 0 = FIFO TX empty irq is masked1 = FIFO TX empy irq is + * enabled */ + __IOM uint32_t SPI_IRQ_MASK_RX_FULL : 1; /*!< [1..1] 0 = FIFO RX full irq is masked1 = FIFO RX full irq is + * enabled */ + uint32_t : 30; + } SPI_IRQ_MASK_REG_b; + }; + + union + { + __IOM uint32_t SPI_STATUS_REG; /*!< (@ 0x00000014) Spi status register */ + + struct + { + __IM uint32_t SPI_STATUS_TX_EMPTY : 1; /*!< [0..0] Auto clear0 = TX fifo level is larger than SPI_TX_TL1 + * = TX fifo level is less or equal to SPI_TX_TL */ + __IM uint32_t SPI_STATUS_RX_FULL : 1; /*!< [1..1] Auto clear0 = RX fifo level is less than SPI_RX_TL+11 + * = RX fifo level is more or equal to SPI_RX_TL+1 */ + uint32_t : 30; + } SPI_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SPI_FIFO_STATUS_REG; /*!< (@ 0x00000018) SPI RX/TX fifo status register */ + + struct + { + __IM uint32_t SPI_RX_FIFO_LEVEL : 6; /*!< [5..0] Gives the number of bytes in RX fifo */ + __IM uint32_t SPI_TX_FIFO_LEVEL : 6; /*!< [11..6] Gives the number of bytes in TX fifo */ + __IM uint32_t SPI_STATUS_RX_EMPTY : 1; /*!< [12..12] 0 = RX fifo is not empty1 = RX fifo is empty */ + __IM uint32_t SPI_STATUS_TX_FULL : 1; /*!< [13..13] 0 = TX fifo is not full1 = TX fifo is full */ + __IM uint32_t SPI_RX_FIFO_OVFL : 1; /*!< [14..14] When 1, receive data is not written to fifo because + * fifo was full and interrupt is generated. It clears with + * SPI_CTRL_REG.SPI_FIFO_RESET */ + __IM uint32_t SPI_TRANSACTION_ACTIVE : 1; /*!< [15..15] In master mode0 = spi transaction is inactive1 = spi + * transaction is active */ + uint32_t : 16; + } SPI_FIFO_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SPI_FIFO_READ_REG; /*!< (@ 0x0000001C) Spi RX fifo read register */ + + struct + { + __IM uint32_t SPI_FIFO_READ : 32; /*!< [31..0] Read from RX fifo. Read access is permit only if SPI_RX_FIFO_EMPTY=0. */ + } SPI_FIFO_READ_REG_b; + }; + + union + { + __IOM uint32_t SPI_FIFO_WRITE_REG; /*!< (@ 0x00000020) Spi TX fifo wtite register */ + + struct + { + __OM uint32_t SPI_FIFO_WRITE : 32; /*!< [31..0] Write to TX fifo. Write access is permit only if SPI_TX_FIFO_FULL + * is 0 */ + } SPI_FIFO_WRITE_REG_b; + }; + + union + { + __IOM uint32_t SPI_CS_CONFIG_REG; /*!< (@ 0x00000024) Spi cs configuration register */ + + struct + { + __IOM uint32_t SPI_CS_SELECT : 3; /*!< [2..0] Control the cs output in master mode0 = none slave device + * selected1 = selected slave device connected to GPIO with + * FUNC_MODE=SPI_CS02 = selected slave device connected to + * GPIO with FUNC_MODE=SPI_CS14 = selected slave device connected + * to GPIO with FUNC_MODE=GPIO */ + uint32_t : 29; + } SPI_CS_CONFIG_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SPI_TXBUFFER_FORCE_REG; /*!< (@ 0x0000002C) SPI TX buffer force low value */ + + struct + { + __OM uint32_t SPI_TXBUFFER_FORCE : 32; /*!< [31..0] Write directly the tx buffer . It must to be used only + * in slave mode */ + } SPI_TXBUFFER_FORCE_REG_b; + }; +} SPI_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SPI2 registers (SPI2) + */ + +typedef struct /*!< (@ 0x40090300) SPI2 Structure */ +{ + union + { + __IOM uint32_t SPI2_CTRL_REG; /*!< (@ 0x00000000) Spi control register */ + + struct + { + __IOM uint32_t SPI_EN : 1; /*!< [0..0] 0 = SPI module is disable1 = SPI module is enable */ + __IOM uint32_t SPI_TX_EN : 1; /*!< [1..1] 0 = TX path is disabled1 = TX path is enabled */ + __IOM uint32_t SPI_RX_EN : 1; /*!< [2..2] 0 = RX path is disabled1 = RX path is enabledNote: if + * spi mode=1 or spi mode=3 readonly is not supported */ + __IOM uint32_t SPI_DMA_TX_EN : 1; /*!< [3..3] applicable only when SPI_TX_EN=10 = No DMA request for + * TX1 = DMA request when SPI_STATUS_TX_EMPTY='1' */ + __IOM uint32_t SPI_DMA_RX_EN : 1; /*!< [4..4] applicable only when SPI_RX_EN=10 = No DMA request for + * RX1 = DMA request when SPI_STATUS_RX_FULL='1' */ + __IOM uint32_t SPI_FIFO_RESET : 1; /*!< [5..5] 0 = Fifo normal operation1 = Fifo in reset state */ + __IOM uint32_t SPI_CAPTURE_AT_NEXT_EDGE : 1; /*!< [6..6] 0 = SPI captures data at correct clock edge1 = SPI captures + * data at next clock edge. (only for Master mode and high + * clock) */ + __IOM uint32_t SPI_SWAP_BYTES : 1; /*!< [7..7] 0 = normal operation1 = LSB and MSB are swaped in APB + * interfaceIn case of 8bit spi interface, DMA/SPI can be + * configured in 16bit mode to off load the bus. Enabling + * SPI_SWAP_BYTES bytes will read/wrte correctly */ + uint32_t : 24; + } SPI2_CTRL_REG_b; + }; + + union + { + __IOM uint32_t SPI2_CONFIG_REG; /*!< (@ 0x00000004) Spi control register */ + + struct + { + __IOM uint32_t SPI_MODE : 2; /*!< [1..0] Define the spi mode (CPOL, CPHA)0 = new data on falling, + * capture on rising, clk low in idle state1 = new data on + * rising, capture on falling, Clk low in idle state2 = new + * data on rising, capture on falling, Clk high in idle state3 + * = new data on falling, capture on rising Clk high in idle + * state */ + __IOM uint32_t SPI_WORD_LENGTH : 5; /*!< [6..2] Define the spi word length = 1+ SPI_WORD_LENGTH (range + * 4 to 32)Note: should be changed with SPI_EN=0 */ + __IOM uint32_t SPI_SLAVE_EN : 1; /*!< [7..7] 0 = SPI module master mode1 = SPI module slave mode */ + uint32_t : 24; + } SPI2_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t SPI2_CLOCK_REG; /*!< (@ 0x00000008) Spi clock register */ + + struct + { + __IOM uint32_t SPI_CLK_DIV : 7; /*!< [6..0] Applicable only in master modeDefines the spi clock frequency + * in master only modeSPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) + * when SPI_CLK_DIV not 0x7Fif SPI_CLK_DIV=0x7F then SPI_CLK=module_clk */ + uint32_t : 25; + } SPI2_CLOCK_REG_b; + }; + + union + { + __IOM uint32_t SPI2_FIFO_CONFIG_REG; /*!< (@ 0x0000000C) Spi fifo configuration register */ + + struct + { + __IOM uint32_t SPI_TX_TL : 8; /*!< [7..0] Transmit FIFO threshold level in bytes. Control the level + * of bytes in fifo that triggers the TX_EMPTY interrupt. + * IRQ is occurred when fifo level is less or equal to SPI_TX_TL. + * Valid FIFO level is from 0 to 32 */ + __IOM uint32_t SPI_RX_TL : 8; /*!< [15..8] Receive FIFO threshold level in bytes. Control the level + * of bytes in fifo that triggers the RX_FULL interrupt. IRQ + * is occurred when fifo level is more or equal to SPI_RX_TL+1. + * Valid FIFO level is from 0 to 32 */ + uint32_t : 16; + } SPI2_FIFO_CONFIG_REG_b; + }; + + union + { + __IOM uint32_t SPI2_IRQ_MASK_REG; /*!< (@ 0x00000010) Spi interrupt mask register */ + + struct + { + __IOM uint32_t SPI_IRQ_MASK_TX_EMPTY : 1; /*!< [0..0] 0 = FIFO TX empty irq is masked1 = FIFO TX empy irq is + * enabled */ + __IOM uint32_t SPI_IRQ_MASK_RX_FULL : 1; /*!< [1..1] 0 = FIFO RX full irq is masked1 = FIFO RX full irq is + * enabled */ + uint32_t : 30; + } SPI2_IRQ_MASK_REG_b; + }; + + union + { + __IOM uint32_t SPI2_STATUS_REG; /*!< (@ 0x00000014) Spi status register */ + + struct + { + __IM uint32_t SPI_STATUS_TX_EMPTY : 1; /*!< [0..0] Auto clear0 = TX fifo level is larger than SPI_TX_TL1 + * = TX fifo level is less or equal to SPI_TX_TL */ + __IM uint32_t SPI_STATUS_RX_FULL : 1; /*!< [1..1] Auto clear0 = RX fifo level is less than SPI_RX_TL+11 + * = RX fifo level is more or equal to SPI_RX_TL+1 */ + uint32_t : 30; + } SPI2_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SPI2_FIFO_STATUS_REG; /*!< (@ 0x00000018) SPI RX/TX fifo status register */ + + struct + { + __IM uint32_t SPI_RX_FIFO_LEVEL : 6; /*!< [5..0] Gives the number of bytes in RX fifo */ + __IM uint32_t SPI_TX_FIFO_LEVEL : 6; /*!< [11..6] Gives the number of bytes in TX fifo */ + __IM uint32_t SPI_STATUS_RX_EMPTY : 1; /*!< [12..12] 0 = RX fifo is not empty1 = RX fifo is empty */ + __IM uint32_t SPI_STATUS_TX_FULL : 1; /*!< [13..13] 0 = TX fifo is not full1 = TX fifo is full */ + __IM uint32_t SPI_RX_FIFO_OVFL : 1; /*!< [14..14] When 1, receive data is not written to fifo because + * fifo was full and interrupt is generated. It clears with + * SPI_CTRL_REG.SPI_FIFO_RESET */ + __IM uint32_t SPI_TRANSACTION_ACTIVE : 1; /*!< [15..15] In master mode0 = spi transaction is inactive1 = spi + * transaction is active */ + uint32_t : 16; + } SPI2_FIFO_STATUS_REG_b; + }; + + union + { + __IOM uint32_t SPI2_FIFO_READ_REG; /*!< (@ 0x0000001C) Spi RX fifo read register */ + + struct + { + __IM uint32_t SPI_FIFO_READ : 32; /*!< [31..0] Read from RX fifo. Read access is permit only if SPI_RX_FIFO_EMPTY=0. */ + } SPI2_FIFO_READ_REG_b; + }; + + union + { + __IOM uint32_t SPI2_FIFO_WRITE_REG; /*!< (@ 0x00000020) Spi TX fifo wtite register */ + + struct + { + __OM uint32_t SPI_FIFO_WRITE : 32; /*!< [31..0] Write to TX fifo. Write access is permit only if SPI_TX_FIFO_FULL + * is 0 */ + } SPI2_FIFO_WRITE_REG_b; + }; + + union + { + __IOM uint32_t SPI2_CS_CONFIG_REG; /*!< (@ 0x00000024) Spi cs configuration register */ + + struct + { + __IOM uint32_t SPI_CS_SELECT : 3; /*!< [2..0] Control the cs output in master mode0 = none slave device + * selected1 = selected slave device connected to GPIO with + * FUNC_MODE=SPI_CS02 = selected slave device connected to + * GPIO with FUNC_MODE=SPI_CS14 = selected slave device connected + * to GPIO with FUNC_MODE=GPIO */ + uint32_t : 29; + } SPI2_CS_CONFIG_REG_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SPI2_TXBUFFER_FORCE_REG; /*!< (@ 0x0000002C) SPI TX buffer force low value */ + + struct + { + __OM uint32_t SPI_TXBUFFER_FORCE : 32; /*!< [31..0] Write directly the tx buffer . It must to be used only + * in slave mode */ + } SPI2_TXBUFFER_FORCE_REG_b; + }; +} SPI2_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ SRC_FIFO_IF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRC_FIFO_IF registers (SRC_FIFO_IF) + */ + +typedef struct /*!< (@ 0x40003000) SRC_FIFO_IF Structure */ +{ + union + { + __IOM uint32_t APU_FIFO_STATUS_REG; /*!< (@ 0x00000000) APU FIFO Status */ + + struct + { + __IOM uint32_t SRC_CH1_IN_EMPTY : 1; /*!< [0..0] SRC input FIFO empty */ + __IOM uint32_t SRC_CH1_IN_FULL : 1; /*!< [1..1] SRC input FIFO full */ + __IOM uint32_t SRC_CH1_OUT_EMPTY : 1; /*!< [2..2] SRC output FIFO empty */ + __IOM uint32_t SRC_CH1_OUT_FULL : 1; /*!< [3..3] SRC output FIFO full */ + __IOM uint32_t SRC_CH2_IN_EMPTY : 1; /*!< [4..4] SRC input FIFO empty */ + __IOM uint32_t SRC_CH2_IN_FULL : 1; /*!< [5..5] SRC input FIFO full */ + __IOM uint32_t SRC_CH2_OUT_EMPTY : 1; /*!< [6..6] SRC output FIFO empty */ + __IOM uint32_t SRC_CH2_OUT_FULL : 1; /*!< [7..7] SRC output FIFO full */ + uint32_t : 8; + __IOM uint32_t DAI_CH1_OUT_EMPTY : 1; /*!< [16..16] DAI output FIFO empty */ + __IOM uint32_t DAI_CH1_OUT_FULL : 1; /*!< [17..17] DAI output FIFO full */ + __IOM uint32_t DAI_CH1_IN_EMPTY : 1; /*!< [18..18] DAI input FIFO empty */ + __IOM uint32_t DAI_CH1_IN_FULL : 1; /*!< [19..19] DAI input FIFO full */ + __IOM uint32_t DAI_CH2_OUT_EMPTY : 1; /*!< [20..20] DAI output FIFO empty */ + __IOM uint32_t DAI_CH2_OUT_FULL : 1; /*!< [21..21] DAI output FIFO full */ + __IOM uint32_t DAI_CH2_IN_EMPTY : 1; /*!< [22..22] DAI input FIFO empty */ + __IOM uint32_t DAI_CH2_IN_FULL : 1; /*!< [23..23] DAI input FIFO full */ + uint32_t : 8; + } APU_FIFO_STATUS_REG_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t APU_SRC_FIFO_IN1_REG; /*!< (@ 0x00000010) SRC data in 1 */ + + struct + { + __OM uint32_t SRC_IN : 32; /*!< [31..0] SRC_FIFO_IN1 */ + } APU_SRC_FIFO_IN1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_FIFO_IN2_REG; /*!< (@ 0x00000014) SRC data in 2 */ + + struct + { + __OM uint32_t SRC_IN : 32; /*!< [31..0] SRC_FIFO_IN2 */ + } APU_SRC_FIFO_IN2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_FIFO_OUT1_REG; /*!< (@ 0x00000018) SRC data out 1 */ + + struct + { + __IM uint32_t SRC_OUT : 32; /*!< [31..0] SRC_FIFO_OUT1 */ + } APU_SRC_FIFO_OUT1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_FIFO_OUT2_REG; /*!< (@ 0x0000001C) SRC data out 2 */ + + struct + { + __IM uint32_t SRC_OUT : 32; /*!< [31..0] SRC_FIFO_OUT2 */ + } APU_SRC_FIFO_OUT2_REG_b; + }; + + union + { + __IOM uint32_t APU_DAI_FIFO_IN1_REG; /*!< (@ 0x00000020) DAI data in 1 */ + + struct + { + __OM uint32_t DAI_IN : 32; /*!< [31..0] DAI_FIFO_OUT1 */ + } APU_DAI_FIFO_IN1_REG_b; + }; + + union + { + __IOM uint32_t APU_DAI_FIFO_IN2_REG; /*!< (@ 0x00000024) DAI data in 2 */ + + struct + { + __OM uint32_t DAI_IN : 32; /*!< [31..0] DAI_FIFO_OUT2 */ + } APU_DAI_FIFO_IN2_REG_b; + }; + + union + { + __IOM uint32_t APU_DAI_FIFO_OUT1_REG; /*!< (@ 0x00000028) DAI data out 1 */ + + struct + { + __IM uint32_t DAI_OUT : 32; /*!< [31..0] DAI_FIFO_IN1 */ + } APU_DAI_FIFO_OUT1_REG_b; + }; + + union + { + __IOM uint32_t APU_DAI_FIFO_OUT2_REG; /*!< (@ 0x0000002C) DAI data out 2 */ + + struct + { + __IM uint32_t DAI_OUT : 32; /*!< [31..0] DAI_FIFO_IN2 */ + } APU_DAI_FIFO_OUT2_REG_b; + }; +} SRC_FIFO_IF_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ SRC_IF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRC_IF registers (SRC_IF) + */ + +typedef struct /*!< (@ 0x400E0C00) SRC_IF Structure */ +{ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t APU_SRC_CTRL_REG; /*!< (@ 0x00000020) SRC control register */ + + struct + { + __IOM uint32_t SRC_EN : 1; /*!< [0..0] SRC_IN and SRC_OUT enable0: disabled1: enabled */ + __IOM uint32_t SRC_IN_AMODE : 1; /*!< [1..1] SRC_IN Automatic conversion mode0: Manual mode1: Automatic + * mode */ + __IOM uint32_t SRC_IN_CAL_BYPASS : 1; /*!< [2..2] SRC_IN upsampling filter bypass0: Do not bypass1: Bypass + * filter */ + __IOM uint32_t SRC_PDM_IN_INV : 1; /*!< [3..3] Invert PDM_CLK, see timing diagrams */ + __IOM uint32_t SRC_IN_DS : 2; /*!< [5..4] SRC_IN UpSampling IIR filters setting00: for sample rates + * up-to 48kHz01: for sample rates of 96kHz10: reserved11: + * for sample rates of 192kHz */ + __IM uint32_t SRC_IN_OK : 1; /*!< [6..6] SRC_IN status0: Acquisition in progress1: Acquisition + * ready */ + __IOM uint32_t SRC_DITHER_DISABLE : 1; /*!< [7..7] Dithering feature0: Enable1: Disable */ + __IOM uint32_t SRC_PCM_GAIN : 2; /*!< [9..8] PCM Input gain */ + __IOM uint32_t SRC_FIFO_IN1_ENABLE : 1; /*!< [10..10] 0: fifo_in1 disable. On each src request, one sample + * is serviced1: fifo_in1 enable. Fifo is used to store samples + * to srcSRC supports only DMA burst size 4 when fifo is enable + * else no burst */ + __IOM uint32_t SRC_FIFO_IN2_ENABLE : 1; /*!< [11..11] 0: fifo_in2 disable. On each src request, one sample + * is serviced1: fifo_in2 enable. Fifo is used to store samples + * to srcSRC supports only DMA burst size 4 when fifo is enable + * else no burst */ + __IOM uint32_t SRC_PDM_EN : 1; /*!< [12..12] PDM input enable */ + __IOM uint32_t SRC_OUT_AMODE : 1; /*!< [13..13] SRC_OUT1 Automatic Conversion mode0:Manual mode1:Automatic + * mode */ + __IOM uint32_t SRC_OUT_CAL_BYPASS : 1; /*!< [14..14] SRC_OUT1 upsampling filter bypass0: Do not bypass1: + * Bypass filter */ + __IOM uint32_t SRC_OUT_SET : 1; /*!< [15..15] SRC_OUT Filter coefficient set selection0: Set 1 is + * intended for wide band and full band audio (16-48 kHz). + * The filters are optimized for a narrow transition band + * and excellent anti-aliasing suppression.1: Set 2 is for + * intended for narrowband and wide band voice calls (8-16 + * kHz). The filters are optimized for low-latency. */ + __IOM uint32_t SRC_OUT_US : 2; /*!< [17..16] SRC_OUT UpSampling IIR filters setting00: for sample + * rates up-to 48kHz01: for sample rates of 96kHz10: reserved11: + * for sample rates of 192kHz */ + __IM uint32_t SRC_OUT_OK : 1; /*!< [18..18] SRC_OUT Status0: acquisition in progress1: acquisition + * ready (In manual mode this bit is always 1) */ + __OM uint32_t SRC_RESYNC : 1; /*!< [19..19] 1: SRC will restart synchronisation */ + __IM uint32_t SRC_IN_OVFLOW : 1; /*!< [20..20] 1: SRC_IN Overflow occurred */ + __IM uint32_t SRC_IN_UNFLOW : 1; /*!< [21..21] 1: SRC_IN Underflow occurred */ + __IM uint32_t SRC_OUT_OVFLOW : 1; /*!< [22..22] 1: SRC_OUT Overflow occurred */ + __IM uint32_t SRC_OUT_UNFLOW : 1; /*!< [23..23] 1: SRC_OUT Underflow occurred */ + __OM uint32_t SRC_IN_FLOWCLR : 1; /*!< [24..24] Writing a 1 clears the SRC_IN Overflow/underflow bits + * 21-20. No more over/underflow indications while bit is + * 1. Keep 1 until the over/under flow bit is cleared */ + __OM uint32_t SRC_OUT_FLOWCLR : 1; /*!< [25..25] Writing a 1 clears the SRC_OUT Overflow/underflow bits + * 23-22. No more over/underflow indications while bit is + * 1. Keep 1 until the over/under flow bit is cleared */ + __IOM uint32_t SRC_FIFO_OUT1_ENABLE : 1; /*!< [26..26] 0: fifo_out1 disable. On each src request, one sample + * is serviced1: fifo_out1 enable. Fifo is used to store samples + * from srcSRC supports only DMA burst size 4 when fifo is + * enable else no burst */ + __IOM uint32_t SRC_FIFO_OUT2_ENABLE : 1; /*!< [27..27] 0: fifo_out2 disable. On each src request, one sample + * is serviced1: fifo_out2 enable. Fifo is used to store samples + * from srcSRC supports only DMA burst size 4 when fifo is + * enable else no burst */ + uint32_t : 2; + __IOM uint32_t SRC_IN_COEF_SET : 1; /*!< [30..30] SRC_IN Filter coefficient set selection0: Set 1 is + * intended for wideband and fullband audio (16-48 kHz). The + * filters are optimized for a narrow transition band and + * excellent anti-aliasing suppression.1: Set 2 is for intended + * for narrowband and wideband voice calls (8-16 kHz). The + * filters are optimized for low-latency. */ + uint32_t : 1; + } APU_SRC_CTRL_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_IN_FS_REG; /*!< (@ 0x00000024) SRC Sample input rate */ + + struct + { + __IOM uint32_t SRC_IN_FS : 24; /*!< [23..0] SRC_IN Sample rateSRC_IN_FS = 4096*Sample_rate/100*(32768/SRC_CLK)Samp + * e_rate upper limit is 192kHz. For 96kHz and 192kHz SRC_CTRLx_REG[SRC_IN_D + * ] must be set as shown below:For SRC_CLK=32.768 kHz, SRC_DIV=1:Sample_rat + * SRC_IN_FS SRC_IN_DS Audio bandwidth8000 Hz 0x050000 0 4000 + * Hz11025 Hz 0x06E400 0 5512 Hz16000 Hz 0x0A0000 0 8000 Hz22050 + * Hz 0x0DC800 0 11025 Hz32000 Hz 0x140000 0 16000 Hz44100 + * Hz 0x1B9 */ + uint32_t : 8; + } APU_SRC_IN_FS_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_OUT_FS_REG; /*!< (@ 0x00000028) SRC Sample output rate */ + + struct + { + __IOM uint32_t SRC_OUT_FS : 24; /*!< [23..0] SRC_OUT Sample rateSRC_IN_FS = 4096*Sample_rate/100*(32768/SRC_CLK)Sam + * le_rate upper limit is 192kHz. For 96kHz and 192kHz SRC_CTRLx_REG[SRC_OUT + * US] must be set as shown below:For SRC_CLK=32.768 kHz, + * SRC_DIV=1:Sample_rate SRC_OUT_FS SRC_OUT_US Audio bandwidth8000 + * Hz 0x050000 0 4000 Hz11025 Hz 0x06E400 0 5512 Hz16000 Hz + * 0x0A0000 0 8000 Hz22050 Hz 0x0DC800 0 11025 Hz32000 Hz + * 0x140000 0 16000 Hz */ + uint32_t : 8; + } APU_SRC_OUT_FS_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_IN1_REG; /*!< (@ 0x0000002C) SRC data in 1 */ + + struct + { + __IOM uint32_t SRC_IN : 32; /*!< [31..0] SRC_IN1 */ + } APU_SRC_IN1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_IN2_REG; /*!< (@ 0x00000030) SRC data in 2 */ + + struct + { + __IOM uint32_t SRC_IN : 32; /*!< [31..0] SRC_IN2 */ + } APU_SRC_IN2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_OUT1_REG; /*!< (@ 0x00000034) SRC data out 1 */ + + struct + { + __IM uint32_t SRC_OUT : 32; /*!< [31..0] SRC_OUT1 */ + } APU_SRC_OUT1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_OUT2_REG; /*!< (@ 0x00000038) SRC data out 2 */ + + struct + { + __IM uint32_t SRC_OUT : 32; /*!< [31..0] SRC_OUT2 */ + } APU_SRC_OUT2_REG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t APU_SRC_FIFO_CTRL_REG; /*!< (@ 0x00000040) SRC FIFO control */ + + struct + { + __IOM uint32_t FIFO_CTRL : 32; /*!< [31..0] bit0 : FIFO enablebit10 : input channel 1 enablebit11 + * : input channel 2 enablebit26 : output channel 1 enablebit27 + * : output channel 2 enable */ + } APU_SRC_FIFO_CTRL_REG_b; + }; + + union + { + __IOM uint32_t APU_DAI_FIFO_CTRL_REG; /*!< (@ 0x00000044) DAI FIFO control */ + + struct + { + __IOM uint32_t FIFO_CTRL : 32; /*!< [31..0] bit0 : FIFO enablebit10 : input channel 1 enablebit11 + * : input channel 2 enablebit26 : output channel 1 enablebit27 + * : output channel 2 enable */ + } APU_DAI_FIFO_CTRL_REG_b; + }; + __IM uint32_t RESERVED2[38]; + + union + { + __IOM uint32_t APU_SRC_COEF10_SET1_REG; /*!< (@ 0x000000E0) SRC coefficient 1,0 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF0 : 16; /*!< [15..0] coefficient 0 */ + __IOM uint32_t SRC_COEF1 : 16; /*!< [31..16] coefficient 1 */ + } APU_SRC_COEF10_SET1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF32_SET1_REG; /*!< (@ 0x000000E4) SRC coefficient 3,2 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF2 : 16; /*!< [15..0] coefficient 2 */ + __IOM uint32_t SRC_COEF3 : 16; /*!< [31..16] coefficient 3 */ + } APU_SRC_COEF32_SET1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF54_SET1_REG; /*!< (@ 0x000000E8) SRC coefficient 5,4 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF4 : 16; /*!< [15..0] coefficient 4 */ + __IOM uint32_t SRC_COEF5 : 16; /*!< [31..16] coefficient 5 */ + } APU_SRC_COEF54_SET1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF76_SET1_REG; /*!< (@ 0x000000EC) SRC coefficient 7,6 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF6 : 16; /*!< [15..0] coefficient 6 */ + __IOM uint32_t SRC_COEF7 : 16; /*!< [31..16] coefficient 7 */ + } APU_SRC_COEF76_SET1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF98_SET1_REG; /*!< (@ 0x000000F0) SRC coefficient 9,8 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF8 : 16; /*!< [15..0] coefficient 8 */ + __IOM uint32_t SRC_COEF9 : 16; /*!< [31..16] coefficient 9 */ + } APU_SRC_COEF98_SET1_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF0A_SET1_REG; /*!< (@ 0x000000F4) SRC coefficient 10 set 1 */ + + struct + { + __IOM uint32_t SRC_COEF10 : 16; /*!< [15..0] coefficient 10 */ + uint32_t : 16; + } APU_SRC_COEF0A_SET1_REG_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t APU_SRC_COEF10_SET2_REG; /*!< (@ 0x00000100) SRC coefficient 1,0 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF0 : 16; /*!< [15..0] coefficient 0 */ + __IOM uint32_t SRC_COEF1 : 16; /*!< [31..16] coefficient 1 */ + } APU_SRC_COEF10_SET2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF32_SET2_REG; /*!< (@ 0x00000104) SRC coefficient 3,2 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF2 : 16; /*!< [15..0] coefficient 2 */ + __IOM uint32_t SRC_COEF3 : 16; /*!< [31..16] coefficient 3 */ + } APU_SRC_COEF32_SET2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF54_SET2_REG; /*!< (@ 0x00000108) SRC coefficient 5,4 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF4 : 16; /*!< [15..0] coefficient 4 */ + __IOM uint32_t SRC_COEF5 : 16; /*!< [31..16] coefficient 5 */ + } APU_SRC_COEF54_SET2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF76_SET2_REG; /*!< (@ 0x0000010C) SRC coefficient 7,6 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF6 : 16; /*!< [15..0] coefficient 6 */ + __IOM uint32_t SRC_COEF7 : 16; /*!< [31..16] coefficient 7 */ + } APU_SRC_COEF76_SET2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF98_SET2_REG; /*!< (@ 0x00000110) SRC coefficient 9,8 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF8 : 16; /*!< [15..0] coefficient 8 */ + __IOM uint32_t SRC_COEF9 : 16; /*!< [31..16] coefficient 9 */ + } APU_SRC_COEF98_SET2_REG_b; + }; + + union + { + __IOM uint32_t APU_SRC_COEF0A_SET2_REG; /*!< (@ 0x00000114) SRC coefficient 10 set 2 */ + + struct + { + __IOM uint32_t SRC_COEF10 : 16; /*!< [15..0] coefficient 10 */ + uint32_t : 16; + } APU_SRC_COEF0A_SET2_REG_b; + }; +} SRC_IF_Type; /*!< Size = 280 (0x118) */ + +/* =========================================================================================================================== */ +/* ================ SYS_WDOG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SYS_WDOG registers (SYS_WDOG) + */ + +typedef struct /*!< (@ 0x400C0700) SYS_WDOG Structure */ +{ + union + { + __IOM uint32_t WATCHDOG_REG; /*!< (@ 0x00000000) Watchdog timer register. */ + + struct + { + __IOM uint32_t WDOG_VAL : 13; /*!< [12..0] Write: Watchdog timer reload value. Note that all bits + * [31-14] must be 0 to reload this register.Read: Actual + * Watchdog timer value. Decremented by 1 every ~10 ms (RC32K) + * or ~29 ms (RCX), the Watchdog timer clock tick.Bit 13 indicates + * a negative counter value. 2, 1, 0, 3FFF16, 3FFE16 and so + * forth. An NMI or WDOG (SYS) reset is generated under the + * following conditions:If WATCHDOG_CTRL_REG[NMI_RST] = 0 + * then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if + * WDOG_VAL =3FF016 -> WDOG res */ + __IOM uint32_t WDOG_VAL_NEG : 1; /*!< [13..13] 0 = Watchdog timer value is positive.1 = Watchdog timer + * value is negative. */ + __OM uint32_t WDOG_WEN : 18; /*!< [31..14] If Bit [31:14] = 0, then write enable for Watchdog + * timer, else write disable.This filter prevents unintentional + * presetting the watchdog with a software runaway. */ + } WATCHDOG_REG_b; + }; + + union + { + __IOM uint32_t WATCHDOG_CTRL_REG; /*!< (@ 0x00000004) WATCHDOG_CTRL_REG */ + + struct + { + __IOM uint32_t NMI_RST : 1; /*!< [0..0] 0 = Watchdog timer generates NMI at value 0, and WDOG + * (SYS) reset at <= -16. Timer can be frozen/resumed using + * SET_FREEZE_REG[FRZ_WDOG] / RESET_FREEZE_REG[FRZ_WDOG].1 + * = Watchdog timer generates a WDOG (SYS) reset at value + * 0 and cannot be frozen by Software.Note that this bit can + * only be set to 1 by SW and only be reset with a WDOG (SYS) + * reset or SW reset.The watchdog is always frozen when the + * Cortex-M33 is halted in DEBUG state */ + uint32_t : 1; + __IOM uint32_t WDOG_FREEZE_EN : 1; /*!< [2..2] 0 = Watchdog timer cannot be frozen when NMI_RST = 01 + * = Watchdog timer can be frozen / resumed using SET_FREEZE_REG[FRZ_WDOG] + * / RESET_FREEZE_REG[FRZ_WDOG] when NMI_RST = 0. */ + __IM uint32_t WRITE_BUSY : 1; /*!< [3..3] 0 = A new WATCHDOG_REG[WDOG_VAL] can be written.1 = No + * new WATCHDOG_REG[WDOG_VAL] can be written.Note : It takes + * some time before the programmed WDOG_VAL is updated in + * the (independent) Watchdog timer. During this time, it + * is not possible to write a new value to WATCHDOG_REG[WDOG_VAL]. */ + uint32_t : 28; + } WATCHDOG_CTRL_REG_b; + }; +} SYS_WDOG_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SYSBUS registers (SYSBUS) + */ + +typedef struct /*!< (@ 0x2F000000) SYSBUS Structure */ +{ + union + { + __IOM uint32_t AHB_DMA_PL1_REG; /*!< (@ 0x00000000) AHB-DMA layer priority level RFMON */ + + struct + { + __IOM uint32_t AHB_DMA_PL1 : 4; /*!< [3..0] Arbitration priority for master RFMON.0 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL1_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL2_REG; /*!< (@ 0x00000004) AHB-DMA layer priority level GEN-DMA */ + + struct + { + __IOM uint32_t AHB_DMA_PL2 : 4; /*!< [3..0] Arbitration priority for master GEN-DMA.0 : disables + * the master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL2_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL3_REG; /*!< (@ 0x00000008) AHB-DMA layer priority level kDMA */ + + struct + { + __IOM uint32_t AHB_DMA_PL3 : 4; /*!< [3..0] Arbitration priority for master kDMA.0 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL3_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL4_REG; /*!< (@ 0x0000000C) AHB-DMA layer priority level SDIO_M */ + + struct + { + __IOM uint32_t AHB_DMA_PL4 : 4; /*!< [3..0] Arbitration priority for master SDIO.0 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL4_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL5_REG; /*!< (@ 0x00000010) AHB-DMA layer priority level SDeMMC_M */ + + struct + { + __IOM uint32_t AHB_DMA_PL5 : 4; /*!< [3..0] Arbitration priority for master SDeMMC.0 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL5_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL6_REG; /*!< (@ 0x00000014) AHB-DMA layer Priority level CC312_M */ + + struct + { + __IOM uint32_t AHB_DMA_PL6 : 4; /*!< [3..0] Arbitration priority for master CC3120 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL6_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_PL7_REG; /*!< (@ 0x00000018) AHB-DMA layer Priority level CPU-S to AHB_DMA + * arbiter registers */ + + struct + { + __IOM uint32_t AHB_DMA_PL7 : 4; /*!< [3..0] Arbitration priority for master CPU-S.0 : disables the + * master1 : lowest ... 15: highest */ + uint32_t : 28; + } AHB_DMA_PL7_REG_b; + }; + __IM uint32_t RESERVED[11]; + + union + { + __IOM uint32_t AHB_DMA_DFLT_MASTER_REG; /*!< (@ 0x00000048) Default master ID number (AHB DMA layer only) */ + + struct + { + __IOM uint32_t AHB_DMA_DFLT_MASTER : 4; /*!< [3..0] Default master ID number register. The default master + * is the master that is granted by the bus when no master + * has requested ownership.0: Dummy master1: RFMON2: GP-DMA3: + * kDMA4: CPU-S */ + uint32_t : 28; + } AHB_DMA_DFLT_MASTER_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_WTEN_REG; /*!< (@ 0x0000004C) Weighted-Token Arbitration Scheme Enable (AHB + * DMA layer only) */ + + struct + { + __IOM uint32_t AHB_DMA_WTEN : 1; /*!< [0..0] Weighted-token arbitration scheme enable. */ + uint32_t : 31; + } AHB_DMA_WTEN_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_TCL_REG; /*!< (@ 0x00000050) Master clock refresh period (AHB DMA layer only) */ + + struct + { + __IOM uint32_t AHB_DMA_TCL : 16; /*!< [15..0] Master clock refresh period, counting clock cycles. + * An arbitration period is defined over this number of tokens. + * When a new arbitration period starts, the master counters + * are reloaded. Recommended value is the sum of the AHB_DMA_CCLMx_REG + * valuesplus 2 tokens for each master. */ + uint32_t : 16; + } AHB_DMA_TCL_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM1_REG; /*!< (@ 0x00000054) RFMON Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Number of tokens (counted in AHB clock cycles) that + * a master can use on the bus before it has to arbitrate + * on a bus master with low priority and having tokens. Masters + * with tokens remaining have priority over masters that have + * used all of their tokens. User should configure all the + * token values ensuring that the sum does not exceeds the + * total allocated number of tokens. If a value of zero is + * configured, then the bus is deemed to have infinite tokens + * and will always operate in the upper-tier of arbitratio */ + uint32_t : 16; + } AHB_DMA_CCLM1_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM2_REG; /*!< (@ 0x00000058) GEN-DMA Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM2_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM3_REG; /*!< (@ 0x0000005C) kDMA Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM3_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM4_REG; /*!< (@ 0x00000060) SDIO Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM4_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM5_REG; /*!< (@ 0x00000064) SDeMMC Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM5_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM6_REG; /*!< (@ 0x00000068) CPU-S Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM6_REG_b; + }; + + union + { + __IOM uint32_t AHB_DMA_CCLM7_REG; /*!< (@ 0x0000006C) CPU-S Master clock tokens */ + + struct + { + __IOM uint32_t AHB_DMA_CCLM : 16; /*!< [15..0] Refer to AHB_DMA_CCLM1_REG */ + uint32_t : 16; + } AHB_DMA_CCLM7_REG_b; + }; + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t AHB_DMA_VERSION_REG; /*!< (@ 0x00000090) Version ID (AHB DMA layer only) */ + + struct + { + __IM uint32_t AHB_DMA_VERSION : 32; /*!< [31..0] AHB_DMA_VERSION */ + } AHB_DMA_VERSION_REG_b; + }; +} SYSBUS_Type; /*!< Size = 148 (0x94) */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS_ICM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SYSBUS_ICM registers (SYSBUS_ICM) + */ + +typedef struct /*!< (@ 0x40070400) SYSBUS_ICM Structure */ +{ + union + { + __IOM uint32_t QSPIRAM_ARB_REG; /*!< (@ 0x00000000) QSPIRAM ICM Priority level */ + + struct + { + __IOM uint32_t QSPIRAM_AHB_DMA_PRIO : 1; /*!< [0..0] priority AHB DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t QSPIRAM_AHB_CPUS_PRIO : 1; /*!< [1..1] priority AHB CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } QSPIRAM_ARB_REG_b; + }; + + union + { + __IOM uint32_t AHBSYS_ARB_REG; /*!< (@ 0x00000004) AHBSYS Peri ICM Priority level */ + + struct + { + __IOM uint32_t AHBSYS_AHB_DMA_PRIO : 1; /*!< [0..0] priority AHB DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t AHBSYS_AHB_CPUS_PRIO : 1; /*!< [1..1] priority AHB CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } AHBSYS_ARB_REG_b; + }; + + union + { + __IOM uint32_t OTP_ARB_REG; /*!< (@ 0x00000008) OTP ICM Priority level */ + + struct + { + __IOM uint32_t OTP_AHB_CPUS_PRIO : 1; /*!< [0..0] priorityAHB_CPUS layer system bus0x0 : Highest priority0x1 + * : Second prority */ + __IOM uint32_t OTP_AHB_DMA_PRIO : 1; /*!< [1..1] priority AHB_DMA layer system bus0x0 : Highest priority0x1 + * : Second prority */ + uint32_t : 30; + } OTP_ARB_REG_b; + }; +} SYSBUS_ICM_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ TDES ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TDES registers (TDES) + */ + +typedef struct /*!< (@ 0x40030000) TDES Structure */ +{ + union + { + __IOM uint32_t TDES_CBC_CTRL_REG; /*!< (@ 0x00000000) CTRL_REG */ + + struct + { + __IOM uint32_t TDES_CBC_ED_SEL : 1; /*!< [0..0] 3DES enc/dec selection1: encryption0: decryption */ + __IOM uint32_t TDES_CBC_IRQ_EN : 1; /*!< [1..1] irq enable */ + uint32_t : 6; + __IOM uint32_t TDES_CBC_START : 1; /*!< [8..8] calculate start */ + uint32_t : 7; + __IOM uint32_t TDES_CBC_FIRST : 1; /*!< [16..16] CBC First */ + uint32_t : 7; + __IM uint32_t TDES_CBC_DONE : 1; /*!< [24..24] 3DES Done */ + uint32_t : 7; + } TDES_CBC_CTRL_REG_b; + }; + + union + { + __IOM uint32_t CBC_IV_0_REG; /*!< (@ 0x00000004) Initial Vector [ 0:31] */ + + struct + { + __IOM uint32_t CBC_IV_0 : 32; /*!< [31..0] Initial Vector [ 0:31] */ + } CBC_IV_0_REG_b; + }; + + union + { + __IOM uint32_t CBC_IV_1_REG; /*!< (@ 0x00000008) Initial Vector [32:63] */ + + struct + { + __IOM uint32_t CBC_IV_1 : 32; /*!< [31..0] Initial Vector [32:63] */ + } CBC_IV_1_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY1_0_REG; /*!< (@ 0x0000000C) key1 [ 0:31] */ + + struct + { + __IOM uint32_t TDES_KEY1_0 : 32; /*!< [31..0] key1 [ 0:31] */ + } TDES_KEY1_0_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY1_1_REG; /*!< (@ 0x00000010) key1 [32:63] */ + + struct + { + __IOM uint32_t TDES_KEY1_1 : 32; /*!< [31..0] key1 [32:63] */ + } TDES_KEY1_1_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY2_0_REG; /*!< (@ 0x00000014) key2 [ 0:31] */ + + struct + { + __IOM uint32_t TDES_KEY2_0 : 32; /*!< [31..0] key2 [ 0:31] */ + } TDES_KEY2_0_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY2_1_REG; /*!< (@ 0x00000018) key2 [32:63] */ + + struct + { + __IOM uint32_t TDES_KEY2_1 : 32; /*!< [31..0] key2 [32:63] */ + } TDES_KEY2_1_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY3_0_REG; /*!< (@ 0x0000001C) key3 [ 0:31] */ + + struct + { + __IOM uint32_t TDES_KEY3_0 : 32; /*!< [31..0] key3 [ 0:31] */ + } TDES_KEY3_0_REG_b; + }; + + union + { + __IOM uint32_t TDES_KEY3_1_REG; /*!< (@ 0x00000020) key3 [32:63] */ + + struct + { + __IOM uint32_t TDES_KEY3_1 : 32; /*!< [31..0] key3 [32:63] */ + } TDES_KEY3_1_REG_b; + }; + + union + { + __IOM uint32_t TDES_INPUT_0_REG; /*!< (@ 0x00000024) Input Text [ 0:31] */ + + struct + { + __IOM uint32_t TDES_INPUT_0 : 32; /*!< [31..0] Input Text [ 0:31] */ + } TDES_INPUT_0_REG_b; + }; + + union + { + __IOM uint32_t TDES_INPUT_1_REG; /*!< (@ 0x00000028) Input Text [32:63] */ + + struct + { + __IOM uint32_t TDES_INPUT_1 : 32; /*!< [31..0] Input Text [32:63] */ + } TDES_INPUT_1_REG_b; + }; + + union + { + __IOM uint32_t TDES_OUTPUT_0_REG; /*!< (@ 0x0000002C) Output Text [ 0:31] */ + + struct + { + __IM uint32_t TDES_OUTPUT_0 : 32; /*!< [31..0] Output Text [ 0:31] */ + } TDES_OUTPUT_0_REG_b; + }; + + union + { + __IOM uint32_t TDES_OUTPUT_1_REG; /*!< (@ 0x00000030) Output Text [32:63] */ + + struct + { + __IM uint32_t TDES_OUTPUT_1 : 32; /*!< [31..0] Output Text [32:63] */ + } TDES_OUTPUT_1_REG_b; + }; +} TDES_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER registers (TIMER) + */ + +typedef struct /*!< (@ 0x40080000) TIMER Structure */ +{ + union + { + __IOM uint32_t TIMER_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable1 = On0 = Off */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode1 = One shot enabled0 = Counter enabled */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction1 = down0 = upNOTE: only change + * counter direction when timer is not enabled */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask1 = timer IRQ is unmasked0 = timer IRQ + * is masked */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Select clock1 = Timer uses the DIVN clock0 = Timer uses + * the lp clockNOTE: when switching clock, the timer clock + * should be disabled (TIM_CLK_EN, bit 8) */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable1 = clock enabled0 = clock disabled */ + __IOM uint32_t TIM_IN3_EVENT_FALL_EN : 1; /*!< [9..9] Event input 3 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IN4_EVENT_FALL_EN : 1; /*!< [10..10] Event input 4 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_CAP_GPIO1_IRQ_EN : 1; /*!< [11..11] 0 = Event on GPIO1 does not create a CAPTIM interrrupt1 + * = Event on GPIO1 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO2_IRQ_EN : 1; /*!< [12..12] 0 = Event on GPIO2 does not create a CAPTIM interrrupt1 + * = Event on GPIO2 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO3_IRQ_EN : 1; /*!< [13..13] 0 = Event on GPIO3 does not create a CAPTIM interrrupt1 + * = Event on GPIO3 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO4_IRQ_EN : 1; /*!< [14..14] 0 = Event on GPIO4 does not create a CAPTIM interrrupt1 + * = Event on GPIO4 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_ONESHOT_TRIGGER : 2; /*!< [16..15] Oneshot trigger source00: Select external GPIO as the + * trigger for one shot01: Select a register write as the + * trigger of one shot10: Either of the two triggers one shot11: + * None of the two triggers one shot */ + __IOM uint32_t TIM_ONESHOT_SWITCH : 1; /*!< [17..17] Automatically switch after the completion of the pulse + * output without the CPU programming anything.0: No automated + * switch from OneShot to Counter mode1: Automated switch + * from OneShot to Counter mode and start counting down. In + * case no start value has been programmed (reload=0), the + * timer keeps generating interrupts until the timer clock + * is disabled */ + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Enable edge detection counter.NOTE: In sleep only 80Mhz + * can be reached at 900 mV */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Select on which edge the edge detection should react;0: + * the counter is triggered on a rising edge1: the counter + * is triggered on a falling edgeNOTE: Only change this when + * EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG */ + __IOM uint32_t TIM_SINGLE_EVENT_CAPTURE : 1; /*!< [20..20] When this bit is set, only the first event on captimer1 + * is captured */ + uint32_t : 11; + } TIMER_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE : 32; /*!< [31..0] Gives the current timer value */ + } TIMER_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2 */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1 */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase0 = Wait for event1 = Delay phase2 = Start + * Shot3 = Shot phase */ + __IM uint32_t TIM_GPIO1_EVENT_PENDING : 1; /*!< [4..4] When 1, GPIO1 event is pending. */ + __IM uint32_t TIM_GPIO2_EVENT_PENDING : 1; /*!< [5..5] When 1, GPIO2 event is pending. */ + __IM uint32_t TIM_GPIO3_EVENT_PENDING : 1; /*!< [6..6] When 1, GPIO3 event is pending. */ + __IM uint32_t TIM_GPIO4_EVENT_PENDING : 1; /*!< [7..7] When 1, GPIO4 event is pending. */ + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an irq has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock has been switched to divn + * clock */ + __IM uint32_t TIM_IN3_STATE : 1; /*!< [12..12] Gives the logic level of the IN3 */ + __IM uint32_t TIM_IN4_STATE : 1; /*!< [13..13] Gives the logic level of the IN4 */ + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the theshold value, this bit is 1 */ + __IM uint32_t TIM_CAPTIM_DETECTED : 1; /*!< [15..15] Indicates that a single event is detected when SINGLE_EVENT_CAPTURE + * is set to 1. Every next event will not update the capture + * timer register */ + uint32_t : 16; + } TIMER_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER_SETTINGS_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in timer mode, Delay phase duration + * in oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles) */ + } TIMER_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in oneshot mode */ + } TIMER_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer reload value and Delay in shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency / + * (TIM_PRESCALER+1) */ + uint32_t : 27; + } TIMER_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the Capture time for event on GPIO1 */ + } TIMER_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the Capture time for event on GPIO2 */ + } TIMER_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value */ + uint32_t : 27; + } TIMER_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)Tim + * r clock is clock after prescaler */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1) */ + } TIMER_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer pulse counter ctrl register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * Valid values 0-32.0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17 */ + uint32_t : 26; + } TIMER_PULSE_GPIO_SEL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_GPIO3_CONF_REG; /*!< (@ 0x00000034) Timer gpio3 selection */ + + struct + { + __IOM uint32_t TIM_GPIO3_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN3, Valid value 0-32. + * 1 for the first gpio, 32 for the last gpio.0: Disable input1: + * P0_002: P0_013: P0_024: P0_035: P0_046: P0_057: P0_068: + * P0_079: P0_0810: P0_0911: P0_1012: P0_1113: P0_1214: P0_1315: + * P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: P1_0521: P1_0622: + * P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: P1_1228: P1_1329: + * P1_1430: P1_1531: P1_1 */ + uint32_t : 26; + } TIMER_GPIO3_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER_GPIO4_CONF_REG; /*!< (@ 0x00000038) Timer gpio4 selection */ + + struct + { + __IOM uint32_t TIM_GPIO4_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN4, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER_GPIO4_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CAPTURE_GPIO3_REG; /*!< (@ 0x0000003C) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO32 : 32; /*!< [31..0] Gives the Capture time for event on GPIO3 */ + } TIMER_CAPTURE_GPIO3_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CAPTURE_GPIO4_REG; /*!< (@ 0x00000040) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO42 : 32; /*!< [31..0] Gives the Capture time for event on GPIO4 */ + } TIMER_CAPTURE_GPIO4_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer pulse counter ctrl register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an irq is fired for the + * pulse counter n-2.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG */ + } TIMER_PULSE_CNT_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER_ONESHOT_TRIGGER_REG; /*!< (@ 0x00000048) Timer oneshot trigger register */ + + struct + { + __OM uint32_t TIM_ONESHOT_TRIGGER_SW : 1; /*!< [0..0] trigger oneshot */ + uint32_t : 31; + } TIMER_ONESHOT_TRIGGER_REG_b; + }; + + union + { + __IOM uint32_t TIMER_PWM_SYNC_REG; /*!< (@ 0x0000004C) Timer pwm synchronisation register */ + + struct + { + __IOM uint32_t PWM_START : 1; /*!< [0..0] Start PWM of the selected timers */ + __IOM uint32_t SYNC_ENABLE : 1; /*!< [1..1] Enable PWM start synchronisation of the selected timers */ + __IOM uint32_t TIMER_SYNC : 1; /*!< [2..2] Enable PWM synchronisation of timer */ + __IOM uint32_t TIMER2_SYNC : 1; /*!< [3..3] Enable PWM start synchronisation of timer2 */ + __IOM uint32_t TIMER3_SYNC : 1; /*!< [4..4] Enable PWM start synchronisation of timer3 */ + __IOM uint32_t TIMER4_SYNC : 1; /*!< [5..5] Enable PWM start synchronisation of timer4 */ + __IOM uint32_t TIMER6_SYNC : 1; /*!< [6..6] Enable PWM start synchronisation of timer6 */ + uint32_t : 25; + } TIMER_PWM_SYNC_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CLEAR_GPIO_EVENT_REG; /*!< (@ 0x00000050) Timer clear gpio event register */ + + struct + { + __OM uint32_t TIM_CLEAR_GPIO1_EVENT : 1; /*!< [0..0] 1 = Clear GPIO1 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO2_EVENT : 1; /*!< [1..1] 1 = Clear GPIO2 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO3_EVENT : 1; /*!< [2..2] 1 = Clear GPIO3 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO4_EVENT : 1; /*!< [3..3] 1 = Clear GPIO4 event. Return always 0 */ + uint32_t : 28; + } TIMER_CLEAR_GPIO_EVENT_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer clear interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value clear interrupt */ + uint32_t : 31; + } TIMER_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer clear pulse interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value will clear irq pulse interrupt */ + uint32_t : 31; + } TIMER_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER2 registers (TIMER2) + */ + +typedef struct /*!< (@ 0x40080100) TIMER2 Structure */ +{ + union + { + __IOM uint32_t TIMER2_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER2_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER2_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER2_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER2_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER2_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER2_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER2_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER2_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER2_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER2_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER2_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER2_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER2_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER2_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER2_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER2_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER2_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER2_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER2_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER2_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER3 registers (TIMER3) + */ + +typedef struct /*!< (@ 0x40080200) TIMER3 Structure */ +{ + union + { + __IOM uint32_t TIMER3_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER3_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER3_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER3_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER3_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER3_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER3_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER3_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER3_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER3_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER3_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER3_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER3_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER3_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER3_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER3_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER3_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER3_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER3_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER3_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER3_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER4 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER4 registers (TIMER4) + */ + +typedef struct /*!< (@ 0x40080300) TIMER4 Structure */ +{ + union + { + __IOM uint32_t TIMER4_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER4_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER4_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER4_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER4_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER4_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER4_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER4_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER4_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER4_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER4_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER4_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER4_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER4_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER4_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER4_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER4_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER4_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER4_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER4_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER4_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER5 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER5 registers (TIMER5) + */ + +typedef struct /*!< (@ 0x40080400) TIMER5 Structure */ +{ + union + { + __IOM uint32_t TIMER5_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable1 = On0 = Off */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode1 = One shot enabled0 = Counter enabled */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction1 = down0 = upNOTE: only change + * counter direction when timer is not enabled */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask1 = timer IRQ is unmasked0 = timer IRQ + * is masked */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Select clock1 = Timer uses the DIVN clock0 = Timer uses + * the lp clockNOTE: when switching clock, the timer clock + * should be disabled (TIM_CLK_EN, bit 8) */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable1 = clock enabled0 = clock disabled */ + __IOM uint32_t TIM_IN3_EVENT_FALL_EN : 1; /*!< [9..9] Event input 3 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_IN4_EVENT_FALL_EN : 1; /*!< [10..10] Event input 4 edge type1 = falling edge0 = rising edge */ + __IOM uint32_t TIM_CAP_GPIO1_IRQ_EN : 1; /*!< [11..11] 0 = Event on GPIO1 does not create a CAPTIM interrrupt1 + * = Event on GPIO1 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO2_IRQ_EN : 1; /*!< [12..12] 0 = Event on GPIO2 does not create a CAPTIM interrrupt1 + * = Event on GPIO2 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO3_IRQ_EN : 1; /*!< [13..13] 0 = Event on GPIO3 does not create a CAPTIM interrrupt1 + * = Event on GPIO3 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_CAP_GPIO4_IRQ_EN : 1; /*!< [14..14] 0 = Event on GPIO4 does not create a CAPTIM interrrupt1 + * = Event on GPIO4 creates a CAPTIM interrrupt */ + __IOM uint32_t TIM_ONESHOT_TRIGGER : 2; /*!< [16..15] Oneshot trigger source00: Select external GPIO as the + * trigger for one shot01: Select a register write as the + * trigger of one shot10: Either of the two triggers one shot11: + * None of the two triggers one shot */ + __IOM uint32_t TIM_ONESHOT_SWITCH : 1; /*!< [17..17] Automatically switch after the completion of the pulse + * output without the CPU programming anything.0: No automated + * switch from OneShot to Counter mode1: Automated switch + * from OneShot to Counter mode and start counting down. In + * case no start value has been programmed (reload=0), the + * timer keeps generating interrupts until the timer clock + * is disabled */ + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Enable edge detection counter.NOTE: In sleep only 80Mhz + * can be reached at 900 mV */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Select on which edge the edge detection should react;0: + * the counter is triggered on a rising edge1: the counter + * is triggered on a falling edgeNOTE: Only change this when + * EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG */ + __IOM uint32_t TIM_SINGLE_EVENT_CAPTURE : 1; /*!< [20..20] When this bit is set, only the first event on captimer1 + * is captured */ + uint32_t : 11; + } TIMER5_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE : 32; /*!< [31..0] Gives the current timer value */ + } TIMER5_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2 */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1 */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase0 = Wait for event1 = Delay phase2 = Start + * Shot3 = Shot phase */ + __IM uint32_t TIM_GPIO1_EVENT_PENDING : 1; /*!< [4..4] When 1, GPIO1 event is pending. */ + __IM uint32_t TIM_GPIO2_EVENT_PENDING : 1; /*!< [5..5] When 1, GPIO2 event is pending. */ + __IM uint32_t TIM_GPIO3_EVENT_PENDING : 1; /*!< [6..6] When 1, GPIO3 event is pending. */ + __IM uint32_t TIM_GPIO4_EVENT_PENDING : 1; /*!< [7..7] When 1, GPIO4 event is pending. */ + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an irq has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock has been switched to divn + * clock */ + __IM uint32_t TIM_IN3_STATE : 1; /*!< [12..12] Gives the logic level of the IN3 */ + __IM uint32_t TIM_IN4_STATE : 1; /*!< [13..13] Gives the logic level of the IN4 */ + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the theshold value, this bit is 1 */ + __IM uint32_t TIM_CAPTIM_DETECTED : 1; /*!< [15..15] Indicates that a single event is detected when SINGLE_EVENT_CAPTURE + * is set to 1. Every next event will not update the capture + * timer register */ + uint32_t : 16; + } TIMER5_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER5_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER5_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_SETTINGS_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in timer mode, Delay phase duration + * in oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles) */ + } TIMER5_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in oneshot mode */ + } TIMER5_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer reload value and Delay in shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency / + * (TIM_PRESCALER+1) */ + uint32_t : 27; + } TIMER5_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the Capture time for event on GPIO1 */ + } TIMER5_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the Capture time for event on GPIO2 */ + } TIMER5_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value */ + uint32_t : 27; + } TIMER5_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)Tim + * r clock is clock after prescaler */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1) */ + } TIMER5_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer pulse counter ctrl register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * Valid values 0-32.0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17 */ + uint32_t : 26; + } TIMER5_PULSE_GPIO_SEL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_GPIO3_CONF_REG; /*!< (@ 0x00000034) Timer gpio3 selection */ + + struct + { + __IOM uint32_t TIM_GPIO3_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN3, Valid value 0-32. + * 1 for the first gpio, 32 for the last gpio.0: Disable input1: + * P0_002: P0_013: P0_024: P0_035: P0_046: P0_057: P0_068: + * P0_079: P0_0810: P0_0911: P0_1012: P0_1113: P0_1214: P0_1315: + * P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: P1_0521: P1_0622: + * P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: P1_1228: P1_1329: + * P1_1430: P1_1531: P1_1 */ + uint32_t : 26; + } TIMER5_GPIO3_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_GPIO4_CONF_REG; /*!< (@ 0x00000038) Timer gpio4 selection */ + + struct + { + __IOM uint32_t TIM_GPIO4_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN4, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER5_GPIO4_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CAPTURE_GPIO3_REG; /*!< (@ 0x0000003C) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO32 : 32; /*!< [31..0] Gives the Capture time for event on GPIO3 */ + } TIMER5_CAPTURE_GPIO3_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CAPTURE_GPIO4_REG; /*!< (@ 0x00000040) Timer value for event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO42 : 32; /*!< [31..0] Gives the Capture time for event on GPIO4 */ + } TIMER5_CAPTURE_GPIO4_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer pulse counter ctrl register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an irq is fired for the + * pulse counter n-2.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG */ + } TIMER5_PULSE_CNT_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_ONESHOT_TRIGGER_REG; /*!< (@ 0x00000048) Timer oneshot trigger register */ + + struct + { + __OM uint32_t TIM_ONESHOT_TRIGGER_SW : 1; /*!< [0..0] trigger oneshot */ + uint32_t : 31; + } TIMER5_ONESHOT_TRIGGER_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_PWM_SYNC_REG; /*!< (@ 0x0000004C) Timer pwm synchronisation register */ + + struct + { + __IOM uint32_t PWM_START : 1; /*!< [0..0] Start PWM of the selected timers */ + __IOM uint32_t SYNC_ENABLE : 1; /*!< [1..1] Enable PWM start synchronisation of the selected timers */ + __IOM uint32_t TIMER_SYNC : 1; /*!< [2..2] Enable PWM synchronisation of timer */ + __IOM uint32_t TIMER2_SYNC : 1; /*!< [3..3] Enable PWM start synchronisation of timer2 */ + __IOM uint32_t TIMER3_SYNC : 1; /*!< [4..4] Enable PWM start synchronisation of timer3 */ + __IOM uint32_t TIMER4_SYNC : 1; /*!< [5..5] Enable PWM start synchronisation of timer4 */ + __IOM uint32_t TIMER6_SYNC : 1; /*!< [6..6] Enable PWM start synchronisation of timer6 */ + uint32_t : 25; + } TIMER5_PWM_SYNC_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CLEAR_GPIO_EVENT_REG; /*!< (@ 0x00000050) Timer clear gpio event register */ + + struct + { + __OM uint32_t TIM_CLEAR_GPIO1_EVENT : 1; /*!< [0..0] 1 = Clear GPIO1 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO2_EVENT : 1; /*!< [1..1] 1 = Clear GPIO2 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO3_EVENT : 1; /*!< [2..2] 1 = Clear GPIO3 event. Return always 0 */ + __OM uint32_t TIM_CLEAR_GPIO4_EVENT : 1; /*!< [3..3] 1 = Clear GPIO4 event. Return always 0 */ + uint32_t : 28; + } TIMER5_CLEAR_GPIO_EVENT_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer clear interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value clear interrupt */ + uint32_t : 31; + } TIMER5_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER5_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer clear pulse interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value will clear irq pulse interrupt */ + uint32_t : 31; + } TIMER5_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER5_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER6 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER6 registers (TIMER6) + */ + +typedef struct /*!< (@ 0x40080500) TIMER6 Structure */ +{ + union + { + __IOM uint32_t TIMER6_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER6_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER6_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER6_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER6_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER6_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER6_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER6_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER6_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER6_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER6_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER6_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER6_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER6_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER6_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER6_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER6_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER6_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER6_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER6_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER6_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER7 registers (TIMER7) + */ + +typedef struct /*!< (@ 0x40080600) TIMER7 Structure */ +{ + union + { + __IOM uint32_t TIMER7_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER7_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER7_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER7_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER7_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER7_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER7_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER7_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER7_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER7_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER7_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER7_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER7_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER7_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER7_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER7_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER7_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER7_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER7_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER7_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER7_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ TIMER8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TIMER8 registers (TIMER8) + */ + +typedef struct /*!< (@ 0x40080700) TIMER8 Structure */ +{ + union + { + __IOM uint32_t TIMER8_CTRL_REG; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint32_t TIM_EN : 1; /*!< [0..0] Timer enable:0: Off1: On */ + __IOM uint32_t TIM_ONESHOT_MODE_EN : 1; /*!< [1..1] Timer mode:0: Counter is enabled.1: One shot is enabled. */ + __IOM uint32_t TIM_COUNT_DOWN_EN : 1; /*!< [2..2] Timer count direction:0: Up1: DownNOTE: Only change this + * bit when timer is disabled. */ + __IOM uint32_t TIM_IN1_EVENT_FALL_EN : 1; /*!< [3..3] Event input 1 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IN2_EVENT_FALL_EN : 1; /*!< [4..4] Event input 2 edge selection:0: Rising edge1: Falling + * edge */ + __IOM uint32_t TIM_IRQ_EN : 1; /*!< [5..5] Interrupt mask:0: Timer IRQ is disable.1: Timer IRQ is + * enable. */ + __IOM uint32_t TIM_FREE_RUN_MODE_EN : 1; /*!< [6..6] Valid when timer counts up, if it is '1' timer does not + * zero when reaches to reload value. it becomes zero only + * when it reaches the max value. */ + __IOM uint32_t TIM_SYS_CLK_EN : 1; /*!< [7..7] Timer clock selection:0: LP_CLK clock1: DIVN clockNOTE: + * When switching clock, the timer clock should be disabled + * (TIM_CLK_EN, bit 8). */ + __IOM uint32_t TIM_CLK_EN : 1; /*!< [8..8] Timer clock enable:0: Clock is disabled.1: Clock is enabled. */ + uint32_t : 9; + __IOM uint32_t TIM_EDGE_DET_CNT_EN : 1; /*!< [18..18] Edge detection counter:0: Disable1: Enable */ + __IOM uint32_t TIM_EDGE_DET_CNT_FALL_EN : 1; /*!< [19..19] Counter trigger edge selection:0: the counter is triggered + * on a rising edge.1: the counter is triggered on a falling + * edge.NOTE: Only change this when EDGE_DET_CNT_EN=0 in TIMER_CTRL_REG. */ + uint32_t : 12; + } TIMER8_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer Counter Value */ + + struct + { + __IM uint32_t TIM_TIMER_VALUE2 : 32; /*!< [31..0] Gives the current timer value. */ + } TIMER8_TIMER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_STATUS_REG; /*!< (@ 0x00000008) Timer Status Register */ + + struct + { + __IM uint32_t TIM_IN1_STATE : 1; /*!< [0..0] Gives the logic level of the IN2. */ + __IM uint32_t TIM_IN2_STATE : 1; /*!< [1..1] Gives the logic level of the IN1. */ + __IM uint32_t TIM_ONESHOT_PHASE : 2; /*!< [3..2] OneShot phase:0: Wait for event.1: Delay phase.2: Start + * Shot.3: Shot phase. */ + uint32_t : 4; + __IM uint32_t TIM_IRQ_STATUS : 1; /*!< [8..8] IRQ status bit. When an IRQ has occured, this bit is + * 1. */ + __IM uint32_t TIM_TIMER_BUSY : 1; /*!< [9..9] Busy with synchronizing PRESCALER_REG, RELOAD_REG and + * SHOTWIDTH_REG. Do not write a new value to these registers + * when this bit is high. */ + __IM uint32_t TIM_PWM_BUSY : 1; /*!< [10..10] Busy with synchronizing PWM_FREQ_REG and PWM_DC_REG. + * Do not write a new value to these registers when this bit + * is high. */ + __IM uint32_t TIM_SWITCHED_TO_DIVN_CLK : 1; /*!< [11..11] Indicates that timer clock is switched to divn clock. */ + uint32_t : 2; + __IM uint32_t TIM_IRQ_PULSE_STATUS : 1; /*!< [14..14] Status bit of IRQ pulse counter. When the pulse counter + * reaches the threshold value, this bit is 1. */ + uint32_t : 17; + } TIMER8_STATUS_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + + struct + { + __IOM uint32_t TIM_GPIO1_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN1, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER8_GPIO1_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + + struct + { + __IOM uint32_t TIM_GPIO2_CONF : 6; /*!< [5..0] Select one of the 32 GPIOs as IN2, Valid values 0-32.0: + * Disable input1: P0_002: P0_013: P0_024: P0_035: P0_046: + * P0_057: P0_068: P0_079: P0_0810: P0_0911: P0_1012: P0_1113: + * P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: P1_0319: P1_0420: + * P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: P1_1026: P1_1127: + * P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: P1_17 */ + uint32_t : 26; + } TIMER8_GPIO2_CONF_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_SETTINGS_REG; /*!< (@ 0x00000014) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_RELOAD2 : 32; /*!< [31..0] Reload or max value in Timer mode; delay phase duration + * in Oneshot mode. Actual delay is the register value plus + * synchronization time (3 clock cycles). */ + } TIMER8_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot Duration in Shot mode */ + + struct + { + __IOM uint32_t TIM_SHOTWIDTH2 : 32; /*!< [31..0] Shot phase duration in Oneshot mode. */ + } TIMER8_SHOTWIDTH_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_PRE_SETTINGS_REG; /*!< (@ 0x0000001C) Timer Reload Value and Delay in Shot mode */ + + struct + { + __IOM uint32_t TIM_PRESCALER2 : 5; /*!< [4..0] Defines the timer count frequency. CLOCK frequency/(TIM_PRESCALER+1). */ + uint32_t : 27; + } TIMER8_PRE_SETTINGS_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer Value for Event on GPIO1 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO12 : 32; /*!< [31..0] Gives the capture time for event on GPIO1. */ + } TIMER8_CAPTURE_GPIO1_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer Value for Event on GPIO2 */ + + struct + { + __IM uint32_t TIM_CAPTURE_GPIO22 : 32; /*!< [31..0] Gives the capture time for event on GPIO2. */ + } TIMER8_CAPTURE_GPIO2_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer Prescaler Counter Value */ + + struct + { + __IM uint32_t TIM_PRESCALER_VAL : 5; /*!< [4..0] Gives the current prescaler counter value. */ + uint32_t : 27; + } TIMER8_PRESCALER_VAL_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_PWM_CTRL_REG; /*!< (@ 0x0000002C) Timer PWM Frequency Register */ + + struct + { + __IOM uint32_t TIM_PWM_FREQ : 16; /*!< [15..0] Defines the PWM frequency. Timer clock frequency/(TIM_PWM_FREQ+1).Time + * clock is the clock after prescaler. */ + __IOM uint32_t TIM_PWM_DC : 16; /*!< [31..16] Defines the PWM duty cycle. TIM_PWM_DC/( TIM_PWM_FREQ+1). */ + } TIMER8_PWM_CTRL_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_PULSE_GPIO_SEL_REG; /*!< (@ 0x00000030) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_GPIO_SEL2 : 6; /*!< [5..0] Select one of the 32 GPIOs as input for the pulse counter, + * valid values 0-32:0: Disable input1: P0_002: P0_013: P0_024: + * P0_035: P0_046: P0_057: P0_068: P0_079: P0_0810: P0_0911: + * P0_1012: P0_1113: P0_1214: P0_1315: P1_0016: P1_0117: P1_0218: + * P1_0319: P1_0420: P1_0521: P1_0622: P1_0723: P1_0824: P1_0925: + * P1_1026: P1_1127: P1_1228: P1_1329: P1_1430: P1_1531: P1_1632: + * P1_17N */ + uint32_t : 26; + } TIMER8_PULSE_GPIO_SEL_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t TIMER8_PULSE_CNT_CTRL_REG; /*!< (@ 0x00000044) Timer Pulse Counter CTRL Register */ + + struct + { + __IOM uint32_t PULSE_CNT_THRESHOLD2 : 32; /*!< [31..0] Select after how many pulses an IRQ is fired for the + * pulse counter.NOTE: Only change this when EDGE_DET_CNT_EN=0 + * in TIMER_CTRL_REG. */ + } TIMER8_PULSE_CNT_CTRL_REG_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t TIMER8_CLEAR_IRQ_REG; /*!< (@ 0x00000054) Timer Clear Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_IRQ : 1; /*!< [0..0] Write any value to clear interrupt. */ + uint32_t : 31; + } TIMER8_CLEAR_IRQ_REG_b; + }; + + union + { + __IOM uint32_t TIMER8_CLEAR_IRQ_PULSE_REG; /*!< (@ 0x00000058) Timer Clear Pulse Interrupt */ + + struct + { + __OM uint32_t TIM_CLEAR_PULSE_IRQ : 1; /*!< [0..0] Write any value to clear IRQ pulse interrupt. */ + uint32_t : 31; + } TIMER8_CLEAR_IRQ_PULSE_REG_b; + }; +} TIMER8_Type; /*!< Size = 92 (0x5c) */ + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/** + * @brief UART registers (UART) + */ + +typedef struct /*!< (@ 0x40000000) UART Structure */ +{ + union + { + __IOM uint32_t UART_DR_REG; /*!< (@ 0x00000000) UART Data Register */ + + struct + { + __IOM uint32_t DR_DATA : 8; /*!< [7..0] Receive (read) data charaterTransmit (write) data character */ + __IOM uint32_t DR_FE : 1; /*!< [8..8] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).In FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t DR_PE : 1; /*!< [9..9] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.In FIFO mode, this error is associated with the + * character at the top of the FIFO. */ + __IOM uint32_t DR_BE : 1; /*!< [10..10] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity and stop bits).In FIFO + * mode, this error is associated with the character at the + * top of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (marking state), + * and the next valid start bit is received. */ + __IOM uint32_t DR_OE : 1; /*!< [11..11] Overrun error. This bit is set to 1 if data is received + * and the receive FIFO is already full.This is cleared to + * 0 once there is an empty space in the FIFO and a new character + * can be written to it. */ + uint32_t : 20; + } UART_DR_REG_b; + }; + + union + { + __IOM uint32_t UART_RSR_REG; /*!< (@ 0x00000004) UART Receive Status (Read), Error Clear (Write) + * Register */ + + struct + { + __IOM uint32_t RSR_FE : 1; /*!< [0..0] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_PE : 1; /*!< [1..1] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_BE : 1; /*!< [2..2] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity, and stop bits).This bit + * is cleared to 0 after a write to the register.In FIFO mode, + * this error is associated with the character at the top + * of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (mark */ + __IOM uint32_t RSR_OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received + * and the FIFO is already full.This bit is cleared to 0 by + * a write to the register.The FIFO contents remain valid + * because no more data is written when the FIFO is full, + * only the contents of the shift register are overwritten. + * The CPU must now read the data, to empty the FIFO. */ + uint32_t : 28; + } UART_RSR_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t UART_FR_REG; /*!< (@ 0x00000018) UART Flag Register */ + + struct + { + __IM uint32_t CTS : 1; /*!< [0..0] Clear to send. This bit is the complement of the UART + * clear to send, nUARTCTS, modem status input.That is, the + * bit is 1 when nUARTCTS is LOW. */ + __IM uint32_t DSR : 1; /*!< [1..1] Data set ready. This bit is the complement of the UART + * data set ready, nUARTDSR, modem status input.That is, the + * bit is 1 when nUARTDSR is LOW. */ + __IM uint32_t DCD : 1; /*!< [2..2] Data carrier detect. This bit is the complement of the + * UART data carrier detect, nUARTDCD, modem status input.That + * is, the bit is 1 when nUARTDCD is LOW. */ + __IM uint32_t BUSY : 1; /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy + * transmitting data. This bit remains set until the complete + * byte, including all the stop bits, has been sent from the + * shift register.This bit is set as soon as the transmit + * FIFO becomes non-empty, regardless of whether the UART + * is enabled or not. */ + __IM uint32_t RXFE : 1; /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is empty.If the FIFO is enabled, the RXFE bit + * is set when the receive FIFO is empty. */ + __IM uint32_t TXFF : 1; /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the transmit holding + * register is full.If the FIFO is enabled, the TXFF bit is + * set when the transmit FIFO is full. */ + __IM uint32_t RXFF : 1; /*!< [6..6] Receive FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is full.If the FIFO is enabled, the RXFF bit is + * set when the receive FIFO is full. */ + __IM uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends + * on the state of the FEN bit in the Line Control Register, + * UARTLCR_HIf the FIFO is disabled, this bit is set when + * the transmit holding register is empty.If the FIFO is enabled, + * the TXFE bit is set when the transmit FIFO is empty.This + * bit does not indicate if there is data in the transmit + * shift register. */ + __IM uint32_t RI : 1; /*!< [8..8] Ring indicator. This bit is the complement of the UART + * ring indicator, nUARTRI, modem status input.That is, the + * bit is 1 when nUARTRI is LOW. */ + uint32_t : 23; + } UART_FR_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t UART_IBRD_REG; /*!< (@ 0x00000024) UART Integer Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVINT : 16; /*!< [15..0] The integer baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 16; + } UART_IBRD_REG_b; + }; + + union + { + __IOM uint32_t UART_FBRD_REG; /*!< (@ 0x00000028) UART Fractional Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVFRAC : 6; /*!< [5..0] The fractional baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 26; + } UART_FBRD_REG_b; + }; + + union + { + __IOM uint32_t UART_LCR_H_REG; /*!< (@ 0x0000002C) UART Line Control Register (High Byte) */ + + struct + { + __IOM uint32_t BRK : 1; /*!< [0..0] Send break. If this bit is set to 1, a low-level is continually + * output on the UARTTXD output, after completing transmission + * of the current character. For the proper execution of the + * break command, the software must set this bit for at least + * two complete frames.For normal use, this bit must be cleared + * to 0. */ + __IOM uint32_t PEN : 1; /*!< [1..1] Parity enable:0 = parity is disabled and no parity bit + * added to the data frame1 = parity checking and generation + * is enabled. */ + __IOM uint32_t EPS : 1; /*!< [2..2] Even parity select. Controls the type of parity the UART + * uses during transmission and reception:0 = odd parity. + * The UART generates or checks for an odd number of 1s in + * the data and parity bits.1 = even parity. The UART generates + * or checks for an even number of 1s in the data and parity + * bits.This bit has no effect when the PEN bit disables parity + * checking and generation. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] Two stop bits select. If this bit is set to 1, two stop + * bits are transmitted at the end of the frame. The receive + * logic does not check for two stop bits being received. */ + __IOM uint32_t FEN : 1; /*!< [4..4] Enable FIFOs:0 = FIFOs are disabled (character mode) + * that is, the FIFOs become 1-byte-deep holding registers1 + * = transmit and receive FIFO buffers are enabled (FIFO mode). */ + __IOM uint32_t WLEN : 2; /*!< [6..5] Word length. These bits indicate the number of data bits + * transmitted or received in a frame as follows:b11 = 8 bitsb10 + * = 7 bitsb01 = 6 bitsb00 = 5 bits. */ + __IOM uint32_t SPS : 1; /*!< [7..7] Stick parity select.0 = stick parity is disabled1 = either:? + * if the EPS bit is 0 then the parity bit is transmitted + * and checked as a 1? if the EPS bit is 1 then the parity + * bit is transmitted and checked as a 0.This bit has no effect + * when the PEN bit disables parity checking and generation. */ + uint32_t : 24; + } UART_LCR_H_REG_b; + }; + + union + { + __IOM uint32_t UART_CR_REG; /*!< (@ 0x00000030) UART Control Register */ + + struct + { + __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable:0 = UART is disabled. If the UART is disabled + * in the middle of transmission or reception, it completes + * the current character before stopping.1 = the UART is enabled. + * Data transmission and reception occurs. */ + uint32_t : 6; + __IOM uint32_t LBE : 1; /*!< [7..7] Loopback enable. If this bit is set to 1, the UARTTXD + * path is fed through to the UARTRXD path.When this bit is + * set, the modem outputs are also fed through to the modem + * inputs.This bit is cleared to 0 on reset, to disable loopback. */ + __IOM uint32_t TXE : 1; /*!< [8..8] Transmit enable. If this bit is set to 1, the transmit + * section of the UART is enabled. */ + __IOM uint32_t RXE : 1; /*!< [9..9] Receive enable. If this bit is set to 1, the receive + * section of the UART is enabled. */ + __IOM uint32_t DTR : 1; /*!< [10..10] Data transmit ready. This bit is the complement of + * the UART data transmit ready, nUARTDTR, modem status output. + * That is, when the bit is programmed to a 1 then nUARTDTR + * is LOW */ + __IOM uint32_t RTS : 1; /*!< [11..11] Request to send. This bit is the complement of the + * UART request to send, nUARTRTS, modem status output. That + * is, when the bit is programmed to a 1 then nUARTRTS is + * LOW */ + __IOM uint32_t Out1 : 1; /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1) + * modem status output. That is, when the bit is programmed + * to a 1 the output is 0. For DTE this can be used as Data + * Carrier Detect (DCD). */ + __IOM uint32_t Out2 : 1; /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2) + * modem status output. That is, when the bit is programmed + * to a 1, the output is 0. For DTE this can be used as Ring + * Indicator (RI). */ + __IOM uint32_t RTSEn : 1; /*!< [14..14] RTS hardware flow control enable. If this bit is set + * to 1, RTS hardware flow control is enabled.Data is only + * requested when there is space in the receive FIFO for it + * to be received. */ + __IOM uint32_t CTSEn : 1; /*!< [15..15] CTS hardware flow control enable. If this bit is set + * to 1, CTS hardware flow control is enabled.Data is only + * transmitted when the nUARTCTS signal is asserted. */ + uint32_t : 16; + } UART_CR_REG_b; + }; + + union + { + __IOM uint32_t UART_IFLS_REG; /*!< (@ 0x00000034) UART Interrupt FIFO Level Select Register */ + + struct + { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] Transmit interrupt FIFO level select. The trigger points + * for the transmit interrupt are as follows:b000 = Transmit + * FIFO becomes 1/8 fullb001 = Transmit FIFO becomes 1/4 fullb010 + * = Transmit FIFO becomes 1/2 fullb011 = Transmit FIFO becomes + * 3/4 fullb100 = Transmit FIFO becomes 7/8 fullb101-b111 + * = Reserved. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] Receive interrupt FIFO level select. The trigger points + * for the receive interrupt are as follows:b000 = Receive + * FIFO becomes 1/8 fullb001 = Receive FIFO becomes 1/4 fullb010 + * = Receive FIFO becomes 1/2 fullb011 = Receive FIFO becomes + * 3/4 fullb100 = Receive FIFO becomes 7/8 fullb101-b111 = + * Reserved. */ + uint32_t : 26; + } UART_IFLS_REG_b; + }; + + union + { + __IOM uint32_t UART_IMSC_REG; /*!< (@ 0x00000038) UART Interrupt Mask Set/Clear Register */ + + struct + { + __IOM uint32_t RIMIM : 1; /*!< [0..0] nUARTRI modem interrupt mask. A read returns the current + * mask for the UARTRIINTR interrupt.On a write of 1, the + * mask of the UARTRIINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] nUARTCTS modem interrupt mask. A read returns the current + * mask for the UARTCTSINTR interrupt.On a write of 1, the + * mask of the UARTCTSINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] nUARTDCD modem interrupt mask. A read returns the current + * mask for the UARTDCDINTR interrupt.On a write of 1, the + * mask of the UARTDCDINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] nUARTDSR modem interrupt mask. A read returns the current + * mask for the UARTDSRINTR interrupt.On a write of 1, the + * mask of the UARTDSRINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] Receive interrupt mask. A read returns the current mask + * for the UARTRXINTR interrupt.On a write of 1, the mask + * of the UARTRXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] Transmit interrupt mask. A read returns the current mask + * for the UARTTXINTR interrupt.On a write of 1, the mask + * of the UARTTXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] Receive timeout interrupt mask. A read returns the current + * mask for the UARTRTINTR interrupt.On a write of 1, the + * mask of the UARTRTINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] Framing error interrupt mask. A read returns the current + * mask for the UARTFEINTR interrupt.On a write of 1, the + * mask of the UARTFEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] Parity error interrupt mask. A read returns the current + * mask for the UARTPEINTR interrupt.On a write of 1, the + * mask of the UARTPEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] Break error interrupt mask. A read returns the current + * mask for the UARTBEINTR interrupt.On a write of 1, the + * mask of the UARTBEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] Overrun error interrupt mask. A read returns the current + * mask for the UARTOEINTR interrupt.On a write of 1, the + * mask of the UARTOEINTR interrupt is set. A write of 0 clears + * the mask. */ + uint32_t : 21; + } UART_IMSC_REG_b; + }; + + union + { + __IOM uint32_t UART_RIS_REG; /*!< (@ 0x0000003C) UART Raw Interrupt Status Register */ + + struct + { + __IM uint32_t RIRMIS : 1; /*!< [0..0] nUARTRI modem interrupt status. Returns the raw interrupt + * state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSRMIS : 1; /*!< [1..1] nUARTCTS modem interrupt status. Returns the raw interrupt + * state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDRMIS : 1; /*!< [2..2] nUARTDCD modem interrupt status. Returns the raw interrupt + * state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRRMIS : 1; /*!< [3..3] nUARTDSR modem interrupt status. Returns the raw interrupt + * state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXRIS : 1; /*!< [4..4] Receive interrupt status. Returns the raw interrupt state + * of the UARTRXINTR interrupt. */ + __IM uint32_t TXRIS : 1; /*!< [5..5] Transmit interrupt status. Returns the raw interrupt + * state of the UARTTXINTR interrupt. */ + __IM uint32_t RTRIS : 1; /*!< [6..6] Receive timeout interrupt status. Returns the raw interrupt + * state of the UARTRTINTR interrupt. */ + __IM uint32_t FERIS : 1; /*!< [7..7] Framing error interrupt status. Returns the raw interrupt + * state of the UARTFEINTR interrupt. */ + __IM uint32_t PERIS : 1; /*!< [8..8] Parity error interrupt status. Returns the raw interrupt + * state of the UARTPEINTR interrupt. */ + __IM uint32_t BERIS : 1; /*!< [9..9] Break error interrupt status. Returns the raw interrupt + * state of the UARTBEINTR interrupt. */ + __IM uint32_t OERIS : 1; /*!< [10..10] Overrun error interrupt status. Returns the raw interrupt + * state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART_RIS_REG_b; + }; + + union + { + __IOM uint32_t UART_MIS_REG; /*!< (@ 0x00000040) UART Masked Interrupt Status Register */ + + struct + { + __IM uint32_t RIMMIS : 1; /*!< [0..0] nUARTRI modem masked interrupt status. Returns the masked + * interrupt state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSMMIS : 1; /*!< [1..1] nUARTCTS modem masked interrupt status. Returns the masked + * interrupt state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDMMIS : 1; /*!< [2..2] nUARTDCD modem masked interrupt status. Returns the masked + * interrupt state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRMMIS : 1; /*!< [3..3] nUARTDSR modem masked interrupt status. Returns the masked + * interrupt state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXMIS : 1; /*!< [4..4] Receive masked interrupt status. Returns the masked interrupt + * state of the UARTRXINTR interrupt. */ + __IM uint32_t TXMIS : 1; /*!< [5..5] Transmit masked interrupt status. Returns the masked + * interrupt state of the UARTTXINTR interrupt. */ + __IM uint32_t RTMIS : 1; /*!< [6..6] Receive timeout masked interrupt status. Returns the + * masked interrupt state of the UARTRTINTR interrupt. */ + __IM uint32_t FEMIS : 1; /*!< [7..7] Framing error masked interrupt status. Returns the masked + * interrupt state of the UARTFEINTR interrupt. */ + __IM uint32_t PEMIS : 1; /*!< [8..8] Parity error masked interrupt status. Returns the masked + * interrupt state of the UARTPEINTR interrupt. */ + __IM uint32_t BEMIS : 1; /*!< [9..9] Break error masked interrupt status. Returns the masked + * interrupt state of the UARTBEINTR interrupt. */ + __IM uint32_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status. Returns the + * masked interrupt state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART_MIS_REG_b; + }; + + union + { + __IOM uint32_t UART_ICR_REG; /*!< (@ 0x00000044) UART Interrupt Clear Register */ + + struct + { + __OM uint32_t RIMIC : 1; /*!< [0..0] nUARTRI modem interrupt clear. Clears the UARTRIINTR + * interrupt. */ + __OM uint32_t CTSMIC : 1; /*!< [1..1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR + * interrupt. */ + __OM uint32_t DCDMIC : 1; /*!< [2..2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR + * interrupt. */ + __OM uint32_t DSRMIC : 1; /*!< [3..3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR + * interrupt. */ + __OM uint32_t RXIC : 1; /*!< [4..4] Receive interrupt clear. Clears the UARTRXINTR interrupt. */ + __OM uint32_t TXIC : 1; /*!< [5..5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. */ + __OM uint32_t RTIC : 1; /*!< [6..6] Receive timeout interrupt clear. Clears the UARTRTINTR + * interrupt. */ + __OM uint32_t FEIC : 1; /*!< [7..7] Framing error interrupt clear. Clears the UARTFEINTR + * interrupt. */ + __OM uint32_t PEIC : 1; /*!< [8..8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. */ + __OM uint32_t BEIC : 1; /*!< [9..9] Break error interrupt clear. Clears the UARTBEINTR interrupt. */ + __OM uint32_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear. Clears the UARTOEINTR + * interrupt. */ + uint32_t : 21; + } UART_ICR_REG_b; + }; + + union + { + __IOM uint32_t UART_DMACR_REG; /*!< (@ 0x00000048) UART DMA Control Register */ + + struct + { + __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA enable. If this bit is set to 1, DMA for + * the receive FIFO is enabled. */ + __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA enable. If this bit is set to 1, DMA for + * the transmit FIFO is enabled. */ + __IOM uint32_t DMAONERR : 1; /*!< [2..2] DMA on error. If this bit is set to 1, the DMA receive + * request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled + * when the UART error interrupt is asserted */ + uint32_t : 29; + } UART_DMACR_REG_b; + }; + + union + { + __IOM uint32_t UART_WA_REG; /*!< (@ 0x0000004C) UART Word Access Enable Register */ + + struct + { + __IOM uint32_t WAE : 1; /*!< [0..0] DMA word access enable bit. If this bit is set to 1, + * DMA word access mode is enabled. */ + uint32_t : 31; + } UART_WA_REG_b; + }; + + union + { + __IOM uint32_t UART_SWFC_REG; /*!< (@ 0x00000050) UART Software Flow Control Enable Register */ + + struct + { + __IOM uint32_t SWFCE : 1; /*!< [0..0] DMA software flow control enable bit. If this bit is + * set to 1, DMA software flow control mode is enabled. */ + uint32_t : 31; + } UART_SWFC_REG_b; + }; + + union + { + __IOM uint32_t UART_RS485EN_REG; /*!< (@ 0x00000054) UART RS485 Mode Enable Register */ + + struct + { + __IOM uint32_t RS485E : 1; /*!< [0..0] DMA RS485 mode enable bit. If this bit is set to 1, DMA + * RS485 mode is enabled. */ + uint32_t : 31; + } UART_RS485EN_REG_b; + }; +} UART_Type; /*!< Size = 88 (0x58) */ + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief UART2 registers (UART2) + */ + +typedef struct /*!< (@ 0x40001000) UART2 Structure */ +{ + union + { + __IOM uint32_t UART2_DR_REG; /*!< (@ 0x00000000) UART Data Register */ + + struct + { + __IOM uint32_t DR_DATA : 8; /*!< [7..0] Receive (read) data charaterTransmit (write) data character */ + __IOM uint32_t DR_FE : 1; /*!< [8..8] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).In FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t DR_PE : 1; /*!< [9..9] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.In FIFO mode, this error is associated with the + * character at the top of the FIFO. */ + __IOM uint32_t DR_BE : 1; /*!< [10..10] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity and stop bits).In FIFO + * mode, this error is associated with the character at the + * top of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (marking state), + * and the next valid start bit is received. */ + __IOM uint32_t DR_OE : 1; /*!< [11..11] Overrun error. This bit is set to 1 if data is received + * and the receive FIFO is already full.This is cleared to + * 0 once there is an empty space in the FIFO and a new character + * can be written to it. */ + uint32_t : 20; + } UART2_DR_REG_b; + }; + + union + { + __IOM uint32_t UART2_RSR_REG; /*!< (@ 0x00000004) UART Receive Status (Read), Error Clear (Write) + * Register */ + + struct + { + __IOM uint32_t RSR_FE : 1; /*!< [0..0] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_PE : 1; /*!< [1..1] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_BE : 1; /*!< [2..2] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity, and stop bits).This bit + * is cleared to 0 after a write to the register.In FIFO mode, + * this error is associated with the character at the top + * of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (mark */ + __IOM uint32_t RSR_OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received + * and the FIFO is already full.This bit is cleared to 0 by + * a write to the register.The FIFO contents remain valid + * because no more data is written when the FIFO is full, + * only the contents of the shift register are overwritten. + * The CPU must now read the data, to empty the FIFO. */ + uint32_t : 28; + } UART2_RSR_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t UART2_FR_REG; /*!< (@ 0x00000018) UART Flag Register */ + + struct + { + __IM uint32_t CTS : 1; /*!< [0..0] Clear to send. This bit is the complement of the UART + * clear to send, nUARTCTS, modem status input.That is, the + * bit is 1 when nUARTCTS is LOW. */ + __IM uint32_t DSR : 1; /*!< [1..1] Data set ready. This bit is the complement of the UART + * data set ready, nUARTDSR, modem status input.That is, the + * bit is 1 when nUARTDSR is LOW. */ + __IM uint32_t DCD : 1; /*!< [2..2] Data carrier detect. This bit is the complement of the + * UART data carrier detect, nUARTDCD, modem status input.That + * is, the bit is 1 when nUARTDCD is LOW. */ + __IM uint32_t BUSY : 1; /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy + * transmitting data. This bit remains set until the complete + * byte, including all the stop bits, has been sent from the + * shift register.This bit is set as soon as the transmit + * FIFO becomes non-empty, regardless of whether the UART + * is enabled or not. */ + __IM uint32_t RXFE : 1; /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is empty.If the FIFO is enabled, the RXFE bit + * is set when the receive FIFO is empty. */ + __IM uint32_t TXFF : 1; /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the transmit holding + * register is full.If the FIFO is enabled, the TXFF bit is + * set when the transmit FIFO is full. */ + __IM uint32_t RXFF : 1; /*!< [6..6] Receive FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is full.If the FIFO is enabled, the RXFF bit is + * set when the receive FIFO is full. */ + __IM uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends + * on the state of the FEN bit in the Line Control Register, + * UARTLCR_HIf the FIFO is disabled, this bit is set when + * the transmit holding register is empty.If the FIFO is enabled, + * the TXFE bit is set when the transmit FIFO is empty.This + * bit does not indicate if there is data in the transmit + * shift register. */ + __IM uint32_t RI : 1; /*!< [8..8] Ring indicator. This bit is the complement of the UART + * ring indicator, nUARTRI, modem status input.That is, the + * bit is 1 when nUARTRI is LOW. */ + uint32_t : 23; + } UART2_FR_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t UART2_IBRD_REG; /*!< (@ 0x00000024) UART Integer Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVINT : 16; /*!< [15..0] The integer baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 16; + } UART2_IBRD_REG_b; + }; + + union + { + __IOM uint32_t UART2_FBRD_REG; /*!< (@ 0x00000028) UART Fractional Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVFRAC : 6; /*!< [5..0] The fractional baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 26; + } UART2_FBRD_REG_b; + }; + + union + { + __IOM uint32_t UART2_LCR_H_REG; /*!< (@ 0x0000002C) UART Line Control Register (High Byte) */ + + struct + { + __IOM uint32_t BRK : 1; /*!< [0..0] Send break. If this bit is set to 1, a low-level is continually + * output on the UARTTXD output, after completing transmission + * of the current character. For the proper execution of the + * break command, the software must set this bit for at least + * two complete frames.For normal use, this bit must be cleared + * to 0. */ + __IOM uint32_t PEN : 1; /*!< [1..1] Parity enable:0 = parity is disabled and no parity bit + * added to the data frame1 = parity checking and generation + * is enabled. */ + __IOM uint32_t EPS : 1; /*!< [2..2] Even parity select. Controls the type of parity the UART + * uses during transmission and reception:0 = odd parity. + * The UART generates or checks for an odd number of 1s in + * the data and parity bits.1 = even parity. The UART generates + * or checks for an even number of 1s in the data and parity + * bits.This bit has no effect when the PEN bit disables parity + * checking and generation. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] Two stop bits select. If this bit is set to 1, two stop + * bits are transmitted at the end of the frame. The receive + * logic does not check for two stop bits being received. */ + __IOM uint32_t FEN : 1; /*!< [4..4] Enable FIFOs:0 = FIFOs are disabled (character mode) + * that is, the FIFOs become 1-byte-deep holding registers1 + * = transmit and receive FIFO buffers are enabled (FIFO mode). */ + __IOM uint32_t WLEN : 2; /*!< [6..5] Word length. These bits indicate the number of data bits + * transmitted or received in a frame as follows:b11 = 8 bitsb10 + * = 7 bitsb01 = 6 bitsb00 = 5 bits. */ + __IOM uint32_t SPS : 1; /*!< [7..7] Stick parity select.0 = stick parity is disabled1 = either:? + * if the EPS bit is 0 then the parity bit is transmitted + * and checked as a 1? if the EPS bit is 1 then the parity + * bit is transmitted and checked as a 0.This bit has no effect + * when the PEN bit disables parity checking and generation. */ + uint32_t : 24; + } UART2_LCR_H_REG_b; + }; + + union + { + __IOM uint32_t UART2_CR_REG; /*!< (@ 0x00000030) UART Control Register */ + + struct + { + __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable:0 = UART is disabled. If the UART is disabled + * in the middle of transmission or reception, it completes + * the current character before stopping.1 = the UART is enabled. + * Data transmission and reception occurs. */ + uint32_t : 6; + __IOM uint32_t LBE : 1; /*!< [7..7] Loopback enable. If this bit is set to 1, the UARTTXD + * path is fed through to the UARTRXD path.When this bit is + * set, the modem outputs are also fed through to the modem + * inputs.This bit is cleared to 0 on reset, to disable loopback. */ + __IOM uint32_t TXE : 1; /*!< [8..8] Transmit enable. If this bit is set to 1, the transmit + * section of the UART is enabled. */ + __IOM uint32_t RXE : 1; /*!< [9..9] Receive enable. If this bit is set to 1, the receive + * section of the UART is enabled. */ + __IOM uint32_t DTR : 1; /*!< [10..10] Data transmit ready. This bit is the complement of + * the UART data transmit ready, nUARTDTR, modem status output. + * That is, when the bit is programmed to a 1 then nUARTDTR + * is LOW */ + __IOM uint32_t RTS : 1; /*!< [11..11] Request to send. This bit is the complement of the + * UART request to send, nUARTRTS, modem status output. That + * is, when the bit is programmed to a 1 then nUARTRTS is + * LOW */ + __IOM uint32_t Out1 : 1; /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1) + * modem status output. That is, when the bit is programmed + * to a 1 the output is 0. For DTE this can be used as Data + * Carrier Detect (DCD). */ + __IOM uint32_t Out2 : 1; /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2) + * modem status output. That is, when the bit is programmed + * to a 1, the output is 0. For DTE this can be used as Ring + * Indicator (RI). */ + __IOM uint32_t RTSEn : 1; /*!< [14..14] RTS hardware flow control enable. If this bit is set + * to 1, RTS hardware flow control is enabled.Data is only + * requested when there is space in the receive FIFO for it + * to be received. */ + __IOM uint32_t CTSEn : 1; /*!< [15..15] CTS hardware flow control enable. If this bit is set + * to 1, CTS hardware flow control is enabled.Data is only + * transmitted when the nUARTCTS signal is asserted. */ + uint32_t : 16; + } UART2_CR_REG_b; + }; + + union + { + __IOM uint32_t UART2_IFLS_REG; /*!< (@ 0x00000034) UART Interrupt FIFO Level Select Register */ + + struct + { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] Transmit interrupt FIFO level select. The trigger points + * for the transmit interrupt are as follows:b000 = Transmit + * FIFO becomes 1/8 fullb001 = Transmit FIFO becomes 1/4 fullb010 + * = Transmit FIFO becomes 1/2 fullb011 = Transmit FIFO becomes + * 3/4 fullb100 = Transmit FIFO becomes 7/8 fullb101-b111 + * = Reserved. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] Receive interrupt FIFO level select. The trigger points + * for the receive interrupt are as follows:b000 = Receive + * FIFO becomes 1/8 fullb001 = Receive FIFO becomes 1/4 fullb010 + * = Receive FIFO becomes 1/2 fullb011 = Receive FIFO becomes + * 3/4 fullb100 = Receive FIFO becomes 7/8 fullb101-b111 = + * Reserved. */ + uint32_t : 26; + } UART2_IFLS_REG_b; + }; + + union + { + __IOM uint32_t UART2_IMSC_REG; /*!< (@ 0x00000038) UART Interrupt Mask Set/Clear Register */ + + struct + { + __IOM uint32_t RIMIM : 1; /*!< [0..0] nUARTRI modem interrupt mask. A read returns the current + * mask for the UARTRIINTR interrupt.On a write of 1, the + * mask of the UARTRIINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] nUARTCTS modem interrupt mask. A read returns the current + * mask for the UARTCTSINTR interrupt.On a write of 1, the + * mask of the UARTCTSINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] nUARTDCD modem interrupt mask. A read returns the current + * mask for the UARTDCDINTR interrupt.On a write of 1, the + * mask of the UARTDCDINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] nUARTDSR modem interrupt mask. A read returns the current + * mask for the UARTDSRINTR interrupt.On a write of 1, the + * mask of the UARTDSRINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] Receive interrupt mask. A read returns the current mask + * for the UARTRXINTR interrupt.On a write of 1, the mask + * of the UARTRXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] Transmit interrupt mask. A read returns the current mask + * for the UARTTXINTR interrupt.On a write of 1, the mask + * of the UARTTXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] Receive timeout interrupt mask. A read returns the current + * mask for the UARTRTINTR interrupt.On a write of 1, the + * mask of the UARTRTINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] Framing error interrupt mask. A read returns the current + * mask for the UARTFEINTR interrupt.On a write of 1, the + * mask of the UARTFEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] Parity error interrupt mask. A read returns the current + * mask for the UARTPEINTR interrupt.On a write of 1, the + * mask of the UARTPEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] Break error interrupt mask. A read returns the current + * mask for the UARTBEINTR interrupt.On a write of 1, the + * mask of the UARTBEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] Overrun error interrupt mask. A read returns the current + * mask for the UARTOEINTR interrupt.On a write of 1, the + * mask of the UARTOEINTR interrupt is set. A write of 0 clears + * the mask. */ + uint32_t : 21; + } UART2_IMSC_REG_b; + }; + + union + { + __IOM uint32_t UART2_RIS_REG; /*!< (@ 0x0000003C) UART Raw Interrupt Status Register */ + + struct + { + __IM uint32_t RIRMIS : 1; /*!< [0..0] nUARTRI modem interrupt status. Returns the raw interrupt + * state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSRMIS : 1; /*!< [1..1] nUARTCTS modem interrupt status. Returns the raw interrupt + * state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDRMIS : 1; /*!< [2..2] nUARTDCD modem interrupt status. Returns the raw interrupt + * state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRRMIS : 1; /*!< [3..3] nUARTDSR modem interrupt status. Returns the raw interrupt + * state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXRIS : 1; /*!< [4..4] Receive interrupt status. Returns the raw interrupt state + * of the UARTRXINTR interrupt. */ + __IM uint32_t TXRIS : 1; /*!< [5..5] Transmit interrupt status. Returns the raw interrupt + * state of the UARTTXINTR interrupt. */ + __IM uint32_t RTRIS : 1; /*!< [6..6] Receive timeout interrupt status. Returns the raw interrupt + * state of the UARTRTINTR interrupt. */ + __IM uint32_t FERIS : 1; /*!< [7..7] Framing error interrupt status. Returns the raw interrupt + * state of the UARTFEINTR interrupt. */ + __IM uint32_t PERIS : 1; /*!< [8..8] Parity error interrupt status. Returns the raw interrupt + * state of the UARTPEINTR interrupt. */ + __IM uint32_t BERIS : 1; /*!< [9..9] Break error interrupt status. Returns the raw interrupt + * state of the UARTBEINTR interrupt. */ + __IM uint32_t OERIS : 1; /*!< [10..10] Overrun error interrupt status. Returns the raw interrupt + * state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART2_RIS_REG_b; + }; + + union + { + __IOM uint32_t UART2_MIS_REG; /*!< (@ 0x00000040) UART Masked Interrupt Status Register */ + + struct + { + __IM uint32_t RIMMIS : 1; /*!< [0..0] nUARTRI modem masked interrupt status. Returns the masked + * interrupt state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSMMIS : 1; /*!< [1..1] nUARTCTS modem masked interrupt status. Returns the masked + * interrupt state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDMMIS : 1; /*!< [2..2] nUARTDCD modem masked interrupt status. Returns the masked + * interrupt state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRMMIS : 1; /*!< [3..3] nUARTDSR modem masked interrupt status. Returns the masked + * interrupt state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXMIS : 1; /*!< [4..4] Receive masked interrupt status. Returns the masked interrupt + * state of the UARTRXINTR interrupt. */ + __IM uint32_t TXMIS : 1; /*!< [5..5] Transmit masked interrupt status. Returns the masked + * interrupt state of the UARTTXINTR interrupt. */ + __IM uint32_t RTMIS : 1; /*!< [6..6] Receive timeout masked interrupt status. Returns the + * masked interrupt state of the UARTRTINTR interrupt. */ + __IM uint32_t FEMIS : 1; /*!< [7..7] Framing error masked interrupt status. Returns the masked + * interrupt state of the UARTFEINTR interrupt. */ + __IM uint32_t PEMIS : 1; /*!< [8..8] Parity error masked interrupt status. Returns the masked + * interrupt state of the UARTPEINTR interrupt. */ + __IM uint32_t BEMIS : 1; /*!< [9..9] Break error masked interrupt status. Returns the masked + * interrupt state of the UARTBEINTR interrupt. */ + __IM uint32_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status. Returns the + * masked interrupt state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART2_MIS_REG_b; + }; + + union + { + __IOM uint32_t UART2_ICR_REG; /*!< (@ 0x00000044) UART Interrupt Clear Register */ + + struct + { + __OM uint32_t RIMIC : 1; /*!< [0..0] nUARTRI modem interrupt clear. Clears the UARTRIINTR + * interrupt. */ + __OM uint32_t CTSMIC : 1; /*!< [1..1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR + * interrupt. */ + __OM uint32_t DCDMIC : 1; /*!< [2..2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR + * interrupt. */ + __OM uint32_t DSRMIC : 1; /*!< [3..3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR + * interrupt. */ + __OM uint32_t RXIC : 1; /*!< [4..4] Receive interrupt clear. Clears the UARTRXINTR interrupt. */ + __OM uint32_t TXIC : 1; /*!< [5..5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. */ + __OM uint32_t RTIC : 1; /*!< [6..6] Receive timeout interrupt clear. Clears the UARTRTINTR + * interrupt. */ + __OM uint32_t FEIC : 1; /*!< [7..7] Framing error interrupt clear. Clears the UARTFEINTR + * interrupt. */ + __OM uint32_t PEIC : 1; /*!< [8..8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. */ + __OM uint32_t BEIC : 1; /*!< [9..9] Break error interrupt clear. Clears the UARTBEINTR interrupt. */ + __OM uint32_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear. Clears the UARTOEINTR + * interrupt. */ + uint32_t : 21; + } UART2_ICR_REG_b; + }; + + union + { + __IOM uint32_t UART2_DMACR_REG; /*!< (@ 0x00000048) UART DMA Control Register */ + + struct + { + __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA enable. If this bit is set to 1, DMA for + * the receive FIFO is enabled. */ + __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA enable. If this bit is set to 1, DMA for + * the transmit FIFO is enabled. */ + __IOM uint32_t DMAONERR : 1; /*!< [2..2] DMA on error. If this bit is set to 1, the DMA receive + * request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled + * when the UART error interrupt is asserted */ + uint32_t : 29; + } UART2_DMACR_REG_b; + }; + + union + { + __IOM uint32_t UART2_WA_REG; /*!< (@ 0x0000004C) UART Word Access Enable Register */ + + struct + { + __IOM uint32_t WAE : 1; /*!< [0..0] DMA word access enable bit. If this bit is set to 1, + * DMA word access mode is enabled. */ + uint32_t : 31; + } UART2_WA_REG_b; + }; + + union + { + __IOM uint32_t UART2_SWFC_REG; /*!< (@ 0x00000050) UART Software Flow Control Enable Register */ + + struct + { + __IOM uint32_t SWFCE : 1; /*!< [0..0] DMA software flow control enable bit. If this bit is + * set to 1, DMA software flow control mode is enabled. */ + uint32_t : 31; + } UART2_SWFC_REG_b; + }; + + union + { + __IOM uint32_t UART2_RS485EN_REG; /*!< (@ 0x00000054) UART RS485 Mode Enable Register */ + + struct + { + __IOM uint32_t RS485E : 1; /*!< [0..0] DMA RS485 mode enable bit. If this bit is set to 1, DMA + * RS485 mode is enabled. */ + uint32_t : 31; + } UART2_RS485EN_REG_b; + }; +} UART2_Type; /*!< Size = 88 (0x58) */ + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief UART3 registers (UART3) + */ + +typedef struct /*!< (@ 0x40002000) UART3 Structure */ +{ + union + { + __IOM uint32_t UART3_DR_REG; /*!< (@ 0x00000000) UART Data Register */ + + struct + { + __IOM uint32_t DR_DATA : 8; /*!< [7..0] Receive (read) data charaterTransmit (write) data character */ + __IOM uint32_t DR_FE : 1; /*!< [8..8] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).In FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t DR_PE : 1; /*!< [9..9] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.In FIFO mode, this error is associated with the + * character at the top of the FIFO. */ + __IOM uint32_t DR_BE : 1; /*!< [10..10] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity and stop bits).In FIFO + * mode, this error is associated with the character at the + * top of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (marking state), + * and the next valid start bit is received. */ + __IOM uint32_t DR_OE : 1; /*!< [11..11] Overrun error. This bit is set to 1 if data is received + * and the receive FIFO is already full.This is cleared to + * 0 once there is an empty space in the FIFO and a new character + * can be written to it. */ + uint32_t : 20; + } UART3_DR_REG_b; + }; + + union + { + __IOM uint32_t UART3_RSR_REG; /*!< (@ 0x00000004) UART Receive Status (Read), Error Clear (Write) + * Register */ + + struct + { + __IOM uint32_t RSR_FE : 1; /*!< [0..0] Framing error. When set to 1, it indicates that the received + * character did not have a valid stop bit (a valid stop bit + * is 1).This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_PE : 1; /*!< [1..1] Parity error. When set to 1, it indicates that the parity + * of the received data character does not match the parity + * that the EPS and SPS bits in the Line Control Register, + * UARTLCR_H.This bit is cleared to 0 by a write to the register.In + * FIFO mode, this error is associated with the character + * at the top of the FIFO. */ + __IOM uint32_t RSR_BE : 1; /*!< [2..2] Break error. This bit is set to 1 if a break condition + * was detected, indicating that the received data input was + * held LOW for longer than a full-word transmission time + * (defined as start, data, parity, and stop bits).This bit + * is cleared to 0 after a write to the register.In FIFO mode, + * this error is associated with the character at the top + * of the FIFO. When a break occurs, only one 0 character + * is loaded into the FIFO. The next character is only enabled + * after the receive data input goes to a 1 (mark */ + __IOM uint32_t RSR_OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received + * and the FIFO is already full.This bit is cleared to 0 by + * a write to the register.The FIFO contents remain valid + * because no more data is written when the FIFO is full, + * only the contents of the shift register are overwritten. + * The CPU must now read the data, to empty the FIFO. */ + uint32_t : 28; + } UART3_RSR_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t UART3_FR_REG; /*!< (@ 0x00000018) UART Flag Register */ + + struct + { + __IM uint32_t CTS : 1; /*!< [0..0] Clear to send. This bit is the complement of the UART + * clear to send, nUARTCTS, modem status input.That is, the + * bit is 1 when nUARTCTS is LOW. */ + __IM uint32_t DSR : 1; /*!< [1..1] Data set ready. This bit is the complement of the UART + * data set ready, nUARTDSR, modem status input.That is, the + * bit is 1 when nUARTDSR is LOW. */ + __IM uint32_t DCD : 1; /*!< [2..2] Data carrier detect. This bit is the complement of the + * UART data carrier detect, nUARTDCD, modem status input.That + * is, the bit is 1 when nUARTDCD is LOW. */ + __IM uint32_t BUSY : 1; /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy + * transmitting data. This bit remains set until the complete + * byte, including all the stop bits, has been sent from the + * shift register.This bit is set as soon as the transmit + * FIFO becomes non-empty, regardless of whether the UART + * is enabled or not. */ + __IM uint32_t RXFE : 1; /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is empty.If the FIFO is enabled, the RXFE bit + * is set when the receive FIFO is empty. */ + __IM uint32_t TXFF : 1; /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the transmit holding + * register is full.If the FIFO is enabled, the TXFF bit is + * set when the transmit FIFO is full. */ + __IM uint32_t RXFF : 1; /*!< [6..6] Receive FIFO full. The meaning of this bit depends on + * the state of the FEN bit in the UARTLCR_H Register.If the + * FIFO is disabled, this bit is set when the receive holding + * register is full.If the FIFO is enabled, the RXFF bit is + * set when the receive FIFO is full. */ + __IM uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends + * on the state of the FEN bit in the Line Control Register, + * UARTLCR_HIf the FIFO is disabled, this bit is set when + * the transmit holding register is empty.If the FIFO is enabled, + * the TXFE bit is set when the transmit FIFO is empty.This + * bit does not indicate if there is data in the transmit + * shift register. */ + __IM uint32_t RI : 1; /*!< [8..8] Ring indicator. This bit is the complement of the UART + * ring indicator, nUARTRI, modem status input.That is, the + * bit is 1 when nUARTRI is LOW. */ + uint32_t : 23; + } UART3_FR_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t UART3_IBRD_REG; /*!< (@ 0x00000024) UART Integer Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVINT : 16; /*!< [15..0] The integer baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 16; + } UART3_IBRD_REG_b; + }; + + union + { + __IOM uint32_t UART3_FBRD_REG; /*!< (@ 0x00000028) UART Fractional Baud Rate Divisor Register */ + + struct + { + __IOM uint32_t BAUD_DIVFRAC : 6; /*!< [5..0] The fractional baud rate divisor.These bits are cleared + * to 0 on reset. */ + uint32_t : 26; + } UART3_FBRD_REG_b; + }; + + union + { + __IOM uint32_t UART3_LCR_H_REG; /*!< (@ 0x0000002C) UART Line Control Register (High Byte) */ + + struct + { + __IOM uint32_t BRK : 1; /*!< [0..0] Send break. If this bit is set to 1, a low-level is continually + * output on the UARTTXD output, after completing transmission + * of the current character. For the proper execution of the + * break command, the software must set this bit for at least + * two complete frames.For normal use, this bit must be cleared + * to 0. */ + __IOM uint32_t PEN : 1; /*!< [1..1] Parity enable:0 = parity is disabled and no parity bit + * added to the data frame1 = parity checking and generation + * is enabled. */ + __IOM uint32_t EPS : 1; /*!< [2..2] Even parity select. Controls the type of parity the UART + * uses during transmission and reception:0 = odd parity. + * The UART generates or checks for an odd number of 1s in + * the data and parity bits.1 = even parity. The UART generates + * or checks for an even number of 1s in the data and parity + * bits.This bit has no effect when the PEN bit disables parity + * checking and generation. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] Two stop bits select. If this bit is set to 1, two stop + * bits are transmitted at the end of the frame. The receive + * logic does not check for two stop bits being received. */ + __IOM uint32_t FEN : 1; /*!< [4..4] Enable FIFOs:0 = FIFOs are disabled (character mode) + * that is, the FIFOs become 1-byte-deep holding registers1 + * = transmit and receive FIFO buffers are enabled (FIFO mode). */ + __IOM uint32_t WLEN : 2; /*!< [6..5] Word length. These bits indicate the number of data bits + * transmitted or received in a frame as follows:b11 = 8 bitsb10 + * = 7 bitsb01 = 6 bitsb00 = 5 bits. */ + __IOM uint32_t SPS : 1; /*!< [7..7] Stick parity select.0 = stick parity is disabled1 = either:? + * if the EPS bit is 0 then the parity bit is transmitted + * and checked as a 1? if the EPS bit is 1 then the parity + * bit is transmitted and checked as a 0.This bit has no effect + * when the PEN bit disables parity checking and generation. */ + uint32_t : 24; + } UART3_LCR_H_REG_b; + }; + + union + { + __IOM uint32_t UART3_CR_REG; /*!< (@ 0x00000030) UART Control Register */ + + struct + { + __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable:0 = UART is disabled. If the UART is disabled + * in the middle of transmission or reception, it completes + * the current character before stopping.1 = the UART is enabled. + * Data transmission and reception occurs. */ + uint32_t : 6; + __IOM uint32_t LBE : 1; /*!< [7..7] Loopback enable. If this bit is set to 1, the UARTTXD + * path is fed through to the UARTRXD path.When this bit is + * set, the modem outputs are also fed through to the modem + * inputs.This bit is cleared to 0 on reset, to disable loopback. */ + __IOM uint32_t TXE : 1; /*!< [8..8] Transmit enable. If this bit is set to 1, the transmit + * section of the UART is enabled. */ + __IOM uint32_t RXE : 1; /*!< [9..9] Receive enable. If this bit is set to 1, the receive + * section of the UART is enabled. */ + __IOM uint32_t DTR : 1; /*!< [10..10] Data transmit ready. This bit is the complement of + * the UART data transmit ready, nUARTDTR, modem status output. + * That is, when the bit is programmed to a 1 then nUARTDTR + * is LOW */ + __IOM uint32_t RTS : 1; /*!< [11..11] Request to send. This bit is the complement of the + * UART request to send, nUARTRTS, modem status output. That + * is, when the bit is programmed to a 1 then nUARTRTS is + * LOW */ + __IOM uint32_t Out1 : 1; /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1) + * modem status output. That is, when the bit is programmed + * to a 1 the output is 0. For DTE this can be used as Data + * Carrier Detect (DCD). */ + __IOM uint32_t Out2 : 1; /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2) + * modem status output. That is, when the bit is programmed + * to a 1, the output is 0. For DTE this can be used as Ring + * Indicator (RI). */ + __IOM uint32_t RTSEn : 1; /*!< [14..14] RTS hardware flow control enable. If this bit is set + * to 1, RTS hardware flow control is enabled.Data is only + * requested when there is space in the receive FIFO for it + * to be received. */ + __IOM uint32_t CTSEn : 1; /*!< [15..15] CTS hardware flow control enable. If this bit is set + * to 1, CTS hardware flow control is enabled.Data is only + * transmitted when the nUARTCTS signal is asserted. */ + uint32_t : 16; + } UART3_CR_REG_b; + }; + + union + { + __IOM uint32_t UART3_IFLS_REG; /*!< (@ 0x00000034) UART Interrupt FIFO Level Select Register */ + + struct + { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] Transmit interrupt FIFO level select. The trigger points + * for the transmit interrupt are as follows:b000 = Transmit + * FIFO becomes 1/8 fullb001 = Transmit FIFO becomes 1/4 fullb010 + * = Transmit FIFO becomes 1/2 fullb011 = Transmit FIFO becomes + * 3/4 fullb100 = Transmit FIFO becomes 7/8 fullb101-b111 + * = Reserved. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] Receive interrupt FIFO level select. The trigger points + * for the receive interrupt are as follows:b000 = Receive + * FIFO becomes 1/8 fullb001 = Receive FIFO becomes 1/4 fullb010 + * = Receive FIFO becomes 1/2 fullb011 = Receive FIFO becomes + * 3/4 fullb100 = Receive FIFO becomes 7/8 fullb101-b111 = + * Reserved. */ + uint32_t : 26; + } UART3_IFLS_REG_b; + }; + + union + { + __IOM uint32_t UART3_IMSC_REG; /*!< (@ 0x00000038) UART Interrupt Mask Set/Clear Register */ + + struct + { + __IOM uint32_t RIMIM : 1; /*!< [0..0] nUARTRI modem interrupt mask. A read returns the current + * mask for the UARTRIINTR interrupt.On a write of 1, the + * mask of the UARTRIINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] nUARTCTS modem interrupt mask. A read returns the current + * mask for the UARTCTSINTR interrupt.On a write of 1, the + * mask of the UARTCTSINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] nUARTDCD modem interrupt mask. A read returns the current + * mask for the UARTDCDINTR interrupt.On a write of 1, the + * mask of the UARTDCDINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] nUARTDSR modem interrupt mask. A read returns the current + * mask for the UARTDSRINTR interrupt.On a write of 1, the + * mask of the UARTDSRINTR interrupt is set. A write of 0 + * clears the mask. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] Receive interrupt mask. A read returns the current mask + * for the UARTRXINTR interrupt.On a write of 1, the mask + * of the UARTRXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] Transmit interrupt mask. A read returns the current mask + * for the UARTTXINTR interrupt.On a write of 1, the mask + * of the UARTTXINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] Receive timeout interrupt mask. A read returns the current + * mask for the UARTRTINTR interrupt.On a write of 1, the + * mask of the UARTRTINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] Framing error interrupt mask. A read returns the current + * mask for the UARTFEINTR interrupt.On a write of 1, the + * mask of the UARTFEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] Parity error interrupt mask. A read returns the current + * mask for the UARTPEINTR interrupt.On a write of 1, the + * mask of the UARTPEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] Break error interrupt mask. A read returns the current + * mask for the UARTBEINTR interrupt.On a write of 1, the + * mask of the UARTBEINTR interrupt is set. A write of 0 clears + * the mask. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] Overrun error interrupt mask. A read returns the current + * mask for the UARTOEINTR interrupt.On a write of 1, the + * mask of the UARTOEINTR interrupt is set. A write of 0 clears + * the mask. */ + uint32_t : 21; + } UART3_IMSC_REG_b; + }; + + union + { + __IOM uint32_t UART3_RIS_REG; /*!< (@ 0x0000003C) UART Raw Interrupt Status Register */ + + struct + { + __IM uint32_t RIRMIS : 1; /*!< [0..0] nUARTRI modem interrupt status. Returns the raw interrupt + * state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSRMIS : 1; /*!< [1..1] nUARTCTS modem interrupt status. Returns the raw interrupt + * state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDRMIS : 1; /*!< [2..2] nUARTDCD modem interrupt status. Returns the raw interrupt + * state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRRMIS : 1; /*!< [3..3] nUARTDSR modem interrupt status. Returns the raw interrupt + * state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXRIS : 1; /*!< [4..4] Receive interrupt status. Returns the raw interrupt state + * of the UARTRXINTR interrupt. */ + __IM uint32_t TXRIS : 1; /*!< [5..5] Transmit interrupt status. Returns the raw interrupt + * state of the UARTTXINTR interrupt. */ + __IM uint32_t RTRIS : 1; /*!< [6..6] Receive timeout interrupt status. Returns the raw interrupt + * state of the UARTRTINTR interrupt. */ + __IM uint32_t FERIS : 1; /*!< [7..7] Framing error interrupt status. Returns the raw interrupt + * state of the UARTFEINTR interrupt. */ + __IM uint32_t PERIS : 1; /*!< [8..8] Parity error interrupt status. Returns the raw interrupt + * state of the UARTPEINTR interrupt. */ + __IM uint32_t BERIS : 1; /*!< [9..9] Break error interrupt status. Returns the raw interrupt + * state of the UARTBEINTR interrupt. */ + __IM uint32_t OERIS : 1; /*!< [10..10] Overrun error interrupt status. Returns the raw interrupt + * state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART3_RIS_REG_b; + }; + + union + { + __IOM uint32_t UART3_MIS_REG; /*!< (@ 0x00000040) UART Masked Interrupt Status Register */ + + struct + { + __IM uint32_t RIMMIS : 1; /*!< [0..0] nUARTRI modem masked interrupt status. Returns the masked + * interrupt state of the UARTRIINTR interrupt. */ + __IM uint32_t CTSMMIS : 1; /*!< [1..1] nUARTCTS modem masked interrupt status. Returns the masked + * interrupt state of the UARTCTSINTR interrupt. */ + __IM uint32_t DCDMMIS : 1; /*!< [2..2] nUARTDCD modem masked interrupt status. Returns the masked + * interrupt state of the UARTDCDINTR interrupt. */ + __IM uint32_t DSRMMIS : 1; /*!< [3..3] nUARTDSR modem masked interrupt status. Returns the masked + * interrupt state of the UARTDSRINTR interrupt. */ + __IM uint32_t RXMIS : 1; /*!< [4..4] Receive masked interrupt status. Returns the masked interrupt + * state of the UARTRXINTR interrupt. */ + __IM uint32_t TXMIS : 1; /*!< [5..5] Transmit masked interrupt status. Returns the masked + * interrupt state of the UARTTXINTR interrupt. */ + __IM uint32_t RTMIS : 1; /*!< [6..6] Receive timeout masked interrupt status. Returns the + * masked interrupt state of the UARTRTINTR interrupt. */ + __IM uint32_t FEMIS : 1; /*!< [7..7] Framing error masked interrupt status. Returns the masked + * interrupt state of the UARTFEINTR interrupt. */ + __IM uint32_t PEMIS : 1; /*!< [8..8] Parity error masked interrupt status. Returns the masked + * interrupt state of the UARTPEINTR interrupt. */ + __IM uint32_t BEMIS : 1; /*!< [9..9] Break error masked interrupt status. Returns the masked + * interrupt state of the UARTBEINTR interrupt. */ + __IM uint32_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status. Returns the + * masked interrupt state of the UARTOEINTR interrupt. */ + uint32_t : 21; + } UART3_MIS_REG_b; + }; + + union + { + __IOM uint32_t UART3_ICR_REG; /*!< (@ 0x00000044) UART Interrupt Clear Register */ + + struct + { + __OM uint32_t RIMIC : 1; /*!< [0..0] nUARTRI modem interrupt clear. Clears the UARTRIINTR + * interrupt. */ + __OM uint32_t CTSMIC : 1; /*!< [1..1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR + * interrupt. */ + __OM uint32_t DCDMIC : 1; /*!< [2..2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR + * interrupt. */ + __OM uint32_t DSRMIC : 1; /*!< [3..3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR + * interrupt. */ + __OM uint32_t RXIC : 1; /*!< [4..4] Receive interrupt clear. Clears the UARTRXINTR interrupt. */ + __OM uint32_t TXIC : 1; /*!< [5..5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. */ + __OM uint32_t RTIC : 1; /*!< [6..6] Receive timeout interrupt clear. Clears the UARTRTINTR + * interrupt. */ + __OM uint32_t FEIC : 1; /*!< [7..7] Framing error interrupt clear. Clears the UARTFEINTR + * interrupt. */ + __OM uint32_t PEIC : 1; /*!< [8..8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. */ + __OM uint32_t BEIC : 1; /*!< [9..9] Break error interrupt clear. Clears the UARTBEINTR interrupt. */ + __OM uint32_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear. Clears the UARTOEINTR + * interrupt. */ + uint32_t : 21; + } UART3_ICR_REG_b; + }; + + union + { + __IOM uint32_t UART3_DMACR_REG; /*!< (@ 0x00000048) UART DMA Control Register */ + + struct + { + __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA enable. If this bit is set to 1, DMA for + * the receive FIFO is enabled. */ + __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA enable. If this bit is set to 1, DMA for + * the transmit FIFO is enabled. */ + __IOM uint32_t DMAONERR : 1; /*!< [2..2] DMA on error. If this bit is set to 1, the DMA receive + * request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled + * when the UART error interrupt is asserted */ + uint32_t : 29; + } UART3_DMACR_REG_b; + }; + + union + { + __IOM uint32_t UART3_WA_REG; /*!< (@ 0x0000004C) UART Word Access Enable Register */ + + struct + { + __IOM uint32_t WAE : 1; /*!< [0..0] DMA word access enable bit. If this bit is set to 1, + * DMA word access mode is enabled. */ + uint32_t : 31; + } UART3_WA_REG_b; + }; + + union + { + __IOM uint32_t UART3_SWFC_REG; /*!< (@ 0x00000050) UART Software Flow Control Enable Register */ + + struct + { + __IOM uint32_t SWFCE : 1; /*!< [0..0] DMA software flow control enable bit. If this bit is + * set to 1, DMA software flow control mode is enabled. */ + uint32_t : 31; + } UART3_SWFC_REG_b; + }; + + union + { + __IOM uint32_t UART3_RS485EN_REG; /*!< (@ 0x00000054) UART RS485 Mode Enable Register */ + + struct + { + __IOM uint32_t RS485E : 1; /*!< [0..0] DMA RS485 mode enable bit. If this bit is set to 1, DMA + * RS485 mode is enabled. */ + uint32_t : 31; + } UART3_RS485EN_REG_b; + }; +} UART3_Type; /*!< Size = 88 (0x58) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define APU_AUD_BASE 0x400E0400UL + #define APU_DSP_BASE 0x400E0800UL + #define AUXADC_BASE 0x40090500UL + #define CACHE_BASE 0x0E010000UL + #define CC312_BASE 0x400F0000UL + #define CHIP_VERSION_BASE 0x40070200UL + #define CLKCAL_BIF_BASE 0x40090600UL + #define CRG_APU_BASE 0x400E0000UL + #define CRG_COM_BASE 0x400C0200UL + #define CRG_PER_BASE 0x40090400UL + #define CRG_SYS_BASE 0x40070500UL + #define CRG_TOP_BASE 0x400C0000UL + #define DAI_BASE 0x400E0900UL + #define DCACHE_BASE 0x21000000UL + #define DMA_BASE 0x40070700UL + #define FPLL_BASE 0x400C0300UL + #define GPIO_BASE 0x400B0000UL + #define GPREG_BASE 0x40070300UL + #define HW_ACC_BASE 0x40032000UL + #define I2C_BASE 0x40090000UL + #define I2C2_BASE 0x40090100UL + #define KDMA_BASE 0x40070A00UL + #define MEMCTRL_BASE 0x400B0800UL + #define OQSPIF_BASE 0x29000000UL + #define OTPC_BASE 0x400F3000UL + #define PSK_BASE 0x40031000UL + #define QSPIC_BASE 0x22000000UL + #define RETMEMCTRL_BASE 0x400B0900UL + #define RFMON_BASE 0x40070600UL + #define RTC_BASE 0x40038000UL + #define SDEMMC_BASE 0x40011000UL + #define SDIO_BASE 0x40010000UL + #define SPI_BASE 0x40090200UL + #define SPI2_BASE 0x40090300UL + #define SRC_FIFO_IF_BASE 0x40003000UL + #define SRC_IF_BASE 0x400E0C00UL + #define SYS_WDOG_BASE 0x400C0700UL + #define SYSBUS_BASE 0x2F000000UL + #define SYSBUS_ICM_BASE 0x40070400UL + #define TDES_BASE 0x40030000UL + #define TIMER_BASE 0x40080000UL + #define TIMER2_BASE 0x40080100UL + #define TIMER3_BASE 0x40080200UL + #define TIMER4_BASE 0x40080300UL + #define TIMER5_BASE 0x40080400UL + #define TIMER6_BASE 0x40080500UL + #define TIMER7_BASE 0x40080600UL + #define TIMER8_BASE 0x40080700UL + #define UART_BASE 0x40000000UL + #define UART2_BASE 0x40001000UL + #define UART3_BASE 0x40002000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define APU_AUD ((APU_AUD_Type *) APU_AUD_BASE) + #define APU_DSP ((APU_DSP_Type *) APU_DSP_BASE) + #define AUXADC ((AUXADC_Type *) AUXADC_BASE) + #define CACHE ((CACHE_Type *) CACHE_BASE) + #define CC312 ((CC312_Type *) CC312_BASE) + #define CHIP_VERSION ((CHIP_VERSION_Type *) CHIP_VERSION_BASE) + #define CLKCAL_BIF ((CLKCAL_BIF_Type *) CLKCAL_BIF_BASE) + #define CRG_APU ((CRG_APU_Type *) CRG_APU_BASE) + #define CRG_COM ((CRG_COM_Type *) CRG_COM_BASE) + #define CRG_PER ((CRG_PER_Type *) CRG_PER_BASE) + #define CRG_SYS ((CRG_SYS_Type *) CRG_SYS_BASE) + #define CRG_TOP ((CRG_TOP_Type *) CRG_TOP_BASE) + #define DAI ((DAI_Type *) DAI_BASE) + #define DCACHE ((DCACHE_Type *) DCACHE_BASE) + #define DMA ((DMA_Type *) DMA_BASE) + #define FPLL ((FPLL_Type *) FPLL_BASE) + #define GPIO ((GPIO_Type *) GPIO_BASE) + #define GPREG ((GPREG_Type *) GPREG_BASE) + #define HW_ACC ((HW_ACC_Type *) HW_ACC_BASE) + #define I2C ((I2C_Type *) I2C_BASE) + #define I2C2 ((I2C2_Type *) I2C2_BASE) + #define KDMA ((KDMA_Type *) KDMA_BASE) + #define MEMCTRL ((MEMCTRL_Type *) MEMCTRL_BASE) + #define OQSPIF ((OQSPIF_Type *) OQSPIF_BASE) + #define OTPC ((OTPC_Type *) OTPC_BASE) + #define PSK ((PSK_Type *) PSK_BASE) + #define QSPIC ((QSPIC_Type *) QSPIC_BASE) + #define RETMEMCTRL ((RETMEMCTRL_Type *) RETMEMCTRL_BASE) + #define RFMON ((RFMON_Type *) RFMON_BASE) + #define RTC ((RTC_Type *) RTC_BASE) + #define SDEMMC ((SDEMMC_Type *) SDEMMC_BASE) + #define SDIO ((SDIO_Type *) SDIO_BASE) + #define SPI ((SPI_Type *) SPI_BASE) + #define SPI2 ((SPI2_Type *) SPI2_BASE) + #define SRC_FIFO_IF ((SRC_FIFO_IF_Type *) SRC_FIFO_IF_BASE) + #define SRC_IF ((SRC_IF_Type *) SRC_IF_BASE) + #define SYS_WDOG ((SYS_WDOG_Type *) SYS_WDOG_BASE) + #define SYSBUS ((SYSBUS_Type *) SYSBUS_BASE) + #define SYSBUS_ICM ((SYSBUS_ICM_Type *) SYSBUS_ICM_BASE) + #define TDES ((TDES_Type *) TDES_BASE) + #define TIMER ((TIMER_Type *) TIMER_BASE) + #define TIMER2 ((TIMER2_Type *) TIMER2_BASE) + #define TIMER3 ((TIMER3_Type *) TIMER3_BASE) + #define TIMER4 ((TIMER4_Type *) TIMER4_BASE) + #define TIMER5 ((TIMER5_Type *) TIMER5_BASE) + #define TIMER6 ((TIMER6_Type *) TIMER6_BASE) + #define TIMER7 ((TIMER7_Type *) TIMER7_BASE) + #define TIMER8 ((TIMER8_Type *) TIMER8_BASE) + #define UART ((UART_Type *) UART_BASE) + #define UART2 ((UART2_Type *) UART2_BASE) + #define UART3 ((UART3_Type *) UART3_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ APU_AUD ================ */ +/* =========================================================================================================================== */ + +/* =================================================== APU_DMIC_CTRL_REG =================================================== */ + #define APU_AUD_APU_DMIC_CTRL_REG_DMIC1_IN_DELAY_Pos (16UL) /*!< DMIC1_IN_DELAY (Bit 16) */ + #define APU_AUD_APU_DMIC_CTRL_REG_DMIC1_IN_DELAY_Msk (0x30000UL) /*!< DMIC1_IN_DELAY (Bitfield-Mask: 0x03) */ + #define APU_AUD_APU_DMIC_CTRL_REG_DMIC_MASTER_MODE_Pos (0UL) /*!< DMIC_MASTER_MODE (Bit 0) */ + #define APU_AUD_APU_DMIC_CTRL_REG_DMIC_MASTER_MODE_Msk (0x1UL) /*!< DMIC_MASTER_MODE (Bitfield-Mask: 0x01) */ +/* =================================================== APU_DMIC_DIV_REG ==================================================== */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC1_PHASE_Pos (16UL) /*!< DMIC1_PHASE (Bit 16) */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC1_PHASE_Msk (0x1f0000UL) /*!< DMIC1_PHASE (Bitfield-Mask: 0x1f) */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC_DIV_Pos (8UL) /*!< DMIC_DIV (Bit 8) */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC_DIV_Msk (0x1f00UL) /*!< DMIC_DIV (Bitfield-Mask: 0x1f) */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC1_CLK_EN_Pos (0UL) /*!< DMIC1_CLK_EN (Bit 0) */ + #define APU_AUD_APU_DMIC_DIV_REG_DMIC1_CLK_EN_Msk (0x1UL) /*!< DMIC1_CLK_EN (Bitfield-Mask: 0x01) */ +/* =================================================== APU_MAIN_DIV_REG ==================================================== */ + #define APU_AUD_APU_MAIN_DIV_REG_APU_MAIN_DIV_EN_Pos (12UL) /*!< APU_MAIN_DIV_EN (Bit 12) */ + #define APU_AUD_APU_MAIN_DIV_REG_APU_MAIN_DIV_EN_Msk (0x1000UL) /*!< APU_MAIN_DIV_EN (Bitfield-Mask: 0x01) */ + #define APU_AUD_APU_MAIN_DIV_REG_APU_MAIN_DIV_Pos (0UL) /*!< APU_MAIN_DIV (Bit 0) */ + #define APU_AUD_APU_MAIN_DIV_REG_APU_MAIN_DIV_Msk (0xfffUL) /*!< APU_MAIN_DIV (Bitfield-Mask: 0xfff) */ +/* =================================================== APU_SYNC_DIV_REG ==================================================== */ + #define APU_AUD_APU_SYNC_DIV_REG_APU_SYNC_DIV_EN_Pos (8UL) /*!< APU_SYNC_DIV_EN (Bit 8) */ + #define APU_AUD_APU_SYNC_DIV_REG_APU_SYNC_DIV_EN_Msk (0x100UL) /*!< APU_SYNC_DIV_EN (Bitfield-Mask: 0x01) */ + #define APU_AUD_APU_SYNC_DIV_REG_APU_SYNC_DIV_Pos (0UL) /*!< APU_SYNC_DIV (Bit 0) */ + #define APU_AUD_APU_SYNC_DIV_REG_APU_SYNC_DIV_Msk (0x1fUL) /*!< APU_SYNC_DIV (Bitfield-Mask: 0x1f) */ +/* ================================================= APU_SYNC_DIV_SEL_REG ================================================== */ + #define APU_AUD_APU_SYNC_DIV_SEL_REG_APU_SYNC_DIV_SEL_Pos (0UL) /*!< APU_SYNC_DIV_SEL (Bit 0) */ + #define APU_AUD_APU_SYNC_DIV_SEL_REG_APU_SYNC_DIV_SEL_Msk (0x3UL) /*!< APU_SYNC_DIV_SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ APU_DSP ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== APU_CTRL_REG ====================================================== */ + #define APU_DSP_APU_CTRL_REG_DAI1_EN_Pos (0UL) /*!< DAI1_EN (Bit 0) */ + #define APU_DSP_APU_CTRL_REG_DAI1_EN_Msk (0x1UL) /*!< DAI1_EN (Bitfield-Mask: 0x01) */ +/* =================================================== APU_MUX_CTRL_REG ==================================================== */ + #define APU_DSP_APU_MUX_CTRL_REG_APU_DSP_MUX_CTL_Pos (24UL) /*!< APU_DSP_MUX_CTL (Bit 24) */ + #define APU_DSP_APU_MUX_CTRL_REG_APU_DSP_MUX_CTL_Msk (0xff000000UL) /*!< APU_DSP_MUX_CTL (Bitfield-Mask: 0xff) */ +/* =================================================== APU_PCM1_DIV_REG ==================================================== */ + #define APU_DSP_APU_PCM1_DIV_REG_PCM1_DIV_Pos (0UL) /*!< PCM1_DIV (Bit 0) */ + #define APU_DSP_APU_PCM1_DIV_REG_PCM1_DIV_Msk (0x7fUL) /*!< PCM1_DIV (Bitfield-Mask: 0x7f) */ +/* ================================================ APU_PCM1_FDIV_HIGH_REG ================================================= */ + #define APU_DSP_APU_PCM1_FDIV_HIGH_REG_PCM1_FDIV_HIGH_Pos (0UL) /*!< PCM1_FDIV_HIGH (Bit 0) */ + #define APU_DSP_APU_PCM1_FDIV_HIGH_REG_PCM1_FDIV_HIGH_Msk (0xffffUL) /*!< PCM1_FDIV_HIGH (Bitfield-Mask: 0xffff) */ +/* =================================================== APU_PCM1_FDIV_REG =================================================== */ + #define APU_DSP_APU_PCM1_FDIV_REG_PCM1_FDIV_Pos (0UL) /*!< PCM1_FDIV (Bit 0) */ + #define APU_DSP_APU_PCM1_FDIV_REG_PCM1_FDIV_Msk (0xffffffffUL) /*!< PCM1_FDIV (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== APU_PCM_CLK_REG ==================================================== */ + #define APU_DSP_APU_PCM_CLK_REG_PCM_USE_FDIV_Pos (2UL) /*!< PCM_USE_FDIV (Bit 2) */ + #define APU_DSP_APU_PCM_CLK_REG_PCM_USE_FDIV_Msk (0x4UL) /*!< PCM_USE_FDIV (Bitfield-Mask: 0x01) */ + #define APU_DSP_APU_PCM_CLK_REG_PCM1_CLK_EN_Pos (0UL) /*!< PCM1_CLK_EN (Bit 0) */ + #define APU_DSP_APU_PCM_CLK_REG_PCM1_CLK_EN_Msk (0x1UL) /*!< PCM1_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================ APU_SYNC_SRC1IN_SEL_REG ================================================ */ + #define APU_DSP_APU_SYNC_SRC1IN_SEL_REG_SRC1_IN_A_SEL_Pos (0UL) /*!< SRC1_IN_A_SEL (Bit 0) */ + #define APU_DSP_APU_SYNC_SRC1IN_SEL_REG_SRC1_IN_A_SEL_Msk (0x3UL) /*!< SRC1_IN_A_SEL (Bitfield-Mask: 0x03) */ +/* =============================================== APU_SYNC_SRC1OUT_SEL_REG ================================================ */ + #define APU_DSP_APU_SYNC_SRC1OUT_SEL_REG_SRC1_OUT_A_SEL_Pos (0UL) /*!< SRC1_OUT_A_SEL (Bit 0) */ + #define APU_DSP_APU_SYNC_SRC1OUT_SEL_REG_SRC1_OUT_A_SEL_Msk (0x3UL) /*!< SRC1_OUT_A_SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AUXADC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== FIFO0_DATA_CURR_REG ================================================== */ + #define AUXADC_FIFO0_DATA_CURR_REG_FIFO0_CURR_DATA_Pos (0UL) /*!< FIFO0_CURR_DATA (Bit 0) */ + #define AUXADC_FIFO0_DATA_CURR_REG_FIFO0_CURR_DATA_Msk (0xffffUL) /*!< FIFO0_CURR_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO0_DMA_DATA_REG =================================================== */ + #define AUXADC_FIFO0_DMA_DATA_REG_FIFO0_DMA_DATA_Pos (0UL) /*!< FIFO0_DMA_DATA (Bit 0) */ + #define AUXADC_FIFO0_DMA_DATA_REG_FIFO0_DMA_DATA_Msk (0xffffUL) /*!< FIFO0_DMA_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO1_DATA_CURR_REG ================================================== */ + #define AUXADC_FIFO1_DATA_CURR_REG_FIFO1_CURR_DATA_Pos (0UL) /*!< FIFO1_CURR_DATA (Bit 0) */ + #define AUXADC_FIFO1_DATA_CURR_REG_FIFO1_CURR_DATA_Msk (0xffffUL) /*!< FIFO1_CURR_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO1_DMA_DATA_REG =================================================== */ + #define AUXADC_FIFO1_DMA_DATA_REG_FIFO1_DMA_DATA_Pos (0UL) /*!< FIFO1_DMA_DATA (Bit 0) */ + #define AUXADC_FIFO1_DMA_DATA_REG_FIFO1_DMA_DATA_Msk (0xffffUL) /*!< FIFO1_DMA_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO2_DATA_CURR_REG ================================================== */ + #define AUXADC_FIFO2_DATA_CURR_REG_FIFO2_CURR_DATA_Pos (0UL) /*!< FIFO2_CURR_DATA (Bit 0) */ + #define AUXADC_FIFO2_DATA_CURR_REG_FIFO2_CURR_DATA_Msk (0xffffUL) /*!< FIFO2_CURR_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO2_DMA_DATA_REG =================================================== */ + #define AUXADC_FIFO2_DMA_DATA_REG_FIFO2_DMA_DATA_Pos (0UL) /*!< FIFO2_DMA_DATA (Bit 0) */ + #define AUXADC_FIFO2_DMA_DATA_REG_FIFO2_DMA_DATA_Msk (0xffffUL) /*!< FIFO2_DMA_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO3_DATA_CURR_REG ================================================== */ + #define AUXADC_FIFO3_DATA_CURR_REG_FIFO3_CURR_DATA_Pos (0UL) /*!< FIFO3_CURR_DATA (Bit 0) */ + #define AUXADC_FIFO3_DATA_CURR_REG_FIFO3_CURR_DATA_Msk (0xffffUL) /*!< FIFO3_CURR_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FIFO3_DMA_DATA_REG =================================================== */ + #define AUXADC_FIFO3_DMA_DATA_REG_FIFO3_DMA_DATA_Pos (0UL) /*!< FIFO3_DMA_DATA (Bit 0) */ + #define AUXADC_FIFO3_DMA_DATA_REG_FIFO3_DMA_DATA_Msk (0xffffUL) /*!< FIFO3_DMA_DATA (Bitfield-Mask: 0xffff) */ +/* ================================================== FXADC_CLK_CTRL_REG =================================================== */ + #define AUXADC_FXADC_CLK_CTRL_REG_FXADC12B_CLK_Pos (8UL) /*!< FXADC12B_CLK (Bit 8) */ + #define AUXADC_FXADC_CLK_CTRL_REG_FXADC12B_CLK_Msk (0xff00UL) /*!< FXADC12B_CLK (Bitfield-Mask: 0xff) */ +/* ================================================== SWITCHING_MODE_REG =================================================== */ + #define AUXADC_SWITCHING_MODE_REG_SWITCHING_MODE_Pos (0UL) /*!< SWITCHING_MODE (Bit 0) */ + #define AUXADC_SWITCHING_MODE_REG_SWITCHING_MODE_Msk (0x1ffUL) /*!< SWITCHING_MODE (Bitfield-Mask: 0x1ff) */ +/* ================================================== TIMESTAMP_CTRL_REG =================================================== */ + #define AUXADC_TIMESTAMP_CTRL_REG_TIMESTAMP_12B_Pos (8UL) /*!< TIMESTAMP_12B (Bit 8) */ + #define AUXADC_TIMESTAMP_CTRL_REG_TIMESTAMP_12B_Msk (0xf00UL) /*!< TIMESTAMP_12B (Bitfield-Mask: 0x0f) */ +/* =================================================== XADC12B_CTRL_REG ==================================================== */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_DATA_FORMAT_Pos (8UL) /*!< ADC12B_DATA_FORMAT (Bit 8) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_DATA_FORMAT_Msk (0x100UL) /*!< ADC12B_DATA_FORMAT (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_TRIM_Pos (5UL) /*!< ADC12B_TRIM (Bit 5) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_TRIM_Msk (0xe0UL) /*!< ADC12B_TRIM (Bitfield-Mask: 0x07) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_CS_Pos (2UL) /*!< ADC12B_CS (Bit 2) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_CS_Msk (0x1cUL) /*!< ADC12B_CS (Bitfield-Mask: 0x07) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_PWRDOEN_Pos (1UL) /*!< ADC12B_PWRDOEN (Bit 1) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_PWRDOEN_Msk (0x2UL) /*!< ADC12B_PWRDOEN (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_RESET_Pos (0UL) /*!< ADC12B_RESET (Bit 0) */ + #define AUXADC_XADC12B_CTRL_REG_ADC12B_RESET_Msk (0x1UL) /*!< ADC12B_RESET (Bitfield-Mask: 0x01) */ +/* ================================================== XADC12B_DMA_EN_REG =================================================== */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO3_ENABLE_Pos (3UL) /*!< FIFO3_ENABLE (Bit 3) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO3_ENABLE_Msk (0x8UL) /*!< FIFO3_ENABLE (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO2_ENABLE_Pos (2UL) /*!< FIFO2_ENABLE (Bit 2) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO2_ENABLE_Msk (0x4UL) /*!< FIFO2_ENABLE (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO1_ENABLE_Pos (1UL) /*!< FIFO1_ENABLE (Bit 1) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO1_ENABLE_Msk (0x2UL) /*!< FIFO1_ENABLE (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO0_ENABLE_Pos (0UL) /*!< FIFO0_ENABLE (Bit 0) */ + #define AUXADC_XADC12B_DMA_EN_REG_FIFO0_ENABLE_Msk (0x1UL) /*!< FIFO0_ENABLE (Bitfield-Mask: 0x01) */ +/* ============================================== XADC12B_FIFO_INTR_MASK_REG =============================================== */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO3_MASK_Pos (7UL) /*!< FL_FIFO3_MASK (Bit 7) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO3_MASK_Msk (0x80UL) /*!< FL_FIFO3_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO2_MASK_Pos (6UL) /*!< FL_FIFO2_MASK (Bit 6) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO2_MASK_Msk (0x40UL) /*!< FL_FIFO2_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO1_MASK_Pos (5UL) /*!< FL_FIFO1_MASK (Bit 5) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO1_MASK_Msk (0x20UL) /*!< FL_FIFO1_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO0_MASK_Pos (4UL) /*!< FL_FIFO0_MASK (Bit 4) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_FL_FIFO0_MASK_Msk (0x10UL) /*!< FL_FIFO0_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO3_MASK_Pos (3UL) /*!< HL_FIFO3_MASK (Bit 3) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO3_MASK_Msk (0x8UL) /*!< HL_FIFO3_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO2_MASK_Pos (2UL) /*!< HL_FIFO2_MASK (Bit 2) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO2_MASK_Msk (0x4UL) /*!< HL_FIFO2_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO1_MASK_Pos (1UL) /*!< HL_FIFO1_MASK (Bit 1) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO1_MASK_Msk (0x2UL) /*!< HL_FIFO1_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO0_MASK_Pos (0UL) /*!< HL_FIFO0_MASK (Bit 0) */ + #define AUXADC_XADC12B_FIFO_INTR_MASK_REG_HL_FIFO0_MASK_Msk (0x1UL) /*!< HL_FIFO0_MASK (Bitfield-Mask: 0x01) */ +/* ================================================ XADC12B_INTR_STATUS_REG ================================================ */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO3_STS_Pos (19UL) /*!< DIFF_THR_FIFO3_STS (Bit 19) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO3_STS_Msk (0x80000UL) /*!< DIFF_THR_FIFO3_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO2_STS_Pos (18UL) /*!< DIFF_THR_FIFO2_STS (Bit 18) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO2_STS_Msk (0x40000UL) /*!< DIFF_THR_FIFO2_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO1_STS_Pos (17UL) /*!< DIFF_THR_FIFO1_STS (Bit 17) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO1_STS_Msk (0x20000UL) /*!< DIFF_THR_FIFO1_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO0_STS_Pos (16UL) /*!< DIFF_THR_FIFO0_STS (Bit 16) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_DIFF_THR_FIFO0_STS_Msk (0x10000UL) /*!< DIFF_THR_FIFO0_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO3_STS_Pos (15UL) /*!< UNDER_THR_FIFO3_STS (Bit 15) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO3_STS_Msk (0x8000UL) /*!< UNDER_THR_FIFO3_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO2_STS_Pos (14UL) /*!< UNDER_THR_FIFO2_STS (Bit 14) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO2_STS_Msk (0x4000UL) /*!< UNDER_THR_FIFO2_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO1_STS_Pos (13UL) /*!< UNDER_THR_FIFO1_STS (Bit 13) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO1_STS_Msk (0x2000UL) /*!< UNDER_THR_FIFO1_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO0_STS_Pos (12UL) /*!< UNDER_THR_FIFO0_STS (Bit 12) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_UNDER_THR_FIFO0_STS_Msk (0x1000UL) /*!< UNDER_THR_FIFO0_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO3_STS_Pos (11UL) /*!< OVER_THR_FIFO3_STS (Bit 11) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO3_STS_Msk (0x800UL) /*!< OVER_THR_FIFO3_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO2_STS_Pos (10UL) /*!< OVER_THR_FIFO2_STS (Bit 10) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO2_STS_Msk (0x400UL) /*!< OVER_THR_FIFO2_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO1_STS_Pos (9UL) /*!< OVER_THR_FIFO1_STS (Bit 9) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO1_STS_Msk (0x200UL) /*!< OVER_THR_FIFO1_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO0_STS_Pos (8UL) /*!< OVER_THR_FIFO0_STS (Bit 8) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_OVER_THR_FIFO0_STS_Msk (0x100UL) /*!< OVER_THR_FIFO0_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO3_STS_Pos (7UL) /*!< FL_FIFO3_STS (Bit 7) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO3_STS_Msk (0x80UL) /*!< FL_FIFO3_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO2_STS_Pos (6UL) /*!< FL_FIFO2_STS (Bit 6) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO2_STS_Msk (0x40UL) /*!< FL_FIFO2_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO1_STS_Pos (5UL) /*!< FL_FIFO1_STS (Bit 5) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO1_STS_Msk (0x20UL) /*!< FL_FIFO1_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO0_STS_Pos (4UL) /*!< FL_FIFO0_STS (Bit 4) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_FL_FIFO0_STS_Msk (0x10UL) /*!< FL_FIFO0_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO3_STS_Pos (3UL) /*!< HL_FIFO3_STS (Bit 3) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO3_STS_Msk (0x8UL) /*!< HL_FIFO3_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO2_STS_Pos (2UL) /*!< HL_FIFO2_STS (Bit 2) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO2_STS_Msk (0x4UL) /*!< HL_FIFO2_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO1_STS_Pos (1UL) /*!< HL_FIFO1_STS (Bit 1) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO1_STS_Msk (0x2UL) /*!< HL_FIFO1_STS (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO0_STS_Pos (0UL) /*!< HL_FIFO0_STS (Bit 0) */ + #define AUXADC_XADC12B_INTR_STATUS_REG_HL_FIFO0_STS_Msk (0x1UL) /*!< HL_FIFO0_STS (Bitfield-Mask: 0x01) */ +/* =============================================== XADC12B_INT_THR_DIFF_REG ================================================ */ + #define AUXADC_XADC12B_INT_THR_DIFF_REG_DIFF_THR_VAL_Pos (1UL) /*!< DIFF_THR_VAL (Bit 1) */ + #define AUXADC_XADC12B_INT_THR_DIFF_REG_DIFF_THR_VAL_Msk (0xfffeUL) /*!< DIFF_THR_VAL (Bitfield-Mask: 0x7fff) */ + #define AUXADC_XADC12B_INT_THR_DIFF_REG_DIFF_THR_EN_Pos (0UL) /*!< DIFF_THR_EN (Bit 0) */ + #define AUXADC_XADC12B_INT_THR_DIFF_REG_DIFF_THR_EN_Msk (0x1UL) /*!< DIFF_THR_EN (Bitfield-Mask: 0x01) */ +/* =============================================== XADC12B_INT_THR_OVER_REG ================================================ */ + #define AUXADC_XADC12B_INT_THR_OVER_REG_OVER_THR_VAL_Pos (1UL) /*!< OVER_THR_VAL (Bit 1) */ + #define AUXADC_XADC12B_INT_THR_OVER_REG_OVER_THR_VAL_Msk (0xfffeUL) /*!< OVER_THR_VAL (Bitfield-Mask: 0x7fff) */ + #define AUXADC_XADC12B_INT_THR_OVER_REG_OVER_THR_EN_Pos (0UL) /*!< OVER_THR_EN (Bit 0) */ + #define AUXADC_XADC12B_INT_THR_OVER_REG_OVER_THR_EN_Msk (0x1UL) /*!< OVER_THR_EN (Bitfield-Mask: 0x01) */ +/* =============================================== XADC12B_INT_THR_UNDER_REG =============================================== */ + #define AUXADC_XADC12B_INT_THR_UNDER_REG_UNDER_THR_VAL_Pos (1UL) /*!< UNDER_THR_VAL (Bit 1) */ + #define AUXADC_XADC12B_INT_THR_UNDER_REG_UNDER_THR_VAL_Msk (0xfffeUL) /*!< UNDER_THR_VAL (Bitfield-Mask: 0x7fff) */ + #define AUXADC_XADC12B_INT_THR_UNDER_REG_UNDER_THR_EN_Pos (0UL) /*!< UNDER_THR_EN (Bit 0) */ + #define AUXADC_XADC12B_INT_THR_UNDER_REG_UNDER_THR_EN_Msk (0x1UL) /*!< UNDER_THR_EN (Bitfield-Mask: 0x01) */ +/* ================================================= XADC12B_RM_SAMPLE_REG ================================================= */ + #define AUXADC_XADC12B_RM_SAMPLE_REG_XADC12B_RM_SAMPLE_Pos (8UL) /*!< XADC12B_RM_SAMPLE (Bit 8) */ + #define AUXADC_XADC12B_RM_SAMPLE_REG_XADC12B_RM_SAMPLE_Msk (0xff00UL) /*!< XADC12B_RM_SAMPLE (Bitfield-Mask: 0xff) */ +/* ================================================= XADC12B_ST_SAMPLE_REG ================================================= */ + #define AUXADC_XADC12B_ST_SAMPLE_REG_XADC12B_SP_INTERVAL_Pos (4UL) /*!< XADC12B_SP_INTERVAL (Bit 4) */ + #define AUXADC_XADC12B_ST_SAMPLE_REG_XADC12B_SP_INTERVAL_Msk (0xf0UL) /*!< XADC12B_SP_INTERVAL (Bitfield-Mask: 0x0f) */ +/* =============================================== XADC12B_THR_INTR_CLR_REG ================================================ */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO3_CLR_Pos (11UL) /*!< DIFF_THR_FIFO3_CLR (Bit 11) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO3_CLR_Msk (0x800UL) /*!< DIFF_THR_FIFO3_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO2_CLR_Pos (10UL) /*!< DIFF_THR_FIFO2_CLR (Bit 10) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO2_CLR_Msk (0x400UL) /*!< DIFF_THR_FIFO2_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO1_CLR_Pos (9UL) /*!< DIFF_THR_FIFO1_CLR (Bit 9) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO1_CLR_Msk (0x200UL) /*!< DIFF_THR_FIFO1_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO0_CLR_Pos (8UL) /*!< DIFF_THR_FIFO0_CLR (Bit 8) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_DIFF_THR_FIFO0_CLR_Msk (0x100UL) /*!< DIFF_THR_FIFO0_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO3_CLR_Pos (7UL) /*!< UNDER_THR_FIFO3_CLR (Bit 7) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO3_CLR_Msk (0x80UL) /*!< UNDER_THR_FIFO3_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO2_CLR_Pos (6UL) /*!< UNDER_THR_FIFO2_CLR (Bit 6) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO2_CLR_Msk (0x40UL) /*!< UNDER_THR_FIFO2_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO1_CLR_Pos (5UL) /*!< UNDER_THR_FIFO1_CLR (Bit 5) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO1_CLR_Msk (0x20UL) /*!< UNDER_THR_FIFO1_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO0_CLR_Pos (4UL) /*!< UNDER_THR_FIFO0_CLR (Bit 4) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_UNDER_THR_FIFO0_CLR_Msk (0x10UL) /*!< UNDER_THR_FIFO0_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO3_CLR_Pos (3UL) /*!< OVER_THR_FIFO3_CLR (Bit 3) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO3_CLR_Msk (0x8UL) /*!< OVER_THR_FIFO3_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO2_CLR_Pos (2UL) /*!< OVER_THR_FIFO2_CLR (Bit 2) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO2_CLR_Msk (0x4UL) /*!< OVER_THR_FIFO2_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO1_CLR_Pos (1UL) /*!< OVER_THR_FIFO1_CLR (Bit 1) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO1_CLR_Msk (0x2UL) /*!< OVER_THR_FIFO1_CLR (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO0_CLR_Pos (0UL) /*!< OVER_THR_FIFO0_CLR (Bit 0) */ + #define AUXADC_XADC12B_THR_INTR_CLR_REG_OVER_THR_FIFO0_CLR_Msk (0x1UL) /*!< OVER_THR_FIFO0_CLR (Bitfield-Mask: 0x01) */ +/* =============================================== XADC12B_THR_INTR_MASK_REG =============================================== */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO3_MASK_Pos (11UL) /*!< DIFF_THR_FIFO3_MASK (Bit 11) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO3_MASK_Msk (0x800UL) /*!< DIFF_THR_FIFO3_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO2_MASK_Pos (10UL) /*!< DIFF_THR_FIFO2_MASK (Bit 10) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO2_MASK_Msk (0x400UL) /*!< DIFF_THR_FIFO2_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO1_MASK_Pos (9UL) /*!< DIFF_THR_FIFO1_MASK (Bit 9) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO1_MASK_Msk (0x200UL) /*!< DIFF_THR_FIFO1_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO0_MASK_Pos (8UL) /*!< DIFF_THR_FIFO0_MASK (Bit 8) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_DIFF_THR_FIFO0_MASK_Msk (0x100UL) /*!< DIFF_THR_FIFO0_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO3_MASK_Pos (7UL) /*!< UNDER_THR_FIFO3_MASK (Bit 7) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO3_MASK_Msk (0x80UL) /*!< UNDER_THR_FIFO3_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO2_MASK_Pos (6UL) /*!< UNDER_THR_FIFO2_MASK (Bit 6) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO2_MASK_Msk (0x40UL) /*!< UNDER_THR_FIFO2_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO1_MASK_Pos (5UL) /*!< UNDER_THR_FIFO1_MASK (Bit 5) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO1_MASK_Msk (0x20UL) /*!< UNDER_THR_FIFO1_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO0_MASK_Pos (4UL) /*!< UNDER_THR_FIFO0_MASK (Bit 4) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_UNDER_THR_FIFO0_MASK_Msk (0x10UL) /*!< UNDER_THR_FIFO0_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO3_MASK_Pos (3UL) /*!< OVER_THR_FIFO3_MASK (Bit 3) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO3_MASK_Msk (0x8UL) /*!< OVER_THR_FIFO3_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO2_MASK_Pos (2UL) /*!< OVER_THR_FIFO2_MASK (Bit 2) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO2_MASK_Msk (0x4UL) /*!< OVER_THR_FIFO2_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO1_MASK_Pos (1UL) /*!< OVER_THR_FIFO1_MASK (Bit 1) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO1_MASK_Msk (0x2UL) /*!< OVER_THR_FIFO1_MASK (Bitfield-Mask: 0x01) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO0_MASK_Pos (0UL) /*!< OVER_THR_FIFO0_MASK (Bit 0) */ + #define AUXADC_XADC12B_THR_INTR_MASK_REG_OVER_THR_FIFO0_MASK_Msk (0x1UL) /*!< OVER_THR_FIFO0_MASK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CACHE_ASSOCCFG_REG =================================================== */ + #define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL) /*!< CACHE_ASSOC (Bit 0) */ + #define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL) /*!< CACHE_ASSOC (Bitfield-Mask: 0x03) */ +/* ================================================= CACHE_CPU_M_HADDR_REG ================================================= */ + #define CACHE_CACHE_CPU_M_HADDR_REG_CACHE_CPU_M_HADDR_Pos (0UL) /*!< CACHE_CPU_M_HADDR (Bit 0) */ + #define CACHE_CACHE_CPU_M_HADDR_REG_CACHE_CPU_M_HADDR_Msk (0xffffffffUL) /*!< CACHE_CPU_M_HADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CACHE_CTRL1_REG ==================================================== */ + #define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos (1UL) /*!< CACHE_RES1 (Bit 1) */ + #define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk (0x2UL) /*!< CACHE_RES1 (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL) /*!< CACHE_FLUSH (Bit 0) */ + #define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL) /*!< CACHE_FLUSH (Bitfield-Mask: 0x01) */ +/* ==================================================== CACHE_CTRL2_REG ==================================================== */ + #define CACHE_CACHE_CTRL2_REG_CACHE_ROM_REGION_EN_Pos (22UL) /*!< CACHE_ROM_REGION_EN (Bit 22) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_ROM_REGION_EN_Msk (0x400000UL) /*!< CACHE_ROM_REGION_EN (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_READY_Pos (21UL) /*!< CACHE_READY (Bit 21) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_READY_Msk (0x200000UL) /*!< CACHE_READY (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (20UL) /*!< CACHE_RAM_INIT (Bit 20) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x100000UL) /*!< CACHE_RAM_INIT (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSHED_Pos (19UL) /*!< CACHE_FLUSHED (Bit 19) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSHED_Msk (0x80000UL) /*!< CACHE_FLUSHED (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (18UL) /*!< CACHE_FLUSH_DISABLE (Bit 18) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x40000UL) /*!< CACHE_FLUSH_DISABLE (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (16UL) /*!< CACHE_USE_FULL_DB_RANGE (Bit 16) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0x30000UL) /*!< CACHE_USE_FULL_DB_RANGE (Bitfield-Mask: 0x03) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (15UL) /*!< CACHE_MHCLKEN_DISABLE (Bit 15) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x8000UL) /*!< CACHE_MHCLKEN_DISABLE (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (14UL) /*!< CACHE_CWF_DISABLE (Bit 14) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x4000UL) /*!< CACHE_CWF_DISABLE (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (13UL) /*!< CACHE_CGEN (Bit 13) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x2000UL) /*!< CACHE_CGEN (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (12UL) /*!< CACHE_WEN (Bit 12) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x1000UL) /*!< CACHE_WEN (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL) /*!< CACHE_LEN (Bit 0) */ + #define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0xfffUL) /*!< CACHE_LEN (Bitfield-Mask: 0xfff) */ +/* ==================================================== CACHE_CTRL3_REG ==================================================== */ + #define CACHE_CACHE_CTRL3_REG_CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS_Pos (8UL) /*!< CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS (Bit 8) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS_Msk (0x100UL) /*!< CACHE_TM_CBUS_SLOW_PERIPH_FOR_SBUS (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos (7UL) /*!< CACHE_CONTROLLER_RESET (Bit 7) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk (0x80UL) /*!< CACHE_CONTROLLER_RESET (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos (4UL) /*!< CACHE_RAM_SIZE_RESET_VALUE (Bit 4) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk (0x70UL) /*!< CACHE_RAM_SIZE_RESET_VALUE (Bitfield-Mask: 0x07) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos (2UL) /*!< CACHE_LINE_SIZE_RESET_VALUE (Bit 2) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk (0xcUL) /*!< CACHE_LINE_SIZE_RESET_VALUE (Bitfield-Mask: 0x03) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos (0UL) /*!< CACHE_ASSOCIATIVITY_RESET_VALUE (Bit 0) */ + #define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk (0x3UL) /*!< CACHE_ASSOCIATIVITY_RESET_VALUE (Bitfield-Mask: 0x03) */ +/* ================================================ CACHE_CTRLR_M_HADDR_REG ================================================ */ + #define CACHE_CACHE_CTRLR_M_HADDR_REG_CACHE_CTRLR_M_HADDR_Pos (0UL) /*!< CACHE_CTRLR_M_HADDR (Bit 0) */ + #define CACHE_CACHE_CTRLR_M_HADDR_REG_CACHE_CTRLR_M_HADDR_Msk (0xffffffffUL) /*!< CACHE_CTRLR_M_HADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CACHE_FLASH_REG ==================================================== */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL) /*!< FLASH_REGION_BASE (Bit 16) */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL) /*!< FLASH_REGION_BASE (Bitfield-Mask: 0xffff) */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL) /*!< FLASH_REGION_OFFSET (Bit 4) */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL) /*!< FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff) */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL) /*!< FLASH_REGION_SIZE (Bit 0) */ + #define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0xfUL) /*!< FLASH_REGION_SIZE (Bitfield-Mask: 0x0f) */ +/* ================================================== CACHE_LNSIZECFG_REG ================================================== */ + #define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL) /*!< CACHE_LINE (Bit 0) */ + #define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL) /*!< CACHE_LINE (Bitfield-Mask: 0x03) */ +/* ================================================== CACHE_MRM_CTRL_REG =================================================== */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bit 4) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bit 3) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL) /*!< MRM_IRQ_TINT_STATUS (Bit 2) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL) /*!< MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL) /*!< MRM_IRQ_MASK (Bit 1) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL) /*!< MRM_IRQ_MASK (Bitfield-Mask: 0x01) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL) /*!< MRM_START (Bit 0) */ + #define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL) /*!< MRM_START (Bitfield-Mask: 0x01) */ +/* ================================================= CACHE_MRM_HITS1WS_REG ================================================= */ + #define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL) /*!< MRM_HITS1WS (Bit 0) */ + #define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL) /*!< MRM_HITS1WS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CACHE_MRM_HITS_REG =================================================== */ + #define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL) /*!< MRM_HITS (Bit 0) */ + #define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL) /*!< MRM_HITS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CACHE_MRM_HITS_THRES_REG ================================================ */ + #define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL) /*!< MRM_HITS_THRES (Bit 0) */ + #define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL) /*!< MRM_HITS_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CACHE_MRM_MISSES_REG ================================================== */ + #define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL) /*!< MRM_MISSES (Bit 0) */ + #define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL) /*!< MRM_MISSES (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CACHE_MRM_MISSES_THRES_REG =============================================== */ + #define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL) /*!< MRM_MISSES_THRES (Bit 0) */ + #define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL) /*!< MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CACHE_MRM_TINT_REG =================================================== */ + #define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL) /*!< MRM_TINT (Bit 0) */ + #define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL) /*!< MRM_TINT (Bitfield-Mask: 0x7ffff) */ +/* ================================================ CACHE_M_HADDR_MAP0_REG ================================================= */ + #define CACHE_CACHE_M_HADDR_MAP0_REG_CACHE_M_HADDR_MAP0_Pos (0UL) /*!< CACHE_M_HADDR_MAP0 (Bit 0) */ + #define CACHE_CACHE_M_HADDR_MAP0_REG_CACHE_M_HADDR_MAP0_Msk (0xffffffffUL) /*!< CACHE_M_HADDR_MAP0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SWD_RESET_REG ===================================================== */ + #define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL) /*!< SWD_HW_RESET_REQ (Bit 0) */ + #define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL) /*!< SWD_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CC312 ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CC312_AES_BUSY_REG =================================================== */ + #define CC312_CC312_AES_BUSY_REG_CC312_AES_BUSY_Pos (0UL) /*!< CC312_AES_BUSY (Bit 0) */ + #define CC312_CC312_AES_BUSY_REG_CC312_AES_BUSY_Msk (0x1UL) /*!< CC312_AES_BUSY (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_AES_CLK_ENABLE_REG ================================================ */ + #define CC312_CC312_AES_CLK_ENABLE_REG_CC312_AES_CLK_EN_Pos (0UL) /*!< CC312_AES_CLK_EN (Bit 0) */ + #define CC312_CC312_AES_CLK_ENABLE_REG_CC312_AES_CLK_EN_Msk (0x1UL) /*!< CC312_AES_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_AES_CMAC_INIT_REG ================================================ */ + #define CC312_CC312_AES_CMAC_INIT_REG_CC312_AES_CMAC_INIT_Pos (0UL) /*!< CC312_AES_CMAC_INIT (Bit 0) */ + #define CC312_CC312_AES_CMAC_INIT_REG_CC312_AES_CMAC_INIT_Msk (0x1UL) /*!< CC312_AES_CMAC_INIT (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_AES_CMAC_SIZE0_KICK_REG ============================================= */ + #define CC312_CC312_AES_CMAC_SIZE0_KICK_REG_CC312_AES_CMAC_SIZE0_KICK_Pos (0UL) /*!< CC312_AES_CMAC_SIZE0_KICK (Bit 0) */ + #define CC312_CC312_AES_CMAC_SIZE0_KICK_REG_CC312_AES_CMAC_SIZE0_KICK_Msk (0x1UL) /*!< CC312_AES_CMAC_SIZE0_KICK (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_AES_CONTROL_REG ================================================= */ + #define CC312_CC312_AES_CONTROL_REG_CC312_DIRECT_ACCESS_Pos (31UL) /*!< CC312_DIRECT_ACCESS (Bit 31) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_DIRECT_ACCESS_Msk (0x80000000UL) /*!< CC312_DIRECT_ACCESS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_XOR_CRYPTOKEY_Pos (29UL) /*!< CC312_AES_XOR_CRYPTOKEY (Bit 29) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_XOR_CRYPTOKEY_Msk (0x20000000UL) /*!< CC312_AES_XOR_CRYPTOKEY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_OUT_MID_TUN_TO_HASH_Pos (28UL) /*!< CC312_AES_OUT_MID_TUN_TO_HASH (Bit 28) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_OUT_MID_TUN_TO_HASH_Msk (0x10000000UL) /*!< CC312_AES_OUT_MID_TUN_TO_HASH (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL_B1_PAD_EN_Pos (26UL) /*!< CC312_AES_TUNNEL_B1_PAD_EN (Bit 26) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL_B1_PAD_EN_Msk (0x4000000UL) /*!< CC312_AES_TUNNEL_B1_PAD_EN (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_OUTPUT_MID_TUNNEL_DATA_Pos (25UL) /*!< CC312_AES_OUTPUT_MID_TUNNEL_DATA (Bit 25) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_OUTPUT_MID_TUNNEL_DATA_Msk (0x2000000UL) /*!< CC312_AES_OUTPUT_MID_TUNNEL_DATA (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL0_ENCRYPT_Pos (24UL) /*!< CC312_AES_TUNNEL0_ENCRYPT (Bit 24) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL0_ENCRYPT_Msk (0x1000000UL) /*!< CC312_AES_TUNNEL0_ENCRYPT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUN_B1_USES_PADDED_DATA_IN_Pos (23UL) /*!< CC312_AES_TUN_B1_USES_PADDED_DATA_IN (Bit 23) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUN_B1_USES_PADDED_DATA_IN_Msk (0x800000UL) /*!< CC312_AES_TUN_B1_USES_PADDED_DATA_IN (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL1_DECRYPT_Pos (22UL) /*!< CC312_AES_TUNNEL1_DECRYPT (Bit 22) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL1_DECRYPT_Msk (0x400000UL) /*!< CC312_AES_TUNNEL1_DECRYPT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_NK_KEY1_Pos (14UL) /*!< CC312_NK_KEY1 (Bit 14) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_NK_KEY1_Msk (0xc000UL) /*!< CC312_NK_KEY1 (Bitfield-Mask: 0x03) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_NK_KEY0_Pos (12UL) /*!< CC312_NK_KEY0 (Bit 12) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_NK_KEY0_Msk (0x3000UL) /*!< CC312_NK_KEY0 (Bitfield-Mask: 0x03) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_CBC_IS_BITLOCKER_Pos (11UL) /*!< CC312_CBC_IS_BITLOCKER (Bit 11) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_CBC_IS_BITLOCKER_Msk (0x800UL) /*!< CC312_CBC_IS_BITLOCKER (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL_IS_ON_Pos (10UL) /*!< CC312_AES_TUNNEL_IS_ON (Bit 10) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_AES_TUNNEL_IS_ON_Msk (0x400UL) /*!< CC312_AES_TUNNEL_IS_ON (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_CBC_IS_ESSIV_Pos (8UL) /*!< CC312_CBC_IS_ESSIV (Bit 8) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_CBC_IS_ESSIV_Msk (0x100UL) /*!< CC312_CBC_IS_ESSIV (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE_KEY1_Pos (5UL) /*!< CC312_MODE_KEY1 (Bit 5) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE_KEY1_Msk (0xe0UL) /*!< CC312_MODE_KEY1 (Bitfield-Mask: 0x07) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE_KEY0_Pos (2UL) /*!< CC312_MODE_KEY0 (Bit 2) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE_KEY0_Msk (0x1cUL) /*!< CC312_MODE_KEY0 (Bitfield-Mask: 0x07) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE0_IS_CBC_CTS_Pos (1UL) /*!< CC312_MODE0_IS_CBC_CTS (Bit 1) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_MODE0_IS_CBC_CTS_Msk (0x2UL) /*!< CC312_MODE0_IS_CBC_CTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_DEC_KEY0_Pos (0UL) /*!< CC312_DEC_KEY0 (Bit 0) */ + #define CC312_CC312_AES_CONTROL_REG_CC312_DEC_KEY0_Msk (0x1UL) /*!< CC312_DEC_KEY0 (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_AES_CTR_0_0_REG ================================================= */ + #define CC312_CC312_AES_CTR_0_0_REG_CC312_AES_CTR_0_0_Pos (0UL) /*!< CC312_AES_CTR_0_0 (Bit 0) */ + #define CC312_CC312_AES_CTR_0_0_REG_CC312_AES_CTR_0_0_Msk (0xffffffffUL) /*!< CC312_AES_CTR_0_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_CTR_0_1_REG ================================================= */ + #define CC312_CC312_AES_CTR_0_1_REG_CC312_AES_CTR_0_1_Pos (0UL) /*!< CC312_AES_CTR_0_1 (Bit 0) */ + #define CC312_CC312_AES_CTR_0_1_REG_CC312_AES_CTR_0_1_Msk (0xffffffffUL) /*!< CC312_AES_CTR_0_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_CTR_0_2_REG ================================================= */ + #define CC312_CC312_AES_CTR_0_2_REG_CC312_AES_CTR_0_2_Pos (0UL) /*!< CC312_AES_CTR_0_2 (Bit 0) */ + #define CC312_CC312_AES_CTR_0_2_REG_CC312_AES_CTR_0_2_Msk (0xffffffffUL) /*!< CC312_AES_CTR_0_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_CTR_0_3_REG ================================================= */ + #define CC312_CC312_AES_CTR_0_3_REG_CC312_AES_CTR_0_3_Pos (0UL) /*!< CC312_AES_CTR_0_3 (Bit 0) */ + #define CC312_CC312_AES_CTR_0_3_REG_CC312_AES_CTR_0_3_Msk (0xffffffffUL) /*!< CC312_AES_CTR_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_AES_CTR_NO_INCREMENT_REG ============================================= */ + #define CC312_CC312_AES_CTR_NO_INCREMENT_REG_CC312_AES_CTR_NO_INCREMENT_Pos (0UL) /*!< CC312_AES_CTR_NO_INCREMENT (Bit 0) */ + #define CC312_CC312_AES_CTR_NO_INCREMENT_REG_CC312_AES_CTR_NO_INCREMENT_Msk (0x1UL) /*!< CC312_AES_CTR_NO_INCREMENT (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_AES_DFA_ERR_STATUS_REG ============================================== */ + #define CC312_CC312_AES_DFA_ERR_STATUS_REG_CC312_AES_DFA_ERR_STATUS_Pos (0UL) /*!< CC312_AES_DFA_ERR_STATUS (Bit 0) */ + #define CC312_CC312_AES_DFA_ERR_STATUS_REG_CC312_AES_DFA_ERR_STATUS_Msk (0x1UL) /*!< CC312_AES_DFA_ERR_STATUS (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_AES_DFA_IS_ON_REG ================================================ */ + #define CC312_CC312_AES_DFA_IS_ON_REG_CC312_AES_DFA_IS_ON_Pos (0UL) /*!< CC312_AES_DFA_IS_ON (Bit 0) */ + #define CC312_CC312_AES_DFA_IS_ON_REG_CC312_AES_DFA_IS_ON_Msk (0x1UL) /*!< CC312_AES_DFA_IS_ON (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_AES_HW_FLAGS_REG ================================================= */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_DFA_CNTRMSR_EXIST_Pos (12UL) /*!< CC312_DFA_CNTRMSR_EXIST (Bit 12) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_DFA_CNTRMSR_EXIST_Msk (0x1000UL) /*!< CC312_DFA_CNTRMSR_EXIST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_SECOND_REGS_SET_EXIST_Pos (11UL) /*!< CC312_SECOND_REGS_SET_EXIST (Bit 11) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_SECOND_REGS_SET_EXIST_Msk (0x800UL) /*!< CC312_SECOND_REGS_SET_EXIST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_aes_tunnel_exists_Pos (10UL) /*!< CC312_aes_tunnel_exists (Bit 10) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_aes_tunnel_exists_Msk (0x400UL) /*!< CC312_aes_tunnel_exists (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_AES_SUPPORT_PREV_IV_Pos (9UL) /*!< CC312_AES_SUPPORT_PREV_IV (Bit 9) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_AES_SUPPORT_PREV_IV_Msk (0x200UL) /*!< CC312_AES_SUPPORT_PREV_IV (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_USE_5_SBOXES_Pos (8UL) /*!< CC312_USE_5_SBOXES (Bit 8) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_USE_5_SBOXES_Msk (0x100UL) /*!< CC312_USE_5_SBOXES (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_USE_SBOX_TABLE_Pos (5UL) /*!< CC312_USE_SBOX_TABLE (Bit 5) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_USE_SBOX_TABLE_Msk (0x20UL) /*!< CC312_USE_SBOX_TABLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_ONLY_ENCRYPT_Pos (4UL) /*!< CC312_ONLY_ENCRYPT (Bit 4) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_ONLY_ENCRYPT_Msk (0x10UL) /*!< CC312_ONLY_ENCRYPT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_CTR_EXIST_Pos (3UL) /*!< CC312_CTR_EXIST (Bit 3) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_CTR_EXIST_Msk (0x8UL) /*!< CC312_CTR_EXIST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_DPA_CNTRMSR_EXIST_Pos (2UL) /*!< CC312_DPA_CNTRMSR_EXIST (Bit 2) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_DPA_CNTRMSR_EXIST_Msk (0x4UL) /*!< CC312_DPA_CNTRMSR_EXIST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_AES_LARGE_RKEK_Pos (1UL) /*!< CC312_AES_LARGE_RKEK (Bit 1) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_AES_LARGE_RKEK_Msk (0x2UL) /*!< CC312_AES_LARGE_RKEK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_SUPPORT_256_192_KEY_Pos (0UL) /*!< CC312_SUPPORT_256_192_KEY (Bit 0) */ + #define CC312_CC312_AES_HW_FLAGS_REG_CC312_SUPPORT_256_192_KEY_Msk (0x1UL) /*!< CC312_SUPPORT_256_192_KEY (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_AES_IV_0_0_REG ================================================== */ + #define CC312_CC312_AES_IV_0_0_REG_CC312_AES_IV_0_0_Pos (0UL) /*!< CC312_AES_IV_0_0 (Bit 0) */ + #define CC312_CC312_AES_IV_0_0_REG_CC312_AES_IV_0_0_Msk (0xffffffffUL) /*!< CC312_AES_IV_0_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_0_1_REG ================================================== */ + #define CC312_CC312_AES_IV_0_1_REG_CC312_AES_IV_0_1_Pos (0UL) /*!< CC312_AES_IV_0_1 (Bit 0) */ + #define CC312_CC312_AES_IV_0_1_REG_CC312_AES_IV_0_1_Msk (0xffffffffUL) /*!< CC312_AES_IV_0_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_0_2_REG ================================================== */ + #define CC312_CC312_AES_IV_0_2_REG_CC312_AES_IV_0_2_Pos (0UL) /*!< CC312_AES_IV_0_2 (Bit 0) */ + #define CC312_CC312_AES_IV_0_2_REG_CC312_AES_IV_0_2_Msk (0xffffffffUL) /*!< CC312_AES_IV_0_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_0_3_REG ================================================== */ + #define CC312_CC312_AES_IV_0_3_REG_CC312_AES_IV_0_3_Pos (0UL) /*!< CC312_AES_IV_0_3 (Bit 0) */ + #define CC312_CC312_AES_IV_0_3_REG_CC312_AES_IV_0_3_Msk (0xffffffffUL) /*!< CC312_AES_IV_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_1_0_REG ================================================== */ + #define CC312_CC312_AES_IV_1_0_REG_CC312_AES_IV_1_0_Pos (0UL) /*!< CC312_AES_IV_1_0 (Bit 0) */ + #define CC312_CC312_AES_IV_1_0_REG_CC312_AES_IV_1_0_Msk (0xffffffffUL) /*!< CC312_AES_IV_1_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_1_1_REG ================================================== */ + #define CC312_CC312_AES_IV_1_1_REG_CC312_AES_IV_1_1_Pos (0UL) /*!< CC312_AES_IV_1_1 (Bit 0) */ + #define CC312_CC312_AES_IV_1_1_REG_CC312_AES_IV_1_1_Msk (0xffffffffUL) /*!< CC312_AES_IV_1_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_1_2_REG ================================================== */ + #define CC312_CC312_AES_IV_1_2_REG_CC312_AES_IV_1_2_Pos (0UL) /*!< CC312_AES_IV_1_2 (Bit 0) */ + #define CC312_CC312_AES_IV_1_2_REG_CC312_AES_IV_1_2_Msk (0xffffffffUL) /*!< CC312_AES_IV_1_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_IV_1_3_REG ================================================== */ + #define CC312_CC312_AES_IV_1_3_REG_CC312_AES_IV_1_3_Pos (0UL) /*!< CC312_AES_IV_1_3 (Bit 0) */ + #define CC312_CC312_AES_IV_1_3_REG_CC312_AES_IV_1_3_Msk (0xffffffffUL) /*!< CC312_AES_IV_1_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_0_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_0_REG_CC312_AES_KEY_0_0_Pos (0UL) /*!< CC312_AES_KEY_0_0 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_0_REG_CC312_AES_KEY_0_0_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_1_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_1_REG_CC312_AES_KEY_0_1_Pos (0UL) /*!< CC312_AES_KEY_0_1 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_1_REG_CC312_AES_KEY_0_1_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_2_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_2_REG_CC312_AES_KEY_0_2_Pos (0UL) /*!< CC312_AES_KEY_0_2 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_2_REG_CC312_AES_KEY_0_2_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_3_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_3_REG_CC312_AES_KEY_0_3_Pos (0UL) /*!< CC312_AES_KEY_0_3 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_3_REG_CC312_AES_KEY_0_3_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_4_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_4_REG_CC312_AES_KEY_0_4_Pos (0UL) /*!< CC312_AES_KEY_0_4 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_4_REG_CC312_AES_KEY_0_4_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_5_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_5_REG_CC312_AES_KEY_0_5_Pos (0UL) /*!< CC312_AES_KEY_0_5 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_5_REG_CC312_AES_KEY_0_5_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_5 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_6_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_6_REG_CC312_AES_KEY_0_6_Pos (0UL) /*!< CC312_AES_KEY_0_6 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_6_REG_CC312_AES_KEY_0_6_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_6 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_0_7_REG ================================================= */ + #define CC312_CC312_AES_KEY_0_7_REG_CC312_AES_KEY_0_7_Pos (0UL) /*!< CC312_AES_KEY_0_7 (Bit 0) */ + #define CC312_CC312_AES_KEY_0_7_REG_CC312_AES_KEY_0_7_Msk (0xffffffffUL) /*!< CC312_AES_KEY_0_7 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_0_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_0_REG_CC312_AES_KEY_1_0_Pos (0UL) /*!< CC312_AES_KEY_1_0 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_0_REG_CC312_AES_KEY_1_0_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_1_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_1_REG_CC312_AES_KEY_1_1_Pos (0UL) /*!< CC312_AES_KEY_1_1 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_1_REG_CC312_AES_KEY_1_1_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_2_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_2_REG_CC312_AES_KEY_1_2_Pos (0UL) /*!< CC312_AES_KEY_1_2 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_2_REG_CC312_AES_KEY_1_2_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_3_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_3_REG_CC312_AES_KEY_1_3_Pos (0UL) /*!< CC312_AES_KEY_1_3 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_3_REG_CC312_AES_KEY_1_3_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_4_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_4_REG_CC312_AES_KEY_1_4_Pos (0UL) /*!< CC312_AES_KEY_1_4 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_4_REG_CC312_AES_KEY_1_4_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_5_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_5_REG_CC312_AES_KEY_1_5_Pos (0UL) /*!< CC312_AES_KEY_1_5 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_5_REG_CC312_AES_KEY_1_5_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_5 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_6_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_6_REG_CC312_AES_KEY_1_6_Pos (0UL) /*!< CC312_AES_KEY_1_6 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_6_REG_CC312_AES_KEY_1_6_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_6 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_AES_KEY_1_7_REG ================================================= */ + #define CC312_CC312_AES_KEY_1_7_REG_CC312_AES_KEY_1_7_Pos (0UL) /*!< CC312_AES_KEY_1_7 (Bit 0) */ + #define CC312_CC312_AES_KEY_1_7_REG_CC312_AES_KEY_1_7_Msk (0xffffffffUL) /*!< CC312_AES_KEY_1_7 (Bitfield-Mask: 0xffffffff) */ +/* ============================================= CC312_AES_REMAINING_BYTES_REG ============================================= */ + #define CC312_CC312_AES_REMAINING_BYTES_REG_CC312_AES_REMAINING_BYTES_Pos (0UL) /*!< CC312_AES_REMAINING_BYTES (Bit 0) */ + #define CC312_CC312_AES_REMAINING_BYTES_REG_CC312_AES_REMAINING_BYTES_Msk (0xffffffffUL) /*!< CC312_AES_REMAINING_BYTES (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_AES_SK1_REG =================================================== */ + #define CC312_CC312_AES_SK1_REG_CC312_AES_SK1_Pos (0UL) /*!< CC312_AES_SK1 (Bit 0) */ + #define CC312_CC312_AES_SK1_REG_CC312_AES_SK1_Msk (0x1UL) /*!< CC312_AES_SK1 (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_AES_SK_REG ==================================================== */ + #define CC312_CC312_AES_SK_REG_CC312_AES_SK_Pos (0UL) /*!< CC312_AES_SK (Bit 0) */ + #define CC312_CC312_AES_SK_REG_CC312_AES_SK_Msk (0x1UL) /*!< CC312_AES_SK (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_AHBM_HMASTLOCK_REG ================================================ */ + #define CC312_CC312_AHBM_HMASTLOCK_REG_CC312_AHB_HMASTLOCK_Pos (0UL) /*!< CC312_AHB_HMASTLOCK (Bit 0) */ + #define CC312_CC312_AHBM_HMASTLOCK_REG_CC312_AHB_HMASTLOCK_Msk (0x1UL) /*!< CC312_AHB_HMASTLOCK (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_AHBM_HNONSEC_REG ================================================= */ + #define CC312_CC312_AHBM_HNONSEC_REG_CC312_AHB_READ_HNONSEC_Pos (1UL) /*!< CC312_AHB_READ_HNONSEC (Bit 1) */ + #define CC312_CC312_AHBM_HNONSEC_REG_CC312_AHB_READ_HNONSEC_Msk (0x2UL) /*!< CC312_AHB_READ_HNONSEC (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AHBM_HNONSEC_REG_CC312_AHB_WRITE_HNONSEC_Pos (0UL) /*!< CC312_AHB_WRITE_HNONSEC (Bit 0) */ + #define CC312_CC312_AHBM_HNONSEC_REG_CC312_AHB_WRITE_HNONSEC_Msk (0x1UL) /*!< CC312_AHB_WRITE_HNONSEC (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_AHBM_HPROT_REG ================================================== */ + #define CC312_CC312_AHBM_HPROT_REG_CC312_AHB_PROT_Pos (0UL) /*!< CC312_AHB_PROT (Bit 0) */ + #define CC312_CC312_AHBM_HPROT_REG_CC312_AHB_PROT_Msk (0xfUL) /*!< CC312_AHB_PROT (Bitfield-Mask: 0x0f) */ +/* ================================================ CC312_AHBM_SINGLES_REG ================================================= */ + #define CC312_CC312_AHBM_SINGLES_REG_CC312_AHB_SINGLES_Pos (0UL) /*!< CC312_AHB_SINGLES (Bit 0) */ + #define CC312_CC312_AHBM_SINGLES_REG_CC312_AHB_SINGLES_Msk (0x1UL) /*!< CC312_AHB_SINGLES (Bitfield-Mask: 0x01) */ +/* =========================================== CC312_AIB_FUSE_PROG_COMPLETED_REG =========================================== */ + #define CC312_CC312_AIB_FUSE_PROG_COMPLETED_REG_CC312_AIB_FUSE_PROG_COMPLETED_Pos (0UL) /*!< CC312_AIB_FUSE_PROG_COMPLETED (Bit 0) */ + #define CC312_CC312_AIB_FUSE_PROG_COMPLETED_REG_CC312_AIB_FUSE_PROG_COMPLETED_Msk (0x1UL) /*!< CC312_AIB_FUSE_PROG_COMPLETED (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_AO_APB_FILTERING_REG =============================================== */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_INST_ACCESS_ALLOW_LOCK_Pos (9UL) /*!< CC312_APBC_ONLY_INST_ACCESS_ALLOW_LOCK (Bit 9) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_INST_ACCESS_ALLOW_LOCK_Msk (0x200UL) /*!< CC312_APBC_ONLY_INST_ACCESS_ALLOW_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_INST_ACCESS_ALLOW_Pos (8UL) /*!< CC312_APBC_ONLY_INST_ACCESS_ALLOW (Bit 8) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_INST_ACCESS_ALLOW_Msk (0x100UL) /*!< CC312_APBC_ONLY_INST_ACCESS_ALLOW (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK_Pos (7UL) /*!< CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK (Bit 7) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK_Msk (0x80UL) /*!< CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_Pos (6UL) /*!< CC312_APBC_ONLY_PRIV_ACCESS_ALLOW (Bit 6) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_PRIV_ACCESS_ALLOW_Msk (0x40UL) /*!< CC312_APBC_ONLY_PRIV_ACCESS_ALLOW (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK_Pos (5UL) /*!< CC312_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK (Bit 5) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK_Msk (0x20UL) /*!< CC312_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_SEC_ACCESS_ALLOW_Pos (4UL) /*!< CC312_APBC_ONLY_SEC_ACCESS_ALLOW (Bit 4) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_APBC_ONLY_SEC_ACCESS_ALLOW_Msk (0x10UL) /*!< CC312_APBC_ONLY_SEC_ACCESS_ALLOW (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_PRIV_ACCESS_ALLOW_LOCK_Pos (3UL) /*!< CC312_ONLY_PRIV_ACCESS_ALLOW_LOCK (Bit 3) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_PRIV_ACCESS_ALLOW_LOCK_Msk (0x8UL) /*!< CC312_ONLY_PRIV_ACCESS_ALLOW_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_PRIV_ACCESS_ALLOW_Pos (2UL) /*!< CC312_ONLY_PRIV_ACCESS_ALLOW (Bit 2) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_PRIV_ACCESS_ALLOW_Msk (0x4UL) /*!< CC312_ONLY_PRIV_ACCESS_ALLOW (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_SEC_ACCESS_ALLOW_LOCK_Pos (1UL) /*!< CC312_ONLY_SEC_ACCESS_ALLOW_LOCK (Bit 1) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_SEC_ACCESS_ALLOW_LOCK_Msk (0x2UL) /*!< CC312_ONLY_SEC_ACCESS_ALLOW_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_SEC_ACCESS_ALLOW_Pos (0UL) /*!< CC312_ONLY_SEC_ACCESS_ALLOW (Bit 0) */ + #define CC312_CC312_AO_APB_FILTERING_REG_CC312_ONLY_SEC_ACCESS_ALLOW_Msk (0x1UL) /*!< CC312_ONLY_SEC_ACCESS_ALLOW (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_AO_CC_GPPC_REG ================================================== */ + #define CC312_CC312_AO_CC_GPPC_REG_CC312_AO_CC_GPPC_Pos (0UL) /*!< CC312_AO_CC_GPPC (Bit 0) */ + #define CC312_CC312_AO_CC_GPPC_REG_CC312_AO_CC_GPPC_Msk (0xffUL) /*!< CC312_AO_CC_GPPC (Bitfield-Mask: 0xff) */ +/* ============================================ CC312_AO_CC_SEC_DEBUG_RESET_REG ============================================ */ + #define CC312_CC312_AO_CC_SEC_DEBUG_RESET_REG_CC312_AO_CC_SEC_DEBUG_RESET_Pos (0UL) /*!< CC312_AO_CC_SEC_DEBUG_RESET (Bit 0) */ + #define CC312_CC312_AO_CC_SEC_DEBUG_RESET_REG_CC312_AO_CC_SEC_DEBUG_RESET_Msk (0x1UL) /*!< CC312_AO_CC_SEC_DEBUG_RESET (Bitfield-Mask: 0x01) */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG ========================================= */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK0_Pos (0UL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK0 (Bit 0) */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK0_Msk (0xffffffffUL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG ========================================= */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK1_Pos (0UL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK1 (Bit 0) */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK1_Msk (0xffffffffUL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG ========================================= */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK2_Pos (0UL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK2 (Bit 0) */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK2_Msk (0xffffffffUL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG ========================================= */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK3_Pos (0UL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK3 (Bit 0) */ + #define CC312_CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG_CC312_AO_ICV_DCU_RESTRICTION_MASK3_Msk (0xffffffffUL) /*!< CC312_AO_ICV_DCU_RESTRICTION_MASK3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================= CC312_AUTOCORR_STATISTIC_REG ============================================== */ + #define CC312_CC312_AUTOCORR_STATISTIC_REG_CC312_AUTOCORR_FAILS_Pos (14UL) /*!< CC312_AUTOCORR_FAILS (Bit 14) */ + #define CC312_CC312_AUTOCORR_STATISTIC_REG_CC312_AUTOCORR_FAILS_Msk (0x3fc000UL) /*!< CC312_AUTOCORR_FAILS (Bitfield-Mask: 0xff) */ + #define CC312_CC312_AUTOCORR_STATISTIC_REG_CC312_AUTOCORR_TRYS_Pos (0UL) /*!< CC312_AUTOCORR_TRYS (Bit 0) */ + #define CC312_CC312_AUTOCORR_STATISTIC_REG_CC312_AUTOCORR_TRYS_Msk (0x3fffUL) /*!< CC312_AUTOCORR_TRYS (Bitfield-Mask: 0x3fff) */ +/* =============================================== CC312_AUTO_HW_PADDING_REG =============================================== */ + #define CC312_CC312_AUTO_HW_PADDING_REG_CC312_AUTO_HW_PADDING_EN_Pos (0UL) /*!< CC312_AUTO_HW_PADDING_EN (Bit 0) */ + #define CC312_CC312_AUTO_HW_PADDING_REG_CC312_AUTO_HW_PADDING_EN_Msk (0x1UL) /*!< CC312_AUTO_HW_PADDING_EN (Bitfield-Mask: 0x01) */ +/* ============================================ CC312_CHACHA_BLOCK_CNT_LSB_REG ============================================= */ + #define CC312_CC312_CHACHA_BLOCK_CNT_LSB_REG_CC312_CHACHA_BLOCK_CNT_LSB_Pos (0UL) /*!< CC312_CHACHA_BLOCK_CNT_LSB (Bit 0) */ + #define CC312_CC312_CHACHA_BLOCK_CNT_LSB_REG_CC312_CHACHA_BLOCK_CNT_LSB_Msk (0xffffffffUL) /*!< CC312_CHACHA_BLOCK_CNT_LSB (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_BLOCK_CNT_MSB_REG ============================================= */ + #define CC312_CC312_CHACHA_BLOCK_CNT_MSB_REG_CC312_CHACHA_BLOCK_CNT_MSB_Pos (0UL) /*!< CC312_CHACHA_BLOCK_CNT_MSB (Bit 0) */ + #define CC312_CC312_CHACHA_BLOCK_CNT_MSB_REG_CC312_CHACHA_BLOCK_CNT_MSB_Msk (0xffffffffUL) /*!< CC312_CHACHA_BLOCK_CNT_MSB (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_BUSY_REG ================================================= */ + #define CC312_CC312_CHACHA_BUSY_REG_CC312_CHACHA_BUSY_Pos (0UL) /*!< CC312_CHACHA_BUSY (Bit 0) */ + #define CC312_CC312_CHACHA_BUSY_REG_CC312_CHACHA_BUSY_Msk (0x1UL) /*!< CC312_CHACHA_BUSY (Bitfield-Mask: 0x01) */ +/* ======================================= CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG ======================================= */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DOUT_BYTE_ORDER_Pos (4UL) /*!< CC312_CHACHA_DOUT_BYTE_ORDER (Bit 4) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DOUT_BYTE_ORDER_Msk (0x10UL) /*!< CC312_CHACHA_DOUT_BYTE_ORDER (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DOUT_WORD_ORDER_Pos (3UL) /*!< CC312_CHACHA_DOUT_WORD_ORDER (Bit 3) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DOUT_WORD_ORDER_Msk (0x8UL) /*!< CC312_CHACHA_DOUT_WORD_ORDER (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_CORE_MATRIX_LBE_ORDER_Pos (2UL) /*!< CC312_CHACHA_CORE_MATRIX_LBE_ORDER (Bit 2) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_CORE_MATRIX_LBE_ORDER_Msk (0x4UL) /*!< CC312_CHACHA_CORE_MATRIX_LBE_ORDER (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DIN_BYTE_ORDER_Pos (1UL) /*!< CC312_CHACHA_DIN_BYTE_ORDER (Bit 1) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DIN_BYTE_ORDER_Msk (0x2UL) /*!< CC312_CHACHA_DIN_BYTE_ORDER (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DIN_WORD_ORDER_Pos (0UL) /*!< CC312_CHACHA_DIN_WORD_ORDER (Bit 0) */ + #define CC312_CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_CC312_CHACHA_DIN_WORD_ORDER_Msk (0x1UL) /*!< CC312_CHACHA_DIN_WORD_ORDER (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_CHACHA_CLK_ENABLE_REG ============================================== */ + #define CC312_CC312_CHACHA_CLK_ENABLE_REG_CC312_CHACHA_CLK_EN_Pos (0UL) /*!< CC312_CHACHA_CLK_EN (Bit 0) */ + #define CC312_CC312_CHACHA_CLK_ENABLE_REG_CC312_CHACHA_CLK_EN_Msk (0x1UL) /*!< CC312_CHACHA_CLK_EN (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_CHACHA_CONTROL_REG_REG ============================================== */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_USE_IV_96BIT_Pos (10UL) /*!< CC312_USE_IV_96BIT (Bit 10) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_USE_IV_96BIT_Msk (0x400UL) /*!< CC312_USE_IV_96BIT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_RESET_BLOCK_CNT_Pos (9UL) /*!< CC312_RESET_BLOCK_CNT (Bit 9) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_RESET_BLOCK_CNT_Msk (0x200UL) /*!< CC312_RESET_BLOCK_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_NUM_OF_ROUNDS_Pos (4UL) /*!< CC312_NUM_OF_ROUNDS (Bit 4) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_NUM_OF_ROUNDS_Msk (0x30UL) /*!< CC312_NUM_OF_ROUNDS (Bitfield-Mask: 0x03) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_KEY_LEN_Pos (3UL) /*!< CC312_KEY_LEN (Bit 3) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_KEY_LEN_Msk (0x8UL) /*!< CC312_KEY_LEN (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_CALC_KEY_FOR_POLY1305_Pos (2UL) /*!< CC312_CALC_KEY_FOR_POLY1305 (Bit 2) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_CALC_KEY_FOR_POLY1305_Msk (0x4UL) /*!< CC312_CALC_KEY_FOR_POLY1305 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_INIT_FROM_HOST_Pos (1UL) /*!< CC312_INIT_FROM_HOST (Bit 1) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_INIT_FROM_HOST_Msk (0x2UL) /*!< CC312_INIT_FROM_HOST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_CHACHA_OR_SALSA_Pos (0UL) /*!< CC312_CHACHA_OR_SALSA (Bit 0) */ + #define CC312_CC312_CHACHA_CONTROL_REG_REG_CC312_CHACHA_OR_SALSA_Msk (0x1UL) /*!< CC312_CHACHA_OR_SALSA (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_CHACHA_DEBUG_REG_REG =============================================== */ + #define CC312_CC312_CHACHA_DEBUG_REG_REG_CC312_CHACHA_DEBUG_FSM_STATE_Pos (0UL) /*!< CC312_CHACHA_DEBUG_FSM_STATE (Bit 0) */ + #define CC312_CC312_CHACHA_DEBUG_REG_REG_CC312_CHACHA_DEBUG_FSM_STATE_Msk (0x3UL) /*!< CC312_CHACHA_DEBUG_FSM_STATE (Bitfield-Mask: 0x03) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY0_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY0_REG_CC312_CHACHA_FOR_POLY_KEY0_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY0 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY0_REG_CC312_CHACHA_FOR_POLY_KEY0_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY1_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY1_REG_CC312_CHACHA_FOR_POLY_KEY1_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY1 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY1_REG_CC312_CHACHA_FOR_POLY_KEY1_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY2_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY2_REG_CC312_CHACHA_FOR_POLY_KEY2_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY2 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY2_REG_CC312_CHACHA_FOR_POLY_KEY2_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY3_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY3_REG_CC312_CHACHA_FOR_POLY_KEY3_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY3 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY3_REG_CC312_CHACHA_FOR_POLY_KEY3_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY4_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY4_REG_CC312_CHACHA_FOR_POLY_KEY4_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY4 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY4_REG_CC312_CHACHA_FOR_POLY_KEY4_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY4 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY5_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY5_REG_CC312_CHACHA_FOR_POLY_KEY5_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY5 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY5_REG_CC312_CHACHA_FOR_POLY_KEY5_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY5 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY6_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY6_REG_CC312_CHACHA_FOR_POLY_KEY6_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY6 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY6_REG_CC312_CHACHA_FOR_POLY_KEY6_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY6 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY7_REG ============================================= */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY7_REG_CC312_CHACHA_FOR_POLY_KEY7_Pos (0UL) /*!< CC312_CHACHA_FOR_POLY_KEY7 (Bit 0) */ + #define CC312_CC312_CHACHA_FOR_POLY_KEY7_REG_CC312_CHACHA_FOR_POLY_KEY7_Msk (0xffffffffUL) /*!< CC312_CHACHA_FOR_POLY_KEY7 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_CHACHA_HW_FLAGS_REG =============================================== */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_FAST_CHACHA_Pos (2UL) /*!< CC312_FAST_CHACHA (Bit 2) */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_FAST_CHACHA_Msk (0x4UL) /*!< CC312_FAST_CHACHA (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_SALSA_EXISTS_Pos (1UL) /*!< CC312_SALSA_EXISTS (Bit 1) */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_SALSA_EXISTS_Msk (0x2UL) /*!< CC312_SALSA_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_CHACHA_EXISTS_Pos (0UL) /*!< CC312_CHACHA_EXISTS (Bit 0) */ + #define CC312_CC312_CHACHA_HW_FLAGS_REG_CC312_CHACHA_EXISTS_Msk (0x1UL) /*!< CC312_CHACHA_EXISTS (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_CHACHA_IV_0_REG ================================================= */ + #define CC312_CC312_CHACHA_IV_0_REG_CC312_CHACHA_IV_0_Pos (0UL) /*!< CC312_CHACHA_IV_0 (Bit 0) */ + #define CC312_CC312_CHACHA_IV_0_REG_CC312_CHACHA_IV_0_Msk (0xffffffffUL) /*!< CC312_CHACHA_IV_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_IV_1_REG ================================================= */ + #define CC312_CC312_CHACHA_IV_1_REG_CC312_CHACHA_IV_1_Pos (0UL) /*!< CC312_CHACHA_IV_1 (Bit 0) */ + #define CC312_CC312_CHACHA_IV_1_REG_CC312_CHACHA_IV_1_Msk (0xffffffffUL) /*!< CC312_CHACHA_IV_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY0_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY0_REG_CC312_CHACHA_KEY0_Pos (0UL) /*!< CC312_CHACHA_KEY0 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY0_REG_CC312_CHACHA_KEY0_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY1_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY1_REG_CC312_CHACHA_KEY1_Pos (0UL) /*!< CC312_CHACHA_KEY1 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY1_REG_CC312_CHACHA_KEY1_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY2_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY2_REG_CC312_CHACHA_KEY2_Pos (0UL) /*!< CC312_CHACHA_KEY2 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY2_REG_CC312_CHACHA_KEY2_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY3_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY3_REG_CC312_CHACHA_KEY3_Pos (0UL) /*!< CC312_CHACHA_KEY3 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY3_REG_CC312_CHACHA_KEY3_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY4_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY4_REG_CC312_CHACHA_KEY4_Pos (0UL) /*!< CC312_CHACHA_KEY4 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY4_REG_CC312_CHACHA_KEY4_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY5_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY5_REG_CC312_CHACHA_KEY5_Pos (0UL) /*!< CC312_CHACHA_KEY5 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY5_REG_CC312_CHACHA_KEY5_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY5 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY6_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY6_REG_CC312_CHACHA_KEY6_Pos (0UL) /*!< CC312_CHACHA_KEY6 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY6_REG_CC312_CHACHA_KEY6_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY6 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CHACHA_KEY7_REG ================================================= */ + #define CC312_CC312_CHACHA_KEY7_REG_CC312_CHACHA_KEY7_Pos (0UL) /*!< CC312_CHACHA_KEY7 (Bit 0) */ + #define CC312_CC312_CHACHA_KEY7_REG_CC312_CHACHA_KEY7_Msk (0xffffffffUL) /*!< CC312_CHACHA_KEY7 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_CHACHA_SW_RESET_REG =============================================== */ + #define CC312_CC312_CHACHA_SW_RESET_REG_CC312_CHACH_SW_RESET_Pos (0UL) /*!< CC312_CHACH_SW_RESET (Bit 0) */ + #define CC312_CC312_CHACHA_SW_RESET_REG_CC312_CHACH_SW_RESET_Msk (0x1UL) /*!< CC312_CHACH_SW_RESET (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_CHACHA_VERSION_REG ================================================ */ + #define CC312_CC312_CHACHA_VERSION_REG_CC312_CHACHA_VERSION_Pos (0UL) /*!< CC312_CHACHA_VERSION (Bit 0) */ + #define CC312_CC312_CHACHA_VERSION_REG_CC312_CHACHA_VERSION_Msk (0xffffffffUL) /*!< CC312_CHACHA_VERSION (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_CLK_STATUS_REG ================================================== */ + #define CC312_CC312_CLK_STATUS_REG_CC312_DMA_CLK_STATUS_Pos (8UL) /*!< CC312_DMA_CLK_STATUS (Bit 8) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_DMA_CLK_STATUS_Msk (0x100UL) /*!< CC312_DMA_CLK_STATUS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_CHACHA_CLK_STATUS_Pos (7UL) /*!< CC312_CHACHA_CLK_STATUS (Bit 7) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_CHACHA_CLK_STATUS_Msk (0x80UL) /*!< CC312_CHACHA_CLK_STATUS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_PKA_CLK_STATUS_Pos (3UL) /*!< CC312_PKA_CLK_STATUS (Bit 3) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_PKA_CLK_STATUS_Msk (0x8UL) /*!< CC312_PKA_CLK_STATUS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_HASH_CLK_STATUS_Pos (2UL) /*!< CC312_HASH_CLK_STATUS (Bit 2) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_HASH_CLK_STATUS_Msk (0x4UL) /*!< CC312_HASH_CLK_STATUS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_AES_CLK_STATUS_Pos (0UL) /*!< CC312_AES_CLK_STATUS (Bit 0) */ + #define CC312_CC312_CLK_STATUS_REG_CC312_AES_CLK_STATUS_Msk (0x1UL) /*!< CC312_AES_CLK_STATUS (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_COMPONENT_ID_0_REG ================================================ */ + #define CC312_CC312_COMPONENT_ID_0_REG_CC312_PRMBL_0_Pos (0UL) /*!< CC312_PRMBL_0 (Bit 0) */ + #define CC312_CC312_COMPONENT_ID_0_REG_CC312_PRMBL_0_Msk (0xffUL) /*!< CC312_PRMBL_0 (Bitfield-Mask: 0xff) */ +/* =============================================== CC312_COMPONENT_ID_1_REG ================================================ */ + #define CC312_CC312_COMPONENT_ID_1_REG_CC312_CLASS_Pos (4UL) /*!< CC312_CLASS (Bit 4) */ + #define CC312_CC312_COMPONENT_ID_1_REG_CC312_CLASS_Msk (0xf0UL) /*!< CC312_CLASS (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_COMPONENT_ID_1_REG_CC312_PRMBL_1_Pos (0UL) /*!< CC312_PRMBL_1 (Bit 0) */ + #define CC312_CC312_COMPONENT_ID_1_REG_CC312_PRMBL_1_Msk (0xfUL) /*!< CC312_PRMBL_1 (Bitfield-Mask: 0x0f) */ +/* =============================================== CC312_COMPONENT_ID_2_REG ================================================ */ + #define CC312_CC312_COMPONENT_ID_2_REG_CC312_PRMBL_2_Pos (0UL) /*!< CC312_PRMBL_2 (Bit 0) */ + #define CC312_CC312_COMPONENT_ID_2_REG_CC312_PRMBL_2_Msk (0xffUL) /*!< CC312_PRMBL_2 (Bitfield-Mask: 0xff) */ +/* =============================================== CC312_COMPONENT_ID_3_REG ================================================ */ + #define CC312_CC312_COMPONENT_ID_3_REG_CC312_PRMBL_3_Pos (0UL) /*!< CC312_PRMBL_3 (Bit 0) */ + #define CC312_CC312_COMPONENT_ID_3_REG_CC312_PRMBL_3_Msk (0xffUL) /*!< CC312_PRMBL_3 (Bitfield-Mask: 0xff) */ +/* ================================================= CC312_CONTEXT_ID_REG ================================================== */ + #define CC312_CC312_CONTEXT_ID_REG_CC312_CONTEXT_ID_Pos (0UL) /*!< CC312_CONTEXT_ID (Bit 0) */ + #define CC312_CC312_CONTEXT_ID_REG_CC312_CONTEXT_ID_Msk (0xffUL) /*!< CC312_CONTEXT_ID (Bitfield-Mask: 0xff) */ +/* ================================================= CC312_CRYPTO_BUSY_REG ================================================= */ + #define CC312_CC312_CRYPTO_BUSY_REG_CC312_CRYPTO_BUSY_Pos (0UL) /*!< CC312_CRYPTO_BUSY (Bit 0) */ + #define CC312_CC312_CRYPTO_BUSY_REG_CC312_CRYPTO_BUSY_Msk (0x1UL) /*!< CC312_CRYPTO_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_CRYPTO_CTL_REG ================================================== */ + #define CC312_CC312_CRYPTO_CTL_REG_CC312_MODE_Pos (0UL) /*!< CC312_MODE (Bit 0) */ + #define CC312_CC312_CRYPTO_CTL_REG_CC312_MODE_Msk (0x1fUL) /*!< CC312_MODE (Bitfield-Mask: 0x1f) */ +/* ================================================= CC312_DIN_BUFFER_REG ================================================== */ + #define CC312_CC312_DIN_BUFFER_REG_CC312_DIN_BUFFER_DATA_Pos (0UL) /*!< CC312_DIN_BUFFER_DATA (Bit 0) */ + #define CC312_CC312_DIN_BUFFER_REG_CC312_DIN_BUFFER_DATA_Msk (0xffffffffUL) /*!< CC312_DIN_BUFFER_DATA (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_DIN_CPU_DATA_SIZE_REG ============================================== */ + #define CC312_CC312_DIN_CPU_DATA_SIZE_REG_CC312_CPU_DIN_SIZE_Pos (0UL) /*!< CC312_CPU_DIN_SIZE (Bit 0) */ + #define CC312_CC312_DIN_CPU_DATA_SIZE_REG_CC312_CPU_DIN_SIZE_Msk (0xffffUL) /*!< CC312_CPU_DIN_SIZE (Bitfield-Mask: 0xffff) */ +/* ============================================== CC312_DIN_FIFO_RST_PNTR_REG ============================================== */ + #define CC312_CC312_DIN_FIFO_RST_PNTR_REG_CC312_RST_Pos (0UL) /*!< CC312_RST (Bit 0) */ + #define CC312_CC312_DIN_FIFO_RST_PNTR_REG_CC312_RST_Msk (0x1UL) /*!< CC312_RST (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_DIN_MEM_DMA_BUSY_REG =============================================== */ + #define CC312_CC312_DIN_MEM_DMA_BUSY_REG_CC312_DIN_MEM_DMA_BUSY_Pos (0UL) /*!< CC312_DIN_MEM_DMA_BUSY (Bit 0) */ + #define CC312_CC312_DIN_MEM_DMA_BUSY_REG_CC312_DIN_MEM_DMA_BUSY_Msk (0x1UL) /*!< CC312_DIN_MEM_DMA_BUSY (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_DIN_SRAM_BYTES_LEN_REG ============================================== */ + #define CC312_CC312_DIN_SRAM_BYTES_LEN_REG_CC312_DIN_SRAM_BYTES_LEN_Pos (0UL) /*!< CC312_DIN_SRAM_BYTES_LEN (Bit 0) */ + #define CC312_CC312_DIN_SRAM_BYTES_LEN_REG_CC312_DIN_SRAM_BYTES_LEN_Msk (0xffffffffUL) /*!< CC312_DIN_SRAM_BYTES_LEN (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_DIN_SRAM_DMA_BUSY_REG ============================================== */ + #define CC312_CC312_DIN_SRAM_DMA_BUSY_REG_CC312_DIN_SRAM_BUSY_Pos (0UL) /*!< CC312_DIN_SRAM_BUSY (Bit 0) */ + #define CC312_CC312_DIN_SRAM_DMA_BUSY_REG_CC312_DIN_SRAM_BUSY_Msk (0x1UL) /*!< CC312_DIN_SRAM_BUSY (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_DIN_SRAM_ENDIANNESS_REG ============================================= */ + #define CC312_CC312_DIN_SRAM_ENDIANNESS_REG_CC312_SRAM_DIN_ENDIANNESS_Pos (0UL) /*!< CC312_SRAM_DIN_ENDIANNESS (Bit 0) */ + #define CC312_CC312_DIN_SRAM_ENDIANNESS_REG_CC312_SRAM_DIN_ENDIANNESS_Msk (0x1UL) /*!< CC312_SRAM_DIN_ENDIANNESS (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_DMA_CLK_ENABLE_REG ================================================ */ + #define CC312_CC312_DMA_CLK_ENABLE_REG_CC312_DMA_CLK_EN_Pos (0UL) /*!< CC312_DMA_CLK_EN (Bit 0) */ + #define CC312_CC312_DMA_CLK_ENABLE_REG_CC312_DMA_CLK_EN_Msk (0x1UL) /*!< CC312_DMA_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_DOUT_BUFFER_REG ================================================= */ + #define CC312_CC312_DOUT_BUFFER_REG_CC312_DOUT_BUFFER_DATA_Pos (0UL) /*!< CC312_DOUT_BUFFER_DATA (Bit 0) */ + #define CC312_CC312_DOUT_BUFFER_REG_CC312_DOUT_BUFFER_DATA_Msk (0xffffffffUL) /*!< CC312_DOUT_BUFFER_DATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_DOUT_FIFO_EMPTY_REG =============================================== */ + #define CC312_CC312_DOUT_FIFO_EMPTY_REG_CC312_DOUT_FIFO_EMPTY_Pos (0UL) /*!< CC312_DOUT_FIFO_EMPTY (Bit 0) */ + #define CC312_CC312_DOUT_FIFO_EMPTY_REG_CC312_DOUT_FIFO_EMPTY_Msk (0x1UL) /*!< CC312_DOUT_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_DOUT_MEM_DMA_BUSY_REG ============================================== */ + #define CC312_CC312_DOUT_MEM_DMA_BUSY_REG_CC312_DOUT_MEM_DMA_BUSY_Pos (0UL) /*!< CC312_DOUT_MEM_DMA_BUSY (Bit 0) */ + #define CC312_CC312_DOUT_MEM_DMA_BUSY_REG_CC312_DOUT_MEM_DMA_BUSY_Msk (0x1UL) /*!< CC312_DOUT_MEM_DMA_BUSY (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_DOUT_SRAM_BYTES_LEN_REG ============================================= */ + #define CC312_CC312_DOUT_SRAM_BYTES_LEN_REG_CC312_DOUT_SRAM_BYTES_LEN_Pos (0UL) /*!< CC312_DOUT_SRAM_BYTES_LEN (Bit 0) */ + #define CC312_CC312_DOUT_SRAM_BYTES_LEN_REG_CC312_DOUT_SRAM_BYTES_LEN_Msk (0xffffffffUL) /*!< CC312_DOUT_SRAM_BYTES_LEN (Bitfield-Mask: 0xffffffff) */ +/* ============================================= CC312_DOUT_SRAM_DMA_BUSY_REG ============================================== */ + #define CC312_CC312_DOUT_SRAM_DMA_BUSY_REG_CC312_DOUT_SRAM_BUSY_Pos (0UL) /*!< CC312_DOUT_SRAM_BUSY (Bit 0) */ + #define CC312_CC312_DOUT_SRAM_DMA_BUSY_REG_CC312_DOUT_SRAM_BUSY_Msk (0x1UL) /*!< CC312_DOUT_SRAM_BUSY (Bitfield-Mask: 0x01) */ +/* ============================================ CC312_DOUT_SRAM_ENDIANNESS_REG ============================================= */ + #define CC312_CC312_DOUT_SRAM_ENDIANNESS_REG_CC312_DOUT_SRAM_ENDIANNESS_Pos (0UL) /*!< CC312_DOUT_SRAM_ENDIANNESS (Bit 0) */ + #define CC312_CC312_DOUT_SRAM_ENDIANNESS_REG_CC312_DOUT_SRAM_ENDIANNESS_Msk (0x1UL) /*!< CC312_DOUT_SRAM_ENDIANNESS (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_DST_LLI_WORD0_REG ================================================ */ + #define CC312_CC312_DST_LLI_WORD0_REG_CC312_DST_LLI_WORD0_Pos (0UL) /*!< CC312_DST_LLI_WORD0 (Bit 0) */ + #define CC312_CC312_DST_LLI_WORD0_REG_CC312_DST_LLI_WORD0_Msk (0xffffffffUL) /*!< CC312_DST_LLI_WORD0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_DST_LLI_WORD1_REG ================================================ */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_LAST_Pos (31UL) /*!< CC312_DST_LLI_LAST (Bit 31) */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_LAST_Msk (0x80000000UL) /*!< CC312_DST_LLI_LAST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_FIRST_Pos (30UL) /*!< CC312_DST_LLI_FIRST (Bit 30) */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_FIRST_Msk (0x40000000UL) /*!< CC312_DST_LLI_FIRST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_BYTES_NUM_Pos (0UL) /*!< CC312_DST_LLI_BYTES_NUM (Bit 0) */ + #define CC312_CC312_DST_LLI_WORD1_REG_CC312_DST_LLI_BYTES_NUM_Msk (0x3fffffffUL) /*!< CC312_DST_LLI_BYTES_NUM (Bitfield-Mask: 0x3fffffff) */ +/* ================================================= CC312_EHR_DATA_0_REG ================================================== */ + #define CC312_CC312_EHR_DATA_0_REG_CC312_EHR_DATA_0_Pos (0UL) /*!< CC312_EHR_DATA_0 (Bit 0) */ + #define CC312_CC312_EHR_DATA_0_REG_CC312_EHR_DATA_0_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_EHR_DATA_1_REG ================================================== */ + #define CC312_CC312_EHR_DATA_1_REG_CC312_EHR_DATA_1_Pos (0UL) /*!< CC312_EHR_DATA_1 (Bit 0) */ + #define CC312_CC312_EHR_DATA_1_REG_CC312_EHR_DATA_1_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_EHR_DATA_2_REG ================================================== */ + #define CC312_CC312_EHR_DATA_2_REG_CC312_EHR_DATA_2_Pos (0UL) /*!< CC312_EHR_DATA_2 (Bit 0) */ + #define CC312_CC312_EHR_DATA_2_REG_CC312_EHR_DATA_2_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_EHR_DATA_3_REG ================================================== */ + #define CC312_CC312_EHR_DATA_3_REG_CC312_EHR_DATA_3_Pos (0UL) /*!< CC312_EHR_DATA_3 (Bit 0) */ + #define CC312_CC312_EHR_DATA_3_REG_CC312_EHR_DATA_3_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_EHR_DATA_4_REG ================================================== */ + #define CC312_CC312_EHR_DATA_4_REG_CC312_EHR_DATA_4_Pos (0UL) /*!< CC312_EHR_DATA_4 (Bit 0) */ + #define CC312_CC312_EHR_DATA_4_REG_CC312_EHR_DATA_4_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_EHR_DATA_5_REG ================================================== */ + #define CC312_CC312_EHR_DATA_5_REG_CC312_EHR_DATA_5_Pos (0UL) /*!< CC312_EHR_DATA_5 (Bit 0) */ + #define CC312_CC312_EHR_DATA_5_REG_CC312_EHR_DATA_5_Msk (0xffffffffUL) /*!< CC312_EHR_DATA_5 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_FIFO_IN_EMPTY_REG ================================================ */ + #define CC312_CC312_FIFO_IN_EMPTY_REG_CC312_EMPTY_Pos (0UL) /*!< CC312_EMPTY (Bit 0) */ + #define CC312_CC312_FIFO_IN_EMPTY_REG_CC312_EMPTY_Msk (0x1UL) /*!< CC312_EMPTY (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_GHASH_BUSY_REG ================================================== */ + #define CC312_CC312_GHASH_BUSY_REG_CC312_GHASH_BUSY_Pos (0UL) /*!< CC312_GHASH_BUSY (Bit 0) */ + #define CC312_CC312_GHASH_BUSY_REG_CC312_GHASH_BUSY_Msk (0x1UL) /*!< CC312_GHASH_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_GHASH_INIT_REG ================================================== */ + #define CC312_CC312_GHASH_INIT_REG_CC312_GHASH_INIT_Pos (0UL) /*!< CC312_GHASH_INIT (Bit 0) */ + #define CC312_CC312_GHASH_INIT_REG_CC312_GHASH_INIT_Msk (0x1UL) /*!< CC312_GHASH_INIT (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_GHASH_IV_0_0_REG ================================================= */ + #define CC312_CC312_GHASH_IV_0_0_REG_CC312_GHASH_IV_0_0_Pos (0UL) /*!< CC312_GHASH_IV_0_0 (Bit 0) */ + #define CC312_CC312_GHASH_IV_0_0_REG_CC312_GHASH_IV_0_0_Msk (0xffffffffUL) /*!< CC312_GHASH_IV_0_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_GHASH_IV_0_1_REG ================================================= */ + #define CC312_CC312_GHASH_IV_0_1_REG_CC312_GHASH_IV_0_1_Pos (0UL) /*!< CC312_GHASH_IV_0_1 (Bit 0) */ + #define CC312_CC312_GHASH_IV_0_1_REG_CC312_GHASH_IV_0_1_Msk (0xffffffffUL) /*!< CC312_GHASH_IV_0_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_GHASH_IV_0_2_REG ================================================= */ + #define CC312_CC312_GHASH_IV_0_2_REG_CC312_GHASH_IV_0_2_Pos (0UL) /*!< CC312_GHASH_IV_0_2 (Bit 0) */ + #define CC312_CC312_GHASH_IV_0_2_REG_CC312_GHASH_IV_0_2_Msk (0xffffffffUL) /*!< CC312_GHASH_IV_0_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_GHASH_IV_0_3_REG ================================================= */ + #define CC312_CC312_GHASH_IV_0_3_REG_CC312_GHASH_IV_0_3_Pos (0UL) /*!< CC312_GHASH_IV_0_3 (Bit 0) */ + #define CC312_CC312_GHASH_IV_0_3_REG_CC312_GHASH_IV_0_3_Msk (0xffffffffUL) /*!< CC312_GHASH_IV_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_GHASH_SUBKEY_0_0_REG =============================================== */ + #define CC312_CC312_GHASH_SUBKEY_0_0_REG_CC312_GHASH_SUBKEY_0_0_Pos (0UL) /*!< CC312_GHASH_SUBKEY_0_0 (Bit 0) */ + #define CC312_CC312_GHASH_SUBKEY_0_0_REG_CC312_GHASH_SUBKEY_0_0_Msk (0xffffffffUL) /*!< CC312_GHASH_SUBKEY_0_0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_GHASH_SUBKEY_0_1_REG =============================================== */ + #define CC312_CC312_GHASH_SUBKEY_0_1_REG_CC312_GHASH_SUBKEY_0_1_Pos (0UL) /*!< CC312_GHASH_SUBKEY_0_1 (Bit 0) */ + #define CC312_CC312_GHASH_SUBKEY_0_1_REG_CC312_GHASH_SUBKEY_0_1_Msk (0xffffffffUL) /*!< CC312_GHASH_SUBKEY_0_1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_GHASH_SUBKEY_0_2_REG =============================================== */ + #define CC312_CC312_GHASH_SUBKEY_0_2_REG_CC312_GHASH_SUBKEY_0_2_Pos (0UL) /*!< CC312_GHASH_SUBKEY_0_2 (Bit 0) */ + #define CC312_CC312_GHASH_SUBKEY_0_2_REG_CC312_GHASH_SUBKEY_0_2_Msk (0xffffffffUL) /*!< CC312_GHASH_SUBKEY_0_2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_GHASH_SUBKEY_0_3_REG =============================================== */ + #define CC312_CC312_GHASH_SUBKEY_0_3_REG_CC312_GHASH_SUBKEY_0_3_Pos (0UL) /*!< CC312_GHASH_SUBKEY_0_3 (Bit 0) */ + #define CC312_CC312_GHASH_SUBKEY_0_3_REG_CC312_GHASH_SUBKEY_0_3_Msk (0xffffffffUL) /*!< CC312_GHASH_SUBKEY_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_HASH_AES_SW_RESET_REG ============================================== */ + #define CC312_CC312_HASH_AES_SW_RESET_REG_CC312_HASH_AES_SW_RESET_Pos (0UL) /*!< CC312_HASH_AES_SW_RESET (Bit 0) */ + #define CC312_CC312_HASH_AES_SW_RESET_REG_CC312_HASH_AES_SW_RESET_Msk (0x1UL) /*!< CC312_HASH_AES_SW_RESET (Bitfield-Mask: 0x01) */ +/* ================================================== CC312_HASH_BUSY_REG ================================================== */ + #define CC312_CC312_HASH_BUSY_REG_CC312_HASH_BUSY_Pos (0UL) /*!< CC312_HASH_BUSY (Bit 0) */ + #define CC312_CC312_HASH_BUSY_REG_CC312_HASH_BUSY_Msk (0x1UL) /*!< CC312_HASH_BUSY (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_HASH_CLK_ENABLE_REG =============================================== */ + #define CC312_CC312_HASH_CLK_ENABLE_REG_CC312_HASH_CLK_EN_Pos (0UL) /*!< CC312_HASH_CLK_EN (Bit 0) */ + #define CC312_CC312_HASH_CLK_ENABLE_REG_CC312_HASH_CLK_EN_Msk (0x1UL) /*!< CC312_HASH_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_HASH_CONTROL_REG ================================================= */ + #define CC312_CC312_HASH_CONTROL_REG_CC312_MODE_3_Pos (3UL) /*!< CC312_MODE_3 (Bit 3) */ + #define CC312_CC312_HASH_CONTROL_REG_CC312_MODE_3_Msk (0x8UL) /*!< CC312_MODE_3 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_CONTROL_REG_CC312_MODE_0_1_Pos (0UL) /*!< CC312_MODE_0_1 (Bit 0) */ + #define CC312_CC312_HASH_CONTROL_REG_CC312_MODE_0_1_Msk (0x3UL) /*!< CC312_MODE_0_1 (Bitfield-Mask: 0x03) */ +/* =============================================== CC312_HASH_CUR_LEN_0_REG ================================================ */ + #define CC312_CC312_HASH_CUR_LEN_0_REG_CC312_HASH_CUR_LEN_0_Pos (0UL) /*!< CC312_HASH_CUR_LEN_0 (Bit 0) */ + #define CC312_CC312_HASH_CUR_LEN_0_REG_CC312_HASH_CUR_LEN_0_Msk (0xffffffffUL) /*!< CC312_HASH_CUR_LEN_0 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HASH_CUR_LEN_1_REG ================================================ */ + #define CC312_CC312_HASH_CUR_LEN_1_REG_CC312_HASH_CUR_LEN_1_Pos (0UL) /*!< CC312_HASH_CUR_LEN_1 (Bit 0) */ + #define CC312_CC312_HASH_CUR_LEN_1_REG_CC312_HASH_CUR_LEN_1_Msk (0xffffffffUL) /*!< CC312_HASH_CUR_LEN_1 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HASH_ENDIANESS_REG ================================================ */ + #define CC312_CC312_HASH_ENDIANESS_REG_CC312_ENDIAN_Pos (0UL) /*!< CC312_ENDIAN (Bit 0) */ + #define CC312_CC312_HASH_ENDIANESS_REG_CC312_ENDIAN_Msk (0x1UL) /*!< CC312_ENDIAN (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_HASH_H0_REG =================================================== */ + #define CC312_CC312_HASH_H0_REG_CC312_HASH_H0_Pos (0UL) /*!< CC312_HASH_H0 (Bit 0) */ + #define CC312_CC312_HASH_H0_REG_CC312_HASH_H0_Msk (0xffffffffUL) /*!< CC312_HASH_H0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H1_REG =================================================== */ + #define CC312_CC312_HASH_H1_REG_CC312_HASH_H1_Pos (0UL) /*!< CC312_HASH_H1 (Bit 0) */ + #define CC312_CC312_HASH_H1_REG_CC312_HASH_H1_Msk (0xffffffffUL) /*!< CC312_HASH_H1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H2_REG =================================================== */ + #define CC312_CC312_HASH_H2_REG_CC312_HASH_H2_Pos (0UL) /*!< CC312_HASH_H2 (Bit 0) */ + #define CC312_CC312_HASH_H2_REG_CC312_HASH_H2_Msk (0xffffffffUL) /*!< CC312_HASH_H2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H3_REG =================================================== */ + #define CC312_CC312_HASH_H3_REG_CC312_HASH_H3_Pos (0UL) /*!< CC312_HASH_H3 (Bit 0) */ + #define CC312_CC312_HASH_H3_REG_CC312_HASH_H3_Msk (0xffffffffUL) /*!< CC312_HASH_H3 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H4_REG =================================================== */ + #define CC312_CC312_HASH_H4_REG_CC312_HASH_H4_Pos (0UL) /*!< CC312_HASH_H4 (Bit 0) */ + #define CC312_CC312_HASH_H4_REG_CC312_HASH_H4_Msk (0xffffffffUL) /*!< CC312_HASH_H4 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H5_REG =================================================== */ + #define CC312_CC312_HASH_H5_REG_CC312_HASH_H5_Pos (0UL) /*!< CC312_HASH_H5 (Bit 0) */ + #define CC312_CC312_HASH_H5_REG_CC312_HASH_H5_Msk (0xffffffffUL) /*!< CC312_HASH_H5 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H6_REG =================================================== */ + #define CC312_CC312_HASH_H6_REG_CC312_HASH_H6_Pos (0UL) /*!< CC312_HASH_H6 (Bit 0) */ + #define CC312_CC312_HASH_H6_REG_CC312_HASH_H6_Msk (0xffffffffUL) /*!< CC312_HASH_H6 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H7_REG =================================================== */ + #define CC312_CC312_HASH_H7_REG_CC312_HASH_H7_Pos (0UL) /*!< CC312_HASH_H7 (Bit 0) */ + #define CC312_CC312_HASH_H7_REG_CC312_HASH_H7_Msk (0xffffffffUL) /*!< CC312_HASH_H7 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CC312_HASH_H8_REG =================================================== */ + #define CC312_CC312_HASH_H8_REG_CC312_HASH_H8_Pos (0UL) /*!< CC312_HASH_H8 (Bit 0) */ + #define CC312_CC312_HASH_H8_REG_CC312_HASH_H8_Msk (0xffffffffUL) /*!< CC312_HASH_H8 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_HASH_PAD_CFG_REG ================================================= */ + #define CC312_CC312_HASH_PAD_CFG_REG_CC312_DO_PAD_Pos (2UL) /*!< CC312_DO_PAD (Bit 2) */ + #define CC312_CC312_HASH_PAD_CFG_REG_CC312_DO_PAD_Msk (0x4UL) /*!< CC312_DO_PAD (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_HASH_PAD_EN_REG ================================================= */ + #define CC312_CC312_HASH_PAD_EN_REG_CC312_HASH_PAD_EN_Pos (0UL) /*!< CC312_HASH_PAD_EN (Bit 0) */ + #define CC312_CC312_HASH_PAD_EN_REG_CC312_HASH_PAD_EN_Msk (0x1UL) /*!< CC312_HASH_PAD_EN (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_HASH_PARAM_REG ================================================== */ + #define CC312_CC312_HASH_PARAM_REG_CC312_DUMP_HASH_TO_DOUT_EXISTS_Pos (18UL) /*!< CC312_DUMP_HASH_TO_DOUT_EXISTS (Bit 18) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_DUMP_HASH_TO_DOUT_EXISTS_Msk (0x40000UL) /*!< CC312_DUMP_HASH_TO_DOUT_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_HASH_COMPARE_EXISTS_Pos (17UL) /*!< CC312_HASH_COMPARE_EXISTS (Bit 17) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_HASH_COMPARE_EXISTS_Msk (0x20000UL) /*!< CC312_HASH_COMPARE_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_SHA_256_EXISTS_Pos (16UL) /*!< CC312_SHA_256_EXISTS (Bit 16) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_SHA_256_EXISTS_Msk (0x10000UL) /*!< CC312_SHA_256_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_HMAC_EXISTS_Pos (15UL) /*!< CC312_HMAC_EXISTS (Bit 15) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_HMAC_EXISTS_Msk (0x8000UL) /*!< CC312_HMAC_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_MD5_EXISTS_Pos (14UL) /*!< CC312_MD5_EXISTS (Bit 14) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_MD5_EXISTS_Msk (0x4000UL) /*!< CC312_MD5_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_PAD_EXISTS_Pos (13UL) /*!< CC312_PAD_EXISTS (Bit 13) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_PAD_EXISTS_Msk (0x2000UL) /*!< CC312_PAD_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_SHA_512_EXISTS_Pos (12UL) /*!< CC312_SHA_512_EXISTS (Bit 12) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_SHA_512_EXISTS_Msk (0x1000UL) /*!< CC312_SHA_512_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_DW_Pos (8UL) /*!< CC312_DW (Bit 8) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_DW_Msk (0xf00UL) /*!< CC312_DW (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_CH_Pos (4UL) /*!< CC312_CH (Bit 4) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_CH_Msk (0xf0UL) /*!< CC312_CH (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_CW_Pos (0UL) /*!< CC312_CW (Bit 0) */ + #define CC312_CC312_HASH_PARAM_REG_CC312_CW_Msk (0xfUL) /*!< CC312_CW (Bitfield-Mask: 0x0f) */ +/* ============================================== CC312_HASH_SEL_AES_MAC_REG =============================================== */ + #define CC312_CC312_HASH_SEL_AES_MAC_REG_CC312_GHASH_SEL_Pos (1UL) /*!< CC312_GHASH_SEL (Bit 1) */ + #define CC312_CC312_HASH_SEL_AES_MAC_REG_CC312_GHASH_SEL_Msk (0x2UL) /*!< CC312_GHASH_SEL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HASH_SEL_AES_MAC_REG_CC312_HASH_SEL_AES_MAC_Pos (0UL) /*!< CC312_HASH_SEL_AES_MAC (Bit 0) */ + #define CC312_CC312_HASH_SEL_AES_MAC_REG_CC312_HASH_SEL_AES_MAC_Msk (0x1UL) /*!< CC312_HASH_SEL_AES_MAC (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_HASH_VERSION_REG ================================================= */ + #define CC312_CC312_HASH_VERSION_REG_CC312_MAJOR_VERSION_NUMBER_Pos (12UL) /*!< CC312_MAJOR_VERSION_NUMBER (Bit 12) */ + #define CC312_CC312_HASH_VERSION_REG_CC312_MAJOR_VERSION_NUMBER_Msk (0xf000UL) /*!< CC312_MAJOR_VERSION_NUMBER (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_HASH_VERSION_REG_CC312_MINOR_VERSION_NUMBER_Pos (8UL) /*!< CC312_MINOR_VERSION_NUMBER (Bit 8) */ + #define CC312_CC312_HASH_VERSION_REG_CC312_MINOR_VERSION_NUMBER_Msk (0xf00UL) /*!< CC312_MINOR_VERSION_NUMBER (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_HASH_VERSION_REG_CC312_FIXES_Pos (0UL) /*!< CC312_FIXES (Bit 0) */ + #define CC312_CC312_HASH_VERSION_REG_CC312_FIXES_Msk (0xffUL) /*!< CC312_FIXES (Bitfield-Mask: 0xff) */ +/* ================================================ CC312_HASH_XOR_DIN_REG ================================================= */ + #define CC312_CC312_HASH_XOR_DIN_REG_CC312_HASH_XOR_DATA_Pos (0UL) /*!< CC312_HASH_XOR_DATA (Bit 0) */ + #define CC312_CC312_HASH_XOR_DIN_REG_CC312_HASH_XOR_DATA_Msk (0xffffffffUL) /*!< CC312_HASH_XOR_DATA (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_HOST_AO_LOCK_BITS_REG ============================================== */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_DFA_ENABLE_LOCK_Pos (8UL) /*!< CC312_HOST_DFA_ENABLE_LOCK (Bit 8) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_DFA_ENABLE_LOCK_Msk (0x100UL) /*!< CC312_HOST_DFA_ENABLE_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_FORCE_DFA_ENABLE_Pos (7UL) /*!< CC312_HOST_FORCE_DFA_ENABLE (Bit 7) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_FORCE_DFA_ENABLE_Msk (0x80UL) /*!< CC312_HOST_FORCE_DFA_ENABLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_RESET_UPON_DEBUG_DISABLE_Pos (6UL) /*!< CC312_RESET_UPON_DEBUG_DISABLE (Bit 6) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_RESET_UPON_DEBUG_DISABLE_Msk (0x40UL) /*!< CC312_RESET_UPON_DEBUG_DISABLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_ICV_RMA_LOCK_Pos (5UL) /*!< CC312_HOST_ICV_RMA_LOCK (Bit 5) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_ICV_RMA_LOCK_Msk (0x20UL) /*!< CC312_HOST_ICV_RMA_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCE_LOCK_Pos (4UL) /*!< CC312_HOST_KCE_LOCK (Bit 4) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCE_LOCK_Msk (0x10UL) /*!< CC312_HOST_KCE_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCP_LOCK_Pos (3UL) /*!< CC312_HOST_KCP_LOCK (Bit 3) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCP_LOCK_Msk (0x8UL) /*!< CC312_HOST_KCP_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCEICV_LOCK_Pos (2UL) /*!< CC312_HOST_KCEICV_LOCK (Bit 2) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KCEICV_LOCK_Msk (0x4UL) /*!< CC312_HOST_KCEICV_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KPICV_LOCK_Pos (1UL) /*!< CC312_HOST_KPICV_LOCK (Bit 1) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_KPICV_LOCK_Msk (0x2UL) /*!< CC312_HOST_KPICV_LOCK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_FATAL_ERR_Pos (0UL) /*!< CC312_HOST_FATAL_ERR (Bit 0) */ + #define CC312_CC312_HOST_AO_LOCK_BITS_REG_CC312_HOST_FATAL_ERR_Msk (0x1UL) /*!< CC312_HOST_FATAL_ERR (Bitfield-Mask: 0x01) */ +/* ================================================== CC312_HOST_BOOT_REG ================================================== */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_EXISTS_LOCAL_Pos (30UL) /*!< CC312_AES_EXISTS_LOCAL (Bit 30) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_EXISTS_LOCAL_Msk (0x40000000UL) /*!< CC312_AES_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_ONLY_ENCRYPT_LOCAL_Pos (29UL) /*!< CC312_ONLY_ENCRYPT_LOCAL (Bit 29) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_ONLY_ENCRYPT_LOCAL_Msk (0x20000000UL) /*!< CC312_ONLY_ENCRYPT_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SUPPORT_256_192_KEY_LOCAL_Pos (28UL) /*!< CC312_SUPPORT_256_192_KEY_LOCAL (Bit 28) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SUPPORT_256_192_KEY_LOCAL_Msk (0x10000000UL) /*!< CC312_SUPPORT_256_192_KEY_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_TUNNELING_ENB_LOCAL_Pos (27UL) /*!< CC312_TUNNELING_ENB_LOCAL (Bit 27) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_TUNNELING_ENB_LOCAL_Msk (0x8000000UL) /*!< CC312_TUNNELING_ENB_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos (26UL) /*!< CC312_AES_DIN_BYTE_RESOLUTION_LOCAL (Bit 26) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_DIN_BYTE_RESOLUTION_LOCAL_Msk (0x4000000UL) /*!< CC312_AES_DIN_BYTE_RESOLUTION_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_CTR_EXISTS_LOCAL_Pos (25UL) /*!< CC312_CTR_EXISTS_LOCAL (Bit 25) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_CTR_EXISTS_LOCAL_Msk (0x2000000UL) /*!< CC312_CTR_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XEX_EXISTS_LOCAL_Pos (24UL) /*!< CC312_AES_XEX_EXISTS_LOCAL (Bit 24) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XEX_EXISTS_LOCAL_Msk (0x1000000UL) /*!< CC312_AES_XEX_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XEX_HW_T_CALC_LOCAL_Pos (23UL) /*!< CC312_AES_XEX_HW_T_CALC_LOCAL (Bit 23) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XEX_HW_T_CALC_LOCAL_Msk (0x800000UL) /*!< CC312_AES_XEX_HW_T_CALC_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_CCM_EXISTS_LOCAL_Pos (22UL) /*!< CC312_AES_CCM_EXISTS_LOCAL (Bit 22) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_CCM_EXISTS_LOCAL_Msk (0x400000UL) /*!< CC312_AES_CCM_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_CMAC_EXISTS_LOCAL_Pos (21UL) /*!< CC312_AES_CMAC_EXISTS_LOCAL (Bit 21) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_CMAC_EXISTS_LOCAL_Msk (0x200000UL) /*!< CC312_AES_CMAC_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XCBC_MAC_EXISTS_LOCAL_Pos (20UL) /*!< CC312_AES_XCBC_MAC_EXISTS_LOCAL (Bit 20) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_AES_XCBC_MAC_EXISTS_LOCAL_Msk (0x100000UL) /*!< CC312_AES_XCBC_MAC_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_DES_EXISTS_LOCAL_Pos (19UL) /*!< CC312_DES_EXISTS_LOCAL (Bit 19) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_DES_EXISTS_LOCAL_Msk (0x80000UL) /*!< CC312_DES_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_C2_EXISTS_LOCAL_Pos (18UL) /*!< CC312_C2_EXISTS_LOCAL (Bit 18) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_C2_EXISTS_LOCAL_Msk (0x40000UL) /*!< CC312_C2_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_HASH_EXISTS_LOCAL_Pos (17UL) /*!< CC312_HASH_EXISTS_LOCAL (Bit 17) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_HASH_EXISTS_LOCAL_Msk (0x20000UL) /*!< CC312_HASH_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_MD5_PRSNT_LOCAL_Pos (16UL) /*!< CC312_MD5_PRSNT_LOCAL (Bit 16) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_MD5_PRSNT_LOCAL_Msk (0x10000UL) /*!< CC312_MD5_PRSNT_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SHA_256_PRSNT_LOCAL_Pos (15UL) /*!< CC312_SHA_256_PRSNT_LOCAL (Bit 15) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SHA_256_PRSNT_LOCAL_Msk (0x8000UL) /*!< CC312_SHA_256_PRSNT_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SHA_512_PRSNT_LOCAL_Pos (14UL) /*!< CC312_SHA_512_PRSNT_LOCAL (Bit 14) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SHA_512_PRSNT_LOCAL_Msk (0x4000UL) /*!< CC312_SHA_512_PRSNT_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RC4_EXISTS_LOCAL_Pos (13UL) /*!< CC312_RC4_EXISTS_LOCAL (Bit 13) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RC4_EXISTS_LOCAL_Msk (0x2000UL) /*!< CC312_RC4_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_PKA_EXISTS_LOCAL_Pos (12UL) /*!< CC312_PKA_EXISTS_LOCAL (Bit 12) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_PKA_EXISTS_LOCAL_Msk (0x1000UL) /*!< CC312_PKA_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RNG_EXISTS_LOCAL_Pos (11UL) /*!< CC312_RNG_EXISTS_LOCAL (Bit 11) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RNG_EXISTS_LOCAL_Msk (0x800UL) /*!< CC312_RNG_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_PAU_EXISTS_LOCAL_Pos (10UL) /*!< CC312_PAU_EXISTS_LOCAL (Bit 10) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_PAU_EXISTS_LOCAL_Msk (0x400UL) /*!< CC312_PAU_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_DSCRPTR_EXISTS_LOCAL_Pos (9UL) /*!< CC312_DSCRPTR_EXISTS_LOCAL (Bit 9) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_DSCRPTR_EXISTS_LOCAL_Msk (0x200UL) /*!< CC312_DSCRPTR_EXISTS_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SRAM_SIZE_LOCAL_Pos (6UL) /*!< CC312_SRAM_SIZE_LOCAL (Bit 6) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SRAM_SIZE_LOCAL_Msk (0x1c0UL) /*!< CC312_SRAM_SIZE_LOCAL (Bitfield-Mask: 0x07) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RKEK_ECC_EXISTS_LOCAL_N_Pos (5UL) /*!< CC312_RKEK_ECC_EXISTS_LOCAL_N (Bit 5) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_RKEK_ECC_EXISTS_LOCAL_N_Msk (0x20UL) /*!< CC312_RKEK_ECC_EXISTS_LOCAL_N (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_EXT_MEM_SECURED_LOCAL_Pos (3UL) /*!< CC312_EXT_MEM_SECURED_LOCAL (Bit 3) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_EXT_MEM_SECURED_LOCAL_Msk (0x8UL) /*!< CC312_EXT_MEM_SECURED_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_HASH_IN_FUSES_LOCAL_Pos (2UL) /*!< CC312_HASH_IN_FUSES_LOCAL (Bit 2) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_HASH_IN_FUSES_LOCAL_Msk (0x4UL) /*!< CC312_HASH_IN_FUSES_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_LARGE_RKEK_LOCAL_Pos (1UL) /*!< CC312_LARGE_RKEK_LOCAL (Bit 1) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_LARGE_RKEK_LOCAL_Msk (0x2UL) /*!< CC312_LARGE_RKEK_LOCAL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SYNTHESIS_CONFIG_Pos (0UL) /*!< CC312_SYNTHESIS_CONFIG (Bit 0) */ + #define CC312_CC312_HOST_BOOT_REG_CC312_SYNTHESIS_CONFIG_Msk (0x1UL) /*!< CC312_SYNTHESIS_CONFIG (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_HOST_CC_IS_IDLE_REG =============================================== */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_CRYPTO_IS_IDLE_Pos (9UL) /*!< CC312_CRYPTO_IS_IDLE (Bit 9) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_CRYPTO_IS_IDLE_Msk (0x200UL) /*!< CC312_CRYPTO_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_PKA_IS_IDLE_Pos (8UL) /*!< CC312_PKA_IS_IDLE (Bit 8) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_PKA_IS_IDLE_Msk (0x100UL) /*!< CC312_PKA_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_RNG_IS_IDLE_Pos (7UL) /*!< CC312_RNG_IS_IDLE (Bit 7) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_RNG_IS_IDLE_Msk (0x80UL) /*!< CC312_RNG_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_FATAL_WR_Pos (6UL) /*!< CC312_FATAL_WR (Bit 6) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_FATAL_WR_Msk (0x40UL) /*!< CC312_FATAL_WR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_NVM_IS_IDLE_Pos (5UL) /*!< CC312_NVM_IS_IDLE (Bit 5) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_NVM_IS_IDLE_Msk (0x20UL) /*!< CC312_NVM_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_NVM_ARB_IS_IDLE_Pos (4UL) /*!< CC312_NVM_ARB_IS_IDLE (Bit 4) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_NVM_ARB_IS_IDLE_Msk (0x10UL) /*!< CC312_NVM_ARB_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_AHB_IS_IDLE_Pos (3UL) /*!< CC312_AHB_IS_IDLE (Bit 3) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_AHB_IS_IDLE_Msk (0x8UL) /*!< CC312_AHB_IS_IDLE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_SYM_IS_BUSY_Pos (2UL) /*!< CC312_SYM_IS_BUSY (Bit 2) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_SYM_IS_BUSY_Msk (0x4UL) /*!< CC312_SYM_IS_BUSY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_HOST_CC_IS_IDLE_EVENT_Pos (1UL) /*!< CC312_HOST_CC_IS_IDLE_EVENT (Bit 1) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_HOST_CC_IS_IDLE_EVENT_Msk (0x2UL) /*!< CC312_HOST_CC_IS_IDLE_EVENT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_HOST_CC_IS_IDLE_Pos (0UL) /*!< CC312_HOST_CC_IS_IDLE (Bit 0) */ + #define CC312_CC312_HOST_CC_IS_IDLE_REG_CC312_HOST_CC_IS_IDLE_Msk (0x1UL) /*!< CC312_HOST_CC_IS_IDLE (Bitfield-Mask: 0x01) */ +/* ========================================= CC312_HOST_CORE_CLK_GATING_ENABLE_REG ========================================= */ + #define CC312_CC312_HOST_CORE_CLK_GATING_ENABLE_REG_CC312_HOST_CORE_CLK_GATING_ENABLE_Pos (0UL) /*!< CC312_HOST_CORE_CLK_GATING_ENABLE (Bit 0) */ + #define CC312_CC312_HOST_CORE_CLK_GATING_ENABLE_REG_CC312_HOST_CORE_CLK_GATING_ENABLE_Msk (0x1UL) /*!< CC312_HOST_CORE_CLK_GATING_ENABLE (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_CRYPTOKEY_SEL_REG ============================================== */ + #define CC312_CC312_HOST_CRYPTOKEY_SEL_REG_CC312_SEL_CRYPTO_KEY_Pos (0UL) /*!< CC312_SEL_CRYPTO_KEY (Bit 0) */ + #define CC312_CC312_HOST_CRYPTOKEY_SEL_REG_CC312_SEL_CRYPTO_KEY_Msk (0x7UL) /*!< CC312_SEL_CRYPTO_KEY (Bitfield-Mask: 0x07) */ +/* ================================================ CC312_HOST_DCU_EN0_REG ================================================= */ + #define CC312_CC312_HOST_DCU_EN0_REG_CC312_HOST_DCU_EN0_Pos (0UL) /*!< CC312_HOST_DCU_EN0 (Bit 0) */ + #define CC312_CC312_HOST_DCU_EN0_REG_CC312_HOST_DCU_EN0_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_EN0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_HOST_DCU_EN1_REG ================================================= */ + #define CC312_CC312_HOST_DCU_EN1_REG_CC312_HOST_DCU_EN1_Pos (0UL) /*!< CC312_HOST_DCU_EN1 (Bit 0) */ + #define CC312_CC312_HOST_DCU_EN1_REG_CC312_HOST_DCU_EN1_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_EN1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_HOST_DCU_EN2_REG ================================================= */ + #define CC312_CC312_HOST_DCU_EN2_REG_CC312_HOST_DCU_EN2_Pos (0UL) /*!< CC312_HOST_DCU_EN2 (Bit 0) */ + #define CC312_CC312_HOST_DCU_EN2_REG_CC312_HOST_DCU_EN2_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_EN2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_HOST_DCU_EN3_REG ================================================= */ + #define CC312_CC312_HOST_DCU_EN3_REG_CC312_HOST_DCU_EN3_Pos (0UL) /*!< CC312_HOST_DCU_EN3 (Bit 0) */ + #define CC312_CC312_HOST_DCU_EN3_REG_CC312_HOST_DCU_EN3_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_EN3 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HOST_DCU_LOCK0_REG ================================================ */ + #define CC312_CC312_HOST_DCU_LOCK0_REG_CC312_HOST_DCU_LOCK0_Pos (0UL) /*!< CC312_HOST_DCU_LOCK0 (Bit 0) */ + #define CC312_CC312_HOST_DCU_LOCK0_REG_CC312_HOST_DCU_LOCK0_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_LOCK0 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HOST_DCU_LOCK1_REG ================================================ */ + #define CC312_CC312_HOST_DCU_LOCK1_REG_CC312_HOST_DCU_LOCK1_Pos (0UL) /*!< CC312_HOST_DCU_LOCK1 (Bit 0) */ + #define CC312_CC312_HOST_DCU_LOCK1_REG_CC312_HOST_DCU_LOCK1_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_LOCK1 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HOST_DCU_LOCK2_REG ================================================ */ + #define CC312_CC312_HOST_DCU_LOCK2_REG_CC312_HOST_DCU_LOCK2_Pos (0UL) /*!< CC312_HOST_DCU_LOCK2 (Bit 0) */ + #define CC312_CC312_HOST_DCU_LOCK2_REG_CC312_HOST_DCU_LOCK2_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_LOCK2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HOST_DCU_LOCK3_REG ================================================ */ + #define CC312_CC312_HOST_DCU_LOCK3_REG_CC312_HOST_DCU_LOCK3_Pos (0UL) /*!< CC312_HOST_DCU_LOCK3 (Bit 0) */ + #define CC312_CC312_HOST_DCU_LOCK3_REG_CC312_HOST_DCU_LOCK3_Msk (0xffffffffUL) /*!< CC312_HOST_DCU_LOCK3 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_HOST_POWERDOWN_REG ================================================ */ + #define CC312_CC312_HOST_POWERDOWN_REG_CC312_HOST_POWERDOWN_Pos (0UL) /*!< CC312_HOST_POWERDOWN (Bit 0) */ + #define CC312_CC312_HOST_POWERDOWN_REG_CC312_HOST_POWERDOWN_Msk (0x1UL) /*!< CC312_HOST_POWERDOWN (Bitfield-Mask: 0x01) */ +/* ========================================== CC312_HOST_REMOVE_CHACHA_ENGINE_REG ========================================== */ + #define CC312_CC312_HOST_REMOVE_CHACHA_ENGINE_REG_CC312_HOST_REMOVE_CHACHA_ENGINE_Pos (0UL) /*!< CC312_HOST_REMOVE_CHACHA_ENGINE (Bit 0) */ + #define CC312_CC312_HOST_REMOVE_CHACHA_ENGINE_REG_CC312_HOST_REMOVE_CHACHA_ENGINE_Msk (0x1UL) /*!< CC312_HOST_REMOVE_CHACHA_ENGINE (Bitfield-Mask: 0x01) */ +/* ========================================== CC312_HOST_REMOVE_GHASH_ENGINE_REG =========================================== */ + #define CC312_CC312_HOST_REMOVE_GHASH_ENGINE_REG_CC312_HOST_REMOVE_GHASH_ENGINE_Pos (0UL) /*!< CC312_HOST_REMOVE_GHASH_ENGINE (Bit 0) */ + #define CC312_CC312_HOST_REMOVE_GHASH_ENGINE_REG_CC312_HOST_REMOVE_GHASH_ENGINE_Msk (0x1UL) /*!< CC312_HOST_REMOVE_GHASH_ENGINE (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_RGF_CC_SW_RST_REG ============================================== */ + #define CC312_CC312_HOST_RGF_CC_SW_RST_REG_CC312_HOST_RGF_CC_SW_RST_Pos (0UL) /*!< CC312_HOST_RGF_CC_SW_RST (Bit 0) */ + #define CC312_CC312_HOST_RGF_CC_SW_RST_REG_CC312_HOST_RGF_CC_SW_RST_Msk (0x1UL) /*!< CC312_HOST_RGF_CC_SW_RST (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_HOST_RGF_ENDIAN_REG =============================================== */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DIN_RD_WBG_Pos (15UL) /*!< CC312_DIN_RD_WBG (Bit 15) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DIN_RD_WBG_Msk (0x8000UL) /*!< CC312_DIN_RD_WBG (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DOUT_WR_WBG_Pos (11UL) /*!< CC312_DOUT_WR_WBG (Bit 11) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DOUT_WR_WBG_Msk (0x800UL) /*!< CC312_DOUT_WR_WBG (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DIN_RD_BG_Pos (7UL) /*!< CC312_DIN_RD_BG (Bit 7) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DIN_RD_BG_Msk (0x80UL) /*!< CC312_DIN_RD_BG (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DOUT_WR_BG_Pos (3UL) /*!< CC312_DOUT_WR_BG (Bit 3) */ + #define CC312_CC312_HOST_RGF_ENDIAN_REG_CC312_DOUT_WR_BG_Msk (0x8UL) /*!< CC312_DOUT_WR_BG (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_HOST_RGF_ICR_REG ================================================= */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_SYM_DMA_COMPLETED_CLEAR_Pos (11UL) /*!< CC312_SYM_DMA_COMPLETED_CLEAR (Bit 11) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_SYM_DMA_COMPLETED_CLEAR_Msk (0x800UL) /*!< CC312_SYM_DMA_COMPLETED_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_RNG_INT_CLEAR_Pos (10UL) /*!< CC312_RNG_INT_CLEAR (Bit 10) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_RNG_INT_CLEAR_Msk (0x400UL) /*!< CC312_RNG_INT_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_PKA_EXP_CLEAR_Pos (9UL) /*!< CC312_PKA_EXP_CLEAR (Bit 9) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_PKA_EXP_CLEAR_Msk (0x200UL) /*!< CC312_PKA_EXP_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_AXI_ERR_CLEAR_Pos (8UL) /*!< CC312_AXI_ERR_CLEAR (Bit 8) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_AXI_ERR_CLEAR_Msk (0x100UL) /*!< CC312_AXI_ERR_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_DOUT_TO_MEM_CLEAR_Pos (7UL) /*!< CC312_DOUT_TO_MEM_CLEAR (Bit 7) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_DOUT_TO_MEM_CLEAR_Msk (0x80UL) /*!< CC312_DOUT_TO_MEM_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_MEM_TO_DIN_CLEAR_Pos (6UL) /*!< CC312_MEM_TO_DIN_CLEAR (Bit 6) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_MEM_TO_DIN_CLEAR_Msk (0x40UL) /*!< CC312_MEM_TO_DIN_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_DOUT_TO_SRAM_CLEAR_Pos (5UL) /*!< CC312_DOUT_TO_SRAM_CLEAR (Bit 5) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_DOUT_TO_SRAM_CLEAR_Msk (0x20UL) /*!< CC312_DOUT_TO_SRAM_CLEAR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_SRAM_TO_DIN_CLEAR_Pos (4UL) /*!< CC312_SRAM_TO_DIN_CLEAR (Bit 4) */ + #define CC312_CC312_HOST_RGF_ICR_REG_CC312_SRAM_TO_DIN_CLEAR_Msk (0x10UL) /*!< CC312_SRAM_TO_DIN_CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_HOST_RGF_IMR_REG ================================================= */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_SYM_DMA_COMPLETED_MASK_Pos (11UL) /*!< CC312_SYM_DMA_COMPLETED_MASK (Bit 11) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_SYM_DMA_COMPLETED_MASK_Msk (0x800UL) /*!< CC312_SYM_DMA_COMPLETED_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_RNG_INT_MASK_Pos (10UL) /*!< CC312_RNG_INT_MASK (Bit 10) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_RNG_INT_MASK_Msk (0x400UL) /*!< CC312_RNG_INT_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_PKA_EXP_MASK_Pos (9UL) /*!< CC312_PKA_EXP_MASK (Bit 9) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_PKA_EXP_MASK_Msk (0x200UL) /*!< CC312_PKA_EXP_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_AXI_ERR_MASK_Pos (8UL) /*!< CC312_AXI_ERR_MASK (Bit 8) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_AXI_ERR_MASK_Msk (0x100UL) /*!< CC312_AXI_ERR_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_DOUT_TO_MEM_MASK_Pos (7UL) /*!< CC312_DOUT_TO_MEM_MASK (Bit 7) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_DOUT_TO_MEM_MASK_Msk (0x80UL) /*!< CC312_DOUT_TO_MEM_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_MEM_TO_DIN_MASK_Pos (6UL) /*!< CC312_MEM_TO_DIN_MASK (Bit 6) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_MEM_TO_DIN_MASK_Msk (0x40UL) /*!< CC312_MEM_TO_DIN_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_DOUT_TO_SRAM_MASK_Pos (5UL) /*!< CC312_DOUT_TO_SRAM_MASK (Bit 5) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_DOUT_TO_SRAM_MASK_Msk (0x20UL) /*!< CC312_DOUT_TO_SRAM_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_SRAM_TO_DIN_MASK_Pos (4UL) /*!< CC312_SRAM_TO_DIN_MASK (Bit 4) */ + #define CC312_CC312_HOST_RGF_IMR_REG_CC312_SRAM_TO_DIN_MASK_Msk (0x10UL) /*!< CC312_SRAM_TO_DIN_MASK (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_HOST_RGF_IRR_REG ================================================= */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_SYM_DMA_COMPLETED_Pos (11UL) /*!< CC312_SYM_DMA_COMPLETED (Bit 11) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_SYM_DMA_COMPLETED_Msk (0x800UL) /*!< CC312_SYM_DMA_COMPLETED (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_RNG_INT_Pos (10UL) /*!< CC312_RNG_INT (Bit 10) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_RNG_INT_Msk (0x400UL) /*!< CC312_RNG_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_PKA_EXP_INT_Pos (9UL) /*!< CC312_PKA_EXP_INT (Bit 9) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_PKA_EXP_INT_Msk (0x200UL) /*!< CC312_PKA_EXP_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_AHB_ERR_INT_Pos (8UL) /*!< CC312_AHB_ERR_INT (Bit 8) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_AHB_ERR_INT_Msk (0x100UL) /*!< CC312_AHB_ERR_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_DOUT_TO_MEM_INT_Pos (7UL) /*!< CC312_DOUT_TO_MEM_INT (Bit 7) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_DOUT_TO_MEM_INT_Msk (0x80UL) /*!< CC312_DOUT_TO_MEM_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_MEM_TO_DIN_INT_Pos (6UL) /*!< CC312_MEM_TO_DIN_INT (Bit 6) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_MEM_TO_DIN_INT_Msk (0x40UL) /*!< CC312_MEM_TO_DIN_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_DOUT_TO_SRAM_INT_Pos (5UL) /*!< CC312_DOUT_TO_SRAM_INT (Bit 5) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_DOUT_TO_SRAM_INT_Msk (0x20UL) /*!< CC312_DOUT_TO_SRAM_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_SRAM_TO_DIN_INT_Pos (4UL) /*!< CC312_SRAM_TO_DIN_INT (Bit 4) */ + #define CC312_CC312_HOST_RGF_IRR_REG_CC312_SRAM_TO_DIN_INT_Msk (0x10UL) /*!< CC312_SRAM_TO_DIN_INT (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_RGF_SIGNATURE_REG ============================================== */ + #define CC312_CC312_HOST_RGF_SIGNATURE_REG_CC312_HOST_SIGNATURE_Pos (0UL) /*!< CC312_HOST_SIGNATURE (Bit 0) */ + #define CC312_CC312_HOST_RGF_SIGNATURE_REG_CC312_HOST_SIGNATURE_Msk (0xffffffffUL) /*!< CC312_HOST_SIGNATURE (Bitfield-Mask: 0xffffffff) */ +/* =========================================== CC312_HOST_SHADOW_KCEICV_REG_REG ============================================ */ + #define CC312_CC312_HOST_SHADOW_KCEICV_REG_REG_CC312_HOST_SHADOW_KCEICV_REG_Pos (0UL) /*!< CC312_HOST_SHADOW_KCEICV_REG (Bit 0) */ + #define CC312_CC312_HOST_SHADOW_KCEICV_REG_REG_CC312_HOST_SHADOW_KCEICV_REG_Msk (0x1UL) /*!< CC312_HOST_SHADOW_KCEICV_REG (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_SHADOW_KCE_REG_REG ============================================= */ + #define CC312_CC312_HOST_SHADOW_KCE_REG_REG_CC312_HOST_SHADOW_KCE_REG_Pos (0UL) /*!< CC312_HOST_SHADOW_KCE_REG (Bit 0) */ + #define CC312_CC312_HOST_SHADOW_KCE_REG_REG_CC312_HOST_SHADOW_KCE_REG_Msk (0x1UL) /*!< CC312_HOST_SHADOW_KCE_REG (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_SHADOW_KCP_REG_REG ============================================= */ + #define CC312_CC312_HOST_SHADOW_KCP_REG_REG_CC312_HOST_SHADOW_KCP_REG_Pos (0UL) /*!< CC312_HOST_SHADOW_KCP_REG (Bit 0) */ + #define CC312_CC312_HOST_SHADOW_KCP_REG_REG_CC312_HOST_SHADOW_KCP_REG_Msk (0x1UL) /*!< CC312_HOST_SHADOW_KCP_REG (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_HOST_SHADOW_KDR_REG_REG ============================================= */ + #define CC312_CC312_HOST_SHADOW_KDR_REG_REG_CC312_HOST_SHADOW_KDR_REG_Pos (0UL) /*!< CC312_HOST_SHADOW_KDR_REG (Bit 0) */ + #define CC312_CC312_HOST_SHADOW_KDR_REG_REG_CC312_HOST_SHADOW_KDR_REG_Msk (0x1UL) /*!< CC312_HOST_SHADOW_KDR_REG (Bitfield-Mask: 0x01) */ +/* ============================================ CC312_HOST_SHADOW_KPICV_REG_REG ============================================ */ + #define CC312_CC312_HOST_SHADOW_KPICV_REG_REG_CC312_HOST_SHADOW_KPICV_REG_Pos (0UL) /*!< CC312_HOST_SHADOW_KPICV_REG (Bit 0) */ + #define CC312_CC312_HOST_SHADOW_KPICV_REG_REG_CC312_HOST_SHADOW_KPICV_REG_Msk (0x1UL) /*!< CC312_HOST_SHADOW_KPICV_REG (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_LCS_IS_VALID_REG ================================================= */ + #define CC312_CC312_LCS_IS_VALID_REG_CC312_LCS_IS_VALID_Pos (0UL) /*!< CC312_LCS_IS_VALID (Bit 0) */ + #define CC312_CC312_LCS_IS_VALID_REG_CC312_LCS_IS_VALID_Msk (0x1UL) /*!< CC312_LCS_IS_VALID (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_LCS_REG_REG =================================================== */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KCEICV_ZERO_CNT_Pos (12UL) /*!< CC312_ERROR_KCEICV_ZERO_CNT (Bit 12) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KCEICV_ZERO_CNT_Msk (0x1000UL) /*!< CC312_ERROR_KCEICV_ZERO_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KPICV_ZERO_CNT_Pos (11UL) /*!< CC312_ERROR_KPICV_ZERO_CNT (Bit 11) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KPICV_ZERO_CNT_Msk (0x800UL) /*!< CC312_ERROR_KPICV_ZERO_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KCE_ZERO_CNT_Pos (10UL) /*!< CC312_ERROR_KCE_ZERO_CNT (Bit 10) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KCE_ZERO_CNT_Msk (0x400UL) /*!< CC312_ERROR_KCE_ZERO_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_PROV_ZERO_CNT_Pos (9UL) /*!< CC312_ERROR_PROV_ZERO_CNT (Bit 9) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_PROV_ZERO_CNT_Msk (0x200UL) /*!< CC312_ERROR_PROV_ZERO_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KDR_ZERO_CNT_Pos (8UL) /*!< CC312_ERROR_KDR_ZERO_CNT (Bit 8) */ + #define CC312_CC312_LCS_REG_REG_CC312_ERROR_KDR_ZERO_CNT_Msk (0x100UL) /*!< CC312_ERROR_KDR_ZERO_CNT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_LCS_REG_REG_CC312_LCS_REG_Pos (0UL) /*!< CC312_LCS_REG (Bit 0) */ + #define CC312_CC312_LCS_REG_REG_CC312_LCS_REG_Msk (0x7UL) /*!< CC312_LCS_REG (Bitfield-Mask: 0x07) */ +/* =============================================== CC312_LOAD_INIT_STATE_REG =============================================== */ + #define CC312_CC312_LOAD_INIT_STATE_REG_CC312_LOAD_Pos (0UL) /*!< CC312_LOAD (Bit 0) */ + #define CC312_CC312_LOAD_INIT_STATE_REG_CC312_LOAD_Msk (0x1UL) /*!< CC312_LOAD (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_MEMORY_MAP0_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP0_REG_CC312_MEMORY_MAP0_Pos (1UL) /*!< CC312_MEMORY_MAP0 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP0_REG_CC312_MEMORY_MAP0_Msk (0x7feUL) /*!< CC312_MEMORY_MAP0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP10_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP10_REG_CC312_MEMORY_MAP10_Pos (1UL) /*!< CC312_MEMORY_MAP10 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP10_REG_CC312_MEMORY_MAP10_Msk (0x7feUL) /*!< CC312_MEMORY_MAP10 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP11_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP11_REG_CC312_MEMORY_MAP11_Pos (1UL) /*!< CC312_MEMORY_MAP11 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP11_REG_CC312_MEMORY_MAP11_Msk (0x7feUL) /*!< CC312_MEMORY_MAP11 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP12_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP12_REG_CC312_MEMORY_MAP12_Pos (1UL) /*!< CC312_MEMORY_MAP12 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP12_REG_CC312_MEMORY_MAP12_Msk (0x7feUL) /*!< CC312_MEMORY_MAP12 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP13_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP13_REG_CC312_MEMORY_MAP13_Pos (1UL) /*!< CC312_MEMORY_MAP13 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP13_REG_CC312_MEMORY_MAP13_Msk (0x7feUL) /*!< CC312_MEMORY_MAP13 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP14_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP14_REG_CC312_MEMORY_MAP14_Pos (1UL) /*!< CC312_MEMORY_MAP14 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP14_REG_CC312_MEMORY_MAP14_Msk (0x7feUL) /*!< CC312_MEMORY_MAP14 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP15_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP15_REG_CC312_MEMORY_MAP15_Pos (1UL) /*!< CC312_MEMORY_MAP15 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP15_REG_CC312_MEMORY_MAP15_Msk (0x7feUL) /*!< CC312_MEMORY_MAP15 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP16_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP16_REG_CC312_MEMORY_MAP16_Pos (1UL) /*!< CC312_MEMORY_MAP16 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP16_REG_CC312_MEMORY_MAP16_Msk (0x7feUL) /*!< CC312_MEMORY_MAP16 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP17_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP17_REG_CC312_MEMORY_MAP17_Pos (1UL) /*!< CC312_MEMORY_MAP17 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP17_REG_CC312_MEMORY_MAP17_Msk (0x7feUL) /*!< CC312_MEMORY_MAP17 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP18_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP18_REG_CC312_MEMORY_MAP18_Pos (1UL) /*!< CC312_MEMORY_MAP18 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP18_REG_CC312_MEMORY_MAP18_Msk (0x7feUL) /*!< CC312_MEMORY_MAP18 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP19_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP19_REG_CC312_MEMORY_MAP19_Pos (1UL) /*!< CC312_MEMORY_MAP19 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP19_REG_CC312_MEMORY_MAP19_Msk (0x7feUL) /*!< CC312_MEMORY_MAP19 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP1_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP1_REG_CC312_MEMORY_MAP1_Pos (1UL) /*!< CC312_MEMORY_MAP1 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP1_REG_CC312_MEMORY_MAP1_Msk (0x7feUL) /*!< CC312_MEMORY_MAP1 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP20_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP20_REG_CC312_MEMORY_MAP20_Pos (1UL) /*!< CC312_MEMORY_MAP20 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP20_REG_CC312_MEMORY_MAP20_Msk (0x7feUL) /*!< CC312_MEMORY_MAP20 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP21_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP21_REG_CC312_MEMORY_MAP21_Pos (1UL) /*!< CC312_MEMORY_MAP21 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP21_REG_CC312_MEMORY_MAP21_Msk (0x7feUL) /*!< CC312_MEMORY_MAP21 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP22_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP22_REG_CC312_MEMORY_MAP22_Pos (1UL) /*!< CC312_MEMORY_MAP22 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP22_REG_CC312_MEMORY_MAP22_Msk (0x7feUL) /*!< CC312_MEMORY_MAP22 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP23_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP23_REG_CC312_MEMORY_MAP23_Pos (1UL) /*!< CC312_MEMORY_MAP23 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP23_REG_CC312_MEMORY_MAP23_Msk (0x7feUL) /*!< CC312_MEMORY_MAP23 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP24_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP24_REG_CC312_MEMORY_MAP24_Pos (1UL) /*!< CC312_MEMORY_MAP24 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP24_REG_CC312_MEMORY_MAP24_Msk (0x7feUL) /*!< CC312_MEMORY_MAP24 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP25_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP25_REG_CC312_MEMORY_MAP25_Pos (1UL) /*!< CC312_MEMORY_MAP25 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP25_REG_CC312_MEMORY_MAP25_Msk (0x7feUL) /*!< CC312_MEMORY_MAP25 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP26_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP26_REG_CC312_MEMORY_MAP26_Pos (1UL) /*!< CC312_MEMORY_MAP26 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP26_REG_CC312_MEMORY_MAP26_Msk (0x7feUL) /*!< CC312_MEMORY_MAP26 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP27_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP27_REG_CC312_MEMORY_MAP27_Pos (1UL) /*!< CC312_MEMORY_MAP27 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP27_REG_CC312_MEMORY_MAP27_Msk (0x7feUL) /*!< CC312_MEMORY_MAP27 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP28_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP28_REG_CC312_MEMORY_MAP28_Pos (1UL) /*!< CC312_MEMORY_MAP28 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP28_REG_CC312_MEMORY_MAP28_Msk (0x7feUL) /*!< CC312_MEMORY_MAP28 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP29_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP29_REG_CC312_MEMORY_MAP29_Pos (1UL) /*!< CC312_MEMORY_MAP29 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP29_REG_CC312_MEMORY_MAP29_Msk (0x7feUL) /*!< CC312_MEMORY_MAP29 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP2_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP2_REG_CC312_MEMORY_MAP2_Pos (1UL) /*!< CC312_MEMORY_MAP2 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP2_REG_CC312_MEMORY_MAP2_Msk (0x7feUL) /*!< CC312_MEMORY_MAP2 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP30_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP30_REG_CC312_MEMORY_MAP30_Pos (1UL) /*!< CC312_MEMORY_MAP30 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP30_REG_CC312_MEMORY_MAP30_Msk (0x7feUL) /*!< CC312_MEMORY_MAP30 (Bitfield-Mask: 0x3ff) */ +/* ================================================ CC312_MEMORY_MAP31_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP31_REG_CC312_MEMORY_MAP31_Pos (1UL) /*!< CC312_MEMORY_MAP31 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP31_REG_CC312_MEMORY_MAP31_Msk (0x7feUL) /*!< CC312_MEMORY_MAP31 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP3_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP3_REG_CC312_MEMORY_MAP3_Pos (1UL) /*!< CC312_MEMORY_MAP3 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP3_REG_CC312_MEMORY_MAP3_Msk (0x7feUL) /*!< CC312_MEMORY_MAP3 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP4_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP4_REG_CC312_MEMORY_MAP4_Pos (1UL) /*!< CC312_MEMORY_MAP4 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP4_REG_CC312_MEMORY_MAP4_Msk (0x7feUL) /*!< CC312_MEMORY_MAP4 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP5_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP5_REG_CC312_MEMORY_MAP5_Pos (1UL) /*!< CC312_MEMORY_MAP5 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP5_REG_CC312_MEMORY_MAP5_Msk (0x7feUL) /*!< CC312_MEMORY_MAP5 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP6_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP6_REG_CC312_MEMORY_MAP6_Pos (1UL) /*!< CC312_MEMORY_MAP6 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP6_REG_CC312_MEMORY_MAP6_Msk (0x7feUL) /*!< CC312_MEMORY_MAP6 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP7_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP7_REG_CC312_MEMORY_MAP7_Pos (1UL) /*!< CC312_MEMORY_MAP7 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP7_REG_CC312_MEMORY_MAP7_Msk (0x7feUL) /*!< CC312_MEMORY_MAP7 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP8_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP8_REG_CC312_MEMORY_MAP8_Pos (1UL) /*!< CC312_MEMORY_MAP8 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP8_REG_CC312_MEMORY_MAP8_Msk (0x7feUL) /*!< CC312_MEMORY_MAP8 (Bitfield-Mask: 0x3ff) */ +/* ================================================= CC312_MEMORY_MAP9_REG ================================================= */ + #define CC312_CC312_MEMORY_MAP9_REG_CC312_MEMORY_MAP9_Pos (1UL) /*!< CC312_MEMORY_MAP9 (Bit 1) */ + #define CC312_CC312_MEMORY_MAP9_REG_CC312_MEMORY_MAP9_Msk (0x7feUL) /*!< CC312_MEMORY_MAP9 (Bitfield-Mask: 0x3ff) */ +/* ============================================== CC312_NVM_DEBUG_STATUS_REG =============================================== */ + #define CC312_CC312_NVM_DEBUG_STATUS_REG_CC312_NVM_SM_Pos (1UL) /*!< CC312_NVM_SM (Bit 1) */ + #define CC312_CC312_NVM_DEBUG_STATUS_REG_CC312_NVM_SM_Msk (0xeUL) /*!< CC312_NVM_SM (Bitfield-Mask: 0x07) */ +/* ================================================= CC312_NVM_IS_IDLE_REG ================================================= */ + #define CC312_CC312_NVM_IS_IDLE_REG_CC312_NVM_IS_IDLE_STATUS_Pos (0UL) /*!< CC312_NVM_IS_IDLE_STATUS (Bit 0) */ + #define CC312_CC312_NVM_IS_IDLE_REG_CC312_NVM_IS_IDLE_STATUS_Msk (0x1UL) /*!< CC312_NVM_IS_IDLE_STATUS (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_N_NP_T0_T1_ADDR_REG =============================================== */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_T1_VIRTUAL_ADDR_Pos (15UL) /*!< CC312_T1_VIRTUAL_ADDR (Bit 15) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_T1_VIRTUAL_ADDR_Msk (0xf8000UL) /*!< CC312_T1_VIRTUAL_ADDR (Bitfield-Mask: 0x1f) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_T0_VIRTUAL_ADDR_Pos (10UL) /*!< CC312_T0_VIRTUAL_ADDR (Bit 10) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_T0_VIRTUAL_ADDR_Msk (0x7c00UL) /*!< CC312_T0_VIRTUAL_ADDR (Bitfield-Mask: 0x1f) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_NP_VIRTUAL_ADDR_Pos (5UL) /*!< CC312_NP_VIRTUAL_ADDR (Bit 5) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_NP_VIRTUAL_ADDR_Msk (0x3e0UL) /*!< CC312_NP_VIRTUAL_ADDR (Bitfield-Mask: 0x1f) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_N_VIRTUAL_ADDR_Pos (0UL) /*!< CC312_N_VIRTUAL_ADDR (Bit 0) */ + #define CC312_CC312_N_NP_T0_T1_ADDR_REG_CC312_N_VIRTUAL_ADDR_Msk (0x1fUL) /*!< CC312_N_VIRTUAL_ADDR (Bitfield-Mask: 0x1f) */ +/* =================================================== CC312_OPCODE_REG ==================================================== */ + #define CC312_CC312_OPCODE_REG_CC312_PKA_OPCODE_Pos (27UL) /*!< CC312_PKA_OPCODE (Bit 27) */ + #define CC312_CC312_OPCODE_REG_CC312_PKA_OPCODE_Msk (0xf8000000UL) /*!< CC312_PKA_OPCODE (Bitfield-Mask: 0x1f) */ + #define CC312_CC312_OPCODE_REG_CC312_LEN_Pos (24UL) /*!< CC312_LEN (Bit 24) */ + #define CC312_CC312_OPCODE_REG_CC312_LEN_Msk (0x7000000UL) /*!< CC312_LEN (Bitfield-Mask: 0x07) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_A_Pos (18UL) /*!< CC312_REG_A (Bit 18) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_A_Msk (0xfc0000UL) /*!< CC312_REG_A (Bitfield-Mask: 0x3f) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_B_Pos (12UL) /*!< CC312_REG_B (Bit 12) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_B_Msk (0x3f000UL) /*!< CC312_REG_B (Bitfield-Mask: 0x3f) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_R_Pos (6UL) /*!< CC312_REG_R (Bit 6) */ + #define CC312_CC312_OPCODE_REG_CC312_REG_R_Msk (0xfc0UL) /*!< CC312_REG_R (Bitfield-Mask: 0x3f) */ + #define CC312_CC312_OPCODE_REG_CC312_TAG_Pos (0UL) /*!< CC312_TAG (Bit 0) */ + #define CC312_CC312_OPCODE_REG_CC312_TAG_Msk (0x3fUL) /*!< CC312_TAG (Bitfield-Mask: 0x3f) */ +/* ============================================= CC312_OTP_ADDR_WIDTH_DEF_REG ============================================== */ + #define CC312_CC312_OTP_ADDR_WIDTH_DEF_REG_CC312_OTP_ADDR_WIDTH_DEF_Pos (0UL) /*!< CC312_OTP_ADDR_WIDTH_DEF (Bit 0) */ + #define CC312_CC312_OTP_ADDR_WIDTH_DEF_REG_CC312_OTP_ADDR_WIDTH_DEF_Msk (0xfUL) /*!< CC312_OTP_ADDR_WIDTH_DEF (Bitfield-Mask: 0x0f) */ +/* =============================================== CC312_PERIPHERAL_ID_0_REG =============================================== */ + #define CC312_CC312_PERIPHERAL_ID_0_REG_CC312_PART_0_Pos (0UL) /*!< CC312_PART_0 (Bit 0) */ + #define CC312_CC312_PERIPHERAL_ID_0_REG_CC312_PART_0_Msk (0xffUL) /*!< CC312_PART_0 (Bitfield-Mask: 0xff) */ +/* =============================================== CC312_PERIPHERAL_ID_1_REG =============================================== */ + #define CC312_CC312_PERIPHERAL_ID_1_REG_CC312_DES_0_JEP106_Pos (4UL) /*!< CC312_DES_0_JEP106 (Bit 4) */ + #define CC312_CC312_PERIPHERAL_ID_1_REG_CC312_DES_0_JEP106_Msk (0xf0UL) /*!< CC312_DES_0_JEP106 (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_PERIPHERAL_ID_1_REG_CC312_PART_1_Pos (0UL) /*!< CC312_PART_1 (Bit 0) */ + #define CC312_CC312_PERIPHERAL_ID_1_REG_CC312_PART_1_Msk (0xfUL) /*!< CC312_PART_1 (Bitfield-Mask: 0x0f) */ +/* =============================================== CC312_PERIPHERAL_ID_2_REG =============================================== */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_REVISION_Pos (4UL) /*!< CC312_REVISION (Bit 4) */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_REVISION_Msk (0xf0UL) /*!< CC312_REVISION (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_JEDEC_Pos (3UL) /*!< CC312_JEDEC (Bit 3) */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_JEDEC_Msk (0x8UL) /*!< CC312_JEDEC (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_DES_1_JEP106_Pos (0UL) /*!< CC312_DES_1_JEP106 (Bit 0) */ + #define CC312_CC312_PERIPHERAL_ID_2_REG_CC312_DES_1_JEP106_Msk (0x7UL) /*!< CC312_DES_1_JEP106 (Bitfield-Mask: 0x07) */ +/* =============================================== CC312_PERIPHERAL_ID_3_REG =============================================== */ + #define CC312_CC312_PERIPHERAL_ID_3_REG_CC312_REVAND_Pos (4UL) /*!< CC312_REVAND (Bit 4) */ + #define CC312_CC312_PERIPHERAL_ID_3_REG_CC312_REVAND_Msk (0xf0UL) /*!< CC312_REVAND (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_PERIPHERAL_ID_3_REG_CC312_CMOD_Pos (0UL) /*!< CC312_CMOD (Bit 0) */ + #define CC312_CC312_PERIPHERAL_ID_3_REG_CC312_CMOD_Msk (0xfUL) /*!< CC312_CMOD (Bitfield-Mask: 0x0f) */ +/* =============================================== CC312_PERIPHERAL_ID_4_REG =============================================== */ + #define CC312_CC312_PERIPHERAL_ID_4_REG_CC312_DES_2_JEP106_Pos (0UL) /*!< CC312_DES_2_JEP106 (Bit 0) */ + #define CC312_CC312_PERIPHERAL_ID_4_REG_CC312_DES_2_JEP106_Msk (0xfUL) /*!< CC312_DES_2_JEP106 (Bitfield-Mask: 0x0f) */ +/* ================================================ CC312_PIDRESERVED0_REG ================================================= */ +/* ================================================ CC312_PIDRESERVED1_REG ================================================= */ +/* ================================================ CC312_PIDRESERVED2_REG ================================================= */ +/* ================================================ CC312_PKA_BUFF_ADDR_REG ================================================ */ + #define CC312_CC312_PKA_BUFF_ADDR_REG_CC312_PKA_BUF_ADDR_Pos (0UL) /*!< CC312_PKA_BUF_ADDR (Bit 0) */ + #define CC312_CC312_PKA_BUFF_ADDR_REG_CC312_PKA_BUF_ADDR_Msk (0xfffUL) /*!< CC312_PKA_BUF_ADDR (Bitfield-Mask: 0xfff) */ +/* =============================================== CC312_PKA_CLK_ENABLE_REG ================================================ */ + #define CC312_CC312_PKA_CLK_ENABLE_REG_CC312_PKA_CLK_EN_Pos (0UL) /*!< CC312_PKA_CLK_EN (Bit 0) */ + #define CC312_CC312_PKA_CLK_ENABLE_REG_CC312_PKA_CLK_EN_Msk (0x1UL) /*!< CC312_PKA_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================== CC312_PKA_DONE_REG =================================================== */ + #define CC312_CC312_PKA_DONE_REG_CC312_PKA_DONE_Pos (0UL) /*!< CC312_PKA_DONE (Bit 0) */ + #define CC312_CC312_PKA_DONE_REG_CC312_PKA_DONE_Msk (0x1UL) /*!< CC312_PKA_DONE (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_PKA_L0_REG ==================================================== */ + #define CC312_CC312_PKA_L0_REG_CC312_PKA_L0_Pos (0UL) /*!< CC312_PKA_L0 (Bit 0) */ + #define CC312_CC312_PKA_L0_REG_CC312_PKA_L0_Msk (0x1fffUL) /*!< CC312_PKA_L0 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L1_REG ==================================================== */ + #define CC312_CC312_PKA_L1_REG_CC312_PKA_L1_Pos (0UL) /*!< CC312_PKA_L1 (Bit 0) */ + #define CC312_CC312_PKA_L1_REG_CC312_PKA_L1_Msk (0x1fffUL) /*!< CC312_PKA_L1 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L2_REG ==================================================== */ + #define CC312_CC312_PKA_L2_REG_CC312_PKA_L2_Pos (0UL) /*!< CC312_PKA_L2 (Bit 0) */ + #define CC312_CC312_PKA_L2_REG_CC312_PKA_L2_Msk (0x1fffUL) /*!< CC312_PKA_L2 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L3_REG ==================================================== */ + #define CC312_CC312_PKA_L3_REG_CC312_PKA_L3_Pos (0UL) /*!< CC312_PKA_L3 (Bit 0) */ + #define CC312_CC312_PKA_L3_REG_CC312_PKA_L3_Msk (0x1fffUL) /*!< CC312_PKA_L3 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L4_REG ==================================================== */ + #define CC312_CC312_PKA_L4_REG_CC312_PKA_L4_Pos (0UL) /*!< CC312_PKA_L4 (Bit 0) */ + #define CC312_CC312_PKA_L4_REG_CC312_PKA_L4_Msk (0x1fffUL) /*!< CC312_PKA_L4 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L5_REG ==================================================== */ + #define CC312_CC312_PKA_L5_REG_CC312_PKA_L5_Pos (0UL) /*!< CC312_PKA_L5 (Bit 0) */ + #define CC312_CC312_PKA_L5_REG_CC312_PKA_L5_Msk (0x1fffUL) /*!< CC312_PKA_L5 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L6_REG ==================================================== */ + #define CC312_CC312_PKA_L6_REG_CC312_PKA_L6_Pos (0UL) /*!< CC312_PKA_L6 (Bit 0) */ + #define CC312_CC312_PKA_L6_REG_CC312_PKA_L6_Msk (0x1fffUL) /*!< CC312_PKA_L6 (Bitfield-Mask: 0x1fff) */ +/* =================================================== CC312_PKA_L7_REG ==================================================== */ + #define CC312_CC312_PKA_L7_REG_CC312_PKA_L7_Pos (0UL) /*!< CC312_PKA_L7 (Bit 0) */ + #define CC312_CC312_PKA_L7_REG_CC312_PKA_L7_Msk (0x1fffUL) /*!< CC312_PKA_L7 (Bitfield-Mask: 0x1fff) */ +/* ================================================ CC312_PKA_MON_READ_REG ================================================= */ + #define CC312_CC312_PKA_MON_READ_REG_CC312_PKA_MON_READ_Pos (0UL) /*!< CC312_PKA_MON_READ (Bit 0) */ + #define CC312_CC312_PKA_MON_READ_REG_CC312_PKA_MON_READ_Msk (0xffffffffUL) /*!< CC312_PKA_MON_READ (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_MON_SELECT_REG ================================================ */ + #define CC312_CC312_PKA_MON_SELECT_REG_CC312_PKA_MON_SELECT_Pos (0UL) /*!< CC312_PKA_MON_SELECT (Bit 0) */ + #define CC312_CC312_PKA_MON_SELECT_REG_CC312_PKA_MON_SELECT_Msk (0xfUL) /*!< CC312_PKA_MON_SELECT (Bitfield-Mask: 0x0f) */ +/* ================================================ CC312_PKA_PIPE_RDY_REG ================================================= */ + #define CC312_CC312_PKA_PIPE_RDY_REG_CC312_PKA_PIPE_RDY_Pos (0UL) /*!< CC312_PKA_PIPE_RDY (Bit 0) */ + #define CC312_CC312_PKA_PIPE_RDY_REG_CC312_PKA_PIPE_RDY_Msk (0x1UL) /*!< CC312_PKA_PIPE_RDY (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_PKA_SRAM_ADDR_REG ================================================ */ + #define CC312_CC312_PKA_SRAM_ADDR_REG_CC312_PKA_SRAM_ADDR_Pos (0UL) /*!< CC312_PKA_SRAM_ADDR (Bit 0) */ + #define CC312_CC312_PKA_SRAM_ADDR_REG_CC312_PKA_SRAM_ADDR_Msk (0xffffffffUL) /*!< CC312_PKA_SRAM_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_SRAM_RADDR_REG ================================================ */ + #define CC312_CC312_PKA_SRAM_RADDR_REG_CC312_PKA_SRAM_RADDR_Pos (0UL) /*!< CC312_PKA_SRAM_RADDR (Bit 0) */ + #define CC312_CC312_PKA_SRAM_RADDR_REG_CC312_PKA_SRAM_RADDR_Msk (0xffffffffUL) /*!< CC312_PKA_SRAM_RADDR (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_SRAM_RDATA_REG ================================================ */ + #define CC312_CC312_PKA_SRAM_RDATA_REG_CC312_PKA_SRAM_RDATA_Pos (0UL) /*!< CC312_PKA_SRAM_RDATA (Bit 0) */ + #define CC312_CC312_PKA_SRAM_RDATA_REG_CC312_PKA_SRAM_RDATA_Msk (0xffffffffUL) /*!< CC312_PKA_SRAM_RDATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_SRAM_WDATA_REG ================================================ */ + #define CC312_CC312_PKA_SRAM_WDATA_REG_CC312_PKA_SRAM_WDATA_Pos (0UL) /*!< CC312_PKA_SRAM_WDATA (Bit 0) */ + #define CC312_CC312_PKA_SRAM_WDATA_REG_CC312_PKA_SRAM_WDATA_Msk (0xffffffffUL) /*!< CC312_PKA_SRAM_WDATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_SRAM_WR_CLR_REG =============================================== */ + #define CC312_CC312_PKA_SRAM_WR_CLR_REG_CC312_PKA_SRAM_WR_CLR_Pos (0UL) /*!< CC312_PKA_SRAM_WR_CLR (Bit 0) */ + #define CC312_CC312_PKA_SRAM_WR_CLR_REG_CC312_PKA_SRAM_WR_CLR_Msk (0xffffffffUL) /*!< CC312_PKA_SRAM_WR_CLR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CC312_PKA_STATUS_REG ================================================== */ + #define CC312_CC312_PKA_STATUS_REG_CC312_LAST_OPCODE_Pos (16UL) /*!< CC312_LAST_OPCODE (Bit 16) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_LAST_OPCODE_Msk (0x1f0000UL) /*!< CC312_LAST_OPCODE (Bitfield-Mask: 0x1f) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_MODINV_OF_ZERO_Pos (15UL) /*!< CC312_MODINV_OF_ZERO (Bit 15) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_MODINV_OF_ZERO_Msk (0x8000UL) /*!< CC312_MODINV_OF_ZERO (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_DIV_BY_ZERO_Pos (14UL) /*!< CC312_DIV_BY_ZERO (Bit 14) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_DIV_BY_ZERO_Msk (0x4000UL) /*!< CC312_DIV_BY_ZERO (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_MODOVRFLW_Pos (13UL) /*!< CC312_ALU_MODOVRFLW (Bit 13) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_MODOVRFLW_Msk (0x2000UL) /*!< CC312_ALU_MODOVRFLW (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_OUT_ZERO_Pos (12UL) /*!< CC312_ALU_OUT_ZERO (Bit 12) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_OUT_ZERO_Msk (0x1000UL) /*!< CC312_ALU_OUT_ZERO (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_SUB_IS_ZERO_Pos (11UL) /*!< CC312_ALU_SUB_IS_ZERO (Bit 11) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_SUB_IS_ZERO_Msk (0x800UL) /*!< CC312_ALU_SUB_IS_ZERO (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_CARRY_MOD_Pos (10UL) /*!< CC312_ALU_CARRY_MOD (Bit 10) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_CARRY_MOD_Msk (0x400UL) /*!< CC312_ALU_CARRY_MOD (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_CARRY_Pos (9UL) /*!< CC312_ALU_CARRY (Bit 9) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_CARRY_Msk (0x200UL) /*!< CC312_ALU_CARRY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_SIGN_OUT_Pos (8UL) /*!< CC312_ALU_SIGN_OUT (Bit 8) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_SIGN_OUT_Msk (0x100UL) /*!< CC312_ALU_SIGN_OUT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_LSB_4BITS_Pos (4UL) /*!< CC312_ALU_LSB_4BITS (Bit 4) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_LSB_4BITS_Msk (0xf0UL) /*!< CC312_ALU_LSB_4BITS (Bitfield-Mask: 0x0f) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_MSB_4BITS_Pos (0UL) /*!< CC312_ALU_MSB_4BITS (Bit 0) */ + #define CC312_CC312_PKA_STATUS_REG_CC312_ALU_MSB_4BITS_Msk (0xfUL) /*!< CC312_ALU_MSB_4BITS (Bitfield-Mask: 0x0f) */ +/* ================================================ CC312_PKA_SW_RESET_REG ================================================= */ + #define CC312_CC312_PKA_SW_RESET_REG_CC312_PKA_SW_RESET_Pos (0UL) /*!< CC312_PKA_SW_RESET (Bit 0) */ + #define CC312_CC312_PKA_SW_RESET_REG_CC312_PKA_SW_RESET_Msk (0x1UL) /*!< CC312_PKA_SW_RESET (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_PKA_VERSION_REG ================================================= */ + #define CC312_CC312_PKA_VERSION_REG_CC312_PKA_VERSION_Pos (0UL) /*!< CC312_PKA_VERSION (Bit 0) */ + #define CC312_CC312_PKA_VERSION_REG_CC312_PKA_VERSION_Msk (0xffffffffUL) /*!< CC312_PKA_VERSION (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_PKA_WORD_ACCESS_REG =============================================== */ + #define CC312_CC312_PKA_WORD_ACCESS_REG_CC312_PKA_WORD_ACCESS_Pos (0UL) /*!< CC312_PKA_WORD_ACCESS (Bit 0) */ + #define CC312_CC312_PKA_WORD_ACCESS_REG_CC312_PKA_WORD_ACCESS_Msk (0xffffffffUL) /*!< CC312_PKA_WORD_ACCESS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_READ_ALIGN_LAST_REG =============================================== */ + #define CC312_CC312_READ_ALIGN_LAST_REG_CC312_READ_ALIGN_LAST_Pos (0UL) /*!< CC312_READ_ALIGN_LAST (Bit 0) */ + #define CC312_CC312_READ_ALIGN_LAST_REG_CC312_READ_ALIGN_LAST_Msk (0x1UL) /*!< CC312_READ_ALIGN_LAST (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_RND_SOURCE_ENABLE_REG ============================================== */ + #define CC312_CC312_RND_SOURCE_ENABLE_REG_CC312_RND_SRC_EN_Pos (0UL) /*!< CC312_RND_SRC_EN (Bit 0) */ + #define CC312_CC312_RND_SOURCE_ENABLE_REG_CC312_RND_SRC_EN_Msk (0x1UL) /*!< CC312_RND_SRC_EN (Bitfield-Mask: 0x01) */ +/* ================================================== CC312_RNG_BUSY_REG =================================================== */ + #define CC312_CC312_RNG_BUSY_REG_CC312_PRNG_BUSY_Pos (2UL) /*!< CC312_PRNG_BUSY (Bit 2) */ + #define CC312_CC312_RNG_BUSY_REG_CC312_PRNG_BUSY_Msk (0x4UL) /*!< CC312_PRNG_BUSY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_BUSY_REG_CC312_TRNG_BUSY_Pos (1UL) /*!< CC312_TRNG_BUSY (Bit 1) */ + #define CC312_CC312_RNG_BUSY_REG_CC312_TRNG_BUSY_Msk (0x2UL) /*!< CC312_TRNG_BUSY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_BUSY_REG_CC312_RNG_BUSY_Pos (0UL) /*!< CC312_RNG_BUSY (Bit 0) */ + #define CC312_CC312_RNG_BUSY_REG_CC312_RNG_BUSY_Msk (0x1UL) /*!< CC312_RNG_BUSY (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_RNG_CLK_ENABLE_REG ================================================ */ + #define CC312_CC312_RNG_CLK_ENABLE_REG_CC312_RNG_CLK_EN_Pos (0UL) /*!< CC312_RNG_CLK_EN (Bit 0) */ + #define CC312_CC312_RNG_CLK_ENABLE_REG_CC312_RNG_CLK_EN_Msk (0x1UL) /*!< CC312_RNG_CLK_EN (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_RNG_DEBUG_EN_INPUT_REG ============================================== */ + #define CC312_CC312_RNG_DEBUG_EN_INPUT_REG_CC312_RNG_DEBUG_EN_Pos (0UL) /*!< CC312_RNG_DEBUG_EN (Bit 0) */ + #define CC312_CC312_RNG_DEBUG_EN_INPUT_REG_CC312_RNG_DEBUG_EN_Msk (0x1UL) /*!< CC312_RNG_DEBUG_EN (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_RNG_DMA_ENABLE_REG ================================================ */ + #define CC312_CC312_RNG_DMA_ENABLE_REG_CC312_RNG_DMA_EN_Pos (0UL) /*!< CC312_RNG_DMA_EN (Bit 0) */ + #define CC312_CC312_RNG_DMA_ENABLE_REG_CC312_RNG_DMA_EN_Msk (0x1UL) /*!< CC312_RNG_DMA_EN (Bitfield-Mask: 0x01) */ +/* ============================================= CC312_RNG_DMA_SAMPLES_NUM_REG ============================================= */ + #define CC312_CC312_RNG_DMA_SAMPLES_NUM_REG_CC312_RNG_SAMPLES_NUM_Pos (0UL) /*!< CC312_RNG_SAMPLES_NUM (Bit 0) */ + #define CC312_CC312_RNG_DMA_SAMPLES_NUM_REG_CC312_RNG_SAMPLES_NUM_Msk (0xffUL) /*!< CC312_RNG_SAMPLES_NUM (Bitfield-Mask: 0xff) */ +/* ============================================== CC312_RNG_DMA_SRAM_ADDR_REG ============================================== */ + #define CC312_CC312_RNG_DMA_SRAM_ADDR_REG_CC312_RNG_SRAM_DMA_ADDR_Pos (0UL) /*!< CC312_RNG_SRAM_DMA_ADDR (Bit 0) */ + #define CC312_CC312_RNG_DMA_SRAM_ADDR_REG_CC312_RNG_SRAM_DMA_ADDR_Msk (0x7ffUL) /*!< CC312_RNG_SRAM_DMA_ADDR (Bitfield-Mask: 0x7ff) */ +/* ============================================== CC312_RNG_DMA_SRC_MASK_REG =============================================== */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL3_Pos (3UL) /*!< CC312_EN_SRC_SEL3 (Bit 3) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL3_Msk (0x8UL) /*!< CC312_EN_SRC_SEL3 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL2_Pos (2UL) /*!< CC312_EN_SRC_SEL2 (Bit 2) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL2_Msk (0x4UL) /*!< CC312_EN_SRC_SEL2 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL1_Pos (1UL) /*!< CC312_EN_SRC_SEL1 (Bit 1) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL1_Msk (0x2UL) /*!< CC312_EN_SRC_SEL1 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL0_Pos (0UL) /*!< CC312_EN_SRC_SEL0 (Bit 0) */ + #define CC312_CC312_RNG_DMA_SRC_MASK_REG_CC312_EN_SRC_SEL0_Msk (0x1UL) /*!< CC312_EN_SRC_SEL0 (Bitfield-Mask: 0x01) */ +/* =============================================== CC312_RNG_DMA_STATUS_REG ================================================ */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_NUM_OF_SAMPLES_Pos (3UL) /*!< CC312_NUM_OF_SAMPLES (Bit 3) */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_NUM_OF_SAMPLES_Msk (0x7f8UL) /*!< CC312_NUM_OF_SAMPLES (Bitfield-Mask: 0xff) */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_DMA_SRC_SEL_Pos (1UL) /*!< CC312_DMA_SRC_SEL (Bit 1) */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_DMA_SRC_SEL_Msk (0x6UL) /*!< CC312_DMA_SRC_SEL (Bitfield-Mask: 0x03) */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_RNG_DMA_BUSY_Pos (0UL) /*!< CC312_RNG_DMA_BUSY (Bit 0) */ + #define CC312_CC312_RNG_DMA_STATUS_REG_CC312_RNG_DMA_BUSY_Msk (0x1UL) /*!< CC312_RNG_DMA_BUSY (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_RNG_ICR_REG =================================================== */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_WHICH_KAT_ERR_Pos (25UL) /*!< CC312_RNG_ICR_WHICH_KAT_ERR (Bit 25) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_WHICH_KAT_ERR_Msk (0x6000000UL) /*!< CC312_RNG_ICR_WHICH_KAT_ERR (Bitfield-Mask: 0x03) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_KAT_ERR_Pos (24UL) /*!< CC312_RNG_ICR_KAT_ERR (Bit 24) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_KAT_ERR_Msk (0x1000000UL) /*!< CC312_RNG_ICR_KAT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_REQ_SIZE_Pos (23UL) /*!< CC312_RNG_ICR_REQ_SIZE (Bit 23) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_REQ_SIZE_Msk (0x800000UL) /*!< CC312_RNG_ICR_REQ_SIZE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_PRNG_CRNGT_ERR_Pos (22UL) /*!< CC312_RNG_ICR_PRNG_CRNGT_ERR (Bit 22) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_PRNG_CRNGT_ERR_Msk (0x400000UL) /*!< CC312_RNG_ICR_PRNG_CRNGT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEED_CNTR_TOP_40_Pos (21UL) /*!< CC312_RNG_ICR_RESEED_CNTR_TOP_40 (Bit 21) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEED_CNTR_TOP_40_Msk (0x200000UL) /*!< CC312_RNG_ICR_RESEED_CNTR_TOP_40 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEED_CNTR_FULL_Pos (20UL) /*!< CC312_RNG_ICR_RESEED_CNTR_FULL (Bit 20) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEED_CNTR_FULL_Msk (0x100000UL) /*!< CC312_RNG_ICR_RESEED_CNTR_FULL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_OUTPUT_READY_Pos (19UL) /*!< CC312_RNG_ICR_OUTPUT_READY (Bit 19) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_OUTPUT_READY_Msk (0x80000UL) /*!< CC312_RNG_ICR_OUTPUT_READY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_FINAL_UPDATE_DONE_Pos (18UL) /*!< CC312_RNG_ICR_FINAL_UPDATE_DONE (Bit 18) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_FINAL_UPDATE_DONE_Msk (0x40000UL) /*!< CC312_RNG_ICR_FINAL_UPDATE_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_INSTANTIATION_DONE_Pos (17UL) /*!< CC312_RNG_ICR_INSTANTIATION_DONE (Bit 17) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_INSTANTIATION_DONE_Msk (0x20000UL) /*!< CC312_RNG_ICR_INSTANTIATION_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEEDING_DONE_Pos (16UL) /*!< CC312_RNG_ICR_RESEEDING_DONE (Bit 16) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RESEEDING_DONE_Msk (0x10000UL) /*!< CC312_RNG_ICR_RESEEDING_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RNG_DMA_DONE_Pos (5UL) /*!< CC312_RNG_ICR_RNG_DMA_DONE (Bit 5) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RNG_DMA_DONE_Msk (0x20UL) /*!< CC312_RNG_ICR_RNG_DMA_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RNG_WATCHDOG_Pos (4UL) /*!< CC312_RNG_ICR_RNG_WATCHDOG (Bit 4) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_RNG_WATCHDOG_Msk (0x10UL) /*!< CC312_RNG_ICR_RNG_WATCHDOG (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_VN_ERR_Pos (3UL) /*!< CC312_RNG_ICR_VN_ERR (Bit 3) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_VN_ERR_Msk (0x8UL) /*!< CC312_RNG_ICR_VN_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_CRNGT_ERR_Pos (2UL) /*!< CC312_RNG_ICR_CRNGT_ERR (Bit 2) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_CRNGT_ERR_Msk (0x4UL) /*!< CC312_RNG_ICR_CRNGT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_AUTOCORR_ERR_Pos (1UL) /*!< CC312_RNG_ICR_AUTOCORR_ERR (Bit 1) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_AUTOCORR_ERR_Msk (0x2UL) /*!< CC312_RNG_ICR_AUTOCORR_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_EHR_VALID_Pos (0UL) /*!< CC312_RNG_ICR_EHR_VALID (Bit 0) */ + #define CC312_CC312_RNG_ICR_REG_CC312_RNG_ICR_EHR_VALID_Msk (0x1UL) /*!< CC312_RNG_ICR_EHR_VALID (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_RNG_IMR_REG =================================================== */ + #define CC312_CC312_RNG_IMR_REG_CC312_RNG_DMA_DONE_INT_Pos (5UL) /*!< CC312_RNG_DMA_DONE_INT (Bit 5) */ + #define CC312_CC312_RNG_IMR_REG_CC312_RNG_DMA_DONE_INT_Msk (0x20UL) /*!< CC312_RNG_DMA_DONE_INT (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_IMR_REG_CC312_WATCHDOG_INT_MASK_Pos (4UL) /*!< CC312_WATCHDOG_INT_MASK (Bit 4) */ + #define CC312_CC312_RNG_IMR_REG_CC312_WATCHDOG_INT_MASK_Msk (0x10UL) /*!< CC312_WATCHDOG_INT_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_IMR_REG_CC312_VN_ERR_INT_MASK_Pos (3UL) /*!< CC312_VN_ERR_INT_MASK (Bit 3) */ + #define CC312_CC312_RNG_IMR_REG_CC312_VN_ERR_INT_MASK_Msk (0x8UL) /*!< CC312_VN_ERR_INT_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_IMR_REG_CC312_CRNGT_ERR_INT_MASK_Pos (2UL) /*!< CC312_CRNGT_ERR_INT_MASK (Bit 2) */ + #define CC312_CC312_RNG_IMR_REG_CC312_CRNGT_ERR_INT_MASK_Msk (0x4UL) /*!< CC312_CRNGT_ERR_INT_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_IMR_REG_CC312_AUTOCORR_ERR_INT_MASK_Pos (1UL) /*!< CC312_AUTOCORR_ERR_INT_MASK (Bit 1) */ + #define CC312_CC312_RNG_IMR_REG_CC312_AUTOCORR_ERR_INT_MASK_Msk (0x2UL) /*!< CC312_AUTOCORR_ERR_INT_MASK (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_IMR_REG_CC312_EHR_VALID_INT_MASK_Pos (0UL) /*!< CC312_EHR_VALID_INT_MASK (Bit 0) */ + #define CC312_CC312_RNG_IMR_REG_CC312_EHR_VALID_INT_MASK_Msk (0x1UL) /*!< CC312_EHR_VALID_INT_MASK (Bitfield-Mask: 0x01) */ +/* =================================================== CC312_RNG_ISR_REG =================================================== */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_WHICH_KAT_ERR_Pos (25UL) /*!< CC312_RNG_ISR_WHICH_KAT_ERR (Bit 25) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_WHICH_KAT_ERR_Msk (0x6000000UL) /*!< CC312_RNG_ISR_WHICH_KAT_ERR (Bitfield-Mask: 0x03) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_KAT_ERR_Pos (24UL) /*!< CC312_RNG_ISR_KAT_ERR (Bit 24) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_KAT_ERR_Msk (0x1000000UL) /*!< CC312_RNG_ISR_KAT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_REQ_SIZE_Pos (23UL) /*!< CC312_RNG_ISR_REQ_SIZE (Bit 23) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_REQ_SIZE_Msk (0x800000UL) /*!< CC312_RNG_ISR_REQ_SIZE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_PRNG_CRNGT_ERR_Pos (22UL) /*!< CC312_RNG_ISR_PRNG_CRNGT_ERR (Bit 22) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_PRNG_CRNGT_ERR_Msk (0x400000UL) /*!< CC312_RNG_ISR_PRNG_CRNGT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEED_CNTR_TOP_40_Pos (21UL) /*!< CC312_RNG_ISR_RESEED_CNTR_TOP_40 (Bit 21) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEED_CNTR_TOP_40_Msk (0x200000UL) /*!< CC312_RNG_ISR_RESEED_CNTR_TOP_40 (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEED_CNTR_FULL_Pos (20UL) /*!< CC312_RNG_ISR_RESEED_CNTR_FULL (Bit 20) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEED_CNTR_FULL_Msk (0x100000UL) /*!< CC312_RNG_ISR_RESEED_CNTR_FULL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_OUTPUT_READY_Pos (19UL) /*!< CC312_RNG_ISR_OUTPUT_READY (Bit 19) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_OUTPUT_READY_Msk (0x80000UL) /*!< CC312_RNG_ISR_OUTPUT_READY (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_FINAL_UPDATE_DONE_Pos (18UL) /*!< CC312_RNG_ISR_FINAL_UPDATE_DONE (Bit 18) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_FINAL_UPDATE_DONE_Msk (0x40000UL) /*!< CC312_RNG_ISR_FINAL_UPDATE_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_INSTANTIATION_DONE_Pos (17UL) /*!< CC312_RNG_ISR_INSTANTIATION_DONE (Bit 17) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_INSTANTIATION_DONE_Msk (0x20000UL) /*!< CC312_RNG_ISR_INSTANTIATION_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEEDING_DONE_Pos (16UL) /*!< CC312_RNG_ISR_RESEEDING_DONE (Bit 16) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_RESEEDING_DONE_Msk (0x10000UL) /*!< CC312_RNG_ISR_RESEEDING_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_DMA_DONE_Pos (5UL) /*!< CC312_RNG_ISR_DMA_DONE (Bit 5) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_DMA_DONE_Msk (0x20UL) /*!< CC312_RNG_ISR_DMA_DONE (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_VN_ERR_Pos (3UL) /*!< CC312_RNG_ISR_VN_ERR (Bit 3) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_VN_ERR_Msk (0x8UL) /*!< CC312_RNG_ISR_VN_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_CRNGT_ERR_Pos (2UL) /*!< CC312_RNG_ISR_CRNGT_ERR (Bit 2) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_CRNGT_ERR_Msk (0x4UL) /*!< CC312_RNG_ISR_CRNGT_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_AUTOCORR_ERR_Pos (1UL) /*!< CC312_RNG_ISR_AUTOCORR_ERR (Bit 1) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_AUTOCORR_ERR_Msk (0x2UL) /*!< CC312_RNG_ISR_AUTOCORR_ERR (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_EHR_VALID_Pos (0UL) /*!< CC312_RNG_ISR_EHR_VALID (Bit 0) */ + #define CC312_CC312_RNG_ISR_REG_CC312_RNG_ISR_EHR_VALID_Msk (0x1UL) /*!< CC312_RNG_ISR_EHR_VALID (Bitfield-Mask: 0x01) */ +/* ================================================ CC312_RNG_SW_RESET_REG ================================================= */ + #define CC312_CC312_RNG_SW_RESET_REG_CC312_RNG_SW_RESET_Pos (0UL) /*!< CC312_RNG_SW_RESET (Bit 0) */ + #define CC312_CC312_RNG_SW_RESET_REG_CC312_RNG_SW_RESET_Msk (0x1UL) /*!< CC312_RNG_SW_RESET (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_RNG_VERSION_REG ================================================= */ + #define CC312_CC312_RNG_VERSION_REG_CC312_RNG_USE_5_SBOXES_Pos (7UL) /*!< CC312_RNG_USE_5_SBOXES (Bit 7) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_RNG_USE_5_SBOXES_Msk (0x80UL) /*!< CC312_RNG_USE_5_SBOXES (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_RESEEDING_EXISTS_Pos (6UL) /*!< CC312_RESEEDING_EXISTS (Bit 6) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_RESEEDING_EXISTS_Msk (0x40UL) /*!< CC312_RESEEDING_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_KAT_EXISTS_Pos (5UL) /*!< CC312_KAT_EXISTS (Bit 5) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_KAT_EXISTS_Msk (0x20UL) /*!< CC312_KAT_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_PRNG_EXISTS_Pos (4UL) /*!< CC312_PRNG_EXISTS (Bit 4) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_PRNG_EXISTS_Msk (0x10UL) /*!< CC312_PRNG_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_TRNG_TESTS_BYPASS_EN_Pos (3UL) /*!< CC312_TRNG_TESTS_BYPASS_EN (Bit 3) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_TRNG_TESTS_BYPASS_EN_Msk (0x8UL) /*!< CC312_TRNG_TESTS_BYPASS_EN (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_AUTOCORR_EXISTS_Pos (2UL) /*!< CC312_AUTOCORR_EXISTS (Bit 2) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_AUTOCORR_EXISTS_Msk (0x4UL) /*!< CC312_AUTOCORR_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_CRNGT_EXISTS_Pos (1UL) /*!< CC312_CRNGT_EXISTS (Bit 1) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_CRNGT_EXISTS_Msk (0x2UL) /*!< CC312_CRNGT_EXISTS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_EHR_WIDTH_192_Pos (0UL) /*!< CC312_EHR_WIDTH_192 (Bit 0) */ + #define CC312_CC312_RNG_VERSION_REG_CC312_EHR_WIDTH_192_Msk (0x1UL) /*!< CC312_EHR_WIDTH_192 (Bitfield-Mask: 0x01) */ +/* ============================================== CC312_RNG_WATCHDOG_VAL_REG =============================================== */ + #define CC312_CC312_RNG_WATCHDOG_VAL_REG_CC312_RNG_WATCHDOG_VAL_Pos (0UL) /*!< CC312_RNG_WATCHDOG_VAL (Bit 0) */ + #define CC312_CC312_RNG_WATCHDOG_VAL_REG_CC312_RNG_WATCHDOG_VAL_Msk (0xffffffffUL) /*!< CC312_RNG_WATCHDOG_VAL (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CC312_RST_BITS_COUNTER_REG =============================================== */ + #define CC312_CC312_RST_BITS_COUNTER_REG_CC312_RST_BITS_COUNTER_Pos (0UL) /*!< CC312_RST_BITS_COUNTER (Bit 0) */ + #define CC312_CC312_RST_BITS_COUNTER_REG_CC312_RST_BITS_COUNTER_Msk (0x1UL) /*!< CC312_RST_BITS_COUNTER (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_SAMPLE_CNT1_REG ================================================= */ + #define CC312_CC312_SAMPLE_CNT1_REG_CC312_SAMPLE_CNTR1_Pos (0UL) /*!< CC312_SAMPLE_CNTR1 (Bit 0) */ + #define CC312_CC312_SAMPLE_CNT1_REG_CC312_SAMPLE_CNTR1_Msk (0xffffffffUL) /*!< CC312_SAMPLE_CNTR1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CC312_SRAM_ADDR_REG ================================================== */ + #define CC312_CC312_SRAM_ADDR_REG_CC312_SRAM_ADDR_Pos (0UL) /*!< CC312_SRAM_ADDR (Bit 0) */ + #define CC312_CC312_SRAM_ADDR_REG_CC312_SRAM_ADDR_Msk (0x7fffUL) /*!< CC312_SRAM_ADDR (Bitfield-Mask: 0x7fff) */ +/* =============================================== CC312_SRAM_DATA_READY_REG =============================================== */ + #define CC312_CC312_SRAM_DATA_READY_REG_CC312_SRAM_READY_Pos (0UL) /*!< CC312_SRAM_READY (Bit 0) */ + #define CC312_CC312_SRAM_DATA_READY_REG_CC312_SRAM_READY_Msk (0x1UL) /*!< CC312_SRAM_READY (Bitfield-Mask: 0x01) */ +/* ================================================== CC312_SRAM_DATA_REG ================================================== */ + #define CC312_CC312_SRAM_DATA_REG_CC312_SRAM_DATA_Pos (0UL) /*!< CC312_SRAM_DATA (Bit 0) */ + #define CC312_CC312_SRAM_DATA_REG_CC312_SRAM_DATA_Msk (0xffffffffUL) /*!< CC312_SRAM_DATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CC312_SRAM_DEST_ADDR_REG ================================================ */ + #define CC312_CC312_SRAM_DEST_ADDR_REG_CC312_SRAM_DEST_Pos (0UL) /*!< CC312_SRAM_DEST (Bit 0) */ + #define CC312_CC312_SRAM_DEST_ADDR_REG_CC312_SRAM_DEST_Msk (0xffffffffUL) /*!< CC312_SRAM_DEST (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_SRAM_SRC_ADDR_REG ================================================ */ + #define CC312_CC312_SRAM_SRC_ADDR_REG_CC312_SRAM_SRC_ADDR_Pos (0UL) /*!< CC312_SRAM_SRC_ADDR (Bit 0) */ + #define CC312_CC312_SRAM_SRC_ADDR_REG_CC312_SRAM_SRC_ADDR_Msk (0xffffffffUL) /*!< CC312_SRAM_SRC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_SRC_LLI_WORD0_REG ================================================ */ + #define CC312_CC312_SRC_LLI_WORD0_REG_CC312_SRC_LLI_WORD0_Pos (0UL) /*!< CC312_SRC_LLI_WORD0 (Bit 0) */ + #define CC312_CC312_SRC_LLI_WORD0_REG_CC312_SRC_LLI_WORD0_Msk (0xffffffffUL) /*!< CC312_SRC_LLI_WORD0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ CC312_SRC_LLI_WORD1_REG ================================================ */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_LAST_Pos (31UL) /*!< CC312_SRC_LLI_LAST (Bit 31) */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_LAST_Msk (0x80000000UL) /*!< CC312_SRC_LLI_LAST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_FIRST_Pos (30UL) /*!< CC312_SRC_LLI_FIRST (Bit 30) */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_FIRST_Msk (0x40000000UL) /*!< CC312_SRC_LLI_FIRST (Bitfield-Mask: 0x01) */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_BYTES_NUM_Pos (0UL) /*!< CC312_SRC_LLI_BYTES_NUM (Bit 0) */ + #define CC312_CC312_SRC_LLI_WORD1_REG_CC312_SRC_LLI_BYTES_NUM_Msk (0x3fffffffUL) /*!< CC312_SRC_LLI_BYTES_NUM (Bitfield-Mask: 0x3fffffff) */ +/* ================================================= CC312_TRNG_CONFIG_REG ================================================= */ + #define CC312_CC312_TRNG_CONFIG_REG_CC312_SOP_SEL_Pos (2UL) /*!< CC312_SOP_SEL (Bit 2) */ + #define CC312_CC312_TRNG_CONFIG_REG_CC312_SOP_SEL_Msk (0x4UL) /*!< CC312_SOP_SEL (Bitfield-Mask: 0x01) */ + #define CC312_CC312_TRNG_CONFIG_REG_CC312_RND_SRC_SEL_Pos (0UL) /*!< CC312_RND_SRC_SEL (Bit 0) */ + #define CC312_CC312_TRNG_CONFIG_REG_CC312_RND_SRC_SEL_Msk (0x3UL) /*!< CC312_RND_SRC_SEL (Bitfield-Mask: 0x03) */ +/* ============================================= CC312_TRNG_DEBUG_CONTROL_REG ============================================== */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_AUTO_CORRELATE_BYPASS_Pos (3UL) /*!< CC312_AUTO_CORRELATE_BYPASS (Bit 3) */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_AUTO_CORRELATE_BYPASS_Msk (0x8UL) /*!< CC312_AUTO_CORRELATE_BYPASS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_TRNG_CRNGT_BYPASS_Pos (2UL) /*!< CC312_TRNG_CRNGT_BYPASS (Bit 2) */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_TRNG_CRNGT_BYPASS_Msk (0x4UL) /*!< CC312_TRNG_CRNGT_BYPASS (Bitfield-Mask: 0x01) */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_VNC_BYPASS_Pos (1UL) /*!< CC312_VNC_BYPASS (Bit 1) */ + #define CC312_CC312_TRNG_DEBUG_CONTROL_REG_CC312_VNC_BYPASS_Msk (0x2UL) /*!< CC312_VNC_BYPASS (Bitfield-Mask: 0x01) */ +/* ================================================= CC312_TRNG_VALID_REG ================================================== */ + #define CC312_CC312_TRNG_VALID_REG_CC312_TRNG_EHR_VALID_Pos (0UL) /*!< CC312_TRNG_EHR_VALID (Bit 0) */ + #define CC312_CC312_TRNG_VALID_REG_CC312_TRNG_EHR_VALID_Msk (0x1UL) /*!< CC312_TRNG_EHR_VALID (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CHIP_VERSION ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CHIP_ID1_REG ====================================================== */ + #define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL) /*!< CHIP_ID1 (Bit 0) */ + #define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL) /*!< CHIP_ID1 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID2_REG ====================================================== */ + #define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL) /*!< CHIP_ID2 (Bit 0) */ + #define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL) /*!< CHIP_ID2 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID3_REG ====================================================== */ + #define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL) /*!< CHIP_ID3 (Bit 0) */ + #define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL) /*!< CHIP_ID3 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID4_REG ====================================================== */ + #define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL) /*!< CHIP_ID4 (Bit 0) */ + #define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL) /*!< CHIP_ID4 (Bitfield-Mask: 0xff) */ +/* =================================================== CHIP_REVISION_REG =================================================== */ + #define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL) /*!< CHIP_REVISION (Bit 0) */ + #define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL) /*!< CHIP_REVISION (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_SWC_REG ====================================================== */ + #define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL) /*!< CHIP_SWC (Bit 0) */ + #define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL) /*!< CHIP_SWC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CHIP_TEST1_REG ===================================================== */ + #define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL) /*!< CHIP_LAYOUT_REVISION (Bit 0) */ + #define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL) /*!< CHIP_LAYOUT_REVISION (Bitfield-Mask: 0xff) */ +/* ==================================================== CHIP_TEST2_REG ===================================================== */ + #define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL) /*!< CHIP_METAL_OPTION (Bit 0) */ + #define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL) /*!< CHIP_METAL_OPTION (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CLKCAL_BIF ================ */ +/* =========================================================================================================================== */ + +/* ============================================== ADC_DIG_CAL_WEIGHT_I_0_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_0_REG_adc_dig_cal_weight_i_0_Pos (0UL) /*!< adc_dig_cal_weight_i_0 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_0_REG_adc_dig_cal_weight_i_0_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_1_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_1_REG_adc_dig_cal_weight_i_1_Pos (0UL) /*!< adc_dig_cal_weight_i_1 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_1_REG_adc_dig_cal_weight_i_1_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_2_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_2_REG_adc_dig_cal_weight_i_2_Pos (0UL) /*!< adc_dig_cal_weight_i_2 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_2_REG_adc_dig_cal_weight_i_2_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_3_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_3_REG_adc_dig_cal_weight_i_3_Pos (0UL) /*!< adc_dig_cal_weight_i_3 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_3_REG_adc_dig_cal_weight_i_3_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_4_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_4_REG_adc_dig_cal_weight_i_4_Pos (0UL) /*!< adc_dig_cal_weight_i_4 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_4_REG_adc_dig_cal_weight_i_4_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_4 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_5_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_5_REG_adc_dig_cal_weight_i_5_Pos (0UL) /*!< adc_dig_cal_weight_i_5 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_5_REG_adc_dig_cal_weight_i_5_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_5 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_6_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_6_REG_adc_dig_cal_weight_i_6_Pos (0UL) /*!< adc_dig_cal_weight_i_6 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_6_REG_adc_dig_cal_weight_i_6_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_6 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_7_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_7_REG_adc_dig_cal_weight_i_7_Pos (0UL) /*!< adc_dig_cal_weight_i_7 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_7_REG_adc_dig_cal_weight_i_7_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_7 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_8_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_8_REG_adc_dig_cal_weight_i_8_Pos (0UL) /*!< adc_dig_cal_weight_i_8 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_8_REG_adc_dig_cal_weight_i_8_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_i_8 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_9_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_9_REG_adc_dig_cal_weight_i_9_Pos (0UL) /*!< adc_dig_cal_weight_i_9 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_I_9_REG_adc_dig_cal_weight_i_9_Msk (0x7ffffffUL) /*!< adc_dig_cal_weight_i_9 (Bitfield-Mask: 0x7ffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_0_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_0_REG_adc_dig_cal_weight_q_0_Pos (0UL) /*!< adc_dig_cal_weight_q_0 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_0_REG_adc_dig_cal_weight_q_0_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_1_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_1_REG_adc_dig_cal_weight_q_1_Pos (0UL) /*!< adc_dig_cal_weight_q_1 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_1_REG_adc_dig_cal_weight_q_1_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_2_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_2_REG_adc_dig_cal_weight_q_2_Pos (0UL) /*!< adc_dig_cal_weight_q_2 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_2_REG_adc_dig_cal_weight_q_2_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_3_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_3_REG_adc_dig_cal_weight_q_3_Pos (0UL) /*!< adc_dig_cal_weight_q_3 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_3_REG_adc_dig_cal_weight_q_3_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_4_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_4_REG_adc_dig_cal_weight_q_4_Pos (0UL) /*!< adc_dig_cal_weight_q_4 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_4_REG_adc_dig_cal_weight_q_4_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_4 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_5_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_5_REG_adc_dig_cal_weight_q_5_Pos (0UL) /*!< adc_dig_cal_weight_q_5 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_5_REG_adc_dig_cal_weight_q_5_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_5 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_6_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_6_REG_adc_dig_cal_weight_q_6_Pos (0UL) /*!< adc_dig_cal_weight_q_6 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_6_REG_adc_dig_cal_weight_q_6_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_6 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_7_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_7_REG_adc_dig_cal_weight_q_7_Pos (0UL) /*!< adc_dig_cal_weight_q_7 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_7_REG_adc_dig_cal_weight_q_7_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_7 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_8_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_8_REG_adc_dig_cal_weight_q_8_Pos (0UL) /*!< adc_dig_cal_weight_q_8 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_8_REG_adc_dig_cal_weight_q_8_Msk (0xffffffffUL) /*!< adc_dig_cal_weight_q_8 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_9_REG =============================================== */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_9_REG_adc_dig_cal_weight_q_9_Pos (0UL) /*!< adc_dig_cal_weight_q_9 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_CAL_WEIGHT_Q_9_REG_adc_dig_cal_weight_q_9_Msk (0x7ffffffUL) /*!< adc_dig_cal_weight_q_9 (Bitfield-Mask: 0x7ffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_0_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_0_REG_adc_dig_o_caled_weight_i_0_Pos (0UL) /*!< adc_dig_o_caled_weight_i_0 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_0_REG_adc_dig_o_caled_weight_i_0_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_1_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_1_REG_adc_dig_o_caled_weight_i_1_Pos (0UL) /*!< adc_dig_o_caled_weight_i_1 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_1_REG_adc_dig_o_caled_weight_i_1_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_2_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_2_REG_adc_dig_o_caled_weight_i_2_Pos (0UL) /*!< adc_dig_o_caled_weight_i_2 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_2_REG_adc_dig_o_caled_weight_i_2_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_3_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_3_REG_adc_dig_o_caled_weight_i_3_Pos (0UL) /*!< adc_dig_o_caled_weight_i_3 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_3_REG_adc_dig_o_caled_weight_i_3_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_4_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_4_REG_adc_dig_o_caled_weight_i_4_Pos (0UL) /*!< adc_dig_o_caled_weight_i_4 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_4_REG_adc_dig_o_caled_weight_i_4_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_4 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_5_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_5_REG_adc_dig_o_caled_weight_i_5_Pos (0UL) /*!< adc_dig_o_caled_weight_i_5 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_5_REG_adc_dig_o_caled_weight_i_5_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_5 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_6_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_6_REG_adc_dig_o_caled_weight_i_6_Pos (0UL) /*!< adc_dig_o_caled_weight_i_6 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_6_REG_adc_dig_o_caled_weight_i_6_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_6 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_7_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_7_REG_adc_dig_o_caled_weight_i_7_Pos (0UL) /*!< adc_dig_o_caled_weight_i_7 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_7_REG_adc_dig_o_caled_weight_i_7_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_7 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_8_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_8_REG_adc_dig_o_caled_weight_i_8_Pos (0UL) /*!< adc_dig_o_caled_weight_i_8 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_8_REG_adc_dig_o_caled_weight_i_8_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_i_8 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_9_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_9_REG_adc_dig_o_caled_weight_i_9_Pos (0UL) /*!< adc_dig_o_caled_weight_i_9 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_I_9_REG_adc_dig_o_caled_weight_i_9_Msk (0x7ffffffUL) /*!< adc_dig_o_caled_weight_i_9 (Bitfield-Mask: 0x7ffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_0_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_0_REG_adc_dig_o_caled_weight_q_0_Pos (0UL) /*!< adc_dig_o_caled_weight_q_0 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_0_REG_adc_dig_o_caled_weight_q_0_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_0 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_1_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_1_REG_adc_dig_o_caled_weight_q_1_Pos (0UL) /*!< adc_dig_o_caled_weight_q_1 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_1_REG_adc_dig_o_caled_weight_q_1_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_1 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_2_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_2_REG_adc_dig_o_caled_weight_q_2_Pos (0UL) /*!< adc_dig_o_caled_weight_q_2 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_2_REG_adc_dig_o_caled_weight_q_2_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_3_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_3_REG_adc_dig_o_caled_weight_q_3_Pos (0UL) /*!< adc_dig_o_caled_weight_q_3 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_3_REG_adc_dig_o_caled_weight_q_3_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_3 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_4_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_4_REG_adc_dig_o_caled_weight_q_4_Pos (0UL) /*!< adc_dig_o_caled_weight_q_4 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_4_REG_adc_dig_o_caled_weight_q_4_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_4 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_5_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_5_REG_adc_dig_o_caled_weight_q_5_Pos (0UL) /*!< adc_dig_o_caled_weight_q_5 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_5_REG_adc_dig_o_caled_weight_q_5_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_5 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_6_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_6_REG_adc_dig_o_caled_weight_q_6_Pos (0UL) /*!< adc_dig_o_caled_weight_q_6 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_6_REG_adc_dig_o_caled_weight_q_6_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_6 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_7_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_7_REG_adc_dig_o_caled_weight_q_7_Pos (0UL) /*!< adc_dig_o_caled_weight_q_7 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_7_REG_adc_dig_o_caled_weight_q_7_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_7 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_8_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_8_REG_adc_dig_o_caled_weight_q_8_Pos (0UL) /*!< adc_dig_o_caled_weight_q_8 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_8_REG_adc_dig_o_caled_weight_q_8_Msk (0xffffffffUL) /*!< adc_dig_o_caled_weight_q_8 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_9_REG ============================================= */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_9_REG_adc_dig_o_caled_weight_q_9_Pos (0UL) /*!< adc_dig_o_caled_weight_q_9 (Bit 0) */ + #define CLKCAL_BIF_ADC_DIG_O_CALED_WEIGHT_Q_9_REG_adc_dig_o_caled_weight_q_9_Msk (0x7ffffffUL) /*!< adc_dig_o_caled_weight_q_9 (Bitfield-Mask: 0x7ffffff) */ +/* ==================================================== CLK_CAL_IRQ_REG ==================================================== */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos (2UL) /*!< CLK_CAL_IRQ_CLR (Bit 2) */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk (0x4UL) /*!< CLK_CAL_IRQ_CLR (Bitfield-Mask: 0x01) */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos (1UL) /*!< CLK_CAL_IRQ_STATUS (Bit 1) */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk (0x2UL) /*!< CLK_CAL_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos (0UL) /*!< CLK_CAL_IRQ_EN (Bit 0) */ + #define CLKCAL_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk (0x1UL) /*!< CLK_CAL_IRQ_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_REF_CNT_REG ==================================================== */ + #define CLKCAL_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL) /*!< REF_CNT_VAL (Bit 0) */ + #define CLKCAL_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL) /*!< REF_CNT_VAL (Bitfield-Mask: 0xffff) */ +/* ==================================================== CLK_REF_SEL_REG ==================================================== */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL) /*!< CAL_CLK_SEL (Bit 5) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL) /*!< CAL_CLK_SEL (Bitfield-Mask: 0x07) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL) /*!< EXT_CNT_EN_SEL (Bit 4) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL) /*!< EXT_CNT_EN_SEL (Bitfield-Mask: 0x01) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL) /*!< REF_CAL_START (Bit 3) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL) /*!< REF_CAL_START (Bitfield-Mask: 0x01) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL) /*!< REF_CLK_SEL (Bit 0) */ + #define CLKCAL_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL) /*!< REF_CLK_SEL (Bitfield-Mask: 0x07) */ +/* ==================================================== CLK_REF_VAL_REG ==================================================== */ + #define CLKCAL_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL) /*!< XTAL_CNT_VAL (Bit 0) */ + #define CLKCAL_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL) /*!< XTAL_CNT_VAL (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CRG_APU ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== APU_AUD_CLK_REG ==================================================== */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_PCLK_DIV_Pos (8UL) /*!< AUD_PCLK_DIV (Bit 8) */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_PCLK_DIV_Msk (0xf00UL) /*!< AUD_PCLK_DIV (Bitfield-Mask: 0x0f) */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_CLK_EN_Pos (4UL) /*!< AUD_CLK_EN (Bit 4) */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_CLK_EN_Msk (0x10UL) /*!< AUD_CLK_EN (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_CLK_DIV_Pos (0UL) /*!< AUD_CLK_DIV (Bit 0) */ + #define CRG_APU_APU_AUD_CLK_REG_AUD_CLK_DIV_Msk (0xfUL) /*!< AUD_CLK_DIV (Bitfield-Mask: 0x0f) */ +/* =================================================== APU_MCLK_CTRL_REG =================================================== */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_INV_Pos (9UL) /*!< MCLK_INV (Bit 9) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_INV_Msk (0x200UL) /*!< MCLK_INV (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_SEL_Pos (8UL) /*!< MCLK_SEL (Bit 8) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_SEL_Msk (0x100UL) /*!< MCLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_EN_Pos (7UL) /*!< MCLK_EN (Bit 7) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_EN_Msk (0x80UL) /*!< MCLK_EN (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_DIV_Pos (0UL) /*!< MCLK_DIV (Bit 0) */ + #define CRG_APU_APU_MCLK_CTRL_REG_MCLK_DIV_Msk (0x7fUL) /*!< MCLK_DIV (Bitfield-Mask: 0x7f) */ +/* ==================================================== APU_SRC_CLK_REG ==================================================== */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_CLK_EN_Pos (7UL) /*!< SRC_CLK_EN (Bit 7) */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_CLK_EN_Msk (0x80UL) /*!< SRC_CLK_EN (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_DMIC_CLK_EN_Pos (4UL) /*!< SRC_DMIC_CLK_EN (Bit 4) */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_DMIC_CLK_EN_Msk (0x10UL) /*!< SRC_DMIC_CLK_EN (Bitfield-Mask: 0x01) */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_CLK_DIV_Pos (0UL) /*!< SRC_CLK_DIV (Bit 0) */ + #define CRG_APU_APU_SRC_CLK_REG_SRC_CLK_DIV_Msk (0xfUL) /*!< SRC_CLK_DIV (Bitfield-Mask: 0x0f) */ +/* ================================================== APU_START_CTRL_REG =================================================== */ + #define CRG_APU_APU_START_CTRL_REG_APU_START_Pos (8UL) /*!< APU_START (Bit 8) */ + #define CRG_APU_APU_START_CTRL_REG_APU_START_Msk (0x100UL) /*!< APU_START (Bitfield-Mask: 0x01) */ +/* =================================================== AUD_CLK_GATE_REG ==================================================== */ + #define CRG_APU_AUD_CLK_GATE_REG_APU_RST_Pos (5UL) /*!< APU_RST (Bit 5) */ + #define CRG_APU_AUD_CLK_GATE_REG_APU_RST_Msk (0x20UL) /*!< APU_RST (Bitfield-Mask: 0x01) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_OVR_Pos (4UL) /*!< AUD_CLK_GATE_OVR (Bit 4) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_OVR_Msk (0x10UL) /*!< AUD_CLK_GATE_OVR (Bitfield-Mask: 0x01) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_STAT_Pos (3UL) /*!< AUD_CLK_GATE_STAT (Bit 3) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_STAT_Msk (0x8UL) /*!< AUD_CLK_GATE_STAT (Bitfield-Mask: 0x01) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_SEL_Pos (2UL) /*!< AUD_CLK_GATE_SEL (Bit 2) */ + #define CRG_APU_AUD_CLK_GATE_REG_AUD_CLK_GATE_SEL_Msk (0x4UL) /*!< AUD_CLK_GATE_SEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CRG_COM ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== DAC_10B_CFG_REG ==================================================== */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_DRVSEL_Pos (4UL) /*!< DAC_DRVSEL (Bit 4) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_DRVSEL_Msk (0x10UL) /*!< DAC_DRVSEL (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_PRBSEN_Pos (3UL) /*!< DAC_PRBSEN (Bit 3) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_PRBSEN_Msk (0x8UL) /*!< DAC_PRBSEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_SUSPEND_Pos (2UL) /*!< DAC_SUSPEND (Bit 2) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_SUSPEND_Msk (0x4UL) /*!< DAC_SUSPEND (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_RESET_Pos (1UL) /*!< DAC_RESET (Bit 1) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_RESET_Msk (0x2UL) /*!< DAC_RESET (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_PD_Pos (0UL) /*!< DAC_PD (Bit 0) */ + #define CRG_COM_DAC_10B_CFG_REG_DAC_PD_Msk (0x1UL) /*!< DAC_PD (Bitfield-Mask: 0x01) */ +/* ===================================================== DAC_CTRL_REG ====================================================== */ + #define CRG_COM_DAC_CTRL_REG_DAC_IN_SEL_Q_Pos (2UL) /*!< DAC_IN_SEL_Q (Bit 2) */ + #define CRG_COM_DAC_CTRL_REG_DAC_IN_SEL_Q_Msk (0x4UL) /*!< DAC_IN_SEL_Q (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_CTRL_REG_DAC_IN_SEL_I_Pos (1UL) /*!< DAC_IN_SEL_I (Bit 1) */ + #define CRG_COM_DAC_CTRL_REG_DAC_IN_SEL_I_Msk (0x2UL) /*!< DAC_IN_SEL_I (Bitfield-Mask: 0x01) */ + #define CRG_COM_DAC_CTRL_REG_DAC_EN_Pos (0UL) /*!< DAC_EN (Bit 0) */ + #define CRG_COM_DAC_CTRL_REG_DAC_EN_Msk (0x1UL) /*!< DAC_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== DAC_FREQ_I_REG ===================================================== */ + #define CRG_COM_DAC_FREQ_I_REG_DAC_FREQ_I_Pos (0UL) /*!< DAC_FREQ_I (Bit 0) */ + #define CRG_COM_DAC_FREQ_I_REG_DAC_FREQ_I_Msk (0x7ffUL) /*!< DAC_FREQ_I (Bitfield-Mask: 0x7ff) */ +/* ==================================================== DAC_FREQ_Q_REG ===================================================== */ + #define CRG_COM_DAC_FREQ_Q_REG_DAC_FREQ_Q_Pos (0UL) /*!< DAC_FREQ_Q (Bit 0) */ + #define CRG_COM_DAC_FREQ_Q_REG_DAC_FREQ_Q_Msk (0x7ffUL) /*!< DAC_FREQ_Q (Bitfield-Mask: 0x7ff) */ +/* ===================================================== DAC_GAIN_REG ====================================================== */ + #define CRG_COM_DAC_GAIN_REG_DAC_GAIN_Q_Pos (8UL) /*!< DAC_GAIN_Q (Bit 8) */ + #define CRG_COM_DAC_GAIN_REG_DAC_GAIN_Q_Msk (0xff00UL) /*!< DAC_GAIN_Q (Bitfield-Mask: 0xff) */ + #define CRG_COM_DAC_GAIN_REG_DAC_GAIN_I_Pos (0UL) /*!< DAC_GAIN_I (Bit 0) */ + #define CRG_COM_DAC_GAIN_REG_DAC_GAIN_I_Msk (0xffUL) /*!< DAC_GAIN_I (Bitfield-Mask: 0xff) */ +/* =================================================== EXT_INTB_CTRL_REG =================================================== */ + #define CRG_COM_EXT_INTB_CTRL_REG_PULSE_DURATION_Pos (2UL) /*!< PULSE_DURATION (Bit 2) */ + #define CRG_COM_EXT_INTB_CTRL_REG_PULSE_DURATION_Msk (0xfcUL) /*!< PULSE_DURATION (Bitfield-Mask: 0x3f) */ + #define CRG_COM_EXT_INTB_CTRL_REG_INTR_MODE_Pos (1UL) /*!< INTR_MODE (Bit 1) */ + #define CRG_COM_EXT_INTB_CTRL_REG_INTR_MODE_Msk (0x2UL) /*!< INTR_MODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_EXT_INTB_CTRL_REG_INTR_POL_Pos (0UL) /*!< INTR_POL (Bit 0) */ + #define CRG_COM_EXT_INTB_CTRL_REG_INTR_POL_Msk (0x1UL) /*!< INTR_POL (Bitfield-Mask: 0x01) */ +/* =================================================== EXT_INTB_SET_REG ==================================================== */ + #define CRG_COM_EXT_INTB_SET_REG_INTR_SET_Pos (0UL) /*!< INTR_SET (Bit 0) */ + #define CRG_COM_EXT_INTB_SET_REG_INTR_SET_Msk (0x1UL) /*!< INTR_SET (Bitfield-Mask: 0x01) */ +/* ===================================================== FADC_CAL1_REG ===================================================== */ + #define CRG_COM_FADC_CAL1_REG_C_ENABLE_Pos (31UL) /*!< C_ENABLE (Bit 31) */ + #define CRG_COM_FADC_CAL1_REG_C_ENABLE_Msk (0x80000000UL) /*!< C_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL1_REG_C_LVL_POLAR_Pos (30UL) /*!< C_LVL_POLAR (Bit 30) */ + #define CRG_COM_FADC_CAL1_REG_C_LVL_POLAR_Msk (0x40000000UL) /*!< C_LVL_POLAR (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL1_REG_C_CAL_START_Pos (29UL) /*!< C_CAL_START (Bit 29) */ + #define CRG_COM_FADC_CAL1_REG_C_CAL_START_Msk (0x20000000UL) /*!< C_CAL_START (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL1_REG_C_OUT_MUTE_Pos (28UL) /*!< C_OUT_MUTE (Bit 28) */ + #define CRG_COM_FADC_CAL1_REG_C_OUT_MUTE_Msk (0x10000000UL) /*!< C_OUT_MUTE (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL1_REG_C_WEIGHT_WR_Pos (27UL) /*!< C_WEIGHT_WR (Bit 27) */ + #define CRG_COM_FADC_CAL1_REG_C_WEIGHT_WR_Msk (0x8000000UL) /*!< C_WEIGHT_WR (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL1_REG_C_DAC_CLK_FREQ_Pos (24UL) /*!< C_DAC_CLK_FREQ (Bit 24) */ + #define CRG_COM_FADC_CAL1_REG_C_DAC_CLK_FREQ_Msk (0x7000000UL) /*!< C_DAC_CLK_FREQ (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CAL1_REG_C_NCO_FREQ_Pos (8UL) /*!< C_NCO_FREQ (Bit 8) */ + #define CRG_COM_FADC_CAL1_REG_C_NCO_FREQ_Msk (0x1fff00UL) /*!< C_NCO_FREQ (Bitfield-Mask: 0x1fff) */ + #define CRG_COM_FADC_CAL1_REG_C_DAC_GAIN_Pos (0UL) /*!< C_DAC_GAIN (Bit 0) */ + #define CRG_COM_FADC_CAL1_REG_C_DAC_GAIN_Msk (0xffUL) /*!< C_DAC_GAIN (Bitfield-Mask: 0xff) */ +/* ===================================================== FADC_CAL2_REG ===================================================== */ + #define CRG_COM_FADC_CAL2_REG_STEP_DELTA_Pos (28UL) /*!< STEP_DELTA (Bit 28) */ + #define CRG_COM_FADC_CAL2_REG_STEP_DELTA_Msk (0x70000000UL) /*!< STEP_DELTA (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CAL2_REG_STEP_ERROR_Pos (24UL) /*!< STEP_ERROR (Bit 24) */ + #define CRG_COM_FADC_CAL2_REG_STEP_ERROR_Msk (0x7000000UL) /*!< STEP_ERROR (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CAL2_REG_SCALE_DELTA_Pos (20UL) /*!< SCALE_DELTA (Bit 20) */ + #define CRG_COM_FADC_CAL2_REG_SCALE_DELTA_Msk (0x700000UL) /*!< SCALE_DELTA (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CAL2_REG_SCALE_ERROR_Pos (16UL) /*!< SCALE_ERROR (Bit 16) */ + #define CRG_COM_FADC_CAL2_REG_SCALE_ERROR_Msk (0x70000UL) /*!< SCALE_ERROR (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CAL2_REG_CND_DONE_Pos (12UL) /*!< CND_DONE (Bit 12) */ + #define CRG_COM_FADC_CAL2_REG_CND_DONE_Msk (0xf000UL) /*!< CND_DONE (Bitfield-Mask: 0x0f) */ + #define CRG_COM_FADC_CAL2_REG_CND_CNT_Pos (8UL) /*!< CND_CNT (Bit 8) */ + #define CRG_COM_FADC_CAL2_REG_CND_CNT_Msk (0x300UL) /*!< CND_CNT (Bitfield-Mask: 0x03) */ + #define CRG_COM_FADC_CAL2_REG_CND_ERROR_TH_Pos (0UL) /*!< CND_ERROR_TH (Bit 0) */ + #define CRG_COM_FADC_CAL2_REG_CND_ERROR_TH_Msk (0xffUL) /*!< CND_ERROR_TH (Bitfield-Mask: 0xff) */ +/* ================================================== FADC_CAL_DONE_I_REG ================================================== */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_DONE_I_Pos (17UL) /*!< CAL_DONE_I (Bit 17) */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_DONE_I_Msk (0x20000UL) /*!< CAL_DONE_I (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_DONE_Q_Pos (16UL) /*!< CAL_DONE_Q (Bit 16) */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_DONE_Q_Msk (0x10000UL) /*!< CAL_DONE_Q (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_CNT_I_Pos (0UL) /*!< CAL_CNT_I (Bit 0) */ + #define CRG_COM_FADC_CAL_DONE_I_REG_CAL_CNT_I_Msk (0xffffUL) /*!< CAL_CNT_I (Bitfield-Mask: 0xffff) */ +/* ================================================== FADC_CAL_DONE_Q_REG ================================================== */ + #define CRG_COM_FADC_CAL_DONE_Q_REG_CAL_DONE_Q_Pos (16UL) /*!< CAL_DONE_Q (Bit 16) */ + #define CRG_COM_FADC_CAL_DONE_Q_REG_CAL_DONE_Q_Msk (0x10000UL) /*!< CAL_DONE_Q (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CAL_DONE_Q_REG_CAL_CNT_Q_Pos (0UL) /*!< CAL_CNT_Q (Bit 0) */ + #define CRG_COM_FADC_CAL_DONE_Q_REG_CAL_CNT_Q_Msk (0xffffUL) /*!< CAL_CNT_Q (Bitfield-Mask: 0xffff) */ +/* ===================================================== FADC_CFG0_REG ===================================================== */ + #define CRG_COM_FADC_CFG0_REG_FADC_RESET_Pos (2UL) /*!< FADC_RESET (Bit 2) */ + #define CRG_COM_FADC_CFG0_REG_FADC_RESET_Msk (0x4UL) /*!< FADC_RESET (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CFG0_REG_FADC_SUSPEND_Pos (1UL) /*!< FADC_SUSPEND (Bit 1) */ + #define CRG_COM_FADC_CFG0_REG_FADC_SUSPEND_Msk (0x2UL) /*!< FADC_SUSPEND (Bitfield-Mask: 0x01) */ + #define CRG_COM_FADC_CFG0_REG_FADC_PD_Pos (0UL) /*!< FADC_PD (Bit 0) */ + #define CRG_COM_FADC_CFG0_REG_FADC_PD_Msk (0x1UL) /*!< FADC_PD (Bitfield-Mask: 0x01) */ +/* ===================================================== FADC_CFG1_REG ===================================================== */ + #define CRG_COM_FADC_CFG1_REG_FADC_VCM_CTRL_Pos (24UL) /*!< FADC_VCM_CTRL (Bit 24) */ + #define CRG_COM_FADC_CFG1_REG_FADC_VCM_CTRL_Msk (0x7000000UL) /*!< FADC_VCM_CTRL (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CFG1_REG_FADC_WKUPPD_Pos (20UL) /*!< FADC_WKUPPD (Bit 20) */ + #define CRG_COM_FADC_CFG1_REG_FADC_WKUPPD_Msk (0xf00000UL) /*!< FADC_WKUPPD (Bitfield-Mask: 0x0f) */ + #define CRG_COM_FADC_CFG1_REG_FADC_WKUPSUSP_Pos (16UL) /*!< FADC_WKUPSUSP (Bit 16) */ + #define CRG_COM_FADC_CFG1_REG_FADC_WKUPSUSP_Msk (0xf0000UL) /*!< FADC_WKUPSUSP (Bitfield-Mask: 0x0f) */ + #define CRG_COM_FADC_CFG1_REG_FADC_ADCBIAS_Pos (12UL) /*!< FADC_ADCBIAS (Bit 12) */ + #define CRG_COM_FADC_CFG1_REG_FADC_ADCBIAS_Msk (0xf000UL) /*!< FADC_ADCBIAS (Bitfield-Mask: 0x0f) */ + #define CRG_COM_FADC_CFG1_REG_FADC_COMPBIAS_Pos (8UL) /*!< FADC_COMPBIAS (Bit 8) */ + #define CRG_COM_FADC_CFG1_REG_FADC_COMPBIAS_Msk (0x300UL) /*!< FADC_COMPBIAS (Bitfield-Mask: 0x03) */ + #define CRG_COM_FADC_CFG1_REG_FADC_MCLKDELS_Pos (4UL) /*!< FADC_MCLKDELS (Bit 4) */ + #define CRG_COM_FADC_CFG1_REG_FADC_MCLKDELS_Msk (0x70UL) /*!< FADC_MCLKDELS (Bitfield-Mask: 0x07) */ + #define CRG_COM_FADC_CFG1_REG_FADC_ASYNCDLY_Pos (0UL) /*!< FADC_ASYNCDLY (Bit 0) */ + #define CRG_COM_FADC_CFG1_REG_FADC_ASYNCDLY_Msk (0x7UL) /*!< FADC_ASYNCDLY (Bitfield-Mask: 0x07) */ +/* ================================================== FADC_DOUT_DELTA_REG ================================================== */ + #define CRG_COM_FADC_DOUT_DELTA_REG_DELTA_I_Pos (16UL) /*!< DELTA_I (Bit 16) */ + #define CRG_COM_FADC_DOUT_DELTA_REG_DELTA_I_Msk (0xffff0000UL) /*!< DELTA_I (Bitfield-Mask: 0xffff) */ + #define CRG_COM_FADC_DOUT_DELTA_REG_DELTA_Q_Pos (0UL) /*!< DELTA_Q (Bit 0) */ + #define CRG_COM_FADC_DOUT_DELTA_REG_DELTA_Q_Msk (0xffffUL) /*!< DELTA_Q (Bitfield-Mask: 0xffff) */ +/* ================================================== FADC_DOUT_ERROR_REG ================================================== */ + #define CRG_COM_FADC_DOUT_ERROR_REG_ERROR_I_Pos (8UL) /*!< ERROR_I (Bit 8) */ + #define CRG_COM_FADC_DOUT_ERROR_REG_ERROR_I_Msk (0xff00UL) /*!< ERROR_I (Bitfield-Mask: 0xff) */ + #define CRG_COM_FADC_DOUT_ERROR_REG_ERROR_Q_Pos (0UL) /*!< ERROR_Q (Bit 0) */ + #define CRG_COM_FADC_DOUT_ERROR_REG_ERROR_Q_Msk (0xffUL) /*!< ERROR_Q (Bitfield-Mask: 0xff) */ +/* =================================================== IP1_BAND_GAP_REG ==================================================== */ + #define CRG_COM_IP1_BAND_GAP_REG_BG_VTRIM_Pos (4UL) /*!< BG_VTRIM (Bit 4) */ + #define CRG_COM_IP1_BAND_GAP_REG_BG_VTRIM_Msk (0x70UL) /*!< BG_VTRIM (Bitfield-Mask: 0x07) */ + #define CRG_COM_IP1_BAND_GAP_REG_LDO_MON_SEL_Pos (0UL) /*!< LDO_MON_SEL (Bit 0) */ + #define CRG_COM_IP1_BAND_GAP_REG_LDO_MON_SEL_Msk (0x7UL) /*!< LDO_MON_SEL (Bitfield-Mask: 0x07) */ +/* =================================================== IP2_BAND_GAP_REG ==================================================== */ + #define CRG_COM_IP2_BAND_GAP_REG_IP2_POR_VDEL_SEL_Pos (4UL) /*!< IP2_POR_VDEL_SEL (Bit 4) */ + #define CRG_COM_IP2_BAND_GAP_REG_IP2_POR_VDEL_SEL_Msk (0x10UL) /*!< IP2_POR_VDEL_SEL (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP2_BAND_GAP_REG_IP2_POR_ADJVFR_Pos (3UL) /*!< IP2_POR_ADJVFR (Bit 3) */ + #define CRG_COM_IP2_BAND_GAP_REG_IP2_POR_ADJVFR_Msk (0x8UL) /*!< IP2_POR_ADJVFR (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP2_BAND_GAP_REG_IP4_VBG_TRIM_Pos (0UL) /*!< IP4_VBG_TRIM (Bit 0) */ + #define CRG_COM_IP2_BAND_GAP_REG_IP4_VBG_TRIM_Msk (0x7UL) /*!< IP4_VBG_TRIM (Bitfield-Mask: 0x07) */ +/* =================================================== IP4_DCDC_DIG_REG ==================================================== */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_CLIM_ENB_Pos (7UL) /*!< DCDC_DIG_CLIM_ENB (Bit 7) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_CLIM_ENB_Msk (0x80UL) /*!< DCDC_DIG_CLIM_ENB (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_ADJ_Pos (4UL) /*!< DCDC_DIG_ADJ (Bit 4) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_ADJ_Msk (0x70UL) /*!< DCDC_DIG_ADJ (Bitfield-Mask: 0x07) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_SUSPENDB_Pos (3UL) /*!< DCDC_DIG_SUSPENDB (Bit 3) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_SUSPENDB_Msk (0x8UL) /*!< DCDC_DIG_SUSPENDB (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_TMF_Pos (0UL) /*!< DCDC_DIG_TMF (Bit 0) */ + #define CRG_COM_IP4_DCDC_DIG_REG_DCDC_DIG_TMF_Msk (0x7UL) /*!< DCDC_DIG_TMF (Bitfield-Mask: 0x07) */ +/* =================================================== IP4_DCDC_FEM_REG ==================================================== */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_CLIM_ENB_Pos (7UL) /*!< DCDC_FEM_CLIM_ENB (Bit 7) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_CLIM_ENB_Msk (0x80UL) /*!< DCDC_FEM_CLIM_ENB (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_ADJ_Pos (4UL) /*!< DCDC_FEM_ADJ (Bit 4) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_ADJ_Msk (0x70UL) /*!< DCDC_FEM_ADJ (Bitfield-Mask: 0x07) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_SUSPENDB_Pos (3UL) /*!< DCDC_FEM_SUSPENDB (Bit 3) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_SUSPENDB_Msk (0x8UL) /*!< DCDC_FEM_SUSPENDB (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_TMF_Pos (0UL) /*!< DCDC_FEM_TMF (Bit 0) */ + #define CRG_COM_IP4_DCDC_FEM_REG_DCDC_FEM_TMF_Msk (0x7UL) /*!< DCDC_FEM_TMF (Bitfield-Mask: 0x07) */ +/* ================================================= IP4_POR_LDO_CTRL_REG ================================================== */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_DIGTOP_LDO_CTRL_Pos (4UL) /*!< DIGTOP_LDO_CTRL (Bit 4) */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_DIGTOP_LDO_CTRL_Msk (0x70UL) /*!< DIGTOP_LDO_CTRL (Bitfield-Mask: 0x07) */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_IP4_POR_VDET_SEL_Pos (1UL) /*!< IP4_POR_VDET_SEL (Bit 1) */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_IP4_POR_VDET_SEL_Msk (0x2UL) /*!< IP4_POR_VDET_SEL (Bitfield-Mask: 0x01) */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_IP4_POR_ADJVFR_Pos (0UL) /*!< IP4_POR_ADJVFR (Bit 0) */ + #define CRG_COM_IP4_POR_LDO_CTRL_REG_IP4_POR_ADJVFR_Msk (0x1UL) /*!< IP4_POR_ADJVFR (Bitfield-Mask: 0x01) */ +/* ===================================================== LDO_CTRL_REG ====================================================== */ + #define CRG_COM_LDO_CTRL_REG_IP2_BG_TRIM_Pos (3UL) /*!< IP2_BG_TRIM (Bit 3) */ + #define CRG_COM_LDO_CTRL_REG_IP2_BG_TRIM_Msk (0x38UL) /*!< IP2_BG_TRIM (Bitfield-Mask: 0x07) */ + #define CRG_COM_LDO_CTRL_REG_FLDO_VCTRL_Pos (0UL) /*!< FLDO_VCTRL (Bit 0) */ + #define CRG_COM_LDO_CTRL_REG_FLDO_VCTRL_Msk (0x7UL) /*!< FLDO_VCTRL (Bitfield-Mask: 0x07) */ +/* ==================================================== MEMORY_CTRL_REG ==================================================== */ + #define CRG_COM_MEMORY_CTRL_REG_OTHER_MEM_Pos (28UL) /*!< OTHER_MEM (Bit 28) */ + #define CRG_COM_MEMORY_CTRL_REG_OTHER_MEM_Msk (0xf0000000UL) /*!< OTHER_MEM (Bitfield-Mask: 0x0f) */ + #define CRG_COM_MEMORY_CTRL_REG_SYS_CLK_MODE_Pos (24UL) /*!< SYS_CLK_MODE (Bit 24) */ + #define CRG_COM_MEMORY_CTRL_REG_SYS_CLK_MODE_Msk (0x1000000UL) /*!< SYS_CLK_MODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_MEMORY_CTRL_REG_MAC_MEM_Pos (20UL) /*!< MAC_MEM (Bit 20) */ + #define CRG_COM_MEMORY_CTRL_REG_MAC_MEM_Msk (0xf00000UL) /*!< MAC_MEM (Bitfield-Mask: 0x0f) */ + #define CRG_COM_MEMORY_CTRL_REG_PHY_MEM_Pos (16UL) /*!< PHY_MEM (Bit 16) */ + #define CRG_COM_MEMORY_CTRL_REG_PHY_MEM_Msk (0xf0000UL) /*!< PHY_MEM (Bitfield-Mask: 0x0f) */ + #define CRG_COM_MEMORY_CTRL_REG_ROM_Pos (8UL) /*!< ROM (Bit 8) */ + #define CRG_COM_MEMORY_CTRL_REG_ROM_Msk (0xf00UL) /*!< ROM (Bitfield-Mask: 0x0f) */ + #define CRG_COM_MEMORY_CTRL_REG_RET_MEM_Pos (4UL) /*!< RET_MEM (Bit 4) */ + #define CRG_COM_MEMORY_CTRL_REG_RET_MEM_Msk (0xf0UL) /*!< RET_MEM (Bitfield-Mask: 0x0f) */ + #define CRG_COM_MEMORY_CTRL_REG_CPU_SRAM_Pos (0UL) /*!< CPU_SRAM (Bit 0) */ + #define CRG_COM_MEMORY_CTRL_REG_CPU_SRAM_Msk (0xfUL) /*!< CPU_SRAM (Bitfield-Mask: 0x0f) */ +/* ==================================================== MON_RF_TEST_REG ==================================================== */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_IP_EXTMODE_Pos (23UL) /*!< EN_IQSW_IP_EXTMODE (Bit 23) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_IP_EXTMODE_Msk (0x800000UL) /*!< EN_IQSW_IP_EXTMODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_IN_EXTMODE_Pos (22UL) /*!< EN_IQSW_IN_EXTMODE (Bit 22) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_IN_EXTMODE_Msk (0x400000UL) /*!< EN_IQSW_IN_EXTMODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_QP_EXTMODE_Pos (21UL) /*!< EN_IQSW_QP_EXTMODE (Bit 21) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_QP_EXTMODE_Msk (0x200000UL) /*!< EN_IQSW_QP_EXTMODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_QN_EXTMODE_Pos (20UL) /*!< EN_IQSW_QN_EXTMODE (Bit 20) */ + #define CRG_COM_MON_RF_TEST_REG_EN_IQSW_QN_EXTMODE_Msk (0x100000UL) /*!< EN_IQSW_QN_EXTMODE (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_IP_SEN_Pos (19UL) /*!< SEL_IQSEL_IP_SEN (Bit 19) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_IP_SEN_Msk (0x80000UL) /*!< SEL_IQSEL_IP_SEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_IN_SEN_Pos (18UL) /*!< SEL_IQSEL_IN_SEN (Bit 18) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_IN_SEN_Msk (0x40000UL) /*!< SEL_IQSEL_IN_SEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_QP_SEN_Pos (17UL) /*!< SEL_IQSEL_QP_SEN (Bit 17) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_QP_SEN_Msk (0x20000UL) /*!< SEL_IQSEL_QP_SEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_QN_SEN_Pos (16UL) /*!< SEL_IQSEL_QN_SEN (Bit 16) */ + #define CRG_COM_MON_RF_TEST_REG_SEL_IQSEL_QN_SEN_Msk (0x10000UL) /*!< SEL_IQSEL_QN_SEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IP_EXT_Pos (15UL) /*!< IQ2NDSW_SEL_IP_EXT (Bit 15) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IP_EXT_Msk (0x8000UL) /*!< IQ2NDSW_SEL_IP_EXT (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IN_EXT_Pos (14UL) /*!< IQ2NDSW_SEL_IN_EXT (Bit 14) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IN_EXT_Msk (0x4000UL) /*!< IQ2NDSW_SEL_IN_EXT (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QP_EXT_Pos (13UL) /*!< IQ2NDSW_SEL_QP_EXT (Bit 13) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QP_EXT_Msk (0x2000UL) /*!< IQ2NDSW_SEL_QP_EXT (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QN_EXT_Pos (12UL) /*!< IQ2NDSW_SEL_QN_EXT (Bit 12) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QN_EXT_Msk (0x1000UL) /*!< IQ2NDSW_SEL_QN_EXT (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IP_Pos (11UL) /*!< IQ2NDSW_SEL_IP (Bit 11) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IP_Msk (0x800UL) /*!< IQ2NDSW_SEL_IP (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IN_Pos (10UL) /*!< IQ2NDSW_SEL_IN (Bit 10) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_IN_Msk (0x400UL) /*!< IQ2NDSW_SEL_IN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QP_Pos (9UL) /*!< IQ2NDSW_SEL_QP (Bit 9) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QP_Msk (0x200UL) /*!< IQ2NDSW_SEL_QP (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QN_Pos (8UL) /*!< IQ2NDSW_SEL_QN (Bit 8) */ + #define CRG_COM_MON_RF_TEST_REG_IQ2NDSW_SEL_QN_Msk (0x100UL) /*!< IQ2NDSW_SEL_QN (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IP1_Pos (7UL) /*!< BB2RF_MUX_IP1 (Bit 7) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IP1_Msk (0x80UL) /*!< BB2RF_MUX_IP1 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IP0_Pos (6UL) /*!< BB2RF_MUX_IP0 (Bit 6) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IP0_Msk (0x40UL) /*!< BB2RF_MUX_IP0 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IN1_Pos (5UL) /*!< BB2RF_MUX_IN1 (Bit 5) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IN1_Msk (0x20UL) /*!< BB2RF_MUX_IN1 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IN0_Pos (4UL) /*!< BB2RF_MUX_IN0 (Bit 4) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_IN0_Msk (0x10UL) /*!< BB2RF_MUX_IN0 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QP1_Pos (3UL) /*!< BB2RF_MUX_QP1 (Bit 3) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QP1_Msk (0x8UL) /*!< BB2RF_MUX_QP1 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QP0_Pos (2UL) /*!< BB2RF_MUX_QP0 (Bit 2) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QP0_Msk (0x4UL) /*!< BB2RF_MUX_QP0 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QN1_Pos (1UL) /*!< BB2RF_MUX_QN1 (Bit 1) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QN1_Msk (0x2UL) /*!< BB2RF_MUX_QN1 (Bitfield-Mask: 0x01) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QN0_Pos (0UL) /*!< BB2RF_MUX_QN0 (Bit 0) */ + #define CRG_COM_MON_RF_TEST_REG_BB2RF_MUX_QN0_Msk (0x1UL) /*!< BB2RF_MUX_QN0 (Bitfield-Mask: 0x01) */ +/* ================================================= NORMAL_TEST_CTRL_REG ================================================== */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_IQ_SEL_Pos (12UL) /*!< IQ_SEL (Bit 12) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_IQ_SEL_Msk (0x1000UL) /*!< IQ_SEL (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_DEBUG_WIFI_Pos (11UL) /*!< DEBUG_WIFI (Bit 11) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_DEBUG_WIFI_Msk (0x800UL) /*!< DEBUG_WIFI (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_RTC_Pos (10UL) /*!< RTC (Bit 10) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_RTC_Msk (0x400UL) /*!< RTC (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_IQ_ADC_Pos (9UL) /*!< IQ_ADC (Bit 9) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_IQ_ADC_Msk (0x200UL) /*!< IQ_ADC (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_AUXADC12B_Pos (7UL) /*!< AUXADC12B (Bit 7) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_AUXADC12B_Msk (0x80UL) /*!< AUXADC12B (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_ADC_DAC_LB_Pos (6UL) /*!< ADC_DAC_LB (Bit 6) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_ADC_DAC_LB_Msk (0x40UL) /*!< ADC_DAC_LB (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_EXT_BB_Pos (5UL) /*!< EXT_BB (Bit 5) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_EXT_BB_Msk (0x20UL) /*!< EXT_BB (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_EXT_RF_Pos (4UL) /*!< EXT_RF (Bit 4) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_EXT_RF_Msk (0x10UL) /*!< EXT_RF (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_DEBUG_GPIO_Pos (3UL) /*!< DEBUG_GPIO (Bit 3) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_DEBUG_GPIO_Msk (0x8UL) /*!< DEBUG_GPIO (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_FLASH_Pos (1UL) /*!< FLASH (Bit 1) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_FLASH_Msk (0x2UL) /*!< FLASH (Bitfield-Mask: 0x01) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_PLL1_Pos (0UL) /*!< PLL1 (Bit 0) */ + #define CRG_COM_NORMAL_TEST_CTRL_REG_PLL1_Msk (0x1UL) /*!< PLL1 (Bitfield-Mask: 0x01) */ +/* =================================================== PAD_LATCH_EN_REG ==================================================== */ + #define CRG_COM_PAD_LATCH_EN_REG_P1_LATCH_EN_Pos (16UL) /*!< P1_LATCH_EN (Bit 16) */ + #define CRG_COM_PAD_LATCH_EN_REG_P1_LATCH_EN_Msk (0xffff0000UL) /*!< P1_LATCH_EN (Bitfield-Mask: 0xffff) */ + #define CRG_COM_PAD_LATCH_EN_REG_P0_LATCH_EN_Pos (2UL) /*!< P0_LATCH_EN (Bit 2) */ + #define CRG_COM_PAD_LATCH_EN_REG_P0_LATCH_EN_Msk (0xfffcUL) /*!< P0_LATCH_EN (Bitfield-Mask: 0x3fff) */ + #define CRG_COM_PAD_LATCH_EN_REG_SWD_LATCH_EN_Pos (0UL) /*!< SWD_LATCH_EN (Bit 0) */ + #define CRG_COM_PAD_LATCH_EN_REG_SWD_LATCH_EN_Msk (0x3UL) /*!< SWD_LATCH_EN (Bitfield-Mask: 0x03) */ +/* =================================================== PLL1_ARM_CTRL_REG =================================================== */ + #define CRG_COM_PLL1_ARM_CTRL_REG_PLL_LOCK_Pos (13UL) /*!< PLL_LOCK (Bit 13) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_PLL_LOCK_Msk (0x2000UL) /*!< PLL_LOCK (Bitfield-Mask: 0x01) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_LF_RCTRL_Pos (11UL) /*!< DPLL1_LF_RCTRL (Bit 11) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_LF_RCTRL_Msk (0x1800UL) /*!< DPLL1_LF_RCTRL (Bitfield-Mask: 0x03) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_SHORT_S_Pos (9UL) /*!< DPLL1_SHORT_S (Bit 9) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_SHORT_S_Msk (0x600UL) /*!< DPLL1_SHORT_S (Bitfield-Mask: 0x03) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_EN_Pos (8UL) /*!< DPLL1_EN (Bit 8) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_EN_Msk (0x100UL) /*!< DPLL1_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_VCO_SEL_Pos (6UL) /*!< DPLL1_VCO_SEL (Bit 6) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_VCO_SEL_Msk (0xc0UL) /*!< DPLL1_VCO_SEL (Bitfield-Mask: 0x03) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_DIV_SEL_Pos (0UL) /*!< DPLL1_DIV_SEL (Bit 0) */ + #define CRG_COM_PLL1_ARM_CTRL_REG_DPLL1_DIV_SEL_Msk (0x3fUL) /*!< DPLL1_DIV_SEL (Bitfield-Mask: 0x3f) */ +/* =================================================== POWER_MANAGE_REG ==================================================== */ + #define CRG_COM_POWER_MANAGE_REG_ISCO_EN_Pos (2UL) /*!< ISCO_EN (Bit 2) */ + #define CRG_COM_POWER_MANAGE_REG_ISCO_EN_Msk (0x4UL) /*!< ISCO_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_POWER_MANAGE_REG_ISO_EN_Pos (1UL) /*!< ISO_EN (Bit 1) */ + #define CRG_COM_POWER_MANAGE_REG_ISO_EN_Msk (0x2UL) /*!< ISO_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== PSRAM_DEBUG_REG ==================================================== */ + #define CRG_COM_PSRAM_DEBUG_REG_PSRAM_STS_MON_Pos (8UL) /*!< PSRAM_STS_MON (Bit 8) */ + #define CRG_COM_PSRAM_DEBUG_REG_PSRAM_STS_MON_Msk (0x1f00UL) /*!< PSRAM_STS_MON (Bitfield-Mask: 0x1f) */ + #define CRG_COM_PSRAM_DEBUG_REG_LATENCY_CNT_Pos (0UL) /*!< LATENCY_CNT (Bit 0) */ + #define CRG_COM_PSRAM_DEBUG_REG_LATENCY_CNT_Msk (0x1fUL) /*!< LATENCY_CNT (Bitfield-Mask: 0x1f) */ +/* ===================================================== TEST_CFG_REG ====================================================== */ + #define CRG_COM_TEST_CFG_REG_CTRL_TX_ATTEN_Pos (16UL) /*!< CTRL_TX_ATTEN (Bit 16) */ + #define CRG_COM_TEST_CFG_REG_CTRL_TX_ATTEN_Msk (0x3f0000UL) /*!< CTRL_TX_ATTEN (Bitfield-Mask: 0x3f) */ + #define CRG_COM_TEST_CFG_REG_TST_GPIO1_DIO2_EN_Pos (15UL) /*!< TST_GPIO1_DIO2_EN (Bit 15) */ + #define CRG_COM_TEST_CFG_REG_TST_GPIO1_DIO2_EN_Msk (0x8000UL) /*!< TST_GPIO1_DIO2_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TST_GPIO0_DIO2_EN_Pos (14UL) /*!< TST_GPIO0_DIO2_EN (Bit 14) */ + #define CRG_COM_TEST_CFG_REG_TST_GPIO0_DIO2_EN_Msk (0x4000UL) /*!< TST_GPIO0_DIO2_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TX_HPI_BURNIN_EN_Pos (13UL) /*!< TX_HPI_BURNIN_EN (Bit 13) */ + #define CRG_COM_TEST_CFG_REG_TX_HPI_BURNIN_EN_Msk (0x2000UL) /*!< TX_HPI_BURNIN_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_HPI_BURNIN_EN_Pos (12UL) /*!< HPI_BURNIN_EN (Bit 12) */ + #define CRG_COM_TEST_CFG_REG_HPI_BURNIN_EN_Msk (0x1000UL) /*!< HPI_BURNIN_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TST2_GPIO_EN_Pos (11UL) /*!< TST2_GPIO_EN (Bit 11) */ + #define CRG_COM_TEST_CFG_REG_TST2_GPIO_EN_Msk (0x800UL) /*!< TST2_GPIO_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TST1_GPIO_EN_Pos (10UL) /*!< TST1_GPIO_EN (Bit 10) */ + #define CRG_COM_TEST_CFG_REG_TST1_GPIO_EN_Msk (0x400UL) /*!< TST1_GPIO_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TST2_GPADC_EN_Pos (9UL) /*!< TST2_GPADC_EN (Bit 9) */ + #define CRG_COM_TEST_CFG_REG_TST2_GPADC_EN_Msk (0x200UL) /*!< TST2_GPADC_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_TST1_GPADC_EN_Pos (8UL) /*!< TST1_GPADC_EN (Bit 8) */ + #define CRG_COM_TEST_CFG_REG_TST1_GPADC_EN_Msk (0x100UL) /*!< TST1_GPADC_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_TEST_CFG_REG_SEL_TST2_MUX_Pos (4UL) /*!< SEL_TST2_MUX (Bit 4) */ + #define CRG_COM_TEST_CFG_REG_SEL_TST2_MUX_Msk (0xf0UL) /*!< SEL_TST2_MUX (Bitfield-Mask: 0x0f) */ + #define CRG_COM_TEST_CFG_REG_SEL_TST1_MUX_Pos (0UL) /*!< SEL_TST1_MUX (Bit 0) */ + #define CRG_COM_TEST_CFG_REG_SEL_TST1_MUX_Msk (0xfUL) /*!< SEL_TST1_MUX (Bitfield-Mask: 0x0f) */ +/* =================================================== XTAL32K_CTRL_REG ==================================================== */ + #define CRG_COM_XTAL32K_CTRL_REG_XTAL32K_ENABLE_Pos (0UL) /*!< XTAL32K_ENABLE (Bit 0) */ + #define CRG_COM_XTAL32K_CTRL_REG_XTAL32K_ENABLE_Msk (0x1UL) /*!< XTAL32K_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== XTAL40M_CTRL_REG ==================================================== */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RDY_Pos (23UL) /*!< XTAL40M_RDY (Bit 23) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RDY_Msk (0x800000UL) /*!< XTAL40M_RDY (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_CCTRL_Pos (16UL) /*!< XTAL40M_CCTRL (Bit 16) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_CCTRL_Msk (0x7f0000UL) /*!< XTAL40M_CCTRL (Bitfield-Mask: 0x7f) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40_GAIN_Pos (8UL) /*!< XTAL40_GAIN (Bit 8) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40_GAIN_Msk (0x700UL) /*!< XTAL40_GAIN (Bitfield-Mask: 0x07) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_ADCCLK_EN_Pos (6UL) /*!< XTAL40M_ADCCLK_EN (Bit 6) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_ADCCLK_EN_Msk (0x40UL) /*!< XTAL40M_ADCCLK_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_TX_EN_Pos (5UL) /*!< XTAL40M_TX_EN (Bit 5) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_TX_EN_Msk (0x20UL) /*!< XTAL40M_TX_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_FPLL_EN_Pos (4UL) /*!< XTAL40M_FPLL_EN (Bit 4) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_FPLL_EN_Msk (0x10UL) /*!< XTAL40M_FPLL_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RFPLL_EN_Pos (3UL) /*!< XTAL40M_RFPLL_EN (Bit 3) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RFPLL_EN_Msk (0x8UL) /*!< XTAL40M_RFPLL_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_DPLL_EN_Pos (2UL) /*!< XTAL40M_DPLL_EN (Bit 2) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_DPLL_EN_Msk (0x4UL) /*!< XTAL40M_DPLL_EN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RFEN_Pos (1UL) /*!< XTAL40M_RFEN (Bit 1) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_RFEN_Msk (0x2UL) /*!< XTAL40M_RFEN (Bitfield-Mask: 0x01) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_EN_Pos (0UL) /*!< XTAL40M_EN (Bit 0) */ + #define CRG_COM_XTAL40M_CTRL_REG_XTAL40M_EN_Msk (0x1UL) /*!< XTAL40M_EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CRG_PER ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CLK_COM_REG ====================================================== */ + #define CRG_PER_CLK_COM_REG_SDEMMC_ENABLE_Pos (13UL) /*!< SDEMMC_ENABLE (Bit 13) */ + #define CRG_PER_CLK_COM_REG_SDEMMC_ENABLE_Msk (0x2000UL) /*!< SDEMMC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_SDIO_ENABLE_Pos (12UL) /*!< SDIO_ENABLE (Bit 12) */ + #define CRG_PER_CLK_COM_REG_SDIO_ENABLE_Msk (0x1000UL) /*!< SDIO_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_UART3_ENABLE_Pos (11UL) /*!< UART3_ENABLE (Bit 11) */ + #define CRG_PER_CLK_COM_REG_UART3_ENABLE_Msk (0x800UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_UART2_ENABLE_Pos (10UL) /*!< UART2_ENABLE (Bit 10) */ + #define CRG_PER_CLK_COM_REG_UART2_ENABLE_Msk (0x400UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_UART_ENABLE_Pos (9UL) /*!< UART_ENABLE (Bit 9) */ + #define CRG_PER_CLK_COM_REG_UART_ENABLE_Msk (0x200UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_AUXADC_ENABLE_Pos (8UL) /*!< AUXADC_ENABLE (Bit 8) */ + #define CRG_PER_CLK_COM_REG_AUXADC_ENABLE_Msk (0x100UL) /*!< AUXADC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_I2C2_CLK_SEL_Pos (7UL) /*!< I2C2_CLK_SEL (Bit 7) */ + #define CRG_PER_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x80UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_I2C2_ENABLE_Pos (6UL) /*!< I2C2_ENABLE (Bit 6) */ + #define CRG_PER_CLK_COM_REG_I2C2_ENABLE_Msk (0x40UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_I2C_CLK_SEL_Pos (5UL) /*!< I2C_CLK_SEL (Bit 5) */ + #define CRG_PER_CLK_COM_REG_I2C_CLK_SEL_Msk (0x20UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_I2C_ENABLE_Pos (4UL) /*!< I2C_ENABLE (Bit 4) */ + #define CRG_PER_CLK_COM_REG_I2C_ENABLE_Msk (0x10UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_SPI2_ENABLE_Pos (2UL) /*!< SPI2_ENABLE (Bit 2) */ + #define CRG_PER_CLK_COM_REG_SPI2_ENABLE_Msk (0x4UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_CLK_COM_REG_SPI_ENABLE_Pos (0UL) /*!< SPI_ENABLE (Bit 0) */ + #define CRG_PER_CLK_COM_REG_SPI_ENABLE_Msk (0x1UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== RESET_CLK_COM_REG =================================================== */ + #define CRG_PER_RESET_CLK_COM_REG_SDEMMC_ENABLE_Pos (13UL) /*!< SDEMMC_ENABLE (Bit 13) */ + #define CRG_PER_RESET_CLK_COM_REG_SDEMMC_ENABLE_Msk (0x2000UL) /*!< SDEMMC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_SDIO_ENABLE_Pos (12UL) /*!< SDIO_ENABLE (Bit 12) */ + #define CRG_PER_RESET_CLK_COM_REG_SDIO_ENABLE_Msk (0x1000UL) /*!< SDIO_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_UART3_ENABLE_Pos (11UL) /*!< UART3_ENABLE (Bit 11) */ + #define CRG_PER_RESET_CLK_COM_REG_UART3_ENABLE_Msk (0x800UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_UART2_ENABLE_Pos (10UL) /*!< UART2_ENABLE (Bit 10) */ + #define CRG_PER_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x400UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_UART_ENABLE_Pos (9UL) /*!< UART_ENABLE (Bit 9) */ + #define CRG_PER_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x200UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_AUXADC_ENABLE_Pos (8UL) /*!< AUXADC_ENABLE (Bit 8) */ + #define CRG_PER_RESET_CLK_COM_REG_AUXADC_ENABLE_Msk (0x100UL) /*!< AUXADC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C2_CLK_SEL_Pos (7UL) /*!< I2C2_CLK_SEL (Bit 7) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x80UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C2_ENABLE_Pos (6UL) /*!< I2C2_ENABLE (Bit 6) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C2_ENABLE_Msk (0x40UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (5UL) /*!< I2C_CLK_SEL (Bit 5) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x20UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C_ENABLE_Pos (4UL) /*!< I2C_ENABLE (Bit 4) */ + #define CRG_PER_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x10UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_SPI2_ENABLE_Pos (2UL) /*!< SPI2_ENABLE (Bit 2) */ + #define CRG_PER_RESET_CLK_COM_REG_SPI2_ENABLE_Msk (0x4UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_RESET_CLK_COM_REG_SPI_ENABLE_Pos (0UL) /*!< SPI_ENABLE (Bit 0) */ + #define CRG_PER_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x1UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== SET_CLK_COM_REG ==================================================== */ + #define CRG_PER_SET_CLK_COM_REG_SDEMMC_ENABLE_Pos (13UL) /*!< SDEMMC_ENABLE (Bit 13) */ + #define CRG_PER_SET_CLK_COM_REG_SDEMMC_ENABLE_Msk (0x2000UL) /*!< SDEMMC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_SDIO_ENABLE_Pos (12UL) /*!< SDIO_ENABLE (Bit 12) */ + #define CRG_PER_SET_CLK_COM_REG_SDIO_ENABLE_Msk (0x1000UL) /*!< SDIO_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_UART3_ENABLE_Pos (11UL) /*!< UART3_ENABLE (Bit 11) */ + #define CRG_PER_SET_CLK_COM_REG_UART3_ENABLE_Msk (0x800UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_UART2_ENABLE_Pos (10UL) /*!< UART2_ENABLE (Bit 10) */ + #define CRG_PER_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x400UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_UART_ENABLE_Pos (9UL) /*!< UART_ENABLE (Bit 9) */ + #define CRG_PER_SET_CLK_COM_REG_UART_ENABLE_Msk (0x200UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_AUXADC_ENABLE_Pos (8UL) /*!< AUXADC_ENABLE (Bit 8) */ + #define CRG_PER_SET_CLK_COM_REG_AUXADC_ENABLE_Msk (0x100UL) /*!< AUXADC_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_I2C2_CLK_SEL_Pos (7UL) /*!< I2C2_CLK_SEL (Bit 7) */ + #define CRG_PER_SET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x80UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_I2C2_ENABLE_Pos (6UL) /*!< I2C2_ENABLE (Bit 6) */ + #define CRG_PER_SET_CLK_COM_REG_I2C2_ENABLE_Msk (0x40UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (5UL) /*!< I2C_CLK_SEL (Bit 5) */ + #define CRG_PER_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x20UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_I2C_ENABLE_Pos (4UL) /*!< I2C_ENABLE (Bit 4) */ + #define CRG_PER_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x10UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_SPI2_ENABLE_Pos (2UL) /*!< SPI2_ENABLE (Bit 2) */ + #define CRG_PER_SET_CLK_COM_REG_SPI2_ENABLE_Msk (0x4UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_PER_SET_CLK_COM_REG_SPI_ENABLE_Pos (0UL) /*!< SPI_ENABLE (Bit 0) */ + #define CRG_PER_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x1UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CRG_SYS ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CACHE_RAM_CTRL_REG =================================================== */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WRASD_Pos (6UL) /*!< CACHERAM_MA_WRASD (Bit 6) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WRASD_Msk (0x40UL) /*!< CACHERAM_MA_WRASD (Bitfield-Mask: 0x01) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WRAS_Pos (4UL) /*!< CACHERAM_MA_WRAS (Bit 4) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WRAS_Msk (0x30UL) /*!< CACHERAM_MA_WRAS (Bitfield-Mask: 0x03) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WL_Pos (2UL) /*!< CACHERAM_MA_WL (Bit 2) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_WL_Msk (0xcUL) /*!< CACHERAM_MA_WL (Bitfield-Mask: 0x03) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_SAWL_Pos (0UL) /*!< CACHERAM_MA_SAWL (Bit 0) */ + #define CRG_SYS_CACHE_RAM_CTRL_REG_CACHERAM_MA_SAWL_Msk (0x3UL) /*!< CACHERAM_MA_SAWL (Bitfield-Mask: 0x03) */ +/* ================================================== CRYPTO_RAM_CTRL_REG ================================================== */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WRASD_Pos (3UL) /*!< CRYPTORAM_MA_WRASD (Bit 3) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WRASD_Msk (0x8UL) /*!< CRYPTORAM_MA_WRASD (Bitfield-Mask: 0x01) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WRAS_Pos (2UL) /*!< CRYPTORAM_MA_WRAS (Bit 2) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WRAS_Msk (0x4UL) /*!< CRYPTORAM_MA_WRAS (Bitfield-Mask: 0x01) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WL_Pos (1UL) /*!< CRYPTORAM_MA_WL (Bit 1) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_WL_Msk (0x2UL) /*!< CRYPTORAM_MA_WL (Bitfield-Mask: 0x01) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_SAWL_Pos (0UL) /*!< CRYPTORAM_MA_SAWL (Bit 0) */ + #define CRG_SYS_CRYPTO_RAM_CTRL_REG_CRYPTORAM_MA_SAWL_Msk (0x1UL) /*!< CRYPTORAM_MA_SAWL (Bitfield-Mask: 0x01) */ +/* ================================================== DCACHE_RAM_CTRL_REG ================================================== */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WRASD_Pos (3UL) /*!< DCACHERAM_MA_WRASD (Bit 3) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WRASD_Msk (0x8UL) /*!< DCACHERAM_MA_WRASD (Bitfield-Mask: 0x01) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WRAS_Pos (2UL) /*!< DCACHERAM_MA_WRAS (Bit 2) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WRAS_Msk (0x4UL) /*!< DCACHERAM_MA_WRAS (Bitfield-Mask: 0x01) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WL_Pos (1UL) /*!< DCACHERAM_MA_WL (Bit 1) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_WL_Msk (0x2UL) /*!< DCACHERAM_MA_WL (Bitfield-Mask: 0x01) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_SAWL_Pos (0UL) /*!< DCACHERAM_MA_SAWL (Bit 0) */ + #define CRG_SYS_DCACHE_RAM_CTRL_REG_DCACHERAM_MA_SAWL_Msk (0x1UL) /*!< DCACHERAM_MA_SAWL (Bitfield-Mask: 0x01) */ +/* =================================================== HPI_CLK_CTRL_REG ==================================================== */ + #define CRG_SYS_HPI_CLK_CTRL_REG_HPI_CLK_DCG_Pos (1UL) /*!< HPI_CLK_DCG (Bit 1) */ + #define CRG_SYS_HPI_CLK_CTRL_REG_HPI_CLK_DCG_Msk (0x2UL) /*!< HPI_CLK_DCG (Bitfield-Mask: 0x01) */ + #define CRG_SYS_HPI_CLK_CTRL_REG_HPI_CLK_OFF_Pos (0UL) /*!< HPI_CLK_OFF (Bit 0) */ + #define CRG_SYS_HPI_CLK_CTRL_REG_HPI_CLK_OFF_Msk (0x1UL) /*!< HPI_CLK_OFF (Bitfield-Mask: 0x01) */ +/* =================================================== MEM_CLK_CTRL_REG ==================================================== */ + #define CRG_SYS_MEM_CLK_CTRL_REG_CACHERAM_CLK_DCG_Pos (5UL) /*!< CACHERAM_CLK_DCG (Bit 5) */ + #define CRG_SYS_MEM_CLK_CTRL_REG_CACHERAM_CLK_DCG_Msk (0x20UL) /*!< CACHERAM_CLK_DCG (Bitfield-Mask: 0x01) */ + #define CRG_SYS_MEM_CLK_CTRL_REG_CACHERAM_CLK_OFF_Pos (4UL) /*!< CACHERAM_CLK_OFF (Bit 4) */ + #define CRG_SYS_MEM_CLK_CTRL_REG_CACHERAM_CLK_OFF_Msk (0x10UL) /*!< CACHERAM_CLK_OFF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CRG_TOP ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== AUX_CLK_DIV_REG ==================================================== */ + #define CRG_TOP_AUX_CLK_DIV_REG_CLK_DIV_AUXA_Pos (0UL) /*!< CLK_DIV_AUXA (Bit 0) */ + #define CRG_TOP_AUX_CLK_DIV_REG_CLK_DIV_AUXA_Msk (0x3ffUL) /*!< CLK_DIV_AUXA (Bitfield-Mask: 0x3ff) */ +/* ===================================================== CLK_AMBA_REG ====================================================== */ + #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_SYNC_Pos (28UL) /*!< HCLK_DIV_SYNC (Bit 28) */ + #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_SYNC_Msk (0x70000000UL) /*!< HCLK_DIV_SYNC (Bitfield-Mask: 0x07) */ + #define CRG_TOP_CLK_AMBA_REG_KDMA_CLK_ENABLE_Pos (27UL) /*!< KDMA_CLK_ENABLE (Bit 27) */ + #define CRG_TOP_CLK_AMBA_REG_KDMA_CLK_ENABLE_Msk (0x8000000UL) /*!< KDMA_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_SPI_CLK_ENABLE_Pos (26UL) /*!< SPI_CLK_ENABLE (Bit 26) */ + #define CRG_TOP_CLK_AMBA_REG_SPI_CLK_ENABLE_Msk (0x4000000UL) /*!< SPI_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_AUX_CLK_ENABLE_Pos (25UL) /*!< AUX_CLK_ENABLE (Bit 25) */ + #define CRG_TOP_CLK_AMBA_REG_AUX_CLK_ENABLE_Msk (0x2000000UL) /*!< AUX_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_TIMER_CLK_ENABLE_Pos (24UL) /*!< TIMER_CLK_ENABLE (Bit 24) */ + #define CRG_TOP_CLK_AMBA_REG_TIMER_CLK_ENABLE_Msk (0x1000000UL) /*!< TIMER_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_PERI_CLK_ENABLE_Pos (23UL) /*!< PERI_CLK_ENABLE (Bit 23) */ + #define CRG_TOP_CLK_AMBA_REG_PERI_CLK_ENABLE_Msk (0x800000UL) /*!< PERI_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_PHY_CLK_ENABLE_Pos (22UL) /*!< PHY_CLK_ENABLE (Bit 22) */ + #define CRG_TOP_CLK_AMBA_REG_PHY_CLK_ENABLE_Msk (0x400000UL) /*!< PHY_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_CC312_CLK_ENABLE_Pos (21UL) /*!< CC312_CLK_ENABLE (Bit 21) */ + #define CRG_TOP_CLK_AMBA_REG_CC312_CLK_ENABLE_Msk (0x200000UL) /*!< CC312_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_GEN_DMA_ENABLE_Pos (20UL) /*!< GEN_DMA_ENABLE (Bit 20) */ + #define CRG_TOP_CLK_AMBA_REG_GEN_DMA_ENABLE_Msk (0x100000UL) /*!< GEN_DMA_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_SYS_MEM_ENABLE_Pos (19UL) /*!< SYS_MEM_ENABLE (Bit 19) */ + #define CRG_TOP_CLK_AMBA_REG_SYS_MEM_ENABLE_Msk (0x80000UL) /*!< SYS_MEM_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_PULLDN_ENABLE_Pos (18UL) /*!< OQSPI_PULLDN_ENABLE (Bit 18) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_PULLDN_ENABLE_Msk (0x40000UL) /*!< OQSPI_PULLDN_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_PULLUP_ENABLE_Pos (17UL) /*!< OQSPI_PULLUP_ENABLE (Bit 17) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_PULLUP_ENABLE_Msk (0x20000UL) /*!< OQSPI_PULLUP_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_GPIO_MODE_Pos (16UL) /*!< OQSPI_GPIO_MODE (Bit 16) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPI_GPIO_MODE_Msk (0x10000UL) /*!< OQSPI_GPIO_MODE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_PULLDN_ENABLE_Pos (15UL) /*!< QSPI2_PULLDN_ENABLE (Bit 15) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_PULLDN_ENABLE_Msk (0x8000UL) /*!< QSPI2_PULLDN_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_PULLUP_ENABLE_Pos (14UL) /*!< QSPI2_PULLUP_ENABLE (Bit 14) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_PULLUP_ENABLE_Msk (0x4000UL) /*!< QSPI2_PULLUP_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Pos (13UL) /*!< QSPI2_ENABLE (Bit 13) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk (0x2000UL) /*!< QSPI2_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Pos (11UL) /*!< QSPI2_DIV (Bit 11) */ + #define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Msk (0x1800UL) /*!< QSPI2_DIV (Bitfield-Mask: 0x03) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPIF_ENABLE_Pos (10UL) /*!< OQSPIF_ENABLE (Bit 10) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPIF_ENABLE_Msk (0x400UL) /*!< OQSPIF_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPIF_DIV_Pos (8UL) /*!< OQSPIF_DIV (Bit 8) */ + #define CRG_TOP_CLK_AMBA_REG_OQSPIF_DIV_Msk (0x300UL) /*!< OQSPIF_DIV (Bitfield-Mask: 0x03) */ + #define CRG_TOP_CLK_AMBA_REG_TDES_ENABLE_Pos (7UL) /*!< TDES_ENABLE (Bit 7) */ + #define CRG_TOP_CLK_AMBA_REG_TDES_ENABLE_Msk (0x80UL) /*!< TDES_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_PSK_CLK_ENABLE_Pos (6UL) /*!< PSK_CLK_ENABLE (Bit 6) */ + #define CRG_TOP_CLK_AMBA_REG_PSK_CLK_ENABLE_Msk (0x40UL) /*!< PSK_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL) /*!< HCLK_DIV (Bit 0) */ + #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL) /*!< HCLK_DIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CLK_CTRL_REG ====================================================== */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL_Pos (13UL) /*!< RUNNING_AT_PLL (Bit 13) */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL_Msk (0x2000UL) /*!< RUNNING_AT_PLL (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL40M_Pos (12UL) /*!< RUNNING_AT_XTAL40M (Bit 12) */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL40M_Msk (0x1000UL) /*!< RUNNING_AT_XTAL40M (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (11UL) /*!< RUNNING_AT_LP_CLK (Bit 11) */ + #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x800UL) /*!< RUNNING_AT_LP_CLK (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_CPU_ENABLE_Pos (10UL) /*!< PLL_CPU_ENABLE (Bit 10) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_CPU_ENABLE_Msk (0x400UL) /*!< PLL_CPU_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_PERI_ENABLE_Pos (9UL) /*!< PLL_PERI_ENABLE (Bit 9) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_PERI_ENABLE_Msk (0x200UL) /*!< PLL_PERI_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_SPI_ENABLE_Pos (8UL) /*!< PLL_SPI_ENABLE (Bit 8) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_SPI_ENABLE_Msk (0x100UL) /*!< PLL_SPI_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_AUX_ENABLE_Pos (7UL) /*!< PLL_AUX_ENABLE (Bit 7) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_AUX_ENABLE_Msk (0x80UL) /*!< PLL_AUX_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_SPI_CLK_SEL_Pos (5UL) /*!< PLL_SPI_CLK_SEL (Bit 5) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_SPI_CLK_SEL_Msk (0x60UL) /*!< PLL_SPI_CLK_SEL (Bitfield-Mask: 0x03) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_CLK_SEL_Pos (2UL) /*!< PLL_CLK_SEL (Bit 2) */ + #define CRG_TOP_CLK_CTRL_REG_PLL_CLK_SEL_Msk (0x1cUL) /*!< PLL_CLK_SEL (Bitfield-Mask: 0x07) */ + #define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL) /*!< SYS_CLK_SEL (Bit 0) */ + #define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL) /*!< SYS_CLK_SEL (Bitfield-Mask: 0x03) */ +/* ===================================================== PMU_CTRL_REG ====================================================== */ + #define CRG_TOP_PMU_CTRL_REG_MAC_SLEEP_Pos (1UL) /*!< MAC_SLEEP (Bit 1) */ + #define CRG_TOP_PMU_CTRL_REG_MAC_SLEEP_Msk (0x2UL) /*!< MAC_SLEEP (Bitfield-Mask: 0x01) */ + #define CRG_TOP_PMU_CTRL_REG_PHY_SLEEP_Pos (0UL) /*!< PHY_SLEEP (Bit 0) */ + #define CRG_TOP_PMU_CTRL_REG_PHY_SLEEP_Msk (0x1UL) /*!< PHY_SLEEP (Bitfield-Mask: 0x01) */ +/* ==================================================== RADIO_RESET_REG ==================================================== */ + #define CRG_TOP_RADIO_RESET_REG_SYSRST_RESET_REQ_Pos (7UL) /*!< SYSRST_RESET_REQ (Bit 7) */ + #define CRG_TOP_RADIO_RESET_REG_SYSRST_RESET_REQ_Msk (0x80UL) /*!< SYSRST_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_MACPI_HW_RESET_REQ_Pos (6UL) /*!< MACPI_HW_RESET_REQ (Bit 6) */ + #define CRG_TOP_RADIO_RESET_REG_MACPI_HW_RESET_REQ_Msk (0x40UL) /*!< MACPI_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_MACCORE_HW_RESET_REQ_Pos (5UL) /*!< MACCORE_HW_RESET_REQ (Bit 5) */ + #define CRG_TOP_RADIO_RESET_REG_MACCORE_HW_RESET_REQ_Msk (0x20UL) /*!< MACCORE_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_WT_HW_RESET_REQ_Pos (4UL) /*!< WT_HW_RESET_REQ (Bit 4) */ + #define CRG_TOP_RADIO_RESET_REG_WT_HW_RESET_REQ_Msk (0x10UL) /*!< WT_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_MPIF_HW_RESET_REQ_Pos (3UL) /*!< MPIF_HW_RESET_REQ (Bit 3) */ + #define CRG_TOP_RADIO_RESET_REG_MPIF_HW_RESET_REQ_Msk (0x8UL) /*!< MPIF_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_PHYCORE_HW_RESET_REQ_Pos (2UL) /*!< PHYCORE_HW_RESET_REQ (Bit 2) */ + #define CRG_TOP_RADIO_RESET_REG_PHYCORE_HW_RESET_REQ_Msk (0x4UL) /*!< PHYCORE_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_PHYREG_HW_RESET_REQ_Pos (1UL) /*!< PHYREG_HW_RESET_REQ (Bit 1) */ + #define CRG_TOP_RADIO_RESET_REG_PHYREG_HW_RESET_REQ_Msk (0x2UL) /*!< PHYREG_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RADIO_RESET_REG_PHYCORE_SW_RESET_REQ_Pos (0UL) /*!< PHYCORE_SW_RESET_REQ (Bit 0) */ + #define CRG_TOP_RADIO_RESET_REG_PHYCORE_SW_RESET_REQ_Msk (0x1UL) /*!< PHYCORE_SW_RESET_REQ (Bitfield-Mask: 0x01) */ +/* =================================================== RESET_FREEZE_REG ==================================================== */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_KDMA_Pos (12UL) /*!< FRZ_KDMA (Bit 12) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_KDMA_Msk (0x1000UL) /*!< FRZ_KDMA (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_DMA_Pos (11UL) /*!< FRZ_DMA (Bit 11) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_DMA_Msk (0x800UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (9UL) /*!< FRZ_SYS_WDOG (Bit 9) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x200UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM8_Pos (8UL) /*!< FRZ_SWTIM8 (Bit 8) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM8_Msk (0x100UL) /*!< FRZ_SWTIM8 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM7_Pos (7UL) /*!< FRZ_SWTIM7 (Bit 7) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM7_Msk (0x80UL) /*!< FRZ_SWTIM7 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM6_Pos (6UL) /*!< FRZ_SWTIM6 (Bit 6) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM6_Msk (0x40UL) /*!< FRZ_SWTIM6 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM5_Pos (5UL) /*!< FRZ_SWTIM5 (Bit 5) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM5_Msk (0x20UL) /*!< FRZ_SWTIM5 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (4UL) /*!< FRZ_SWTIM4 (Bit 4) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x10UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (3UL) /*!< FRZ_SWTIM3 (Bit 3) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x8UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (2UL) /*!< FRZ_SWTIM2 (Bit 2) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x4UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */ + #define CRG_TOP_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ +/* ==================================================== RESET_STAT_REG ===================================================== */ + #define CRG_TOP_RESET_STAT_REG_M33_WDOG_STAT_Pos (4UL) /*!< M33_WDOG_STAT (Bit 4) */ + #define CRG_TOP_RESET_STAT_REG_M33_WDOG_STAT_Msk (0x10UL) /*!< M33_WDOG_STAT (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (3UL) /*!< SWD_HWRESET_STAT (Bit 3) */ + #define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x8UL) /*!< SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL) /*!< SWRESET_STAT (Bit 2) */ + #define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL) /*!< SWRESET_STAT (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL) /*!< HWRESET_STAT (Bit 1) */ + #define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL) /*!< HWRESET_STAT (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL) /*!< PORESET_STAT (Bit 0) */ + #define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL) /*!< PORESET_STAT (Bitfield-Mask: 0x01) */ +/* ================================================== RETAIN_MEM_CTRL_REG ================================================== */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_DCACHE_RETAIN_Pos (7UL) /*!< DCACHE_RETAIN (Bit 7) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_DCACHE_RETAIN_Msk (0x80UL) /*!< DCACHE_RETAIN (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_CACHE_RETAIN_Pos (6UL) /*!< CACHE_RETAIN (Bit 6) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_CACHE_RETAIN_Msk (0x40UL) /*!< CACHE_RETAIN (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM3_PWR_CTRL_Pos (4UL) /*!< SYS_RAM3_PWR_CTRL (Bit 4) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM3_PWR_CTRL_Msk (0x30UL) /*!< SYS_RAM3_PWR_CTRL (Bitfield-Mask: 0x03) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM2_PWR_CTRL_Pos (2UL) /*!< SYS_RAM2_PWR_CTRL (Bit 2) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM2_PWR_CTRL_Msk (0xcUL) /*!< SYS_RAM2_PWR_CTRL (Bitfield-Mask: 0x03) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM1_PWR_CTRL_Pos (0UL) /*!< SYS_RAM1_PWR_CTRL (Bit 0) */ + #define CRG_TOP_RETAIN_MEM_CTRL_REG_SYS_RAM1_PWR_CTRL_Msk (0x3UL) /*!< SYS_RAM1_PWR_CTRL (Bitfield-Mask: 0x03) */ +/* ===================================================== RFMON_INT_REG ===================================================== */ + #define CRG_TOP_RFMON_INT_REG_CFG_RESET_Pos (1UL) /*!< CFG_RESET (Bit 1) */ + #define CRG_TOP_RFMON_INT_REG_CFG_RESET_Msk (0x2UL) /*!< CFG_RESET (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RFMON_INT_REG_CLK_ENABLE_Pos (0UL) /*!< CLK_ENABLE (Bit 0) */ + #define CRG_TOP_RFMON_INT_REG_CLK_ENABLE_Msk (0x1UL) /*!< CLK_ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== RST_CTRL_REG ====================================================== */ + #define CRG_TOP_RST_CTRL_REG_MEM_RESET_REQ_Pos (4UL) /*!< MEM_RESET_REQ (Bit 4) */ + #define CRG_TOP_RST_CTRL_REG_MEM_RESET_REQ_Msk (0x10UL) /*!< MEM_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RST_CTRL_REG_TIMER_RESET_REQ_Pos (3UL) /*!< TIMER_RESET_REQ (Bit 3) */ + #define CRG_TOP_RST_CTRL_REG_TIMER_RESET_REQ_Msk (0x8UL) /*!< TIMER_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RST_CTRL_REG_AUD_RESET_REQ_Pos (2UL) /*!< AUD_RESET_REQ (Bit 2) */ + #define CRG_TOP_RST_CTRL_REG_AUD_RESET_REQ_Msk (0x4UL) /*!< AUD_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RST_CTRL_REG_PERI_RESET_REQ_Pos (1UL) /*!< PERI_RESET_REQ (Bit 1) */ + #define CRG_TOP_RST_CTRL_REG_PERI_RESET_REQ_Msk (0x2UL) /*!< PERI_RESET_REQ (Bitfield-Mask: 0x01) */ + #define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Pos (0UL) /*!< SYS_CACHE_FLUSH_WITH_SW_RESET (Bit 0) */ + #define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Msk (0x1UL) /*!< SYS_CACHE_FLUSH_WITH_SW_RESET (Bitfield-Mask: 0x01) */ +/* ==================================================== SET_FREEZE_REG ===================================================== */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_KDMA_Pos (12UL) /*!< FRZ_KDMA (Bit 12) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_KDMA_Msk (0x1000UL) /*!< FRZ_KDMA (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_DMA_Pos (11UL) /*!< FRZ_DMA (Bit 11) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_DMA_Msk (0x800UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (9UL) /*!< FRZ_SYS_WDOG (Bit 9) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x200UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM8_Pos (8UL) /*!< FRZ_SWTIM8 (Bit 8) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM8_Msk (0x100UL) /*!< FRZ_SWTIM8 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM7_Pos (7UL) /*!< FRZ_SWTIM7 (Bit 7) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM7_Msk (0x80UL) /*!< FRZ_SWTIM7 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM6_Pos (6UL) /*!< FRZ_SWTIM6 (Bit 6) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM6_Msk (0x40UL) /*!< FRZ_SWTIM6 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM5_Pos (5UL) /*!< FRZ_SWTIM5 (Bit 5) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM5_Msk (0x20UL) /*!< FRZ_SWTIM5 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM4_Pos (4UL) /*!< FRZ_SWTIM4 (Bit 4) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x10UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM3_Pos (3UL) /*!< FRZ_SWTIM3 (Bit 3) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x8UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM2_Pos (2UL) /*!< FRZ_SWTIM2 (Bit 2) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x4UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */ + #define CRG_TOP_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ +/* ===================================================== SYS_CTRL_REG ====================================================== */ + #define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (7UL) /*!< SW_RESET (Bit 7) */ + #define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x80UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (6UL) /*!< CACHERAM_MUX (Bit 6) */ + #define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x40UL) /*!< CACHERAM_MUX (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos (5UL) /*!< DRA_OFF (Bit 5) */ + #define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk (0x20UL) /*!< DRA_OFF (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (4UL) /*!< DEBUGGER_ENABLE (Bit 4) */ + #define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x10UL) /*!< DEBUGGER_ENABLE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL) /*!< REMAP_INTVECT (Bit 3) */ + #define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL) /*!< REMAP_INTVECT (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL) /*!< REMAP_ADR0 (Bit 0) */ + #define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL) /*!< REMAP_ADR0 (Bitfield-Mask: 0x07) */ +/* ==================================================== SYS_STATUS_REG ===================================================== */ + #define CRG_TOP_SYS_STATUS_REG_DBG_IS_ACTIVE_Pos (6UL) /*!< DBG_IS_ACTIVE (Bit 6) */ + #define CRG_TOP_SYS_STATUS_REG_DBG_IS_ACTIVE_Msk (0x40UL) /*!< DBG_IS_ACTIVE (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_PHY_IS_UP_Pos (5UL) /*!< PHY_IS_UP (Bit 5) */ + #define CRG_TOP_SYS_STATUS_REG_PHY_IS_UP_Msk (0x20UL) /*!< PHY_IS_UP (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_PHY_IS_DOWN_Pos (4UL) /*!< PHY_IS_DOWN (Bit 4) */ + #define CRG_TOP_SYS_STATUS_REG_PHY_IS_DOWN_Msk (0x10UL) /*!< PHY_IS_DOWN (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_MAC_IS_UP_Pos (3UL) /*!< MAC_IS_UP (Bit 3) */ + #define CRG_TOP_SYS_STATUS_REG_MAC_IS_UP_Msk (0x8UL) /*!< MAC_IS_UP (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_MAC_IS_DOWN_Pos (2UL) /*!< MAC_IS_DOWN (Bit 2) */ + #define CRG_TOP_SYS_STATUS_REG_MAC_IS_DOWN_Msk (0x4UL) /*!< MAC_IS_DOWN (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_SYS_IS_UP_Pos (1UL) /*!< SYS_IS_UP (Bit 1) */ + #define CRG_TOP_SYS_STATUS_REG_SYS_IS_UP_Msk (0x2UL) /*!< SYS_IS_UP (Bitfield-Mask: 0x01) */ + #define CRG_TOP_SYS_STATUS_REG_SYS_IS_DOWN_Pos (0UL) /*!< SYS_IS_DOWN (Bit 0) */ + #define CRG_TOP_SYS_STATUS_REG_SYS_IS_DOWN_Msk (0x1UL) /*!< SYS_IS_DOWN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DAI ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== DAI_CONFIG_REG ===================================================== */ + #define DAI_DAI_CONFIG_REG_FRAME_LEN_Pos (2UL) /*!< FRAME_LEN (Bit 2) */ + #define DAI_DAI_CONFIG_REG_FRAME_LEN_Msk (0x1cUL) /*!< FRAME_LEN (Bitfield-Mask: 0x07) */ + #define DAI_DAI_CONFIG_REG_FORMAT_Pos (0UL) /*!< FORMAT (Bit 0) */ + #define DAI_DAI_CONFIG_REG_FORMAT_Msk (0x3UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ +/* ================================================= DAI_DATA_OUT_CTRL_REG ================================================= */ + #define DAI_DAI_DATA_OUT_CTRL_REG_TDM_EARLY_RLS_Pos (5UL) /*!< TDM_EARLY_RLS (Bit 5) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_TDM_EARLY_RLS_Msk (0x20UL) /*!< TDM_EARLY_RLS (Bitfield-Mask: 0x01) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_DATA_OUT_EN_Pos (3UL) /*!< DATA_OUT_EN (Bit 3) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_DATA_OUT_EN_Msk (0x18UL) /*!< DATA_OUT_EN (Bitfield-Mask: 0x03) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_WCLK_POL_Pos (1UL) /*!< WCLK_POL (Bit 1) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_WCLK_POL_Msk (0x2UL) /*!< WCLK_POL (Bitfield-Mask: 0x01) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_BCLK_POL_Pos (0UL) /*!< BCLK_POL (Bit 0) */ + #define DAI_DAI_DATA_OUT_CTRL_REG_BCLK_POL_Msk (0x1UL) /*!< BCLK_POL (Bitfield-Mask: 0x01) */ +/* ================================================= DAI_DATA_OUT_TEST_REG ================================================= */ + #define DAI_DAI_DATA_OUT_TEST_REG_DATA_OUT_POL_Pos (2UL) /*!< DATA_OUT_POL (Bit 2) */ + #define DAI_DAI_DATA_OUT_TEST_REG_DATA_OUT_POL_Msk (0x4UL) /*!< DATA_OUT_POL (Bitfield-Mask: 0x01) */ +/* ==================================================== DAI_ENABLE_REG ===================================================== */ + #define DAI_DAI_ENABLE_REG_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define DAI_DAI_ENABLE_REG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ===================================================== DAI_MODE_REG ====================================================== */ + #define DAI_DAI_MODE_REG_MODE_Pos (0UL) /*!< MODE (Bit 0) */ + #define DAI_DAI_MODE_REG_MODE_Msk (0x1UL) /*!< MODE (Bitfield-Mask: 0x01) */ +/* ================================================== DAI_OFFSET_LSB_REG =================================================== */ + #define DAI_DAI_OFFSET_LSB_REG_OFFSET_LSB_Pos (0UL) /*!< OFFSET_LSB (Bit 0) */ + #define DAI_DAI_OFFSET_LSB_REG_OFFSET_LSB_Msk (0xffUL) /*!< OFFSET_LSB (Bitfield-Mask: 0xff) */ +/* ================================================== DAI_OFFSET_MSB_REG =================================================== */ + #define DAI_DAI_OFFSET_MSB_REG_OFFSET_MSB_Pos (0UL) /*!< OFFSET_MSB (Bit 0) */ + #define DAI_DAI_OFFSET_MSB_REG_OFFSET_MSB_Msk (0xfUL) /*!< OFFSET_MSB (Bitfield-Mask: 0x0f) */ +/* ==================================================== DAI_RX1_CH_REG ===================================================== */ + #define DAI_DAI_RX1_CH_REG_RX1_CH_Pos (0UL) /*!< RX1_CH (Bit 0) */ + #define DAI_DAI_RX1_CH_REG_RX1_CH_Msk (0x3UL) /*!< RX1_CH (Bitfield-Mask: 0x03) */ +/* ====================================================== DAI_RX1_REG ====================================================== */ + #define DAI_DAI_RX1_REG_RX1_REG_Pos (0UL) /*!< RX1_REG (Bit 0) */ + #define DAI_DAI_RX1_REG_RX1_REG_Msk (0xffffffffUL) /*!< RX1_REG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DAI_RX2_CH_REG ===================================================== */ + #define DAI_DAI_RX2_CH_REG_RX2_CH_Pos (0UL) /*!< RX2_CH (Bit 0) */ + #define DAI_DAI_RX2_CH_REG_RX2_CH_Msk (0x3UL) /*!< RX2_CH (Bitfield-Mask: 0x03) */ +/* ====================================================== DAI_RX2_REG ====================================================== */ + #define DAI_DAI_RX2_REG_RX2_REG_Pos (0UL) /*!< RX2_REG (Bit 0) */ + #define DAI_DAI_RX2_REG_RX2_REG_Msk (0xffffffffUL) /*!< RX2_REG (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DAI_SLOT_CNT_REG ==================================================== */ + #define DAI_DAI_SLOT_CNT_REG_SLOT_CNT_Pos (0UL) /*!< SLOT_CNT (Bit 0) */ + #define DAI_DAI_SLOT_CNT_REG_SLOT_CNT_Msk (0x3UL) /*!< SLOT_CNT (Bitfield-Mask: 0x03) */ +/* =================================================== DAI_SR_CONFIG_REG =================================================== */ + #define DAI_DAI_SR_CONFIG_REG_DAI_SR_Pos (0UL) /*!< DAI_SR (Bit 0) */ + #define DAI_DAI_SR_CONFIG_REG_DAI_SR_Msk (0x1fUL) /*!< DAI_SR (Bitfield-Mask: 0x1f) */ +/* =================================================== DAI_SYNC_WIN_REG ==================================================== */ + #define DAI_DAI_SYNC_WIN_REG_SYNC_WIN_MODE_Pos (7UL) /*!< SYNC_WIN_MODE (Bit 7) */ + #define DAI_DAI_SYNC_WIN_REG_SYNC_WIN_MODE_Msk (0x80UL) /*!< SYNC_WIN_MODE (Bitfield-Mask: 0x01) */ + #define DAI_DAI_SYNC_WIN_REG_SYNC_WIN_WIDTH_Pos (0UL) /*!< SYNC_WIN_WIDTH (Bit 0) */ + #define DAI_DAI_SYNC_WIN_REG_SYNC_WIN_WIDTH_Msk (0x1fUL) /*!< SYNC_WIN_WIDTH (Bitfield-Mask: 0x1f) */ +/* ==================================================== DAI_TX1_CH_REG ===================================================== */ + #define DAI_DAI_TX1_CH_REG_TX1_CH_Pos (0UL) /*!< TX1_CH (Bit 0) */ + #define DAI_DAI_TX1_CH_REG_TX1_CH_Msk (0x3UL) /*!< TX1_CH (Bitfield-Mask: 0x03) */ +/* ====================================================== DAI_TX1_REG ====================================================== */ + #define DAI_DAI_TX1_REG_TX1_REG_Pos (0UL) /*!< TX1_REG (Bit 0) */ + #define DAI_DAI_TX1_REG_TX1_REG_Msk (0xffffffffUL) /*!< TX1_REG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DAI_TX2_CH_REG ===================================================== */ + #define DAI_DAI_TX2_CH_REG_TX2_CH_Pos (0UL) /*!< TX2_CH (Bit 0) */ + #define DAI_DAI_TX2_CH_REG_TX2_CH_Msk (0x3UL) /*!< TX2_CH (Bitfield-Mask: 0x03) */ +/* ====================================================== DAI_TX2_REG ====================================================== */ + #define DAI_DAI_TX2_REG_TX2_REG_Pos (0UL) /*!< TX2_REG (Bit 0) */ + #define DAI_DAI_TX2_REG_TX2_REG_Msk (0xffffffffUL) /*!< TX2_REG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DAI_TX_MUX_REG ===================================================== */ + #define DAI_DAI_TX_MUX_REG_DAI_TX2_SEL_Pos (1UL) /*!< DAI_TX2_SEL (Bit 1) */ + #define DAI_DAI_TX_MUX_REG_DAI_TX2_SEL_Msk (0x2UL) /*!< DAI_TX2_SEL (Bitfield-Mask: 0x01) */ + #define DAI_DAI_TX_MUX_REG_DAI_TX1_SEL_Pos (0UL) /*!< DAI_TX1_SEL (Bit 0) */ + #define DAI_DAI_TX_MUX_REG_DAI_TX1_SEL_Msk (0x1UL) /*!< DAI_TX1_SEL (Bitfield-Mask: 0x01) */ +/* ===================================================== DAI_W_LEN_REG ===================================================== */ + #define DAI_DAI_W_LEN_REG_W_LEN_Pos (0UL) /*!< W_LEN (Bit 0) */ + #define DAI_DAI_W_LEN_REG_W_LEN_Msk (0x3UL) /*!< W_LEN (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ DCACHE ================ */ +/* =========================================================================================================================== */ + +/* ================================================= DCACHE_BASE_ADDR_REG ================================================== */ + #define DCACHE_DCACHE_BASE_ADDR_REG_DCACHE_BASE_ADDR_Pos (0UL) /*!< DCACHE_BASE_ADDR (Bit 0) */ + #define DCACHE_DCACHE_BASE_ADDR_REG_DCACHE_BASE_ADDR_Msk (0x1ffffUL) /*!< DCACHE_BASE_ADDR (Bitfield-Mask: 0x1ffff) */ +/* ==================================================== DCACHE_CTRL_REG ==================================================== */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_DISABLE_CLKGATE_Pos (25UL) /*!< DCACHE_DISABLE_CLKGATE (Bit 25) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_DISABLE_CLKGATE_Msk (0x2000000UL) /*!< DCACHE_DISABLE_CLKGATE (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WBUFFER_FLUSH_Pos (24UL) /*!< DCACHE_WBUFFER_FLUSH (Bit 24) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WBUFFER_FLUSH_Msk (0x1000000UL) /*!< DCACHE_WBUFFER_FLUSH (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WBUFFER_EMPTY_Pos (23UL) /*!< DCACHE_WBUFFER_EMPTY (Bit 23) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WBUFFER_EMPTY_Msk (0x800000UL) /*!< DCACHE_WBUFFER_EMPTY (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WFLUSHED_Pos (22UL) /*!< DCACHE_WFLUSHED (Bit 22) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WFLUSHED_Msk (0x400000UL) /*!< DCACHE_WFLUSHED (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_READY_Pos (21UL) /*!< DCACHE_READY (Bit 21) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_READY_Msk (0x200000UL) /*!< DCACHE_READY (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WFLUSH_Pos (20UL) /*!< DCACHE_WFLUSH (Bit 20) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_WFLUSH_Msk (0x100000UL) /*!< DCACHE_WFLUSH (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_INIT_Pos (19UL) /*!< DCACHE_INIT (Bit 19) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_INIT_Msk (0x80000UL) /*!< DCACHE_INIT (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_ENABLE_Pos (18UL) /*!< DCACHE_ENABLE (Bit 18) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_ENABLE_Msk (0x40000UL) /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_LEN_Pos (0UL) /*!< DCACHE_LEN (Bit 0) */ + #define DCACHE_DCACHE_CTRL_REG_DCACHE_LEN_Msk (0x3ffffUL) /*!< DCACHE_LEN (Bitfield-Mask: 0x3ffff) */ +/* ================================================== DCACHE_MRM_CTRL_REG ================================================== */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_EVICTS_THRES_STATUS_Pos (5UL) /*!< MRM_IRQ_EVICTS_THRES_STATUS (Bit 5) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_EVICTS_THRES_STATUS_Msk (0x20UL) /*!< MRM_IRQ_EVICTS_THRES_STATUS (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bit 4) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bit 3) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL) /*!< MRM_IRQ_TINT_STATUS (Bit 2) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL) /*!< MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL) /*!< MRM_IRQ_MASK (Bit 1) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL) /*!< MRM_IRQ_MASK (Bitfield-Mask: 0x01) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_START_Pos (0UL) /*!< MRM_START (Bit 0) */ + #define DCACHE_DCACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL) /*!< MRM_START (Bitfield-Mask: 0x01) */ +/* ================================================= DCACHE_MRM_EVICTS_REG ================================================= */ + #define DCACHE_DCACHE_MRM_EVICTS_REG_MRM_EVICTS_Pos (0UL) /*!< MRM_EVICTS (Bit 0) */ + #define DCACHE_DCACHE_MRM_EVICTS_REG_MRM_EVICTS_Msk (0xffffffffUL) /*!< MRM_EVICTS (Bitfield-Mask: 0xffffffff) */ +/* ============================================== DCACHE_MRM_EVICTS_THRES_REG ============================================== */ + #define DCACHE_DCACHE_MRM_EVICTS_THRES_REG_MRM_EVICTS_THRES_Pos (0UL) /*!< MRM_EVICTS_THRES (Bit 0) */ + #define DCACHE_DCACHE_MRM_EVICTS_THRES_REG_MRM_EVICTS_THRES_Msk (0xffffffffUL) /*!< MRM_EVICTS_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DCACHE_MRM_HITS_REG ================================================== */ + #define DCACHE_DCACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL) /*!< MRM_HITS (Bit 0) */ + #define DCACHE_DCACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL) /*!< MRM_HITS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== DCACHE_MRM_HITS_THRES_REG =============================================== */ + #define DCACHE_DCACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL) /*!< MRM_HITS_THRES (Bit 0) */ + #define DCACHE_DCACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL) /*!< MRM_HITS_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DCACHE_MRM_MISSES_REG ================================================= */ + #define DCACHE_DCACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL) /*!< MRM_MISSES (Bit 0) */ + #define DCACHE_DCACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL) /*!< MRM_MISSES (Bitfield-Mask: 0xffffffff) */ +/* ============================================== DCACHE_MRM_MISSES_THRES_REG ============================================== */ + #define DCACHE_DCACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL) /*!< MRM_MISSES_THRES (Bit 0) */ + #define DCACHE_DCACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL) /*!< MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DCACHE_MRM_TINT_REG ================================================== */ + #define DCACHE_DCACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL) /*!< MRM_TINT (Bit 0) */ + #define DCACHE_DCACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL) /*!< MRM_TINT (Bitfield-Mask: 0x7ffff) */ + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* =================================================== DMA0_A_START_REG ==================================================== */ + #define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL) /*!< DMA0_A_START (Bit 0) */ + #define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL) /*!< DMA0_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA0_B_START_REG ==================================================== */ + #define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL) /*!< DMA0_B_START (Bit 0) */ + #define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL) /*!< DMA0_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA0_CTRL_REG ===================================================== */ + #define DMA_DMA0_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA0_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA0_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA0_IDX_REG ====================================================== */ + #define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL) /*!< DMA0_IDX (Bit 0) */ + #define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL) /*!< DMA0_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA0_INT_REG ====================================================== */ + #define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL) /*!< DMA0_INT (Bit 0) */ + #define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL) /*!< DMA0_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA0_LEN_REG ====================================================== */ + #define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL) /*!< DMA0_LEN (Bit 0) */ + #define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL) /*!< DMA0_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA10_A_START_REG =================================================== */ + #define DMA_DMA10_A_START_REG_DMA10_A_START_Pos (0UL) /*!< DMA10_A_START (Bit 0) */ + #define DMA_DMA10_A_START_REG_DMA10_A_START_Msk (0xffffffffUL) /*!< DMA10_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA10_B_START_REG =================================================== */ + #define DMA_DMA10_B_START_REG_DMA10_B_START_Pos (0UL) /*!< DMA10_B_START (Bit 0) */ + #define DMA_DMA10_B_START_REG_DMA10_B_START_Msk (0xffffffffUL) /*!< DMA10_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA10_CTRL_REG ===================================================== */ + #define DMA_DMA10_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA10_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA10_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA10_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA10_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA10_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA10_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA10_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA10_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA10_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA10_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA10_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA10_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA10_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA10_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA10_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA10_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA10_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA10_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA10_IDX_REG ===================================================== */ + #define DMA_DMA10_IDX_REG_DMA10_IDX_Pos (0UL) /*!< DMA10_IDX (Bit 0) */ + #define DMA_DMA10_IDX_REG_DMA10_IDX_Msk (0xffffUL) /*!< DMA10_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA10_INT_REG ===================================================== */ + #define DMA_DMA10_INT_REG_DMA10_INT_Pos (0UL) /*!< DMA10_INT (Bit 0) */ + #define DMA_DMA10_INT_REG_DMA10_INT_Msk (0xffffUL) /*!< DMA10_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA10_LEN_REG ===================================================== */ + #define DMA_DMA10_LEN_REG_DMA10_LEN_Pos (0UL) /*!< DMA10_LEN (Bit 0) */ + #define DMA_DMA10_LEN_REG_DMA10_LEN_Msk (0xffffUL) /*!< DMA10_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA11_A_START_REG =================================================== */ + #define DMA_DMA11_A_START_REG_DMA11_A_START_Pos (0UL) /*!< DMA11_A_START (Bit 0) */ + #define DMA_DMA11_A_START_REG_DMA11_A_START_Msk (0xffffffffUL) /*!< DMA11_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA11_B_START_REG =================================================== */ + #define DMA_DMA11_B_START_REG_DMA11_B_START_Pos (0UL) /*!< DMA11_B_START (Bit 0) */ + #define DMA_DMA11_B_START_REG_DMA11_B_START_Msk (0xffffffffUL) /*!< DMA11_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA11_CTRL_REG ===================================================== */ + #define DMA_DMA11_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA11_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA11_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA11_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA11_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA11_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA11_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA11_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA11_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA11_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA11_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA11_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA11_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA11_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA11_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA11_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA11_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA11_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA11_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA11_IDX_REG ===================================================== */ + #define DMA_DMA11_IDX_REG_DMA11_IDX_Pos (0UL) /*!< DMA11_IDX (Bit 0) */ + #define DMA_DMA11_IDX_REG_DMA11_IDX_Msk (0xffffUL) /*!< DMA11_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA11_INT_REG ===================================================== */ + #define DMA_DMA11_INT_REG_DMA11_INT_Pos (0UL) /*!< DMA11_INT (Bit 0) */ + #define DMA_DMA11_INT_REG_DMA11_INT_Msk (0xffffUL) /*!< DMA11_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA11_LEN_REG ===================================================== */ + #define DMA_DMA11_LEN_REG_DMA11_LEN_Pos (0UL) /*!< DMA11_LEN (Bit 0) */ + #define DMA_DMA11_LEN_REG_DMA11_LEN_Msk (0xffffUL) /*!< DMA11_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA12_A_START_REG =================================================== */ + #define DMA_DMA12_A_START_REG_DMA12_A_START_Pos (0UL) /*!< DMA12_A_START (Bit 0) */ + #define DMA_DMA12_A_START_REG_DMA12_A_START_Msk (0xffffffffUL) /*!< DMA12_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA12_B_START_REG =================================================== */ + #define DMA_DMA12_B_START_REG_DMA12_B_START_Pos (0UL) /*!< DMA12_B_START (Bit 0) */ + #define DMA_DMA12_B_START_REG_DMA12_B_START_Msk (0xffffffffUL) /*!< DMA12_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA12_CTRL_REG ===================================================== */ + #define DMA_DMA12_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA12_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA12_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA12_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA12_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA12_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA12_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA12_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA12_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA12_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA12_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA12_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA12_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA12_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA12_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA12_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA12_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA12_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA12_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA12_IDX_REG ===================================================== */ + #define DMA_DMA12_IDX_REG_DMA12_IDX_Pos (0UL) /*!< DMA12_IDX (Bit 0) */ + #define DMA_DMA12_IDX_REG_DMA12_IDX_Msk (0xffffUL) /*!< DMA12_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA12_INT_REG ===================================================== */ + #define DMA_DMA12_INT_REG_DMA12_INT_Pos (0UL) /*!< DMA12_INT (Bit 0) */ + #define DMA_DMA12_INT_REG_DMA12_INT_Msk (0xffffUL) /*!< DMA12_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA12_LEN_REG ===================================================== */ + #define DMA_DMA12_LEN_REG_DMA12_LEN_Pos (0UL) /*!< DMA12_LEN (Bit 0) */ + #define DMA_DMA12_LEN_REG_DMA12_LEN_Msk (0xffffUL) /*!< DMA12_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA13_A_START_REG =================================================== */ + #define DMA_DMA13_A_START_REG_DMA13_A_START_Pos (0UL) /*!< DMA13_A_START (Bit 0) */ + #define DMA_DMA13_A_START_REG_DMA13_A_START_Msk (0xffffffffUL) /*!< DMA13_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA13_B_START_REG =================================================== */ + #define DMA_DMA13_B_START_REG_DMA13_B_START_Pos (0UL) /*!< DMA13_B_START (Bit 0) */ + #define DMA_DMA13_B_START_REG_DMA13_B_START_Msk (0xffffffffUL) /*!< DMA13_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA13_CTRL_REG ===================================================== */ + #define DMA_DMA13_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA13_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA13_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA13_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA13_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA13_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA13_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA13_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA13_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA13_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA13_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA13_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA13_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA13_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA13_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA13_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA13_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA13_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA13_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA13_IDX_REG ===================================================== */ + #define DMA_DMA13_IDX_REG_DMA13_IDX_Pos (0UL) /*!< DMA13_IDX (Bit 0) */ + #define DMA_DMA13_IDX_REG_DMA13_IDX_Msk (0xffffUL) /*!< DMA13_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA13_INT_REG ===================================================== */ + #define DMA_DMA13_INT_REG_DMA13_INT_Pos (0UL) /*!< DMA13_INT (Bit 0) */ + #define DMA_DMA13_INT_REG_DMA13_INT_Msk (0xffffUL) /*!< DMA13_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA13_LEN_REG ===================================================== */ + #define DMA_DMA13_LEN_REG_DMA13_LEN_Pos (0UL) /*!< DMA13_LEN (Bit 0) */ + #define DMA_DMA13_LEN_REG_DMA13_LEN_Msk (0xffffUL) /*!< DMA13_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA14_A_START_REG =================================================== */ + #define DMA_DMA14_A_START_REG_DMA14_A_START_Pos (0UL) /*!< DMA14_A_START (Bit 0) */ + #define DMA_DMA14_A_START_REG_DMA14_A_START_Msk (0xffffffffUL) /*!< DMA14_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA14_B_START_REG =================================================== */ + #define DMA_DMA14_B_START_REG_DMA14_B_START_Pos (0UL) /*!< DMA14_B_START (Bit 0) */ + #define DMA_DMA14_B_START_REG_DMA14_B_START_Msk (0xffffffffUL) /*!< DMA14_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA14_CTRL_REG ===================================================== */ + #define DMA_DMA14_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA14_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA14_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA14_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA14_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA14_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA14_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA14_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA14_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA14_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA14_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA14_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA14_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA14_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA14_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA14_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA14_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA14_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA14_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA14_IDX_REG ===================================================== */ + #define DMA_DMA14_IDX_REG_DMA14_IDX_Pos (0UL) /*!< DMA14_IDX (Bit 0) */ + #define DMA_DMA14_IDX_REG_DMA14_IDX_Msk (0xffffUL) /*!< DMA14_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA14_INT_REG ===================================================== */ + #define DMA_DMA14_INT_REG_DMA14_INT_Pos (0UL) /*!< DMA14_INT (Bit 0) */ + #define DMA_DMA14_INT_REG_DMA14_INT_Msk (0xffffUL) /*!< DMA14_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA14_LEN_REG ===================================================== */ + #define DMA_DMA14_LEN_REG_DMA14_LEN_Pos (0UL) /*!< DMA14_LEN (Bit 0) */ + #define DMA_DMA14_LEN_REG_DMA14_LEN_Msk (0xffffUL) /*!< DMA14_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA15_A_START_REG =================================================== */ + #define DMA_DMA15_A_START_REG_DMA15_A_START_Pos (0UL) /*!< DMA15_A_START (Bit 0) */ + #define DMA_DMA15_A_START_REG_DMA15_A_START_Msk (0xffffffffUL) /*!< DMA15_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA15_B_START_REG =================================================== */ + #define DMA_DMA15_B_START_REG_DMA15_B_START_Pos (0UL) /*!< DMA15_B_START (Bit 0) */ + #define DMA_DMA15_B_START_REG_DMA15_B_START_Msk (0xffffffffUL) /*!< DMA15_B_START (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DMA15_CTRL_REG ===================================================== */ + #define DMA_DMA15_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA15_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA15_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA15_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA15_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA15_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA15_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA15_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA15_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA15_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA15_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA15_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA15_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA15_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA15_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA15_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA15_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA15_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA15_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA15_IDX_REG ===================================================== */ + #define DMA_DMA15_IDX_REG_DMA15_IDX_Pos (0UL) /*!< DMA15_IDX (Bit 0) */ + #define DMA_DMA15_IDX_REG_DMA15_IDX_Msk (0xffffUL) /*!< DMA15_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA15_INT_REG ===================================================== */ + #define DMA_DMA15_INT_REG_DMA15_INT_Pos (0UL) /*!< DMA15_INT (Bit 0) */ + #define DMA_DMA15_INT_REG_DMA15_INT_Msk (0xffffUL) /*!< DMA15_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA15_LEN_REG ===================================================== */ + #define DMA_DMA15_LEN_REG_DMA15_LEN_Pos (0UL) /*!< DMA15_LEN (Bit 0) */ + #define DMA_DMA15_LEN_REG_DMA15_LEN_Msk (0xffffUL) /*!< DMA15_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA1_A_START_REG ==================================================== */ + #define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL) /*!< DMA1_A_START (Bit 0) */ + #define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL) /*!< DMA1_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA1_B_START_REG ==================================================== */ + #define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL) /*!< DMA1_B_START (Bit 0) */ + #define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL) /*!< DMA1_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA1_CTRL_REG ===================================================== */ + #define DMA_DMA1_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA1_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA1_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA1_IDX_REG ====================================================== */ + #define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL) /*!< DMA1_IDX (Bit 0) */ + #define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL) /*!< DMA1_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA1_INT_REG ====================================================== */ + #define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL) /*!< DMA1_INT (Bit 0) */ + #define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL) /*!< DMA1_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA1_LEN_REG ====================================================== */ + #define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL) /*!< DMA1_LEN (Bit 0) */ + #define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL) /*!< DMA1_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA2_A_START_REG ==================================================== */ + #define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL) /*!< DMA2_A_START (Bit 0) */ + #define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL) /*!< DMA2_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA2_B_START_REG ==================================================== */ + #define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL) /*!< DMA2_B_START (Bit 0) */ + #define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL) /*!< DMA2_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA2_CTRL_REG ===================================================== */ + #define DMA_DMA2_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA2_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA2_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA2_IDX_REG ====================================================== */ + #define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL) /*!< DMA2_IDX (Bit 0) */ + #define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL) /*!< DMA2_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA2_INT_REG ====================================================== */ + #define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL) /*!< DMA2_INT (Bit 0) */ + #define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL) /*!< DMA2_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA2_LEN_REG ====================================================== */ + #define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL) /*!< DMA2_LEN (Bit 0) */ + #define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL) /*!< DMA2_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA3_A_START_REG ==================================================== */ + #define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL) /*!< DMA3_A_START (Bit 0) */ + #define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL) /*!< DMA3_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA3_B_START_REG ==================================================== */ + #define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL) /*!< DMA3_B_START (Bit 0) */ + #define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL) /*!< DMA3_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA3_CTRL_REG ===================================================== */ + #define DMA_DMA3_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA3_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA3_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA3_IDX_REG ====================================================== */ + #define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL) /*!< DMA3_IDX (Bit 0) */ + #define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL) /*!< DMA3_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA3_INT_REG ====================================================== */ + #define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL) /*!< DMA3_INT (Bit 0) */ + #define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL) /*!< DMA3_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA3_LEN_REG ====================================================== */ + #define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL) /*!< DMA3_LEN (Bit 0) */ + #define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL) /*!< DMA3_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA4_A_START_REG ==================================================== */ + #define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL) /*!< DMA4_A_START (Bit 0) */ + #define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL) /*!< DMA4_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA4_B_START_REG ==================================================== */ + #define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL) /*!< DMA4_B_START (Bit 0) */ + #define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL) /*!< DMA4_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA4_CTRL_REG ===================================================== */ + #define DMA_DMA4_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA4_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA4_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA4_IDX_REG ====================================================== */ + #define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL) /*!< DMA4_IDX (Bit 0) */ + #define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL) /*!< DMA4_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA4_INT_REG ====================================================== */ + #define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL) /*!< DMA4_INT (Bit 0) */ + #define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL) /*!< DMA4_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA4_LEN_REG ====================================================== */ + #define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL) /*!< DMA4_LEN (Bit 0) */ + #define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL) /*!< DMA4_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA5_A_START_REG ==================================================== */ + #define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL) /*!< DMA5_A_START (Bit 0) */ + #define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL) /*!< DMA5_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA5_B_START_REG ==================================================== */ + #define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL) /*!< DMA5_B_START (Bit 0) */ + #define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL) /*!< DMA5_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA5_CTRL_REG ===================================================== */ + #define DMA_DMA5_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA5_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA5_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA5_IDX_REG ====================================================== */ + #define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL) /*!< DMA5_IDX (Bit 0) */ + #define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL) /*!< DMA5_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA5_INT_REG ====================================================== */ + #define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL) /*!< DMA5_INT (Bit 0) */ + #define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL) /*!< DMA5_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA5_LEN_REG ====================================================== */ + #define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL) /*!< DMA5_LEN (Bit 0) */ + #define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL) /*!< DMA5_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA6_A_START_REG ==================================================== */ + #define DMA_DMA6_A_START_REG_DMA6_A_START_Pos (0UL) /*!< DMA6_A_START (Bit 0) */ + #define DMA_DMA6_A_START_REG_DMA6_A_START_Msk (0xffffffffUL) /*!< DMA6_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA6_B_START_REG ==================================================== */ + #define DMA_DMA6_B_START_REG_DMA6_B_START_Pos (0UL) /*!< DMA6_B_START (Bit 0) */ + #define DMA_DMA6_B_START_REG_DMA6_B_START_Msk (0xffffffffUL) /*!< DMA6_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA6_CTRL_REG ===================================================== */ + #define DMA_DMA6_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA6_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA6_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA6_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA6_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA6_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA6_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA6_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA6_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA6_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA6_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA6_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA6_IDX_REG ====================================================== */ + #define DMA_DMA6_IDX_REG_DMA6_IDX_Pos (0UL) /*!< DMA6_IDX (Bit 0) */ + #define DMA_DMA6_IDX_REG_DMA6_IDX_Msk (0xffffUL) /*!< DMA6_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA6_INT_REG ====================================================== */ + #define DMA_DMA6_INT_REG_DMA6_INT_Pos (0UL) /*!< DMA6_INT (Bit 0) */ + #define DMA_DMA6_INT_REG_DMA6_INT_Msk (0xffffUL) /*!< DMA6_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA6_LEN_REG ====================================================== */ + #define DMA_DMA6_LEN_REG_DMA6_LEN_Pos (0UL) /*!< DMA6_LEN (Bit 0) */ + #define DMA_DMA6_LEN_REG_DMA6_LEN_Msk (0xffffUL) /*!< DMA6_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA7_A_START_REG ==================================================== */ + #define DMA_DMA7_A_START_REG_DMA7_A_START_Pos (0UL) /*!< DMA7_A_START (Bit 0) */ + #define DMA_DMA7_A_START_REG_DMA7_A_START_Msk (0xffffffffUL) /*!< DMA7_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA7_B_START_REG ==================================================== */ + #define DMA_DMA7_B_START_REG_DMA7_B_START_Pos (0UL) /*!< DMA7_B_START (Bit 0) */ + #define DMA_DMA7_B_START_REG_DMA7_B_START_Msk (0xffffffffUL) /*!< DMA7_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA7_CTRL_REG ===================================================== */ + #define DMA_DMA7_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA7_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA7_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA7_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA7_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA7_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA7_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA7_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA7_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA7_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA7_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA7_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA7_IDX_REG ====================================================== */ + #define DMA_DMA7_IDX_REG_DMA7_IDX_Pos (0UL) /*!< DMA7_IDX (Bit 0) */ + #define DMA_DMA7_IDX_REG_DMA7_IDX_Msk (0xffffUL) /*!< DMA7_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA7_INT_REG ====================================================== */ + #define DMA_DMA7_INT_REG_DMA7_INT_Pos (0UL) /*!< DMA7_INT (Bit 0) */ + #define DMA_DMA7_INT_REG_DMA7_INT_Msk (0xffffUL) /*!< DMA7_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA7_LEN_REG ====================================================== */ + #define DMA_DMA7_LEN_REG_DMA7_LEN_Pos (0UL) /*!< DMA7_LEN (Bit 0) */ + #define DMA_DMA7_LEN_REG_DMA7_LEN_Msk (0xffffUL) /*!< DMA7_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA8_A_START_REG ==================================================== */ + #define DMA_DMA8_A_START_REG_DMA8_A_START_Pos (0UL) /*!< DMA8_A_START (Bit 0) */ + #define DMA_DMA8_A_START_REG_DMA8_A_START_Msk (0xffffffffUL) /*!< DMA8_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA8_B_START_REG ==================================================== */ + #define DMA_DMA8_B_START_REG_DMA8_B_START_Pos (0UL) /*!< DMA8_B_START (Bit 0) */ + #define DMA_DMA8_B_START_REG_DMA8_B_START_Msk (0xffffffffUL) /*!< DMA8_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA8_CTRL_REG ===================================================== */ + #define DMA_DMA8_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA8_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA8_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA8_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA8_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA8_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA8_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA8_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA8_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA8_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA8_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA8_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA8_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA8_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA8_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA8_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA8_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA8_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA8_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA8_IDX_REG ====================================================== */ + #define DMA_DMA8_IDX_REG_DMA8_IDX_Pos (0UL) /*!< DMA8_IDX (Bit 0) */ + #define DMA_DMA8_IDX_REG_DMA8_IDX_Msk (0xffffUL) /*!< DMA8_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA8_INT_REG ====================================================== */ + #define DMA_DMA8_INT_REG_DMA8_INT_Pos (0UL) /*!< DMA8_INT (Bit 0) */ + #define DMA_DMA8_INT_REG_DMA8_INT_Msk (0xffffUL) /*!< DMA8_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA8_LEN_REG ====================================================== */ + #define DMA_DMA8_LEN_REG_DMA8_LEN_Pos (0UL) /*!< DMA8_LEN (Bit 0) */ + #define DMA_DMA8_LEN_REG_DMA8_LEN_Msk (0xffffUL) /*!< DMA8_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA9_A_START_REG ==================================================== */ + #define DMA_DMA9_A_START_REG_DMA9_A_START_Pos (0UL) /*!< DMA9_A_START (Bit 0) */ + #define DMA_DMA9_A_START_REG_DMA9_A_START_Msk (0xffffffffUL) /*!< DMA9_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA9_B_START_REG ==================================================== */ + #define DMA_DMA9_B_START_REG_DMA9_B_START_Pos (0UL) /*!< DMA9_B_START (Bit 0) */ + #define DMA_DMA9_B_START_REG_DMA9_B_START_Msk (0xffffffffUL) /*!< DMA9_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA9_CTRL_REG ===================================================== */ + #define DMA_DMA9_CTRL_REG_ADDR_INC_Pos (16UL) /*!< ADDR_INC (Bit 16) */ + #define DMA_DMA9_CTRL_REG_ADDR_INC_Msk (0x70000UL) /*!< ADDR_INC (Bitfield-Mask: 0x07) */ + #define DMA_DMA9_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ + #define DMA_DMA9_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ + #define DMA_DMA9_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ + #define DMA_DMA9_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ + #define DMA_DMA9_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ + #define DMA_DMA9_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ + #define DMA_DMA9_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ + #define DMA_DMA9_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ + #define DMA_DMA9_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ + #define DMA_DMA9_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ + #define DMA_DMA9_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ + #define DMA_DMA9_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ + #define DMA_DMA9_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ + #define DMA_DMA9_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ + #define DMA_DMA9_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define DMA_DMA9_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ + #define DMA_DMA9_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA9_IDX_REG ====================================================== */ + #define DMA_DMA9_IDX_REG_DMA9_IDX_Pos (0UL) /*!< DMA9_IDX (Bit 0) */ + #define DMA_DMA9_IDX_REG_DMA9_IDX_Msk (0xffffUL) /*!< DMA9_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA9_INT_REG ====================================================== */ + #define DMA_DMA9_INT_REG_DMA9_INT_Pos (0UL) /*!< DMA9_INT (Bit 0) */ + #define DMA_DMA9_INT_REG_DMA9_INT_Msk (0xffffUL) /*!< DMA9_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA9_LEN_REG ====================================================== */ + #define DMA_DMA9_LEN_REG_DMA9_LEN_Pos (0UL) /*!< DMA9_LEN (Bit 0) */ + #define DMA_DMA9_LEN_REG_DMA9_LEN_Msk (0xffffUL) /*!< DMA9_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA_CLEAR_INT_REG =================================================== */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH15_Pos (15UL) /*!< DMA_RST_IRQ_CH15 (Bit 15) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH15_Msk (0x8000UL) /*!< DMA_RST_IRQ_CH15 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH14_Pos (14UL) /*!< DMA_RST_IRQ_CH14 (Bit 14) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH14_Msk (0x4000UL) /*!< DMA_RST_IRQ_CH14 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH13_Pos (13UL) /*!< DMA_RST_IRQ_CH13 (Bit 13) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH13_Msk (0x2000UL) /*!< DMA_RST_IRQ_CH13 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH12_Pos (12UL) /*!< DMA_RST_IRQ_CH12 (Bit 12) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH12_Msk (0x1000UL) /*!< DMA_RST_IRQ_CH12 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH11_Pos (11UL) /*!< DMA_RST_IRQ_CH11 (Bit 11) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH11_Msk (0x800UL) /*!< DMA_RST_IRQ_CH11 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH10_Pos (10UL) /*!< DMA_RST_IRQ_CH10 (Bit 10) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH10_Msk (0x400UL) /*!< DMA_RST_IRQ_CH10 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH9_Pos (9UL) /*!< DMA_RST_IRQ_CH9 (Bit 9) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH9_Msk (0x200UL) /*!< DMA_RST_IRQ_CH9 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH8_Pos (8UL) /*!< DMA_RST_IRQ_CH8 (Bit 8) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH8_Msk (0x100UL) /*!< DMA_RST_IRQ_CH8 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL) /*!< DMA_RST_IRQ_CH7 (Bit 7) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL) /*!< DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL) /*!< DMA_RST_IRQ_CH6 (Bit 6) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL) /*!< DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL) /*!< DMA_RST_IRQ_CH5 (Bit 5) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL) /*!< DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL) /*!< DMA_RST_IRQ_CH4 (Bit 4) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL) /*!< DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL) /*!< DMA_RST_IRQ_CH3 (Bit 3) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL) /*!< DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL) /*!< DMA_RST_IRQ_CH2 (Bit 2) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL) /*!< DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL) /*!< DMA_RST_IRQ_CH1 (Bit 1) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL) /*!< DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL) /*!< DMA_RST_IRQ_CH0 (Bit 0) */ + #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL) /*!< DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01) */ +/* =================================================== DMA_INT_MASK_REG ==================================================== */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE15_Pos (15UL) /*!< DMA_IRQ_ENABLE15 (Bit 15) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE15_Msk (0x8000UL) /*!< DMA_IRQ_ENABLE15 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE14_Pos (14UL) /*!< DMA_IRQ_ENABLE14 (Bit 14) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE14_Msk (0x4000UL) /*!< DMA_IRQ_ENABLE14 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE13_Pos (13UL) /*!< DMA_IRQ_ENABLE13 (Bit 13) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE13_Msk (0x2000UL) /*!< DMA_IRQ_ENABLE13 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE12_Pos (12UL) /*!< DMA_IRQ_ENABLE12 (Bit 12) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE12_Msk (0x1000UL) /*!< DMA_IRQ_ENABLE12 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE11_Pos (11UL) /*!< DMA_IRQ_ENABLE11 (Bit 11) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE11_Msk (0x800UL) /*!< DMA_IRQ_ENABLE11 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE10_Pos (10UL) /*!< DMA_IRQ_ENABLE10 (Bit 10) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE10_Msk (0x400UL) /*!< DMA_IRQ_ENABLE10 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE9_Pos (9UL) /*!< DMA_IRQ_ENABLE9 (Bit 9) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE9_Msk (0x200UL) /*!< DMA_IRQ_ENABLE9 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE8_Pos (8UL) /*!< DMA_IRQ_ENABLE8 (Bit 8) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE8_Msk (0x100UL) /*!< DMA_IRQ_ENABLE8 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Pos (7UL) /*!< DMA_IRQ_ENABLE7 (Bit 7) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Msk (0x80UL) /*!< DMA_IRQ_ENABLE7 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Pos (6UL) /*!< DMA_IRQ_ENABLE6 (Bit 6) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Msk (0x40UL) /*!< DMA_IRQ_ENABLE6 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL) /*!< DMA_IRQ_ENABLE5 (Bit 5) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL) /*!< DMA_IRQ_ENABLE5 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL) /*!< DMA_IRQ_ENABLE4 (Bit 4) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL) /*!< DMA_IRQ_ENABLE4 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL) /*!< DMA_IRQ_ENABLE3 (Bit 3) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL) /*!< DMA_IRQ_ENABLE3 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL) /*!< DMA_IRQ_ENABLE2 (Bit 2) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL) /*!< DMA_IRQ_ENABLE2 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL) /*!< DMA_IRQ_ENABLE1 (Bit 1) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL) /*!< DMA_IRQ_ENABLE1 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL) /*!< DMA_IRQ_ENABLE0 (Bit 0) */ + #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL) /*!< DMA_IRQ_ENABLE0 (Bitfield-Mask: 0x01) */ +/* ================================================== DMA_INT_STATUS_REG =================================================== */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR15_Pos (31UL) /*!< DMA_BUS_ERR15 (Bit 31) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR15_Msk (0x80000000UL) /*!< DMA_BUS_ERR15 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR14_Pos (30UL) /*!< DMA_BUS_ERR14 (Bit 30) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR14_Msk (0x40000000UL) /*!< DMA_BUS_ERR14 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR13_Pos (29UL) /*!< DMA_BUS_ERR13 (Bit 29) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR13_Msk (0x20000000UL) /*!< DMA_BUS_ERR13 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR12_Pos (28UL) /*!< DMA_BUS_ERR12 (Bit 28) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR12_Msk (0x10000000UL) /*!< DMA_BUS_ERR12 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR11_Pos (27UL) /*!< DMA_BUS_ERR11 (Bit 27) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR11_Msk (0x8000000UL) /*!< DMA_BUS_ERR11 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR10_Pos (26UL) /*!< DMA_BUS_ERR10 (Bit 26) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR10_Msk (0x4000000UL) /*!< DMA_BUS_ERR10 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR9_Pos (25UL) /*!< DMA_BUS_ERR9 (Bit 25) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR9_Msk (0x2000000UL) /*!< DMA_BUS_ERR9 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR8_Pos (24UL) /*!< DMA_BUS_ERR8 (Bit 24) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR8_Msk (0x1000000UL) /*!< DMA_BUS_ERR8 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Pos (23UL) /*!< DMA_BUS_ERR7 (Bit 23) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Msk (0x800000UL) /*!< DMA_BUS_ERR7 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Pos (22UL) /*!< DMA_BUS_ERR6 (Bit 22) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Msk (0x400000UL) /*!< DMA_BUS_ERR6 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (21UL) /*!< DMA_BUS_ERR5 (Bit 21) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x200000UL) /*!< DMA_BUS_ERR5 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (20UL) /*!< DMA_BUS_ERR4 (Bit 20) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x100000UL) /*!< DMA_BUS_ERR4 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (19UL) /*!< DMA_BUS_ERR3 (Bit 19) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x80000UL) /*!< DMA_BUS_ERR3 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (18UL) /*!< DMA_BUS_ERR2 (Bit 18) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x40000UL) /*!< DMA_BUS_ERR2 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (17UL) /*!< DMA_BUS_ERR1 (Bit 17) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x20000UL) /*!< DMA_BUS_ERR1 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (16UL) /*!< DMA_BUS_ERR0 (Bit 16) */ + #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x10000UL) /*!< DMA_BUS_ERR0 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH15_Pos (15UL) /*!< DMA_IRQ_CH15 (Bit 15) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH15_Msk (0x8000UL) /*!< DMA_IRQ_CH15 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH14_Pos (14UL) /*!< DMA_IRQ_CH14 (Bit 14) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH14_Msk (0x4000UL) /*!< DMA_IRQ_CH14 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH13_Pos (13UL) /*!< DMA_IRQ_CH13 (Bit 13) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH13_Msk (0x2000UL) /*!< DMA_IRQ_CH13 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH12_Pos (12UL) /*!< DMA_IRQ_CH12 (Bit 12) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH12_Msk (0x1000UL) /*!< DMA_IRQ_CH12 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH11_Pos (11UL) /*!< DMA_IRQ_CH11 (Bit 11) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH11_Msk (0x800UL) /*!< DMA_IRQ_CH11 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH10_Pos (10UL) /*!< DMA_IRQ_CH10 (Bit 10) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH10_Msk (0x400UL) /*!< DMA_IRQ_CH10 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH9_Pos (9UL) /*!< DMA_IRQ_CH9 (Bit 9) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH9_Msk (0x200UL) /*!< DMA_IRQ_CH9 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH8_Pos (8UL) /*!< DMA_IRQ_CH8 (Bit 8) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH8_Msk (0x100UL) /*!< DMA_IRQ_CH8 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL) /*!< DMA_IRQ_CH7 (Bit 7) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL) /*!< DMA_IRQ_CH7 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL) /*!< DMA_IRQ_CH6 (Bit 6) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL) /*!< DMA_IRQ_CH6 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL) /*!< DMA_IRQ_CH5 (Bit 5) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL) /*!< DMA_IRQ_CH5 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL) /*!< DMA_IRQ_CH4 (Bit 4) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL) /*!< DMA_IRQ_CH4 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL) /*!< DMA_IRQ_CH3 (Bit 3) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL) /*!< DMA_IRQ_CH3 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL) /*!< DMA_IRQ_CH2 (Bit 2) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL) /*!< DMA_IRQ_CH2 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL) /*!< DMA_IRQ_CH1 (Bit 1) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL) /*!< DMA_IRQ_CH1 (Bitfield-Mask: 0x01) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL) /*!< DMA_IRQ_CH0 (Bit 0) */ + #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL) /*!< DMA_IRQ_CH0 (Bitfield-Mask: 0x01) */ +/* =================================================== DMA_REQ_MUX2_REG ==================================================== */ + #define DMA_DMA_REQ_MUX2_REG_DMA7_SEL_Pos (24UL) /*!< DMA7_SEL (Bit 24) */ + #define DMA_DMA_REQ_MUX2_REG_DMA7_SEL_Msk (0x1f000000UL) /*!< DMA7_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX2_REG_DMA6_SEL_Pos (16UL) /*!< DMA6_SEL (Bit 16) */ + #define DMA_DMA_REQ_MUX2_REG_DMA6_SEL_Msk (0x1f0000UL) /*!< DMA6_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX2_REG_DMA5_SEL_Pos (8UL) /*!< DMA5_SEL (Bit 8) */ + #define DMA_DMA_REQ_MUX2_REG_DMA5_SEL_Msk (0x1f00UL) /*!< DMA5_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX2_REG_DMA4_SEL_Pos (0UL) /*!< DMA4_SEL (Bit 0) */ + #define DMA_DMA_REQ_MUX2_REG_DMA4_SEL_Msk (0x1fUL) /*!< DMA4_SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== DMA_REQ_MUX3_REG ==================================================== */ + #define DMA_DMA_REQ_MUX3_REG_DMA11_SEL_Pos (24UL) /*!< DMA11_SEL (Bit 24) */ + #define DMA_DMA_REQ_MUX3_REG_DMA11_SEL_Msk (0x1f000000UL) /*!< DMA11_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX3_REG_DMA10_SEL_Pos (16UL) /*!< DMA10_SEL (Bit 16) */ + #define DMA_DMA_REQ_MUX3_REG_DMA10_SEL_Msk (0x1f0000UL) /*!< DMA10_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX3_REG_DMA9_SEL_Pos (8UL) /*!< DMA9_SEL (Bit 8) */ + #define DMA_DMA_REQ_MUX3_REG_DMA9_SEL_Msk (0x1f00UL) /*!< DMA9_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX3_REG_DMA8_SEL_Pos (0UL) /*!< DMA8_SEL (Bit 0) */ + #define DMA_DMA_REQ_MUX3_REG_DMA8_SEL_Msk (0x1fUL) /*!< DMA8_SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== DMA_REQ_MUX4_REG ==================================================== */ + #define DMA_DMA_REQ_MUX4_REG_DMA15_SEL_Pos (24UL) /*!< DMA15_SEL (Bit 24) */ + #define DMA_DMA_REQ_MUX4_REG_DMA15_SEL_Msk (0x1f000000UL) /*!< DMA15_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX4_REG_DMA14_SEL_Pos (16UL) /*!< DMA14_SEL (Bit 16) */ + #define DMA_DMA_REQ_MUX4_REG_DMA14_SEL_Msk (0x1f0000UL) /*!< DMA14_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX4_REG_DMA13_SEL_Pos (8UL) /*!< DMA13_SEL (Bit 8) */ + #define DMA_DMA_REQ_MUX4_REG_DMA13_SEL_Msk (0x1f00UL) /*!< DMA13_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX4_REG_DMA12_SEL_Pos (0UL) /*!< DMA12_SEL (Bit 0) */ + #define DMA_DMA_REQ_MUX4_REG_DMA12_SEL_Msk (0x1fUL) /*!< DMA12_SEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== DMA_REQ_MUX_REG ==================================================== */ + #define DMA_DMA_REQ_MUX_REG_DMA3_SEL_Pos (24UL) /*!< DMA3_SEL (Bit 24) */ + #define DMA_DMA_REQ_MUX_REG_DMA3_SEL_Msk (0x1f000000UL) /*!< DMA3_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX_REG_DMA2_SEL_Pos (16UL) /*!< DMA2_SEL (Bit 16) */ + #define DMA_DMA_REQ_MUX_REG_DMA2_SEL_Msk (0x1f0000UL) /*!< DMA2_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX_REG_DMA1_SEL_Pos (8UL) /*!< DMA1_SEL (Bit 8) */ + #define DMA_DMA_REQ_MUX_REG_DMA1_SEL_Msk (0x1f00UL) /*!< DMA1_SEL (Bitfield-Mask: 0x1f) */ + #define DMA_DMA_REQ_MUX_REG_DMA0_SEL_Pos (0UL) /*!< DMA0_SEL (Bit 0) */ + #define DMA_DMA_REQ_MUX_REG_DMA0_SEL_Msk (0x1fUL) /*!< DMA0_SEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ FPLL ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== PLLD_CONFIG_REG ==================================================== */ + #define FPLL_PLLD_CONFIG_REG_OUTDIV_Pos (8UL) /*!< OUTDIV (Bit 8) */ + #define FPLL_PLLD_CONFIG_REG_OUTDIV_Msk (0x300UL) /*!< OUTDIV (Bitfield-Mask: 0x03) */ + #define FPLL_PLLD_CONFIG_REG_INDIV_Pos (5UL) /*!< INDIV (Bit 5) */ + #define FPLL_PLLD_CONFIG_REG_INDIV_Msk (0xe0UL) /*!< INDIV (Bitfield-Mask: 0x07) */ + #define FPLL_PLLD_CONFIG_REG_BIAS_HOLD_Pos (0UL) /*!< BIAS_HOLD (Bit 0) */ + #define FPLL_PLLD_CONFIG_REG_BIAS_HOLD_Msk (0x1UL) /*!< BIAS_HOLD (Bitfield-Mask: 0x01) */ +/* ===================================================== PLLD_CTRL_REG ===================================================== */ + #define FPLL_PLLD_CTRL_REG_FPLL_EN_Pos (5UL) /*!< FPLL_EN (Bit 5) */ + #define FPLL_PLLD_CTRL_REG_FPLL_EN_Msk (0x20UL) /*!< FPLL_EN (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_CTRL_REG_VCO_EN_Pos (4UL) /*!< VCO_EN (Bit 4) */ + #define FPLL_PLLD_CTRL_REG_VCO_EN_Msk (0x10UL) /*!< VCO_EN (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_CTRL_REG_PFD_CP_EN_Pos (3UL) /*!< PFD_CP_EN (Bit 3) */ + #define FPLL_PLLD_CTRL_REG_PFD_CP_EN_Msk (0x8UL) /*!< PFD_CP_EN (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_CTRL_REG_BYPASS_SEL_Pos (2UL) /*!< BYPASS_SEL (Bit 2) */ + #define FPLL_PLLD_CTRL_REG_BYPASS_SEL_Msk (0x4UL) /*!< BYPASS_SEL (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_CTRL_REG_CLKOUT_EN_Pos (1UL) /*!< CLKOUT_EN (Bit 1) */ + #define FPLL_PLLD_CTRL_REG_CLKOUT_EN_Msk (0x2UL) /*!< CLKOUT_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== PLLD_FBDIV_REG ===================================================== */ + #define FPLL_PLLD_FBDIV_REG_FBDIV_Pos (0UL) /*!< FBDIV (Bit 0) */ + #define FPLL_PLLD_FBDIV_REG_FBDIV_Msk (0xfffffUL) /*!< FBDIV (Bitfield-Mask: 0xfffff) */ +/* =================================================== PLLD_IRQ_CLR_REG ==================================================== */ + #define FPLL_PLLD_IRQ_CLR_REG_CLR_IRQ_PLL_LOCK_Pos (1UL) /*!< CLR_IRQ_PLL_LOCK (Bit 1) */ + #define FPLL_PLLD_IRQ_CLR_REG_CLR_IRQ_PLL_LOCK_Msk (0x2UL) /*!< CLR_IRQ_PLL_LOCK (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_IRQ_CLR_REG_CLR_IRQ_PLL_LOST_LOCK_Pos (0UL) /*!< CLR_IRQ_PLL_LOST_LOCK (Bit 0) */ + #define FPLL_PLLD_IRQ_CLR_REG_CLR_IRQ_PLL_LOST_LOCK_Msk (0x1UL) /*!< CLR_IRQ_PLL_LOST_LOCK (Bitfield-Mask: 0x01) */ +/* =================================================== PLLD_IRQ_MASK_REG =================================================== */ + #define FPLL_PLLD_IRQ_MASK_REG_MIRQ_PLL_LOCK_Pos (1UL) /*!< MIRQ_PLL_LOCK (Bit 1) */ + #define FPLL_PLLD_IRQ_MASK_REG_MIRQ_PLL_LOCK_Msk (0x2UL) /*!< MIRQ_PLL_LOCK (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_IRQ_MASK_REG_MIRQ_PLL_LOST_LOCK_Pos (0UL) /*!< MIRQ_PLL_LOST_LOCK (Bit 0) */ + #define FPLL_PLLD_IRQ_MASK_REG_MIRQ_PLL_LOST_LOCK_Msk (0x1UL) /*!< MIRQ_PLL_LOST_LOCK (Bitfield-Mask: 0x01) */ +/* ===================================================== PLLD_IRQ_REG ====================================================== */ + #define FPLL_PLLD_IRQ_REG_IRQ_PLL_LOCK_Pos (1UL) /*!< IRQ_PLL_LOCK (Bit 1) */ + #define FPLL_PLLD_IRQ_REG_IRQ_PLL_LOCK_Msk (0x2UL) /*!< IRQ_PLL_LOCK (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_IRQ_REG_IRQ_PLL_LOST_LOCK_Pos (0UL) /*!< IRQ_PLL_LOST_LOCK (Bit 0) */ + #define FPLL_PLLD_IRQ_REG_IRQ_PLL_LOST_LOCK_Msk (0x1UL) /*!< IRQ_PLL_LOST_LOCK (Bitfield-Mask: 0x01) */ +/* ==================================================== PLLD_STATUS_REG ==================================================== */ + #define FPLL_PLLD_STATUS_REG_STA_PLL_LOCK_Pos (2UL) /*!< STA_PLL_LOCK (Bit 2) */ + #define FPLL_PLLD_STATUS_REG_STA_PLL_LOCK_Msk (0x4UL) /*!< STA_PLL_LOCK (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_STATUS_REG_STA_RUNNING_AT_FPLL_Pos (1UL) /*!< STA_RUNNING_AT_FPLL (Bit 1) */ + #define FPLL_PLLD_STATUS_REG_STA_RUNNING_AT_FPLL_Msk (0x2UL) /*!< STA_RUNNING_AT_FPLL (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_STATUS_REG_STA_RUNNING_AT_XTAL40M_Pos (0UL) /*!< STA_RUNNING_AT_XTAL40M (Bit 0) */ + #define FPLL_PLLD_STATUS_REG_STA_RUNNING_AT_XTAL40M_Msk (0x1UL) /*!< STA_RUNNING_AT_XTAL40M (Bitfield-Mask: 0x01) */ +/* ===================================================== PLLD_TEST_REG ===================================================== */ + #define FPLL_PLLD_TEST_REG_CAL_EN_Pos (5UL) /*!< CAL_EN (Bit 5) */ + #define FPLL_PLLD_TEST_REG_CAL_EN_Msk (0x20UL) /*!< CAL_EN (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_TEST_REG_CP_BIAS_Pos (4UL) /*!< CP_BIAS (Bit 4) */ + #define FPLL_PLLD_TEST_REG_CP_BIAS_Msk (0x10UL) /*!< CP_BIAS (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_TEST_REG_ANA_TEST_SEL_Pos (3UL) /*!< ANA_TEST_SEL (Bit 3) */ + #define FPLL_PLLD_TEST_REG_ANA_TEST_SEL_Msk (0x8UL) /*!< ANA_TEST_SEL (Bitfield-Mask: 0x01) */ + #define FPLL_PLLD_TEST_REG_SDM_DITHER_Pos (1UL) /*!< SDM_DITHER (Bit 1) */ + #define FPLL_PLLD_TEST_REG_SDM_DITHER_Msk (0x6UL) /*!< SDM_DITHER (Bitfield-Mask: 0x03) */ + #define FPLL_PLLD_TEST_REG_SDM_ENABLE_Pos (0UL) /*!< SDM_ENABLE (Bit 0) */ + #define FPLL_PLLD_TEST_REG_SDM_ENABLE_Msk (0x1UL) /*!< SDM_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== PLLD_VCO_TRIM_REG =================================================== */ + #define FPLL_PLLD_VCO_TRIM_REG_CAL_VCO_Pos (0UL) /*!< CAL_VCO (Bit 0) */ + #define FPLL_PLLD_VCO_TRIM_REG_CAL_VCO_Msk (0xfUL) /*!< CAL_VCO (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BIST_CTRL_REG ===================================================== */ + #define GPIO_BIST_CTRL_REG_SHOW_BIST_Pos (7UL) /*!< SHOW_BIST (Bit 7) */ + #define GPIO_BIST_CTRL_REG_SHOW_BIST_Msk (0x80UL) /*!< SHOW_BIST (Bitfield-Mask: 0x01) */ + #define GPIO_BIST_CTRL_REG_ADDRESS_SCRAMBLING_Pos (6UL) /*!< ADDRESS_SCRAMBLING (Bit 6) */ + #define GPIO_BIST_CTRL_REG_ADDRESS_SCRAMBLING_Msk (0x40UL) /*!< ADDRESS_SCRAMBLING (Bitfield-Mask: 0x01) */ + #define GPIO_BIST_CTRL_REG_FAST_ADDRESS_Pos (5UL) /*!< FAST_ADDRESS (Bit 5) */ + #define GPIO_BIST_CTRL_REG_FAST_ADDRESS_Msk (0x20UL) /*!< FAST_ADDRESS (Bitfield-Mask: 0x01) */ + #define GPIO_BIST_CTRL_REG_RAMBIST_REPEAT_Pos (4UL) /*!< RAMBIST_REPEAT (Bit 4) */ + #define GPIO_BIST_CTRL_REG_RAMBIST_REPEAT_Msk (0x10UL) /*!< RAMBIST_REPEAT (Bitfield-Mask: 0x01) */ + #define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos (2UL) /*!< RAM_BIST_PATTERN (Bit 2) */ + #define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk (0xcUL) /*!< RAM_BIST_PATTERN (Bitfield-Mask: 0x03) */ + #define GPIO_BIST_CTRL_REG_BIST_CONFIG_Pos (0UL) /*!< BIST_CONFIG (Bit 0) */ + #define GPIO_BIST_CTRL_REG_BIST_CONFIG_Msk (0x3UL) /*!< BIST_CONFIG (Bitfield-Mask: 0x03) */ +/* ===================================================== EMMC_MODE_REG ===================================================== */ + #define GPIO_EMMC_MODE_REG_EMMC_PULL_SEL_Pos (20UL) /*!< EMMC_PULL_SEL (Bit 20) */ + #define GPIO_EMMC_MODE_REG_EMMC_PULL_SEL_Msk (0x3ff00000UL) /*!< EMMC_PULL_SEL (Bitfield-Mask: 0x3ff) */ + #define GPIO_EMMC_MODE_REG_EMMC_PULL_EN_Pos (8UL) /*!< EMMC_PULL_EN (Bit 8) */ + #define GPIO_EMMC_MODE_REG_EMMC_PULL_EN_Msk (0x3ff00UL) /*!< EMMC_PULL_EN (Bitfield-Mask: 0x3ff) */ + #define GPIO_EMMC_MODE_REG_EMMC_CLKIN_SEL_Pos (7UL) /*!< EMMC_CLKIN_SEL (Bit 7) */ + #define GPIO_EMMC_MODE_REG_EMMC_CLKIN_SEL_Msk (0x80UL) /*!< EMMC_CLKIN_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_WP_VAL_Pos (6UL) /*!< EMMC_WP_VAL (Bit 6) */ + #define GPIO_EMMC_MODE_REG_EMMC_WP_VAL_Msk (0x40UL) /*!< EMMC_WP_VAL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_CD_VAL_Pos (5UL) /*!< EMMC_CD_VAL (Bit 5) */ + #define GPIO_EMMC_MODE_REG_EMMC_CD_VAL_Msk (0x20UL) /*!< EMMC_CD_VAL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_WP_SEL_Pos (4UL) /*!< EMMC_WP_SEL (Bit 4) */ + #define GPIO_EMMC_MODE_REG_EMMC_WP_SEL_Msk (0x10UL) /*!< EMMC_WP_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_CD_SEL_Pos (3UL) /*!< EMMC_CD_SEL (Bit 3) */ + #define GPIO_EMMC_MODE_REG_EMMC_CD_SEL_Msk (0x8UL) /*!< EMMC_CD_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_OCTA_MODE_Pos (2UL) /*!< EMMC_OCTA_MODE (Bit 2) */ + #define GPIO_EMMC_MODE_REG_EMMC_OCTA_MODE_Msk (0x4UL) /*!< EMMC_OCTA_MODE (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_PORT_SEL_Pos (1UL) /*!< EMMC_PORT_SEL (Bit 1) */ + #define GPIO_EMMC_MODE_REG_EMMC_PORT_SEL_Msk (0x2UL) /*!< EMMC_PORT_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_EMMC_MODE_REG_EMMC_ENABLE_Pos (0UL) /*!< EMMC_ENABLE (Bit 0) */ + #define GPIO_EMMC_MODE_REG_EMMC_ENABLE_Msk (0x1UL) /*!< EMMC_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_CLK_SEL_REG ==================================================== */ + #define GPIO_GPIO_CLK_SEL_REG_MCLK_OUTPUT_EN_Pos (10UL) /*!< MCLK_OUTPUT_EN (Bit 10) */ + #define GPIO_GPIO_CLK_SEL_REG_MCLK_OUTPUT_EN_Msk (0x400UL) /*!< MCLK_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_DPLL480M_OUTPUT_EN_Pos (9UL) /*!< DPLL480M_OUTPUT_EN (Bit 9) */ + #define GPIO_GPIO_CLK_SEL_REG_DPLL480M_OUTPUT_EN_Msk (0x200UL) /*!< DPLL480M_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_FPLL98M_OUTPUT_EN_Pos (8UL) /*!< FPLL98M_OUTPUT_EN (Bit 8) */ + #define GPIO_GPIO_CLK_SEL_REG_FPLL98M_OUTPUT_EN_Msk (0x100UL) /*!< FPLL98M_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_OSC32K_OUTPUT_EN_Pos (7UL) /*!< OSC32K_OUTPUT_EN (Bit 7) */ + #define GPIO_GPIO_CLK_SEL_REG_OSC32K_OUTPUT_EN_Msk (0x80UL) /*!< OSC32K_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Pos (6UL) /*!< XTAL32K_OUTPUT_EN (Bit 6) */ + #define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Msk (0x40UL) /*!< XTAL32K_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_RC10M_OUTPUT_EN_Pos (5UL) /*!< RC10M_OUTPUT_EN (Bit 5) */ + #define GPIO_GPIO_CLK_SEL_REG_RC10M_OUTPUT_EN_Msk (0x20UL) /*!< RC10M_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_XTAL40M_OUTPUT_EN_Pos (4UL) /*!< XTAL40M_OUTPUT_EN (Bit 4) */ + #define GPIO_GPIO_CLK_SEL_REG_XTAL40M_OUTPUT_EN_Msk (0x10UL) /*!< XTAL40M_OUTPUT_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL) /*!< FUNC_CLOCK_EN (Bit 3) */ + #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL) /*!< FUNC_CLOCK_EN (Bitfield-Mask: 0x01) */ + #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL) /*!< FUNC_CLOCK_SEL (Bit 0) */ + #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL) /*!< FUNC_CLOCK_SEL (Bitfield-Mask: 0x07) */ +/* ================================================== GPIO_INT_CLR_P0_REG ================================================== */ + #define GPIO_GPIO_INT_CLR_P0_REG_GPIO_CLEAR_P0_Pos (0UL) /*!< GPIO_CLEAR_P0 (Bit 0) */ + #define GPIO_GPIO_INT_CLR_P0_REG_GPIO_CLEAR_P0_Msk (0x3fffUL) /*!< GPIO_CLEAR_P0 (Bitfield-Mask: 0x3fff) */ +/* ================================================== GPIO_INT_CLR_P1_REG ================================================== */ + #define GPIO_GPIO_INT_CLR_P1_REG_GPIO_CLEAR_P1_Pos (0UL) /*!< GPIO_CLEAR_P1 (Bit 0) */ + #define GPIO_GPIO_INT_CLR_P1_REG_GPIO_CLEAR_P1_Msk (0xffffUL) /*!< GPIO_CLEAR_P1 (Bitfield-Mask: 0xffff) */ +/* ================================================== GPIO_INT_POL_P0_REG ================================================== */ + #define GPIO_GPIO_INT_POL_P0_REG_GPIO_POL_P0_Pos (0UL) /*!< GPIO_POL_P0 (Bit 0) */ + #define GPIO_GPIO_INT_POL_P0_REG_GPIO_POL_P0_Msk (0x3fffUL) /*!< GPIO_POL_P0 (Bitfield-Mask: 0x3fff) */ +/* ================================================== GPIO_INT_POL_P1_REG ================================================== */ + #define GPIO_GPIO_INT_POL_P1_REG_GPIO_POL_P1_Pos (0UL) /*!< GPIO_POL_P1 (Bit 0) */ + #define GPIO_GPIO_INT_POL_P1_REG_GPIO_POL_P1_Msk (0xffffUL) /*!< GPIO_POL_P1 (Bitfield-Mask: 0xffff) */ +/* ================================================== GPIO_INT_SEL_P0_REG ================================================== */ + #define GPIO_GPIO_INT_SEL_P0_REG_GPIO_SELECT_P0_Pos (0UL) /*!< GPIO_SELECT_P0 (Bit 0) */ + #define GPIO_GPIO_INT_SEL_P0_REG_GPIO_SELECT_P0_Msk (0x3fffUL) /*!< GPIO_SELECT_P0 (Bitfield-Mask: 0x3fff) */ +/* ================================================== GPIO_INT_SEL_P1_REG ================================================== */ + #define GPIO_GPIO_INT_SEL_P1_REG_GPIO_SELECT_P1_Pos (0UL) /*!< GPIO_SELECT_P1 (Bit 0) */ + #define GPIO_GPIO_INT_SEL_P1_REG_GPIO_SELECT_P1_Msk (0xffffUL) /*!< GPIO_SELECT_P1 (Bitfield-Mask: 0xffff) */ +/* ================================================== GPIO_INT_STS_P0_REG ================================================== */ + #define GPIO_GPIO_INT_STS_P0_REG_GPIO_STAT_P0_Pos (0UL) /*!< GPIO_STAT_P0 (Bit 0) */ + #define GPIO_GPIO_INT_STS_P0_REG_GPIO_STAT_P0_Msk (0x3fffUL) /*!< GPIO_STAT_P0 (Bitfield-Mask: 0x3fff) */ +/* ================================================== GPIO_INT_STS_P1_REG ================================================== */ + #define GPIO_GPIO_INT_STS_P1_REG_GPIO_STAT_P1_Pos (0UL) /*!< GPIO_STAT_P1 (Bit 0) */ + #define GPIO_GPIO_INT_STS_P1_REG_GPIO_STAT_P1_Msk (0xffffUL) /*!< GPIO_STAT_P1 (Bitfield-Mask: 0xffff) */ +/* =================================================== GPIO_SEL1_P0_REG ==================================================== */ + #define GPIO_GPIO_SEL1_P0_REG_GPIO_SEL1_P0_Pos (0UL) /*!< GPIO_SEL1_P0 (Bit 0) */ + #define GPIO_GPIO_SEL1_P0_REG_GPIO_SEL1_P0_Msk (0x3fffUL) /*!< GPIO_SEL1_P0 (Bitfield-Mask: 0x3fff) */ +/* =================================================== GPIO_SEL1_P1_REG ==================================================== */ + #define GPIO_GPIO_SEL1_P1_REG_GPIO_SEL1_P1_Pos (0UL) /*!< GPIO_SEL1_P1 (Bit 0) */ + #define GPIO_GPIO_SEL1_P1_REG_GPIO_SEL1_P1_Msk (0xffffUL) /*!< GPIO_SEL1_P1 (Bitfield-Mask: 0xffff) */ +/* ==================================================== GPIO_SEL_P0_REG ==================================================== */ + #define GPIO_GPIO_SEL_P0_REG_GPIO_SEL_P0_Pos (0UL) /*!< GPIO_SEL_P0 (Bit 0) */ + #define GPIO_GPIO_SEL_P0_REG_GPIO_SEL_P0_Msk (0x3fffUL) /*!< GPIO_SEL_P0 (Bitfield-Mask: 0x3fff) */ +/* ==================================================== GPIO_SEL_P1_REG ==================================================== */ + #define GPIO_GPIO_SEL_P1_REG_GPIO_SEL_P1_Pos (0UL) /*!< GPIO_SEL_P1 (Bit 0) */ + #define GPIO_GPIO_SEL_P1_REG_GPIO_SEL_P1_Msk (0xffffUL) /*!< GPIO_SEL_P1 (Bitfield-Mask: 0xffff) */ +/* ==================================================== P0_00_MODE_REG ===================================================== */ + #define GPIO_P0_00_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_00_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_00_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_00_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_00_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_00_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_00_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_00_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_00_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_01_MODE_REG ===================================================== */ + #define GPIO_P0_01_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_01_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_01_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_01_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_01_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_01_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_01_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_01_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_01_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_02_MODE_REG ===================================================== */ + #define GPIO_P0_02_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_02_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_02_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_02_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_02_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_02_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_02_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_02_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_02_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_03_MODE_REG ===================================================== */ + #define GPIO_P0_03_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_03_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_03_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_03_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_03_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_03_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_03_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_03_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_03_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_04_MODE_REG ===================================================== */ + #define GPIO_P0_04_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_04_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_04_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_04_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_04_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_04_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_04_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_04_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_04_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_05_MODE_REG ===================================================== */ + #define GPIO_P0_05_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_05_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_05_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_05_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_05_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_05_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_05_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_05_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_05_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_06_MODE_REG ===================================================== */ + #define GPIO_P0_06_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_06_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_06_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_06_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_06_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_06_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_06_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_06_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_06_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_07_MODE_REG ===================================================== */ + #define GPIO_P0_07_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_07_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_07_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_07_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_07_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_07_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_07_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_07_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_07_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_08_MODE_REG ===================================================== */ + #define GPIO_P0_08_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_08_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_08_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_08_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_08_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_08_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_08_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_08_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_08_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_09_MODE_REG ===================================================== */ + #define GPIO_P0_09_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_09_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_09_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_09_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_09_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_09_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_09_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_09_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_09_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_10_MODE_REG ===================================================== */ + #define GPIO_P0_10_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_10_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_10_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_10_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_10_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_10_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_10_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_10_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_10_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_11_MODE_REG ===================================================== */ + #define GPIO_P0_11_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_11_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_11_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_11_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_11_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_11_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_11_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_11_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_11_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_12_MODE_REG ===================================================== */ + #define GPIO_P0_12_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_12_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_12_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_12_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_12_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_12_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_12_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_12_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_12_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P0_13_MODE_REG ===================================================== */ + #define GPIO_P0_13_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P0_13_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P0_13_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P0_13_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P0_13_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P0_13_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P0_13_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P0_13_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P0_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P0_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P0_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P0_13_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ====================================================== P0_DATA_REG ====================================================== */ + #define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL) /*!< P0_DATA (Bit 0) */ + #define GPIO_P0_DATA_REG_P0_DATA_Msk (0x3fffUL) /*!< P0_DATA (Bitfield-Mask: 0x3fff) */ +/* =================================================== P0_RESET_DATA_REG =================================================== */ + #define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL) /*!< P0_RESET (Bit 0) */ + #define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0x3fffUL) /*!< P0_RESET (Bitfield-Mask: 0x3fff) */ +/* ==================================================== P0_SET_DATA_REG ==================================================== */ + #define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL) /*!< P0_SET (Bit 0) */ + #define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0x3fffUL) /*!< P0_SET (Bitfield-Mask: 0x3fff) */ +/* ==================================================== P1_00_MODE_REG ===================================================== */ + #define GPIO_P1_00_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_00_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_00_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_00_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_00_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_00_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_00_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_00_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_00_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_01_MODE_REG ===================================================== */ + #define GPIO_P1_01_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_01_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_01_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_01_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_01_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_01_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_01_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_01_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_01_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_02_MODE_REG ===================================================== */ + #define GPIO_P1_02_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_02_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_02_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_02_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_02_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_02_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_02_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_02_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_02_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_03_MODE_REG ===================================================== */ + #define GPIO_P1_03_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_03_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_03_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_03_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_03_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_03_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_03_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_03_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_03_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_04_MODE_REG ===================================================== */ + #define GPIO_P1_04_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_04_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_04_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_04_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_04_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_04_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_04_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_04_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_04_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_05_MODE_REG ===================================================== */ + #define GPIO_P1_05_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_05_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_05_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_05_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_05_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_05_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_05_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_05_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_05_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_06_MODE_REG ===================================================== */ + #define GPIO_P1_06_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_06_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_06_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_06_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_06_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_06_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_06_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_06_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_06_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_07_MODE_REG ===================================================== */ + #define GPIO_P1_07_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_07_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_07_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_07_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_07_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_07_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_07_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_07_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_07_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_08_MODE_REG ===================================================== */ + #define GPIO_P1_08_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_08_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_08_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_08_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_08_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_08_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_08_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_08_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_08_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_09_MODE_REG ===================================================== */ + #define GPIO_P1_09_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_09_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_09_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_09_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_09_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_09_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_09_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_09_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_09_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_10_MODE_REG ===================================================== */ + #define GPIO_P1_10_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_10_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_10_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_10_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_10_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_10_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_10_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_10_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_10_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_11_MODE_REG ===================================================== */ + #define GPIO_P1_11_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_11_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_11_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_11_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_11_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_11_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_11_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_11_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_11_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_12_MODE_REG ===================================================== */ + #define GPIO_P1_12_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_12_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_12_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_12_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_12_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_12_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_12_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_12_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_12_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_13_MODE_REG ===================================================== */ + #define GPIO_P1_13_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_13_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_13_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_13_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_13_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_13_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_13_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_13_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_13_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_14_MODE_REG ===================================================== */ + #define GPIO_P1_14_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_14_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_14_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_14_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_14_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_14_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_14_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_14_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_14_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_14_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_14_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_14_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ==================================================== P1_15_MODE_REG ===================================================== */ + #define GPIO_P1_15_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_P1_15_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_P1_15_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_P1_15_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_P1_15_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_P1_15_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_P1_15_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_P1_15_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_P1_15_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_P1_15_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_P1_15_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_P1_15_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ====================================================== P1_DATA_REG ====================================================== */ + #define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL) /*!< P1_DATA (Bit 0) */ + #define GPIO_P1_DATA_REG_P1_DATA_Msk (0xffffUL) /*!< P1_DATA (Bitfield-Mask: 0xffff) */ +/* =================================================== P1_RESET_DATA_REG =================================================== */ + #define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL) /*!< P1_RESET (Bit 0) */ + #define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0xffffUL) /*!< P1_RESET (Bitfield-Mask: 0xffff) */ +/* ==================================================== P1_SET_DATA_REG ==================================================== */ + #define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL) /*!< P1_SET (Bit 0) */ + #define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0xffffUL) /*!< P1_SET (Bitfield-Mask: 0xffff) */ +/* ================================================== RAMBIST_ENABLE1_REG ================================================== */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VMX32_BIST_ENABLE_Pos (31UL) /*!< LDPC0_VMX32_BIST_ENABLE (Bit 31) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VMX32_BIST_ENABLE_Msk (0x80000000UL) /*!< LDPC0_VMX32_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VMX10_BIST_ENABLE_Pos (30UL) /*!< LDPC0_VMX10_BIST_ENABLE (Bit 30) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VMX10_BIST_ENABLE_Msk (0x40000000UL) /*!< LDPC0_VMX10_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VR_BIST_ENABLE_Pos (29UL) /*!< LDPC0_VR_BIST_ENABLE (Bit 29) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_VR_BIST_ENABLE_Msk (0x20000000UL) /*!< LDPC0_VR_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_CR_BIST_ENABLE_Pos (28UL) /*!< LDPC0_CR_BIST_ENABLE (Bit 28) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPC0_CR_BIST_ENABLE_Msk (0x10000000UL) /*!< LDPC0_CR_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM6_BIST_ENABLE_Pos (27UL) /*!< FFTMEM6_BIST_ENABLE (Bit 27) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM6_BIST_ENABLE_Msk (0x8000000UL) /*!< FFTMEM6_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM5_BIST_ENABLE_Pos (26UL) /*!< FFTMEM5_BIST_ENABLE (Bit 26) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM5_BIST_ENABLE_Msk (0x4000000UL) /*!< FFTMEM5_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM4_BIST_ENABLE_Pos (25UL) /*!< FFTMEM4_BIST_ENABLE (Bit 25) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM4_BIST_ENABLE_Msk (0x2000000UL) /*!< FFTMEM4_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM3_BIST_ENABLE_Pos (24UL) /*!< FFTMEM3_BIST_ENABLE (Bit 24) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM3_BIST_ENABLE_Msk (0x1000000UL) /*!< FFTMEM3_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM2_BIST_ENABLE_Pos (23UL) /*!< FFTMEM2_BIST_ENABLE (Bit 23) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM2_BIST_ENABLE_Msk (0x800000UL) /*!< FFTMEM2_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM1_BIST_ENABLE_Pos (22UL) /*!< FFTMEM1_BIST_ENABLE (Bit 22) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM1_BIST_ENABLE_Msk (0x400000UL) /*!< FFTMEM1_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM0_BIST_ENABLE_Pos (21UL) /*!< FFTMEM0_BIST_ENABLE (Bit 21) */ + #define GPIO_RAMBIST_ENABLE1_REG_FFTMEM0_BIST_ENABLE_Msk (0x200000UL) /*!< FFTMEM0_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_RADAR_BIST_ENABLE_Pos (20UL) /*!< RADAR_BIST_ENABLE (Bit 20) */ + #define GPIO_RAMBIST_ENABLE1_REG_RADAR_BIST_ENABLE_Msk (0x100000UL) /*!< RADAR_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_BFMEE_BIST_ENABLE_Pos (19UL) /*!< BFMEE_BIST_ENABLE (Bit 19) */ + #define GPIO_RAMBIST_ENABLE1_REG_BFMEE_BIST_ENABLE_Msk (0x80000UL) /*!< BFMEE_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPCTX_BIST_ENABLE_Pos (18UL) /*!< LDPCTX_BIST_ENABLE (Bit 18) */ + #define GPIO_RAMBIST_ENABLE1_REG_LDPCTX_BIST_ENABLE_Msk (0x40000UL) /*!< LDPCTX_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MPIFRX_BIST_ENABLE_Pos (17UL) /*!< MPIFRX_BIST_ENABLE (Bit 17) */ + #define GPIO_RAMBIST_ENABLE1_REG_MPIFRX_BIST_ENABLE_Msk (0x20000UL) /*!< MPIFRX_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MPIFTX_BIST_ENABLE_Pos (16UL) /*!< MPIFTX_BIST_ENABLE (Bit 16) */ + #define GPIO_RAMBIST_ENABLE1_REG_MPIFTX_BIST_ENABLE_Msk (0x10000UL) /*!< MPIFTX_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SBOXRAM_BIST_ENABLE_Pos (15UL) /*!< SBOXRAM_BIST_ENABLE (Bit 15) */ + #define GPIO_RAMBIST_ENABLE1_REG_SBOXRAM_BIST_ENABLE_Msk (0x8000UL) /*!< SBOXRAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MACRX_BIST_ENABLE_Pos (14UL) /*!< MACRX_BIST_ENABLE (Bit 14) */ + #define GPIO_RAMBIST_ENABLE1_REG_MACRX_BIST_ENABLE_Msk (0x4000UL) /*!< MACRX_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MACTX_BIST_ENABLE_Pos (13UL) /*!< MACTX_BIST_ENABLE (Bit 13) */ + #define GPIO_RAMBIST_ENABLE1_REG_MACTX_BIST_ENABLE_Msk (0x2000UL) /*!< MACTX_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MIBRAM_BIST_ENABLE_Pos (12UL) /*!< MIBRAM_BIST_ENABLE (Bit 12) */ + #define GPIO_RAMBIST_ENABLE1_REG_MIBRAM_BIST_ENABLE_Msk (0x1000UL) /*!< MIBRAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_KEYSTG1_BIST_ENABLE_Pos (11UL) /*!< KEYSTG1_BIST_ENABLE (Bit 11) */ + #define GPIO_RAMBIST_ENABLE1_REG_KEYSTG1_BIST_ENABLE_Msk (0x800UL) /*!< KEYSTG1_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_KEYSTG0_BIST_ENABLE_Pos (10UL) /*!< KEYSTG0_BIST_ENABLE (Bit 10) */ + #define GPIO_RAMBIST_ENABLE1_REG_KEYSTG0_BIST_ENABLE_Msk (0x400UL) /*!< KEYSTG0_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_CC312RAM_BIST_ENABLE_Pos (9UL) /*!< CC312RAM_BIST_ENABLE (Bit 9) */ + #define GPIO_RAMBIST_ENABLE1_REG_CC312RAM_BIST_ENABLE_Msk (0x200UL) /*!< CC312RAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_AGCRAM_BIST_ENABLE_Pos (8UL) /*!< AGCRAM_BIST_ENABLE (Bit 8) */ + #define GPIO_RAMBIST_ENABLE1_REG_AGCRAM_BIST_ENABLE_Msk (0x100UL) /*!< AGCRAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_RETMEM_BIST_ENABLE_Pos (7UL) /*!< RETMEM_BIST_ENABLE (Bit 7) */ + #define GPIO_RAMBIST_ENABLE1_REG_RETMEM_BIST_ENABLE_Msk (0x80UL) /*!< RETMEM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM5_BIST_ENABLE_Pos (6UL) /*!< SYSRAM5_BIST_ENABLE (Bit 6) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM5_BIST_ENABLE_Msk (0x40UL) /*!< SYSRAM5_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM4_BIST_ENABLE_Pos (5UL) /*!< SYSRAM4_BIST_ENABLE (Bit 5) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM4_BIST_ENABLE_Msk (0x20UL) /*!< SYSRAM4_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM3_BIST_ENABLE_Pos (4UL) /*!< SYSRAM3_BIST_ENABLE (Bit 4) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM3_BIST_ENABLE_Msk (0x10UL) /*!< SYSRAM3_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM2_BIST_ENABLE_Pos (3UL) /*!< SYSRAM2_BIST_ENABLE (Bit 3) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM2_BIST_ENABLE_Msk (0x8UL) /*!< SYSRAM2_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM1_BIST_ENABLE_Pos (2UL) /*!< SYSRAM1_BIST_ENABLE (Bit 2) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM1_BIST_ENABLE_Msk (0x4UL) /*!< SYSRAM1_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM0_BIST_ENABLE_Pos (1UL) /*!< SYSRAM0_BIST_ENABLE (Bit 1) */ + #define GPIO_RAMBIST_ENABLE1_REG_SYSRAM0_BIST_ENABLE_Msk (0x2UL) /*!< SYSRAM0_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE1_REG_MROM_BIST_ENABLE_Pos (0UL) /*!< MROM_BIST_ENABLE (Bit 0) */ + #define GPIO_RAMBIST_ENABLE1_REG_MROM_BIST_ENABLE_Msk (0x1UL) /*!< MROM_BIST_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== RAMBIST_ENABLE2_REG ================================================== */ + #define GPIO_RAMBIST_ENABLE2_REG_DCACHE_TAG_RAM_BIST_ENABLE_Pos (10UL) /*!< DCACHE_TAG_RAM_BIST_ENABLE (Bit 10) */ + #define GPIO_RAMBIST_ENABLE2_REG_DCACHE_TAG_RAM_BIST_ENABLE_Msk (0x400UL) /*!< DCACHE_TAG_RAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_DCACHE_DATA_RAM_BIST_ENABLE_Pos (9UL) /*!< DCACHE_DATA_RAM_BIST_ENABLE (Bit 9) */ + #define GPIO_RAMBIST_ENABLE2_REG_DCACHE_DATA_RAM_BIST_ENABLE_Msk (0x200UL) /*!< DCACHE_DATA_RAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_CACHE_MEM10_BIST_ENABLE_Pos (8UL) /*!< CACHE_MEM10_BIST_ENABLE (Bit 8) */ + #define GPIO_RAMBIST_ENABLE2_REG_CACHE_MEM10_BIST_ENABLE_Msk (0x100UL) /*!< CACHE_MEM10_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_SDIO_RAM_BIST_ENABLE_Pos (7UL) /*!< SDIO_RAM_BIST_ENABLE (Bit 7) */ + #define GPIO_RAMBIST_ENABLE2_REG_SDIO_RAM_BIST_ENABLE_Msk (0x80UL) /*!< SDIO_RAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_EMMCRAM_BIST_ENABLE_Pos (6UL) /*!< EMMCRAM_BIST_ENABLE (Bit 6) */ + #define GPIO_RAMBIST_ENABLE2_REG_EMMCRAM_BIST_ENABLE_Msk (0x40UL) /*!< EMMCRAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_BDFD1_RAM_BIST_ENABLE_Pos (5UL) /*!< BDFD1_RAM_BIST_ENABLE (Bit 5) */ + #define GPIO_RAMBIST_ENABLE2_REG_BDFD1_RAM_BIST_ENABLE_Msk (0x20UL) /*!< BDFD1_RAM_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_HDXY_BIST_ENABLE_Pos (4UL) /*!< LDPC0_HDXY_BIST_ENABLE (Bit 4) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_HDXY_BIST_ENABLE_Msk (0x10UL) /*!< LDPC0_HDXY_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY54_BIST_ENABLE_Pos (3UL) /*!< LDPC0_VMY54_BIST_ENABLE (Bit 3) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY54_BIST_ENABLE_Msk (0x8UL) /*!< LDPC0_VMY54_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY32_BIST_ENABLE_Pos (2UL) /*!< LDPC0_VMY32_BIST_ENABLE (Bit 2) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY32_BIST_ENABLE_Msk (0x4UL) /*!< LDPC0_VMY32_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY10_BIST_ENABLE_Pos (1UL) /*!< LDPC0_VMY10_BIST_ENABLE (Bit 1) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMY10_BIST_ENABLE_Msk (0x2UL) /*!< LDPC0_VMY10_BIST_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMX54_BIST_ENABLE_Pos (0UL) /*!< LDPC0_VMX54_BIST_ENABLE (Bit 0) */ + #define GPIO_RAMBIST_ENABLE2_REG_LDPC0_VMX54_BIST_ENABLE_Msk (0x1UL) /*!< LDPC0_VMX54_BIST_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== RAMBIST_RESULT1_REG ================================================== */ + #define GPIO_RAMBIST_RESULT1_REG_RAM_GRP1_BIST_FAIL_Pos (0UL) /*!< RAM_GRP1_BIST_FAIL (Bit 0) */ + #define GPIO_RAMBIST_RESULT1_REG_RAM_GRP1_BIST_FAIL_Msk (0xffffffffUL) /*!< RAM_GRP1_BIST_FAIL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== RAMBIST_RESULT2_REG ================================================== */ + #define GPIO_RAMBIST_RESULT2_REG_RAM_GRP2_BIST_FAIL_Pos (0UL) /*!< RAM_GRP2_BIST_FAIL (Bit 0) */ + #define GPIO_RAMBIST_RESULT2_REG_RAM_GRP2_BIST_FAIL_Msk (0xffffffffUL) /*!< RAM_GRP2_BIST_FAIL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== RAMBIST_RESULT3_REG ================================================== */ + #define GPIO_RAMBIST_RESULT3_REG_RAM_GRP3_BIST_FAIL_Pos (0UL) /*!< RAM_GRP3_BIST_FAIL (Bit 0) */ + #define GPIO_RAMBIST_RESULT3_REG_RAM_GRP3_BIST_FAIL_Msk (0xfUL) /*!< RAM_GRP3_BIST_FAIL (Bitfield-Mask: 0x0f) */ +/* ================================================== RAMBIST_STATUS1_REG ================================================== */ + #define GPIO_RAMBIST_STATUS1_REG_RAM_GRP1_BIST_BUSY_Pos (0UL) /*!< RAM_GRP1_BIST_BUSY (Bit 0) */ + #define GPIO_RAMBIST_STATUS1_REG_RAM_GRP1_BIST_BUSY_Msk (0xffffffffUL) /*!< RAM_GRP1_BIST_BUSY (Bitfield-Mask: 0xffffffff) */ +/* ================================================== RAMBIST_STATUS2_REG ================================================== */ + #define GPIO_RAMBIST_STATUS2_REG_RAM_GRP2_BIST_BUSY_Pos (0UL) /*!< RAM_GRP2_BIST_BUSY (Bit 0) */ + #define GPIO_RAMBIST_STATUS2_REG_RAM_GRP2_BIST_BUSY_Msk (0xffffffffUL) /*!< RAM_GRP2_BIST_BUSY (Bitfield-Mask: 0xffffffff) */ +/* ================================================== RAMBIST_STATUS3_REG ================================================== */ + #define GPIO_RAMBIST_STATUS3_REG_RAM_GRP3_BIST_BUSY_Pos (0UL) /*!< RAM_GRP3_BIST_BUSY (Bit 0) */ + #define GPIO_RAMBIST_STATUS3_REG_RAM_GRP3_BIST_BUSY_Msk (0xfUL) /*!< RAM_GRP3_BIST_BUSY (Bitfield-Mask: 0x0f) */ +/* ================================================== ROMBIST_RESULT_REG =================================================== */ + #define GPIO_ROMBIST_RESULT_REG_ROMBIST_RESULT_Pos (0UL) /*!< ROMBIST_RESULT (Bit 0) */ + #define GPIO_ROMBIST_RESULT_REG_ROMBIST_RESULT_Msk (0xffffffffUL) /*!< ROMBIST_RESULT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SDIO_MODE_REG ===================================================== */ + #define GPIO_SDIO_MODE_REG_SDIO_PULL_SEL_Pos (10UL) /*!< SDIO_PULL_SEL (Bit 10) */ + #define GPIO_SDIO_MODE_REG_SDIO_PULL_SEL_Msk (0xfc00UL) /*!< SDIO_PULL_SEL (Bitfield-Mask: 0x3f) */ + #define GPIO_SDIO_MODE_REG_SDIO_PULL_EN_Pos (4UL) /*!< SDIO_PULL_EN (Bit 4) */ + #define GPIO_SDIO_MODE_REG_SDIO_PULL_EN_Msk (0x3f0UL) /*!< SDIO_PULL_EN (Bitfield-Mask: 0x3f) */ + #define GPIO_SDIO_MODE_REG_CFG_DRV_Pos (2UL) /*!< CFG_DRV (Bit 2) */ + #define GPIO_SDIO_MODE_REG_CFG_DRV_Msk (0xcUL) /*!< CFG_DRV (Bitfield-Mask: 0x03) */ + #define GPIO_SDIO_MODE_REG_SDIO_PORT_SEL_Pos (1UL) /*!< SDIO_PORT_SEL (Bit 1) */ + #define GPIO_SDIO_MODE_REG_SDIO_PORT_SEL_Msk (0x2UL) /*!< SDIO_PORT_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_SDIO_MODE_REG_SDIO_PAD_ENABLE_Pos (0UL) /*!< SDIO_PAD_ENABLE (Bit 0) */ + #define GPIO_SDIO_MODE_REG_SDIO_PAD_ENABLE_Msk (0x1UL) /*!< SDIO_PAD_ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== SW0_MODE_REG ====================================================== */ + #define GPIO_SW0_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_SW0_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_SW0_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_SW0_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_SW0_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_SW0_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_SW0_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_SW0_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_SW0_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_SW0_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_SW0_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_SW0_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_SW0_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_SW0_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ===================================================== SW1_MODE_REG ====================================================== */ + #define GPIO_SW1_MODE_REG_POE_Pos (15UL) /*!< POE (Bit 15) */ + #define GPIO_SW1_MODE_REG_POE_Msk (0x8000UL) /*!< POE (Bitfield-Mask: 0x01) */ + #define GPIO_SW1_MODE_REG_SR_Pos (14UL) /*!< SR (Bit 14) */ + #define GPIO_SW1_MODE_REG_SR_Msk (0x4000UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define GPIO_SW1_MODE_REG_DS_Pos (12UL) /*!< DS (Bit 12) */ + #define GPIO_SW1_MODE_REG_DS_Msk (0x3000UL) /*!< DS (Bitfield-Mask: 0x03) */ + #define GPIO_SW1_MODE_REG_IS_Pos (11UL) /*!< IS (Bit 11) */ + #define GPIO_SW1_MODE_REG_IS_Msk (0x800UL) /*!< IS (Bitfield-Mask: 0x01) */ + #define GPIO_SW1_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ + #define GPIO_SW1_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ + #define GPIO_SW1_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ + #define GPIO_SW1_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ + #define GPIO_SW1_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define GPIO_SW1_MODE_REG_PID_Msk (0x7fUL) /*!< PID (Bitfield-Mask: 0x7f) */ +/* ====================================================== SW_DATA_REG ====================================================== */ + #define GPIO_SW_DATA_REG_SWD_DATA_Pos (0UL) /*!< SWD_DATA (Bit 0) */ + #define GPIO_SW_DATA_REG_SWD_DATA_Msk (0x3UL) /*!< SWD_DATA (Bitfield-Mask: 0x03) */ +/* =================================================== SW_RESET_DATA_REG =================================================== */ + #define GPIO_SW_RESET_DATA_REG_SWD_RESET_Pos (0UL) /*!< SWD_RESET (Bit 0) */ + #define GPIO_SW_RESET_DATA_REG_SWD_RESET_Msk (0x3UL) /*!< SWD_RESET (Bitfield-Mask: 0x03) */ +/* ==================================================== SW_SET_DATA_REG ==================================================== */ + #define GPIO_SW_SET_DATA_REG_SWD_SET_Pos (0UL) /*!< SWD_SET (Bit 0) */ + #define GPIO_SW_SET_DATA_REG_SWD_SET_Msk (0x3UL) /*!< SWD_SET (Bitfield-Mask: 0x03) */ +/* ==================================================== TEST_CTRL2_REG ===================================================== */ + #define GPIO_TEST_CTRL2_REG_SCAN_CONTROL_Pos (0UL) /*!< SCAN_CONTROL (Bit 0) */ + #define GPIO_TEST_CTRL2_REG_SCAN_CONTROL_Msk (0x3fUL) /*!< SCAN_CONTROL (Bitfield-Mask: 0x3f) */ +/* ===================================================== TEST_CTRL_REG ===================================================== */ + #define GPIO_TEST_CTRL_REG_RF_ONLY_MODE_SEL_Pos (20UL) /*!< RF_ONLY_MODE_SEL (Bit 20) */ + #define GPIO_TEST_CTRL_REG_RF_ONLY_MODE_SEL_Msk (0x100000UL) /*!< RF_ONLY_MODE_SEL (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_RF_ONLY_MODE_EN_Pos (19UL) /*!< RF_ONLY_MODE_EN (Bit 19) */ + #define GPIO_TEST_CTRL_REG_RF_ONLY_MODE_EN_Msk (0x80000UL) /*!< RF_ONLY_MODE_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_POLARTX_SCAN_TEST_EN_Pos (18UL) /*!< POLARTX_SCAN_TEST_EN (Bit 18) */ + #define GPIO_TEST_CTRL_REG_POLARTX_SCAN_TEST_EN_Msk (0x40000UL) /*!< POLARTX_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_UPSAM_2G4_2_SCAN_TEST_EN_Pos (17UL) /*!< UPSAM_2G4_2_SCAN_TEST_EN (Bit 17) */ + #define GPIO_TEST_CTRL_REG_UPSAM_2G4_2_SCAN_TEST_EN_Msk (0x20000UL) /*!< UPSAM_2G4_2_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_UPSAM_2G4_1_SCAN_TEST_EN_Pos (16UL) /*!< UPSAM_2G4_1_SCAN_TEST_EN (Bit 16) */ + #define GPIO_TEST_CTRL_REG_UPSAM_2G4_1_SCAN_TEST_EN_Msk (0x10000UL) /*!< UPSAM_2G4_1_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_UPSAM_5G0_2_SCAN_TEST_EN_Pos (15UL) /*!< UPSAM_5G0_2_SCAN_TEST_EN (Bit 15) */ + #define GPIO_TEST_CTRL_REG_UPSAM_5G0_2_SCAN_TEST_EN_Msk (0x8000UL) /*!< UPSAM_5G0_2_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_UPSAM_5G0_1_SCAN_TEST_EN_Pos (14UL) /*!< UPSAM_5G0_1_SCAN_TEST_EN (Bit 14) */ + #define GPIO_TEST_CTRL_REG_UPSAM_5G0_1_SCAN_TEST_EN_Msk (0x4000UL) /*!< UPSAM_5G0_1_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_FILCAL_SCAN_TEST_EN_Pos (13UL) /*!< FILCAL_SCAN_TEST_EN (Bit 13) */ + #define GPIO_TEST_CTRL_REG_FILCAL_SCAN_TEST_EN_Msk (0x2000UL) /*!< FILCAL_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_AFC_SCAN_TEST_EN_Pos (12UL) /*!< AFC_SCAN_TEST_EN (Bit 12) */ + #define GPIO_TEST_CTRL_REG_AFC_SCAN_TEST_EN_Msk (0x1000UL) /*!< AFC_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_LOCAL_SCAN_TEST_EN_Pos (11UL) /*!< LOCAL_SCAN_TEST_EN (Bit 11) */ + #define GPIO_TEST_CTRL_REG_LOCAL_SCAN_TEST_EN_Msk (0x800UL) /*!< LOCAL_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_LD_SCAN_TEST_EN_Pos (10UL) /*!< LD_SCAN_TEST_EN (Bit 10) */ + #define GPIO_TEST_CTRL_REG_LD_SCAN_TEST_EN_Msk (0x400UL) /*!< LD_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_ADCSEN_SCAN_TEST_EN_Pos (9UL) /*!< ADCSEN_SCAN_TEST_EN (Bit 9) */ + #define GPIO_TEST_CTRL_REG_ADCSEN_SCAN_TEST_EN_Msk (0x200UL) /*!< ADCSEN_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_RTC_SCAN_TEST_EN_Pos (8UL) /*!< RTC_SCAN_TEST_EN (Bit 8) */ + #define GPIO_TEST_CTRL_REG_RTC_SCAN_TEST_EN_Msk (0x100UL) /*!< RTC_SCAN_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_RFMON_TBUS_SEL_Pos (6UL) /*!< RFMON_TBUS_SEL (Bit 6) */ + #define GPIO_TEST_CTRL_REG_RFMON_TBUS_SEL_Msk (0xc0UL) /*!< RFMON_TBUS_SEL (Bitfield-Mask: 0x03) */ + #define GPIO_TEST_CTRL_REG_AUXADC_TEST_EN_Pos (5UL) /*!< AUXADC_TEST_EN (Bit 5) */ + #define GPIO_TEST_CTRL_REG_AUXADC_TEST_EN_Msk (0x20UL) /*!< AUXADC_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_IQDAC_TEST_EN_Pos (4UL) /*!< IQDAC_TEST_EN (Bit 4) */ + #define GPIO_TEST_CTRL_REG_IQDAC_TEST_EN_Msk (0x10UL) /*!< IQDAC_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_IQADC_TEST_EN_Pos (3UL) /*!< IQADC_TEST_EN (Bit 3) */ + #define GPIO_TEST_CTRL_REG_IQADC_TEST_EN_Msk (0x8UL) /*!< IQADC_TEST_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_RTC_MONITOR_EN_Pos (2UL) /*!< RTC_MONITOR_EN (Bit 2) */ + #define GPIO_TEST_CTRL_REG_RTC_MONITOR_EN_Msk (0x4UL) /*!< RTC_MONITOR_EN (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_RFPT_ENABLE_Pos (1UL) /*!< RFPT_ENABLE (Bit 1) */ + #define GPIO_TEST_CTRL_REG_RFPT_ENABLE_Msk (0x2UL) /*!< RFPT_ENABLE (Bitfield-Mask: 0x01) */ + #define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos (0UL) /*!< SHOW_CLOCKS (Bit 0) */ + #define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk (0x1UL) /*!< SHOW_CLOCKS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GPREG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DEBUG_REG ======================================================= */ + #define GPREG_DEBUG_REG_ETM_TRACE_MAP_ON_PINS_EN_Pos (4UL) /*!< ETM_TRACE_MAP_ON_PINS_EN (Bit 4) */ + #define GPREG_DEBUG_REG_ETM_TRACE_MAP_ON_PINS_EN_Msk (0x10UL) /*!< ETM_TRACE_MAP_ON_PINS_EN (Bitfield-Mask: 0x01) */ + #define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (3UL) /*!< SYS_CPUWAIT_ON_JTAG (Bit 3) */ + #define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x8UL) /*!< SYS_CPUWAIT_ON_JTAG (Bitfield-Mask: 0x01) */ + #define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (2UL) /*!< SYS_CPUWAIT (Bit 2) */ + #define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x4UL) /*!< SYS_CPUWAIT (Bitfield-Mask: 0x01) */ + #define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (1UL) /*!< SYS_CPU_IS_HALTED (Bit 1) */ + #define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x2UL) /*!< SYS_CPU_IS_HALTED (Bitfield-Mask: 0x01) */ + #define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL) /*!< SYS_CPU_FREEZE_EN (Bit 0) */ + #define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL) /*!< SYS_CPU_FREEZE_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== GP_STATUS_REG ===================================================== */ + #define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL) /*!< CAL_PHASE (Bit 0) */ + #define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL) /*!< CAL_PHASE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ HW_ACC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CRC_1_ADDR_MAX_REG =================================================== */ + #define HW_ACC_CRC_1_ADDR_MAX_REG_CRC_1_ADDR_MAX_Pos (0UL) /*!< CRC_1_ADDR_MAX (Bit 0) */ + #define HW_ACC_CRC_1_ADDR_MAX_REG_CRC_1_ADDR_MAX_Msk (0xffffffffUL) /*!< CRC_1_ADDR_MAX (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRC_1_ADDR_MIN_REG =================================================== */ + #define HW_ACC_CRC_1_ADDR_MIN_REG_CRC_1_ADDR_MIN_Pos (0UL) /*!< CRC_1_ADDR_MIN (Bit 0) */ + #define HW_ACC_CRC_1_ADDR_MIN_REG_CRC_1_ADDR_MIN_Msk (0xffffffffUL) /*!< CRC_1_ADDR_MIN (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRC_1_CAL_VAL_REG =================================================== */ + #define HW_ACC_CRC_1_CAL_VAL_REG_CRC_1_CAL_VAL_Pos (0UL) /*!< CRC_1_CAL_VAL (Bit 0) */ + #define HW_ACC_CRC_1_CAL_VAL_REG_CRC_1_CAL_VAL_Msk (0xffffffffUL) /*!< CRC_1_CAL_VAL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CRC_1_CAL_VAL_REV_REG ================================================= */ + #define HW_ACC_CRC_1_CAL_VAL_REV_REG_CRC_1_CAL_VAL_REV_Pos (0UL) /*!< CRC_1_CAL_VAL_REV (Bit 0) */ + #define HW_ACC_CRC_1_CAL_VAL_REV_REG_CRC_1_CAL_VAL_REV_Msk (0xffffffffUL) /*!< CRC_1_CAL_VAL_REV (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRC_1_CONFIG_REG ==================================================== */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_OP_TYPE_Pos (26UL) /*!< CRC_1_OP_TYPE (Bit 26) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_OP_TYPE_Msk (0xc000000UL) /*!< CRC_1_OP_TYPE (Bitfield-Mask: 0x03) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_CHK_MST_Pos (25UL) /*!< CRC_1_CHK_MST (Bit 25) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_CHK_MST_Msk (0x2000000UL) /*!< CRC_1_CHK_MST (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_CHK_ADDR_Pos (24UL) /*!< CRC_1_CHK_ADDR (Bit 24) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_CHK_ADDR_Msk (0x1000000UL) /*!< CRC_1_CHK_ADDR (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_MST_TYPE_Pos (16UL) /*!< CRC_1_MST_TYPE (Bit 16) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_MST_TYPE_Msk (0x1f0000UL) /*!< CRC_1_MST_TYPE (Bitfield-Mask: 0x1f) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_SWAP_EN_Pos (13UL) /*!< CRC_1_SWAP_EN (Bit 13) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_SWAP_EN_Msk (0x2000UL) /*!< CRC_1_SWAP_EN (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_ENDIAN_TYPE_Pos (12UL) /*!< CRC_1_ENDIAN_TYPE (Bit 12) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_ENDIAN_TYPE_Msk (0x1000UL) /*!< CRC_1_ENDIAN_TYPE (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_PAR_TYPE_Pos (9UL) /*!< CRC_1_PAR_TYPE (Bit 9) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_PAR_TYPE_Msk (0x600UL) /*!< CRC_1_PAR_TYPE (Bitfield-Mask: 0x03) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_ACC_TYPE_Pos (8UL) /*!< CRC_1_ACC_TYPE (Bit 8) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_ACC_TYPE_Msk (0x100UL) /*!< CRC_1_ACC_TYPE (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_PATH_SEL_Pos (0UL) /*!< CRC_1_PATH_SEL (Bit 0) */ + #define HW_ACC_CRC_1_CONFIG_REG_CRC_1_PATH_SEL_Msk (0x1fUL) /*!< CRC_1_PATH_SEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== CRC_1_OP_EN_REG ==================================================== */ + #define HW_ACC_CRC_1_OP_EN_REG_CRC_1_OP_EN_Pos (0UL) /*!< CRC_1_OP_EN (Bit 0) */ + #define HW_ACC_CRC_1_OP_EN_REG_CRC_1_OP_EN_Msk (0x1UL) /*!< CRC_1_OP_EN (Bitfield-Mask: 0x01) */ +/* ================================================= CRC_1_PSEUDO_VAL_REG ================================================== */ + #define HW_ACC_CRC_1_PSEUDO_VAL_REG_CRC_1_PSEUDO_VAL_Pos (0UL) /*!< CRC_1_PSEUDO_VAL (Bit 0) */ + #define HW_ACC_CRC_1_PSEUDO_VAL_REG_CRC_1_PSEUDO_VAL_Msk (0xffffffffUL) /*!< CRC_1_PSEUDO_VAL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRC_1_REQ_CTRL_REG =================================================== */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_STOP_Pos (2UL) /*!< CRC_1_REQ_STOP (Bit 2) */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_STOP_Msk (0x4UL) /*!< CRC_1_REQ_STOP (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_START_Pos (1UL) /*!< CRC_1_REQ_START (Bit 1) */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_START_Msk (0x2UL) /*!< CRC_1_REQ_START (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_CLR_Pos (0UL) /*!< CRC_1_REQ_CLR (Bit 0) */ + #define HW_ACC_CRC_1_REQ_CTRL_REG_CRC_1_REQ_CLR_Msk (0x1UL) /*!< CRC_1_REQ_CLR (Bitfield-Mask: 0x01) */ +/* ================================================== CRC_1_SEED_VAL_REG =================================================== */ + #define HW_ACC_CRC_1_SEED_VAL_REG_CRC_1_SEED_VAL_Pos (0UL) /*!< CRC_1_SEED_VAL (Bit 0) */ + #define HW_ACC_CRC_1_SEED_VAL_REG_CRC_1_SEED_VAL_Msk (0xffffffffUL) /*!< CRC_1_SEED_VAL (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CRC_1_STA_REG ===================================================== */ + #define HW_ACC_CRC_1_STA_REG_CRC_1_CAL_STA_Pos (24UL) /*!< CRC_1_CAL_STA (Bit 24) */ + #define HW_ACC_CRC_1_STA_REG_CRC_1_CAL_STA_Msk (0x3000000UL) /*!< CRC_1_CAL_STA (Bitfield-Mask: 0x03) */ +/* =================================================== CRC_ADDR_MAX_REG ==================================================== */ + #define HW_ACC_CRC_ADDR_MAX_REG_CRC_ADDR_MAX_Pos (0UL) /*!< CRC_ADDR_MAX (Bit 0) */ + #define HW_ACC_CRC_ADDR_MAX_REG_CRC_ADDR_MAX_Msk (0xffffffffUL) /*!< CRC_ADDR_MAX (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRC_ADDR_MIN_REG ==================================================== */ + #define HW_ACC_CRC_ADDR_MIN_REG_CRC_ADDR_MIN_Pos (0UL) /*!< CRC_ADDR_MIN (Bit 0) */ + #define HW_ACC_CRC_ADDR_MIN_REG_CRC_ADDR_MIN_Msk (0xffffffffUL) /*!< CRC_ADDR_MIN (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRC_CAL_VAL_REG ==================================================== */ + #define HW_ACC_CRC_CAL_VAL_REG_CRC_CAL_VAL_Pos (0UL) /*!< CRC_CAL_VAL (Bit 0) */ + #define HW_ACC_CRC_CAL_VAL_REG_CRC_CAL_VAL_Msk (0xffffffffUL) /*!< CRC_CAL_VAL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRC_CAL_VAL_REV_REG ================================================== */ + #define HW_ACC_CRC_CAL_VAL_REV_REG_CRC_CAL_VAL_REV_Pos (0UL) /*!< CRC_CAL_VAL_REV (Bit 0) */ + #define HW_ACC_CRC_CAL_VAL_REV_REG_CRC_CAL_VAL_REV_Msk (0xffffffffUL) /*!< CRC_CAL_VAL_REV (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRC_CONFIG_REG ===================================================== */ + #define HW_ACC_CRC_CONFIG_REG_CRC_OP_TYPE_Pos (26UL) /*!< CRC_OP_TYPE (Bit 26) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_OP_TYPE_Msk (0xc000000UL) /*!< CRC_OP_TYPE (Bitfield-Mask: 0x03) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_CHK_MST_Pos (25UL) /*!< CRC_CHK_MST (Bit 25) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_CHK_MST_Msk (0x2000000UL) /*!< CRC_CHK_MST (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_CHK_ADDR_Pos (24UL) /*!< CRC_CHK_ADDR (Bit 24) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_CHK_ADDR_Msk (0x1000000UL) /*!< CRC_CHK_ADDR (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_MST_TYPE_Pos (16UL) /*!< CRC_MST_TYPE (Bit 16) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_MST_TYPE_Msk (0x1f0000UL) /*!< CRC_MST_TYPE (Bitfield-Mask: 0x1f) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_SWAP_EN_Pos (13UL) /*!< CRC_SWAP_EN (Bit 13) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_SWAP_EN_Msk (0x2000UL) /*!< CRC_SWAP_EN (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_ENDIAN_TYPE_Pos (12UL) /*!< CRC_ENDIAN_TYPE (Bit 12) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_ENDIAN_TYPE_Msk (0x1000UL) /*!< CRC_ENDIAN_TYPE (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_PAR_TYPE_Pos (9UL) /*!< CRC_PAR_TYPE (Bit 9) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_PAR_TYPE_Msk (0x600UL) /*!< CRC_PAR_TYPE (Bitfield-Mask: 0x03) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_ACC_TYPE_Pos (8UL) /*!< CRC_ACC_TYPE (Bit 8) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_ACC_TYPE_Msk (0x100UL) /*!< CRC_ACC_TYPE (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_PATH_SEL_Pos (0UL) /*!< CRC_PATH_SEL (Bit 0) */ + #define HW_ACC_CRC_CONFIG_REG_CRC_PATH_SEL_Msk (0x1fUL) /*!< CRC_PATH_SEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== CRC_OP_EN_REG ===================================================== */ + #define HW_ACC_CRC_OP_EN_REG_CRC_OP_EN_Pos (0UL) /*!< CRC_OP_EN (Bit 0) */ + #define HW_ACC_CRC_OP_EN_REG_CRC_OP_EN_Msk (0x1UL) /*!< CRC_OP_EN (Bitfield-Mask: 0x01) */ +/* ================================================== CRC_PSEUDO_VAL_REG =================================================== */ + #define HW_ACC_CRC_PSEUDO_VAL_REG_CRC_PSEUDO_VAL_Pos (0UL) /*!< CRC_PSEUDO_VAL (Bit 0) */ + #define HW_ACC_CRC_PSEUDO_VAL_REG_CRC_PSEUDO_VAL_Msk (0xffffffffUL) /*!< CRC_PSEUDO_VAL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRC_REQ_CTRL_REG ==================================================== */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_STOP_Pos (2UL) /*!< CRC_REQ_STOP (Bit 2) */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_STOP_Msk (0x4UL) /*!< CRC_REQ_STOP (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_START_Pos (1UL) /*!< CRC_REQ_START (Bit 1) */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_START_Msk (0x2UL) /*!< CRC_REQ_START (Bitfield-Mask: 0x01) */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_CLR_Pos (0UL) /*!< CRC_REQ_CLR (Bit 0) */ + #define HW_ACC_CRC_REQ_CTRL_REG_CRC_REQ_CLR_Msk (0x1UL) /*!< CRC_REQ_CLR (Bitfield-Mask: 0x01) */ +/* =================================================== CRC_SEED_VAL_REG ==================================================== */ + #define HW_ACC_CRC_SEED_VAL_REG_CRC_SEED_VAL_Pos (0UL) /*!< CRC_SEED_VAL (Bit 0) */ + #define HW_ACC_CRC_SEED_VAL_REG_CRC_SEED_VAL_Msk (0xffffffffUL) /*!< CRC_SEED_VAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CRC_STA_REG ====================================================== */ + #define HW_ACC_CRC_STA_REG_CRC_CAL_STA_Pos (24UL) /*!< CRC_CAL_STA (Bit 24) */ + #define HW_ACC_CRC_STA_REG_CRC_CAL_STA_Msk (0x3000000UL) /*!< CRC_CAL_STA (Bitfield-Mask: 0x03) */ +/* ================================================== HW_CHS_ADDR_MAX_REG ================================================== */ + #define HW_ACC_HW_CHS_ADDR_MAX_REG_HW_CHS_ADDR_MAX_Pos (0UL) /*!< HW_CHS_ADDR_MAX (Bit 0) */ + #define HW_ACC_HW_CHS_ADDR_MAX_REG_HW_CHS_ADDR_MAX_Msk (0xffffffffUL) /*!< HW_CHS_ADDR_MAX (Bitfield-Mask: 0xffffffff) */ +/* ================================================== HW_CHS_ADDR_MIN_REG ================================================== */ + #define HW_ACC_HW_CHS_ADDR_MIN_REG_HW_CHS_ADDR_MIN_Pos (0UL) /*!< HW_CHS_ADDR_MIN (Bit 0) */ + #define HW_ACC_HW_CHS_ADDR_MIN_REG_HW_CHS_ADDR_MIN_Msk (0xffffffffUL) /*!< HW_CHS_ADDR_MIN (Bitfield-Mask: 0xffffffff) */ +/* ================================================== HW_CHS_CAL_STA_REG =================================================== */ + #define HW_ACC_HW_CHS_CAL_STA_REG_HW_CHS_CAL_STA_Pos (24UL) /*!< HW_CHS_CAL_STA (Bit 24) */ + #define HW_ACC_HW_CHS_CAL_STA_REG_HW_CHS_CAL_STA_Msk (0x3000000UL) /*!< HW_CHS_CAL_STA (Bitfield-Mask: 0x03) */ + #define HW_ACC_HW_CHS_CAL_STA_REG_HW_CHS_CAL_NUM_Pos (0UL) /*!< HW_CHS_CAL_NUM (Bit 0) */ + #define HW_ACC_HW_CHS_CAL_STA_REG_HW_CHS_CAL_NUM_Msk (0xfffffUL) /*!< HW_CHS_CAL_NUM (Bitfield-Mask: 0xfffff) */ +/* ================================================== HW_CHS_CAL_VAL_REG =================================================== */ + #define HW_ACC_HW_CHS_CAL_VAL_REG_HW_CHS_CAL_VAL_Pos (0UL) /*!< HW_CHS_CAL_VAL (Bit 0) */ + #define HW_ACC_HW_CHS_CAL_VAL_REG_HW_CHS_CAL_VAL_Msk (0xffffUL) /*!< HW_CHS_CAL_VAL (Bitfield-Mask: 0xffff) */ +/* =================================================== HW_CHS_CONFIG_REG =================================================== */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_CHK_ADDR_Pos (24UL) /*!< HW_CHS_CHK_ADDR (Bit 24) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_CHK_ADDR_Msk (0x1000000UL) /*!< HW_CHS_CHK_ADDR (Bitfield-Mask: 0x01) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_MST_TYPE_Pos (16UL) /*!< HW_CHS_MST_TYPE (Bit 16) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_MST_TYPE_Msk (0x1f0000UL) /*!< HW_CHS_MST_TYPE (Bitfield-Mask: 0x1f) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_PAR_TYPE_Pos (9UL) /*!< HW_CHS_PAR_TYPE (Bit 9) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_PAR_TYPE_Msk (0x600UL) /*!< HW_CHS_PAR_TYPE (Bitfield-Mask: 0x03) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_PATH_SEL_Pos (0UL) /*!< HW_CHS_PATH_SEL (Bit 0) */ + #define HW_ACC_HW_CHS_CONFIG_REG_HW_CHS_PATH_SEL_Msk (0x1fUL) /*!< HW_CHS_PATH_SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== HW_CHS_OP_EN_REG ==================================================== */ + #define HW_ACC_HW_CHS_OP_EN_REG_HW_CHS_OP_EN_Pos (0UL) /*!< HW_CHS_OP_EN (Bit 0) */ + #define HW_ACC_HW_CHS_OP_EN_REG_HW_CHS_OP_EN_Msk (0x1UL) /*!< HW_CHS_OP_EN (Bitfield-Mask: 0x01) */ +/* ================================================= HW_CHS_PSEUDO_VAL_REG ================================================= */ +/* ================================================== HW_CHS_REQ_CTRL_REG ================================================== */ + #define HW_ACC_HW_CHS_REQ_CTRL_REG_HW_CHS_REQ_START_Pos (1UL) /*!< HW_CHS_REQ_START (Bit 1) */ + #define HW_ACC_HW_CHS_REQ_CTRL_REG_HW_CHS_REQ_START_Msk (0x2UL) /*!< HW_CHS_REQ_START (Bitfield-Mask: 0x01) */ + #define HW_ACC_HW_CHS_REQ_CTRL_REG_HW_CHS_REQ_CLR_Pos (0UL) /*!< HW_CHS_REQ_CLR (Bit 0) */ + #define HW_ACC_HW_CHS_REQ_CTRL_REG_HW_CHS_REQ_CLR_Msk (0x1UL) /*!< HW_CHS_REQ_CLR (Bitfield-Mask: 0x01) */ +/* ==================================================== PRNG_OP_EN_REG ===================================================== */ + #define HW_ACC_PRNG_OP_EN_REG_PRNG_OP_EN_Pos (0UL) /*!< PRNG_OP_EN (Bit 0) */ + #define HW_ACC_PRNG_OP_EN_REG_PRNG_OP_EN_Msk (0x1UL) /*!< PRNG_OP_EN (Bitfield-Mask: 0x01) */ +/* =================================================== PRNG_PAR_TYPE_REG =================================================== */ + #define HW_ACC_PRNG_PAR_TYPE_REG_PRNG_PAR_TYPE_Pos (0UL) /*!< PRNG_PAR_TYPE (Bit 0) */ + #define HW_ACC_PRNG_PAR_TYPE_REG_PRNG_PAR_TYPE_Msk (0x3UL) /*!< PRNG_PAR_TYPE (Bitfield-Mask: 0x03) */ +/* =================================================== PRNG_REG_CAL_VAL ==================================================== */ + #define HW_ACC_PRNG_REG_CAL_VAL_PRNG_CAL_VAL_REG_Pos (0UL) /*!< PRNG_CAL_VAL_REG (Bit 0) */ + #define HW_ACC_PRNG_REG_CAL_VAL_PRNG_CAL_VAL_REG_Msk (0xffffffffUL) /*!< PRNG_CAL_VAL_REG (Bitfield-Mask: 0xffffffff) */ +/* =================================================== PRNG_REQ_CLR_REG ==================================================== */ + #define HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_GET_Pos (1UL) /*!< PRNG_REQ_GET (Bit 1) */ + #define HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_GET_Msk (0x2UL) /*!< PRNG_REQ_GET (Bitfield-Mask: 0x01) */ + #define HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_CLR_Pos (0UL) /*!< PRNG_REQ_CLR (Bit 0) */ + #define HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_CLR_Msk (0x1UL) /*!< PRNG_REQ_CLR (Bitfield-Mask: 0x01) */ +/* ===================================================== PRNG_SEED_REG ===================================================== */ + #define HW_ACC_PRNG_SEED_REG_PRNG_SEED_VAL_Pos (0UL) /*!< PRNG_SEED_VAL (Bit 0) */ + #define HW_ACC_PRNG_SEED_REG_PRNG_SEED_VAL_Msk (0x7fffffffUL) /*!< PRNG_SEED_VAL (Bitfield-Mask: 0x7fffffff) */ + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C_ACK_GENERAL_CALL_REG ================================================ */ + #define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */ + #define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_ACTIVITY_REG ================================================== */ + #define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */ + #define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_GEN_CALL_REG ================================================== */ + #define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */ + #define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_CLR_INTR_REG ==================================================== */ + #define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */ + #define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RD_REQ_REG =================================================== */ + #define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */ + #define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RX_DONE_REG ================================================== */ + #define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */ + #define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RX_OVER_REG ================================================== */ + #define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */ + #define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_RX_UNDER_REG ================================================== */ + #define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */ + #define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_START_DET_REG ================================================= */ + #define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */ + #define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_STOP_DET_REG ================================================== */ + #define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */ + #define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_TX_ABRT_REG ================================================== */ + #define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */ + #define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_TX_OVER_REG ================================================== */ + #define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */ + #define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_COMP_PARAM1_REG ================================================== */ + #define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL) /*!< IC_COMP_PARAM1 (Bit 0) */ + #define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffffffUL) /*!< IC_COMP_PARAM1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== I2C_COMP_TYPE_REG =================================================== */ + #define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL) /*!< IC_COMP_TYPE (Bit 0) */ + #define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffffffUL) /*!< IC_COMP_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= I2C_COMP_VERSION_REG ================================================== */ + #define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL) /*!< IC_COMP_VERSION (Bit 0) */ + #define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffffffUL) /*!< IC_COMP_VERSION (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== I2C_CON_REG ====================================================== */ + #define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */ + #define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */ + #define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */ + #define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */ + #define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */ + #define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */ + #define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */ + #define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */ + #define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */ + #define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */ + #define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */ + #define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_DATA_CMD_REG ==================================================== */ + #define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */ + #define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */ + #define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */ + #define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */ + #define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */ + #define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */ + #define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */ + #define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */ +/* ==================================================== I2C_DMA_CR_REG ===================================================== */ + #define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */ + #define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */ + #define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_DMA_RDLR_REG ==================================================== */ + #define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */ + #define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */ +/* =================================================== I2C_DMA_TDLR_REG ==================================================== */ + #define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */ + #define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */ +/* ==================================================== I2C_ENABLE_REG ===================================================== */ + #define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */ + #define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */ + #define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */ + #define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */ + #define I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_ENABLE_STATUS_REG ================================================= */ + #define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */ + #define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ + #define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */ + #define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */ + #define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_FS_SCL_HCNT_REG ================================================== */ + #define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */ + #define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_FS_SCL_LCNT_REG ================================================== */ + #define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ + #define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C_HS_MADDR_REG ==================================================== */ + #define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */ + #define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */ +/* ================================================== I2C_HS_SCL_HCNT_REG ================================================== */ + #define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */ + #define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_HS_SCL_LCNT_REG ================================================== */ + #define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */ + #define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C_IC_FS_SPKLEN_REG ================================================== */ + #define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */ + #define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================= I2C_IC_HS_SPKLEN_REG ================================================== */ + #define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */ + #define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */ +/* =================================================== I2C_INTR_MASK_REG =================================================== */ + #define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */ + #define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ + #define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ + #define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */ + #define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */ + #define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */ + #define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */ + #define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */ + #define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ + #define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_INTR_STAT_REG =================================================== */ + #define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ + #define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ + #define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ + #define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */ + #define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */ + #define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */ + #define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */ + #define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */ + #define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ + #define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_RAW_INTR_STAT_REG ================================================= */ + #define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ + #define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ + #define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */ + #define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */ + #define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */ + #define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */ + #define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */ + #define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C_RXFLR_REG ===================================================== */ + #define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */ + #define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */ +/* ===================================================== I2C_RX_TL_REG ===================================================== */ + #define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */ + #define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */ +/* ====================================================== I2C_SAR_REG ====================================================== */ + #define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */ + #define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */ +/* =================================================== I2C_SDA_HOLD_REG ==================================================== */ + #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */ + #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */ + #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */ + #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C_SDA_SETUP_REG =================================================== */ + #define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */ + #define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */ +/* ================================================== I2C_SS_SCL_HCNT_REG ================================================== */ + #define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */ + #define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_SS_SCL_LCNT_REG ================================================== */ + #define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */ + #define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== I2C_STATUS_REG ===================================================== */ + #define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */ + #define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */ + #define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */ + #define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */ + #define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */ + #define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */ + #define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */ + #define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */ + #define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */ + #define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */ + #define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */ + #define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */ + #define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ====================================================== I2C_TAR_REG ====================================================== */ + #define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */ + #define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */ + #define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */ + #define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */ +/* ===================================================== I2C_TXFLR_REG ===================================================== */ + #define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */ + #define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */ +/* ================================================ I2C_TX_ABRT_SOURCE_REG ================================================= */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */ + #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C_TX_TL_REG ===================================================== */ + #define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */ + #define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ I2C2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C2_ACK_GENERAL_CALL_REG =============================================== */ + #define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */ + #define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_ACTIVITY_REG ================================================= */ + #define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */ + #define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_GEN_CALL_REG ================================================= */ + #define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */ + #define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_CLR_INTR_REG =================================================== */ + #define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */ + #define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */ +/* ================================================== I2C2_CLR_RD_REQ_REG ================================================== */ + #define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */ + #define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_DONE_REG ================================================== */ + #define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */ + #define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_OVER_REG ================================================== */ + #define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */ + #define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_UNDER_REG ================================================= */ + #define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */ + #define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_CLR_START_DET_REG ================================================= */ + #define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */ + #define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_STOP_DET_REG ================================================= */ + #define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */ + #define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_TX_ABRT_REG ================================================== */ + #define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */ + #define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_TX_OVER_REG ================================================== */ + #define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */ + #define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_COMP_PARAM1_REG ================================================== */ + #define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL) /*!< IC_COMP_PARAM1 (Bit 0) */ + #define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffffffUL) /*!< IC_COMP_PARAM1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== I2C2_COMP_TYPE_REG =================================================== */ + #define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL) /*!< IC_COMP_TYPE (Bit 0) */ + #define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffffffUL) /*!< IC_COMP_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= I2C2_COMP_VERSION_REG ================================================= */ + #define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL) /*!< IC_COMP_VERSION (Bit 0) */ + #define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffffffUL) /*!< IC_COMP_VERSION (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== I2C2_CON_REG ====================================================== */ + #define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */ + #define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */ + #define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */ + #define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */ + #define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */ + #define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */ + #define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */ + #define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */ + #define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */ + #define I2C2_I2C2_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */ + #define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */ + #define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_DATA_CMD_REG =================================================== */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */ + #define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */ +/* ==================================================== I2C2_DMA_CR_REG ==================================================== */ + #define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */ + #define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */ + #define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_DMA_RDLR_REG =================================================== */ + #define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */ + #define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */ +/* =================================================== I2C2_DMA_TDLR_REG =================================================== */ + #define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */ + #define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */ +/* ==================================================== I2C2_ENABLE_REG ==================================================== */ + #define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */ + #define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */ + #define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */ + #define I2C2_I2C2_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_ENABLE_STATUS_REG ================================================= */ + #define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */ + #define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */ + #define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */ + #define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_FS_SCL_HCNT_REG ================================================== */ + #define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */ + #define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_FS_SCL_LCNT_REG ================================================== */ + #define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ + #define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C2_HS_MADDR_REG =================================================== */ + #define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */ + #define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */ +/* ================================================= I2C2_HS_SCL_HCNT_REG ================================================== */ + #define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */ + #define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_HS_SCL_LCNT_REG ================================================== */ + #define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */ + #define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_IC_FS_SPKLEN_REG ================================================= */ + #define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */ + #define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================= I2C2_IC_HS_SPKLEN_REG ================================================= */ + #define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */ + #define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================== I2C2_INTR_MASK_REG =================================================== */ + #define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */ + #define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ + #define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */ + #define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */ + #define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */ + #define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */ + #define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ + #define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================== I2C2_INTR_STAT_REG =================================================== */ + #define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ + #define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ + #define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */ + #define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */ + #define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */ + #define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */ + #define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ + #define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_RAW_INTR_STAT_REG ================================================= */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */ + #define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */ +/* ==================================================== I2C2_RXFLR_REG ===================================================== */ + #define I2C2_I2C2_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */ + #define I2C2_I2C2_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */ +/* ==================================================== I2C2_RX_TL_REG ===================================================== */ + #define I2C2_I2C2_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */ + #define I2C2_I2C2_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */ +/* ===================================================== I2C2_SAR_REG ====================================================== */ + #define I2C2_I2C2_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */ + #define I2C2_I2C2_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */ +/* =================================================== I2C2_SDA_HOLD_REG =================================================== */ + #define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */ + #define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */ + #define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */ + #define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C2_SDA_SETUP_REG =================================================== */ + #define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */ + #define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */ +/* ================================================= I2C2_SS_SCL_HCNT_REG ================================================== */ + #define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */ + #define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_SS_SCL_LCNT_REG ================================================== */ + #define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */ + #define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== I2C2_STATUS_REG ==================================================== */ + #define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */ + #define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */ + #define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */ + #define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */ + #define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */ + #define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */ + #define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */ + #define I2C2_I2C2_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */ + #define I2C2_I2C2_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */ + #define I2C2_I2C2_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */ + #define I2C2_I2C2_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */ + #define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C2_TAR_REG ====================================================== */ + #define I2C2_I2C2_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */ + #define I2C2_I2C2_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */ + #define I2C2_I2C2_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */ + #define I2C2_I2C2_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */ +/* ==================================================== I2C2_TXFLR_REG ===================================================== */ + #define I2C2_I2C2_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */ + #define I2C2_I2C2_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */ +/* ================================================ I2C2_TX_ABRT_SOURCE_REG ================================================ */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */ + #define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ +/* ==================================================== I2C2_TX_TL_REG ===================================================== */ + #define I2C2_I2C2_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */ + #define I2C2_I2C2_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ KDMA ================ */ +/* =========================================================================================================================== */ + +/* ============================================== KDMA_AHB_HPROT_11_TO_8_REG =============================================== */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH11_SRC_HPROT_Pos (28UL) /*!< CH11_SRC_HPROT (Bit 28) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH11_SRC_HPROT_Msk (0xf0000000UL) /*!< CH11_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH11_DST_HPROT_Pos (24UL) /*!< CH11_DST_HPROT (Bit 24) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH11_DST_HPROT_Msk (0xf000000UL) /*!< CH11_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH10_SRC_HPROT_Pos (20UL) /*!< CH10_SRC_HPROT (Bit 20) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH10_SRC_HPROT_Msk (0xf00000UL) /*!< CH10_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH10_DST_HPROT_Pos (16UL) /*!< CH10_DST_HPROT (Bit 16) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH10_DST_HPROT_Msk (0xf0000UL) /*!< CH10_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH9_SRC_HPROT_Pos (12UL) /*!< CH9_SRC_HPROT (Bit 12) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH9_SRC_HPROT_Msk (0xf000UL) /*!< CH9_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH9_DST_HPROT_Pos (8UL) /*!< CH9_DST_HPROT (Bit 8) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH9_DST_HPROT_Msk (0xf00UL) /*!< CH9_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH8_SRC_HPROT_Pos (4UL) /*!< CH8_SRC_HPROT (Bit 4) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH8_SRC_HPROT_Msk (0xf0UL) /*!< CH8_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH8_DST_HPROT_Pos (0UL) /*!< CH8_DST_HPROT (Bit 0) */ + #define KDMA_KDMA_AHB_HPROT_11_TO_8_REG_CH8_DST_HPROT_Msk (0xfUL) /*!< CH8_DST_HPROT (Bitfield-Mask: 0x0f) */ +/* =============================================== KDMA_AHB_HPROT_3_TO_0_REG =============================================== */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH3_SRC_HPROT_Pos (28UL) /*!< CH3_SRC_HPROT (Bit 28) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH3_SRC_HPROT_Msk (0xf0000000UL) /*!< CH3_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH3_DST_HPROT_Pos (24UL) /*!< CH3_DST_HPROT (Bit 24) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH3_DST_HPROT_Msk (0xf000000UL) /*!< CH3_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH2_SRC_HPROT_Pos (20UL) /*!< CH2_SRC_HPROT (Bit 20) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH2_SRC_HPROT_Msk (0xf00000UL) /*!< CH2_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH2_DST_HPROT_Pos (16UL) /*!< CH2_DST_HPROT (Bit 16) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH2_DST_HPROT_Msk (0xf0000UL) /*!< CH2_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH1_SRC_HPROT_Pos (12UL) /*!< CH1_SRC_HPROT (Bit 12) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH1_SRC_HPROT_Msk (0xf000UL) /*!< CH1_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH1_DST_HPROT_Pos (8UL) /*!< CH1_DST_HPROT (Bit 8) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH1_DST_HPROT_Msk (0xf00UL) /*!< CH1_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH0_SRC_HPROT_Pos (4UL) /*!< CH0_SRC_HPROT (Bit 4) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH0_SRC_HPROT_Msk (0xf0UL) /*!< CH0_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH0_DST_HPROT_Pos (0UL) /*!< CH0_DST_HPROT (Bit 0) */ + #define KDMA_KDMA_AHB_HPROT_3_TO_0_REG_CH0_DST_HPROT_Msk (0xfUL) /*!< CH0_DST_HPROT (Bitfield-Mask: 0x0f) */ +/* =============================================== KDMA_AHB_HPROT_7_TO_4_REG =============================================== */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH7_SRC_HPROT_Pos (28UL) /*!< CH7_SRC_HPROT (Bit 28) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH7_SRC_HPROT_Msk (0xf0000000UL) /*!< CH7_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH7_DST_HPROT_Pos (24UL) /*!< CH7_DST_HPROT (Bit 24) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH7_DST_HPROT_Msk (0xf000000UL) /*!< CH7_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH6_SRC_HPROT_Pos (20UL) /*!< CH6_SRC_HPROT (Bit 20) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH6_SRC_HPROT_Msk (0xf00000UL) /*!< CH6_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH6_DST_HPROT_Pos (16UL) /*!< CH6_DST_HPROT (Bit 16) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH6_DST_HPROT_Msk (0xf0000UL) /*!< CH6_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH5_SRC_HPROT_Pos (12UL) /*!< CH5_SRC_HPROT (Bit 12) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH5_SRC_HPROT_Msk (0xf000UL) /*!< CH5_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH5_DST_HPROT_Pos (8UL) /*!< CH5_DST_HPROT (Bit 8) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH5_DST_HPROT_Msk (0xf00UL) /*!< CH5_DST_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH4_SRC_HPROT_Pos (4UL) /*!< CH4_SRC_HPROT (Bit 4) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH4_SRC_HPROT_Msk (0xf0UL) /*!< CH4_SRC_HPROT (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH4_DST_HPROT_Pos (0UL) /*!< CH4_DST_HPROT (Bit 0) */ + #define KDMA_KDMA_AHB_HPROT_7_TO_4_REG_CH4_DST_HPROT_Msk (0xfUL) /*!< CH4_DST_HPROT (Bitfield-Mask: 0x0f) */ +/* ============================================= KDMA_CFG_DESCRIPTOR_ADDR_REG ============================================== */ + #define KDMA_KDMA_CFG_DESCRIPTOR_ADDR_REG_CFG_DESCRIPTOR_ADDR_Pos (0UL) /*!< CFG_DESCRIPTOR_ADDR (Bit 0) */ + #define KDMA_KDMA_CFG_DESCRIPTOR_ADDR_REG_CFG_DESCRIPTOR_ADDR_Msk (0xffffffffUL) /*!< CFG_DESCRIPTOR_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ KDMA_CHANNEL_ENABLE_REG ================================================ */ + #define KDMA_KDMA_CHANNEL_ENABLE_REG_CHANNEL_ENABLE_Pos (0UL) /*!< CHANNEL_ENABLE (Bit 0) */ + #define KDMA_KDMA_CHANNEL_ENABLE_REG_CHANNEL_ENABLE_Msk (0xfffUL) /*!< CHANNEL_ENABLE (Bitfield-Mask: 0xfff) */ +/* ==================================================== KDMA_ENABLE_REG ==================================================== */ + #define KDMA_KDMA_ENABLE_REG_DMA_ENABLE_Pos (0UL) /*!< DMA_ENABLE (Bit 0) */ + #define KDMA_KDMA_ENABLE_REG_DMA_ENABLE_Msk (0x1UL) /*!< DMA_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= KDMA_IRQ_DONE_CLR_REG ================================================= */ + #define KDMA_KDMA_IRQ_DONE_CLR_REG_IRQ_DONE_CLR_Pos (0UL) /*!< IRQ_DONE_CLR (Bit 0) */ + #define KDMA_KDMA_IRQ_DONE_CLR_REG_IRQ_DONE_CLR_Msk (0xfffUL) /*!< IRQ_DONE_CLR (Bitfield-Mask: 0xfff) */ +/* =================================================== KDMA_IRQ_DONE_REG =================================================== */ + #define KDMA_KDMA_IRQ_DONE_REG_IRQ_DONE_Pos (0UL) /*!< IRQ_DONE (Bit 0) */ + #define KDMA_KDMA_IRQ_DONE_REG_IRQ_DONE_Msk (0xfffUL) /*!< IRQ_DONE (Bitfield-Mask: 0xfff) */ +/* ================================================ KDMA_IRQ_DONE_TYPE_REG ================================================= */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL11_DONE_TYPE_Pos (22UL) /*!< CHANNEL11_DONE_TYPE (Bit 22) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL11_DONE_TYPE_Msk (0xc00000UL) /*!< CHANNEL11_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL10_DONE_TYPE_Pos (20UL) /*!< CHANNEL10_DONE_TYPE (Bit 20) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL10_DONE_TYPE_Msk (0x300000UL) /*!< CHANNEL10_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL9_DONE_TYPE_Pos (18UL) /*!< CHANNEL9_DONE_TYPE (Bit 18) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL9_DONE_TYPE_Msk (0xc0000UL) /*!< CHANNEL9_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL8_DONE_TYPE_Pos (16UL) /*!< CHANNEL8_DONE_TYPE (Bit 16) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL8_DONE_TYPE_Msk (0x30000UL) /*!< CHANNEL8_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL7_DONE_TYPE_Pos (14UL) /*!< CHANNEL7_DONE_TYPE (Bit 14) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL7_DONE_TYPE_Msk (0xc000UL) /*!< CHANNEL7_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL6_DONE_TYPE_Pos (12UL) /*!< CHANNEL6_DONE_TYPE (Bit 12) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL6_DONE_TYPE_Msk (0x3000UL) /*!< CHANNEL6_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL5_DONE_TYPE_Pos (10UL) /*!< CHANNEL5_DONE_TYPE (Bit 10) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL5_DONE_TYPE_Msk (0xc00UL) /*!< CHANNEL5_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL4_DONE_TYPE_Pos (8UL) /*!< CHANNEL4_DONE_TYPE (Bit 8) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL4_DONE_TYPE_Msk (0x300UL) /*!< CHANNEL4_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL3_DONE_TYPE_Pos (6UL) /*!< CHANNEL3_DONE_TYPE (Bit 6) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL3_DONE_TYPE_Msk (0xc0UL) /*!< CHANNEL3_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL2_DONE_TYPE_Pos (4UL) /*!< CHANNEL2_DONE_TYPE (Bit 4) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL2_DONE_TYPE_Msk (0x30UL) /*!< CHANNEL2_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL1_DONE_TYPE_Pos (2UL) /*!< CHANNEL1_DONE_TYPE (Bit 2) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL1_DONE_TYPE_Msk (0xcUL) /*!< CHANNEL1_DONE_TYPE (Bitfield-Mask: 0x03) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL0_DONE_TYPE_Pos (0UL) /*!< CHANNEL0_DONE_TYPE (Bit 0) */ + #define KDMA_KDMA_IRQ_DONE_TYPE_REG_CHANNEL0_DONE_TYPE_Msk (0x3UL) /*!< CHANNEL0_DONE_TYPE (Bitfield-Mask: 0x03) */ +/* ================================================= KDMA_IRQ_ERR_CLR_REG ================================================== */ + #define KDMA_KDMA_IRQ_ERR_CLR_REG_IRQ_ERR_CLR_Pos (0UL) /*!< IRQ_ERR_CLR (Bit 0) */ + #define KDMA_KDMA_IRQ_ERR_CLR_REG_IRQ_ERR_CLR_Msk (0xfffUL) /*!< IRQ_ERR_CLR (Bitfield-Mask: 0xfff) */ +/* =================================================== KDMA_IRQ_ERR_REG ==================================================== */ + #define KDMA_KDMA_IRQ_ERR_REG_IRQ_ERR_Pos (0UL) /*!< IRQ_ERR (Bit 0) */ + #define KDMA_KDMA_IRQ_ERR_REG_IRQ_ERR_Msk (0xfffUL) /*!< IRQ_ERR (Bitfield-Mask: 0xfff) */ +/* ================================================= KDMA_LLI_COUNTER_REG ================================================== */ + #define KDMA_KDMA_LLI_COUNTER_REG_LAST_DONE_CHANNEL_Pos (16UL) /*!< LAST_DONE_CHANNEL (Bit 16) */ + #define KDMA_KDMA_LLI_COUNTER_REG_LAST_DONE_CHANNEL_Msk (0xf0000UL) /*!< LAST_DONE_CHANNEL (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_LLI_COUNTER_REG_LLI_COUNTER_Pos (0UL) /*!< LLI_COUNTER (Bit 0) */ + #define KDMA_KDMA_LLI_COUNTER_REG_LLI_COUNTER_Msk (0xffffUL) /*!< LLI_COUNTER (Bitfield-Mask: 0xffff) */ +/* ==================================================== KDMA_RESET_REG ===================================================== */ + #define KDMA_KDMA_RESET_REG_DMA_RESET_Pos (0UL) /*!< DMA_RESET (Bit 0) */ + #define KDMA_KDMA_RESET_REG_DMA_RESET_Msk (0x1UL) /*!< DMA_RESET (Bitfield-Mask: 0x01) */ +/* ================================================ KDMA_STATUS_COUNTER_REG ================================================ */ + #define KDMA_KDMA_STATUS_COUNTER_REG_ARB_LAST_FLAG_Pos (31UL) /*!< ARB_LAST_FLAG (Bit 31) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_ARB_LAST_FLAG_Msk (0x80000000UL) /*!< ARB_LAST_FLAG (Bitfield-Mask: 0x01) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_ARB_DONE_COUNTER_Pos (16UL) /*!< ARB_DONE_COUNTER (Bit 16) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_ARB_DONE_COUNTER_Msk (0x7fff0000UL) /*!< ARB_DONE_COUNTER (Bitfield-Mask: 0x7fff) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_TRANSFER_LAST_FLAG_Pos (15UL) /*!< TRANSFER_LAST_FLAG (Bit 15) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_TRANSFER_LAST_FLAG_Msk (0x8000UL) /*!< TRANSFER_LAST_FLAG (Bitfield-Mask: 0x01) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_TRANSFER_DONE_COUNTER_Pos (0UL) /*!< TRANSFER_DONE_COUNTER (Bit 0) */ + #define KDMA_KDMA_STATUS_COUNTER_REG_TRANSFER_DONE_COUNTER_Msk (0x7fffUL) /*!< TRANSFER_DONE_COUNTER (Bitfield-Mask: 0x7fff) */ +/* ============================================= KDMA_STATUS_DESC_ADDR_PRE_REG ============================================= */ + #define KDMA_KDMA_STATUS_DESC_ADDR_PRE_REG_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define KDMA_KDMA_STATUS_DESC_ADDR_PRE_REG_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== KDMA_STATUS_DESC_ADDR_REG =============================================== */ + #define KDMA_KDMA_STATUS_DESC_ADDR_REG_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define KDMA_KDMA_STATUS_DESC_ADDR_REG_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= KDMA_STATUS_DESC_REG ================================================== */ + #define KDMA_KDMA_STATUS_DESC_REG_TASK_DESCRIPTOR_Pos (0UL) /*!< TASK_DESCRIPTOR (Bit 0) */ + #define KDMA_KDMA_STATUS_DESC_REG_TASK_DESCRIPTOR_Msk (0xffffffffUL) /*!< TASK_DESCRIPTOR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== KDMA_STATUS_REG ==================================================== */ + #define KDMA_KDMA_STATUS_REG_CURRENT_STATE_Pos (20UL) /*!< CURRENT_STATE (Bit 20) */ + #define KDMA_KDMA_STATUS_REG_CURRENT_STATE_Msk (0xf00000UL) /*!< CURRENT_STATE (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_STATUS_REG_CURRENT_ACTIVE_CH_Pos (16UL) /*!< CURRENT_ACTIVE_CH (Bit 16) */ + #define KDMA_KDMA_STATUS_REG_CURRENT_ACTIVE_CH_Msk (0xf0000UL) /*!< CURRENT_ACTIVE_CH (Bitfield-Mask: 0x0f) */ + #define KDMA_KDMA_STATUS_REG_PENDING_CH_Pos (0UL) /*!< PENDING_CH (Bit 0) */ + #define KDMA_KDMA_STATUS_REG_PENDING_CH_Msk (0xfffUL) /*!< PENDING_CH (Bitfield-Mask: 0xfff) */ +/* ================================================== KDMA_SW_REQUEST_REG ================================================== */ + #define KDMA_KDMA_SW_REQUEST_REG_SW_REQUEST_Pos (0UL) /*!< SW_REQUEST (Bit 0) */ + #define KDMA_KDMA_SW_REQUEST_REG_SW_REQUEST_Msk (0xfffUL) /*!< SW_REQUEST (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ MEMCTRL ================ */ +/* =========================================================================================================================== */ + +/* ================================================== MEMCTRL_AUD_ARB_REG ================================================== */ + #define MEMCTRL_MEMCTRL_AUD_ARB_REG_APB_AHB_CPUS_PRIO_Pos (1UL) /*!< APB_AHB_CPUS_PRIO (Bit 1) */ + #define MEMCTRL_MEMCTRL_AUD_ARB_REG_APB_AHB_CPUS_PRIO_Msk (0x2UL) /*!< APB_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_AUD_ARB_REG_APB_AHB_DMA_PRIO_Pos (0UL) /*!< APB_AHB_DMA_PRIO (Bit 0) */ + #define MEMCTRL_MEMCTRL_AUD_ARB_REG_APB_AHB_DMA_PRIO_Msk (0x1UL) /*!< APB_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ +/* ================================================= MEMCTRL_CC312_ARB_REG ================================================= */ + #define MEMCTRL_MEMCTRL_CC312_ARB_REG_APB_AHB_CPUS_PRIO_Pos (1UL) /*!< APB_AHB_CPUS_PRIO (Bit 1) */ + #define MEMCTRL_MEMCTRL_CC312_ARB_REG_APB_AHB_CPUS_PRIO_Msk (0x2UL) /*!< APB_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_CC312_ARB_REG_APB_AHB_DMA_PRIO_Pos (0UL) /*!< APB_AHB_DMA_PRIO (Bit 0) */ + #define MEMCTRL_MEMCTRL_CC312_ARB_REG_APB_AHB_DMA_PRIO_Msk (0x1UL) /*!< APB_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ +/* =============================================== MEMCTRL_CIS_BASE_ADDR_REG =============================================== */ + #define MEMCTRL_MEMCTRL_CIS_BASE_ADDR_REG_MEM_CIS_BASE_ADDR_Pos (0UL) /*!< MEM_CIS_BASE_ADDR (Bit 0) */ + #define MEMCTRL_MEMCTRL_CIS_BASE_ADDR_REG_MEM_CIS_BASE_ADDR_Msk (0x7fffffUL) /*!< MEM_CIS_BASE_ADDR (Bitfield-Mask: 0x7fffff) */ +/* ============================================== MEMCTRL_DYNAMIC_CLK_ON_REG =============================================== */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_MEM_UNIT_Pos (5UL) /*!< MEM_UNIT (Bit 5) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_MEM_UNIT_Msk (0x20UL) /*!< MEM_UNIT (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_MMI2MEM_Pos (3UL) /*!< MMI2MEM (Bit 3) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_MMI2MEM_Msk (0x8UL) /*!< MMI2MEM (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_ARBITER_Pos (1UL) /*!< ARBITER (Bit 1) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_ARBITER_Msk (0x2UL) /*!< ARBITER (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_AHB2MEM_Pos (0UL) /*!< AHB2MEM (Bit 0) */ + #define MEMCTRL_MEMCTRL_DYNAMIC_CLK_ON_REG_AHB2MEM_Msk (0x1UL) /*!< AHB2MEM (Bitfield-Mask: 0x01) */ +/* ================================================ MEMCTRL_MST_CLK_EN_REG ================================================= */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CIS_CLK_EN_Pos (5UL) /*!< MST_CIS_CLK_EN (Bit 5) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CIS_CLK_EN_Msk (0x20UL) /*!< MST_CIS_CLK_EN (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_WIFI_HSU_CLK_EN_Pos (4UL) /*!< MST_WIFI_HSU_CLK_EN (Bit 4) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_WIFI_HSU_CLK_EN_Msk (0x10UL) /*!< MST_WIFI_HSU_CLK_EN (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_WIFI_MAC_CLK_EN_Pos (3UL) /*!< MST_WIFI_MAC_CLK_EN (Bit 3) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_WIFI_MAC_CLK_EN_Msk (0x8UL) /*!< MST_WIFI_MAC_CLK_EN (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_DMA_CLK_EN_Pos (2UL) /*!< MST_DMA_CLK_EN (Bit 2) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_DMA_CLK_EN_Msk (0x4UL) /*!< MST_DMA_CLK_EN (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CPUS_CLK_EN_Pos (1UL) /*!< MST_CPUS_CLK_EN (Bit 1) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CPUS_CLK_EN_Msk (0x2UL) /*!< MST_CPUS_CLK_EN (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CPUC_CLK_EN_Pos (0UL) /*!< MST_CPUC_CLK_EN (Bit 0) */ + #define MEMCTRL_MEMCTRL_MST_CLK_EN_REG_MST_CPUC_CLK_EN_Msk (0x1UL) /*!< MST_CPUC_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================= MEMCTRL_PRIO_ARB_REG ================================================== */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CIS_RAM_Pos (10UL) /*!< PRIO_ARB_CIS_RAM (Bit 10) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CIS_RAM_Msk (0xc00UL) /*!< PRIO_ARB_CIS_RAM (Bitfield-Mask: 0x03) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_WIFI_HSU_RAM_Pos (8UL) /*!< PRIO_ARB_WIFI_HSU_RAM (Bit 8) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_WIFI_HSU_RAM_Msk (0x300UL) /*!< PRIO_ARB_WIFI_HSU_RAM (Bitfield-Mask: 0x03) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_WIFI_MAC_RAM_Pos (6UL) /*!< PRIO_ARB_WIFI_MAC_RAM (Bit 6) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_WIFI_MAC_RAM_Msk (0xc0UL) /*!< PRIO_ARB_WIFI_MAC_RAM (Bitfield-Mask: 0x03) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_DMA_RAM_Pos (4UL) /*!< PRIO_ARB_DMA_RAM (Bit 4) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_DMA_RAM_Msk (0x30UL) /*!< PRIO_ARB_DMA_RAM (Bitfield-Mask: 0x03) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUS_RAM_Pos (2UL) /*!< PRIO_ARB_CPUS_RAM (Bit 2) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUS_RAM_Msk (0xcUL) /*!< PRIO_ARB_CPUS_RAM (Bitfield-Mask: 0x03) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUC_RAM_Pos (0UL) /*!< PRIO_ARB_CPUC_RAM (Bit 0) */ + #define MEMCTRL_MEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUC_RAM_Msk (0x3UL) /*!< PRIO_ARB_CPUC_RAM (Bitfield-Mask: 0x03) */ +/* =================================================== MEMCTRL_STALL_REG =================================================== */ + #define MEMCTRL_MEMCTRL_STALL_REG_CIS_MAX_STALL_Pos (20UL) /*!< CIS_MAX_STALL (Bit 20) */ + #define MEMCTRL_MEMCTRL_STALL_REG_CIS_MAX_STALL_Msk (0xf00000UL) /*!< CIS_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define MEMCTRL_MEMCTRL_STALL_REG_WIFI_HSU_MAX_STALL_Pos (16UL) /*!< WIFI_HSU_MAX_STALL (Bit 16) */ + #define MEMCTRL_MEMCTRL_STALL_REG_WIFI_HSU_MAX_STALL_Msk (0xf0000UL) /*!< WIFI_HSU_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define MEMCTRL_MEMCTRL_STALL_REG_WIFI_MAC_MAX_STALL_Pos (12UL) /*!< WIFI_MAC_MAX_STALL (Bit 12) */ + #define MEMCTRL_MEMCTRL_STALL_REG_WIFI_MAC_MAX_STALL_Msk (0xf000UL) /*!< WIFI_MAC_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_DMA_MAX_STALL_Pos (8UL) /*!< AHB_DMA_MAX_STALL (Bit 8) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_DMA_MAX_STALL_Msk (0xf00UL) /*!< AHB_DMA_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_CPUS_MAX_STALL_Pos (4UL) /*!< AHB_CPUS_MAX_STALL (Bit 4) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_CPUS_MAX_STALL_Msk (0xf0UL) /*!< AHB_CPUS_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_CPUC_MAX_STALL_Pos (0UL) /*!< AHB_CPUC_MAX_STALL (Bit 0) */ + #define MEMCTRL_MEMCTRL_STALL_REG_AHB_CPUC_MAX_STALL_Msk (0xfUL) /*!< AHB_CPUC_MAX_STALL (Bitfield-Mask: 0x0f) */ +/* ============================================== MEMCTRL_STATIC_CLK_OFF_REG =============================================== */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM23_Pos (23UL) /*!< SRAM23 (Bit 23) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM23_Msk (0x800000UL) /*!< SRAM23 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM22_Pos (22UL) /*!< SRAM22 (Bit 22) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM22_Msk (0x400000UL) /*!< SRAM22 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM21_Pos (21UL) /*!< SRAM21 (Bit 21) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM21_Msk (0x200000UL) /*!< SRAM21 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM20_Pos (20UL) /*!< SRAM20 (Bit 20) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM20_Msk (0x100000UL) /*!< SRAM20 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM19_Pos (19UL) /*!< SRAM19 (Bit 19) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM19_Msk (0x80000UL) /*!< SRAM19 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM18_Pos (18UL) /*!< SRAM18 (Bit 18) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM18_Msk (0x40000UL) /*!< SRAM18 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM17_Pos (17UL) /*!< SRAM17 (Bit 17) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM17_Msk (0x20000UL) /*!< SRAM17 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM16_Pos (16UL) /*!< SRAM16 (Bit 16) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM16_Msk (0x10000UL) /*!< SRAM16 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM15_Pos (15UL) /*!< SRAM15 (Bit 15) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM15_Msk (0x8000UL) /*!< SRAM15 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM14_Pos (14UL) /*!< SRAM14 (Bit 14) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM14_Msk (0x4000UL) /*!< SRAM14 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM13_Pos (13UL) /*!< SRAM13 (Bit 13) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM13_Msk (0x2000UL) /*!< SRAM13 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM12_Pos (12UL) /*!< SRAM12 (Bit 12) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM12_Msk (0x1000UL) /*!< SRAM12 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM11_Pos (11UL) /*!< SRAM11 (Bit 11) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM11_Msk (0x800UL) /*!< SRAM11 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM10_Pos (10UL) /*!< SRAM10 (Bit 10) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM10_Msk (0x400UL) /*!< SRAM10 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM9_Pos (9UL) /*!< SRAM9 (Bit 9) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM9_Msk (0x200UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM8_Pos (8UL) /*!< SRAM8 (Bit 8) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM8_Msk (0x100UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM7_Pos (7UL) /*!< SRAM7 (Bit 7) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM7_Msk (0x80UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM6_Pos (6UL) /*!< SRAM6 (Bit 6) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM6_Msk (0x40UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM5_Pos (5UL) /*!< SRAM5 (Bit 5) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM5_Msk (0x20UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM4_Pos (4UL) /*!< SRAM4 (Bit 4) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM4_Msk (0x10UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM3_Pos (3UL) /*!< SRAM3 (Bit 3) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM3_Msk (0x8UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM2_Pos (2UL) /*!< SRAM2 (Bit 2) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM2_Msk (0x4UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM1_Pos (1UL) /*!< SRAM1 (Bit 1) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM1_Msk (0x2UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM0_Pos (0UL) /*!< SRAM0 (Bit 0) */ + #define MEMCTRL_MEMCTRL_STATIC_CLK_OFF_REG_SRAM0_Msk (0x1UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +/* ================================================== MEMCTRL_STATUS_REG =================================================== */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM23_OFF_BUT_ACCESS_Pos (23UL) /*!< RAM23_OFF_BUT_ACCESS (Bit 23) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM23_OFF_BUT_ACCESS_Msk (0x800000UL) /*!< RAM23_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM22_OFF_BUT_ACCESS_Pos (22UL) /*!< RAM22_OFF_BUT_ACCESS (Bit 22) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM22_OFF_BUT_ACCESS_Msk (0x400000UL) /*!< RAM22_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM21_OFF_BUT_ACCESS_Pos (21UL) /*!< RAM21_OFF_BUT_ACCESS (Bit 21) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM21_OFF_BUT_ACCESS_Msk (0x200000UL) /*!< RAM21_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM20_OFF_BUT_ACCESS_Pos (20UL) /*!< RAM20_OFF_BUT_ACCESS (Bit 20) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM20_OFF_BUT_ACCESS_Msk (0x100000UL) /*!< RAM20_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM19_OFF_BUT_ACCESS_Pos (19UL) /*!< RAM19_OFF_BUT_ACCESS (Bit 19) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM19_OFF_BUT_ACCESS_Msk (0x80000UL) /*!< RAM19_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM18_OFF_BUT_ACCESS_Pos (18UL) /*!< RAM18_OFF_BUT_ACCESS (Bit 18) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM18_OFF_BUT_ACCESS_Msk (0x40000UL) /*!< RAM18_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM17_OFF_BUT_ACCESS_Pos (17UL) /*!< RAM17_OFF_BUT_ACCESS (Bit 17) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM17_OFF_BUT_ACCESS_Msk (0x20000UL) /*!< RAM17_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM16_OFF_BUT_ACCESS_Pos (16UL) /*!< RAM16_OFF_BUT_ACCESS (Bit 16) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM16_OFF_BUT_ACCESS_Msk (0x10000UL) /*!< RAM16_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM15_OFF_BUT_ACCESS_Pos (15UL) /*!< RAM15_OFF_BUT_ACCESS (Bit 15) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM15_OFF_BUT_ACCESS_Msk (0x8000UL) /*!< RAM15_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM14_OFF_BUT_ACCESS_Pos (14UL) /*!< RAM14_OFF_BUT_ACCESS (Bit 14) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM14_OFF_BUT_ACCESS_Msk (0x4000UL) /*!< RAM14_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM13_OFF_BUT_ACCESS_Pos (13UL) /*!< RAM13_OFF_BUT_ACCESS (Bit 13) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM13_OFF_BUT_ACCESS_Msk (0x2000UL) /*!< RAM13_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM12_OFF_BUT_ACCESS_Pos (12UL) /*!< RAM12_OFF_BUT_ACCESS (Bit 12) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM12_OFF_BUT_ACCESS_Msk (0x1000UL) /*!< RAM12_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM11_OFF_BUT_ACCESS_Pos (11UL) /*!< RAM11_OFF_BUT_ACCESS (Bit 11) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM11_OFF_BUT_ACCESS_Msk (0x800UL) /*!< RAM11_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM10_OFF_BUT_ACCESS_Pos (10UL) /*!< RAM10_OFF_BUT_ACCESS (Bit 10) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM10_OFF_BUT_ACCESS_Msk (0x400UL) /*!< RAM10_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM9_OFF_BUT_ACCESS_Pos (9UL) /*!< RAM9_OFF_BUT_ACCESS (Bit 9) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM9_OFF_BUT_ACCESS_Msk (0x200UL) /*!< RAM9_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM8_OFF_BUT_ACCESS_Pos (8UL) /*!< RAM8_OFF_BUT_ACCESS (Bit 8) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM8_OFF_BUT_ACCESS_Msk (0x100UL) /*!< RAM8_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM7_OFF_BUT_ACCESS_Pos (7UL) /*!< RAM7_OFF_BUT_ACCESS (Bit 7) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM7_OFF_BUT_ACCESS_Msk (0x80UL) /*!< RAM7_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM6_OFF_BUT_ACCESS_Pos (6UL) /*!< RAM6_OFF_BUT_ACCESS (Bit 6) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM6_OFF_BUT_ACCESS_Msk (0x40UL) /*!< RAM6_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM5_OFF_BUT_ACCESS_Pos (5UL) /*!< RAM5_OFF_BUT_ACCESS (Bit 5) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM5_OFF_BUT_ACCESS_Msk (0x20UL) /*!< RAM5_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM4_OFF_BUT_ACCESS_Pos (4UL) /*!< RAM4_OFF_BUT_ACCESS (Bit 4) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM4_OFF_BUT_ACCESS_Msk (0x10UL) /*!< RAM4_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM3_OFF_BUT_ACCESS_Pos (3UL) /*!< RAM3_OFF_BUT_ACCESS (Bit 3) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM3_OFF_BUT_ACCESS_Msk (0x8UL) /*!< RAM3_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM2_OFF_BUT_ACCESS_Pos (2UL) /*!< RAM2_OFF_BUT_ACCESS (Bit 2) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM2_OFF_BUT_ACCESS_Msk (0x4UL) /*!< RAM2_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM1_OFF_BUT_ACCESS_Pos (1UL) /*!< RAM1_OFF_BUT_ACCESS (Bit 1) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM1_OFF_BUT_ACCESS_Msk (0x2UL) /*!< RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM0_OFF_BUT_ACCESS_Pos (0UL) /*!< RAM0_OFF_BUT_ACCESS (Bit 0) */ + #define MEMCTRL_MEMCTRL_STATUS_REG_RAM0_OFF_BUT_ACCESS_Msk (0x1UL) /*!< RAM0_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +/* ================================================== MEMCTRL_SYS_ARB_REG ================================================== */ + #define MEMCTRL_MEMCTRL_SYS_ARB_REG_APB_AHB_CPUS_PRIO_Pos (1UL) /*!< APB_AHB_CPUS_PRIO (Bit 1) */ + #define MEMCTRL_MEMCTRL_SYS_ARB_REG_APB_AHB_CPUS_PRIO_Msk (0x2UL) /*!< APB_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ + #define MEMCTRL_MEMCTRL_SYS_ARB_REG_APB_AHB_DMA_PRIO_Pos (0UL) /*!< APB_AHB_DMA_PRIO (Bit 0) */ + #define MEMCTRL_MEMCTRL_SYS_ARB_REG_APB_AHB_DMA_PRIO_Msk (0x1UL) /*!< APB_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OQSPIF ================ */ +/* =========================================================================================================================== */ + +/* ================================================== OQSPIF_BURSTBRK_REG ================================================== */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_EN_Pos (23UL) /*!< OSPIC_BRK_EN (Bit 23) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_EN_Msk (0x800000UL) /*!< OSPIC_BRK_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_SEC_HF_DS_Pos (22UL) /*!< OSPIC_SEC_HF_DS (Bit 22) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_SEC_HF_DS_Msk (0x400000UL) /*!< OSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_TX_MD_Pos (20UL) /*!< OSPIC_BRK_TX_MD (Bit 20) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_TX_MD_Msk (0x300000UL) /*!< OSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_SZ_Pos (16UL) /*!< OSPIC_BRK_SZ (Bit 16) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_SZ_Msk (0xf0000UL) /*!< OSPIC_BRK_SZ (Bitfield-Mask: 0x0f) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_WRD_Pos (0UL) /*!< OSPIC_BRK_WRD (Bit 0) */ + #define OQSPIF_OQSPIF_BURSTBRK_REG_OSPIC_BRK_WRD_Msk (0xffffUL) /*!< OSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */ +/* ================================================= OQSPIF_BURSTCMDA_REG ================================================== */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_DMY_TX_MD_Pos (30UL) /*!< OSPIC_DMY_TX_MD (Bit 30) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< OSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_EXT_TX_MD_Pos (28UL) /*!< OSPIC_EXT_TX_MD (Bit 28) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< OSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_ADR_TX_MD_Pos (26UL) /*!< OSPIC_ADR_TX_MD (Bit 26) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< OSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_TX_MD_Pos (24UL) /*!< OSPIC_INST_TX_MD (Bit 24) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< OSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_EXT_BYTE_Pos (16UL) /*!< OSPIC_EXT_BYTE (Bit 16) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< OSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_WB_Pos (8UL) /*!< OSPIC_INST_WB (Bit 8) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_WB_Msk (0xff00UL) /*!< OSPIC_INST_WB (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_Pos (0UL) /*!< OSPIC_INST (Bit 0) */ + #define OQSPIF_OQSPIF_BURSTCMDA_REG_OSPIC_INST_Msk (0xffUL) /*!< OSPIC_INST (Bitfield-Mask: 0xff) */ +/* ================================================= OQSPIF_BURSTCMDB_REG ================================================== */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_CS_HIGH_MIN_Pos (16UL) /*!< OSPIC_CS_HIGH_MIN (Bit 16) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_CS_HIGH_MIN_Msk (0x70000UL) /*!< OSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_SIZE_Pos (14UL) /*!< OSPIC_WRAP_SIZE (Bit 14) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_SIZE_Msk (0xc000UL) /*!< OSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_LEN_Pos (12UL) /*!< OSPIC_WRAP_LEN (Bit 12) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_LEN_Msk (0x3000UL) /*!< OSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_MD_Pos (11UL) /*!< OSPIC_WRAP_MD (Bit 11) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_WRAP_MD_Msk (0x800UL) /*!< OSPIC_WRAP_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_INST_MD_Pos (10UL) /*!< OSPIC_INST_MD (Bit 10) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_INST_MD_Msk (0x400UL) /*!< OSPIC_INST_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DMY_EN_Pos (9UL) /*!< OSPIC_DMY_EN (Bit 9) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DMY_EN_Msk (0x200UL) /*!< OSPIC_DMY_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DMY_NUM_Pos (4UL) /*!< OSPIC_DMY_NUM (Bit 4) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DMY_NUM_Msk (0x1f0UL) /*!< OSPIC_DMY_NUM (Bitfield-Mask: 0x1f) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_EXT_HF_DS_Pos (3UL) /*!< OSPIC_EXT_HF_DS (Bit 3) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_EXT_HF_DS_Msk (0x8UL) /*!< OSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_EXT_BYTE_EN_Pos (2UL) /*!< OSPIC_EXT_BYTE_EN (Bit 2) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< OSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DAT_RX_MD_Pos (0UL) /*!< OSPIC_DAT_RX_MD (Bit 0) */ + #define OQSPIF_OQSPIF_BURSTCMDB_REG_OSPIC_DAT_RX_MD_Msk (0x3UL) /*!< OSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */ +/* ================================================= OQSPIF_CHCKERASE_REG ================================================== */ + #define OQSPIF_OQSPIF_CHCKERASE_REG_OSPIC_CHCKERASE_Pos (0UL) /*!< OSPIC_CHCKERASE (Bit 0) */ + #define OQSPIF_OQSPIF_CHCKERASE_REG_OSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< OSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== OQSPIF_CTRLBUS_REG =================================================== */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_DIS_CS_Pos (5UL) /*!< OSPIC_DIS_CS (Bit 5) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_DIS_CS_Msk (0x20UL) /*!< OSPIC_DIS_CS (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_EN_CS_Pos (4UL) /*!< OSPIC_EN_CS (Bit 4) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_EN_CS_Msk (0x10UL) /*!< OSPIC_EN_CS (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_OCTAL_Pos (3UL) /*!< OSPIC_SET_OCTAL (Bit 3) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_OCTAL_Msk (0x8UL) /*!< OSPIC_SET_OCTAL (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_QUAD_Pos (2UL) /*!< OSPIC_SET_QUAD (Bit 2) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_QUAD_Msk (0x4UL) /*!< OSPIC_SET_QUAD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_DUAL_Pos (1UL) /*!< OSPIC_SET_DUAL (Bit 1) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_DUAL_Msk (0x2UL) /*!< OSPIC_SET_DUAL (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_SINGLE_Pos (0UL) /*!< OSPIC_SET_SINGLE (Bit 0) */ + #define OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_SINGLE_Msk (0x1UL) /*!< OSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */ +/* ================================================== OQSPIF_CTRLMODE_REG ================================================== */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_DAT_Pos (28UL) /*!< OSPIC_IO_UH_DAT (Bit 28) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_DAT_Msk (0xf0000000UL) /*!< OSPIC_IO_UH_DAT (Bitfield-Mask: 0x0f) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_OEN_Pos (27UL) /*!< OSPIC_IO_UH_OEN (Bit 27) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_OEN_Msk (0x8000000UL) /*!< OSPIC_IO_UH_OEN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_INC_LIM_EN_Pos (18UL) /*!< OSPIC_INC_LIM_EN (Bit 18) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_INC_LIM_EN_Msk (0x40000UL) /*!< OSPIC_INC_LIM_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RD_ERR_EN_Pos (17UL) /*!< OSPIC_RD_ERR_EN (Bit 17) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RD_ERR_EN_Msk (0x20000UL) /*!< OSPIC_RD_ERR_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_MAN_DIRCHG_MD_Pos (16UL) /*!< OSPIC_MAN_DIRCHG_MD (Bit 16) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_MAN_DIRCHG_MD_Msk (0x10000UL) /*!< OSPIC_MAN_DIRCHG_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_DMY_MD_Pos (15UL) /*!< OSPIC_DMY_MD (Bit 15) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_DMY_MD_Msk (0x8000UL) /*!< OSPIC_DMY_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CMD_X2_EN_Pos (14UL) /*!< OSPIC_CMD_X2_EN (Bit 14) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CMD_X2_EN_Msk (0x4000UL) /*!< OSPIC_CMD_X2_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_USE_32BA_Pos (13UL) /*!< OSPIC_USE_32BA (Bit 13) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_USE_32BA_Msk (0x2000UL) /*!< OSPIC_USE_32BA (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_BUF_LIM_EN_Pos (12UL) /*!< OSPIC_BUF_LIM_EN (Bit 12) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_BUF_LIM_EN_Msk (0x1000UL) /*!< OSPIC_BUF_LIM_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_PCLK_MD_Pos (9UL) /*!< OSPIC_PCLK_MD (Bit 9) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_PCLK_MD_Msk (0xe00UL) /*!< OSPIC_PCLK_MD (Bitfield-Mask: 0x07) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RPIPE_EN_Pos (8UL) /*!< OSPIC_RPIPE_EN (Bit 8) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RPIPE_EN_Msk (0x100UL) /*!< OSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RXD_NEG_Pos (7UL) /*!< OSPIC_RXD_NEG (Bit 7) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RXD_NEG_Msk (0x80UL) /*!< OSPIC_RXD_NEG (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_HRDY_MD_Pos (6UL) /*!< OSPIC_HRDY_MD (Bit 6) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_HRDY_MD_Msk (0x40UL) /*!< OSPIC_HRDY_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_DAT_Pos (5UL) /*!< OSPIC_IO3_DAT (Bit 5) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_DAT_Msk (0x20UL) /*!< OSPIC_IO3_DAT (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_DAT_Pos (4UL) /*!< OSPIC_IO2_DAT (Bit 4) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_DAT_Msk (0x10UL) /*!< OSPIC_IO2_DAT (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_OEN_Pos (3UL) /*!< OSPIC_IO3_OEN (Bit 3) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_OEN_Msk (0x8UL) /*!< OSPIC_IO3_OEN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_OEN_Pos (2UL) /*!< OSPIC_IO2_OEN (Bit 2) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_OEN_Msk (0x4UL) /*!< OSPIC_IO2_OEN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CLK_MD_Pos (1UL) /*!< OSPIC_CLK_MD (Bit 1) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CLK_MD_Msk (0x2UL) /*!< OSPIC_CLK_MD (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_AUTO_MD_Pos (0UL) /*!< OSPIC_AUTO_MD (Bit 0) */ + #define OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_AUTO_MD_Msk (0x1UL) /*!< OSPIC_AUTO_MD (Bitfield-Mask: 0x01) */ +/* ================================================== OQSPIF_CTR_CTRL_REG ================================================== */ + #define OQSPIF_OQSPIF_CTR_CTRL_REG_OSPIC_CTR_EN_Pos (0UL) /*!< OSPIC_CTR_EN (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_CTRL_REG_OSPIC_CTR_EN_Msk (0x1UL) /*!< OSPIC_CTR_EN (Bitfield-Mask: 0x01) */ +/* ================================================= OQSPIF_CTR_EADDR_REG ================================================== */ + #define OQSPIF_OQSPIF_CTR_EADDR_REG_OSPIC_CTR_EADDR_Pos (10UL) /*!< OSPIC_CTR_EADDR (Bit 10) */ + #define OQSPIF_OQSPIF_CTR_EADDR_REG_OSPIC_CTR_EADDR_Msk (0xfffffc00UL) /*!< OSPIC_CTR_EADDR (Bitfield-Mask: 0x3fffff) */ +/* ================================================ OQSPIF_CTR_KEY_0_3_REG ================================================= */ + #define OQSPIF_OQSPIF_CTR_KEY_0_3_REG_OSPIC_CTR_KEY_0_3_Pos (0UL) /*!< OSPIC_CTR_KEY_0_3 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_0_3_REG_OSPIC_CTR_KEY_0_3_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_0_3 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_KEY_12_15_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_12_15_REG_OSPIC_CTR_KEY_12_15_Pos (0UL) /*!< OSPIC_CTR_KEY_12_15 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_12_15_REG_OSPIC_CTR_KEY_12_15_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_12_15 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_KEY_16_19_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_16_19_REG_OSPIC_CTR_KEY_16_19_Pos (0UL) /*!< OSPIC_CTR_KEY_16_19 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_16_19_REG_OSPIC_CTR_KEY_16_19_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_16_19 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_KEY_20_23_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_20_23_REG_OSPIC_CTR_KEY_20_23_Pos (0UL) /*!< OSPIC_CTR_KEY_20_23 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_20_23_REG_OSPIC_CTR_KEY_20_23_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_20_23 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_KEY_24_27_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_24_27_REG_OSPIC_CTR_KEY_24_27_Pos (0UL) /*!< OSPIC_CTR_KEY_24_27 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_24_27_REG_OSPIC_CTR_KEY_24_27_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_24_27 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_KEY_28_31_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_28_31_REG_OSPIC_CTR_KEY_28_31_Pos (0UL) /*!< OSPIC_CTR_KEY_28_31 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_28_31_REG_OSPIC_CTR_KEY_28_31_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_28_31 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ OQSPIF_CTR_KEY_4_7_REG ================================================= */ + #define OQSPIF_OQSPIF_CTR_KEY_4_7_REG_OSPIC_CTR_KEY_4_7_Pos (0UL) /*!< OSPIC_CTR_KEY_4_7 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_4_7_REG_OSPIC_CTR_KEY_4_7_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_4_7 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ OQSPIF_CTR_KEY_8_11_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_KEY_8_11_REG_OSPIC_CTR_KEY_8_11_Pos (0UL) /*!< OSPIC_CTR_KEY_8_11 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_KEY_8_11_REG_OSPIC_CTR_KEY_8_11_Msk (0xffffffffUL) /*!< OSPIC_CTR_KEY_8_11 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_NONCE_0_3_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_NONCE_0_3_REG_OSPIC_CTR_NONCE_0_3_Pos (0UL) /*!< OSPIC_CTR_NONCE_0_3 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_NONCE_0_3_REG_OSPIC_CTR_NONCE_0_3_Msk (0xffffffffUL) /*!< OSPIC_CTR_NONCE_0_3 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== OQSPIF_CTR_NONCE_4_7_REG ================================================ */ + #define OQSPIF_OQSPIF_CTR_NONCE_4_7_REG_OSPIC_CTR_NONCE_4_7_Pos (0UL) /*!< OSPIC_CTR_NONCE_4_7 (Bit 0) */ + #define OQSPIF_OQSPIF_CTR_NONCE_4_7_REG_OSPIC_CTR_NONCE_4_7_Msk (0xffffffffUL) /*!< OSPIC_CTR_NONCE_4_7 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= OQSPIF_CTR_SADDR_REG ================================================== */ + #define OQSPIF_OQSPIF_CTR_SADDR_REG_OSPIC_CTR_SADDR_Pos (10UL) /*!< OSPIC_CTR_SADDR (Bit 10) */ + #define OQSPIF_OQSPIF_CTR_SADDR_REG_OSPIC_CTR_SADDR_Msk (0xfffffc00UL) /*!< OSPIC_CTR_SADDR (Bitfield-Mask: 0x3fffff) */ +/* ================================================= OQSPIF_DUMMYDATA_REG ================================================== */ + #define OQSPIF_OQSPIF_DUMMYDATA_REG_OSPIC_DUMMYDATA_Pos (0UL) /*!< OSPIC_DUMMYDATA (Bit 0) */ + #define OQSPIF_OQSPIF_DUMMYDATA_REG_OSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< OSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= OQSPIF_ERASECMDA_REG ================================================== */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_RES_INST_Pos (24UL) /*!< OSPIC_RES_INST (Bit 24) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_RES_INST_Msk (0xff000000UL) /*!< OSPIC_RES_INST (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_SUS_INST_Pos (16UL) /*!< OSPIC_SUS_INST (Bit 16) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_SUS_INST_Msk (0xff0000UL) /*!< OSPIC_SUS_INST (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_WEN_INST_Pos (8UL) /*!< OSPIC_WEN_INST (Bit 8) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_WEN_INST_Msk (0xff00UL) /*!< OSPIC_WEN_INST (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_ERS_INST_Pos (0UL) /*!< OSPIC_ERS_INST (Bit 0) */ + #define OQSPIF_OQSPIF_ERASECMDA_REG_OSPIC_ERS_INST_Msk (0xffUL) /*!< OSPIC_ERS_INST (Bitfield-Mask: 0xff) */ +/* ================================================= OQSPIF_ERASECMDB_REG ================================================== */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_RESSUS_DLY_Pos (24UL) /*!< OSPIC_RESSUS_DLY (Bit 24) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_RESSUS_DLY_Msk (0xff000000UL) /*!< OSPIC_RESSUS_DLY (Bitfield-Mask: 0xff) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERSRES_HLD_Pos (16UL) /*!< OSPIC_ERSRES_HLD (Bit 16) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< OSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERS_CS_HI_Pos (10UL) /*!< OSPIC_ERS_CS_HI (Bit 10) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< OSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_EAD_TX_MD_Pos (8UL) /*!< OSPIC_EAD_TX_MD (Bit 8) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_EAD_TX_MD_Msk (0x300UL) /*!< OSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_RES_TX_MD_Pos (6UL) /*!< OSPIC_RES_TX_MD (Bit 6) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_RES_TX_MD_Msk (0xc0UL) /*!< OSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_SUS_TX_MD_Pos (4UL) /*!< OSPIC_SUS_TX_MD (Bit 4) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_SUS_TX_MD_Msk (0x30UL) /*!< OSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_WEN_TX_MD_Pos (2UL) /*!< OSPIC_WEN_TX_MD (Bit 2) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_WEN_TX_MD_Msk (0xcUL) /*!< OSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERS_TX_MD_Pos (0UL) /*!< OSPIC_ERS_TX_MD (Bit 0) */ + #define OQSPIF_OQSPIF_ERASECMDB_REG_OSPIC_ERS_TX_MD_Msk (0x3UL) /*!< OSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */ +/* ================================================= OQSPIF_ERASECMDC_REG ================================================== */ + #define OQSPIF_OQSPIF_ERASECMDC_REG_OSPIC_SUSSTS_DLY_Pos (0UL) /*!< OSPIC_SUSSTS_DLY (Bit 0) */ + #define OQSPIF_OQSPIF_ERASECMDC_REG_OSPIC_SUSSTS_DLY_Msk (0x3fUL) /*!< OSPIC_SUSSTS_DLY (Bitfield-Mask: 0x3f) */ +/* ================================================= OQSPIF_ERASECTRL_REG ================================================== */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_RES_DIS_Pos (28UL) /*!< OSPIC_ERS_RES_DIS (Bit 28) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_RES_DIS_Msk (0x10000000UL) /*!< OSPIC_ERS_RES_DIS (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_STATE_Pos (25UL) /*!< OSPIC_ERS_STATE (Bit 25) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_STATE_Msk (0xe000000UL) /*!< OSPIC_ERS_STATE (Bitfield-Mask: 0x07) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERASE_EN_Pos (24UL) /*!< OSPIC_ERASE_EN (Bit 24) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERASE_EN_Msk (0x1000000UL) /*!< OSPIC_ERASE_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_ADDR_Pos (4UL) /*!< OSPIC_ERS_ADDR (Bit 4) */ + #define OQSPIF_OQSPIF_ERASECTRL_REG_OSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< OSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== OQSPIF_GP_REG ===================================================== */ + #define OQSPIF_OQSPIF_GP_REG_OSPIC_PADS_SLEW_Pos (3UL) /*!< OSPIC_PADS_SLEW (Bit 3) */ + #define OQSPIF_OQSPIF_GP_REG_OSPIC_PADS_SLEW_Msk (0x18UL) /*!< OSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_GP_REG_OSPIC_PADS_DRV_Pos (1UL) /*!< OSPIC_PADS_DRV (Bit 1) */ + #define OQSPIF_OQSPIF_GP_REG_OSPIC_PADS_DRV_Msk (0x6UL) /*!< OSPIC_PADS_DRV (Bitfield-Mask: 0x03) */ +/* ================================================== OQSPIF_READDATA_REG ================================================== */ + #define OQSPIF_OQSPIF_READDATA_REG_OSPIC_READDATA_Pos (0UL) /*!< OSPIC_READDATA (Bit 0) */ + #define OQSPIF_OQSPIF_READDATA_REG_OSPIC_READDATA_Msk (0xffffffffUL) /*!< OSPIC_READDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== OQSPIF_RECVDATA_REG ================================================== */ + #define OQSPIF_OQSPIF_RECVDATA_REG_OSPIC_RECVDATA_Pos (0UL) /*!< OSPIC_RECVDATA (Bit 0) */ + #define OQSPIF_OQSPIF_RECVDATA_REG_OSPIC_RECVDATA_Msk (0xffffffffUL) /*!< OSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= OQSPIF_STATUSCMD_REG ================================================== */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_ZERO_Pos (30UL) /*!< OSPIC_RSTAT_DMY_ZERO (Bit 30) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_ZERO_Msk (0x40000000UL) /*!< OSPIC_RSTAT_DMY_ZERO (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_TX_MD_Pos (28UL) /*!< OSPIC_RSTAT_DMY_TX_MD (Bit 28) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_TX_MD_Msk (0x30000000UL) /*!< OSPIC_RSTAT_DMY_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_NUM_Pos (24UL) /*!< OSPIC_RSTAT_DMY_NUM (Bit 24) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_NUM_Msk (0xf000000UL) /*!< OSPIC_RSTAT_DMY_NUM (Bitfield-Mask: 0x0f) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_EN_Pos (23UL) /*!< OSPIC_RSTAT_DMY_EN (Bit 23) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_DMY_EN_Msk (0x800000UL) /*!< OSPIC_RSTAT_DMY_EN (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_STSDLY_SEL_Pos (22UL) /*!< OSPIC_STSDLY_SEL (Bit 22) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< OSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RESSTS_DLY_Pos (16UL) /*!< OSPIC_RESSTS_DLY (Bit 16) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< OSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_BUSY_VAL_Pos (15UL) /*!< OSPIC_BUSY_VAL (Bit 15) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_BUSY_VAL_Msk (0x8000UL) /*!< OSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_BUSY_POS_Pos (12UL) /*!< OSPIC_BUSY_POS (Bit 12) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_BUSY_POS_Msk (0x7000UL) /*!< OSPIC_BUSY_POS (Bitfield-Mask: 0x07) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_RX_MD_Pos (10UL) /*!< OSPIC_RSTAT_RX_MD (Bit 10) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< OSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_TX_MD_Pos (8UL) /*!< OSPIC_RSTAT_TX_MD (Bit 8) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< OSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_INST_Pos (0UL) /*!< OSPIC_RSTAT_INST (Bit 0) */ + #define OQSPIF_OQSPIF_STATUSCMD_REG_OSPIC_RSTAT_INST_Msk (0xffUL) /*!< OSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */ +/* =================================================== OQSPIF_STATUS_REG =================================================== */ + #define OQSPIF_OQSPIF_STATUS_REG_OSPIC_BUSY_Pos (0UL) /*!< OSPIC_BUSY (Bit 0) */ + #define OQSPIF_OQSPIF_STATUS_REG_OSPIC_BUSY_Msk (0x1UL) /*!< OSPIC_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================= OQSPIF_WRITEDATA_REG ================================================== */ + #define OQSPIF_OQSPIF_WRITEDATA_REG_OSPIC_WRITEDATA_Pos (0UL) /*!< OSPIC_WRITEDATA (Bit 0) */ + #define OQSPIF_OQSPIF_WRITEDATA_REG_OSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< OSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ OTPC ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== OTPC_MODE_REG ===================================================== */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Pos (6UL) /*!< OTPC_MODE_PRG_SEL (Bit 6) */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Msk (0xc0UL) /*!< OTPC_MODE_PRG_SEL (Bitfield-Mask: 0x03) */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Pos (4UL) /*!< OTPC_MODE_USE_TST_ROW (Bit 4) */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Msk (0x10UL) /*!< OTPC_MODE_USE_TST_ROW (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL) /*!< OTPC_MODE_MODE (Bit 0) */ + #define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL) /*!< OTPC_MODE_MODE (Bitfield-Mask: 0x07) */ +/* ===================================================== OTPC_STAT_REG ===================================================== */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Pos (2UL) /*!< OTPC_STAT_MRDY (Bit 2) */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Msk (0x4UL) /*!< OTPC_STAT_MRDY (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Pos (1UL) /*!< OTPC_STAT_PBUF_EMPTY (Bit 1) */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Msk (0x2UL) /*!< OTPC_STAT_PBUF_EMPTY (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL) /*!< OTPC_STAT_PRDY (Bit 0) */ + #define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL) /*!< OTPC_STAT_PRDY (Bitfield-Mask: 0x01) */ +/* ================================================== OTPC_TEST_PWORD_REG ================================================== */ + #define OTPC_OTPC_TEST_PWORD_REG_OTPC_TEST_PWORD_Pos (0UL) /*!< OTPC_TEST_PWORD (Bit 0) */ + #define OTPC_OTPC_TEST_PWORD_REG_OTPC_TEST_PWORD_Msk (0xffffffffUL) /*!< OTPC_TEST_PWORD (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== OTPC_TEST_REG ===================================================== */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_MAN_Pos (31UL) /*!< OTPC_TEST_ECC_MAN (Bit 31) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_MAN_Msk (0x80000000UL) /*!< OTPC_TEST_ECC_MAN (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_ERR_Pos (24UL) /*!< OTPC_TEST_ECC_ERR (Bit 24) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_ERR_Msk (0x1000000UL) /*!< OTPC_TEST_ECC_ERR (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_OUT_Pos (16UL) /*!< OTPC_TEST_ECC_OUT (Bit 16) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_OUT_Msk (0x3f0000UL) /*!< OTPC_TEST_ECC_OUT (Bitfield-Mask: 0x3f) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_IN_Pos (8UL) /*!< OTPC_TEST_ECC_IN (Bit 8) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_IN_Msk (0x3f00UL) /*!< OTPC_TEST_ECC_IN (Bitfield-Mask: 0x3f) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_EN_DE_Pos (2UL) /*!< OTPC_TEST_ECC_EN_DE (Bit 2) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_ECC_EN_DE_Msk (0x4UL) /*!< OTPC_TEST_ECC_EN_DE (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_MODE_Pos (0UL) /*!< OTPC_TEST_MODE (Bit 0) */ + #define OTPC_OTPC_TEST_REG_OTPC_TEST_MODE_Msk (0x3UL) /*!< OTPC_TEST_MODE (Bitfield-Mask: 0x03) */ +/* ===================================================== OTPC_TIM1_REG ===================================================== */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos (24UL) /*!< OTPC_TIM1_US_T_CSP (Bit 24) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Msk (0x7f000000UL) /*!< OTPC_TIM1_US_T_CSP (Bitfield-Mask: 0x7f) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos (20UL) /*!< OTPC_TIM1_US_T_CS (Bit 20) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Msk (0xf00000UL) /*!< OTPC_TIM1_US_T_CS (Bitfield-Mask: 0x0f) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Pos (16UL) /*!< OTPC_TIM1_US_T_PL (Bit 16) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Msk (0xf0000UL) /*!< OTPC_TIM1_US_T_PL (Bitfield-Mask: 0x0f) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos (12UL) /*!< OTPC_TIM1_CC_T_RD (Bit 12) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Msk (0xf000UL) /*!< OTPC_TIM1_CC_T_RD (Bitfield-Mask: 0x0f) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos (8UL) /*!< OTPC_TIM1_CC_T_20NS (Bit 8) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Msk (0x700UL) /*!< OTPC_TIM1_CC_T_20NS (Bitfield-Mask: 0x07) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (0UL) /*!< OTPC_TIM1_CC_T_1US (Bit 0) */ + #define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0xffUL) /*!< OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0xff) */ +/* ===================================================== OTPC_TIM2_REG ===================================================== */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Pos (31UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bit 31) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Msk (0x80000000UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bitfield-Mask: 0x01) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Pos (29UL) /*!< OTPC_TIM2_US_T_SAS (Bit 29) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Msk (0x60000000UL) /*!< OTPC_TIM2_US_T_SAS (Bitfield-Mask: 0x03) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Pos (24UL) /*!< OTPC_TIM2_US_T_PPH (Bit 24) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Msk (0x1f000000UL) /*!< OTPC_TIM2_US_T_PPH (Bitfield-Mask: 0x1f) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Pos (21UL) /*!< OTPC_TIM2_US_T_VDS (Bit 21) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Msk (0xe00000UL) /*!< OTPC_TIM2_US_T_VDS (Bitfield-Mask: 0x07) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Pos (16UL) /*!< OTPC_TIM2_US_T_PPS (Bit 16) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Msk (0x1f0000UL) /*!< OTPC_TIM2_US_T_PPS (Bitfield-Mask: 0x1f) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Pos (8UL) /*!< OTPC_TIM2_US_T_PPR (Bit 8) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Msk (0x7f00UL) /*!< OTPC_TIM2_US_T_PPR (Bitfield-Mask: 0x7f) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Pos (5UL) /*!< OTPC_TIM2_US_T_PWI (Bit 5) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Msk (0xe0UL) /*!< OTPC_TIM2_US_T_PWI (Bitfield-Mask: 0x07) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Pos (0UL) /*!< OTPC_TIM2_US_T_PW (Bit 0) */ + #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Msk (0x1fUL) /*!< OTPC_TIM2_US_T_PW (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PSK ================ */ +/* =========================================================================================================================== */ + +/* =================================================== PSK_SHA1_CTRL_REG =================================================== */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Iteration_Pos (16UL) /*!< PSK_SHA1_Iteration (Bit 16) */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Iteration_Msk (0xffff0000UL) /*!< PSK_SHA1_Iteration (Bitfield-Mask: 0xffff) */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Start_Pos (1UL) /*!< PSK_SHA1_Start (Bit 1) */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Start_Msk (0x2UL) /*!< PSK_SHA1_Start (Bitfield-Mask: 0x01) */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Enable_Pos (0UL) /*!< PSK_SHA1_Enable (Bit 0) */ + #define PSK_PSK_SHA1_CTRL_REG_PSK_SHA1_Enable_Msk (0x1UL) /*!< PSK_SHA1_Enable (Bitfield-Mask: 0x01) */ +/* ================================================== PSK_SHA1_DATA_0_REG ================================================== */ + #define PSK_PSK_SHA1_DATA_0_REG_PSK_SHA1_DATA_0_Pos (0UL) /*!< PSK_SHA1_DATA_0 (Bit 0) */ + #define PSK_PSK_SHA1_DATA_0_REG_PSK_SHA1_DATA_0_Msk (0xffffffffUL) /*!< PSK_SHA1_DATA_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_DATA_1_REG ================================================== */ + #define PSK_PSK_SHA1_DATA_1_REG_PSK_SHA1_DATA_1_Pos (0UL) /*!< PSK_SHA1_DATA_1 (Bit 0) */ + #define PSK_PSK_SHA1_DATA_1_REG_PSK_SHA1_DATA_1_Msk (0xffffffffUL) /*!< PSK_SHA1_DATA_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_DATA_2_REG ================================================== */ + #define PSK_PSK_SHA1_DATA_2_REG_PSK_SHA1_DATA_2_Pos (0UL) /*!< PSK_SHA1_DATA_2 (Bit 0) */ + #define PSK_PSK_SHA1_DATA_2_REG_PSK_SHA1_DATA_2_Msk (0xffffffffUL) /*!< PSK_SHA1_DATA_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_DATA_3_REG ================================================== */ + #define PSK_PSK_SHA1_DATA_3_REG_PSK_SHA1_DATA_3_Pos (0UL) /*!< PSK_SHA1_DATA_3 (Bit 0) */ + #define PSK_PSK_SHA1_DATA_3_REG_PSK_SHA1_DATA_3_Msk (0xffffffffUL) /*!< PSK_SHA1_DATA_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_DATA_4_REG ================================================== */ + #define PSK_PSK_SHA1_DATA_4_REG_PSK_SHA1_DATA_4_Pos (0UL) /*!< PSK_SHA1_DATA_4 (Bit 0) */ + #define PSK_PSK_SHA1_DATA_4_REG_PSK_SHA1_DATA_4_Msk (0xffffffffUL) /*!< PSK_SHA1_DATA_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PSK_SHA1_DIGEST_0_REG ================================================= */ + #define PSK_PSK_SHA1_DIGEST_0_REG_PSK_SHA1_DIGEST_0_Pos (0UL) /*!< PSK_SHA1_DIGEST_0 (Bit 0) */ + #define PSK_PSK_SHA1_DIGEST_0_REG_PSK_SHA1_DIGEST_0_Msk (0xffffffffUL) /*!< PSK_SHA1_DIGEST_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PSK_SHA1_DIGEST_1_REG ================================================= */ + #define PSK_PSK_SHA1_DIGEST_1_REG_PSK_SHA1_DIGEST_1_Pos (0UL) /*!< PSK_SHA1_DIGEST_1 (Bit 0) */ + #define PSK_PSK_SHA1_DIGEST_1_REG_PSK_SHA1_DIGEST_1_Msk (0xffffffffUL) /*!< PSK_SHA1_DIGEST_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PSK_SHA1_DIGEST_2_REG ================================================= */ + #define PSK_PSK_SHA1_DIGEST_2_REG_PSK_SHA1_DIGEST_2_Pos (0UL) /*!< PSK_SHA1_DIGEST_2 (Bit 0) */ + #define PSK_PSK_SHA1_DIGEST_2_REG_PSK_SHA1_DIGEST_2_Msk (0xffffffffUL) /*!< PSK_SHA1_DIGEST_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PSK_SHA1_DIGEST_3_REG ================================================= */ + #define PSK_PSK_SHA1_DIGEST_3_REG_PSK_SHA1_DIGEST_3_Pos (0UL) /*!< PSK_SHA1_DIGEST_3 (Bit 0) */ + #define PSK_PSK_SHA1_DIGEST_3_REG_PSK_SHA1_DIGEST_3_Msk (0xffffffffUL) /*!< PSK_SHA1_DIGEST_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PSK_SHA1_DIGEST_4_REG ================================================= */ + #define PSK_PSK_SHA1_DIGEST_4_REG_PSK_SHA1_DIGEST_4_Pos (0UL) /*!< PSK_SHA1_DIGEST_4 (Bit 0) */ + #define PSK_PSK_SHA1_DIGEST_4_REG_PSK_SHA1_DIGEST_4_Msk (0xffffffffUL) /*!< PSK_SHA1_DIGEST_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV1_0_REG ================================================== */ + #define PSK_PSK_SHA1_IHV1_0_REG_PSK_SHA1_IHV1_0_Pos (0UL) /*!< PSK_SHA1_IHV1_0 (Bit 0) */ + #define PSK_PSK_SHA1_IHV1_0_REG_PSK_SHA1_IHV1_0_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV1_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV1_1_REG ================================================== */ + #define PSK_PSK_SHA1_IHV1_1_REG_PSK_SHA1_IHV1_1_Pos (0UL) /*!< PSK_SHA1_IHV1_1 (Bit 0) */ + #define PSK_PSK_SHA1_IHV1_1_REG_PSK_SHA1_IHV1_1_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV1_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV1_2_REG ================================================== */ + #define PSK_PSK_SHA1_IHV1_2_REG_PSK_SHA1_IHV1_2_Pos (0UL) /*!< PSK_SHA1_IHV1_2 (Bit 0) */ + #define PSK_PSK_SHA1_IHV1_2_REG_PSK_SHA1_IHV1_2_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV1_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV1_3_REG ================================================== */ + #define PSK_PSK_SHA1_IHV1_3_REG_PSK_SHA1_IHV1_3_Pos (0UL) /*!< PSK_SHA1_IHV1_3 (Bit 0) */ + #define PSK_PSK_SHA1_IHV1_3_REG_PSK_SHA1_IHV1_3_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV1_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV1_4_REG ================================================== */ + #define PSK_PSK_SHA1_IHV1_4_REG_PSK_SHA1_IHV1_4_Pos (0UL) /*!< PSK_SHA1_IHV1_4 (Bit 0) */ + #define PSK_PSK_SHA1_IHV1_4_REG_PSK_SHA1_IHV1_4_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV1_4 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV2_0_REG ================================================== */ + #define PSK_PSK_SHA1_IHV2_0_REG_PSK_SHA1_IHV2_0_Pos (0UL) /*!< PSK_SHA1_IHV2_0 (Bit 0) */ + #define PSK_PSK_SHA1_IHV2_0_REG_PSK_SHA1_IHV2_0_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV2_0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV2_1_REG ================================================== */ + #define PSK_PSK_SHA1_IHV2_1_REG_PSK_SHA1_IHV2_1_Pos (0UL) /*!< PSK_SHA1_IHV2_1 (Bit 0) */ + #define PSK_PSK_SHA1_IHV2_1_REG_PSK_SHA1_IHV2_1_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV2_1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV2_2_REG ================================================== */ + #define PSK_PSK_SHA1_IHV2_2_REG_PSK_SHA1_IHV2_2_Pos (0UL) /*!< PSK_SHA1_IHV2_2 (Bit 0) */ + #define PSK_PSK_SHA1_IHV2_2_REG_PSK_SHA1_IHV2_2_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV2_2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV2_3_REG ================================================== */ + #define PSK_PSK_SHA1_IHV2_3_REG_PSK_SHA1_IHV2_3_Pos (0UL) /*!< PSK_SHA1_IHV2_3 (Bit 0) */ + #define PSK_PSK_SHA1_IHV2_3_REG_PSK_SHA1_IHV2_3_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV2_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PSK_SHA1_IHV2_4_REG ================================================== */ + #define PSK_PSK_SHA1_IHV2_4_REG_PSK_SHA1_IHV2_4_Pos (0UL) /*!< PSK_SHA1_IHV2_4 (Bit 0) */ + #define PSK_PSK_SHA1_IHV2_4_REG_PSK_SHA1_IHV2_4_Msk (0xffffffffUL) /*!< PSK_SHA1_IHV2_4 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ QSPIC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== QSPIC_AWRITECMD_REG ================================================== */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bit 14) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bitfield-Mask: 0x1f) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL) /*!< QSPIC_WR_DAT_TX_MD (Bit 12) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL) /*!< QSPIC_WR_DAT_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL) /*!< QSPIC_WR_ADR_TX_MD (Bit 10) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL) /*!< QSPIC_WR_ADR_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL) /*!< QSPIC_WR_INST_TX_MD (Bit 8) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL) /*!< QSPIC_WR_INST_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL) /*!< QSPIC_WR_INST (Bit 0) */ + #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL) /*!< QSPIC_WR_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC_BURSTBRK_REG =================================================== */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC_SEC_HF_DS (Bit 20) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC_BRK_TX_MD (Bit 18) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC_BRK_SZ (Bit 17) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC_BRK_EN (Bit 16) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC_BRK_WRD (Bit 0) */ + #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */ +/* ================================================== QSPIC_BURSTCMDA_REG ================================================== */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC_DMY_TX_MD (Bit 30) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC_EXT_TX_MD (Bit 28) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC_ADR_TX_MD (Bit 26) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC_INST_TX_MD (Bit 24) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC_EXT_BYTE (Bit 16) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC_INST_WB (Bit 8) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC_INST (Bit 0) */ + #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC_BURSTCMDB_REG ================================================== */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC_DMY_FORCE (Bit 15) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC_CS_HIGH_MIN (Bit 12) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC_WRAP_SIZE (Bit 10) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC_WRAP_LEN (Bit 8) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC_WRAP_MD (Bit 7) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC_INST_MD (Bit 6) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC_DMY_NUM (Bit 4) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC_EXT_HF_DS (Bit 3) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC_EXT_BYTE_EN (Bit 2) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC_DAT_RX_MD (Bit 0) */ + #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC_CHCKERASE_REG ================================================== */ + #define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC_CHCKERASE (Bit 0) */ + #define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== QSPIC_CTRLBUS_REG =================================================== */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC_DIS_CS (Bit 4) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC_EN_CS (Bit 3) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC_SET_QUAD (Bit 2) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC_SET_DUAL (Bit 1) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC_SET_SINGLE (Bit 0) */ + #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_CTRLMODE_REG =================================================== */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL) /*!< QSPIC_CLK_FREE_EN (Bit 16) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL) /*!< QSPIC_CLK_FREE_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL) /*!< QSPIC_CS_MD (Bit 15) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL) /*!< QSPIC_CS_MD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL) /*!< QSPIC_SRAM_EN (Bit 14) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL) /*!< QSPIC_SRAM_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC_USE_32BA (Bit 13) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL) /*!< QSPIC_FORCENSEQ_EN (Bit 12) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL) /*!< QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC_PCLK_MD (Bit 9) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC_RPIPE_EN (Bit 8) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC_RXD_NEG (Bit 7) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC_HRDY_MD (Bit 6) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC_IO3_DAT (Bit 5) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC_IO2_DAT (Bit 4) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC_IO3_OEN (Bit 3) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC_IO2_OEN (Bit 2) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC_CLK_MD (Bit 1) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC_AUTO_MD (Bit 0) */ + #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_DUMMYDATA_REG ================================================== */ + #define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC_DUMMYDATA (Bit 0) */ + #define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_ERASECMDA_REG ================================================== */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC_RES_INST (Bit 24) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC_SUS_INST (Bit 16) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC_WEN_INST (Bit 8) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC_ERS_INST (Bit 0) */ + #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC_ERASECMDB_REG ================================================== */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC_RESSUS_DLY (Bit 24) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC_ERSRES_HLD (Bit 16) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC_ERS_CS_HI (Bit 10) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC_EAD_TX_MD (Bit 8) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC_RES_TX_MD (Bit 6) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC_SUS_TX_MD (Bit 4) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC_WEN_TX_MD (Bit 2) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC_ERS_TX_MD (Bit 0) */ + #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC_ERASECTRL_REG ================================================== */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC_ERS_STATE (Bit 25) */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC_ERASE_EN (Bit 24) */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC_ERS_ADDR (Bit 4) */ + #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== QSPIC_GP_REG ====================================================== */ + #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC_PADS_SLEW (Bit 3) */ + #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC_PADS_DRV (Bit 1) */ + #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_GP_REG_QSPIC_SELECT_Pos (0UL) /*!< QSPIC_SELECT (Bit 0) */ + #define QSPIC_QSPIC_GP_REG_QSPIC_SELECT_Msk (0x1UL) /*!< QSPIC_SELECT (Bitfield-Mask: 0x01) */ +/* =================================================== QSPIC_MEMBLEN_REG =================================================== */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL) /*!< QSPIC_T_CEM_CC (Bit 4) */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL) /*!< QSPIC_T_CEM_CC (Bitfield-Mask: 0x3ff) */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL) /*!< QSPIC_T_CEM_EN (Bit 3) */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL) /*!< QSPIC_T_CEM_EN (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL) /*!< QSPIC_MEMBLEN (Bit 0) */ + #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL) /*!< QSPIC_MEMBLEN (Bitfield-Mask: 0x07) */ +/* ================================================== QSPIC_READDATA_REG =================================================== */ + #define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC_READDATA (Bit 0) */ + #define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_RECVDATA_REG =================================================== */ + #define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC_RECVDATA (Bit 0) */ + #define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_STATUSCMD_REG ================================================== */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC_STSDLY_SEL (Bit 22) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC_RESSTS_DLY (Bit 16) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC_BUSY_VAL (Bit 15) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC_BUSY_POS (Bit 12) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC_RSTAT_RX_MD (Bit 10) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC_RSTAT_TX_MD (Bit 8) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC_RSTAT_INST (Bit 0) */ + #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */ +/* =================================================== QSPIC_STATUS_REG ==================================================== */ + #define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC_BUSY (Bit 0) */ + #define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_WRITEDATA_REG ================================================== */ + #define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC_WRITEDATA (Bit 0) */ + #define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ RETMEMCTRL ================ */ +/* =========================================================================================================================== */ + +/* ============================================= RETMEMCTRL_DYNAMIC_CLK_ON_REG ============================================= */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_MEM_UNIT_Pos (5UL) /*!< MEM_UNIT (Bit 5) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_MEM_UNIT_Msk (0x20UL) /*!< MEM_UNIT (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_MMI2MEM_Pos (3UL) /*!< MMI2MEM (Bit 3) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_MMI2MEM_Msk (0x8UL) /*!< MMI2MEM (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_ARBITER_Pos (1UL) /*!< ARBITER (Bit 1) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_ARBITER_Msk (0x2UL) /*!< ARBITER (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_AHB2MEM_Pos (0UL) /*!< AHB2MEM (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_DYNAMIC_CLK_ON_REG_AHB2MEM_Msk (0x1UL) /*!< AHB2MEM (Bitfield-Mask: 0x01) */ +/* =============================================== RETMEMCTRL_MST_CLK_EN_REG =============================================== */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_M33_MTB_CLK_EN_Pos (3UL) /*!< MST_M33_MTB_CLK_EN (Bit 3) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_M33_MTB_CLK_EN_Msk (0x8UL) /*!< MST_M33_MTB_CLK_EN (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_DMA_CLK_EN_Pos (2UL) /*!< MST_DMA_CLK_EN (Bit 2) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_DMA_CLK_EN_Msk (0x4UL) /*!< MST_DMA_CLK_EN (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_CPUS_CLK_EN_Pos (1UL) /*!< MST_CPUS_CLK_EN (Bit 1) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_CPUS_CLK_EN_Msk (0x2UL) /*!< MST_CPUS_CLK_EN (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_CPUC_CLK_EN_Pos (0UL) /*!< MST_CPUC_CLK_EN (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_MST_CLK_EN_REG_MST_CPUC_CLK_EN_Msk (0x1UL) /*!< MST_CPUC_CLK_EN (Bitfield-Mask: 0x01) */ +/* ================================================ RETMEMCTRL_PRIO_ARB_REG ================================================ */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_DMA_RAM_Pos (4UL) /*!< PRIO_ARB_DMA_RAM (Bit 4) */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_DMA_RAM_Msk (0x30UL) /*!< PRIO_ARB_DMA_RAM (Bitfield-Mask: 0x03) */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUS_RAM_Pos (2UL) /*!< PRIO_ARB_CPUS_RAM (Bit 2) */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUS_RAM_Msk (0xcUL) /*!< PRIO_ARB_CPUS_RAM (Bitfield-Mask: 0x03) */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUC_RAM_Pos (0UL) /*!< PRIO_ARB_CPUC_RAM (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_PRIO_ARB_REG_PRIO_ARB_CPUC_RAM_Msk (0x3UL) /*!< PRIO_ARB_CPUC_RAM (Bitfield-Mask: 0x03) */ +/* ================================================= RETMEMCTRL_STALL_REG ================================================== */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_DMA_MAX_STALL_Pos (8UL) /*!< AHB_DMA_MAX_STALL (Bit 8) */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_DMA_MAX_STALL_Msk (0xf00UL) /*!< AHB_DMA_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_CPUS_MAX_STALL_Pos (4UL) /*!< AHB_CPUS_MAX_STALL (Bit 4) */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_CPUS_MAX_STALL_Msk (0xf0UL) /*!< AHB_CPUS_MAX_STALL (Bitfield-Mask: 0x0f) */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_CPUC_MAX_STALL_Pos (0UL) /*!< AHB_CPUC_MAX_STALL (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_STALL_REG_AHB_CPUC_MAX_STALL_Msk (0xfUL) /*!< AHB_CPUC_MAX_STALL (Bitfield-Mask: 0x0f) */ +/* ============================================= RETMEMCTRL_STATIC_CLK_OFF_REG ============================================= */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM2_Pos (2UL) /*!< SRAM2 (Bit 2) */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM2_Msk (0x4UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM1_Pos (1UL) /*!< SRAM1 (Bit 1) */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM1_Msk (0x2UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM0_Pos (0UL) /*!< SRAM0 (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_STATIC_CLK_OFF_REG_SRAM0_Msk (0x1UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +/* ================================================= RETMEMCTRL_STATUS_REG ================================================= */ + #define RETMEMCTRL_RETMEMCTRL_STATUS_REG_RAM1_OFF_BUT_ACCESS_Pos (1UL) /*!< RAM1_OFF_BUT_ACCESS (Bit 1) */ + #define RETMEMCTRL_RETMEMCTRL_STATUS_REG_RAM1_OFF_BUT_ACCESS_Msk (0x2UL) /*!< RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + #define RETMEMCTRL_RETMEMCTRL_STATUS_REG_RAM0_OFF_BUT_ACCESS_Pos (0UL) /*!< RAM0_OFF_BUT_ACCESS (Bit 0) */ + #define RETMEMCTRL_RETMEMCTRL_STATUS_REG_RAM0_OFF_BUT_ACCESS_Msk (0x1UL) /*!< RAM0_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ RFMON ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== RFMON_ADDR_REG ===================================================== */ + #define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Pos (2UL) /*!< RFMON_ADDR (Bit 2) */ + #define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Msk (0xfffffffcUL) /*!< RFMON_ADDR (Bitfield-Mask: 0x3fffffff) */ +/* ================================================== RFMON_CRV_ADDR_REG =================================================== */ + #define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Pos (2UL) /*!< RFMON_CRV_ADDR (Bit 2) */ + #define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Msk (0xfffffffcUL) /*!< RFMON_CRV_ADDR (Bitfield-Mask: 0x3fffffff) */ +/* =================================================== RFMON_CRV_LEN_REG =================================================== */ + #define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Pos (0UL) /*!< RFMON_CRV_LEN (Bit 0) */ + #define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Msk (0x1ffffUL) /*!< RFMON_CRV_LEN (Bitfield-Mask: 0x1ffff) */ +/* ==================================================== RFMON_CTRL_REG ===================================================== */ + #define RFMON_RFMON_CTRL_REG_RFMON_READ_FORCE_Pos (3UL) /*!< RFMON_READ_FORCE (Bit 3) */ + #define RFMON_RFMON_CTRL_REG_RFMON_READ_FORCE_Msk (0x8UL) /*!< RFMON_READ_FORCE (Bitfield-Mask: 0x01) */ + #define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Pos (2UL) /*!< RFMON_BREQ_FORCE (Bit 2) */ + #define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Msk (0x4UL) /*!< RFMON_BREQ_FORCE (Bitfield-Mask: 0x01) */ + #define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Pos (1UL) /*!< RFMON_CIRC_EN (Bit 1) */ + #define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Msk (0x2UL) /*!< RFMON_CIRC_EN (Bitfield-Mask: 0x01) */ + #define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Pos (0UL) /*!< RFMON_PACK_EN (Bit 0) */ + #define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Msk (0x1UL) /*!< RFMON_PACK_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== RFMON_LEN_REG ===================================================== */ + #define RFMON_RFMON_LEN_REG_RFMON_LEN_Pos (0UL) /*!< RFMON_LEN (Bit 0) */ + #define RFMON_RFMON_LEN_REG_RFMON_LEN_Msk (0x1ffffUL) /*!< RFMON_LEN (Bitfield-Mask: 0x1ffff) */ +/* ==================================================== RFMON_STAT_REG ===================================================== */ + #define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Pos (1UL) /*!< RFMON_OFLOW_STK (Bit 1) */ + #define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Msk (0x2UL) /*!< RFMON_OFLOW_STK (Bitfield-Mask: 0x01) */ + #define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Pos (0UL) /*!< RFMON_ACTIVE (Bit 0) */ + #define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Msk (0x1UL) /*!< RFMON_ACTIVE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== BCFM_IRQ_EN_REG ==================================================== */ + #define RTC_BCFM_IRQ_EN_REG_BCFM_IRQ_EN_Pos (0UL) /*!< BCFM_IRQ_EN (Bit 0) */ + #define RTC_BCFM_IRQ_EN_REG_BCFM_IRQ_EN_Msk (0x1UL) /*!< BCFM_IRQ_EN (Bitfield-Mask: 0x01) */ +/* ================================================== BCFM_IRQ_STATUS_REG ================================================== */ + #define RTC_BCFM_IRQ_STATUS_REG_BCFM_IRQ_STATUS_Pos (0UL) /*!< BCFM_IRQ_STATUS (Bit 0) */ + #define RTC_BCFM_IRQ_STATUS_REG_BCFM_IRQ_STATUS_Msk (0x1UL) /*!< BCFM_IRQ_STATUS (Bitfield-Mask: 0x01) */ +/* ==================================================== BCFM_OP_EN_REG ===================================================== */ + #define RTC_BCFM_OP_EN_REG_BCFM_OP_EN_Pos (0UL) /*!< BCFM_OP_EN (Bit 0) */ + #define RTC_BCFM_OP_EN_REG_BCFM_OP_EN_Msk (0x1UL) /*!< BCFM_OP_EN (Bitfield-Mask: 0x01) */ +/* ================================================== BCFM_OP_STATUS_REG =================================================== */ + #define RTC_BCFM_OP_STATUS_REG_BCFM_OP_STATUS_Pos (0UL) /*!< BCFM_OP_STATUS (Bit 0) */ + #define RTC_BCFM_OP_STATUS_REG_BCFM_OP_STATUS_Msk (0x3UL) /*!< BCFM_OP_STATUS (Bitfield-Mask: 0x03) */ +/* ================================================= BCFM_REQ_CLR_IRQ_REG ================================================== */ + #define RTC_BCFM_REQ_CLR_IRQ_REG_BCFM_REQ_CLR_IRQ_Pos (1UL) /*!< BCFM_REQ_CLR_IRQ (Bit 1) */ + #define RTC_BCFM_REQ_CLR_IRQ_REG_BCFM_REQ_CLR_IRQ_Msk (0x2UL) /*!< BCFM_REQ_CLR_IRQ (Bitfield-Mask: 0x01) */ + #define RTC_BCFM_REQ_CLR_IRQ_REG_BCFM_REQ_START_Pos (0UL) /*!< BCFM_REQ_START (Bit 0) */ + #define RTC_BCFM_REQ_CLR_IRQ_REG_BCFM_REQ_START_Msk (0x1UL) /*!< BCFM_REQ_START (Bitfield-Mask: 0x01) */ +/* =================================================== BCFM_TOT_CYC_REG ==================================================== */ + #define RTC_BCFM_TOT_CYC_REG_BCFM_TOT_CYC_Pos (0UL) /*!< BCFM_TOT_CYC (Bit 0) */ + #define RTC_BCFM_TOT_CYC_REG_BCFM_TOT_CYC_Msk (0xffffUL) /*!< BCFM_TOT_CYC (Bitfield-Mask: 0xffff) */ +/* ==================================================== BOR_CIRCUIT_REG ==================================================== */ + #define RTC_BOR_CIRCUIT_REG_BR_STATUS_READ_Pos (14UL) /*!< BR_STATUS_READ (Bit 14) */ + #define RTC_BOR_CIRCUIT_REG_BR_STATUS_READ_Msk (0x4000UL) /*!< BR_STATUS_READ (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BL_STATUS_READ_Pos (13UL) /*!< BL_STATUS_READ (Bit 13) */ + #define RTC_BOR_CIRCUIT_REG_BL_STATUS_READ_Msk (0x2000UL) /*!< BL_STATUS_READ (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BR_HYS_CTRL_Pos (12UL) /*!< BR_HYS_CTRL (Bit 12) */ + #define RTC_BOR_CIRCUIT_REG_BR_HYS_CTRL_Msk (0x1000UL) /*!< BR_HYS_CTRL (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BL_HYS_CTRL_Pos (11UL) /*!< BL_HYS_CTRL (Bit 11) */ + #define RTC_BOR_CIRCUIT_REG_BL_HYS_CTRL_Msk (0x800UL) /*!< BL_HYS_CTRL (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_RF_LO_CAL_ENABLE_Pos (10UL) /*!< RF_LO_CAL_ENABLE (Bit 10) */ + #define RTC_BOR_CIRCUIT_REG_RF_LO_CAL_ENABLE_Msk (0x400UL) /*!< RF_LO_CAL_ENABLE (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BR_OUT_EN_Pos (9UL) /*!< BR_OUT_EN (Bit 9) */ + #define RTC_BOR_CIRCUIT_REG_BR_OUT_EN_Msk (0x200UL) /*!< BR_OUT_EN (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BL_OUT_EN_Pos (8UL) /*!< BL_OUT_EN (Bit 8) */ + #define RTC_BOR_CIRCUIT_REG_BL_OUT_EN_Msk (0x100UL) /*!< BL_OUT_EN (Bitfield-Mask: 0x01) */ + #define RTC_BOR_CIRCUIT_REG_BR_OUT_CTRL_Pos (4UL) /*!< BR_OUT_CTRL (Bit 4) */ + #define RTC_BOR_CIRCUIT_REG_BR_OUT_CTRL_Msk (0xf0UL) /*!< BR_OUT_CTRL (Bitfield-Mask: 0x0f) */ + #define RTC_BOR_CIRCUIT_REG_BL_OUT_CTRL_Pos (0UL) /*!< BL_OUT_CTRL (Bit 0) */ + #define RTC_BOR_CIRCUIT_REG_BL_OUT_CTRL_Msk (0xfUL) /*!< BL_OUT_CTRL (Bitfield-Mask: 0x0f) */ +/* ==================================================== CLK_XTAL32K_REG ==================================================== */ + #define RTC_CLK_XTAL32K_REG_VBAT_BIAS_I_CTRL_Pos (10UL) /*!< VBAT_BIAS_I_CTRL (Bit 10) */ + #define RTC_CLK_XTAL32K_REG_VBAT_BIAS_I_CTRL_Msk (0x400UL) /*!< VBAT_BIAS_I_CTRL (Bitfield-Mask: 0x01) */ + #define RTC_CLK_XTAL32K_REG_XTAL_LDO_I_CTRL_Pos (8UL) /*!< XTAL_LDO_I_CTRL (Bit 8) */ + #define RTC_CLK_XTAL32K_REG_XTAL_LDO_I_CTRL_Msk (0x300UL) /*!< XTAL_LDO_I_CTRL (Bitfield-Mask: 0x03) */ + #define RTC_CLK_XTAL32K_REG_XTAL_LDO_CTRL_Pos (5UL) /*!< XTAL_LDO_CTRL (Bit 5) */ + #define RTC_CLK_XTAL32K_REG_XTAL_LDO_CTRL_Msk (0xe0UL) /*!< XTAL_LDO_CTRL (Bitfield-Mask: 0x07) */ + #define RTC_CLK_XTAL32K_REG_XR_BAT_EN_Pos (4UL) /*!< XR_BAT_EN (Bit 4) */ + #define RTC_CLK_XTAL32K_REG_XR_BAT_EN_Msk (0x10UL) /*!< XR_BAT_EN (Bitfield-Mask: 0x01) */ + #define RTC_CLK_XTAL32K_REG_XTAL_CLK_SEL_Pos (2UL) /*!< XTAL_CLK_SEL (Bit 2) */ + #define RTC_CLK_XTAL32K_REG_XTAL_CLK_SEL_Msk (0xcUL) /*!< XTAL_CLK_SEL (Bitfield-Mask: 0x03) */ + #define RTC_CLK_XTAL32K_REG_XTAL_BAT_EN_Pos (1UL) /*!< XTAL_BAT_EN (Bit 1) */ + #define RTC_CLK_XTAL32K_REG_XTAL_BAT_EN_Msk (0x2UL) /*!< XTAL_BAT_EN (Bitfield-Mask: 0x01) */ + #define RTC_CLK_XTAL32K_REG_PDB_OSC_EN_Pos (0UL) /*!< PDB_OSC_EN (Bit 0) */ + #define RTC_CLK_XTAL32K_REG_PDB_OSC_EN_Msk (0x1UL) /*!< PDB_OSC_EN (Bitfield-Mask: 0x01) */ +/* ================================================== CNT_BASE_TESTI_REG =================================================== */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_TEST2_Pos (10UL) /*!< TIN_CNT_TEST2 (Bit 10) */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_TEST2_Msk (0x7c00UL) /*!< TIN_CNT_TEST2 (Bitfield-Mask: 0x1f) */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_TEST1_Pos (5UL) /*!< TIN_CNT_TEST1 (Bit 5) */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_TEST1_Msk (0x3e0UL) /*!< TIN_CNT_TEST1 (Bitfield-Mask: 0x1f) */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_BASE_Pos (0UL) /*!< TIN_CNT_BASE (Bit 0) */ + #define RTC_CNT_BASE_TESTI_REG_TIN_CNT_BASE_Msk (0x1fUL) /*!< TIN_CNT_BASE (Bitfield-Mask: 0x1f) */ +/* ===================================================== CNT_TESTI_REG ===================================================== */ + #define RTC_CNT_TESTI_REG_DFT_NBIAS_TRIM_Pos (31UL) /*!< DFT_NBIAS_TRIM (Bit 31) */ + #define RTC_CNT_TESTI_REG_DFT_NBIAS_TRIM_Msk (0x80000000UL) /*!< DFT_NBIAS_TRIM (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_LDO_DPLL_MON_Pos (30UL) /*!< EN_LDO_DPLL_MON (Bit 30) */ + #define RTC_CNT_TESTI_REG_EN_LDO_DPLL_MON_Msk (0x40000000UL) /*!< EN_LDO_DPLL_MON (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_LDO_ADCSEN_MON_Pos (29UL) /*!< EN_LDO_ADCSEN_MON (Bit 29) */ + #define RTC_CNT_TESTI_REG_EN_LDO_ADCSEN_MON_Msk (0x20000000UL) /*!< EN_LDO_ADCSEN_MON (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_LP_DIG_LDO_MON_Pos (28UL) /*!< EN_LP_DIG_LDO_MON (Bit 28) */ + #define RTC_CNT_TESTI_REG_EN_LP_DIG_LDO_MON_Msk (0x10000000UL) /*!< EN_LP_DIG_LDO_MON (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_TRIM_NBIAS_I_Pos (24UL) /*!< TRIM_NBIAS_I (Bit 24) */ + #define RTC_CNT_TESTI_REG_TRIM_NBIAS_I_Msk (0xf000000UL) /*!< TRIM_NBIAS_I (Bitfield-Mask: 0x0f) */ + #define RTC_CNT_TESTI_REG_EN_DFT_VREF_Pos (23UL) /*!< EN_DFT_VREF (Bit 23) */ + #define RTC_CNT_TESTI_REG_EN_DFT_VREF_Msk (0x800000UL) /*!< EN_DFT_VREF (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_DFT_VDDD_RET_Pos (22UL) /*!< EN_DFT_VDDD_RET (Bit 22) */ + #define RTC_CNT_TESTI_REG_EN_DFT_VDDD_RET_Msk (0x400000UL) /*!< EN_DFT_VDDD_RET (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_NBIAS_TRIM_Pos (21UL) /*!< EN_NBIAS_TRIM (Bit 21) */ + #define RTC_CNT_TESTI_REG_EN_NBIAS_TRIM_Msk (0x200000UL) /*!< EN_NBIAS_TRIM (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_DFT_SEL_ANA_BGR_Pos (19UL) /*!< DFT_SEL_ANA_BGR (Bit 19) */ + #define RTC_CNT_TESTI_REG_DFT_SEL_ANA_BGR_Msk (0x180000UL) /*!< DFT_SEL_ANA_BGR (Bitfield-Mask: 0x03) */ + #define RTC_CNT_TESTI_REG_EN_DFT_NBIAS_Pos (18UL) /*!< EN_DFT_NBIAS (Bit 18) */ + #define RTC_CNT_TESTI_REG_EN_DFT_NBIAS_Msk (0x40000UL) /*!< EN_DFT_NBIAS (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_XTAL40M_LDO_MON_Pos (17UL) /*!< EN_XTAL40M_LDO_MON (Bit 17) */ + #define RTC_CNT_TESTI_REG_EN_XTAL40M_LDO_MON_Msk (0x20000UL) /*!< EN_XTAL40M_LDO_MON (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_RTC_GPO_SW_VBAT_Pos (16UL) /*!< EN_RTC_GPO_SW_VBAT (Bit 16) */ + #define RTC_CNT_TESTI_REG_EN_RTC_GPO_SW_VBAT_Msk (0x10000UL) /*!< EN_RTC_GPO_SW_VBAT (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EN_DPLL_CLK_BYPASS_Pos (11UL) /*!< EN_DPLL_CLK_BYPASS (Bit 11) */ + #define RTC_CNT_TESTI_REG_EN_DPLL_CLK_BYPASS_Msk (0x800UL) /*!< EN_DPLL_CLK_BYPASS (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_AUXADC12_CS_Pos (8UL) /*!< AUXADC12_CS (Bit 8) */ + #define RTC_CNT_TESTI_REG_AUXADC12_CS_Msk (0x700UL) /*!< AUXADC12_CS (Bitfield-Mask: 0x07) */ + #define RTC_CNT_TESTI_REG_EXT_INT_BR_Pos (7UL) /*!< EXT_INT_BR (Bit 7) */ + #define RTC_CNT_TESTI_REG_EXT_INT_BR_Msk (0x80UL) /*!< EXT_INT_BR (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_EXT_INT_BL_Pos (6UL) /*!< EXT_INT_BL (Bit 6) */ + #define RTC_CNT_TESTI_REG_EXT_INT_BL_Msk (0x40UL) /*!< EXT_INT_BL (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_I_SIGNAL_Pos (5UL) /*!< I_SIGNAL (Bit 5) */ + #define RTC_CNT_TESTI_REG_I_SIGNAL_Msk (0x20UL) /*!< I_SIGNAL (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_BR_TESTI_REG_Pos (1UL) /*!< BR_TESTI_REG (Bit 1) */ + #define RTC_CNT_TESTI_REG_BR_TESTI_REG_Msk (0x2UL) /*!< BR_TESTI_REG (Bitfield-Mask: 0x01) */ + #define RTC_CNT_TESTI_REG_IP3_PWR_ON_REG_Pos (0UL) /*!< IP3_PWR_ON_REG (Bit 0) */ + #define RTC_CNT_TESTI_REG_IP3_PWR_ON_REG_Msk (0x1UL) /*!< IP3_PWR_ON_REG (Bitfield-Mask: 0x01) */ +/* ===================================================== COMP_INT_REG ====================================================== */ + #define RTC_COMP_INT_REG_COMPINT_Pos (23UL) /*!< COMPINT (Bit 23) */ + #define RTC_COMP_INT_REG_COMPINT_Msk (0x800000UL) /*!< COMPINT (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_CLK_SEL_Pos (20UL) /*!< CLK_SEL (Bit 20) */ + #define RTC_COMP_INT_REG_CLK_SEL_Msk (0x100000UL) /*!< CLK_SEL (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_PULSE_SELECT_Pos (16UL) /*!< PULSE_SELECT (Bit 16) */ + #define RTC_COMP_INT_REG_PULSE_SELECT_Msk (0xf0000UL) /*!< PULSE_SELECT (Bitfield-Mask: 0x0f) */ + #define RTC_COMP_INT_REG_INT_CLR_Pos (15UL) /*!< INT_CLR (Bit 15) */ + #define RTC_COMP_INT_REG_INT_CLR_Msk (0x8000UL) /*!< INT_CLR (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_INT_EN_Pos (14UL) /*!< INT_EN (Bit 14) */ + #define RTC_COMP_INT_REG_INT_EN_Msk (0x4000UL) /*!< INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_G_FILTER_THR_Pos (8UL) /*!< G_FILTER_THR (Bit 8) */ + #define RTC_COMP_INT_REG_G_FILTER_THR_Msk (0x1f00UL) /*!< G_FILTER_THR (Bitfield-Mask: 0x1f) */ + #define RTC_COMP_INT_REG_G_FILTER_EN_Pos (4UL) /*!< G_FILTER_EN (Bit 4) */ + #define RTC_COMP_INT_REG_G_FILTER_EN_Msk (0x10UL) /*!< G_FILTER_EN (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_EDGE_SEL_Pos (3UL) /*!< EDGE_SEL (Bit 3) */ + #define RTC_COMP_INT_REG_EDGE_SEL_Msk (0x8UL) /*!< EDGE_SEL (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_CNT_RST_Pos (2UL) /*!< CNT_RST (Bit 2) */ + #define RTC_COMP_INT_REG_CNT_RST_Msk (0x4UL) /*!< CNT_RST (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_CNT_ENABLE_Pos (1UL) /*!< CNT_ENABLE (Bit 1) */ + #define RTC_COMP_INT_REG_CNT_ENABLE_Msk (0x2UL) /*!< CNT_ENABLE (Bitfield-Mask: 0x01) */ + #define RTC_COMP_INT_REG_OSC_15M_ENABLE_Pos (0UL) /*!< OSC_15M_ENABLE (Bit 0) */ + #define RTC_COMP_INT_REG_OSC_15M_ENABLE_Msk (0x1UL) /*!< OSC_15M_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== DCDC_CNTL_OFF_REG =================================================== */ + #define RTC_DCDC_CNTL_OFF_REG_DCDC_AUTO_PWR_ON_EN_Pos (1UL) /*!< DCDC_AUTO_PWR_ON_EN (Bit 1) */ + #define RTC_DCDC_CNTL_OFF_REG_DCDC_AUTO_PWR_ON_EN_Msk (0x2UL) /*!< DCDC_AUTO_PWR_ON_EN (Bitfield-Mask: 0x01) */ + #define RTC_DCDC_CNTL_OFF_REG_DCDC_PWR_OFF_Pos (0UL) /*!< DCDC_PWR_OFF (Bit 0) */ + #define RTC_DCDC_CNTL_OFF_REG_DCDC_PWR_OFF_Msk (0x1UL) /*!< DCDC_PWR_OFF (Bitfield-Mask: 0x01) */ +/* ==================================================== ENABLE_CTRL_REG ==================================================== */ + #define RTC_ENABLE_CTRL_REG_BLACK_OUT_HIGH_INT_EN_Pos (11UL) /*!< BLACK_OUT_HIGH_INT_EN (Bit 11) */ + #define RTC_ENABLE_CTRL_REG_BLACK_OUT_HIGH_INT_EN_Msk (0x800UL) /*!< BLACK_OUT_HIGH_INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_BLACK_OUT_LOW_INT_EN_Pos (10UL) /*!< BLACK_OUT_LOW_INT_EN (Bit 10) */ + #define RTC_ENABLE_CTRL_REG_BLACK_OUT_LOW_INT_EN_Msk (0x400UL) /*!< BLACK_OUT_LOW_INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_SLEEP5_EN_Pos (9UL) /*!< SLEEP5_EN (Bit 9) */ + #define RTC_ENABLE_CTRL_REG_SLEEP5_EN_Msk (0x200UL) /*!< SLEEP5_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_SLEEP4_EN_Pos (8UL) /*!< SLEEP4_EN (Bit 8) */ + #define RTC_ENABLE_CTRL_REG_SLEEP4_EN_Msk (0x100UL) /*!< SLEEP4_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_DIG_LDO_DELAY_Pos (5UL) /*!< DIG_LDO_DELAY (Bit 5) */ + #define RTC_ENABLE_CTRL_REG_DIG_LDO_DELAY_Msk (0x60UL) /*!< DIG_LDO_DELAY (Bitfield-Mask: 0x03) */ + #define RTC_ENABLE_CTRL_REG_REAL_CNT_LOAD_Pos (4UL) /*!< REAL_CNT_LOAD (Bit 4) */ + #define RTC_ENABLE_CTRL_REG_REAL_CNT_LOAD_Msk (0x10UL) /*!< REAL_CNT_LOAD (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_BROWN_OUT_HIGH_INT_EN_Pos (3UL) /*!< BROWN_OUT_HIGH_INT_EN (Bit 3) */ + #define RTC_ENABLE_CTRL_REG_BROWN_OUT_HIGH_INT_EN_Msk (0x8UL) /*!< BROWN_OUT_HIGH_INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_BROWN_OUT_LOW_INT_EN_Pos (2UL) /*!< BROWN_OUT_LOW_INT_EN (Bit 2) */ + #define RTC_ENABLE_CTRL_REG_BROWN_OUT_LOW_INT_EN_Msk (0x4UL) /*!< BROWN_OUT_LOW_INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_WATCHDOG_OUT_INT_EN_Pos (1UL) /*!< WATCHDOG_OUT_INT_EN (Bit 1) */ + #define RTC_ENABLE_CTRL_REG_WATCHDOG_OUT_INT_EN_Msk (0x2UL) /*!< WATCHDOG_OUT_INT_EN (Bitfield-Mask: 0x01) */ + #define RTC_ENABLE_CTRL_REG_SLEEP3_EN_Pos (0UL) /*!< SLEEP3_EN (Bit 0) */ + #define RTC_ENABLE_CTRL_REG_SLEEP3_EN_Msk (0x1UL) /*!< SLEEP3_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== FRC_CNT_0_REG ===================================================== */ + #define RTC_FRC_CNT_0_REG_FRC_CNT_0_Pos (0UL) /*!< FRC_CNT_0 (Bit 0) */ + #define RTC_FRC_CNT_0_REG_FRC_CNT_0_Msk (0xffffffffUL) /*!< FRC_CNT_0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== FRC_CNT_1_REG ===================================================== */ + #define RTC_FRC_CNT_1_REG_FRC_CNT_1_Pos (0UL) /*!< FRC_CNT_1 (Bit 0) */ + #define RTC_FRC_CNT_1_REG_FRC_CNT_1_Msk (0xfUL) /*!< FRC_CNT_1 (Bitfield-Mask: 0x0f) */ +/* =================================================== GPIO_WAKEUP0_REG ==================================================== */ + #define RTC_GPIO_WAKEUP0_REG_GPIO_WAKEUP_EDGE_INVERSION_SEL_Pos (0UL) /*!< GPIO_WAKEUP_EDGE_INVERSION_SEL (Bit 0) */ + #define RTC_GPIO_WAKEUP0_REG_GPIO_WAKEUP_EDGE_INVERSION_SEL_Msk (0x7ffUL) /*!< GPIO_WAKEUP_EDGE_INVERSION_SEL (Bitfield-Mask: 0x7ff) */ +/* =================================================== GPIO_WAKEUP1_REG ==================================================== */ + #define RTC_GPIO_WAKEUP1_REG_GPIO_WAKEUP_EN_SEL_Pos (16UL) /*!< GPIO_WAKEUP_EN_SEL (Bit 16) */ + #define RTC_GPIO_WAKEUP1_REG_GPIO_WAKEUP_EN_SEL_Msk (0x7ff0000UL) /*!< GPIO_WAKEUP_EN_SEL (Bitfield-Mask: 0x7ff) */ + #define RTC_GPIO_WAKEUP1_REG_GPIO_WAKEUP_SRC_Pos (0UL) /*!< GPIO_WAKEUP_SRC (Bit 0) */ + #define RTC_GPIO_WAKEUP1_REG_GPIO_WAKEUP_SRC_Msk (0x7ffUL) /*!< GPIO_WAKEUP_SRC (Bitfield-Mask: 0x7ff) */ +/* ====================================================== INT_THR_REG ====================================================== */ + #define RTC_INT_THR_REG_INT_THR_Pos (0UL) /*!< INT_THR (Bit 0) */ + #define RTC_INT_THR_REG_INT_THR_Msk (0xffffffffUL) /*!< INT_THR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IP4_FLDO_BG_CONT_REG ================================================== */ + #define RTC_IP4_FLDO_BG_CONT_REG_F_DIO_ST_BYP_EN_Pos (12UL) /*!< F_DIO_ST_BYP_EN (Bit 12) */ + #define RTC_IP4_FLDO_BG_CONT_REG_F_DIO_ST_BYP_EN_Msk (0x1000UL) /*!< F_DIO_ST_BYP_EN (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_F_DIO_ST_CTRL_Pos (8UL) /*!< F_DIO_ST_CTRL (Bit 8) */ + #define RTC_IP4_FLDO_BG_CONT_REG_F_DIO_ST_CTRL_Msk (0xf00UL) /*!< F_DIO_ST_CTRL (Bitfield-Mask: 0x0f) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM2_Pos (5UL) /*!< VBG_TRIM2 (Bit 5) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM2_Msk (0x20UL) /*!< VBG_TRIM2 (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM1_Pos (4UL) /*!< VBG_TRIM1 (Bit 4) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM1_Msk (0x10UL) /*!< VBG_TRIM1 (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM0_Pos (3UL) /*!< VBG_TRIM0 (Bit 3) */ + #define RTC_IP4_FLDO_BG_CONT_REG_VBG_TRIM0_Msk (0x8UL) /*!< VBG_TRIM0 (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL2_Pos (2UL) /*!< FLDO_VCTRL2 (Bit 2) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL2_Msk (0x4UL) /*!< FLDO_VCTRL2 (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL1_Pos (1UL) /*!< FLDO_VCTRL1 (Bit 1) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL1_Msk (0x2UL) /*!< FLDO_VCTRL1 (Bitfield-Mask: 0x01) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL0_Pos (0UL) /*!< FLDO_VCTRL0 (Bit 0) */ + #define RTC_IP4_FLDO_BG_CONT_REG_FLDO_VCTRL0_Msk (0x1UL) /*!< FLDO_VCTRL0 (Bitfield-Mask: 0x01) */ +/* ==================================================== LDO_ENABLE2_REG ==================================================== */ + #define RTC_LDO_ENABLE2_REG_EN_TST_INT_Pos (7UL) /*!< EN_TST_INT (Bit 7) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_INT_Msk (0x80UL) /*!< EN_TST_INT (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO3_Pos (6UL) /*!< EN_TST_GPIO3 (Bit 6) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO3_Msk (0x40UL) /*!< EN_TST_GPIO3 (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO2_Pos (5UL) /*!< EN_TST_GPIO2 (Bit 5) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO2_Msk (0x20UL) /*!< EN_TST_GPIO2 (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO1_Pos (4UL) /*!< EN_TST_GPIO1 (Bit 4) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO1_Msk (0x10UL) /*!< EN_TST_GPIO1 (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO0_Pos (3UL) /*!< EN_TST_GPIO0 (Bit 3) */ + #define RTC_LDO_ENABLE2_REG_EN_TST_GPIO0_Msk (0x8UL) /*!< EN_TST_GPIO0 (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_ULDO_MAN_CONT_VALUE_Pos (2UL) /*!< ULDO_MAN_CONT_VALUE (Bit 2) */ + #define RTC_LDO_ENABLE2_REG_ULDO_MAN_CONT_VALUE_Msk (0x4UL) /*!< ULDO_MAN_CONT_VALUE (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_ULDO_MAN_CONT_Pos (1UL) /*!< ULDO_MAN_CONT (Bit 1) */ + #define RTC_LDO_ENABLE2_REG_ULDO_MAN_CONT_Msk (0x2UL) /*!< ULDO_MAN_CONT (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE2_REG_RTC_XTAL40M_EN_Pos (0UL) /*!< RTC_XTAL40M_EN (Bit 0) */ + #define RTC_LDO_ENABLE2_REG_RTC_XTAL40M_EN_Msk (0x1UL) /*!< RTC_XTAL40M_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== LDO_ENABLE_REG ===================================================== */ + #define RTC_LDO_ENABLE_REG_CFG_LPDIG_LDO_V_Pos (26UL) /*!< CFG_LPDIG_LDO_V (Bit 26) */ + #define RTC_LDO_ENABLE_REG_CFG_LPDIG_LDO_V_Msk (0x3c000000UL) /*!< CFG_LPDIG_LDO_V (Bitfield-Mask: 0x0f) */ + #define RTC_LDO_ENABLE_REG_CFG_LPDIGLDO_I_Pos (24UL) /*!< CFG_LPDIGLDO_I (Bit 24) */ + #define RTC_LDO_ENABLE_REG_CFG_LPDIGLDO_I_Msk (0x3000000UL) /*!< CFG_LPDIGLDO_I (Bitfield-Mask: 0x03) */ + #define RTC_LDO_ENABLE_REG_EN_LP_DIG_LDO_Pos (23UL) /*!< EN_LP_DIG_LDO (Bit 23) */ + #define RTC_LDO_ENABLE_REG_EN_LP_DIG_LDO_Msk (0x800000UL) /*!< EN_LP_DIG_LDO (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_CTRL_ST_PA_DCDC_Pos (18UL) /*!< CTRL_ST_PA_DCDC (Bit 18) */ + #define RTC_LDO_ENABLE_REG_CTRL_ST_PA_DCDC_Msk (0x7c0000UL) /*!< CTRL_ST_PA_DCDC (Bitfield-Mask: 0x1f) */ + #define RTC_LDO_ENABLE_REG_EN_DCDC_PA_Pos (17UL) /*!< EN_DCDC_PA (Bit 17) */ + #define RTC_LDO_ENABLE_REG_EN_DCDC_PA_Msk (0x20000UL) /*!< EN_DCDC_PA (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_EN_ST_PAD_DCDC_BYP_Pos (16UL) /*!< EN_ST_PAD_DCDC_BYP (Bit 16) */ + #define RTC_LDO_ENABLE_REG_EN_ST_PAD_DCDC_BYP_Msk (0x10000UL) /*!< EN_ST_PAD_DCDC_BYP (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_FLASH_LDO_AUTO_OFF_Pos (15UL) /*!< FLASH_LDO_AUTO_OFF (Bit 15) */ + #define RTC_LDO_ENABLE_REG_FLASH_LDO_AUTO_OFF_Msk (0x8000UL) /*!< FLASH_LDO_AUTO_OFF (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DCDC_CTRL_OFF_Pos (14UL) /*!< LDO_EN_DCDC_CTRL_OFF (Bit 14) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DCDC_CTRL_OFF_Msk (0x4000UL) /*!< LDO_EN_DCDC_CTRL_OFF (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_BOOST_PWR_OFF_Pos (13UL) /*!< LDO_EN_BOOST_PWR_OFF (Bit 13) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_BOOST_PWR_OFF_Msk (0x2000UL) /*!< LDO_EN_BOOST_PWR_OFF (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_RESET_12V_HOLD_EN_Pos (12UL) /*!< LDO_EN_RESET_12V_HOLD_EN (Bit 12) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_RESET_12V_HOLD_EN_Msk (0x1000UL) /*!< LDO_EN_RESET_12V_HOLD_EN (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_FLASH_DIO_MANUAL_VAL_Pos (11UL) /*!< LDO_EN_FLASH_DIO_MANUAL_VAL (Bit 11) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_FLASH_DIO_MANUAL_VAL_Msk (0x800UL) /*!< LDO_EN_FLASH_DIO_MANUAL_VAL (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_FLASH_DIO_MANUAL_MODE_Pos (10UL) /*!< LDO_EN_FLASH_DIO_MANUAL_MODE (Bit 10) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_FLASH_DIO_MANUAL_MODE_Msk (0x400UL) /*!< LDO_EN_FLASH_DIO_MANUAL_MODE (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_IP1_LDO_Pos (9UL) /*!< LDO_EN_PDB_IP1_LDO (Bit 9) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_IP1_LDO_Msk (0x200UL) /*!< LDO_EN_PDB_IP1_LDO (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_RF_LDO_Pos (8UL) /*!< LDO_EN_PDB_RF_LDO (Bit 8) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_RF_LDO_Msk (0x100UL) /*!< LDO_EN_PDB_RF_LDO (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DIG_LDO_CNTL_Pos (7UL) /*!< LDO_EN_DIG_LDO_CNTL (Bit 7) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DIG_LDO_CNTL_Msk (0x80UL) /*!< LDO_EN_DIG_LDO_CNTL (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DCDC_CNTL_XTAL_Pos (6UL) /*!< LDO_EN_DCDC_CNTL_XTAL (Bit 6) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_DCDC_CNTL_XTAL_Msk (0x40UL) /*!< LDO_EN_DCDC_CNTL_XTAL (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_ULDO_Pos (5UL) /*!< LDO_EN_PDB_ULDO (Bit 5) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_ULDO_Msk (0x20UL) /*!< LDO_EN_PDB_ULDO (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_IP3_OTP_Pos (4UL) /*!< LDO_EN_PDB_IP3_OTP (Bit 4) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_IP3_OTP_Msk (0x10UL) /*!< LDO_EN_PDB_IP3_OTP (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_OTP_PWRPRDY_Pos (3UL) /*!< LDO_EN_OTP_PWRPRDY (Bit 3) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_OTP_PWRPRDY_Msk (0x8UL) /*!< LDO_EN_OTP_PWRPRDY (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_LDO_PLL1_Pos (2UL) /*!< LDO_EN_LDO_PLL1 (Bit 2) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_LDO_PLL1_Msk (0x4UL) /*!< LDO_EN_LDO_PLL1 (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_EN_FDIO_PULLDN_Pos (1UL) /*!< EN_FDIO_PULLDN (Bit 1) */ + #define RTC_LDO_ENABLE_REG_EN_FDIO_PULLDN_Msk (0x2UL) /*!< EN_FDIO_PULLDN (Bitfield-Mask: 0x01) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_XTAL_NOISE_REDU_Pos (0UL) /*!< LDO_EN_PDB_XTAL_NOISE_REDU (Bit 0) */ + #define RTC_LDO_ENABLE_REG_LDO_EN_PDB_XTAL_NOISE_REDU_Msk (0x1UL) /*!< LDO_EN_PDB_XTAL_NOISE_REDU (Bitfield-Mask: 0x01) */ +/* ===================================================== PULSE_CNT_REG ===================================================== */ + #define RTC_PULSE_CNT_REG_PULSE_CNT_Pos (0UL) /*!< PULSE_CNT (Bit 0) */ + #define RTC_PULSE_CNT_REG_PULSE_CNT_Msk (0xffffffffUL) /*!< PULSE_CNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== RCX32K_REG ======================================================= */ + #define RTC_RCX32K_REG_TRIM_RCX32K_COSC_Pos (16UL) /*!< TRIM_RCX32K_COSC (Bit 16) */ + #define RTC_RCX32K_REG_TRIM_RCX32K_COSC_Msk (0x30000UL) /*!< TRIM_RCX32K_COSC (Bitfield-Mask: 0x03) */ + #define RTC_RCX32K_REG_CFG_TEST_HI_Pos (14UL) /*!< CFG_TEST_HI (Bit 14) */ + #define RTC_RCX32K_REG_CFG_TEST_HI_Msk (0xc000UL) /*!< CFG_TEST_HI (Bitfield-Mask: 0x03) */ + #define RTC_RCX32K_REG_TRIM_RCX32K_ROSC_Pos (0UL) /*!< TRIM_RCX32K_ROSC (Bit 0) */ + #define RTC_RCX32K_REG_TRIM_RCX32K_ROSC_Msk (0x3fffUL) /*!< TRIM_RCX32K_ROSC (Bitfield-Mask: 0x3fff) */ +/* ==================================================== READ_STATUS_REG ==================================================== */ + #define RTC_READ_STATUS_REG_DCDC_PA_OK_RD_STATUS_Pos (15UL) /*!< DCDC_PA_OK_RD_STATUS (Bit 15) */ + #define RTC_READ_STATUS_REG_DCDC_PA_OK_RD_STATUS_Msk (0x8000UL) /*!< DCDC_PA_OK_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_LP_DIG_LDO_OK_RD_STATUS_Pos (14UL) /*!< LP_DIG_LDO_OK_RD_STATUS (Bit 14) */ + #define RTC_READ_STATUS_REG_LP_DIG_LDO_OK_RD_STATUS_Msk (0x4000UL) /*!< LP_DIG_LDO_OK_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_IP1_LDO_RDY_VBAT_RD_STATUS_Pos (13UL) /*!< IP1_LDO_RDY_VBAT_RD_STATUS (Bit 13) */ + #define RTC_READ_STATUS_REG_IP1_LDO_RDY_VBAT_RD_STATUS_Msk (0x2000UL) /*!< IP1_LDO_RDY_VBAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_DCDC_RDY_VBAT_RD_STATUS_Pos (12UL) /*!< DCDC_RDY_VBAT_RD_STATUS (Bit 12) */ + #define RTC_READ_STATUS_REG_DCDC_RDY_VBAT_RD_STATUS_Msk (0x1000UL) /*!< DCDC_RDY_VBAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_F_LDO_RDY_RD_STATUS_Pos (11UL) /*!< F_LDO_RDY_RD_STATUS (Bit 11) */ + #define RTC_READ_STATUS_REG_F_LDO_RDY_RD_STATUS_Msk (0x800UL) /*!< F_LDO_RDY_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_DIG_LDO_RDY_VBAT_RD_STATUS_Pos (10UL) /*!< DIG_LDO_RDY_VBAT_RD_STATUS (Bit 10) */ + #define RTC_READ_STATUS_REG_DIG_LDO_RDY_VBAT_RD_STATUS_Msk (0x400UL) /*!< DIG_LDO_RDY_VBAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_RF_LDO_RDY_VBAT_RD_STATUS_Pos (9UL) /*!< RF_LDO_RDY_VBAT_RD_STATUS (Bit 9) */ + #define RTC_READ_STATUS_REG_RF_LDO_RDY_VBAT_RD_STATUS_Msk (0x200UL) /*!< RF_LDO_RDY_VBAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_XTAL40M_RDY_VBAT_RD_STATUS_Pos (8UL) /*!< XTAL40M_RDY_VBAT_RD_STATUS (Bit 8) */ + #define RTC_READ_STATUS_REG_XTAL40M_RDY_VBAT_RD_STATUS_Msk (0x100UL) /*!< XTAL40M_RDY_VBAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_WWATCHDOGCLK_RD_STATUS_Pos (7UL) /*!< WWATCHDOGCLK_RD_STATUS (Bit 7) */ + #define RTC_READ_STATUS_REG_WWATCHDOGCLK_RD_STATUS_Msk (0x80UL) /*!< WWATCHDOGCLK_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_RESET_POSITION_RD_STATUS_Pos (6UL) /*!< RESET_POSITION_RD_STATUS (Bit 6) */ + #define RTC_READ_STATUS_REG_RESET_POSITION_RD_STATUS_Msk (0x40UL) /*!< RESET_POSITION_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_OTP_RDY_RD_STATUS_Pos (5UL) /*!< OTP_RDY_RD_STATUS (Bit 5) */ + #define RTC_READ_STATUS_REG_OTP_RDY_RD_STATUS_Msk (0x20UL) /*!< OTP_RDY_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_WTEMPEQCOMPWKCNT_RD_STATUS_Pos (4UL) /*!< WTEMPEQCOMPWKCNT_RD_STATUS (Bit 4) */ + #define RTC_READ_STATUS_REG_WTEMPEQCOMPWKCNT_RD_STATUS_Msk (0x10UL) /*!< WTEMPEQCOMPWKCNT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_XTAL_RDY_BAT_RD_STATUS_Pos (3UL) /*!< XTAL_RDY_BAT_RD_STATUS (Bit 3) */ + #define RTC_READ_STATUS_REG_XTAL_RDY_BAT_RD_STATUS_Msk (0x8UL) /*!< XTAL_RDY_BAT_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_X12_CLK_RD_STATUS_Pos (1UL) /*!< X12_CLK_RD_STATUS (Bit 1) */ + #define RTC_READ_STATUS_REG_X12_CLK_RD_STATUS_Msk (0x2UL) /*!< X12_CLK_RD_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_READ_STATUS_REG_WAKE_UP_SOURCE__RD_STATUS_Pos (0UL) /*!< WAKE_UP_SOURCE__RD_STATUS (Bit 0) */ + #define RTC_READ_STATUS_REG_WAKE_UP_SOURCE__RD_STATUS_Msk (0x1UL) /*!< WAKE_UP_SOURCE__RD_STATUS (Bitfield-Mask: 0x01) */ +/* =================================================== RTC_ACC_ADDR_REG ==================================================== */ + #define RTC_RTC_ACC_ADDR_REG_RTC_ACC_ADDR_Pos (0UL) /*!< RTC_ACC_ADDR (Bit 0) */ + #define RTC_RTC_ACC_ADDR_REG_RTC_ACC_ADDR_Msk (0x7fUL) /*!< RTC_ACC_ADDR (Bitfield-Mask: 0x7f) */ +/* ================================================== RTC_ACC_AUTO_EN_REG ================================================== */ + #define RTC_RTC_ACC_AUTO_EN_REG_RTC_ACC_AUTO_EN_Pos (0UL) /*!< RTC_ACC_AUTO_EN (Bit 0) */ + #define RTC_RTC_ACC_AUTO_EN_REG_RTC_ACC_AUTO_EN_Msk (0x1UL) /*!< RTC_ACC_AUTO_EN (Bitfield-Mask: 0x01) */ +/* =================================================== RTC_ACC_BUSY_REG ==================================================== */ + #define RTC_RTC_ACC_BUSY_REG_RTC_ACC_BUSY_Pos (0UL) /*!< RTC_ACC_BUSY (Bit 0) */ + #define RTC_RTC_ACC_BUSY_REG_RTC_ACC_BUSY_Msk (0x1UL) /*!< RTC_ACC_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================== RTC_ACC_OP_TYPE_REG ================================================== */ + #define RTC_RTC_ACC_OP_TYPE_REG_RTC_ACC_OP_TYPE_Pos (0UL) /*!< RTC_ACC_OP_TYPE (Bit 0) */ + #define RTC_RTC_ACC_OP_TYPE_REG_RTC_ACC_OP_TYPE_Msk (0x7UL) /*!< RTC_ACC_OP_TYPE (Bitfield-Mask: 0x07) */ +/* ==================================================== RTC_ACC_REQ_REG ==================================================== */ + #define RTC_RTC_ACC_REQ_REG_RTC_ACC_REQ_CLR_Pos (1UL) /*!< RTC_ACC_REQ_CLR (Bit 1) */ + #define RTC_RTC_ACC_REQ_REG_RTC_ACC_REQ_CLR_Msk (0x2UL) /*!< RTC_ACC_REQ_CLR (Bitfield-Mask: 0x01) */ + #define RTC_RTC_ACC_REQ_REG_RTC_ACC_REQ_START_Pos (0UL) /*!< RTC_ACC_REQ_START (Bit 0) */ + #define RTC_RTC_ACC_REQ_REG_RTC_ACC_REQ_START_Msk (0x1UL) /*!< RTC_ACC_REQ_START (Bitfield-Mask: 0x01) */ +/* =================================================== RTC_ACC_WDATA_REG =================================================== */ + #define RTC_RTC_ACC_WDATA_REG_RTC_ACC_WDATA_Pos (0UL) /*!< RTC_ACC_WDATA (Bit 0) */ + #define RTC_RTC_ACC_WDATA_REG_RTC_ACC_WDATA_Msk (0xffffffffUL) /*!< RTC_ACC_WDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== RTC_CLK_GR_CYC_REG =================================================== */ + #define RTC_RTC_CLK_GR_CYC_REG_RTC_CLK_GR_CYC_Pos (0UL) /*!< RTC_CLK_GR_CYC (Bit 0) */ + #define RTC_RTC_CLK_GR_CYC_REG_RTC_CLK_GR_CYC_Msk (0xfUL) /*!< RTC_CLK_GR_CYC (Bitfield-Mask: 0x0f) */ +/* ==================================================== RTC_CLK_INV_REG ==================================================== */ + #define RTC_RTC_CLK_INV_REG_RTC_CLK_INV_Pos (0UL) /*!< RTC_CLK_INV (Bit 0) */ + #define RTC_RTC_CLK_INV_REG_RTC_CLK_INV_Msk (0x1UL) /*!< RTC_CLK_INV (Bitfield-Mask: 0x01) */ +/* ===================================================== RTC_EDGE_REG ====================================================== */ + #define RTC_RTC_EDGE_REG_RTC_EDGE_AUTO_N_Pos (8UL) /*!< RTC_EDGE_AUTO_N (Bit 8) */ + #define RTC_RTC_EDGE_REG_RTC_EDGE_AUTO_N_Msk (0x100UL) /*!< RTC_EDGE_AUTO_N (Bitfield-Mask: 0x01) */ + #define RTC_RTC_EDGE_REG_RTC_EDGE_EN_Pos (0UL) /*!< RTC_EDGE_EN (Bit 0) */ + #define RTC_RTC_EDGE_REG_RTC_EDGE_EN_Msk (0x3UL) /*!< RTC_EDGE_EN (Bitfield-Mask: 0x03) */ +/* ================================================== RTC_EXP_CLR_IRQ_REG ================================================== */ + #define RTC_RTC_EXP_CLR_IRQ_REG_RTC_EXP_CLR_IRQ_Pos (1UL) /*!< RTC_EXP_CLR_IRQ (Bit 1) */ + #define RTC_RTC_EXP_CLR_IRQ_REG_RTC_EXP_CLR_IRQ_Msk (0x2UL) /*!< RTC_EXP_CLR_IRQ (Bitfield-Mask: 0x01) */ + #define RTC_RTC_EXP_CLR_IRQ_REG_RTC_EXP_START_Pos (0UL) /*!< RTC_EXP_START (Bit 0) */ + #define RTC_RTC_EXP_CLR_IRQ_REG_RTC_EXP_START_Msk (0x1UL) /*!< RTC_EXP_START (Bitfield-Mask: 0x01) */ +/* ================================================== RTC_EXP_IRQ_EN_REG =================================================== */ + #define RTC_RTC_EXP_IRQ_EN_REG_RTC_EXP_IRQ_EN_Pos (0UL) /*!< RTC_EXP_IRQ_EN (Bit 0) */ + #define RTC_RTC_EXP_IRQ_EN_REG_RTC_EXP_IRQ_EN_Msk (0x7UL) /*!< RTC_EXP_IRQ_EN (Bitfield-Mask: 0x07) */ +/* ================================================== RTC_EXP_OP_STS_REG =================================================== */ + #define RTC_RTC_EXP_OP_STS_REG_RTC_EXP_OP_STATUS_Pos (8UL) /*!< RTC_EXP_OP_STATUS (Bit 8) */ + #define RTC_RTC_EXP_OP_STS_REG_RTC_EXP_OP_STATUS_Msk (0x100UL) /*!< RTC_EXP_OP_STATUS (Bitfield-Mask: 0x01) */ + #define RTC_RTC_EXP_OP_STS_REG_RTC_EXP_IRQ_STATUS_Pos (0UL) /*!< RTC_EXP_IRQ_STATUS (Bit 0) */ + #define RTC_RTC_EXP_OP_STS_REG_RTC_EXP_IRQ_STATUS_Msk (0x7UL) /*!< RTC_EXP_IRQ_STATUS (Bitfield-Mask: 0x07) */ +/* ==================================================== RTC_EXP_TH0_REG ==================================================== */ + #define RTC_RTC_EXP_TH0_REG_RTC_EXP_TH0_Pos (0UL) /*!< RTC_EXP_TH0 (Bit 0) */ + #define RTC_RTC_EXP_TH0_REG_RTC_EXP_TH0_Msk (0xffffffffUL) /*!< RTC_EXP_TH0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RTC_EXP_TH1_REG ==================================================== */ + #define RTC_RTC_EXP_TH1_REG_RTC_EXP_TH1_Pos (0UL) /*!< RTC_EXP_TH1 (Bit 0) */ + #define RTC_RTC_EXP_TH1_REG_RTC_EXP_TH1_Msk (0xfUL) /*!< RTC_EXP_TH1 (Bitfield-Mask: 0x0f) */ +/* ================================================== RTC_FRC_STATUS_REG =================================================== */ + #define RTC_RTC_FRC_STATUS_REG_RTC_FRC_STATUS_Pos (0UL) /*!< RTC_FRC_STATUS (Bit 0) */ + #define RTC_RTC_FRC_STATUS_REG_RTC_FRC_STATUS_Msk (0x7UL) /*!< RTC_FRC_STATUS (Bitfield-Mask: 0x07) */ +/* ====================================================== RTC_IF_REG ======================================================= */ + #define RTC_RTC_IF_REG_RTC_IF_TYPE_Pos (24UL) /*!< RTC_IF_TYPE (Bit 24) */ + #define RTC_RTC_IF_REG_RTC_IF_TYPE_Msk (0x1000000UL) /*!< RTC_IF_TYPE (Bitfield-Mask: 0x01) */ + #define RTC_RTC_IF_REG_RTC_IF_2_DL_EN_Pos (18UL) /*!< RTC_IF_2_DL_EN (Bit 18) */ + #define RTC_RTC_IF_REG_RTC_IF_2_DL_EN_Msk (0x40000UL) /*!< RTC_IF_2_DL_EN (Bitfield-Mask: 0x01) */ + #define RTC_RTC_IF_REG_RTC_IF_1_DL_EN_Pos (17UL) /*!< RTC_IF_1_DL_EN (Bit 17) */ + #define RTC_RTC_IF_REG_RTC_IF_1_DL_EN_Msk (0x20000UL) /*!< RTC_IF_1_DL_EN (Bitfield-Mask: 0x01) */ + #define RTC_RTC_IF_REG_RTC_IF_0_DL_EN_Pos (16UL) /*!< RTC_IF_0_DL_EN (Bit 16) */ + #define RTC_RTC_IF_REG_RTC_IF_0_DL_EN_Msk (0x10000UL) /*!< RTC_IF_0_DL_EN (Bitfield-Mask: 0x01) */ + #define RTC_RTC_IF_REG_RTC_IF_2_DL_Pos (8UL) /*!< RTC_IF_2_DL (Bit 8) */ + #define RTC_RTC_IF_REG_RTC_IF_2_DL_Msk (0xf00UL) /*!< RTC_IF_2_DL (Bitfield-Mask: 0x0f) */ + #define RTC_RTC_IF_REG_RTC_IF_1_DL_Pos (4UL) /*!< RTC_IF_1_DL (Bit 4) */ + #define RTC_RTC_IF_REG_RTC_IF_1_DL_Msk (0xf0UL) /*!< RTC_IF_1_DL (Bitfield-Mask: 0x0f) */ + #define RTC_RTC_IF_REG_RTC_IF_0_DL_Pos (0UL) /*!< RTC_IF_0_DL (Bit 0) */ + #define RTC_RTC_IF_REG_RTC_IF_0_DL_Msk (0xfUL) /*!< RTC_IF_0_DL (Bitfield-Mask: 0x0f) */ +/* ==================================================== RTC_IRQ_EN_REG ===================================================== */ + #define RTC_RTC_IRQ_EN_REG_RTC_IRQ_EN_Pos (0UL) /*!< RTC_IRQ_EN (Bit 0) */ + #define RTC_RTC_IRQ_EN_REG_RTC_IRQ_EN_Msk (0x3UL) /*!< RTC_IRQ_EN (Bitfield-Mask: 0x03) */ +/* ================================================== RTC_IRQ_STATUS_REG =================================================== */ + #define RTC_RTC_IRQ_STATUS_REG_RTC_IRQ_STATUS_Pos (0UL) /*!< RTC_IRQ_STATUS (Bit 0) */ + #define RTC_RTC_IRQ_STATUS_REG_RTC_IRQ_STATUS_Msk (0x3UL) /*!< RTC_IRQ_STATUS (Bitfield-Mask: 0x03) */ +/* ==================================================== RTC_MIRROR_REG ===================================================== */ + #define RTC_RTC_MIRROR_REG_RTC_MR_EN_Pos (1UL) /*!< RTC_MR_EN (Bit 1) */ + #define RTC_RTC_MIRROR_REG_RTC_MR_EN_Msk (0x2UL) /*!< RTC_MR_EN (Bitfield-Mask: 0x01) */ + #define RTC_RTC_MIRROR_REG_RTC_OP_EN_Pos (0UL) /*!< RTC_OP_EN (Bit 0) */ + #define RTC_RTC_MIRROR_REG_RTC_OP_EN_Msk (0x1UL) /*!< RTC_OP_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== RTC_MR_FRC0_REG ==================================================== */ + #define RTC_RTC_MR_FRC0_REG_RTC_MR_FRC0_Pos (0UL) /*!< RTC_MR_FRC0 (Bit 0) */ + #define RTC_RTC_MR_FRC0_REG_RTC_MR_FRC0_Msk (0xffffffffUL) /*!< RTC_MR_FRC0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RTC_MR_FRC1_REG ==================================================== */ + #define RTC_RTC_MR_FRC1_REG_RTC_MR_FRC1_Pos (0UL) /*!< RTC_MR_FRC1 (Bit 0) */ + #define RTC_RTC_MR_FRC1_REG_RTC_MR_FRC1_Msk (0xfUL) /*!< RTC_MR_FRC1 (Bitfield-Mask: 0x0f) */ +/* ================================================== RTC_MR_SEL_8040_REG ================================================== */ + #define RTC_RTC_MR_SEL_8040_REG_RTC_MR_SEL_8040_Pos (0UL) /*!< RTC_MR_SEL_8040 (Bit 0) */ + #define RTC_RTC_MR_SEL_8040_REG_RTC_MR_SEL_8040_Msk (0x1UL) /*!< RTC_MR_SEL_8040 (Bitfield-Mask: 0x01) */ +/* ====================================================== RTC_REQ_REG ====================================================== */ + #define RTC_RTC_REQ_REG_RTC_REQ_LOAD_MR_Pos (3UL) /*!< RTC_REQ_LOAD_MR (Bit 3) */ + #define RTC_RTC_REQ_REG_RTC_REQ_LOAD_MR_Msk (0x8UL) /*!< RTC_REQ_LOAD_MR (Bitfield-Mask: 0x01) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_IRQ_Pos (2UL) /*!< RTC_REQ_CLR_IRQ (Bit 2) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_IRQ_Msk (0x4UL) /*!< RTC_REQ_CLR_IRQ (Bitfield-Mask: 0x01) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_MR_Pos (1UL) /*!< RTC_REQ_CLR_MR (Bit 1) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_MR_Msk (0x2UL) /*!< RTC_REQ_CLR_MR (Bitfield-Mask: 0x01) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_Pos (0UL) /*!< RTC_REQ_CLR (Bit 0) */ + #define RTC_RTC_REQ_REG_RTC_REQ_CLR_Msk (0x1UL) /*!< RTC_REQ_CLR (Bitfield-Mask: 0x01) */ +/* ==================================================== RTM_CONTROL_REG ==================================================== */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_IO_RETEN_CTRL_Pos (16UL) /*!< RTM_CTRL_IO_RETEN_CTRL (Bit 16) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_IO_RETEN_CTRL_Msk (0x1f0000UL) /*!< RTM_CTRL_IO_RETEN_CTRL (Bitfield-Mask: 0x1f) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_RET_RET_Pos (11UL) /*!< RTM_CTRL_RET_RET (Bit 11) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_RET_RET_Msk (0x3800UL) /*!< RTM_CTRL_RET_RET (Bitfield-Mask: 0x07) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_RET_SLR_Pos (8UL) /*!< RTM_CTRL_RET_SLR (Bit 8) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_RET_SLR_Msk (0x700UL) /*!< RTM_CTRL_RET_SLR (Bitfield-Mask: 0x07) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PWR_DN_INFO_Pos (3UL) /*!< RTM_CTRL_PWR_DN_INFO (Bit 3) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PWR_DN_INFO_Msk (0x78UL) /*!< RTM_CTRL_PWR_DN_INFO (Bitfield-Mask: 0x0f) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PDP_ISO_SHARED_IO_Pos (2UL) /*!< RTM_CTRL_PDP_ISO_SHARED_IO (Bit 2) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PDP_ISO_SHARED_IO_Msk (0x4UL) /*!< RTM_CTRL_PDP_ISO_SHARED_IO (Bitfield-Mask: 0x01) */ + #define RTC_RTM_CONTROL_REG_RTM_INFO_Pos (1UL) /*!< RTM_INFO (Bit 1) */ + #define RTC_RTM_CONTROL_REG_RTM_INFO_Msk (0x2UL) /*!< RTM_INFO (Bitfield-Mask: 0x01) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PDB_ISO_Pos (0UL) /*!< RTM_CTRL_PDB_ISO (Bit 0) */ + #define RTC_RTM_CONTROL_REG_RTM_CTRL_PDB_ISO_Msk (0x1UL) /*!< RTM_CTRL_PDB_ISO (Bitfield-Mask: 0x01) */ +/* ================================================ TEST_ULDO_SLP_CTRL_REG ================================================= */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_ULDO_HICTRL_SLP_Pos (12UL) /*!< ULDO_HICTRL_SLP (Bit 12) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_ULDO_HICTRL_SLP_Msk (0x3000UL) /*!< ULDO_HICTRL_SLP (Bitfield-Mask: 0x03) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_ULDO_VCTRL_SLP_Pos (8UL) /*!< ULDO_VCTRL_SLP (Bit 8) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_ULDO_VCTRL_SLP_Msk (0xf00UL) /*!< ULDO_VCTRL_SLP (Bitfield-Mask: 0x0f) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SS_EN_SEL_Pos (6UL) /*!< TEST_SS_EN_SEL (Bit 6) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SS_EN_SEL_Msk (0xc0UL) /*!< TEST_SS_EN_SEL (Bitfield-Mask: 0x03) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_DW_WAKE_UP_RST_CTRL_Pos (5UL) /*!< TEST_DW_WAKE_UP_RST_CTRL (Bit 5) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_DW_WAKE_UP_RST_CTRL_Msk (0x20UL) /*!< TEST_DW_WAKE_UP_RST_CTRL (Bitfield-Mask: 0x01) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SENSOR_OUTPUT_MUX_0_Pos (4UL) /*!< TEST_SENSOR_OUTPUT_MUX_0 (Bit 4) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SENSOR_OUTPUT_MUX_0_Msk (0x10UL) /*!< TEST_SENSOR_OUTPUT_MUX_0 (Bitfield-Mask: 0x01) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SENSOR_OUTPUT_MUX_1_Pos (3UL) /*!< TEST_SENSOR_OUTPUT_MUX_1 (Bit 3) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SENSOR_OUTPUT_MUX_1_Msk (0x8UL) /*!< TEST_SENSOR_OUTPUT_MUX_1 (Bitfield-Mask: 0x01) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SEL_8040_Pos (0UL) /*!< TEST_SEL_8040 (Bit 0) */ + #define RTC_TEST_ULDO_SLP_CTRL_REG_TEST_SEL_8040_Msk (0x7UL) /*!< TEST_SEL_8040 (Bitfield-Mask: 0x07) */ +/* ===================================================== ULDO_CONT_REG ===================================================== */ + #define RTC_ULDO_CONT_REG_DCDC_ST_BYP_Pos (29UL) /*!< DCDC_ST_BYP (Bit 29) */ + #define RTC_ULDO_CONT_REG_DCDC_ST_BYP_Msk (0x20000000UL) /*!< DCDC_ST_BYP (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_DCDC_ST_CTRL_4_0_Pos (24UL) /*!< DCDC_ST_CTRL_4_0 (Bit 24) */ + #define RTC_ULDO_CONT_REG_DCDC_ST_CTRL_4_0_Msk (0x1f000000UL) /*!< DCDC_ST_CTRL_4_0 (Bitfield-Mask: 0x1f) */ + #define RTC_ULDO_CONT_REG_FLAG_DPLL_LDO_Pos (23UL) /*!< FLAG_DPLL_LDO (Bit 23) */ + #define RTC_ULDO_CONT_REG_FLAG_DPLL_LDO_Msk (0x800000UL) /*!< FLAG_DPLL_LDO (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_FLAG_ADCSEN_LDO_Pos (22UL) /*!< FLAG_ADCSEN_LDO (Bit 22) */ + #define RTC_ULDO_CONT_REG_FLAG_ADCSEN_LDO_Msk (0x400000UL) /*!< FLAG_ADCSEN_LDO (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_FLAG_SEN_DVDD_POR_Pos (21UL) /*!< FLAG_SEN_DVDD_POR (Bit 21) */ + #define RTC_ULDO_CONT_REG_FLAG_SEN_DVDD_POR_Msk (0x200000UL) /*!< FLAG_SEN_DVDD_POR (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_FLAG_RCORE_POR_Pos (20UL) /*!< FLAG_RCORE_POR (Bit 20) */ + #define RTC_ULDO_CONT_REG_FLAG_RCORE_POR_Msk (0x100000UL) /*!< FLAG_RCORE_POR (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_FLAG_LDODCDC_POR_Pos (19UL) /*!< FLAG_LDODCDC_POR (Bit 19) */ + #define RTC_ULDO_CONT_REG_FLAG_LDODCDC_POR_Msk (0x80000UL) /*!< FLAG_LDODCDC_POR (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_FLAG_DVDD_POR_Pos (18UL) /*!< FLAG_DVDD_POR (Bit 18) */ + #define RTC_ULDO_CONT_REG_FLAG_DVDD_POR_Msk (0x40000UL) /*!< FLAG_DVDD_POR (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_RTC_XTAL32K_GM_Pos (16UL) /*!< RTC_XTAL32K_GM (Bit 16) */ + #define RTC_ULDO_CONT_REG_RTC_XTAL32K_GM_Msk (0x30000UL) /*!< RTC_XTAL32K_GM (Bitfield-Mask: 0x03) */ + #define RTC_ULDO_CONT_REG_RTC_OSC32K_ICTRL_Pos (14UL) /*!< RTC_OSC32K_ICTRL (Bit 14) */ + #define RTC_ULDO_CONT_REG_RTC_OSC32K_ICTRL_Msk (0xc000UL) /*!< RTC_OSC32K_ICTRL (Bitfield-Mask: 0x03) */ + #define RTC_ULDO_CONT_REG_RTC_XTAL32K_ICTRL_Pos (12UL) /*!< RTC_XTAL32K_ICTRL (Bit 12) */ + #define RTC_ULDO_CONT_REG_RTC_XTAL32K_ICTRL_Msk (0x3000UL) /*!< RTC_XTAL32K_ICTRL (Bitfield-Mask: 0x03) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_LICTRL_Pos (10UL) /*!< RTC_ULDO_LICTRL (Bit 10) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_LICTRL_Msk (0xc00UL) /*!< RTC_ULDO_LICTRL (Bitfield-Mask: 0x03) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_HICTRL_Pos (8UL) /*!< RTC_ULDO_HICTRL (Bit 8) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_HICTRL_Msk (0x300UL) /*!< RTC_ULDO_HICTRL (Bitfield-Mask: 0x03) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_VCTRL_Pos (4UL) /*!< RTC_ULDO_VCTRL (Bit 4) */ + #define RTC_ULDO_CONT_REG_RTC_ULDO_VCTRL_Msk (0xf0UL) /*!< RTC_ULDO_VCTRL (Bitfield-Mask: 0x0f) */ + #define RTC_ULDO_CONT_REG_PDB_TEST_BUF_Pos (1UL) /*!< PDB_TEST_BUF (Bit 1) */ + #define RTC_ULDO_CONT_REG_PDB_TEST_BUF_Msk (0x2UL) /*!< PDB_TEST_BUF (Bitfield-Mask: 0x01) */ + #define RTC_ULDO_CONT_REG_RTC_CLK_INVERSION_Pos (0UL) /*!< RTC_CLK_INVERSION (Bit 0) */ + #define RTC_ULDO_CONT_REG_RTC_CLK_INVERSION_Msk (0x1UL) /*!< RTC_CLK_INVERSION (Bitfield-Mask: 0x01) */ +/* =================================================== WAKEUP_CNT_0_REG ==================================================== */ + #define RTC_WAKEUP_CNT_0_REG_WAKEUP_CNT_0_Pos (0UL) /*!< WAKEUP_CNT_0 (Bit 0) */ + #define RTC_WAKEUP_CNT_0_REG_WAKEUP_CNT_0_Msk (0xffffffffUL) /*!< WAKEUP_CNT_0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== WAKEUP_CNT_1_REG ==================================================== */ + #define RTC_WAKEUP_CNT_1_REG_WAKEUP_CNT_1_Pos (0UL) /*!< WAKEUP_CNT_1 (Bit 0) */ + #define RTC_WAKEUP_CNT_1_REG_WAKEUP_CNT_1_Msk (0xfUL) /*!< WAKEUP_CNT_1 (Bitfield-Mask: 0x0f) */ +/* ================================================== WAKEUP_SRC_CLR_REG =================================================== */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_TIMER_IRQ_DETECT_CLEAR_Pos (6UL) /*!< WAKEUP_TIMER_IRQ_DETECT_CLEAR (Bit 6) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_TIMER_IRQ_DETECT_CLEAR_Msk (0x40UL) /*!< WAKEUP_TIMER_IRQ_DETECT_CLEAR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_PULSE_CNT_DETECT_CLEAR_Pos (5UL) /*!< WAKEUP_PULSE_CNT_DETECT_CLEAR (Bit 5) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_PULSE_CNT_DETECT_CLEAR_Msk (0x20UL) /*!< WAKEUP_PULSE_CNT_DETECT_CLEAR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_SENSOR_DETECT_CLEAR_Pos (4UL) /*!< WAKEUP_SENSOR_DETECT_CLEAR (Bit 4) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_SENSOR_DETECT_CLEAR_Msk (0x10UL) /*!< WAKEUP_SENSOR_DETECT_CLEAR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_WATCHDOGCLR_Pos (3UL) /*!< WAKEUP_WATCHDOGCLR (Bit 3) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_WATCHDOGCLR_Msk (0x8UL) /*!< WAKEUP_WATCHDOGCLR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_PORCLR_Pos (2UL) /*!< WAKEUP_PORCLR (Bit 2) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_PORCLR_Msk (0x4UL) /*!< WAKEUP_PORCLR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_EQCLR_Pos (1UL) /*!< WAKEUP_EQCLR (Bit 1) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_EQCLR_Msk (0x2UL) /*!< WAKEUP_EQCLR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_GPIOWKCLR_Pos (0UL) /*!< WAKEUP_GPIOWKCLR (Bit 0) */ + #define RTC_WAKEUP_SRC_CLR_REG_WAKEUP_GPIOWKCLR_Msk (0x1UL) /*!< WAKEUP_GPIOWKCLR (Bitfield-Mask: 0x01) */ +/* ================================================ WAKEUP_SRC_CLR_SIG_REG ================================================= */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_ADC_WAKEUP_STATUS_Pos (8UL) /*!< ADC_WAKEUP_STATUS (Bit 8) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_ADC_WAKEUP_STATUS_Msk (0xf00UL) /*!< ADC_WAKEUP_STATUS (Bitfield-Mask: 0x0f) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_TIMER_IRQ_DETECT_Pos (6UL) /*!< TIMER_IRQ_DETECT (Bit 6) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_TIMER_IRQ_DETECT_Msk (0x40UL) /*!< TIMER_IRQ_DETECT (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_PULSE_CNT_DETECT_Pos (5UL) /*!< PULSE_CNT_DETECT (Bit 5) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_PULSE_CNT_DETECT_Msk (0x20UL) /*!< PULSE_CNT_DETECT (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_ADC_DETECT_Pos (4UL) /*!< ADC_DETECT (Bit 4) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_ADC_DETECT_Msk (0x10UL) /*!< ADC_DETECT (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_WATCHDOG_DETECT_Pos (3UL) /*!< WATCHDOG_DETECT (Bit 3) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_WATCHDOG_DETECT_Msk (0x8UL) /*!< WATCHDOG_DETECT (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_POR_INDICATOR_Pos (2UL) /*!< POR_INDICATOR (Bit 2) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_POR_INDICATOR_Msk (0x4UL) /*!< POR_INDICATOR (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_FRC_COMPARE_DETECT_Pos (1UL) /*!< FRC_COMPARE_DETECT (Bit 1) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_FRC_COMPARE_DETECT_Msk (0x2UL) /*!< FRC_COMPARE_DETECT (Bitfield-Mask: 0x01) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_GPIO_WAKE_UP_DETECT_Pos (0UL) /*!< GPIO_WAKE_UP_DETECT (Bit 0) */ + #define RTC_WAKEUP_SRC_CLR_SIG_REG_GPIO_WAKE_UP_DETECT_Msk (0x1UL) /*!< GPIO_WAKE_UP_DETECT (Bitfield-Mask: 0x01) */ +/* ================================================= WDOG_CNT_BIT_POS_REG ================================================== */ + #define RTC_WDOG_CNT_BIT_POS_REG_WATCHDOG_CNT_READ_VAL_Pos (5UL) /*!< WATCHDOG_CNT_READ_VAL (Bit 5) */ + #define RTC_WDOG_CNT_BIT_POS_REG_WATCHDOG_CNT_READ_VAL_Msk (0x60UL) /*!< WATCHDOG_CNT_READ_VAL (Bitfield-Mask: 0x03) */ + #define RTC_WDOG_CNT_BIT_POS_REG_FRC35_14_BIT_SEL_Pos (0UL) /*!< FRC35_14_BIT_SEL (Bit 0) */ + #define RTC_WDOG_CNT_BIT_POS_REG_FRC35_14_BIT_SEL_Msk (0x1fUL) /*!< FRC35_14_BIT_SEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== XADC12_CNTL_REG ==================================================== */ + #define RTC_XADC12_CNTL_REG_AUXADC12_BITNUM_Pos (14UL) /*!< AUXADC12_BITNUM (Bit 14) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_BITNUM_Msk (0xc000UL) /*!< AUXADC12_BITNUM (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_IVREF_Pos (12UL) /*!< AUXADC12_IVREF (Bit 12) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_IVREF_Msk (0x3000UL) /*!< AUXADC12_IVREF (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_ICOMPS_Pos (10UL) /*!< AUXADC12_ICOMPS (Bit 10) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_ICOMPS_Msk (0xc00UL) /*!< AUXADC12_ICOMPS (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_ICOMP_Pos (8UL) /*!< AUXADC12_ICOMP (Bit 8) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_ICOMP_Msk (0x300UL) /*!< AUXADC12_ICOMP (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_CNTL_REG_SS_EN_OUTPUT_VAL_Pos (7UL) /*!< SS_EN_OUTPUT_VAL (Bit 7) */ + #define RTC_XADC12_CNTL_REG_SS_EN_OUTPUT_VAL_Msk (0x80UL) /*!< SS_EN_OUTPUT_VAL (Bitfield-Mask: 0x01) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_TRIM_Pos (4UL) /*!< AUXADC12_TRIM (Bit 4) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_TRIM_Msk (0x70UL) /*!< AUXADC12_TRIM (Bitfield-Mask: 0x07) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_PDB_Pos (1UL) /*!< AUXADC12_PDB (Bit 1) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_PDB_Msk (0x2UL) /*!< AUXADC12_PDB (Bitfield-Mask: 0x01) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_RESET_Pos (0UL) /*!< AUXADC12_RESET (Bit 0) */ + #define RTC_XADC12_CNTL_REG_AUXADC12_RESET_Msk (0x1UL) /*!< AUXADC12_RESET (Bitfield-Mask: 0x01) */ +/* =================================================== XADC12_SP_NUM_REG =================================================== */ + #define RTC_XADC12_SP_NUM_REG_ADC_SAMPLE_RANGE_SEL_Pos (3UL) /*!< ADC_SAMPLE_RANGE_SEL (Bit 3) */ + #define RTC_XADC12_SP_NUM_REG_ADC_SAMPLE_RANGE_SEL_Msk (0xf8UL) /*!< ADC_SAMPLE_RANGE_SEL (Bitfield-Mask: 0x1f) */ + #define RTC_XADC12_SP_NUM_REG_ADC_SMLP_NUM_AVR_Pos (0UL) /*!< ADC_SMLP_NUM_AVR (Bit 0) */ + #define RTC_XADC12_SP_NUM_REG_ADC_SMLP_NUM_AVR_Msk (0x7UL) /*!< ADC_SMLP_NUM_AVR (Bitfield-Mask: 0x07) */ +/* =================================================== XADC12_THR01_REG ==================================================== */ + #define RTC_XADC12_THR01_REG_XADC12_THR_CONFIG_CH1_Pos (28UL) /*!< XADC12_THR_CONFIG_CH1 (Bit 28) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_CONFIG_CH1_Msk (0x30000000UL) /*!< XADC12_THR_CONFIG_CH1 (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_LEVEL1_CH2_Pos (16UL) /*!< XADC12_THR_LEVEL1_CH2 (Bit 16) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_LEVEL1_CH2_Msk (0xfff0000UL) /*!< XADC12_THR_LEVEL1_CH2 (Bitfield-Mask: 0xfff) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_CONFIG_CH0_Pos (12UL) /*!< XADC12_THR_CONFIG_CH0 (Bit 12) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_CONFIG_CH0_Msk (0x3000UL) /*!< XADC12_THR_CONFIG_CH0 (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_LEVEL0_CH0_Pos (0UL) /*!< XADC12_THR_LEVEL0_CH0 (Bit 0) */ + #define RTC_XADC12_THR01_REG_XADC12_THR_LEVEL0_CH0_Msk (0xfffUL) /*!< XADC12_THR_LEVEL0_CH0 (Bitfield-Mask: 0xfff) */ +/* =================================================== XADC12_THR23_REG ==================================================== */ + #define RTC_XADC12_THR23_REG_XADC12_THR_CONFIG_CH3_Pos (28UL) /*!< XADC12_THR_CONFIG_CH3 (Bit 28) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_CONFIG_CH3_Msk (0x30000000UL) /*!< XADC12_THR_CONFIG_CH3 (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_LEVEL3_CH3_Pos (16UL) /*!< XADC12_THR_LEVEL3_CH3 (Bit 16) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_LEVEL3_CH3_Msk (0xfff0000UL) /*!< XADC12_THR_LEVEL3_CH3 (Bitfield-Mask: 0xfff) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_CONFIG_CH2_Pos (12UL) /*!< XADC12_THR_CONFIG_CH2 (Bit 12) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_CONFIG_CH2_Msk (0x3000UL) /*!< XADC12_THR_CONFIG_CH2 (Bitfield-Mask: 0x03) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_LEVEL2_CH2_Pos (0UL) /*!< XADC12_THR_LEVEL2_CH2 (Bit 0) */ + #define RTC_XADC12_THR23_REG_XADC12_THR_LEVEL2_CH2_Msk (0xfffUL) /*!< XADC12_THR_LEVEL2_CH2 (Bitfield-Mask: 0xfff) */ +/* ================================================= XADC12_TIMER_SET_REG ================================================== */ + #define RTC_XADC12_TIMER_SET_REG_ASWCH_CTRL_Pos (24UL) /*!< ASWCH_CTRL (Bit 24) */ + #define RTC_XADC12_TIMER_SET_REG_ASWCH_CTRL_Msk (0x1f000000UL) /*!< ASWCH_CTRL (Bitfield-Mask: 0x1f) */ + #define RTC_XADC12_TIMER_SET_REG_EXT_SEN_ACTIVATE_TMR_VAL_Pos (16UL) /*!< EXT_SEN_ACTIVATE_TMR_VAL (Bit 16) */ + #define RTC_XADC12_TIMER_SET_REG_EXT_SEN_ACTIVATE_TMR_VAL_Msk (0xf0000UL) /*!< EXT_SEN_ACTIVATE_TMR_VAL (Bitfield-Mask: 0x0f) */ + #define RTC_XADC12_TIMER_SET_REG_IP3_ACTIVATE_TMR_VAL_Pos (8UL) /*!< IP3_ACTIVATE_TMR_VAL (Bit 8) */ + #define RTC_XADC12_TIMER_SET_REG_IP3_ACTIVATE_TMR_VAL_Msk (0x3f00UL) /*!< IP3_ACTIVATE_TMR_VAL (Bitfield-Mask: 0x3f) */ + #define RTC_XADC12_TIMER_SET_REG_SENSOR_DETECT_ACT_Pos (7UL) /*!< SENSOR_DETECT_ACT (Bit 7) */ + #define RTC_XADC12_TIMER_SET_REG_SENSOR_DETECT_ACT_Msk (0x80UL) /*!< SENSOR_DETECT_ACT (Bitfield-Mask: 0x01) */ + #define RTC_XADC12_TIMER_SET_REG_X12_CLK_TMR_CNT_SRC_Pos (4UL) /*!< X12_CLK_TMR_CNT_SRC (Bit 4) */ + #define RTC_XADC12_TIMER_SET_REG_X12_CLK_TMR_CNT_SRC_Msk (0x70UL) /*!< X12_CLK_TMR_CNT_SRC (Bitfield-Mask: 0x07) */ + #define RTC_XADC12_TIMER_SET_REG_AX12B_TIMER_VAL_Pos (0UL) /*!< AX12B_TIMER_VAL (Bit 0) */ + #define RTC_XADC12_TIMER_SET_REG_AX12B_TIMER_VAL_Msk (0xfUL) /*!< AX12B_TIMER_VAL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDEMMC ================ */ +/* =========================================================================================================================== */ + +/* ============================================== SDEMMC_ADMAERRORSTATUS_REG =============================================== */ + #define SDEMMC_SDEMMC_ADMAERRORSTATUS_REG_LengthMismatchError_Pos (2UL) /*!< LengthMismatchError (Bit 2) */ + #define SDEMMC_SDEMMC_ADMAERRORSTATUS_REG_LengthMismatchError_Msk (0x4UL) /*!< LengthMismatchError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_ADMAERRORSTATUS_REG_ADMAErrorState_Pos (0UL) /*!< ADMAErrorState (Bit 0) */ + #define SDEMMC_SDEMMC_ADMAERRORSTATUS_REG_ADMAErrorState_Msk (0x3UL) /*!< ADMAErrorState (Bitfield-Mask: 0x03) */ +/* ============================================= SDEMMC_ADMA_SYS_ADDR_LOW_REG ============================================== */ + #define SDEMMC_SDEMMC_ADMA_SYS_ADDR_LOW_REG_ADMASystemAddress_Pos (0UL) /*!< ADMASystemAddress (Bit 0) */ + #define SDEMMC_SDEMMC_ADMA_SYS_ADDR_LOW_REG_ADMASystemAddress_Msk (0xffffffffUL) /*!< ADMASystemAddress (Bitfield-Mask: 0xffffffff) */ +/* ============================================ SDEMMC_ADMA_SYS_ADDR_UPPER_REG ============================================= */ + #define SDEMMC_SDEMMC_ADMA_SYS_ADDR_UPPER_REG_ADMASystemAddressUpperbits_Pos (0UL) /*!< ADMASystemAddressUpperbits (Bit 0) */ + #define SDEMMC_SDEMMC_ADMA_SYS_ADDR_UPPER_REG_ADMASystemAddressUpperbits_Msk (0xffffffffUL) /*!< ADMASystemAddressUpperbits (Bitfield-Mask: 0xffffffff) */ +/* ============================================= SDEMMC_AUTOCMDERRORSTATUS_REG ============================================= */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_PresetValueEnable_Pos (31UL) /*!< PresetValueEnable (Bit 31) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_PresetValueEnable_Msk (0x80000000UL) /*!< PresetValueEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AsynchronousInterruptEnable_Pos (30UL) /*!< AsynchronousInterruptEnable (Bit 30) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AsynchronousInterruptEnable_Msk (0x40000000UL) /*!< AsynchronousInterruptEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_SamplingClockSelect_Pos (23UL) /*!< SamplingClockSelect (Bit 23) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_SamplingClockSelect_Msk (0x800000UL) /*!< SamplingClockSelect (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_ExecuteTuning_Pos (22UL) /*!< ExecuteTuning (Bit 22) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_ExecuteTuning_Msk (0x400000UL) /*!< ExecuteTuning (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_DriveStrengthSelect_Pos (20UL) /*!< DriveStrengthSelect (Bit 20) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_DriveStrengthSelect_Msk (0x300000UL) /*!< DriveStrengthSelect (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_SignalingEnable1_8V_Pos (19UL) /*!< SignalingEnable1_8V (Bit 19) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_SignalingEnable1_8V_Msk (0x80000UL) /*!< SignalingEnable1_8V (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_UHSModeSelect_Pos (16UL) /*!< UHSModeSelect (Bit 16) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_UHSModeSelect_Msk (0x70000UL) /*!< UHSModeSelect (Bitfield-Mask: 0x07) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_CommandNotIssuedByAutoCMD12Error_Pos (7UL) /*!< CommandNotIssuedByAutoCMD12Error (Bit 7) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_CommandNotIssuedByAutoCMD12Error_Msk (0x80UL) /*!< CommandNotIssuedByAutoCMD12Error (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDIndexError_Pos (4UL) /*!< AutoCMDIndexError (Bit 4) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDIndexError_Msk (0x10UL) /*!< AutoCMDIndexError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDEndBitError_Pos (3UL) /*!< AutoCMDEndBitError (Bit 3) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDEndBitError_Msk (0x8UL) /*!< AutoCMDEndBitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDCRCError_Pos (2UL) /*!< AutoCMDCRCError (Bit 2) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDCRCError_Msk (0x4UL) /*!< AutoCMDCRCError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDTimeoutError_Pos (1UL) /*!< AutoCMDTimeoutError (Bit 1) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMDTimeoutError_Msk (0x2UL) /*!< AutoCMDTimeoutError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMD12NotExecuted_Pos (0UL) /*!< AutoCMD12NotExecuted (Bit 0) */ + #define SDEMMC_SDEMMC_AUTOCMDERRORSTATUS_REG_AutoCMD12NotExecuted_Msk (0x1UL) /*!< AutoCMD12NotExecuted (Bitfield-Mask: 0x01) */ +/* =================================================== SDEMMC_BLOCK_REG ==================================================== */ + #define SDEMMC_SDEMMC_BLOCK_REG_BlockCountForCurrentTransfer_Pos (16UL) /*!< BlockCountForCurrentTransfer (Bit 16) */ + #define SDEMMC_SDEMMC_BLOCK_REG_BlockCountForCurrentTransfer_Msk (0xffff0000UL) /*!< BlockCountForCurrentTransfer (Bitfield-Mask: 0xffff) */ + #define SDEMMC_SDEMMC_BLOCK_REG_HostSDMABufferBoundry_Pos (12UL) /*!< HostSDMABufferBoundry (Bit 12) */ + #define SDEMMC_SDEMMC_BLOCK_REG_HostSDMABufferBoundry_Msk (0x7000UL) /*!< HostSDMABufferBoundry (Bitfield-Mask: 0x07) */ + #define SDEMMC_SDEMMC_BLOCK_REG_TransferBlockSize_Pos (0UL) /*!< TransferBlockSize (Bit 0) */ + #define SDEMMC_SDEMMC_BLOCK_REG_TransferBlockSize_Msk (0xfffUL) /*!< TransferBlockSize (Bitfield-Mask: 0xfff) */ +/* ============================================= SDEMMC_BOOTTIMEOUT_CTRL__REG ============================================== */ + #define SDEMMC_SDEMMC_BOOTTIMEOUT_CTRL__REG_BootDataTimeoutCounterValue_Pos (0UL) /*!< BootDataTimeoutCounterValue (Bit 0) */ + #define SDEMMC_SDEMMC_BOOTTIMEOUT_CTRL__REG_BootDataTimeoutCounterValue_Msk (0xffffffffUL) /*!< BootDataTimeoutCounterValue (Bitfield-Mask: 0xffffffff) */ +/* =============================================== SDEMMC_BUFFERDATAPORT_REG =============================================== */ + #define SDEMMC_SDEMMC_BUFFERDATAPORT_REG_BufferData_Pos (0UL) /*!< BufferData (Bit 0) */ + #define SDEMMC_SDEMMC_BUFFERDATAPORT_REG_BufferData_Msk (0xffffffffUL) /*!< BufferData (Bitfield-Mask: 0xffffffff) */ +/* =============================================== SDEMMC_CAPABILITIES0_REG ================================================ */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SlotType_Pos (30UL) /*!< SlotType (Bit 30) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SlotType_Msk (0xc0000000UL) /*!< SlotType (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_AsynchronousInterruptSupport_Pos (29UL) /*!< AsynchronousInterruptSupport (Bit 29) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_AsynchronousInterruptSupport_Msk (0x20000000UL) /*!< AsynchronousInterruptSupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SystemBusSupport64bit_Pos (28UL) /*!< SystemBusSupport64bit (Bit 28) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SystemBusSupport64bit_Msk (0x10000000UL) /*!< SystemBusSupport64bit (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport18V_Pos (26UL) /*!< VoltageSupport18V (Bit 26) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport18V_Msk (0x4000000UL) /*!< VoltageSupport18V (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport30V_Pos (25UL) /*!< VoltageSupport30V (Bit 25) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport30V_Msk (0x2000000UL) /*!< VoltageSupport30V (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport33V_Pos (24UL) /*!< VoltageSupport33V (Bit 24) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_VoltageSupport33V_Msk (0x1000000UL) /*!< VoltageSupport33V (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SuspendResumeSupport_Pos (23UL) /*!< SuspendResumeSupport (Bit 23) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SuspendResumeSupport_Msk (0x800000UL) /*!< SuspendResumeSupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SDMASupport_Pos (22UL) /*!< SDMASupport (Bit 22) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SDMASupport_Msk (0x400000UL) /*!< SDMASupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_HighSpeedSupport_Pos (21UL) /*!< HighSpeedSupport (Bit 21) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_HighSpeedSupport_Msk (0x200000UL) /*!< HighSpeedSupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_ADMA2Support_Pos (19UL) /*!< ADMA2Support (Bit 19) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_ADMA2Support_Msk (0x80000UL) /*!< ADMA2Support (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SupportforEmbeddedDevice8bit_Pos (18UL) /*!< SupportforEmbeddedDevice8bit (Bit 18) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_SupportforEmbeddedDevice8bit_Msk (0x40000UL) /*!< SupportforEmbeddedDevice8bit (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_MaxBlockLength_Pos (16UL) /*!< MaxBlockLength (Bit 16) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_MaxBlockLength_Msk (0x30000UL) /*!< MaxBlockLength (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_BaseClockFrequencyForSDClock_Pos (8UL) /*!< BaseClockFrequencyForSDClock (Bit 8) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_BaseClockFrequencyForSDClock_Msk (0xff00UL) /*!< BaseClockFrequencyForSDClock (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_TimeoutClockUnit_Pos (7UL) /*!< TimeoutClockUnit (Bit 7) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_TimeoutClockUnit_Msk (0x80UL) /*!< TimeoutClockUnit (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_TimeoutClockFrequency_Pos (0UL) /*!< TimeoutClockFrequency (Bit 0) */ + #define SDEMMC_SDEMMC_CAPABILITIES0_REG_TimeoutClockFrequency_Msk (0x3fUL) /*!< TimeoutClockFrequency (Bitfield-Mask: 0x3f) */ +/* =============================================== SDEMMC_CAPABILITIES1_REG ================================================ */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_ClockMultiplier_Pos (16UL) /*!< ClockMultiplier (Bit 16) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_ClockMultiplier_Msk (0xff0000UL) /*!< ClockMultiplier (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_ReTuningModes_Pos (14UL) /*!< ReTuningModes (Bit 14) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_ReTuningModes_Msk (0xc000UL) /*!< ReTuningModes (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_UseTuningforSDR50_Pos (13UL) /*!< UseTuningforSDR50 (Bit 13) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_UseTuningforSDR50_Msk (0x2000UL) /*!< UseTuningforSDR50 (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_TimerCountforReTuning_Pos (8UL) /*!< TimerCountforReTuning (Bit 8) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_TimerCountforReTuning_Msk (0xf00UL) /*!< TimerCountforReTuning (Bitfield-Mask: 0x0f) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeDSupport_Pos (6UL) /*!< DriverTypeDSupport (Bit 6) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeDSupport_Msk (0x40UL) /*!< DriverTypeDSupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeCSupport_Pos (5UL) /*!< DriverTypeCSupport (Bit 5) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeCSupport_Msk (0x20UL) /*!< DriverTypeCSupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeASupport_Pos (4UL) /*!< DriverTypeASupport (Bit 4) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DriverTypeASupport_Msk (0x10UL) /*!< DriverTypeASupport (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DDR50Support_Pos (2UL) /*!< DDR50Support (Bit 2) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_DDR50Support_Msk (0x4UL) /*!< DDR50Support (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_SDR104Support_Pos (1UL) /*!< SDR104Support (Bit 1) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_SDR104Support_Msk (0x2UL) /*!< SDR104Support (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_SDR50Support_Pos (0UL) /*!< SDR50Support (Bit 0) */ + #define SDEMMC_SDEMMC_CAPABILITIES1_REG_SDR50Support_Msk (0x1UL) /*!< SDR50Support (Bitfield-Mask: 0x01) */ +/* =============================================== SDEMMC_DEBUGSELECTION_REG =============================================== */ + #define SDEMMC_SDEMMC_DEBUGSELECTION_REG_DebugSel_Pos (0UL) /*!< DebugSel (Bit 0) */ + #define SDEMMC_SDEMMC_DEBUGSELECTION_REG_DebugSel_Msk (0x1UL) /*!< DebugSel (Bitfield-Mask: 0x01) */ +/* ============================================ SDEMMC_FORCE_EVENET_ERRSTAT_REG ============================================ */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForVendorSpecificError_Pos (26UL) /*!< ForceEventForVendorSpecificError (Bit 26) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForVendorSpecificError_Msk (0xfc000000UL) /*!< ForceEventForVendorSpecificError (Bitfield-Mask: 0x3f) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForADMAError_Pos (25UL) /*!< ForceEventForADMAError (Bit 25) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForADMAError_Msk (0x2000000UL) /*!< ForceEventForADMAError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDError_Pos (24UL) /*!< ForceEventForAutoCMDError (Bit 24) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDError_Msk (0x1000000UL) /*!< ForceEventForAutoCMDError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCurrentLimitError_Pos (23UL) /*!< ForceEventForCurrentLimitError (Bit 23) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCurrentLimitError_Msk (0x800000UL) /*!< ForceEventForCurrentLimitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataEndBitError_Pos (22UL) /*!< ForceEventForDataEndBitError (Bit 22) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataEndBitError_Msk (0x400000UL) /*!< ForceEventForDataEndBitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataCRCError_Pos (21UL) /*!< ForceEventForDataCRCError (Bit 21) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataCRCError_Msk (0x200000UL) /*!< ForceEventForDataCRCError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataTimeoutError_Pos (20UL) /*!< ForceEventForDataTimeoutError (Bit 20) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForDataTimeoutError_Msk (0x100000UL) /*!< ForceEventForDataTimeoutError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandIndexError_Pos (19UL) /*!< ForceEventForCommandIndexError (Bit 19) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandIndexError_Msk (0x80000UL) /*!< ForceEventForCommandIndexError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandEndBitError_Pos (18UL) /*!< ForceEventForCommandEndBitError (Bit 18) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandEndBitError_Msk (0x40000UL) /*!< ForceEventForCommandEndBitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandCRCError_Pos (17UL) /*!< ForceEventForCommandCRCError (Bit 17) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandCRCError_Msk (0x20000UL) /*!< ForceEventForCommandCRCError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandTimeoutError_Pos (16UL) /*!< ForceEventForCommandTimeoutError (Bit 16) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandTimeoutError_Msk (0x10000UL) /*!< ForceEventForCommandTimeoutError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandNotIssuedByAutoCMD12Error_Pos (7UL) /*!< ForceEventForCommandNotIssuedByAutoCMD12Error (Bit 7) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForCommandNotIssuedByAutoCMD12Error_Msk (0x80UL) /*!< ForceEventForCommandNotIssuedByAutoCMD12Error (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDIndex_Pos (4UL) /*!< ForceEventForAutoCMDIndex (Bit 4) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDIndex_Msk (0x10UL) /*!< ForceEventForAutoCMDIndex (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDEndBit_Pos (3UL) /*!< ForceEventForAutoCMDEndBit (Bit 3) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDEndBit_Msk (0x8UL) /*!< ForceEventForAutoCMDEndBit (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDCRC_Pos (2UL) /*!< ForceEventForAutoCMDCRC (Bit 2) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDCRC_Msk (0x4UL) /*!< ForceEventForAutoCMDCRC (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDTimeout_Pos (1UL) /*!< ForceEventForAutoCMDTimeout (Bit 1) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMDTimeout_Msk (0x2UL) /*!< ForceEventForAutoCMDTimeout (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMD12NotExec_Pos (0UL) /*!< ForceEventForAutoCMD12NotExec (Bit 0) */ + #define SDEMMC_SDEMMC_FORCE_EVENET_ERRSTAT_REG_ForceEventForAutoCMD12NotExec_Msk (0x1UL) /*!< ForceEventForAutoCMD12NotExec (Bitfield-Mask: 0x01) */ +/* ============================================= SDEMMC_GLB_ITNR_SIGNAL_EN_REG ============================================= */ + #define SDEMMC_SDEMMC_GLB_ITNR_SIGNAL_EN_REG_IntSrcSD_Pos (2UL) /*!< IntSrcSD (Bit 2) */ + #define SDEMMC_SDEMMC_GLB_ITNR_SIGNAL_EN_REG_IntSrcSD_Msk (0x4UL) /*!< IntSrcSD (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_GLB_ITNR_SIGNAL_EN_REG_IntSrcXD_Pos (1UL) /*!< IntSrcXD (Bit 1) */ + #define SDEMMC_SDEMMC_GLB_ITNR_SIGNAL_EN_REG_IntSrcXD_Msk (0x2UL) /*!< IntSrcXD (Bitfield-Mask: 0x01) */ +/* ============================================= SDEMMC_GLB_ITNR_STATUS_EN_REG ============================================= */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_EN_REG_IntSrcSD_Pos (2UL) /*!< IntSrcSD (Bit 2) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_EN_REG_IntSrcSD_Msk (0x4UL) /*!< IntSrcSD (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_EN_REG_IntSrcXD_Pos (1UL) /*!< IntSrcXD (Bit 1) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_EN_REG_IntSrcXD_Msk (0x2UL) /*!< IntSrcXD (Bitfield-Mask: 0x01) */ +/* ============================================== SDEMMC_GLB_ITNR_STATUS_REG =============================================== */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_REG_IntSrcSD_Pos (2UL) /*!< IntSrcSD (Bit 2) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_REG_IntSrcSD_Msk (0x4UL) /*!< IntSrcSD (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_REG_IntSrcXD_Pos (1UL) /*!< IntSrcXD (Bit 1) */ + #define SDEMMC_SDEMMC_GLB_ITNR_STATUS_REG_IntSrcXD_Msk (0x2UL) /*!< IntSrcXD (Bitfield-Mask: 0x01) */ +/* ================================================ SDEMMC_HOST_CTRL_1_REG ================================================= */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnSDCardRemoval_Pos (26UL) /*!< WakeupEventEnableOnSDCardRemoval (Bit 26) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnSDCardRemoval_Msk (0x4000000UL) /*!< WakeupEventEnableOnSDCardRemoval (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnSDCardInsertion_Pos (25UL) /*!< WakeupEventEnableOnSDCardInsertion (Bit 25) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnSDCardInsertion_Msk (0x2000000UL) /*!< WakeupEventEnableOnSDCardInsertion (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnCardInterrupt_Pos (24UL) /*!< WakeupEventEnableOnCardInterrupt (Bit 24) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_WakeupEventEnableOnCardInterrupt_Msk (0x1000000UL) /*!< WakeupEventEnableOnCardInterrupt (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_BootAckChk_Pos (23UL) /*!< BootAckChk (Bit 23) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_BootAckChk_Msk (0x800000UL) /*!< BootAckChk (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_AltBootEn_Pos (22UL) /*!< AltBootEn (Bit 22) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_AltBootEn_Msk (0x400000UL) /*!< AltBootEn (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_BootEn_Pos (21UL) /*!< BootEn (Bit 21) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_BootEn_Msk (0x200000UL) /*!< BootEn (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SpiMode_Pos (20UL) /*!< SpiMode (Bit 20) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SpiMode_Msk (0x100000UL) /*!< SpiMode (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_InterruptAtBlockGap_Pos (19UL) /*!< InterruptAtBlockGap (Bit 19) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_InterruptAtBlockGap_Msk (0x80000UL) /*!< InterruptAtBlockGap (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ReadWaitControl_Pos (18UL) /*!< ReadWaitControl (Bit 18) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ReadWaitControl_Msk (0x40000UL) /*!< ReadWaitControl (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ContinueRequest_Pos (17UL) /*!< ContinueRequest (Bit 17) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ContinueRequest_Msk (0x20000UL) /*!< ContinueRequest (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_StopAtBlockGapRequest_Pos (16UL) /*!< StopAtBlockGapRequest (Bit 16) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_StopAtBlockGapRequest_Msk (0x10000UL) /*!< StopAtBlockGapRequest (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_HardwareRst_Pos (12UL) /*!< HardwareRst (Bit 12) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_HardwareRst_Msk (0x1000UL) /*!< HardwareRst (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SDBusVoltageSelect_Pos (9UL) /*!< SDBusVoltageSelect (Bit 9) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SDBusVoltageSelect_Msk (0xe00UL) /*!< SDBusVoltageSelect (Bitfield-Mask: 0x07) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SDBusPower_Pos (8UL) /*!< SDBusPower (Bit 8) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_SDBusPower_Msk (0x100UL) /*!< SDBusPower (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_CardDetectSignalSelection_Pos (7UL) /*!< CardDetectSignalSelection (Bit 7) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_CardDetectSignalSelection_Msk (0x80UL) /*!< CardDetectSignalSelection (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_CardDetectTestLevel_Pos (6UL) /*!< CardDetectTestLevel (Bit 6) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_CardDetectTestLevel_Msk (0x40UL) /*!< CardDetectTestLevel (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ExtendedDataTransferWidth_Pos (5UL) /*!< ExtendedDataTransferWidth (Bit 5) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_ExtendedDataTransferWidth_Msk (0x20UL) /*!< ExtendedDataTransferWidth (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_DMASelect_Pos (3UL) /*!< DMASelect (Bit 3) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_DMASelect_Msk (0x18UL) /*!< DMASelect (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_HighSpeedEnable_Pos (2UL) /*!< HighSpeedEnable (Bit 2) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_HighSpeedEnable_Msk (0x4UL) /*!< HighSpeedEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_DataTransferWidth_Pos (1UL) /*!< DataTransferWidth (Bit 1) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_DataTransferWidth_Msk (0x2UL) /*!< DataTransferWidth (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_LEDControl_Pos (0UL) /*!< LEDControl (Bit 0) */ + #define SDEMMC_SDEMMC_HOST_CTRL_1_REG_LEDControl_Msk (0x1UL) /*!< LEDControl (Bitfield-Mask: 0x01) */ +/* ============================================ SDEMMC_MAX_CUR_CAPABILITIES_REG ============================================ */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor1_8V_Pos (16UL) /*!< MaximumCurrentFor1_8V (Bit 16) */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor1_8V_Msk (0xff0000UL) /*!< MaximumCurrentFor1_8V (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor3_0V_Pos (8UL) /*!< MaximumCurrentFor3_0V (Bit 8) */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor3_0V_Msk (0xff00UL) /*!< MaximumCurrentFor3_0V (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor3_3V_Pos (0UL) /*!< MaximumCurrentFor3_3V (Bit 0) */ + #define SDEMMC_SDEMMC_MAX_CUR_CAPABILITIES_REG_MaximumCurrentFor3_3V_Msk (0xffUL) /*!< MaximumCurrentFor3_3V (Bitfield-Mask: 0xff) */ +/* =========================================== SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG ============================================ */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_VendorSpecificErrorSignalEnb_Pos (27UL) /*!< VendorSpecificErrorSignalEnb (Bit 27) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_VendorSpecificErrorSignalEnb_Msk (0xf8000000UL) /*!< VendorSpecificErrorSignalEnb (Bitfield-Mask: 0x1f) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_TuningErrorSignalEnb_Pos (26UL) /*!< TuningErrorSignalEnb (Bit 26) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_TuningErrorSignalEnb_Msk (0x4000000UL) /*!< TuningErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_ADMAErrorSignalEnb_Pos (25UL) /*!< ADMAErrorSignalEnb (Bit 25) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_ADMAErrorSignalEnb_Msk (0x2000000UL) /*!< ADMAErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_AutoCMDErrorSignalEnb_Pos (24UL) /*!< AutoCMDErrorSignalEnb (Bit 24) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_AutoCMDErrorSignalEnb_Msk (0x1000000UL) /*!< AutoCMDErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CurrentLimitErrorSignalEnb_Pos (23UL) /*!< CurrentLimitErrorSignalEnb (Bit 23) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CurrentLimitErrorSignalEnb_Msk (0x800000UL) /*!< CurrentLimitErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataEndBitErrorSignalEnb_Pos (22UL) /*!< DataEndBitErrorSignalEnb (Bit 22) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataEndBitErrorSignalEnb_Msk (0x400000UL) /*!< DataEndBitErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataCRCErrorSignalEnb_Pos (21UL) /*!< DataCRCErrorSignalEnb (Bit 21) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataCRCErrorSignalEnb_Msk (0x200000UL) /*!< DataCRCErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataTimeoutErrorSignalEnb_Pos (20UL) /*!< DataTimeoutErrorSignalEnb (Bit 20) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DataTimeoutErrorSignalEnb_Msk (0x100000UL) /*!< DataTimeoutErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandIndexErrorSignalEnb_Pos (19UL) /*!< CommandIndexErrorSignalEnb (Bit 19) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandIndexErrorSignalEnb_Msk (0x80000UL) /*!< CommandIndexErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandEndBitErrorSignalEnb_Pos (18UL) /*!< CommandEndBitErrorSignalEnb (Bit 18) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandEndBitErrorSignalEnb_Msk (0x40000UL) /*!< CommandEndBitErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandCRCErrorSignalEnb_Pos (17UL) /*!< CommandCRCErrorSignalEnb (Bit 17) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandCRCErrorSignalEnb_Msk (0x20000UL) /*!< CommandCRCErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandTimeoutErrorSignalEnb_Pos (16UL) /*!< CommandTimeoutErrorSignalEnb (Bit 16) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandTimeoutErrorSignalEnb_Msk (0x10000UL) /*!< CommandTimeoutErrorSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_FixedTo0_Pos (15UL) /*!< FixedTo0 (Bit 15) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_FixedTo0_Msk (0x8000UL) /*!< FixedTo0 (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BootTerminateInterruptSignalEnable_Pos (14UL) /*!< BootTerminateInterruptSignalEnable (Bit 14) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BootTerminateInterruptSignalEnable_Msk (0x4000UL) /*!< BootTerminateInterruptSignalEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BootAckRcvSignalEnable_Pos (13UL) /*!< BootAckRcvSignalEnable (Bit 13) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BootAckRcvSignalEnable_Msk (0x2000UL) /*!< BootAckRcvSignalEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_ReTuningEventSignalEnable_Pos (12UL) /*!< ReTuningEventSignalEnable (Bit 12) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_ReTuningEventSignalEnable_Msk (0x1000UL) /*!< ReTuningEventSignalEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_CSignalEnb_Pos (11UL) /*!< INT_CSignalEnb (Bit 11) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_CSignalEnb_Msk (0x800UL) /*!< INT_CSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_BSignalEnb_Pos (10UL) /*!< INT_BSignalEnb (Bit 10) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_BSignalEnb_Msk (0x400UL) /*!< INT_BSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_ASignalEnb_Pos (9UL) /*!< INT_ASignalEnb (Bit 9) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_INT_ASignalEnb_Msk (0x200UL) /*!< INT_ASignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardInterruptSignalEnb_Pos (8UL) /*!< CardInterruptSignalEnb (Bit 8) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardInterruptSignalEnb_Msk (0x100UL) /*!< CardInterruptSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardRemovalSignalEnb_Pos (7UL) /*!< CardRemovalSignalEnb (Bit 7) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardRemovalSignalEnb_Msk (0x80UL) /*!< CardRemovalSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardInsertionSignalEnb_Pos (6UL) /*!< CardInsertionSignalEnb (Bit 6) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CardInsertionSignalEnb_Msk (0x40UL) /*!< CardInsertionSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BufferReadReadySignalEnb_Pos (5UL) /*!< BufferReadReadySignalEnb (Bit 5) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BufferReadReadySignalEnb_Msk (0x20UL) /*!< BufferReadReadySignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BufferWriteReadySignalEnb_Pos (4UL) /*!< BufferWriteReadySignalEnb (Bit 4) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BufferWriteReadySignalEnb_Msk (0x10UL) /*!< BufferWriteReadySignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DMAInterruptSignalEnb_Pos (3UL) /*!< DMAInterruptSignalEnb (Bit 3) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_DMAInterruptSignalEnb_Msk (0x8UL) /*!< DMAInterruptSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BlockGapEventSignalEnb_Pos (2UL) /*!< BlockGapEventSignalEnb (Bit 2) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_BlockGapEventSignalEnb_Msk (0x4UL) /*!< BlockGapEventSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_TransferCompleteSignalEnb_Pos (1UL) /*!< TransferCompleteSignalEnb (Bit 1) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_TransferCompleteSignalEnb_Msk (0x2UL) /*!< TransferCompleteSignalEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandCompleteSignalEnb_Pos (0UL) /*!< CommandCompleteSignalEnb (Bit 0) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG_CommandCompleteSignalEnb_Msk (0x1UL) /*!< CommandCompleteSignalEnb (Bitfield-Mask: 0x01) */ +/* =========================================== SDEMMC_NORMAL_ITNR_STATUS_EN_REG ============================================ */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_VendorSpecificErrorStatusEnb_Pos (27UL) /*!< VendorSpecificErrorStatusEnb (Bit 27) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_VendorSpecificErrorStatusEnb_Msk (0xf8000000UL) /*!< VendorSpecificErrorStatusEnb (Bitfield-Mask: 0x1f) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_TuningErrorStatusEnb_Pos (26UL) /*!< TuningErrorStatusEnb (Bit 26) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_TuningErrorStatusEnb_Msk (0x4000000UL) /*!< TuningErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_ADMAErrorStatusEnb_Pos (25UL) /*!< ADMAErrorStatusEnb (Bit 25) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_ADMAErrorStatusEnb_Msk (0x2000000UL) /*!< ADMAErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_AutoCMDErrorStatusEnb_Pos (24UL) /*!< AutoCMDErrorStatusEnb (Bit 24) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_AutoCMDErrorStatusEnb_Msk (0x1000000UL) /*!< AutoCMDErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CurrentLimitErrorStatusEnb_Pos (23UL) /*!< CurrentLimitErrorStatusEnb (Bit 23) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CurrentLimitErrorStatusEnb_Msk (0x800000UL) /*!< CurrentLimitErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataEndBitErrorStatusEnb_Pos (22UL) /*!< DataEndBitErrorStatusEnb (Bit 22) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataEndBitErrorStatusEnb_Msk (0x400000UL) /*!< DataEndBitErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataCRCErrorStatusEnb_Pos (21UL) /*!< DataCRCErrorStatusEnb (Bit 21) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataCRCErrorStatusEnb_Msk (0x200000UL) /*!< DataCRCErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataTimeoutErrorStatusEnb_Pos (20UL) /*!< DataTimeoutErrorStatusEnb (Bit 20) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DataTimeoutErrorStatusEnb_Msk (0x100000UL) /*!< DataTimeoutErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandIndexErrorStatusEnb_Pos (19UL) /*!< CommandIndexErrorStatusEnb (Bit 19) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandIndexErrorStatusEnb_Msk (0x80000UL) /*!< CommandIndexErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandEndBitErrorStatusEnb_Pos (18UL) /*!< CommandEndBitErrorStatusEnb (Bit 18) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandEndBitErrorStatusEnb_Msk (0x40000UL) /*!< CommandEndBitErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandCRCErrorStatusEnb_Pos (17UL) /*!< CommandCRCErrorStatusEnb (Bit 17) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandCRCErrorStatusEnb_Msk (0x20000UL) /*!< CommandCRCErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandTimeoutErrorStatusEnb_Pos (16UL) /*!< CommandTimeoutErrorStatusEnb (Bit 16) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandTimeoutErrorStatusEnb_Msk (0x10000UL) /*!< CommandTimeoutErrorStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_FixedTo0_Pos (15UL) /*!< FixedTo0 (Bit 15) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_FixedTo0_Msk (0x8000UL) /*!< FixedTo0 (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BootTerminateInterruptStatusEnb_Pos (14UL) /*!< BootTerminateInterruptStatusEnb (Bit 14) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BootTerminateInterruptStatusEnb_Msk (0x4000UL) /*!< BootTerminateInterruptStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BootAckRcvStatusEnb_Pos (13UL) /*!< BootAckRcvStatusEnb (Bit 13) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BootAckRcvStatusEnb_Msk (0x2000UL) /*!< BootAckRcvStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_ReTuningEventStatusEnable_Pos (12UL) /*!< ReTuningEventStatusEnable (Bit 12) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_ReTuningEventStatusEnable_Msk (0x1000UL) /*!< ReTuningEventStatusEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_CStatusEnb_Pos (11UL) /*!< INT_CStatusEnb (Bit 11) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_CStatusEnb_Msk (0x800UL) /*!< INT_CStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_BStatusEnb_Pos (10UL) /*!< INT_BStatusEnb (Bit 10) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_BStatusEnb_Msk (0x400UL) /*!< INT_BStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_AStatusEnb_Pos (9UL) /*!< INT_AStatusEnb (Bit 9) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_INT_AStatusEnb_Msk (0x200UL) /*!< INT_AStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardInterruptStatusEnb_Pos (8UL) /*!< CardInterruptStatusEnb (Bit 8) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardInterruptStatusEnb_Msk (0x100UL) /*!< CardInterruptStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardRemovalStatusEnb_Pos (7UL) /*!< CardRemovalStatusEnb (Bit 7) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardRemovalStatusEnb_Msk (0x80UL) /*!< CardRemovalStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardInsertionStatusEnb_Pos (6UL) /*!< CardInsertionStatusEnb (Bit 6) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CardInsertionStatusEnb_Msk (0x40UL) /*!< CardInsertionStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BufferReadReadyStatusEnb_Pos (5UL) /*!< BufferReadReadyStatusEnb (Bit 5) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BufferReadReadyStatusEnb_Msk (0x20UL) /*!< BufferReadReadyStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BufferWriteReadyStatusEnb_Pos (4UL) /*!< BufferWriteReadyStatusEnb (Bit 4) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BufferWriteReadyStatusEnb_Msk (0x10UL) /*!< BufferWriteReadyStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DMAInterruptStatusEnb_Pos (3UL) /*!< DMAInterruptStatusEnb (Bit 3) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_DMAInterruptStatusEnb_Msk (0x8UL) /*!< DMAInterruptStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BlockGapEventStatusEnb_Pos (2UL) /*!< BlockGapEventStatusEnb (Bit 2) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_BlockGapEventStatusEnb_Msk (0x4UL) /*!< BlockGapEventStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_TransferCompleteStatusEnb_Pos (1UL) /*!< TransferCompleteStatusEnb (Bit 1) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_TransferCompleteStatusEnb_Msk (0x2UL) /*!< TransferCompleteStatusEnb (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandCompleteStatusEnb_Pos (0UL) /*!< CommandCompleteStatusEnb (Bit 0) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_EN_REG_CommandCompleteStatusEnb_Msk (0x1UL) /*!< CommandCompleteStatusEnb (Bitfield-Mask: 0x01) */ +/* ============================================= SDEMMC_NORMAL_ITNR_STATUS_REG ============================================= */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_VendorSpecificError_Pos (27UL) /*!< VendorSpecificError (Bit 27) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_VendorSpecificError_Msk (0xf8000000UL) /*!< VendorSpecificError (Bitfield-Mask: 0x1f) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_TuningError_Pos (26UL) /*!< TuningError (Bit 26) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_TuningError_Msk (0x4000000UL) /*!< TuningError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ADMAError_Pos (25UL) /*!< ADMAError (Bit 25) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ADMAError_Msk (0x2000000UL) /*!< ADMAError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_AutoCMDError_Pos (24UL) /*!< AutoCMDError (Bit 24) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_AutoCMDError_Msk (0x1000000UL) /*!< AutoCMDError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CurrentLimitError_Pos (23UL) /*!< CurrentLimitError (Bit 23) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CurrentLimitError_Msk (0x800000UL) /*!< CurrentLimitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataEndBitError_Pos (22UL) /*!< DataEndBitError (Bit 22) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataEndBitError_Msk (0x400000UL) /*!< DataEndBitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataCRCError_Pos (21UL) /*!< DataCRCError (Bit 21) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataCRCError_Msk (0x200000UL) /*!< DataCRCError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataTimeoutError_Pos (20UL) /*!< DataTimeoutError (Bit 20) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DataTimeoutError_Msk (0x100000UL) /*!< DataTimeoutError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandIndexError_Pos (19UL) /*!< CommandIndexError (Bit 19) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandIndexError_Msk (0x80000UL) /*!< CommandIndexError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandEndBitError_Pos (18UL) /*!< CommandEndBitError (Bit 18) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandEndBitError_Msk (0x40000UL) /*!< CommandEndBitError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandCRCError_Pos (17UL) /*!< CommandCRCError (Bit 17) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandCRCError_Msk (0x20000UL) /*!< CommandCRCError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandTimeoutError_Pos (16UL) /*!< CommandTimeoutError (Bit 16) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandTimeoutError_Msk (0x10000UL) /*!< CommandTimeoutError (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ErrorInterrupt_Pos (15UL) /*!< ErrorInterrupt (Bit 15) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ErrorInterrupt_Msk (0x8000UL) /*!< ErrorInterrupt (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BootTerminateInterrupt_Pos (14UL) /*!< BootTerminateInterrupt (Bit 14) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BootTerminateInterrupt_Msk (0x4000UL) /*!< BootTerminateInterrupt (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BootAckRcv_Pos (13UL) /*!< BootAckRcv (Bit 13) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BootAckRcv_Msk (0x2000UL) /*!< BootAckRcv (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ReTuningEvent_Pos (12UL) /*!< ReTuningEvent (Bit 12) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_ReTuningEvent_Msk (0x1000UL) /*!< ReTuningEvent (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_C_Pos (11UL) /*!< INT_C (Bit 11) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_C_Msk (0x800UL) /*!< INT_C (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_B_Pos (10UL) /*!< INT_B (Bit 10) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_B_Msk (0x400UL) /*!< INT_B (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_A_Pos (9UL) /*!< INT_A (Bit 9) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_INT_A_Msk (0x200UL) /*!< INT_A (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardInterrupt_Pos (8UL) /*!< CardInterrupt (Bit 8) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardInterrupt_Msk (0x100UL) /*!< CardInterrupt (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardRemoval_Pos (7UL) /*!< CardRemoval (Bit 7) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardRemoval_Msk (0x80UL) /*!< CardRemoval (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardInsertion_Pos (6UL) /*!< CardInsertion (Bit 6) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CardInsertion_Msk (0x40UL) /*!< CardInsertion (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BufferReadReady_Pos (5UL) /*!< BufferReadReady (Bit 5) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BufferReadReady_Msk (0x20UL) /*!< BufferReadReady (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BufferWriteReady_Pos (4UL) /*!< BufferWriteReady (Bit 4) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BufferWriteReady_Msk (0x10UL) /*!< BufferWriteReady (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DMAInterrupt_Pos (3UL) /*!< DMAInterrupt (Bit 3) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_DMAInterrupt_Msk (0x8UL) /*!< DMAInterrupt (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BlockGapEvent_Pos (2UL) /*!< BlockGapEvent (Bit 2) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_BlockGapEvent_Msk (0x4UL) /*!< BlockGapEvent (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_TransferComplete_Pos (1UL) /*!< TransferComplete (Bit 1) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_TransferComplete_Msk (0x2UL) /*!< TransferComplete (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandComplete_Pos (0UL) /*!< CommandComplete (Bit 0) */ + #define SDEMMC_SDEMMC_NORMAL_ITNR_STATUS_REG_CommandComplete_Msk (0x1UL) /*!< CommandComplete (Bitfield-Mask: 0x01) */ +/* ================================================ SDEMMC_PRESENTSTATE_REG ================================================ */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CMDLineSignalLevel_Pos (24UL) /*!< CMDLineSignalLevel (Bit 24) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CMDLineSignalLevel_Msk (0x1000000UL) /*!< CMDLineSignalLevel (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_DAT3TO0LineSignalLevel_Pos (20UL) /*!< DAT3TO0LineSignalLevel (Bit 20) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_DAT3TO0LineSignalLevel_Msk (0xf00000UL) /*!< DAT3TO0LineSignalLevel (Bitfield-Mask: 0x0f) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_WriteProtectSwitchPinLevel_Pos (19UL) /*!< WriteProtectSwitchPinLevel (Bit 19) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_WriteProtectSwitchPinLevel_Msk (0x80000UL) /*!< WriteProtectSwitchPinLevel (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardDetectPinLevel_Pos (18UL) /*!< CardDetectPinLevel (Bit 18) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardDetectPinLevel_Msk (0x40000UL) /*!< CardDetectPinLevel (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardStateStable_Pos (17UL) /*!< CardStateStable (Bit 17) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardStateStable_Msk (0x20000UL) /*!< CardStateStable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardInserted_Pos (16UL) /*!< CardInserted (Bit 16) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CardInserted_Msk (0x10000UL) /*!< CardInserted (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_BufferReadEnable_Pos (11UL) /*!< BufferReadEnable (Bit 11) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_BufferReadEnable_Msk (0x800UL) /*!< BufferReadEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_BufferWriteEnable_Pos (10UL) /*!< BufferWriteEnable (Bit 10) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_BufferWriteEnable_Msk (0x400UL) /*!< BufferWriteEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_ReadTransferActive_Pos (9UL) /*!< ReadTransferActive (Bit 9) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_ReadTransferActive_Msk (0x200UL) /*!< ReadTransferActive (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_WriteTransferActive_Pos (8UL) /*!< WriteTransferActive (Bit 8) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_WriteTransferActive_Msk (0x100UL) /*!< WriteTransferActive (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_ReTuningRequest_Pos (3UL) /*!< ReTuningRequest (Bit 3) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_ReTuningRequest_Msk (0x8UL) /*!< ReTuningRequest (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_DATLineActive_Pos (2UL) /*!< DATLineActive (Bit 2) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_DATLineActive_Msk (0x4UL) /*!< DATLineActive (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CommandInhibitDAT_Pos (1UL) /*!< CommandInhibitDAT (Bit 1) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CommandInhibitDAT_Msk (0x2UL) /*!< CommandInhibitDAT (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CommandInhibitCMD_Pos (0UL) /*!< CommandInhibitCMD (Bit 0) */ + #define SDEMMC_SDEMMC_PRESENTSTATE_REG_CommandInhibitCMD_Msk (0x1UL) /*!< CommandInhibitCMD (Bitfield-Mask: 0x01) */ +/* ================================================ SDEMMC_PRESETVALUE0_REG ================================================ */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdDriveStrengthSelectValue_Pos (30UL) /*!< DefSpdDriveStrengthSelectValue (Bit 30) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdDriveStrengthSelectValue_Msk (0xc0000000UL) /*!< DefSpdDriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdClockGeneratorSelectValue_Pos (26UL) /*!< DefSpdClockGeneratorSelectValue (Bit 26) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdClockGeneratorSelectValue_Msk (0x4000000UL) /*!< DefSpdClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdSDCLKFrequenceSelectValue_Pos (16UL) /*!< DefSpdSDCLKFrequenceSelectValue (Bit 16) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_DefSpdSDCLKFrequenceSelectValue_Msk (0x3ff0000UL) /*!< DefSpdSDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitDriveStrengthSelectValue_Pos (14UL) /*!< InitDriveStrengthSelectValue (Bit 14) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitDriveStrengthSelectValue_Msk (0xc000UL) /*!< InitDriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitClockGeneratorSelectValue_Pos (10UL) /*!< InitClockGeneratorSelectValue (Bit 10) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitClockGeneratorSelectValue_Msk (0x400UL) /*!< InitClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitSDCLKFrequenceSelectValue_Pos (0UL) /*!< InitSDCLKFrequenceSelectValue (Bit 0) */ + #define SDEMMC_SDEMMC_PRESETVALUE0_REG_InitSDCLKFrequenceSelectValue_Msk (0x3ffUL) /*!< InitSDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ +/* ================================================ SDEMMC_PRESETVALUE1_REG ================================================ */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12DriveStrengthSelectValue_Pos (30UL) /*!< SDR12DriveStrengthSelectValue (Bit 30) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12DriveStrengthSelectValue_Msk (0xc0000000UL) /*!< SDR12DriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12ClockGeneratorSelectValue_Pos (26UL) /*!< SDR12ClockGeneratorSelectValue (Bit 26) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12ClockGeneratorSelectValue_Msk (0x4000000UL) /*!< SDR12ClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12SDCLKFrequenceSelectValue_Pos (16UL) /*!< SDR12SDCLKFrequenceSelectValue (Bit 16) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_SDR12SDCLKFrequenceSelectValue_Msk (0x3ff0000UL) /*!< SDR12SDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdDriveStrengthSelectValue_Pos (14UL) /*!< HighSpdDriveStrengthSelectValue (Bit 14) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdDriveStrengthSelectValue_Msk (0xc000UL) /*!< HighSpdDriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdClockGeneratorSelectValue_Pos (10UL) /*!< HighSpdClockGeneratorSelectValue (Bit 10) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdClockGeneratorSelectValue_Msk (0x400UL) /*!< HighSpdClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdSDCLKFrequenceSelectValue_Pos (0UL) /*!< HighSpdSDCLKFrequenceSelectValue (Bit 0) */ + #define SDEMMC_SDEMMC_PRESETVALUE1_REG_HighSpdSDCLKFrequenceSelectValue_Msk (0x3ffUL) /*!< HighSpdSDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ +/* ================================================ SDEMMC_PRESETVALUE2_REG ================================================ */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50DriveStrengthSelectValue_Pos (30UL) /*!< SDR50DriveStrengthSelectValue (Bit 30) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50DriveStrengthSelectValue_Msk (0xc0000000UL) /*!< SDR50DriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50ClockGeneratorSelectValue_Pos (26UL) /*!< SDR50ClockGeneratorSelectValue (Bit 26) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50ClockGeneratorSelectValue_Msk (0x4000000UL) /*!< SDR50ClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50SDCLKFrequenceSelectValue_Pos (16UL) /*!< SDR50SDCLKFrequenceSelectValue (Bit 16) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR50SDCLKFrequenceSelectValue_Msk (0x3ff0000UL) /*!< SDR50SDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25DriveStrengthSelectValue_Pos (14UL) /*!< SDR25DriveStrengthSelectValue (Bit 14) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25DriveStrengthSelectValue_Msk (0xc000UL) /*!< SDR25DriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25ClockGeneratorSelectValue_Pos (10UL) /*!< SDR25ClockGeneratorSelectValue (Bit 10) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25ClockGeneratorSelectValue_Msk (0x400UL) /*!< SDR25ClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25SDCLKFrequenceSelectValue_Pos (0UL) /*!< SDR25SDCLKFrequenceSelectValue (Bit 0) */ + #define SDEMMC_SDEMMC_PRESETVALUE2_REG_SDR25SDCLKFrequenceSelectValue_Msk (0x3ffUL) /*!< SDR25SDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ +/* ================================================ SDEMMC_PRESETVALUE3_REG ================================================ */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50DriveStrengthSelectValue_Pos (30UL) /*!< DDR50DriveStrengthSelectValue (Bit 30) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50DriveStrengthSelectValue_Msk (0xc0000000UL) /*!< DDR50DriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50ClockGeneratorSelectValue_Pos (26UL) /*!< DDR50ClockGeneratorSelectValue (Bit 26) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50ClockGeneratorSelectValue_Msk (0x4000000UL) /*!< DDR50ClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50SDCLKFrequenceSelectValue_Pos (16UL) /*!< DDR50SDCLKFrequenceSelectValue (Bit 16) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_DDR50SDCLKFrequenceSelectValue_Msk (0x3ff0000UL) /*!< DDR50SDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104DriveStrengthSelectValue_Pos (14UL) /*!< SDR104DriveStrengthSelectValue (Bit 14) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104DriveStrengthSelectValue_Msk (0xc000UL) /*!< SDR104DriveStrengthSelectValue (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104ClockGeneratorSelectValue_Pos (10UL) /*!< SDR104ClockGeneratorSelectValue (Bit 10) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104ClockGeneratorSelectValue_Msk (0x400UL) /*!< SDR104ClockGeneratorSelectValue (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104SDCLKFrequenceSelectValue_Pos (0UL) /*!< SDR104SDCLKFrequenceSelectValue (Bit 0) */ + #define SDEMMC_SDEMMC_PRESETVALUE3_REG_SDR104SDCLKFrequenceSelectValue_Msk (0x3ffUL) /*!< SDR104SDCLKFrequenceSelectValue (Bitfield-Mask: 0x3ff) */ +/* ================================================= SDEMMC_RESPONSE0_REG ================================================== */ + #define SDEMMC_SDEMMC_RESPONSE0_REG_Reponse0_Pos (0UL) /*!< Reponse0 (Bit 0) */ + #define SDEMMC_SDEMMC_RESPONSE0_REG_Reponse0_Msk (0xffffffffUL) /*!< Reponse0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SDEMMC_RESPONSE1_REG ================================================== */ + #define SDEMMC_SDEMMC_RESPONSE1_REG_Reponse1_Pos (0UL) /*!< Reponse1 (Bit 0) */ + #define SDEMMC_SDEMMC_RESPONSE1_REG_Reponse1_Msk (0xffffffffUL) /*!< Reponse1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SDEMMC_RESPONSE2_REG ================================================== */ + #define SDEMMC_SDEMMC_RESPONSE2_REG_Reponse2_Pos (0UL) /*!< Reponse2 (Bit 0) */ + #define SDEMMC_SDEMMC_RESPONSE2_REG_Reponse2_Msk (0xffffffffUL) /*!< Reponse2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SDEMMC_RESPONSE3_REG ================================================== */ + #define SDEMMC_SDEMMC_RESPONSE3_REG_Reponse3_Pos (0UL) /*!< Reponse3 (Bit 0) */ + #define SDEMMC_SDEMMC_RESPONSE3_REG_Reponse3_Msk (0xffffffffUL) /*!< Reponse3 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG ============================================ */ + #define SDEMMC_SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG_SDMA_System_Address_Argument2_Pos (0UL) /*!< SDMA_System_Address_Argument2 (Bit 0) */ + #define SDEMMC_SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG_SDMA_System_Address_Argument2_Msk (0xffffffffUL) /*!< SDMA_System_Address_Argument2 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== SDEMMC_SHAREDBUS_CTRL__REG =============================================== */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_BackEndPowerControl_Pos (24UL) /*!< BackEndPowerControl (Bit 24) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_BackEndPowerControl_Msk (0x7f000000UL) /*!< BackEndPowerControl (Bitfield-Mask: 0x7f) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_InterruptPinSelect_Pos (20UL) /*!< InterruptPinSelect (Bit 20) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_InterruptPinSelect_Msk (0x700000UL) /*!< InterruptPinSelect (Bitfield-Mask: 0x07) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_ClockPinSelect_Pos (16UL) /*!< ClockPinSelect (Bit 16) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_ClockPinSelect_Msk (0x70000UL) /*!< ClockPinSelect (Bitfield-Mask: 0x07) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_BusWidthPreset_Pos (8UL) /*!< BusWidthPreset (Bit 8) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_BusWidthPreset_Msk (0x7f00UL) /*!< BusWidthPreset (Bitfield-Mask: 0x7f) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_NumberOfInterruptInputPins_Pos (4UL) /*!< NumberOfInterruptInputPins (Bit 4) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_NumberOfInterruptInputPins_Msk (0x30UL) /*!< NumberOfInterruptInputPins (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_NumberOfClockPins_Pos (0UL) /*!< NumberOfClockPins (Bit 0) */ + #define SDEMMC_SDEMMC_SHAREDBUS_CTRL__REG_NumberOfClockPins_Msk (0x7UL) /*!< NumberOfClockPins (Bitfield-Mask: 0x07) */ +/* ============================================== SDEMMC_SLOT_ITNR_STATUS_REG ============================================== */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_SpecificationVersionNumber_Pos (16UL) /*!< SpecificationVersionNumber (Bit 16) */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_SpecificationVersionNumber_Msk (0xff0000UL) /*!< SpecificationVersionNumber (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_VendorVersionNumber_Pos (8UL) /*!< VendorVersionNumber (Bit 8) */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_VendorVersionNumber_Msk (0xff00UL) /*!< VendorVersionNumber (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_InterruptSignalForEachSlot_Pos (0UL) /*!< InterruptSignalForEachSlot (Bit 0) */ + #define SDEMMC_SDEMMC_SLOT_ITNR_STATUS_REG_InterruptSignalForEachSlot_Msk (0xffUL) /*!< InterruptSignalForEachSlot (Bitfield-Mask: 0xff) */ +/* ============================================ SDEMMC_TRANSFERMODE_COMMAND_REG ============================================ */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandIndex_Pos (24UL) /*!< CommandIndex (Bit 24) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandIndex_Msk (0x3f000000UL) /*!< CommandIndex (Bitfield-Mask: 0x3f) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandType_Pos (23UL) /*!< CommandType (Bit 23) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandType_Msk (0x800000UL) /*!< CommandType (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DataPresentSelect_Pos (21UL) /*!< DataPresentSelect (Bit 21) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DataPresentSelect_Msk (0x200000UL) /*!< DataPresentSelect (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandIndexCheckEnable_Pos (20UL) /*!< CommandIndexCheckEnable (Bit 20) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandIndexCheckEnable_Msk (0x100000UL) /*!< CommandIndexCheckEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandCRCCheckEnable_Pos (19UL) /*!< CommandCRCCheckEnable (Bit 19) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_CommandCRCCheckEnable_Msk (0x80000UL) /*!< CommandCRCCheckEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_ResponseTypeSelect_Pos (16UL) /*!< ResponseTypeSelect (Bit 16) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_ResponseTypeSelect_Msk (0x30000UL) /*!< ResponseTypeSelect (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_MultiSingleBlockSelect_Pos (5UL) /*!< MultiSingleBlockSelect (Bit 5) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_MultiSingleBlockSelect_Msk (0x20UL) /*!< MultiSingleBlockSelect (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DataTransferDirectionSelect_Pos (4UL) /*!< DataTransferDirectionSelect (Bit 4) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DataTransferDirectionSelect_Msk (0x10UL) /*!< DataTransferDirectionSelect (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_AutoCMDEnable_Pos (2UL) /*!< AutoCMDEnable (Bit 2) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_AutoCMDEnable_Msk (0xcUL) /*!< AutoCMDEnable (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_BlockCountEnable_Pos (1UL) /*!< BlockCountEnable (Bit 1) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_BlockCountEnable_Msk (0x2UL) /*!< BlockCountEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DMAEnable_Pos (0UL) /*!< DMAEnable (Bit 0) */ + #define SDEMMC_SDEMMC_TRANSFERMODE_COMMAND_REG_DMAEnable_Msk (0x1UL) /*!< DMAEnable (Bitfield-Mask: 0x01) */ +/* =================================================== SDEMMC_VENDOR_REG =================================================== */ + #define SDEMMC_SDEMMC_VENDOR_REG_Delay_cmdin_datin_dis_Pos (1UL) /*!< Delay_cmdin_datin_dis (Bit 1) */ + #define SDEMMC_SDEMMC_VENDOR_REG_Delay_cmdin_datin_dis_Msk (0x2UL) /*!< Delay_cmdin_datin_dis (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC_VENDOR_REG_AutoGateSDCLK_Pos (0UL) /*!< AutoGateSDCLK (Bit 0) */ + #define SDEMMC_SDEMMC_VENDOR_REG_AutoGateSDCLK_Msk (0x1UL) /*!< AutoGateSDCLK (Bitfield-Mask: 0x01) */ +/* ================================================== SDEMMC__ARGU_1_REG =================================================== */ + #define SDEMMC_SDEMMC__ARGU_1_REG_Argument1_Pos (0UL) /*!< Argument1 (Bit 0) */ + #define SDEMMC_SDEMMC__ARGU_1_REG_Argument1_Msk (0xffffffffUL) /*!< Argument1 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ SDEMMC__CLK__CTRL__REG ================================================= */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForDATLine_Pos (26UL) /*!< SoftwareResetForDATLine (Bit 26) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForDATLine_Msk (0x4000000UL) /*!< SoftwareResetForDATLine (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForCMDLine_Pos (25UL) /*!< SoftwareResetForCMDLine (Bit 25) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForCMDLine_Msk (0x2000000UL) /*!< SoftwareResetForCMDLine (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForAll_Pos (24UL) /*!< SoftwareResetForAll (Bit 24) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SoftwareResetForAll_Msk (0x1000000UL) /*!< SoftwareResetForAll (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_DataTimeoutCounterValue_Pos (16UL) /*!< DataTimeoutCounterValue (Bit 16) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_DataTimeoutCounterValue_Msk (0xf0000UL) /*!< DataTimeoutCounterValue (Bitfield-Mask: 0x0f) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SDCLKFrequencySelect_Pos (8UL) /*!< SDCLKFrequencySelect (Bit 8) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SDCLKFrequencySelect_Msk (0xff00UL) /*!< SDCLKFrequencySelect (Bitfield-Mask: 0xff) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_UpperBitsofSDCLKFrequencySelect_Pos (6UL) /*!< UpperBitsofSDCLKFrequencySelect (Bit 6) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_UpperBitsofSDCLKFrequencySelect_Msk (0xc0UL) /*!< UpperBitsofSDCLKFrequencySelect (Bitfield-Mask: 0x03) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_ClockGeneratorSelect_Pos (5UL) /*!< ClockGeneratorSelect (Bit 5) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_ClockGeneratorSelect_Msk (0x20UL) /*!< ClockGeneratorSelect (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SDClockEnable_Pos (2UL) /*!< SDClockEnable (Bit 2) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_SDClockEnable_Msk (0x4UL) /*!< SDClockEnable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_InternalClockStable_Pos (1UL) /*!< InternalClockStable (Bit 1) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_InternalClockStable_Msk (0x2UL) /*!< InternalClockStable (Bitfield-Mask: 0x01) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_InternalClockEnable_Pos (0UL) /*!< InternalClockEnable (Bit 0) */ + #define SDEMMC_SDEMMC__CLK__CTRL__REG_InternalClockEnable_Msk (0x1UL) /*!< InternalClockEnable (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SDIO ================ */ +/* =========================================================================================================================== */ + +/* ============================================= SDIO_ADMA_SYSTEM_ADDRESS_REG ============================================== */ + #define SDIO_SDIO_ADMA_SYSTEM_ADDRESS_REG_ADMA_SYSTEM_ADDRESS_Pos (28UL) /*!< ADMA_SYSTEM_ADDRESS (Bit 28) */ + #define SDIO_SDIO_ADMA_SYSTEM_ADDRESS_REG_ADMA_SYSTEM_ADDRESS_Msk (0xf0000000UL) /*!< ADMA_SYSTEM_ADDRESS (Bitfield-Mask: 0x0f) */ +/* ============================================== SDIO_AHB_FN0_INT_ENABLE_REG ============================================== */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_ERR_EN_Pos (11UL) /*!< FN0_ADMA_ERR_EN (Bit 11) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_ERR_EN_Msk (0x800UL) /*!< FN0_ADMA_ERR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_INT_EN_Pos (10UL) /*!< FN0_ADMA_INT_EN (Bit 10) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_INT_EN_Msk (0x400UL) /*!< FN0_ADMA_INT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_END_EN_Pos (9UL) /*!< FN0_ADMA_END_EN (Bit 9) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_ADMA_END_EN_Msk (0x200UL) /*!< FN0_ADMA_END_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_ERR_EN_Pos (8UL) /*!< FN0_RD_ERR_EN (Bit 8) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_ERR_EN_Msk (0x100UL) /*!< FN0_RD_ERR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_OVR_EN_Pos (7UL) /*!< FN0_RD_OVR_EN (Bit 7) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_OVR_EN_Msk (0x80UL) /*!< FN0_RD_OVR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_STRT_EN_Pos (6UL) /*!< FN0_RD_STRT_EN (Bit 6) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_RD_STRT_EN_Msk (0x40UL) /*!< FN0_RD_STRT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_WR_TRN_OVR_EN_Pos (5UL) /*!< FN0_WR_TRN_OVR_EN (Bit 5) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_WR_TRN_OVR_EN_Msk (0x20UL) /*!< FN0_WR_TRN_OVR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_WR_STRT_EN_Pos (4UL) /*!< FN0_WR_STRT_EN (Bit 4) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_FN0_WR_STRT_EN_Msk (0x10UL) /*!< FN0_WR_STRT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_CMD19_RD_TRN_OVR_EN_Pos (3UL) /*!< CMD19_RD_TRN_OVR_EN (Bit 3) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_CMD19_RD_TRN_OVR_EN_Msk (0x8UL) /*!< CMD19_RD_TRN_OVR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_CMD19_RD_STRT_EN_Pos (2UL) /*!< CMD19_RD_STRT_EN (Bit 2) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_CMD19_RD_STRT_EN_Msk (0x4UL) /*!< CMD19_RD_STRT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_VOLT_SWITCH_CMD_EN_Pos (1UL) /*!< VOLT_SWITCH_CMD_EN (Bit 1) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_VOLT_SWITCH_CMD_EN_Msk (0x2UL) /*!< VOLT_SWITCH_CMD_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_AHBSOFT_RST_EN_Pos (0UL) /*!< AHBSOFT_RST_EN (Bit 0) */ + #define SDIO_SDIO_AHB_FN0_INT_ENABLE_REG_AHBSOFT_RST_EN_Msk (0x1UL) /*!< AHBSOFT_RST_EN (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_AHB_FN0_INT_REG ================================================== */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_ERR_Pos (11UL) /*!< FN0_ADMA_ERR (Bit 11) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_ERR_Msk (0x800UL) /*!< FN0_ADMA_ERR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_INT_Pos (10UL) /*!< FN0_ADMA_INT (Bit 10) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_INT_Msk (0x400UL) /*!< FN0_ADMA_INT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_END_Pos (9UL) /*!< FN0_ADMA_END (Bit 9) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_ADMA_END_Msk (0x200UL) /*!< FN0_ADMA_END (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_ERR_Pos (8UL) /*!< FN0_RD_ERR (Bit 8) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_ERR_Msk (0x100UL) /*!< FN0_RD_ERR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_OVR_Pos (7UL) /*!< FN0_RD_OVR (Bit 7) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_OVR_Msk (0x80UL) /*!< FN0_RD_OVR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_STRT_Pos (6UL) /*!< FN0_RD_STRT (Bit 6) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_RD_STRT_Msk (0x40UL) /*!< FN0_RD_STRT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_WR_TRN_OVR_Pos (5UL) /*!< FN0_WR_TRN_OVR (Bit 5) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_WR_TRN_OVR_Msk (0x20UL) /*!< FN0_WR_TRN_OVR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_WR_STRT_Pos (4UL) /*!< FN0_WR_STRT (Bit 4) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_FN0_WR_STRT_Msk (0x10UL) /*!< FN0_WR_STRT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_CMD19_RD_TRN_OVR_Pos (3UL) /*!< CMD19_RD_TRN_OVR (Bit 3) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_CMD19_RD_TRN_OVR_Msk (0x8UL) /*!< CMD19_RD_TRN_OVR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_CMD19_RD_STRT_Pos (2UL) /*!< CMD19_RD_STRT (Bit 2) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_CMD19_RD_STRT_Msk (0x4UL) /*!< CMD19_RD_STRT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_VOLT_SWITCH_CMD_Pos (1UL) /*!< VOLT_SWITCH_CMD (Bit 1) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_VOLT_SWITCH_CMD_Msk (0x2UL) /*!< VOLT_SWITCH_CMD (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_AHBSOFT_RST_Pos (0UL) /*!< AHBSOFT_RST (Bit 0) */ + #define SDIO_SDIO_AHB_FN0_INT_REG_AHBSOFT_RST_Msk (0x1UL) /*!< AHBSOFT_RST (Bitfield-Mask: 0x01) */ +/* ============================================== SDIO_AHB_FN1_INT_ENABLE_REG ============================================== */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FUN1_EN_INT_EN_Pos (13UL) /*!< FUN1_EN_INT_EN (Bit 13) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FUN1_EN_INT_EN_Msk (0x2000UL) /*!< FUN1_EN_INT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_ERR_EN_Pos (12UL) /*!< ADMA_ERR_EN (Bit 12) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_ERR_EN_Msk (0x1000UL) /*!< ADMA_ERR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_INT_EN_Pos (11UL) /*!< ADMA_INT_EN (Bit 11) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_INT_EN_Msk (0x800UL) /*!< ADMA_INT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_RESUME_EN_Pos (10UL) /*!< RESUME_EN (Bit 10) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_RESUME_EN_Msk (0x400UL) /*!< RESUME_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SUSPEND_EN_Pos (9UL) /*!< FN1_SUSPEND_EN (Bit 9) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SUSPEND_EN_Msk (0x200UL) /*!< FN1_SUSPEND_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_END_INT_EN_Pos (8UL) /*!< ADMA_END_INT_EN (Bit 8) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_ADMA_END_INT_EN_Msk (0x100UL) /*!< ADMA_END_INT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SDIO_WR_START_EN_Pos (7UL) /*!< FN1_SDIO_WR_START_EN (Bit 7) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SDIO_WR_START_EN_Msk (0x80UL) /*!< FN1_SDIO_WR_START_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SDIO_RD_START_EN_Pos (6UL) /*!< FN1_SDIO_RD_START_EN (Bit 6) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_SDIO_RD_START_EN_Msk (0x40UL) /*!< FN1_SDIO_RD_START_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_ACK_TO_ARM_EN_Pos (5UL) /*!< FN1_ACK_TO_ARM_EN (Bit 5) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_ACK_TO_ARM_EN_Msk (0x20UL) /*!< FN1_ACK_TO_ARM_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_SD_HOST_FN1_MSG_RDY_EN_Pos (4UL) /*!< SD_HOST_FN1_MSG_RDY_EN (Bit 4) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_SD_HOST_FN1_MSG_RDY_EN_Msk (0x10UL) /*!< SD_HOST_FN1_MSG_RDY_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FUN1_RST_EN_Pos (3UL) /*!< FUN1_RST_EN (Bit 3) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FUN1_RST_EN_Msk (0x8UL) /*!< FUN1_RST_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_RD_ERROR_EN_Pos (2UL) /*!< FN1_RD_ERROR_EN (Bit 2) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_RD_ERROR_EN_Msk (0x4UL) /*!< FN1_RD_ERROR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_RD_OVER_EN_Pos (1UL) /*!< FN1_RD_OVER_EN (Bit 1) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_RD_OVER_EN_Msk (0x2UL) /*!< FN1_RD_OVER_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_WR_OVER_EN_Pos (0UL) /*!< FN1_WR_OVER_EN (Bit 0) */ + #define SDIO_SDIO_AHB_FN1_INT_ENABLE_REG_FN1_WR_OVER_EN_Msk (0x1UL) /*!< FN1_WR_OVER_EN (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_AHB_FN1_INT_REG ================================================== */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FUN1_EN_Pos (13UL) /*!< FUN1_EN (Bit 13) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FUN1_EN_Msk (0x2000UL) /*!< FUN1_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_ERR_Pos (12UL) /*!< ADMA_ERR (Bit 12) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_ERR_Msk (0x1000UL) /*!< ADMA_ERR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_INT_Pos (11UL) /*!< ADMA_INT (Bit 11) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_INT_Msk (0x800UL) /*!< ADMA_INT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_RESUME_Pos (10UL) /*!< RESUME (Bit 10) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_RESUME_Msk (0x400UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SUSPEND_Pos (9UL) /*!< FN1_SUSPEND (Bit 9) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SUSPEND_Msk (0x200UL) /*!< FN1_SUSPEND (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_END_INT_Pos (8UL) /*!< ADMA_END_INT (Bit 8) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_ADMA_END_INT_Msk (0x100UL) /*!< ADMA_END_INT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SDIO_WR_START_Pos (7UL) /*!< FN1_SDIO_WR_START (Bit 7) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SDIO_WR_START_Msk (0x80UL) /*!< FN1_SDIO_WR_START (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SDIO_RD_START_Pos (6UL) /*!< FN1_SDIO_RD_START (Bit 6) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_SDIO_RD_START_Msk (0x40UL) /*!< FN1_SDIO_RD_START (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_ACK_TO_ARM_Pos (5UL) /*!< FN1_ACK_TO_ARM (Bit 5) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_ACK_TO_ARM_Msk (0x20UL) /*!< FN1_ACK_TO_ARM (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_SD_HOST_FN1_MSG_RDY_Pos (4UL) /*!< SD_HOST_FN1_MSG_RDY (Bit 4) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_SD_HOST_FN1_MSG_RDY_Msk (0x10UL) /*!< SD_HOST_FN1_MSG_RDY (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FUN1_RST_Pos (3UL) /*!< FUN1_RST (Bit 3) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FUN1_RST_Msk (0x8UL) /*!< FUN1_RST (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_RD_ERROR_Pos (2UL) /*!< FN1_RD_ERROR (Bit 2) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_RD_ERROR_Msk (0x4UL) /*!< FN1_RD_ERROR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_RD_OVER_Pos (1UL) /*!< FN1_RD_OVER (Bit 1) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_RD_OVER_Msk (0x2UL) /*!< FN1_RD_OVER (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_WR_OVER_Pos (0UL) /*!< FN1_WR_OVER (Bit 0) */ + #define SDIO_SDIO_AHB_FN1_INT_REG_FN1_WR_OVER_Msk (0x1UL) /*!< FN1_WR_OVER (Bitfield-Mask: 0x01) */ +/* ============================================== SDIO_AHB_SDIOTRANSCOUNT_REG ============================================== */ + #define SDIO_SDIO_AHB_SDIOTRANSCOUNT_REG_XFER_CNT_REG_Pos (0UL) /*!< XFER_CNT_REG (Bit 0) */ + #define SDIO_SDIO_AHB_SDIOTRANSCOUNT_REG_XFER_CNT_REG_Msk (0x1fffffUL) /*!< XFER_CNT_REG (Bitfield-Mask: 0x1fffff) */ +/* ================================================ SDIO_AHB_TRANSCOUNT_REG ================================================ */ + #define SDIO_SDIO_AHB_TRANSCOUNT_REG_AHB_XFER_CNT_Pos (0UL) /*!< AHB_XFER_CNT (Bit 0) */ + #define SDIO_SDIO_AHB_TRANSCOUNT_REG_AHB_XFER_CNT_Msk (0x1fffffUL) /*!< AHB_XFER_CNT (Bitfield-Mask: 0x1fffff) */ +/* =================================================== SDIO_ARGUMENT_REG =================================================== */ + #define SDIO_SDIO_ARGUMENT_REG_ARG_REG_Pos (0UL) /*!< ARG_REG (Bit 0) */ + #define SDIO_SDIO_ARGUMENT_REG_ARG_REG_Msk (0xffffffffUL) /*!< ARG_REG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== SDIO_ARM_GP_REG ==================================================== */ + #define SDIO_SDIO_ARM_GP_REG_ARM_GP_Pos (0UL) /*!< ARM_GP (Bit 0) */ + #define SDIO_SDIO_ARM_GP_REG_ARM_GP_Msk (0xffffffffUL) /*!< ARM_GP (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SDIO_BLKSIZE_REG ==================================================== */ + #define SDIO_SDIO_BLKSIZE_REG_SIN_MUL_BLK_Pos (12UL) /*!< SIN_MUL_BLK (Bit 12) */ + #define SDIO_SDIO_BLKSIZE_REG_SIN_MUL_BLK_Msk (0x1000UL) /*!< SIN_MUL_BLK (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_BLKSIZE_REG_BLK_SIZE_Pos (0UL) /*!< BLK_SIZE (Bit 0) */ + #define SDIO_SDIO_BLKSIZE_REG_BLK_SIZE_Msk (0xfffUL) /*!< BLK_SIZE (Bitfield-Mask: 0xfff) */ +/* =================================================== SDIO_CARDRDY_REG ==================================================== */ + #define SDIO_SDIO_CARDRDY_REG_CARD_RDY_Pos (0UL) /*!< CARD_RDY (Bit 0) */ + #define SDIO_SDIO_CARDRDY_REG_CARD_RDY_Msk (0x1UL) /*!< CARD_RDY (Bitfield-Mask: 0x01) */ +/* ===================================================== SDIO_CCCR_REG ===================================================== */ + #define SDIO_SDIO_CCCR_REG_CMD_INDEX_Pos (22UL) /*!< CMD_INDEX (Bit 22) */ + #define SDIO_SDIO_CCCR_REG_CMD_INDEX_Msk (0xfc00000UL) /*!< CMD_INDEX (Bitfield-Mask: 0x3f) */ + #define SDIO_SDIO_CCCR_REG_SHS_Pos (21UL) /*!< SHS (Bit 21) */ + #define SDIO_SDIO_CCCR_REG_SHS_Msk (0x200000UL) /*!< SHS (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SMPC_Pos (20UL) /*!< SMPC (Bit 20) */ + #define SDIO_SDIO_CCCR_REG_SMPC_Msk (0x100000UL) /*!< SMPC (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_FOURBLS_Pos (19UL) /*!< FOURBLS (Bit 19) */ + #define SDIO_SDIO_CCCR_REG_FOURBLS_Msk (0x80000UL) /*!< FOURBLS (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_LSC_Pos (18UL) /*!< LSC (Bit 18) */ + #define SDIO_SDIO_CCCR_REG_LSC_Msk (0x40000UL) /*!< LSC (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_S4MI_Pos (17UL) /*!< S4MI (Bit 17) */ + #define SDIO_SDIO_CCCR_REG_S4MI_Msk (0x20000UL) /*!< S4MI (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SBS_Pos (16UL) /*!< SBS (Bit 16) */ + #define SDIO_SDIO_CCCR_REG_SBS_Msk (0x10000UL) /*!< SBS (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SRW_Pos (15UL) /*!< SRW (Bit 15) */ + #define SDIO_SDIO_CCCR_REG_SRW_Msk (0x8000UL) /*!< SRW (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SMB_Pos (14UL) /*!< SMB (Bit 14) */ + #define SDIO_SDIO_CCCR_REG_SMB_Msk (0x4000UL) /*!< SMB (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SDC_Pos (13UL) /*!< SDC (Bit 13) */ + #define SDIO_SDIO_CCCR_REG_SDC_Msk (0x2000UL) /*!< SDC (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SCSI_Pos (12UL) /*!< SCSI (Bit 12) */ + #define SDIO_SDIO_CCCR_REG_SCSI_Msk (0x1000UL) /*!< SCSI (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CCCR_REG_SD_REVISION_Pos (8UL) /*!< SD_REVISION (Bit 8) */ + #define SDIO_SDIO_CCCR_REG_SD_REVISION_Msk (0xf00UL) /*!< SD_REVISION (Bitfield-Mask: 0x0f) */ + #define SDIO_SDIO_CCCR_REG_SDIO_REVISION_Pos (4UL) /*!< SDIO_REVISION (Bit 4) */ + #define SDIO_SDIO_CCCR_REG_SDIO_REVISION_Msk (0xf0UL) /*!< SDIO_REVISION (Bitfield-Mask: 0x0f) */ + #define SDIO_SDIO_CCCR_REG_CCCR_REVISION_Pos (0UL) /*!< CCCR_REVISION (Bit 0) */ + #define SDIO_SDIO_CCCR_REG_CCCR_REVISION_Msk (0xfUL) /*!< CCCR_REVISION (Bitfield-Mask: 0x0f) */ +/* =============================================== SDIO_CLK_DELAY_TIMER_REG ================================================ */ + #define SDIO_SDIO_CLK_DELAY_TIMER_REG_CLK_DELAY_TIMER_Pos (0UL) /*!< CLK_DELAY_TIMER (Bit 0) */ + #define SDIO_SDIO_CLK_DELAY_TIMER_REG_CLK_DELAY_TIMER_Msk (0xffffffffUL) /*!< CLK_DELAY_TIMER (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SDIO_CLOCK_WAKEUP_REG ================================================= */ + #define SDIO_SDIO_CLOCK_WAKEUP_REG_MANUAL_CLK_ENABLE_Pos (1UL) /*!< MANUAL_CLK_ENABLE (Bit 1) */ + #define SDIO_SDIO_CLOCK_WAKEUP_REG_MANUAL_CLK_ENABLE_Msk (0x2UL) /*!< MANUAL_CLK_ENABLE (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_CLOCK_WAKEUP_REG_AUTO_CLK_ENABLE_Pos (0UL) /*!< AUTO_CLK_ENABLE (Bit 0) */ + #define SDIO_SDIO_CLOCK_WAKEUP_REG_AUTO_CLK_ENABLE_Msk (0x1UL) /*!< AUTO_CLK_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_CSA_POINTER_REG ================================================== */ + #define SDIO_SDIO_CSA_POINTER_REG_CSA_POINTER_Pos (0UL) /*!< CSA_POINTER (Bit 0) */ + #define SDIO_SDIO_CSA_POINTER_REG_CSA_POINTER_Msk (0xffffffUL) /*!< CSA_POINTER (Bitfield-Mask: 0xffffff) */ +/* ===================================================== SDIO_FBR_REG ====================================================== */ + #define SDIO_SDIO_FBR_REG_SDIO_SPS_Pos (13UL) /*!< SDIO_SPS (Bit 13) */ + #define SDIO_SDIO_FBR_REG_SDIO_SPS_Msk (0x2000UL) /*!< SDIO_SPS (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_FBR_REG_EXTENDED_IO_DEVICE_CODE1_Pos (5UL) /*!< EXTENDED_IO_DEVICE_CODE1 (Bit 5) */ + #define SDIO_SDIO_FBR_REG_EXTENDED_IO_DEVICE_CODE1_Msk (0x1fe0UL) /*!< EXTENDED_IO_DEVICE_CODE1 (Bitfield-Mask: 0xff) */ + #define SDIO_SDIO_FBR_REG_FUN_CSA_SUP_Pos (4UL) /*!< FUN_CSA_SUP (Bit 4) */ + #define SDIO_SDIO_FBR_REG_FUN_CSA_SUP_Msk (0x10UL) /*!< FUN_CSA_SUP (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_FBR_REG_IO_DEVICE_CODE1_Pos (0UL) /*!< IO_DEVICE_CODE1 (Bit 0) */ + #define SDIO_SDIO_FBR_REG_IO_DEVICE_CODE1_Msk (0xfUL) /*!< IO_DEVICE_CODE1 (Bitfield-Mask: 0x0f) */ +/* ==================================================== SDIO_FUNRDY_REG ==================================================== */ + #define SDIO_SDIO_FUNRDY_REG_CARD_RDY_Pos (0UL) /*!< CARD_RDY (Bit 0) */ + #define SDIO_SDIO_FUNRDY_REG_CARD_RDY_Msk (0x1UL) /*!< CARD_RDY (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_GLB_INT_ENA_REG ================================================== */ + #define SDIO_SDIO_GLB_INT_ENA_REG_FN1_INT_TO_ARM_EN_Pos (1UL) /*!< FN1_INT_TO_ARM_EN (Bit 1) */ + #define SDIO_SDIO_GLB_INT_ENA_REG_FN1_INT_TO_ARM_EN_Msk (0x2UL) /*!< FN1_INT_TO_ARM_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_GLB_INT_ENA_REG_FN0_INT_TO_ARM_EN_Pos (0UL) /*!< FN0_INT_TO_ARM_EN (Bit 0) */ + #define SDIO_SDIO_GLB_INT_ENA_REG_FN0_INT_TO_ARM_EN_Msk (0x1UL) /*!< FN0_INT_TO_ARM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_GLB_INT_STS_REG ================================================== */ + #define SDIO_SDIO_GLB_INT_STS_REG_FN1_INT_TO_ARM_Pos (1UL) /*!< FN1_INT_TO_ARM (Bit 1) */ + #define SDIO_SDIO_GLB_INT_STS_REG_FN1_INT_TO_ARM_Msk (0x2UL) /*!< FN1_INT_TO_ARM (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_GLB_INT_STS_REG_FN0_INT_TO_ARM_Pos (0UL) /*!< FN0_INT_TO_ARM (Bit 0) */ + #define SDIO_SDIO_GLB_INT_STS_REG_FN0_INT_TO_ARM_Msk (0x1UL) /*!< FN0_INT_TO_ARM (Bitfield-Mask: 0x01) */ +/* ================================================== SDIO_INTERRUPT_REG =================================================== */ + #define SDIO_SDIO_INTERRUPT_REG_ACK_TO_SD_HOST_EN_Pos (11UL) /*!< ACK_TO_SD_HOST_EN (Bit 11) */ + #define SDIO_SDIO_INTERRUPT_REG_ACK_TO_SD_HOST_EN_Msk (0x800UL) /*!< ACK_TO_SD_HOST_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_MESSAGE_FROM_ARM_EN_Pos (10UL) /*!< MESSAGE_FROM_ARM_EN (Bit 10) */ + #define SDIO_SDIO_INTERRUPT_REG_MESSAGE_FROM_ARM_EN_Msk (0x400UL) /*!< MESSAGE_FROM_ARM_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_ERROR_EN_Pos (9UL) /*!< READ_ERROR_EN (Bit 9) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_ERROR_EN_Msk (0x200UL) /*!< READ_ERROR_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_DATA_READY_INT_EN_Pos (8UL) /*!< READ_DATA_READY_INT_EN (Bit 8) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_DATA_READY_INT_EN_Msk (0x100UL) /*!< READ_DATA_READY_INT_EN (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_ACK_TO_SD_HOST_Pos (3UL) /*!< ACK_TO_SD_HOST (Bit 3) */ + #define SDIO_SDIO_INTERRUPT_REG_ACK_TO_SD_HOST_Msk (0x8UL) /*!< ACK_TO_SD_HOST (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_MESSAGE_FROM_ARM_Pos (2UL) /*!< MESSAGE_FROM_ARM (Bit 2) */ + #define SDIO_SDIO_INTERRUPT_REG_MESSAGE_FROM_ARM_Msk (0x4UL) /*!< MESSAGE_FROM_ARM (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_ERROR_Pos (1UL) /*!< READ_ERROR (Bit 1) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_ERROR_Msk (0x2UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_DATA_READY_INT_Pos (0UL) /*!< READ_DATA_READY_INT (Bit 0) */ + #define SDIO_SDIO_INTERRUPT_REG_READ_DATA_READY_INT_Msk (0x1UL) /*!< READ_DATA_READY_INT (Bitfield-Mask: 0x01) */ +/* ===================================================== SDIO_IOR_REG ====================================================== */ + #define SDIO_SDIO_IOR_REG_IOR_REG_Pos (0UL) /*!< IOR_REG (Bit 0) */ + #define SDIO_SDIO_IOR_REG_IOR_REG_Msk (0x1UL) /*!< IOR_REG (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_IO_ACC_MODE_REG ================================================== */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SAI_Pos (6UL) /*!< SAI (Bit 6) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTD_Pos (5UL) /*!< SDTD (Bit 5) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTD_Msk (0x20UL) /*!< SDTD (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTC_Pos (4UL) /*!< SDTC (Bit 4) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTC_Msk (0x10UL) /*!< SDTC (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTA_Pos (3UL) /*!< SDTA (Bit 3) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDTA_Msk (0x8UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDDR50_Pos (2UL) /*!< SDDR50 (Bit 2) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SDDR50_Msk (0x4UL) /*!< SDDR50 (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SSDR104_Pos (1UL) /*!< SSDR104 (Bit 1) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SSDR104_Msk (0x2UL) /*!< SSDR104 (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SSDR50_Pos (0UL) /*!< SSDR50 (Bit 0) */ + #define SDIO_SDIO_IO_ACC_MODE_REG_SSDR50_Msk (0x1UL) /*!< SSDR50 (Bitfield-Mask: 0x01) */ +/* =============================================== SDIO_LAST_FETCH_ADDR_REG ================================================ */ + #define SDIO_SDIO_LAST_FETCH_ADDR_REG_LAST_FETCH_ADDR_Pos (0UL) /*!< LAST_FETCH_ADDR (Bit 0) */ + #define SDIO_SDIO_LAST_FETCH_ADDR_REG_LAST_FETCH_ADDR_Msk (0xffffffffUL) /*!< LAST_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SDIO_OCR_REG ====================================================== */ + #define SDIO_SDIO_OCR_REG_OCR_Pos (0UL) /*!< OCR (Bit 0) */ + #define SDIO_SDIO_OCR_REG_OCR_Msk (0xffffffUL) /*!< OCR (Bitfield-Mask: 0xffffff) */ +/* ================================================ SDIO_POWER_CONTROL_REG ================================================= */ + #define SDIO_SDIO_POWER_CONTROL_REG_FASTINIT_REQUEST_Pos (9UL) /*!< FASTINIT_REQUEST (Bit 9) */ + #define SDIO_SDIO_POWER_CONTROL_REG_FASTINIT_REQUEST_Msk (0x200UL) /*!< FASTINIT_REQUEST (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_POWER_CONTROL_REG_POWERDOWN_REQUEST_Pos (8UL) /*!< POWERDOWN_REQUEST (Bit 8) */ + #define SDIO_SDIO_POWER_CONTROL_REG_POWERDOWN_REQUEST_Msk (0x100UL) /*!< POWERDOWN_REQUEST (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_POWER_CONTROL_REG_EPS_FUN1_Pos (1UL) /*!< EPS_FUN1 (Bit 1) */ + #define SDIO_SDIO_POWER_CONTROL_REG_EPS_FUN1_Msk (0x2UL) /*!< EPS_FUN1 (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_POWER_CONTROL_REG_EMPC_Pos (0UL) /*!< EMPC (Bit 0) */ + #define SDIO_SDIO_POWER_CONTROL_REG_EMPC_Msk (0x1UL) /*!< EMPC (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_POWER_STATE_REG ================================================== */ + #define SDIO_SDIO_POWER_STATE_REG_PWR_STATE_FN1_Pos (0UL) /*!< PWR_STATE_FN1 (Bit 0) */ + #define SDIO_SDIO_POWER_STATE_REG_PWR_STATE_FN1_Msk (0xfUL) /*!< PWR_STATE_FN1 (Bitfield-Mask: 0x0f) */ +/* =================================================== SDIO_RDBLKCNT_REG =================================================== */ + #define SDIO_SDIO_RDBLKCNT_REG_RD_BLK_CNT_Pos (0UL) /*!< RD_BLK_CNT (Bit 0) */ + #define SDIO_SDIO_RDBLKCNT_REG_RD_BLK_CNT_Msk (0xffffUL) /*!< RD_BLK_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== SDIO_RDDATRDY_REG =================================================== */ + #define SDIO_SDIO_RDDATRDY_REG_FN1_RDDATRDY_Pos (0UL) /*!< FN1_RDDATRDY (Bit 0) */ + #define SDIO_SDIO_RDDATRDY_REG_FN1_RDDATRDY_Msk (0x1UL) /*!< FN1_RDDATRDY (Bitfield-Mask: 0x01) */ +/* ================================================== SDIO_SD_HOST_GP_REG ================================================== */ + #define SDIO_SDIO_SD_HOST_GP_REG_SD_HOST_GP_Pos (0UL) /*!< SD_HOST_GP (Bit 0) */ + #define SDIO_SDIO_SD_HOST_GP_REG_SD_HOST_GP_Msk (0xffffffffUL) /*!< SD_HOST_GP (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SDIO_SOFT_RST_AHB_REG ================================================= */ + #define SDIO_SDIO_SOFT_RST_AHB_REG_AHBSOFT_VALID_Pos (0UL) /*!< AHBSOFT_VALID (Bit 0) */ + #define SDIO_SDIO_SOFT_RST_AHB_REG_AHBSOFT_VALID_Msk (0x1UL) /*!< AHBSOFT_VALID (Bitfield-Mask: 0x01) */ +/* ================================================= SDIO_UHS_SUPPORT_REG ================================================== */ + #define SDIO_SDIO_UHS_SUPPORT_REG_SD_CMD_LINE_SWITCHED_Pos (4UL) /*!< SD_CMD_LINE_SWITCHED (Bit 4) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_SD_CMD_LINE_SWITCHED_Msk (0x10UL) /*!< SD_CMD_LINE_SWITCHED (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_SD_CLK_LINE_SWITCHED_Pos (3UL) /*!< SD_CLK_LINE_SWITCHED (Bit 3) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_SD_CLK_LINE_SWITCHED_Msk (0x8UL) /*!< SD_CLK_LINE_SWITCHED (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_CARD_VOLT_ACCEPTED_Pos (2UL) /*!< CARD_VOLT_ACCEPTED (Bit 2) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_CARD_VOLT_ACCEPTED_Msk (0x4UL) /*!< CARD_VOLT_ACCEPTED (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_DDR_DLY_SELECT_Pos (1UL) /*!< DDR_DLY_SELECT (Bit 1) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_DDR_DLY_SELECT_Msk (0x2UL) /*!< DDR_DLY_SELECT (Bitfield-Mask: 0x01) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_UHS_SUPPORT_Pos (0UL) /*!< UHS_SUPPORT (Bit 0) */ + #define SDIO_SDIO_UHS_SUPPORT_REG_UHS_SUPPORT_Msk (0x1UL) /*!< UHS_SUPPORT (Bitfield-Mask: 0x01) */ +/* =================================================== SDIO_WRBLKCNT_REG =================================================== */ + #define SDIO_SDIO_WRBLKCNT_REG_WR_BLK_CNT_Pos (0UL) /*!< WR_BLK_CNT (Bit 0) */ + #define SDIO_SDIO_WRBLKCNT_REG_WR_BLK_CNT_Msk (0xffffUL) /*!< WR_BLK_CNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SPI_CLOCK_REG ===================================================== */ + #define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos (0UL) /*!< SPI_CLK_DIV (Bit 0) */ + #define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk (0x7fUL) /*!< SPI_CLK_DIV (Bitfield-Mask: 0x7f) */ +/* ==================================================== SPI_CONFIG_REG ===================================================== */ + #define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos (7UL) /*!< SPI_SLAVE_EN (Bit 7) */ + #define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Msk (0x80UL) /*!< SPI_SLAVE_EN (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Pos (2UL) /*!< SPI_WORD_LENGTH (Bit 2) */ + #define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Msk (0x7cUL) /*!< SPI_WORD_LENGTH (Bitfield-Mask: 0x1f) */ + #define SPI_SPI_CONFIG_REG_SPI_MODE_Pos (0UL) /*!< SPI_MODE (Bit 0) */ + #define SPI_SPI_CONFIG_REG_SPI_MODE_Msk (0x3UL) /*!< SPI_MODE (Bitfield-Mask: 0x03) */ +/* =================================================== SPI_CS_CONFIG_REG =================================================== */ + #define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Pos (0UL) /*!< SPI_CS_SELECT (Bit 0) */ + #define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Msk (0x7UL) /*!< SPI_CS_SELECT (Bitfield-Mask: 0x07) */ +/* ===================================================== SPI_CTRL_REG ====================================================== */ + #define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos (7UL) /*!< SPI_SWAP_BYTES (Bit 7) */ + #define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Msk (0x80UL) /*!< SPI_SWAP_BYTES (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos (6UL) /*!< SPI_CAPTURE_AT_NEXT_EDGE (Bit 6) */ + #define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk (0x40UL) /*!< SPI_CAPTURE_AT_NEXT_EDGE (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Pos (5UL) /*!< SPI_FIFO_RESET (Bit 5) */ + #define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk (0x20UL) /*!< SPI_FIFO_RESET (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Pos (4UL) /*!< SPI_DMA_RX_EN (Bit 4) */ + #define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk (0x10UL) /*!< SPI_DMA_RX_EN (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Pos (3UL) /*!< SPI_DMA_TX_EN (Bit 3) */ + #define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk (0x8UL) /*!< SPI_DMA_TX_EN (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_RX_EN_Pos (2UL) /*!< SPI_RX_EN (Bit 2) */ + #define SPI_SPI_CTRL_REG_SPI_RX_EN_Msk (0x4UL) /*!< SPI_RX_EN (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_TX_EN_Pos (1UL) /*!< SPI_TX_EN (Bit 1) */ + #define SPI_SPI_CTRL_REG_SPI_TX_EN_Msk (0x2UL) /*!< SPI_TX_EN (Bitfield-Mask: 0x01) */ + #define SPI_SPI_CTRL_REG_SPI_EN_Pos (0UL) /*!< SPI_EN (Bit 0) */ + #define SPI_SPI_CTRL_REG_SPI_EN_Msk (0x1UL) /*!< SPI_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SPI_FIFO_CONFIG_REG ================================================== */ + #define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos (8UL) /*!< SPI_RX_TL (Bit 8) */ + #define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk (0xff00UL) /*!< SPI_RX_TL (Bitfield-Mask: 0xff) */ + #define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos (0UL) /*!< SPI_TX_TL (Bit 0) */ + #define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk (0xffUL) /*!< SPI_TX_TL (Bitfield-Mask: 0xff) */ +/* =================================================== SPI_FIFO_READ_REG =================================================== */ + #define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Pos (0UL) /*!< SPI_FIFO_READ (Bit 0) */ + #define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Msk (0xffffffffUL) /*!< SPI_FIFO_READ (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SPI_FIFO_STATUS_REG ================================================== */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos (15UL) /*!< SPI_TRANSACTION_ACTIVE (Bit 15) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk (0x8000UL) /*!< SPI_TRANSACTION_ACTIVE (Bitfield-Mask: 0x01) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos (14UL) /*!< SPI_RX_FIFO_OVFL (Bit 14) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk (0x4000UL) /*!< SPI_RX_FIFO_OVFL (Bitfield-Mask: 0x01) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos (13UL) /*!< SPI_STATUS_TX_FULL (Bit 13) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk (0x2000UL) /*!< SPI_STATUS_TX_FULL (Bitfield-Mask: 0x01) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos (12UL) /*!< SPI_STATUS_RX_EMPTY (Bit 12) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk (0x1000UL) /*!< SPI_STATUS_RX_EMPTY (Bitfield-Mask: 0x01) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos (6UL) /*!< SPI_TX_FIFO_LEVEL (Bit 6) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk (0xfc0UL) /*!< SPI_TX_FIFO_LEVEL (Bitfield-Mask: 0x3f) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos (0UL) /*!< SPI_RX_FIFO_LEVEL (Bit 0) */ + #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk (0x3fUL) /*!< SPI_RX_FIFO_LEVEL (Bitfield-Mask: 0x3f) */ +/* ================================================== SPI_FIFO_WRITE_REG =================================================== */ + #define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos (0UL) /*!< SPI_FIFO_WRITE (Bit 0) */ + #define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk (0xffffffffUL) /*!< SPI_FIFO_WRITE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SPI_IRQ_MASK_REG ==================================================== */ + #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos (1UL) /*!< SPI_IRQ_MASK_RX_FULL (Bit 1) */ + #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk (0x2UL) /*!< SPI_IRQ_MASK_RX_FULL (Bitfield-Mask: 0x01) */ + #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos (0UL) /*!< SPI_IRQ_MASK_TX_EMPTY (Bit 0) */ + #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk (0x1UL) /*!< SPI_IRQ_MASK_TX_EMPTY (Bitfield-Mask: 0x01) */ +/* ==================================================== SPI_STATUS_REG ===================================================== */ + #define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Pos (1UL) /*!< SPI_STATUS_RX_FULL (Bit 1) */ + #define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk (0x2UL) /*!< SPI_STATUS_RX_FULL (Bitfield-Mask: 0x01) */ + #define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos (0UL) /*!< SPI_STATUS_TX_EMPTY (Bit 0) */ + #define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk (0x1UL) /*!< SPI_STATUS_TX_EMPTY (Bitfield-Mask: 0x01) */ +/* ================================================ SPI_TXBUFFER_FORCE_REG ================================================= */ + #define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos (0UL) /*!< SPI_TXBUFFER_FORCE (Bit 0) */ + #define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk (0xffffffffUL) /*!< SPI_TXBUFFER_FORCE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== SPI2_CLOCK_REG ===================================================== */ + #define SPI2_SPI2_CLOCK_REG_SPI_CLK_DIV_Pos (0UL) /*!< SPI_CLK_DIV (Bit 0) */ + #define SPI2_SPI2_CLOCK_REG_SPI_CLK_DIV_Msk (0x7fUL) /*!< SPI_CLK_DIV (Bitfield-Mask: 0x7f) */ +/* ==================================================== SPI2_CONFIG_REG ==================================================== */ + #define SPI2_SPI2_CONFIG_REG_SPI_SLAVE_EN_Pos (7UL) /*!< SPI_SLAVE_EN (Bit 7) */ + #define SPI2_SPI2_CONFIG_REG_SPI_SLAVE_EN_Msk (0x80UL) /*!< SPI_SLAVE_EN (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CONFIG_REG_SPI_WORD_LENGTH_Pos (2UL) /*!< SPI_WORD_LENGTH (Bit 2) */ + #define SPI2_SPI2_CONFIG_REG_SPI_WORD_LENGTH_Msk (0x7cUL) /*!< SPI_WORD_LENGTH (Bitfield-Mask: 0x1f) */ + #define SPI2_SPI2_CONFIG_REG_SPI_MODE_Pos (0UL) /*!< SPI_MODE (Bit 0) */ + #define SPI2_SPI2_CONFIG_REG_SPI_MODE_Msk (0x3UL) /*!< SPI_MODE (Bitfield-Mask: 0x03) */ +/* ================================================== SPI2_CS_CONFIG_REG =================================================== */ + #define SPI2_SPI2_CS_CONFIG_REG_SPI_CS_SELECT_Pos (0UL) /*!< SPI_CS_SELECT (Bit 0) */ + #define SPI2_SPI2_CS_CONFIG_REG_SPI_CS_SELECT_Msk (0x7UL) /*!< SPI_CS_SELECT (Bitfield-Mask: 0x07) */ +/* ===================================================== SPI2_CTRL_REG ===================================================== */ + #define SPI2_SPI2_CTRL_REG_SPI_SWAP_BYTES_Pos (7UL) /*!< SPI_SWAP_BYTES (Bit 7) */ + #define SPI2_SPI2_CTRL_REG_SPI_SWAP_BYTES_Msk (0x80UL) /*!< SPI_SWAP_BYTES (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos (6UL) /*!< SPI_CAPTURE_AT_NEXT_EDGE (Bit 6) */ + #define SPI2_SPI2_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk (0x40UL) /*!< SPI_CAPTURE_AT_NEXT_EDGE (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_FIFO_RESET_Pos (5UL) /*!< SPI_FIFO_RESET (Bit 5) */ + #define SPI2_SPI2_CTRL_REG_SPI_FIFO_RESET_Msk (0x20UL) /*!< SPI_FIFO_RESET (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_DMA_RX_EN_Pos (4UL) /*!< SPI_DMA_RX_EN (Bit 4) */ + #define SPI2_SPI2_CTRL_REG_SPI_DMA_RX_EN_Msk (0x10UL) /*!< SPI_DMA_RX_EN (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_DMA_TX_EN_Pos (3UL) /*!< SPI_DMA_TX_EN (Bit 3) */ + #define SPI2_SPI2_CTRL_REG_SPI_DMA_TX_EN_Msk (0x8UL) /*!< SPI_DMA_TX_EN (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_RX_EN_Pos (2UL) /*!< SPI_RX_EN (Bit 2) */ + #define SPI2_SPI2_CTRL_REG_SPI_RX_EN_Msk (0x4UL) /*!< SPI_RX_EN (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_TX_EN_Pos (1UL) /*!< SPI_TX_EN (Bit 1) */ + #define SPI2_SPI2_CTRL_REG_SPI_TX_EN_Msk (0x2UL) /*!< SPI_TX_EN (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_CTRL_REG_SPI_EN_Pos (0UL) /*!< SPI_EN (Bit 0) */ + #define SPI2_SPI2_CTRL_REG_SPI_EN_Msk (0x1UL) /*!< SPI_EN (Bitfield-Mask: 0x01) */ +/* ================================================= SPI2_FIFO_CONFIG_REG ================================================== */ + #define SPI2_SPI2_FIFO_CONFIG_REG_SPI_RX_TL_Pos (8UL) /*!< SPI_RX_TL (Bit 8) */ + #define SPI2_SPI2_FIFO_CONFIG_REG_SPI_RX_TL_Msk (0xff00UL) /*!< SPI_RX_TL (Bitfield-Mask: 0xff) */ + #define SPI2_SPI2_FIFO_CONFIG_REG_SPI_TX_TL_Pos (0UL) /*!< SPI_TX_TL (Bit 0) */ + #define SPI2_SPI2_FIFO_CONFIG_REG_SPI_TX_TL_Msk (0xffUL) /*!< SPI_TX_TL (Bitfield-Mask: 0xff) */ +/* ================================================== SPI2_FIFO_READ_REG =================================================== */ + #define SPI2_SPI2_FIFO_READ_REG_SPI_FIFO_READ_Pos (0UL) /*!< SPI_FIFO_READ (Bit 0) */ + #define SPI2_SPI2_FIFO_READ_REG_SPI_FIFO_READ_Msk (0xffffffffUL) /*!< SPI_FIFO_READ (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SPI2_FIFO_STATUS_REG ================================================== */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos (15UL) /*!< SPI_TRANSACTION_ACTIVE (Bit 15) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk (0x8000UL) /*!< SPI_TRANSACTION_ACTIVE (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos (14UL) /*!< SPI_RX_FIFO_OVFL (Bit 14) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk (0x4000UL) /*!< SPI_RX_FIFO_OVFL (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos (13UL) /*!< SPI_STATUS_TX_FULL (Bit 13) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk (0x2000UL) /*!< SPI_STATUS_TX_FULL (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos (12UL) /*!< SPI_STATUS_RX_EMPTY (Bit 12) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk (0x1000UL) /*!< SPI_STATUS_RX_EMPTY (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos (6UL) /*!< SPI_TX_FIFO_LEVEL (Bit 6) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk (0xfc0UL) /*!< SPI_TX_FIFO_LEVEL (Bitfield-Mask: 0x3f) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos (0UL) /*!< SPI_RX_FIFO_LEVEL (Bit 0) */ + #define SPI2_SPI2_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk (0x3fUL) /*!< SPI_RX_FIFO_LEVEL (Bitfield-Mask: 0x3f) */ +/* ================================================== SPI2_FIFO_WRITE_REG ================================================== */ + #define SPI2_SPI2_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos (0UL) /*!< SPI_FIFO_WRITE (Bit 0) */ + #define SPI2_SPI2_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk (0xffffffffUL) /*!< SPI_FIFO_WRITE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SPI2_IRQ_MASK_REG =================================================== */ + #define SPI2_SPI2_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos (1UL) /*!< SPI_IRQ_MASK_RX_FULL (Bit 1) */ + #define SPI2_SPI2_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk (0x2UL) /*!< SPI_IRQ_MASK_RX_FULL (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos (0UL) /*!< SPI_IRQ_MASK_TX_EMPTY (Bit 0) */ + #define SPI2_SPI2_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk (0x1UL) /*!< SPI_IRQ_MASK_TX_EMPTY (Bitfield-Mask: 0x01) */ +/* ==================================================== SPI2_STATUS_REG ==================================================== */ + #define SPI2_SPI2_STATUS_REG_SPI_STATUS_RX_FULL_Pos (1UL) /*!< SPI_STATUS_RX_FULL (Bit 1) */ + #define SPI2_SPI2_STATUS_REG_SPI_STATUS_RX_FULL_Msk (0x2UL) /*!< SPI_STATUS_RX_FULL (Bitfield-Mask: 0x01) */ + #define SPI2_SPI2_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos (0UL) /*!< SPI_STATUS_TX_EMPTY (Bit 0) */ + #define SPI2_SPI2_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk (0x1UL) /*!< SPI_STATUS_TX_EMPTY (Bitfield-Mask: 0x01) */ +/* ================================================ SPI2_TXBUFFER_FORCE_REG ================================================ */ + #define SPI2_SPI2_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos (0UL) /*!< SPI_TXBUFFER_FORCE (Bit 0) */ + #define SPI2_SPI2_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk (0xffffffffUL) /*!< SPI_TXBUFFER_FORCE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ SRC_FIFO_IF ================ */ +/* =========================================================================================================================== */ + +/* ================================================= APU_DAI_FIFO_IN1_REG ================================================== */ + #define SRC_FIFO_IF_APU_DAI_FIFO_IN1_REG_DAI_IN_Pos (0UL) /*!< DAI_IN (Bit 0) */ + #define SRC_FIFO_IF_APU_DAI_FIFO_IN1_REG_DAI_IN_Msk (0xffffffffUL) /*!< DAI_IN (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_DAI_FIFO_IN2_REG ================================================== */ + #define SRC_FIFO_IF_APU_DAI_FIFO_IN2_REG_DAI_IN_Pos (0UL) /*!< DAI_IN (Bit 0) */ + #define SRC_FIFO_IF_APU_DAI_FIFO_IN2_REG_DAI_IN_Msk (0xffffffffUL) /*!< DAI_IN (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_DAI_FIFO_OUT1_REG ================================================= */ + #define SRC_FIFO_IF_APU_DAI_FIFO_OUT1_REG_DAI_OUT_Pos (0UL) /*!< DAI_OUT (Bit 0) */ + #define SRC_FIFO_IF_APU_DAI_FIFO_OUT1_REG_DAI_OUT_Msk (0xffffffffUL) /*!< DAI_OUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_DAI_FIFO_OUT2_REG ================================================= */ + #define SRC_FIFO_IF_APU_DAI_FIFO_OUT2_REG_DAI_OUT_Pos (0UL) /*!< DAI_OUT (Bit 0) */ + #define SRC_FIFO_IF_APU_DAI_FIFO_OUT2_REG_DAI_OUT_Msk (0xffffffffUL) /*!< DAI_OUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== APU_FIFO_STATUS_REG ================================================== */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_IN_FULL_Pos (23UL) /*!< DAI_CH2_IN_FULL (Bit 23) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_IN_FULL_Msk (0x800000UL) /*!< DAI_CH2_IN_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_IN_EMPTY_Pos (22UL) /*!< DAI_CH2_IN_EMPTY (Bit 22) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_IN_EMPTY_Msk (0x400000UL) /*!< DAI_CH2_IN_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_OUT_FULL_Pos (21UL) /*!< DAI_CH2_OUT_FULL (Bit 21) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_OUT_FULL_Msk (0x200000UL) /*!< DAI_CH2_OUT_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_OUT_EMPTY_Pos (20UL) /*!< DAI_CH2_OUT_EMPTY (Bit 20) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH2_OUT_EMPTY_Msk (0x100000UL) /*!< DAI_CH2_OUT_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_IN_FULL_Pos (19UL) /*!< DAI_CH1_IN_FULL (Bit 19) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_IN_FULL_Msk (0x80000UL) /*!< DAI_CH1_IN_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_IN_EMPTY_Pos (18UL) /*!< DAI_CH1_IN_EMPTY (Bit 18) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_IN_EMPTY_Msk (0x40000UL) /*!< DAI_CH1_IN_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_OUT_FULL_Pos (17UL) /*!< DAI_CH1_OUT_FULL (Bit 17) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_OUT_FULL_Msk (0x20000UL) /*!< DAI_CH1_OUT_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_OUT_EMPTY_Pos (16UL) /*!< DAI_CH1_OUT_EMPTY (Bit 16) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_DAI_CH1_OUT_EMPTY_Msk (0x10000UL) /*!< DAI_CH1_OUT_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_OUT_FULL_Pos (7UL) /*!< SRC_CH2_OUT_FULL (Bit 7) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_OUT_FULL_Msk (0x80UL) /*!< SRC_CH2_OUT_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_OUT_EMPTY_Pos (6UL) /*!< SRC_CH2_OUT_EMPTY (Bit 6) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_OUT_EMPTY_Msk (0x40UL) /*!< SRC_CH2_OUT_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_IN_FULL_Pos (5UL) /*!< SRC_CH2_IN_FULL (Bit 5) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_IN_FULL_Msk (0x20UL) /*!< SRC_CH2_IN_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_IN_EMPTY_Pos (4UL) /*!< SRC_CH2_IN_EMPTY (Bit 4) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH2_IN_EMPTY_Msk (0x10UL) /*!< SRC_CH2_IN_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_OUT_FULL_Pos (3UL) /*!< SRC_CH1_OUT_FULL (Bit 3) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_OUT_FULL_Msk (0x8UL) /*!< SRC_CH1_OUT_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_OUT_EMPTY_Pos (2UL) /*!< SRC_CH1_OUT_EMPTY (Bit 2) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_OUT_EMPTY_Msk (0x4UL) /*!< SRC_CH1_OUT_EMPTY (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_IN_FULL_Pos (1UL) /*!< SRC_CH1_IN_FULL (Bit 1) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_IN_FULL_Msk (0x2UL) /*!< SRC_CH1_IN_FULL (Bitfield-Mask: 0x01) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_IN_EMPTY_Pos (0UL) /*!< SRC_CH1_IN_EMPTY (Bit 0) */ + #define SRC_FIFO_IF_APU_FIFO_STATUS_REG_SRC_CH1_IN_EMPTY_Msk (0x1UL) /*!< SRC_CH1_IN_EMPTY (Bitfield-Mask: 0x01) */ +/* ================================================= APU_SRC_FIFO_IN1_REG ================================================== */ + #define SRC_FIFO_IF_APU_SRC_FIFO_IN1_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ + #define SRC_FIFO_IF_APU_SRC_FIFO_IN1_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_SRC_FIFO_IN2_REG ================================================== */ + #define SRC_FIFO_IF_APU_SRC_FIFO_IN2_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ + #define SRC_FIFO_IF_APU_SRC_FIFO_IN2_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_SRC_FIFO_OUT1_REG ================================================= */ + #define SRC_FIFO_IF_APU_SRC_FIFO_OUT1_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ + #define SRC_FIFO_IF_APU_SRC_FIFO_OUT1_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= APU_SRC_FIFO_OUT2_REG ================================================= */ + #define SRC_FIFO_IF_APU_SRC_FIFO_OUT2_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ + #define SRC_FIFO_IF_APU_SRC_FIFO_OUT2_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ SRC_IF ================ */ +/* =========================================================================================================================== */ + +/* ================================================= APU_DAI_FIFO_CTRL_REG ================================================= */ + #define SRC_IF_APU_DAI_FIFO_CTRL_REG_FIFO_CTRL_Pos (0UL) /*!< FIFO_CTRL (Bit 0) */ + #define SRC_IF_APU_DAI_FIFO_CTRL_REG_FIFO_CTRL_Msk (0xffffffffUL) /*!< FIFO_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ APU_SRC_COEF0A_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL) /*!< SRC_COEF10 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL) /*!< SRC_COEF10 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF0A_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF0A_SET2_REG_SRC_COEF10_Pos (0UL) /*!< SRC_COEF10 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF0A_SET2_REG_SRC_COEF10_Msk (0xffffUL) /*!< SRC_COEF10 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF10_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF10_SET1_REG_SRC_COEF1_Pos (16UL) /*!< SRC_COEF1 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL) /*!< SRC_COEF1 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF10_SET1_REG_SRC_COEF0_Pos (0UL) /*!< SRC_COEF0 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL) /*!< SRC_COEF0 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF10_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF10_SET2_REG_SRC_COEF1_Pos (16UL) /*!< SRC_COEF1 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF10_SET2_REG_SRC_COEF1_Msk (0xffff0000UL) /*!< SRC_COEF1 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF10_SET2_REG_SRC_COEF0_Pos (0UL) /*!< SRC_COEF0 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF10_SET2_REG_SRC_COEF0_Msk (0xffffUL) /*!< SRC_COEF0 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF32_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF32_SET1_REG_SRC_COEF3_Pos (16UL) /*!< SRC_COEF3 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL) /*!< SRC_COEF3 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF32_SET1_REG_SRC_COEF2_Pos (0UL) /*!< SRC_COEF2 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL) /*!< SRC_COEF2 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF32_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF32_SET2_REG_SRC_COEF3_Pos (16UL) /*!< SRC_COEF3 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF32_SET2_REG_SRC_COEF3_Msk (0xffff0000UL) /*!< SRC_COEF3 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF32_SET2_REG_SRC_COEF2_Pos (0UL) /*!< SRC_COEF2 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF32_SET2_REG_SRC_COEF2_Msk (0xffffUL) /*!< SRC_COEF2 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF54_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF54_SET1_REG_SRC_COEF5_Pos (16UL) /*!< SRC_COEF5 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL) /*!< SRC_COEF5 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF54_SET1_REG_SRC_COEF4_Pos (0UL) /*!< SRC_COEF4 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL) /*!< SRC_COEF4 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF54_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF54_SET2_REG_SRC_COEF5_Pos (16UL) /*!< SRC_COEF5 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF54_SET2_REG_SRC_COEF5_Msk (0xffff0000UL) /*!< SRC_COEF5 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF54_SET2_REG_SRC_COEF4_Pos (0UL) /*!< SRC_COEF4 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF54_SET2_REG_SRC_COEF4_Msk (0xffffUL) /*!< SRC_COEF4 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF76_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF76_SET1_REG_SRC_COEF7_Pos (16UL) /*!< SRC_COEF7 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL) /*!< SRC_COEF7 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF76_SET1_REG_SRC_COEF6_Pos (0UL) /*!< SRC_COEF6 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL) /*!< SRC_COEF6 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF76_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF76_SET2_REG_SRC_COEF7_Pos (16UL) /*!< SRC_COEF7 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF76_SET2_REG_SRC_COEF7_Msk (0xffff0000UL) /*!< SRC_COEF7 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF76_SET2_REG_SRC_COEF6_Pos (0UL) /*!< SRC_COEF6 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF76_SET2_REG_SRC_COEF6_Msk (0xffffUL) /*!< SRC_COEF6 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF98_SET1_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF98_SET1_REG_SRC_COEF9_Pos (16UL) /*!< SRC_COEF9 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL) /*!< SRC_COEF9 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF98_SET1_REG_SRC_COEF8_Pos (0UL) /*!< SRC_COEF8 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL) /*!< SRC_COEF8 (Bitfield-Mask: 0xffff) */ +/* ================================================ APU_SRC_COEF98_SET2_REG ================================================ */ + #define SRC_IF_APU_SRC_COEF98_SET2_REG_SRC_COEF9_Pos (16UL) /*!< SRC_COEF9 (Bit 16) */ + #define SRC_IF_APU_SRC_COEF98_SET2_REG_SRC_COEF9_Msk (0xffff0000UL) /*!< SRC_COEF9 (Bitfield-Mask: 0xffff) */ + #define SRC_IF_APU_SRC_COEF98_SET2_REG_SRC_COEF8_Pos (0UL) /*!< SRC_COEF8 (Bit 0) */ + #define SRC_IF_APU_SRC_COEF98_SET2_REG_SRC_COEF8_Msk (0xffffUL) /*!< SRC_COEF8 (Bitfield-Mask: 0xffff) */ +/* =================================================== APU_SRC_CTRL_REG ==================================================== */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_COEF_SET_Pos (30UL) /*!< SRC_IN_COEF_SET (Bit 30) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_COEF_SET_Msk (0x40000000UL) /*!< SRC_IN_COEF_SET (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_OUT2_ENABLE_Pos (27UL) /*!< SRC_FIFO_OUT2_ENABLE (Bit 27) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_OUT2_ENABLE_Msk (0x8000000UL) /*!< SRC_FIFO_OUT2_ENABLE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_OUT1_ENABLE_Pos (26UL) /*!< SRC_FIFO_OUT1_ENABLE (Bit 26) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_OUT1_ENABLE_Msk (0x4000000UL) /*!< SRC_FIFO_OUT1_ENABLE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL) /*!< SRC_OUT_FLOWCLR (Bit 25) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL) /*!< SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL) /*!< SRC_IN_FLOWCLR (Bit 24) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL) /*!< SRC_IN_FLOWCLR (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL) /*!< SRC_OUT_UNFLOW (Bit 23) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL) /*!< SRC_OUT_UNFLOW (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL) /*!< SRC_OUT_OVFLOW (Bit 22) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL) /*!< SRC_OUT_OVFLOW (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL) /*!< SRC_IN_UNFLOW (Bit 21) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL) /*!< SRC_IN_UNFLOW (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL) /*!< SRC_IN_OVFLOW (Bit 20) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL) /*!< SRC_IN_OVFLOW (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_RESYNC_Pos (19UL) /*!< SRC_RESYNC (Bit 19) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_RESYNC_Msk (0x80000UL) /*!< SRC_RESYNC (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_OK_Pos (18UL) /*!< SRC_OUT_OK (Bit 18) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL) /*!< SRC_OUT_OK (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_US_Pos (16UL) /*!< SRC_OUT_US (Bit 16) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_US_Msk (0x30000UL) /*!< SRC_OUT_US (Bitfield-Mask: 0x03) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_SET_Pos (15UL) /*!< SRC_OUT_SET (Bit 15) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_SET_Msk (0x8000UL) /*!< SRC_OUT_SET (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL) /*!< SRC_OUT_CAL_BYPASS (Bit 14) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL) /*!< SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_AMODE_Pos (13UL) /*!< SRC_OUT_AMODE (Bit 13) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL) /*!< SRC_OUT_AMODE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PDM_EN_Pos (12UL) /*!< SRC_PDM_EN (Bit 12) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PDM_EN_Msk (0x1000UL) /*!< SRC_PDM_EN (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_IN2_ENABLE_Pos (11UL) /*!< SRC_FIFO_IN2_ENABLE (Bit 11) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_IN2_ENABLE_Msk (0x800UL) /*!< SRC_FIFO_IN2_ENABLE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_IN1_ENABLE_Pos (10UL) /*!< SRC_FIFO_IN1_ENABLE (Bit 10) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_FIFO_IN1_ENABLE_Msk (0x400UL) /*!< SRC_FIFO_IN1_ENABLE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PCM_GAIN_Pos (8UL) /*!< SRC_PCM_GAIN (Bit 8) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PCM_GAIN_Msk (0x300UL) /*!< SRC_PCM_GAIN (Bitfield-Mask: 0x03) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL) /*!< SRC_DITHER_DISABLE (Bit 7) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL) /*!< SRC_DITHER_DISABLE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_OK_Pos (6UL) /*!< SRC_IN_OK (Bit 6) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_OK_Msk (0x40UL) /*!< SRC_IN_OK (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_DS_Pos (4UL) /*!< SRC_IN_DS (Bit 4) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_DS_Msk (0x30UL) /*!< SRC_IN_DS (Bitfield-Mask: 0x03) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL) /*!< SRC_PDM_IN_INV (Bit 3) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL) /*!< SRC_PDM_IN_INV (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL) /*!< SRC_IN_CAL_BYPASS (Bit 2) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL) /*!< SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_AMODE_Pos (1UL) /*!< SRC_IN_AMODE (Bit 1) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL) /*!< SRC_IN_AMODE (Bitfield-Mask: 0x01) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_EN_Pos (0UL) /*!< SRC_EN (Bit 0) */ + #define SRC_IF_APU_SRC_CTRL_REG_SRC_EN_Msk (0x1UL) /*!< SRC_EN (Bitfield-Mask: 0x01) */ +/* ================================================= APU_SRC_FIFO_CTRL_REG ================================================= */ + #define SRC_IF_APU_SRC_FIFO_CTRL_REG_FIFO_CTRL_Pos (0UL) /*!< FIFO_CTRL (Bit 0) */ + #define SRC_IF_APU_SRC_FIFO_CTRL_REG_FIFO_CTRL_Msk (0xffffffffUL) /*!< FIFO_CTRL (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== APU_SRC_IN1_REG ==================================================== */ + #define SRC_IF_APU_SRC_IN1_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ + #define SRC_IF_APU_SRC_IN1_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== APU_SRC_IN2_REG ==================================================== */ + #define SRC_IF_APU_SRC_IN2_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ + #define SRC_IF_APU_SRC_IN2_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* =================================================== APU_SRC_IN_FS_REG =================================================== */ + #define SRC_IF_APU_SRC_IN_FS_REG_SRC_IN_FS_Pos (0UL) /*!< SRC_IN_FS (Bit 0) */ + #define SRC_IF_APU_SRC_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL) /*!< SRC_IN_FS (Bitfield-Mask: 0xffffff) */ +/* =================================================== APU_SRC_OUT1_REG ==================================================== */ + #define SRC_IF_APU_SRC_OUT1_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ + #define SRC_IF_APU_SRC_OUT1_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== APU_SRC_OUT2_REG ==================================================== */ + #define SRC_IF_APU_SRC_OUT2_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ + #define SRC_IF_APU_SRC_OUT2_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== APU_SRC_OUT_FS_REG =================================================== */ + #define SRC_IF_APU_SRC_OUT_FS_REG_SRC_OUT_FS_Pos (0UL) /*!< SRC_OUT_FS (Bit 0) */ + #define SRC_IF_APU_SRC_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL) /*!< SRC_OUT_FS (Bitfield-Mask: 0xffffff) */ + +/* =========================================================================================================================== */ +/* ================ SYS_WDOG ================ */ +/* =========================================================================================================================== */ + +/* =================================================== WATCHDOG_CTRL_REG =================================================== */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL) /*!< WRITE_BUSY (Bit 3) */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL) /*!< WRITE_BUSY (Bitfield-Mask: 0x01) */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL) /*!< WDOG_FREEZE_EN (Bit 2) */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL) /*!< WDOG_FREEZE_EN (Bitfield-Mask: 0x01) */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL) /*!< NMI_RST (Bit 0) */ + #define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL) /*!< NMI_RST (Bitfield-Mask: 0x01) */ +/* ===================================================== WATCHDOG_REG ====================================================== */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL) /*!< WDOG_WEN (Bit 14) */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL) /*!< WDOG_WEN (Bitfield-Mask: 0x3ffff) */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL) /*!< WDOG_VAL_NEG (Bit 13) */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL) /*!< WDOG_VAL_NEG (Bitfield-Mask: 0x01) */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL) /*!< WDOG_VAL (Bit 0) */ + #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL) /*!< WDOG_VAL (Bitfield-Mask: 0x1fff) */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS ================ */ +/* =========================================================================================================================== */ + +/* =================================================== AHB_DMA_CCLM1_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM2_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM3_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM4_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM5_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM5_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM5_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM6_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM6_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM6_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM7_REG =================================================== */ + #define SYSBUS_AHB_DMA_CCLM7_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ + #define SYSBUS_AHB_DMA_CCLM7_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* ================================================ AHB_DMA_DFLT_MASTER_REG ================================================ */ + #define SYSBUS_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL) /*!< AHB_DMA_DFLT_MASTER (Bit 0) */ + #define SYSBUS_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL) /*!< AHB_DMA_DFLT_MASTER (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL1_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL) /*!< AHB_DMA_PL1 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL) /*!< AHB_DMA_PL1 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL2_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL) /*!< AHB_DMA_PL2 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL) /*!< AHB_DMA_PL2 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL3_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL) /*!< AHB_DMA_PL3 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL) /*!< AHB_DMA_PL3 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL4_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL) /*!< AHB_DMA_PL4 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL) /*!< AHB_DMA_PL4 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL5_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL5_REG_AHB_DMA_PL5_Pos (0UL) /*!< AHB_DMA_PL5 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL5_REG_AHB_DMA_PL5_Msk (0xfUL) /*!< AHB_DMA_PL5 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL6_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL6_REG_AHB_DMA_PL6_Pos (0UL) /*!< AHB_DMA_PL6 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL6_REG_AHB_DMA_PL6_Msk (0xfUL) /*!< AHB_DMA_PL6 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL7_REG ==================================================== */ + #define SYSBUS_AHB_DMA_PL7_REG_AHB_DMA_PL7_Pos (0UL) /*!< AHB_DMA_PL7 (Bit 0) */ + #define SYSBUS_AHB_DMA_PL7_REG_AHB_DMA_PL7_Msk (0xfUL) /*!< AHB_DMA_PL7 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_TCL_REG ==================================================== */ + #define SYSBUS_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL) /*!< AHB_DMA_TCL (Bit 0) */ + #define SYSBUS_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL) /*!< AHB_DMA_TCL (Bitfield-Mask: 0xffff) */ +/* ================================================== AHB_DMA_VERSION_REG ================================================== */ + #define SYSBUS_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL) /*!< AHB_DMA_VERSION (Bit 0) */ + #define SYSBUS_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL) /*!< AHB_DMA_VERSION (Bitfield-Mask: 0xffffffff) */ +/* =================================================== AHB_DMA_WTEN_REG ==================================================== */ + #define SYSBUS_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL) /*!< AHB_DMA_WTEN (Bit 0) */ + #define SYSBUS_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL) /*!< AHB_DMA_WTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS_ICM ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== AHBSYS_ARB_REG ===================================================== */ + #define SYSBUS_ICM_AHBSYS_ARB_REG_AHBSYS_AHB_CPUS_PRIO_Pos (1UL) /*!< AHBSYS_AHB_CPUS_PRIO (Bit 1) */ + #define SYSBUS_ICM_AHBSYS_ARB_REG_AHBSYS_AHB_CPUS_PRIO_Msk (0x2UL) /*!< AHBSYS_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ + #define SYSBUS_ICM_AHBSYS_ARB_REG_AHBSYS_AHB_DMA_PRIO_Pos (0UL) /*!< AHBSYS_AHB_DMA_PRIO (Bit 0) */ + #define SYSBUS_ICM_AHBSYS_ARB_REG_AHBSYS_AHB_DMA_PRIO_Msk (0x1UL) /*!< AHBSYS_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ +/* ====================================================== OTP_ARB_REG ====================================================== */ + #define SYSBUS_ICM_OTP_ARB_REG_OTP_AHB_DMA_PRIO_Pos (1UL) /*!< OTP_AHB_DMA_PRIO (Bit 1) */ + #define SYSBUS_ICM_OTP_ARB_REG_OTP_AHB_DMA_PRIO_Msk (0x2UL) /*!< OTP_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ + #define SYSBUS_ICM_OTP_ARB_REG_OTP_AHB_CPUS_PRIO_Pos (0UL) /*!< OTP_AHB_CPUS_PRIO (Bit 0) */ + #define SYSBUS_ICM_OTP_ARB_REG_OTP_AHB_CPUS_PRIO_Msk (0x1UL) /*!< OTP_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ +/* ==================================================== QSPIRAM_ARB_REG ==================================================== */ + #define SYSBUS_ICM_QSPIRAM_ARB_REG_QSPIRAM_AHB_CPUS_PRIO_Pos (1UL) /*!< QSPIRAM_AHB_CPUS_PRIO (Bit 1) */ + #define SYSBUS_ICM_QSPIRAM_ARB_REG_QSPIRAM_AHB_CPUS_PRIO_Msk (0x2UL) /*!< QSPIRAM_AHB_CPUS_PRIO (Bitfield-Mask: 0x01) */ + #define SYSBUS_ICM_QSPIRAM_ARB_REG_QSPIRAM_AHB_DMA_PRIO_Pos (0UL) /*!< QSPIRAM_AHB_DMA_PRIO (Bit 0) */ + #define SYSBUS_ICM_QSPIRAM_ARB_REG_QSPIRAM_AHB_DMA_PRIO_Msk (0x1UL) /*!< QSPIRAM_AHB_DMA_PRIO (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TDES ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CBC_IV_0_REG ====================================================== */ + #define TDES_CBC_IV_0_REG_CBC_IV_0_Pos (0UL) /*!< CBC_IV_0 (Bit 0) */ + #define TDES_CBC_IV_0_REG_CBC_IV_0_Msk (0xffffffffUL) /*!< CBC_IV_0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CBC_IV_1_REG ====================================================== */ + #define TDES_CBC_IV_1_REG_CBC_IV_1_Pos (0UL) /*!< CBC_IV_1 (Bit 0) */ + #define TDES_CBC_IV_1_REG_CBC_IV_1_Msk (0xffffffffUL) /*!< CBC_IV_1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDES_CBC_CTRL_REG =================================================== */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_DONE_Pos (24UL) /*!< TDES_CBC_DONE (Bit 24) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_DONE_Msk (0x1000000UL) /*!< TDES_CBC_DONE (Bitfield-Mask: 0x01) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_FIRST_Pos (16UL) /*!< TDES_CBC_FIRST (Bit 16) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_FIRST_Msk (0x10000UL) /*!< TDES_CBC_FIRST (Bitfield-Mask: 0x01) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_START_Pos (8UL) /*!< TDES_CBC_START (Bit 8) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_START_Msk (0x100UL) /*!< TDES_CBC_START (Bitfield-Mask: 0x01) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_IRQ_EN_Pos (1UL) /*!< TDES_CBC_IRQ_EN (Bit 1) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_IRQ_EN_Msk (0x2UL) /*!< TDES_CBC_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_ED_SEL_Pos (0UL) /*!< TDES_CBC_ED_SEL (Bit 0) */ + #define TDES_TDES_CBC_CTRL_REG_TDES_CBC_ED_SEL_Msk (0x1UL) /*!< TDES_CBC_ED_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== TDES_INPUT_0_REG ==================================================== */ + #define TDES_TDES_INPUT_0_REG_TDES_INPUT_0_Pos (0UL) /*!< TDES_INPUT_0 (Bit 0) */ + #define TDES_TDES_INPUT_0_REG_TDES_INPUT_0_Msk (0xffffffffUL) /*!< TDES_INPUT_0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDES_INPUT_1_REG ==================================================== */ + #define TDES_TDES_INPUT_1_REG_TDES_INPUT_1_Pos (0UL) /*!< TDES_INPUT_1 (Bit 0) */ + #define TDES_TDES_INPUT_1_REG_TDES_INPUT_1_Msk (0xffffffffUL) /*!< TDES_INPUT_1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY1_0_REG ==================================================== */ + #define TDES_TDES_KEY1_0_REG_TDES_KEY1_0_Pos (0UL) /*!< TDES_KEY1_0 (Bit 0) */ + #define TDES_TDES_KEY1_0_REG_TDES_KEY1_0_Msk (0xffffffffUL) /*!< TDES_KEY1_0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY1_1_REG ==================================================== */ + #define TDES_TDES_KEY1_1_REG_TDES_KEY1_1_Pos (0UL) /*!< TDES_KEY1_1 (Bit 0) */ + #define TDES_TDES_KEY1_1_REG_TDES_KEY1_1_Msk (0xffffffffUL) /*!< TDES_KEY1_1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY2_0_REG ==================================================== */ + #define TDES_TDES_KEY2_0_REG_TDES_KEY2_0_Pos (0UL) /*!< TDES_KEY2_0 (Bit 0) */ + #define TDES_TDES_KEY2_0_REG_TDES_KEY2_0_Msk (0xffffffffUL) /*!< TDES_KEY2_0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY2_1_REG ==================================================== */ + #define TDES_TDES_KEY2_1_REG_TDES_KEY2_1_Pos (0UL) /*!< TDES_KEY2_1 (Bit 0) */ + #define TDES_TDES_KEY2_1_REG_TDES_KEY2_1_Msk (0xffffffffUL) /*!< TDES_KEY2_1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY3_0_REG ==================================================== */ + #define TDES_TDES_KEY3_0_REG_TDES_KEY3_0_Pos (0UL) /*!< TDES_KEY3_0 (Bit 0) */ + #define TDES_TDES_KEY3_0_REG_TDES_KEY3_0_Msk (0xffffffffUL) /*!< TDES_KEY3_0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TDES_KEY3_1_REG ==================================================== */ + #define TDES_TDES_KEY3_1_REG_TDES_KEY3_1_Pos (0UL) /*!< TDES_KEY3_1 (Bit 0) */ + #define TDES_TDES_KEY3_1_REG_TDES_KEY3_1_Msk (0xffffffffUL) /*!< TDES_KEY3_1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDES_OUTPUT_0_REG =================================================== */ + #define TDES_TDES_OUTPUT_0_REG_TDES_OUTPUT_0_Pos (0UL) /*!< TDES_OUTPUT_0 (Bit 0) */ + #define TDES_TDES_OUTPUT_0_REG_TDES_OUTPUT_0_Msk (0xffffffffUL) /*!< TDES_OUTPUT_0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDES_OUTPUT_1_REG =================================================== */ + #define TDES_TDES_OUTPUT_1_REG_TDES_OUTPUT_1_Pos (0UL) /*!< TDES_OUTPUT_1 (Bit 0) */ + #define TDES_TDES_OUTPUT_1_REG_TDES_OUTPUT_1_Msk (0xffffffffUL) /*!< TDES_OUTPUT_1 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +/* ================================================ TIMER_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO3_REG ================================================ */ + #define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO32_Pos (0UL) /*!< TIM_CAPTURE_GPIO32 (Bit 0) */ + #define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO32_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO4_REG ================================================ */ + #define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO42_Pos (0UL) /*!< TIM_CAPTURE_GPIO42 (Bit 0) */ + #define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO42_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO42 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER_CLEAR_GPIO_EVENT_REG =============================================== */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bit 3) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bit 2) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bit 1) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bit 0) */ + #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01) */ +/* =============================================== TIMER_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER_TIMER_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER_TIMER_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER_CLEAR_IRQ_REG ================================================== */ + #define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER_CTRL_REG ===================================================== */ + #define TIMER_TIMER_CTRL_REG_TIM_SINGLE_EVENT_CAPTURE_Pos (20UL) /*!< TIM_SINGLE_EVENT_CAPTURE (Bit 20) */ + #define TIMER_TIMER_CTRL_REG_TIM_SINGLE_EVENT_CAPTURE_Msk (0x100000UL) /*!< TIM_SINGLE_EVENT_CAPTURE (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER_TIMER_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER_TIMER_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_SWITCH_Pos (17UL) /*!< TIM_ONESHOT_SWITCH (Bit 17) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_SWITCH_Msk (0x20000UL) /*!< TIM_ONESHOT_SWITCH (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_TRIGGER_Pos (15UL) /*!< TIM_ONESHOT_TRIGGER (Bit 15) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_TRIGGER_Msk (0x18000UL) /*!< TIM_ONESHOT_TRIGGER (Bitfield-Mask: 0x03) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bit 14) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bit 13) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bit 12) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bit 11) */ + #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL) /*!< TIM_IN4_EVENT_FALL_EN (Bit 10) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL) /*!< TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL) /*!< TIM_IN3_EVENT_FALL_EN (Bit 9) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL) /*!< TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER_GPIO1_CONF_REG ================================================== */ + #define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO2_CONF_REG ================================================== */ + #define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO3_CONF_REG ================================================== */ + #define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL) /*!< TIM_GPIO3_CONF (Bit 0) */ + #define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL) /*!< TIM_GPIO3_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO4_CONF_REG ================================================== */ + #define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL) /*!< TIM_GPIO4_CONF (Bit 0) */ + #define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL) /*!< TIM_GPIO4_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER_ONESHOT_TRIGGER_REG =============================================== */ + #define TIMER_TIMER_ONESHOT_TRIGGER_REG_TIM_ONESHOT_TRIGGER_SW_Pos (0UL) /*!< TIM_ONESHOT_TRIGGER_SW (Bit 0) */ + #define TIMER_TIMER_ONESHOT_TRIGGER_REG_TIM_ONESHOT_TRIGGER_SW_Msk (0x1UL) /*!< TIM_ONESHOT_TRIGGER_SW (Bitfield-Mask: 0x01) */ +/* ================================================ TIMER_PRESCALER_VAL_REG ================================================ */ + #define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER_PRE_SETTINGS_REG ================================================= */ + #define TIMER_TIMER_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER_TIMER_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER_PULSE_CNT_CTRL_REG ================================================ */ + #define TIMER_TIMER_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER_TIMER_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER_PULSE_GPIO_SEL_REG ================================================ */ + #define TIMER_TIMER_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER_TIMER_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER_PWM_CTRL_REG =================================================== */ + #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER_PWM_SYNC_REG =================================================== */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER6_SYNC_Pos (6UL) /*!< TIMER6_SYNC (Bit 6) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER6_SYNC_Msk (0x40UL) /*!< TIMER6_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER4_SYNC_Pos (5UL) /*!< TIMER4_SYNC (Bit 5) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER4_SYNC_Msk (0x20UL) /*!< TIMER4_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER3_SYNC_Pos (4UL) /*!< TIMER3_SYNC (Bit 4) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER3_SYNC_Msk (0x10UL) /*!< TIMER3_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER2_SYNC_Pos (3UL) /*!< TIMER2_SYNC (Bit 3) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER2_SYNC_Msk (0x8UL) /*!< TIMER2_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER_SYNC_Pos (2UL) /*!< TIMER_SYNC (Bit 2) */ + #define TIMER_TIMER_PWM_SYNC_REG_TIMER_SYNC_Msk (0x4UL) /*!< TIMER_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_SYNC_ENABLE_Pos (1UL) /*!< SYNC_ENABLE (Bit 1) */ + #define TIMER_TIMER_PWM_SYNC_REG_SYNC_ENABLE_Msk (0x2UL) /*!< SYNC_ENABLE (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_PWM_SYNC_REG_PWM_START_Pos (0UL) /*!< PWM_START (Bit 0) */ + #define TIMER_TIMER_PWM_SYNC_REG_PWM_START_Msk (0x1UL) /*!< PWM_START (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER_SETTINGS_REG =================================================== */ + #define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TIMER_SHOTWIDTH_REG ================================================== */ + #define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER_STATUS_REG ==================================================== */ + #define TIMER_TIMER_STATUS_REG_TIM_CAPTIM_DETECTED_Pos (15UL) /*!< TIM_CAPTIM_DETECTED (Bit 15) */ + #define TIMER_TIMER_STATUS_REG_TIM_CAPTIM_DETECTED_Msk (0x8000UL) /*!< TIM_CAPTIM_DETECTED (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER_TIMER_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Pos (13UL) /*!< TIM_IN4_STATE (Bit 13) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Msk (0x2000UL) /*!< TIM_IN4_STATE (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Pos (12UL) /*!< TIM_IN3_STATE (Bit 12) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Msk (0x1000UL) /*!< TIM_IN3_STATE (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL) /*!< TIM_GPIO4_EVENT_PENDING (Bit 7) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL) /*!< TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL) /*!< TIM_GPIO3_EVENT_PENDING (Bit 6) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL) /*!< TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL) /*!< TIM_GPIO2_EVENT_PENDING (Bit 5) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL) /*!< TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL) /*!< TIM_GPIO1_EVENT_PENDING (Bit 4) */ + #define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL) /*!< TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER_TIMER_VAL_REG ================================================== */ + #define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ + #define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER2_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER2_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER2_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER2_TIMER2_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER2_TIMER2_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER2_CLEAR_IRQ_REG ================================================== */ + #define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER2_CTRL_REG ==================================================== */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER2_GPIO1_CONF_REG ================================================= */ + #define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER2_GPIO2_CONF_REG ================================================= */ + #define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER2_PRESCALER_VAL_REG ================================================ */ + #define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER2_PRE_SETTINGS_REG ================================================ */ + #define TIMER2_TIMER2_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER2_TIMER2_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER2_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER2_TIMER2_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER2_TIMER2_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER2_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER2_TIMER2_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER2_TIMER2_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER2_PWM_CTRL_REG ================================================== */ + #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER2_SETTINGS_REG ================================================== */ + #define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER2_SHOTWIDTH_REG ================================================== */ + #define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER2_STATUS_REG =================================================== */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER2_TIMER_VAL_REG ================================================== */ + #define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER3_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER3_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER3_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER3_TIMER3_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER3_TIMER3_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER3_CLEAR_IRQ_REG ================================================== */ + #define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER3_CTRL_REG ==================================================== */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER3_GPIO1_CONF_REG ================================================= */ + #define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER3_GPIO2_CONF_REG ================================================= */ + #define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER3_PRESCALER_VAL_REG ================================================ */ + #define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER3_PRE_SETTINGS_REG ================================================ */ + #define TIMER3_TIMER3_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER3_TIMER3_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER3_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER3_TIMER3_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER3_TIMER3_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER3_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER3_TIMER3_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER3_TIMER3_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER3_PWM_CTRL_REG ================================================== */ + #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER3_SETTINGS_REG ================================================== */ + #define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER3_SHOTWIDTH_REG ================================================== */ + #define TIMER3_TIMER3_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER3_TIMER3_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER3_STATUS_REG =================================================== */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER3_TIMER_VAL_REG ================================================== */ + #define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER4 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER4_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER4_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER4_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER4_TIMER4_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER4_TIMER4_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER4_CLEAR_IRQ_REG ================================================== */ + #define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER4_CTRL_REG ==================================================== */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER4_GPIO1_CONF_REG ================================================= */ + #define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER4_GPIO2_CONF_REG ================================================= */ + #define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER4_PRESCALER_VAL_REG ================================================ */ + #define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER4_PRE_SETTINGS_REG ================================================ */ + #define TIMER4_TIMER4_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER4_TIMER4_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER4_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER4_TIMER4_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER4_TIMER4_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER4_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER4_TIMER4_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER4_TIMER4_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER4_PWM_CTRL_REG ================================================== */ + #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER4_SETTINGS_REG ================================================== */ + #define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER4_SHOTWIDTH_REG ================================================== */ + #define TIMER4_TIMER4_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER4_TIMER4_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER4_STATUS_REG =================================================== */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER4_TIMER_VAL_REG ================================================== */ + #define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER5 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER5_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER5_TIMER5_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER5_TIMER5_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER5_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER5_TIMER5_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER5_TIMER5_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER5_CAPTURE_GPIO3_REG ================================================ */ + #define TIMER5_TIMER5_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO32_Pos (0UL) /*!< TIM_CAPTURE_GPIO32 (Bit 0) */ + #define TIMER5_TIMER5_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO32_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO32 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER5_CAPTURE_GPIO4_REG ================================================ */ + #define TIMER5_TIMER5_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO42_Pos (0UL) /*!< TIM_CAPTURE_GPIO42 (Bit 0) */ + #define TIMER5_TIMER5_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO42_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO42 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER5_CLEAR_GPIO_EVENT_REG ============================================== */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bit 3) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bit 2) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bit 1) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bit 0) */ + #define TIMER5_TIMER5_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01) */ +/* ============================================== TIMER5_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER5_TIMER5_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER5_TIMER5_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER5_CLEAR_IRQ_REG ================================================== */ + #define TIMER5_TIMER5_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER5_TIMER5_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER5_CTRL_REG ==================================================== */ + #define TIMER5_TIMER5_CTRL_REG_TIM_SINGLE_EVENT_CAPTURE_Pos (20UL) /*!< TIM_SINGLE_EVENT_CAPTURE (Bit 20) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_SINGLE_EVENT_CAPTURE_Msk (0x100000UL) /*!< TIM_SINGLE_EVENT_CAPTURE (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_SWITCH_Pos (17UL) /*!< TIM_ONESHOT_SWITCH (Bit 17) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_SWITCH_Msk (0x20000UL) /*!< TIM_ONESHOT_SWITCH (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_TRIGGER_Pos (15UL) /*!< TIM_ONESHOT_TRIGGER (Bit 15) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_TRIGGER_Msk (0x18000UL) /*!< TIM_ONESHOT_TRIGGER (Bitfield-Mask: 0x03) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bit 14) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bit 13) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bit 12) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bit 11) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL) /*!< TIM_IN4_EVENT_FALL_EN (Bit 10) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL) /*!< TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL) /*!< TIM_IN3_EVENT_FALL_EN (Bit 9) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL) /*!< TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER5_TIMER5_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER5_GPIO1_CONF_REG ================================================= */ + #define TIMER5_TIMER5_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER5_TIMER5_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER5_GPIO2_CONF_REG ================================================= */ + #define TIMER5_TIMER5_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER5_TIMER5_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER5_GPIO3_CONF_REG ================================================= */ + #define TIMER5_TIMER5_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL) /*!< TIM_GPIO3_CONF (Bit 0) */ + #define TIMER5_TIMER5_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL) /*!< TIM_GPIO3_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER5_GPIO4_CONF_REG ================================================= */ + #define TIMER5_TIMER5_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL) /*!< TIM_GPIO4_CONF (Bit 0) */ + #define TIMER5_TIMER5_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL) /*!< TIM_GPIO4_CONF (Bitfield-Mask: 0x3f) */ +/* ============================================== TIMER5_ONESHOT_TRIGGER_REG =============================================== */ + #define TIMER5_TIMER5_ONESHOT_TRIGGER_REG_TIM_ONESHOT_TRIGGER_SW_Pos (0UL) /*!< TIM_ONESHOT_TRIGGER_SW (Bit 0) */ + #define TIMER5_TIMER5_ONESHOT_TRIGGER_REG_TIM_ONESHOT_TRIGGER_SW_Msk (0x1UL) /*!< TIM_ONESHOT_TRIGGER_SW (Bitfield-Mask: 0x01) */ +/* =============================================== TIMER5_PRESCALER_VAL_REG ================================================ */ + #define TIMER5_TIMER5_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER5_TIMER5_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER5_PRE_SETTINGS_REG ================================================ */ + #define TIMER5_TIMER5_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER5_TIMER5_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER5_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER5_TIMER5_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER5_TIMER5_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER5_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER5_TIMER5_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER5_TIMER5_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER5_PWM_CTRL_REG ================================================== */ + #define TIMER5_TIMER5_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER5_TIMER5_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER5_TIMER5_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER5_TIMER5_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER5_PWM_SYNC_REG ================================================== */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER6_SYNC_Pos (6UL) /*!< TIMER6_SYNC (Bit 6) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER6_SYNC_Msk (0x40UL) /*!< TIMER6_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER4_SYNC_Pos (5UL) /*!< TIMER4_SYNC (Bit 5) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER4_SYNC_Msk (0x20UL) /*!< TIMER4_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER3_SYNC_Pos (4UL) /*!< TIMER3_SYNC (Bit 4) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER3_SYNC_Msk (0x10UL) /*!< TIMER3_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER2_SYNC_Pos (3UL) /*!< TIMER2_SYNC (Bit 3) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER2_SYNC_Msk (0x8UL) /*!< TIMER2_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER_SYNC_Pos (2UL) /*!< TIMER_SYNC (Bit 2) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_TIMER_SYNC_Msk (0x4UL) /*!< TIMER_SYNC (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_SYNC_ENABLE_Pos (1UL) /*!< SYNC_ENABLE (Bit 1) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_SYNC_ENABLE_Msk (0x2UL) /*!< SYNC_ENABLE (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_PWM_START_Pos (0UL) /*!< PWM_START (Bit 0) */ + #define TIMER5_TIMER5_PWM_SYNC_REG_PWM_START_Msk (0x1UL) /*!< PWM_START (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER5_SETTINGS_REG ================================================== */ + #define TIMER5_TIMER5_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER5_TIMER5_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER5_SHOTWIDTH_REG ================================================== */ + #define TIMER5_TIMER5_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER5_TIMER5_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER5_STATUS_REG =================================================== */ + #define TIMER5_TIMER5_STATUS_REG_TIM_CAPTIM_DETECTED_Pos (15UL) /*!< TIM_CAPTIM_DETECTED (Bit 15) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_CAPTIM_DETECTED_Msk (0x8000UL) /*!< TIM_CAPTIM_DETECTED (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN4_STATE_Pos (13UL) /*!< TIM_IN4_STATE (Bit 13) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN4_STATE_Msk (0x2000UL) /*!< TIM_IN4_STATE (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN3_STATE_Pos (12UL) /*!< TIM_IN3_STATE (Bit 12) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN3_STATE_Msk (0x1000UL) /*!< TIM_IN3_STATE (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL) /*!< TIM_GPIO4_EVENT_PENDING (Bit 7) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL) /*!< TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL) /*!< TIM_GPIO3_EVENT_PENDING (Bit 6) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL) /*!< TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL) /*!< TIM_GPIO2_EVENT_PENDING (Bit 5) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL) /*!< TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL) /*!< TIM_GPIO1_EVENT_PENDING (Bit 4) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL) /*!< TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER5_TIMER5_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER5_TIMER_VAL_REG ================================================== */ + #define TIMER5_TIMER5_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ + #define TIMER5_TIMER5_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER6 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER6_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER6_TIMER6_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER6_TIMER6_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER6_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER6_TIMER6_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER6_TIMER6_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER6_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER6_TIMER6_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER6_TIMER6_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER6_CLEAR_IRQ_REG ================================================== */ + #define TIMER6_TIMER6_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER6_TIMER6_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER6_CTRL_REG ==================================================== */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER6_TIMER6_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER6_GPIO1_CONF_REG ================================================= */ + #define TIMER6_TIMER6_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER6_TIMER6_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER6_GPIO2_CONF_REG ================================================= */ + #define TIMER6_TIMER6_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER6_TIMER6_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER6_PRESCALER_VAL_REG ================================================ */ + #define TIMER6_TIMER6_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER6_TIMER6_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER6_PRE_SETTINGS_REG ================================================ */ + #define TIMER6_TIMER6_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER6_TIMER6_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER6_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER6_TIMER6_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER6_TIMER6_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER6_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER6_TIMER6_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER6_TIMER6_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER6_PWM_CTRL_REG ================================================== */ + #define TIMER6_TIMER6_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER6_TIMER6_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER6_TIMER6_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER6_TIMER6_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER6_SETTINGS_REG ================================================== */ + #define TIMER6_TIMER6_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER6_TIMER6_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER6_SHOTWIDTH_REG ================================================== */ + #define TIMER6_TIMER6_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER6_TIMER6_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER6_STATUS_REG =================================================== */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER6_TIMER6_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER6_TIMER_VAL_REG ================================================== */ + #define TIMER6_TIMER6_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER6_TIMER6_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER7 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER7_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER7_TIMER7_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER7_TIMER7_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER7_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER7_TIMER7_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER7_TIMER7_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER7_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER7_TIMER7_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER7_TIMER7_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER7_CLEAR_IRQ_REG ================================================== */ + #define TIMER7_TIMER7_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER7_TIMER7_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER7_CTRL_REG ==================================================== */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER7_TIMER7_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER7_GPIO1_CONF_REG ================================================= */ + #define TIMER7_TIMER7_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER7_TIMER7_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER7_GPIO2_CONF_REG ================================================= */ + #define TIMER7_TIMER7_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER7_TIMER7_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER7_PRESCALER_VAL_REG ================================================ */ + #define TIMER7_TIMER7_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER7_TIMER7_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER7_PRE_SETTINGS_REG ================================================ */ + #define TIMER7_TIMER7_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER7_TIMER7_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER7_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER7_TIMER7_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER7_TIMER7_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER7_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER7_TIMER7_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER7_TIMER7_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER7_PWM_CTRL_REG ================================================== */ + #define TIMER7_TIMER7_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER7_TIMER7_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER7_TIMER7_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER7_TIMER7_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER7_SETTINGS_REG ================================================== */ + #define TIMER7_TIMER7_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER7_TIMER7_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER7_SHOTWIDTH_REG ================================================== */ + #define TIMER7_TIMER7_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER7_TIMER7_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER7_STATUS_REG =================================================== */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER7_TIMER7_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER7_TIMER_VAL_REG ================================================== */ + #define TIMER7_TIMER7_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER7_TIMER7_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ TIMER8 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER8_CAPTURE_GPIO1_REG ================================================ */ + #define TIMER8_TIMER8_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Pos (0UL) /*!< TIM_CAPTURE_GPIO12 (Bit 0) */ + #define TIMER8_TIMER8_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO12_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO12 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER8_CAPTURE_GPIO2_REG ================================================ */ + #define TIMER8_TIMER8_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Pos (0UL) /*!< TIM_CAPTURE_GPIO22 (Bit 0) */ + #define TIMER8_TIMER8_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO22_Msk (0xffffffffUL) /*!< TIM_CAPTURE_GPIO22 (Bitfield-Mask: 0xffffffff) */ +/* ============================================== TIMER8_CLEAR_IRQ_PULSE_REG =============================================== */ + #define TIMER8_TIMER8_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Pos (0UL) /*!< TIM_CLEAR_PULSE_IRQ (Bit 0) */ + #define TIMER8_TIMER8_CLEAR_IRQ_PULSE_REG_TIM_CLEAR_PULSE_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_PULSE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER8_CLEAR_IRQ_REG ================================================== */ + #define TIMER8_TIMER8_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ + #define TIMER8_TIMER8_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER8_CTRL_REG ==================================================== */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Pos (19UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bit 19) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EDGE_DET_CNT_FALL_EN_Msk (0x80000UL) /*!< TIM_EDGE_DET_CNT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EDGE_DET_CNT_EN_Pos (18UL) /*!< TIM_EDGE_DET_CNT_EN (Bit 18) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EDGE_DET_CNT_EN_Msk (0x40000UL) /*!< TIM_EDGE_DET_CNT_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ + #define TIMER8_TIMER8_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER8_GPIO1_CONF_REG ================================================= */ + #define TIMER8_TIMER8_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ + #define TIMER8_TIMER8_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER8_GPIO2_CONF_REG ================================================= */ + #define TIMER8_TIMER8_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ + #define TIMER8_TIMER8_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* =============================================== TIMER8_PRESCALER_VAL_REG ================================================ */ + #define TIMER8_TIMER8_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ + #define TIMER8_TIMER8_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER8_PRE_SETTINGS_REG ================================================ */ + #define TIMER8_TIMER8_PRE_SETTINGS_REG_TIM_PRESCALER2_Pos (0UL) /*!< TIM_PRESCALER2 (Bit 0) */ + #define TIMER8_TIMER8_PRE_SETTINGS_REG_TIM_PRESCALER2_Msk (0x1fUL) /*!< TIM_PRESCALER2 (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER8_PULSE_CNT_CTRL_REG =============================================== */ + #define TIMER8_TIMER8_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Pos (0UL) /*!< PULSE_CNT_THRESHOLD2 (Bit 0) */ + #define TIMER8_TIMER8_PULSE_CNT_CTRL_REG_PULSE_CNT_THRESHOLD2_Msk (0xffffffffUL) /*!< PULSE_CNT_THRESHOLD2 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== TIMER8_PULSE_GPIO_SEL_REG =============================================== */ + #define TIMER8_TIMER8_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Pos (0UL) /*!< PULSE_CNT_GPIO_SEL2 (Bit 0) */ + #define TIMER8_TIMER8_PULSE_GPIO_SEL_REG_PULSE_CNT_GPIO_SEL2_Msk (0x3fUL) /*!< PULSE_CNT_GPIO_SEL2 (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER8_PWM_CTRL_REG ================================================== */ + #define TIMER8_TIMER8_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL) /*!< TIM_PWM_DC (Bit 16) */ + #define TIMER8_TIMER8_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ + #define TIMER8_TIMER8_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ + #define TIMER8_TIMER8_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER8_SETTINGS_REG ================================================== */ + #define TIMER8_TIMER8_SETTINGS_REG_TIM_RELOAD2_Pos (0UL) /*!< TIM_RELOAD2 (Bit 0) */ + #define TIMER8_TIMER8_SETTINGS_REG_TIM_RELOAD2_Msk (0xffffffffUL) /*!< TIM_RELOAD2 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TIMER8_SHOTWIDTH_REG ================================================== */ + #define TIMER8_TIMER8_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Pos (0UL) /*!< TIM_SHOTWIDTH2 (Bit 0) */ + #define TIMER8_TIMER8_SHOTWIDTH_REG_TIM_SHOTWIDTH2_Msk (0xffffffffUL) /*!< TIM_SHOTWIDTH2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TIMER8_STATUS_REG =================================================== */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IRQ_PULSE_STATUS_Pos (14UL) /*!< TIM_IRQ_PULSE_STATUS (Bit 14) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk (0x4000UL) /*!< TIM_IRQ_PULSE_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bit 11) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL) /*!< TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_PWM_BUSY_Pos (10UL) /*!< TIM_PWM_BUSY (Bit 10) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL) /*!< TIM_PWM_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL) /*!< TIM_TIMER_BUSY (Bit 9) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL) /*!< TIM_TIMER_BUSY (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL) /*!< TIM_IRQ_STATUS (Bit 8) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL) /*!< TIM_IRQ_STATUS (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ + #define TIMER8_TIMER8_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER8_TIMER_VAL_REG ================================================== */ + #define TIMER8_TIMER8_TIMER_VAL_REG_TIM_TIMER_VALUE2_Pos (0UL) /*!< TIM_TIMER_VALUE2 (Bit 0) */ + #define TIMER8_TIMER8_TIMER_VAL_REG_TIM_TIMER_VALUE2_Msk (0xffffffffUL) /*!< TIM_TIMER_VALUE2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== UART_CR_REG ====================================================== */ + #define UART_UART_CR_REG_CTSEn_Pos (15UL) /*!< CTSEn (Bit 15) */ + #define UART_UART_CR_REG_CTSEn_Msk (0x8000UL) /*!< CTSEn (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_RTSEn_Pos (14UL) /*!< RTSEn (Bit 14) */ + #define UART_UART_CR_REG_RTSEn_Msk (0x4000UL) /*!< RTSEn (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_Out2_Pos (13UL) /*!< Out2 (Bit 13) */ + #define UART_UART_CR_REG_Out2_Msk (0x2000UL) /*!< Out2 (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_Out1_Pos (12UL) /*!< Out1 (Bit 12) */ + #define UART_UART_CR_REG_Out1_Msk (0x1000UL) /*!< Out1 (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_RTS_Pos (11UL) /*!< RTS (Bit 11) */ + #define UART_UART_CR_REG_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_DTR_Pos (10UL) /*!< DTR (Bit 10) */ + #define UART_UART_CR_REG_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_RXE_Pos (9UL) /*!< RXE (Bit 9) */ + #define UART_UART_CR_REG_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_TXE_Pos (8UL) /*!< TXE (Bit 8) */ + #define UART_UART_CR_REG_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_LBE_Pos (7UL) /*!< LBE (Bit 7) */ + #define UART_UART_CR_REG_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ + #define UART_UART_CR_REG_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ + #define UART_UART_CR_REG_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ==================================================== UART_DMACR_REG ===================================================== */ + #define UART_UART_DMACR_REG_DMAONERR_Pos (2UL) /*!< DMAONERR (Bit 2) */ + #define UART_UART_DMACR_REG_DMAONERR_Msk (0x4UL) /*!< DMAONERR (Bitfield-Mask: 0x01) */ + #define UART_UART_DMACR_REG_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ + #define UART_UART_DMACR_REG_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ + #define UART_UART_DMACR_REG_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ + #define UART_UART_DMACR_REG_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +/* ====================================================== UART_DR_REG ====================================================== */ + #define UART_UART_DR_REG_DR_OE_Pos (11UL) /*!< DR_OE (Bit 11) */ + #define UART_UART_DR_REG_DR_OE_Msk (0x800UL) /*!< DR_OE (Bitfield-Mask: 0x01) */ + #define UART_UART_DR_REG_DR_BE_Pos (10UL) /*!< DR_BE (Bit 10) */ + #define UART_UART_DR_REG_DR_BE_Msk (0x400UL) /*!< DR_BE (Bitfield-Mask: 0x01) */ + #define UART_UART_DR_REG_DR_PE_Pos (9UL) /*!< DR_PE (Bit 9) */ + #define UART_UART_DR_REG_DR_PE_Msk (0x200UL) /*!< DR_PE (Bitfield-Mask: 0x01) */ + #define UART_UART_DR_REG_DR_FE_Pos (8UL) /*!< DR_FE (Bit 8) */ + #define UART_UART_DR_REG_DR_FE_Msk (0x100UL) /*!< DR_FE (Bitfield-Mask: 0x01) */ + #define UART_UART_DR_REG_DR_DATA_Pos (0UL) /*!< DR_DATA (Bit 0) */ + #define UART_UART_DR_REG_DR_DATA_Msk (0xffUL) /*!< DR_DATA (Bitfield-Mask: 0xff) */ +/* ===================================================== UART_FBRD_REG ===================================================== */ + #define UART_UART_FBRD_REG_BAUD_DIVFRAC_Pos (0UL) /*!< BAUD_DIVFRAC (Bit 0) */ + #define UART_UART_FBRD_REG_BAUD_DIVFRAC_Msk (0x3fUL) /*!< BAUD_DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ====================================================== UART_FR_REG ====================================================== */ + #define UART_UART_FR_REG_RI_Pos (8UL) /*!< RI (Bit 8) */ + #define UART_UART_FR_REG_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ + #define UART_UART_FR_REG_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ + #define UART_UART_FR_REG_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ + #define UART_UART_FR_REG_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ + #define UART_UART_FR_REG_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ + #define UART_UART_FR_REG_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_DCD_Pos (2UL) /*!< DCD (Bit 2) */ + #define UART_UART_FR_REG_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_DSR_Pos (1UL) /*!< DSR (Bit 1) */ + #define UART_UART_FR_REG_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ + #define UART_UART_FR_REG_CTS_Pos (0UL) /*!< CTS (Bit 0) */ + #define UART_UART_FR_REG_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_IBRD_REG ===================================================== */ + #define UART_UART_IBRD_REG_BAUD_DIVINT_Pos (0UL) /*!< BAUD_DIVINT (Bit 0) */ + #define UART_UART_IBRD_REG_BAUD_DIVINT_Msk (0xffffUL) /*!< BAUD_DIVINT (Bitfield-Mask: 0xffff) */ +/* ===================================================== UART_ICR_REG ====================================================== */ + #define UART_UART_ICR_REG_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ + #define UART_UART_ICR_REG_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ + #define UART_UART_ICR_REG_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ + #define UART_UART_ICR_REG_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ + #define UART_UART_ICR_REG_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ + #define UART_UART_ICR_REG_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ + #define UART_UART_ICR_REG_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ + #define UART_UART_ICR_REG_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ + #define UART_UART_ICR_REG_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ + #define UART_UART_ICR_REG_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ + #define UART_UART_ICR_REG_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ + #define UART_UART_ICR_REG_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */ + #define UART_UART_ICR_REG_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_IFLS_REG ===================================================== */ + #define UART_UART_IFLS_REG_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ + #define UART_UART_IFLS_REG_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ + #define UART_UART_IFLS_REG_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ + #define UART_UART_IFLS_REG_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ===================================================== UART_IMSC_REG ===================================================== */ + #define UART_UART_IMSC_REG_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ + #define UART_UART_IMSC_REG_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ + #define UART_UART_IMSC_REG_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ + #define UART_UART_IMSC_REG_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ + #define UART_UART_IMSC_REG_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ + #define UART_UART_IMSC_REG_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ + #define UART_UART_IMSC_REG_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ + #define UART_UART_IMSC_REG_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ + #define UART_UART_IMSC_REG_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ + #define UART_UART_IMSC_REG_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ + #define UART_UART_IMSC_REG_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ + #define UART_UART_IMSC_REG_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */ + #define UART_UART_IMSC_REG_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */ +/* ==================================================== UART_LCR_H_REG ===================================================== */ + #define UART_UART_LCR_H_REG_SPS_Pos (7UL) /*!< SPS (Bit 7) */ + #define UART_UART_LCR_H_REG_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ + #define UART_UART_LCR_H_REG_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ + #define UART_UART_LCR_H_REG_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ + #define UART_UART_LCR_H_REG_FEN_Pos (4UL) /*!< FEN (Bit 4) */ + #define UART_UART_LCR_H_REG_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ + #define UART_UART_LCR_H_REG_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ + #define UART_UART_LCR_H_REG_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ + #define UART_UART_LCR_H_REG_EPS_Pos (2UL) /*!< EPS (Bit 2) */ + #define UART_UART_LCR_H_REG_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ + #define UART_UART_LCR_H_REG_PEN_Pos (1UL) /*!< PEN (Bit 1) */ + #define UART_UART_LCR_H_REG_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ + #define UART_UART_LCR_H_REG_BRK_Pos (0UL) /*!< BRK (Bit 0) */ + #define UART_UART_LCR_H_REG_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_MIS_REG ====================================================== */ + #define UART_UART_MIS_REG_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ + #define UART_UART_MIS_REG_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ + #define UART_UART_MIS_REG_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ + #define UART_UART_MIS_REG_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ + #define UART_UART_MIS_REG_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ + #define UART_UART_MIS_REG_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ + #define UART_UART_MIS_REG_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ + #define UART_UART_MIS_REG_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ + #define UART_UART_MIS_REG_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ + #define UART_UART_MIS_REG_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ + #define UART_UART_MIS_REG_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_MIS_REG_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */ + #define UART_UART_MIS_REG_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_RIS_REG ====================================================== */ + #define UART_UART_RIS_REG_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ + #define UART_UART_RIS_REG_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ + #define UART_UART_RIS_REG_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ + #define UART_UART_RIS_REG_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ + #define UART_UART_RIS_REG_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ + #define UART_UART_RIS_REG_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ + #define UART_UART_RIS_REG_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ + #define UART_UART_RIS_REG_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_DSRRMIS_Pos (3UL) /*!< DSRRMIS (Bit 3) */ + #define UART_UART_RIS_REG_DSRRMIS_Msk (0x8UL) /*!< DSRRMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_DCDRMIS_Pos (2UL) /*!< DCDRMIS (Bit 2) */ + #define UART_UART_RIS_REG_DCDRMIS_Msk (0x4UL) /*!< DCDRMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_CTSRMIS_Pos (1UL) /*!< CTSRMIS (Bit 1) */ + #define UART_UART_RIS_REG_CTSRMIS_Msk (0x2UL) /*!< CTSRMIS (Bitfield-Mask: 0x01) */ + #define UART_UART_RIS_REG_RIRMIS_Pos (0UL) /*!< RIRMIS (Bit 0) */ + #define UART_UART_RIS_REG_RIRMIS_Msk (0x1UL) /*!< RIRMIS (Bitfield-Mask: 0x01) */ +/* =================================================== UART_RS485EN_REG ==================================================== */ + #define UART_UART_RS485EN_REG_RS485E_Pos (0UL) /*!< RS485E (Bit 0) */ + #define UART_UART_RS485EN_REG_RS485E_Msk (0x1UL) /*!< RS485E (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_RSR_REG ====================================================== */ + #define UART_UART_RSR_REG_RSR_OE_Pos (3UL) /*!< RSR_OE (Bit 3) */ + #define UART_UART_RSR_REG_RSR_OE_Msk (0x8UL) /*!< RSR_OE (Bitfield-Mask: 0x01) */ + #define UART_UART_RSR_REG_RSR_BE_Pos (2UL) /*!< RSR_BE (Bit 2) */ + #define UART_UART_RSR_REG_RSR_BE_Msk (0x4UL) /*!< RSR_BE (Bitfield-Mask: 0x01) */ + #define UART_UART_RSR_REG_RSR_PE_Pos (1UL) /*!< RSR_PE (Bit 1) */ + #define UART_UART_RSR_REG_RSR_PE_Msk (0x2UL) /*!< RSR_PE (Bitfield-Mask: 0x01) */ + #define UART_UART_RSR_REG_RSR_FE_Pos (0UL) /*!< RSR_FE (Bit 0) */ + #define UART_UART_RSR_REG_RSR_FE_Msk (0x1UL) /*!< RSR_FE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_SWFC_REG ===================================================== */ + #define UART_UART_SWFC_REG_SWFCE_Pos (0UL) /*!< SWFCE (Bit 0) */ + #define UART_UART_SWFC_REG_SWFCE_Msk (0x1UL) /*!< SWFCE (Bitfield-Mask: 0x01) */ +/* ====================================================== UART_WA_REG ====================================================== */ + #define UART_UART_WA_REG_WAE_Pos (0UL) /*!< WAE (Bit 0) */ + #define UART_UART_WA_REG_WAE_Msk (0x1UL) /*!< WAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART2_CR_REG ====================================================== */ + #define UART2_UART2_CR_REG_CTSEn_Pos (15UL) /*!< CTSEn (Bit 15) */ + #define UART2_UART2_CR_REG_CTSEn_Msk (0x8000UL) /*!< CTSEn (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_RTSEn_Pos (14UL) /*!< RTSEn (Bit 14) */ + #define UART2_UART2_CR_REG_RTSEn_Msk (0x4000UL) /*!< RTSEn (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_Out2_Pos (13UL) /*!< Out2 (Bit 13) */ + #define UART2_UART2_CR_REG_Out2_Msk (0x2000UL) /*!< Out2 (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_Out1_Pos (12UL) /*!< Out1 (Bit 12) */ + #define UART2_UART2_CR_REG_Out1_Msk (0x1000UL) /*!< Out1 (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_RTS_Pos (11UL) /*!< RTS (Bit 11) */ + #define UART2_UART2_CR_REG_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_DTR_Pos (10UL) /*!< DTR (Bit 10) */ + #define UART2_UART2_CR_REG_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_RXE_Pos (9UL) /*!< RXE (Bit 9) */ + #define UART2_UART2_CR_REG_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_TXE_Pos (8UL) /*!< TXE (Bit 8) */ + #define UART2_UART2_CR_REG_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_LBE_Pos (7UL) /*!< LBE (Bit 7) */ + #define UART2_UART2_CR_REG_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_CR_REG_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ + #define UART2_UART2_CR_REG_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_DMACR_REG ==================================================== */ + #define UART2_UART2_DMACR_REG_DMAONERR_Pos (2UL) /*!< DMAONERR (Bit 2) */ + #define UART2_UART2_DMACR_REG_DMAONERR_Msk (0x4UL) /*!< DMAONERR (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DMACR_REG_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ + #define UART2_UART2_DMACR_REG_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DMACR_REG_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ + #define UART2_UART2_DMACR_REG_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_DR_REG ====================================================== */ + #define UART2_UART2_DR_REG_DR_OE_Pos (11UL) /*!< DR_OE (Bit 11) */ + #define UART2_UART2_DR_REG_DR_OE_Msk (0x800UL) /*!< DR_OE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DR_REG_DR_BE_Pos (10UL) /*!< DR_BE (Bit 10) */ + #define UART2_UART2_DR_REG_DR_BE_Msk (0x400UL) /*!< DR_BE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DR_REG_DR_PE_Pos (9UL) /*!< DR_PE (Bit 9) */ + #define UART2_UART2_DR_REG_DR_PE_Msk (0x200UL) /*!< DR_PE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DR_REG_DR_FE_Pos (8UL) /*!< DR_FE (Bit 8) */ + #define UART2_UART2_DR_REG_DR_FE_Msk (0x100UL) /*!< DR_FE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_DR_REG_DR_DATA_Pos (0UL) /*!< DR_DATA (Bit 0) */ + #define UART2_UART2_DR_REG_DR_DATA_Msk (0xffUL) /*!< DR_DATA (Bitfield-Mask: 0xff) */ +/* ==================================================== UART2_FBRD_REG ===================================================== */ + #define UART2_UART2_FBRD_REG_BAUD_DIVFRAC_Pos (0UL) /*!< BAUD_DIVFRAC (Bit 0) */ + #define UART2_UART2_FBRD_REG_BAUD_DIVFRAC_Msk (0x3fUL) /*!< BAUD_DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ===================================================== UART2_FR_REG ====================================================== */ + #define UART2_UART2_FR_REG_RI_Pos (8UL) /*!< RI (Bit 8) */ + #define UART2_UART2_FR_REG_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ + #define UART2_UART2_FR_REG_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ + #define UART2_UART2_FR_REG_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ + #define UART2_UART2_FR_REG_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ + #define UART2_UART2_FR_REG_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ + #define UART2_UART2_FR_REG_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_DCD_Pos (2UL) /*!< DCD (Bit 2) */ + #define UART2_UART2_FR_REG_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_DSR_Pos (1UL) /*!< DSR (Bit 1) */ + #define UART2_UART2_FR_REG_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ + #define UART2_UART2_FR_REG_CTS_Pos (0UL) /*!< CTS (Bit 0) */ + #define UART2_UART2_FR_REG_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_IBRD_REG ===================================================== */ + #define UART2_UART2_IBRD_REG_BAUD_DIVINT_Pos (0UL) /*!< BAUD_DIVINT (Bit 0) */ + #define UART2_UART2_IBRD_REG_BAUD_DIVINT_Msk (0xffffUL) /*!< BAUD_DIVINT (Bitfield-Mask: 0xffff) */ +/* ===================================================== UART2_ICR_REG ===================================================== */ + #define UART2_UART2_ICR_REG_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ + #define UART2_UART2_ICR_REG_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ + #define UART2_UART2_ICR_REG_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ + #define UART2_UART2_ICR_REG_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ + #define UART2_UART2_ICR_REG_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ + #define UART2_UART2_ICR_REG_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ + #define UART2_UART2_ICR_REG_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ + #define UART2_UART2_ICR_REG_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ + #define UART2_UART2_ICR_REG_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ + #define UART2_UART2_ICR_REG_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ + #define UART2_UART2_ICR_REG_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ + #define UART2_UART2_ICR_REG_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */ + #define UART2_UART2_ICR_REG_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_IFLS_REG ===================================================== */ + #define UART2_UART2_IFLS_REG_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ + #define UART2_UART2_IFLS_REG_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ + #define UART2_UART2_IFLS_REG_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ + #define UART2_UART2_IFLS_REG_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ==================================================== UART2_IMSC_REG ===================================================== */ + #define UART2_UART2_IMSC_REG_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ + #define UART2_UART2_IMSC_REG_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ + #define UART2_UART2_IMSC_REG_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ + #define UART2_UART2_IMSC_REG_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ + #define UART2_UART2_IMSC_REG_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ + #define UART2_UART2_IMSC_REG_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ + #define UART2_UART2_IMSC_REG_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ + #define UART2_UART2_IMSC_REG_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ + #define UART2_UART2_IMSC_REG_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ + #define UART2_UART2_IMSC_REG_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ + #define UART2_UART2_IMSC_REG_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ + #define UART2_UART2_IMSC_REG_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */ + #define UART2_UART2_IMSC_REG_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_LCR_H_REG ==================================================== */ + #define UART2_UART2_LCR_H_REG_SPS_Pos (7UL) /*!< SPS (Bit 7) */ + #define UART2_UART2_LCR_H_REG_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_LCR_H_REG_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ + #define UART2_UART2_LCR_H_REG_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ + #define UART2_UART2_LCR_H_REG_FEN_Pos (4UL) /*!< FEN (Bit 4) */ + #define UART2_UART2_LCR_H_REG_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ + #define UART2_UART2_LCR_H_REG_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ + #define UART2_UART2_LCR_H_REG_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ + #define UART2_UART2_LCR_H_REG_EPS_Pos (2UL) /*!< EPS (Bit 2) */ + #define UART2_UART2_LCR_H_REG_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_LCR_H_REG_PEN_Pos (1UL) /*!< PEN (Bit 1) */ + #define UART2_UART2_LCR_H_REG_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ + #define UART2_UART2_LCR_H_REG_BRK_Pos (0UL) /*!< BRK (Bit 0) */ + #define UART2_UART2_LCR_H_REG_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_MIS_REG ===================================================== */ + #define UART2_UART2_MIS_REG_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ + #define UART2_UART2_MIS_REG_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ + #define UART2_UART2_MIS_REG_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ + #define UART2_UART2_MIS_REG_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ + #define UART2_UART2_MIS_REG_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ + #define UART2_UART2_MIS_REG_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ + #define UART2_UART2_MIS_REG_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ + #define UART2_UART2_MIS_REG_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ + #define UART2_UART2_MIS_REG_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ + #define UART2_UART2_MIS_REG_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ + #define UART2_UART2_MIS_REG_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_MIS_REG_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */ + #define UART2_UART2_MIS_REG_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_RIS_REG ===================================================== */ + #define UART2_UART2_RIS_REG_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ + #define UART2_UART2_RIS_REG_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ + #define UART2_UART2_RIS_REG_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ + #define UART2_UART2_RIS_REG_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ + #define UART2_UART2_RIS_REG_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ + #define UART2_UART2_RIS_REG_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ + #define UART2_UART2_RIS_REG_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ + #define UART2_UART2_RIS_REG_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_DSRRMIS_Pos (3UL) /*!< DSRRMIS (Bit 3) */ + #define UART2_UART2_RIS_REG_DSRRMIS_Msk (0x8UL) /*!< DSRRMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_DCDRMIS_Pos (2UL) /*!< DCDRMIS (Bit 2) */ + #define UART2_UART2_RIS_REG_DCDRMIS_Msk (0x4UL) /*!< DCDRMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_CTSRMIS_Pos (1UL) /*!< CTSRMIS (Bit 1) */ + #define UART2_UART2_RIS_REG_CTSRMIS_Msk (0x2UL) /*!< CTSRMIS (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RIS_REG_RIRMIS_Pos (0UL) /*!< RIRMIS (Bit 0) */ + #define UART2_UART2_RIS_REG_RIRMIS_Msk (0x1UL) /*!< RIRMIS (Bitfield-Mask: 0x01) */ +/* =================================================== UART2_RS485EN_REG =================================================== */ + #define UART2_UART2_RS485EN_REG_RS485E_Pos (0UL) /*!< RS485E (Bit 0) */ + #define UART2_UART2_RS485EN_REG_RS485E_Msk (0x1UL) /*!< RS485E (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_RSR_REG ===================================================== */ + #define UART2_UART2_RSR_REG_RSR_OE_Pos (3UL) /*!< RSR_OE (Bit 3) */ + #define UART2_UART2_RSR_REG_RSR_OE_Msk (0x8UL) /*!< RSR_OE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RSR_REG_RSR_BE_Pos (2UL) /*!< RSR_BE (Bit 2) */ + #define UART2_UART2_RSR_REG_RSR_BE_Msk (0x4UL) /*!< RSR_BE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RSR_REG_RSR_PE_Pos (1UL) /*!< RSR_PE (Bit 1) */ + #define UART2_UART2_RSR_REG_RSR_PE_Msk (0x2UL) /*!< RSR_PE (Bitfield-Mask: 0x01) */ + #define UART2_UART2_RSR_REG_RSR_FE_Pos (0UL) /*!< RSR_FE (Bit 0) */ + #define UART2_UART2_RSR_REG_RSR_FE_Msk (0x1UL) /*!< RSR_FE (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_SWFC_REG ===================================================== */ + #define UART2_UART2_SWFC_REG_SWFCE_Pos (0UL) /*!< SWFCE (Bit 0) */ + #define UART2_UART2_SWFC_REG_SWFCE_Msk (0x1UL) /*!< SWFCE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_WA_REG ====================================================== */ + #define UART2_UART2_WA_REG_WAE_Pos (0UL) /*!< WAE (Bit 0) */ + #define UART2_UART2_WA_REG_WAE_Msk (0x1UL) /*!< WAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART3_CR_REG ====================================================== */ + #define UART3_UART3_CR_REG_CTSEn_Pos (15UL) /*!< CTSEn (Bit 15) */ + #define UART3_UART3_CR_REG_CTSEn_Msk (0x8000UL) /*!< CTSEn (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_RTSEn_Pos (14UL) /*!< RTSEn (Bit 14) */ + #define UART3_UART3_CR_REG_RTSEn_Msk (0x4000UL) /*!< RTSEn (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_Out2_Pos (13UL) /*!< Out2 (Bit 13) */ + #define UART3_UART3_CR_REG_Out2_Msk (0x2000UL) /*!< Out2 (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_Out1_Pos (12UL) /*!< Out1 (Bit 12) */ + #define UART3_UART3_CR_REG_Out1_Msk (0x1000UL) /*!< Out1 (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_RTS_Pos (11UL) /*!< RTS (Bit 11) */ + #define UART3_UART3_CR_REG_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_DTR_Pos (10UL) /*!< DTR (Bit 10) */ + #define UART3_UART3_CR_REG_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_RXE_Pos (9UL) /*!< RXE (Bit 9) */ + #define UART3_UART3_CR_REG_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_TXE_Pos (8UL) /*!< TXE (Bit 8) */ + #define UART3_UART3_CR_REG_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_LBE_Pos (7UL) /*!< LBE (Bit 7) */ + #define UART3_UART3_CR_REG_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_CR_REG_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ + #define UART3_UART3_CR_REG_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_DMACR_REG ==================================================== */ + #define UART3_UART3_DMACR_REG_DMAONERR_Pos (2UL) /*!< DMAONERR (Bit 2) */ + #define UART3_UART3_DMACR_REG_DMAONERR_Msk (0x4UL) /*!< DMAONERR (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DMACR_REG_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ + #define UART3_UART3_DMACR_REG_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DMACR_REG_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ + #define UART3_UART3_DMACR_REG_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_DR_REG ====================================================== */ + #define UART3_UART3_DR_REG_DR_OE_Pos (11UL) /*!< DR_OE (Bit 11) */ + #define UART3_UART3_DR_REG_DR_OE_Msk (0x800UL) /*!< DR_OE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DR_REG_DR_BE_Pos (10UL) /*!< DR_BE (Bit 10) */ + #define UART3_UART3_DR_REG_DR_BE_Msk (0x400UL) /*!< DR_BE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DR_REG_DR_PE_Pos (9UL) /*!< DR_PE (Bit 9) */ + #define UART3_UART3_DR_REG_DR_PE_Msk (0x200UL) /*!< DR_PE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DR_REG_DR_FE_Pos (8UL) /*!< DR_FE (Bit 8) */ + #define UART3_UART3_DR_REG_DR_FE_Msk (0x100UL) /*!< DR_FE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_DR_REG_DR_DATA_Pos (0UL) /*!< DR_DATA (Bit 0) */ + #define UART3_UART3_DR_REG_DR_DATA_Msk (0xffUL) /*!< DR_DATA (Bitfield-Mask: 0xff) */ +/* ==================================================== UART3_FBRD_REG ===================================================== */ + #define UART3_UART3_FBRD_REG_BAUD_DIVFRAC_Pos (0UL) /*!< BAUD_DIVFRAC (Bit 0) */ + #define UART3_UART3_FBRD_REG_BAUD_DIVFRAC_Msk (0x3fUL) /*!< BAUD_DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ===================================================== UART3_FR_REG ====================================================== */ + #define UART3_UART3_FR_REG_RI_Pos (8UL) /*!< RI (Bit 8) */ + #define UART3_UART3_FR_REG_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ + #define UART3_UART3_FR_REG_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ + #define UART3_UART3_FR_REG_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ + #define UART3_UART3_FR_REG_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ + #define UART3_UART3_FR_REG_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ + #define UART3_UART3_FR_REG_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_DCD_Pos (2UL) /*!< DCD (Bit 2) */ + #define UART3_UART3_FR_REG_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_DSR_Pos (1UL) /*!< DSR (Bit 1) */ + #define UART3_UART3_FR_REG_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ + #define UART3_UART3_FR_REG_CTS_Pos (0UL) /*!< CTS (Bit 0) */ + #define UART3_UART3_FR_REG_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_IBRD_REG ===================================================== */ + #define UART3_UART3_IBRD_REG_BAUD_DIVINT_Pos (0UL) /*!< BAUD_DIVINT (Bit 0) */ + #define UART3_UART3_IBRD_REG_BAUD_DIVINT_Msk (0xffffUL) /*!< BAUD_DIVINT (Bitfield-Mask: 0xffff) */ +/* ===================================================== UART3_ICR_REG ===================================================== */ + #define UART3_UART3_ICR_REG_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ + #define UART3_UART3_ICR_REG_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ + #define UART3_UART3_ICR_REG_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ + #define UART3_UART3_ICR_REG_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ + #define UART3_UART3_ICR_REG_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ + #define UART3_UART3_ICR_REG_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ + #define UART3_UART3_ICR_REG_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ + #define UART3_UART3_ICR_REG_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ + #define UART3_UART3_ICR_REG_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ + #define UART3_UART3_ICR_REG_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ + #define UART3_UART3_ICR_REG_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ + #define UART3_UART3_ICR_REG_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */ + #define UART3_UART3_ICR_REG_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_IFLS_REG ===================================================== */ + #define UART3_UART3_IFLS_REG_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ + #define UART3_UART3_IFLS_REG_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ + #define UART3_UART3_IFLS_REG_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ + #define UART3_UART3_IFLS_REG_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ==================================================== UART3_IMSC_REG ===================================================== */ + #define UART3_UART3_IMSC_REG_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ + #define UART3_UART3_IMSC_REG_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ + #define UART3_UART3_IMSC_REG_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ + #define UART3_UART3_IMSC_REG_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ + #define UART3_UART3_IMSC_REG_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ + #define UART3_UART3_IMSC_REG_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ + #define UART3_UART3_IMSC_REG_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ + #define UART3_UART3_IMSC_REG_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ + #define UART3_UART3_IMSC_REG_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ + #define UART3_UART3_IMSC_REG_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ + #define UART3_UART3_IMSC_REG_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ + #define UART3_UART3_IMSC_REG_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */ + #define UART3_UART3_IMSC_REG_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_LCR_H_REG ==================================================== */ + #define UART3_UART3_LCR_H_REG_SPS_Pos (7UL) /*!< SPS (Bit 7) */ + #define UART3_UART3_LCR_H_REG_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_LCR_H_REG_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ + #define UART3_UART3_LCR_H_REG_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ + #define UART3_UART3_LCR_H_REG_FEN_Pos (4UL) /*!< FEN (Bit 4) */ + #define UART3_UART3_LCR_H_REG_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ + #define UART3_UART3_LCR_H_REG_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ + #define UART3_UART3_LCR_H_REG_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ + #define UART3_UART3_LCR_H_REG_EPS_Pos (2UL) /*!< EPS (Bit 2) */ + #define UART3_UART3_LCR_H_REG_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_LCR_H_REG_PEN_Pos (1UL) /*!< PEN (Bit 1) */ + #define UART3_UART3_LCR_H_REG_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ + #define UART3_UART3_LCR_H_REG_BRK_Pos (0UL) /*!< BRK (Bit 0) */ + #define UART3_UART3_LCR_H_REG_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_MIS_REG ===================================================== */ + #define UART3_UART3_MIS_REG_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ + #define UART3_UART3_MIS_REG_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ + #define UART3_UART3_MIS_REG_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ + #define UART3_UART3_MIS_REG_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ + #define UART3_UART3_MIS_REG_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ + #define UART3_UART3_MIS_REG_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ + #define UART3_UART3_MIS_REG_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ + #define UART3_UART3_MIS_REG_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ + #define UART3_UART3_MIS_REG_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ + #define UART3_UART3_MIS_REG_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ + #define UART3_UART3_MIS_REG_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_MIS_REG_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */ + #define UART3_UART3_MIS_REG_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_RIS_REG ===================================================== */ + #define UART3_UART3_RIS_REG_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ + #define UART3_UART3_RIS_REG_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ + #define UART3_UART3_RIS_REG_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ + #define UART3_UART3_RIS_REG_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ + #define UART3_UART3_RIS_REG_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ + #define UART3_UART3_RIS_REG_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ + #define UART3_UART3_RIS_REG_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ + #define UART3_UART3_RIS_REG_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_DSRRMIS_Pos (3UL) /*!< DSRRMIS (Bit 3) */ + #define UART3_UART3_RIS_REG_DSRRMIS_Msk (0x8UL) /*!< DSRRMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_DCDRMIS_Pos (2UL) /*!< DCDRMIS (Bit 2) */ + #define UART3_UART3_RIS_REG_DCDRMIS_Msk (0x4UL) /*!< DCDRMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_CTSRMIS_Pos (1UL) /*!< CTSRMIS (Bit 1) */ + #define UART3_UART3_RIS_REG_CTSRMIS_Msk (0x2UL) /*!< CTSRMIS (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RIS_REG_RIRMIS_Pos (0UL) /*!< RIRMIS (Bit 0) */ + #define UART3_UART3_RIS_REG_RIRMIS_Msk (0x1UL) /*!< RIRMIS (Bitfield-Mask: 0x01) */ +/* =================================================== UART3_RS485EN_REG =================================================== */ + #define UART3_UART3_RS485EN_REG_RS485E_Pos (0UL) /*!< RS485E (Bit 0) */ + #define UART3_UART3_RS485EN_REG_RS485E_Msk (0x1UL) /*!< RS485E (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_RSR_REG ===================================================== */ + #define UART3_UART3_RSR_REG_RSR_OE_Pos (3UL) /*!< RSR_OE (Bit 3) */ + #define UART3_UART3_RSR_REG_RSR_OE_Msk (0x8UL) /*!< RSR_OE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RSR_REG_RSR_BE_Pos (2UL) /*!< RSR_BE (Bit 2) */ + #define UART3_UART3_RSR_REG_RSR_BE_Msk (0x4UL) /*!< RSR_BE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RSR_REG_RSR_PE_Pos (1UL) /*!< RSR_PE (Bit 1) */ + #define UART3_UART3_RSR_REG_RSR_PE_Msk (0x2UL) /*!< RSR_PE (Bitfield-Mask: 0x01) */ + #define UART3_UART3_RSR_REG_RSR_FE_Pos (0UL) /*!< RSR_FE (Bit 0) */ + #define UART3_UART3_RSR_REG_RSR_FE_Msk (0x1UL) /*!< RSR_FE (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_SWFC_REG ===================================================== */ + #define UART3_UART3_SWFC_REG_SWFCE_Pos (0UL) /*!< SWFCE (Bit 0) */ + #define UART3_UART3_SWFC_REG_SWFCE_Msk (0x1UL) /*!< SWFCE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_WA_REG ====================================================== */ + #define UART3_UART3_WA_REG_WAE_Pos (0UL) /*!< WAE (Bit 0) */ + #define UART3_UART3_WA_REG_WAE_Msk (0x1UL) /*!< WAE (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Enumerated Values Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup EnumValue_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ APU_AUD ================ */ +/* =========================================================================================================================== */ + +/* =================================================== APU_DMIC_CTRL_REG =================================================== */ +/* =================================================== APU_DMIC_DIV_REG ==================================================== */ +/* =================================================== APU_MAIN_DIV_REG ==================================================== */ +/* =================================================== APU_SYNC_DIV_REG ==================================================== */ +/* ================================================= APU_SYNC_DIV_SEL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ APU_DSP ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== APU_CTRL_REG ====================================================== */ +/* =================================================== APU_MUX_CTRL_REG ==================================================== */ +/* =================================================== APU_PCM1_DIV_REG ==================================================== */ +/* ================================================ APU_PCM1_FDIV_HIGH_REG ================================================= */ +/* =================================================== APU_PCM1_FDIV_REG =================================================== */ +/* ==================================================== APU_PCM_CLK_REG ==================================================== */ +/* ================================================ APU_SYNC_SRC1IN_SEL_REG ================================================ */ +/* =============================================== APU_SYNC_SRC1OUT_SEL_REG ================================================ */ + +/* =========================================================================================================================== */ +/* ================ AUXADC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== FIFO0_DATA_CURR_REG ================================================== */ +/* ================================================== FIFO0_DMA_DATA_REG =================================================== */ +/* ================================================== FIFO1_DATA_CURR_REG ================================================== */ +/* ================================================== FIFO1_DMA_DATA_REG =================================================== */ +/* ================================================== FIFO2_DATA_CURR_REG ================================================== */ +/* ================================================== FIFO2_DMA_DATA_REG =================================================== */ +/* ================================================== FIFO3_DATA_CURR_REG ================================================== */ +/* ================================================== FIFO3_DMA_DATA_REG =================================================== */ +/* ================================================== FXADC_CLK_CTRL_REG =================================================== */ +/* ================================================== SWITCHING_MODE_REG =================================================== */ +/* ================================================== TIMESTAMP_CTRL_REG =================================================== */ +/* =================================================== XADC12B_CTRL_REG ==================================================== */ +/* ================================================== XADC12B_DMA_EN_REG =================================================== */ +/* ============================================== XADC12B_FIFO_INTR_MASK_REG =============================================== */ +/* ================================================ XADC12B_INTR_STATUS_REG ================================================ */ +/* =============================================== XADC12B_INT_THR_DIFF_REG ================================================ */ +/* =============================================== XADC12B_INT_THR_OVER_REG ================================================ */ +/* =============================================== XADC12B_INT_THR_UNDER_REG =============================================== */ +/* ================================================= XADC12B_RM_SAMPLE_REG ================================================= */ +/* ================================================= XADC12B_ST_SAMPLE_REG ================================================= */ +/* =============================================== XADC12B_THR_INTR_CLR_REG ================================================ */ +/* =============================================== XADC12B_THR_INTR_MASK_REG =============================================== */ + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CACHE_ASSOCCFG_REG =================================================== */ +/* ================================================= CACHE_CPU_M_HADDR_REG ================================================= */ +/* ==================================================== CACHE_CTRL1_REG ==================================================== */ +/* ==================================================== CACHE_CTRL2_REG ==================================================== */ +/* ==================================================== CACHE_CTRL3_REG ==================================================== */ +/* ================================================ CACHE_CTRLR_M_HADDR_REG ================================================ */ +/* ==================================================== CACHE_FLASH_REG ==================================================== */ +/* ================================================== CACHE_LNSIZECFG_REG ================================================== */ +/* ================================================== CACHE_MRM_CTRL_REG =================================================== */ +/* ================================================= CACHE_MRM_HITS1WS_REG ================================================= */ +/* ================================================== CACHE_MRM_HITS_REG =================================================== */ +/* =============================================== CACHE_MRM_HITS_THRES_REG ================================================ */ +/* ================================================= CACHE_MRM_MISSES_REG ================================================== */ +/* ============================================== CACHE_MRM_MISSES_THRES_REG =============================================== */ +/* ================================================== CACHE_MRM_TINT_REG =================================================== */ +/* ================================================ CACHE_M_HADDR_MAP0_REG ================================================= */ +/* ===================================================== SWD_RESET_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ CC312 ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CC312_AES_BUSY_REG =================================================== */ +/* =============================================== CC312_AES_CLK_ENABLE_REG ================================================ */ +/* ================================================ CC312_AES_CMAC_INIT_REG ================================================ */ +/* ============================================= CC312_AES_CMAC_SIZE0_KICK_REG ============================================= */ +/* ================================================= CC312_AES_CONTROL_REG ================================================= */ +/* ================================================= CC312_AES_CTR_0_0_REG ================================================= */ +/* ================================================= CC312_AES_CTR_0_1_REG ================================================= */ +/* ================================================= CC312_AES_CTR_0_2_REG ================================================= */ +/* ================================================= CC312_AES_CTR_0_3_REG ================================================= */ +/* ============================================ CC312_AES_CTR_NO_INCREMENT_REG ============================================= */ +/* ============================================= CC312_AES_DFA_ERR_STATUS_REG ============================================== */ +/* ================================================ CC312_AES_DFA_IS_ON_REG ================================================ */ +/* ================================================ CC312_AES_HW_FLAGS_REG ================================================= */ +/* ================================================= CC312_AES_IV_0_0_REG ================================================== */ +/* ================================================= CC312_AES_IV_0_1_REG ================================================== */ +/* ================================================= CC312_AES_IV_0_2_REG ================================================== */ +/* ================================================= CC312_AES_IV_0_3_REG ================================================== */ +/* ================================================= CC312_AES_IV_1_0_REG ================================================== */ +/* ================================================= CC312_AES_IV_1_1_REG ================================================== */ +/* ================================================= CC312_AES_IV_1_2_REG ================================================== */ +/* ================================================= CC312_AES_IV_1_3_REG ================================================== */ +/* ================================================= CC312_AES_KEY_0_0_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_1_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_2_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_3_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_4_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_5_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_6_REG ================================================= */ +/* ================================================= CC312_AES_KEY_0_7_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_0_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_1_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_2_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_3_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_4_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_5_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_6_REG ================================================= */ +/* ================================================= CC312_AES_KEY_1_7_REG ================================================= */ +/* ============================================= CC312_AES_REMAINING_BYTES_REG ============================================= */ +/* =================================================== CC312_AES_SK1_REG =================================================== */ +/* =================================================== CC312_AES_SK_REG ==================================================== */ +/* =============================================== CC312_AHBM_HMASTLOCK_REG ================================================ */ +/* ================================================ CC312_AHBM_HNONSEC_REG ================================================= */ +/* ================================================= CC312_AHBM_HPROT_REG ================================================== */ +/* ================================================ CC312_AHBM_SINGLES_REG ================================================= */ +/* =========================================== CC312_AIB_FUSE_PROG_COMPLETED_REG =========================================== */ +/* ============================================== CC312_AO_APB_FILTERING_REG =============================================== */ +/* ================================================= CC312_AO_CC_GPPC_REG ================================================== */ +/* ============================================ CC312_AO_CC_SEC_DEBUG_RESET_REG ============================================ */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK0_REG ========================================= */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK1_REG ========================================= */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK2_REG ========================================= */ +/* ======================================== CC312_AO_ICV_DCU_RESTRICTION_MASK3_REG ========================================= */ +/* ============================================= CC312_AUTOCORR_STATISTIC_REG ============================================== */ +/* =============================================== CC312_AUTO_HW_PADDING_REG =============================================== */ +/* ============================================ CC312_CHACHA_BLOCK_CNT_LSB_REG ============================================= */ +/* ============================================ CC312_CHACHA_BLOCK_CNT_MSB_REG ============================================= */ +/* ================================================= CC312_CHACHA_BUSY_REG ================================================= */ +/* ======================================= CC312_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG ======================================= */ +/* ============================================== CC312_CHACHA_CLK_ENABLE_REG ============================================== */ +/* ============================================= CC312_CHACHA_CONTROL_REG_REG ============================================== */ +/* ============================================== CC312_CHACHA_DEBUG_REG_REG =============================================== */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY0_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY1_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY2_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY3_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY4_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY5_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY6_REG ============================================= */ +/* ============================================ CC312_CHACHA_FOR_POLY_KEY7_REG ============================================= */ +/* =============================================== CC312_CHACHA_HW_FLAGS_REG =============================================== */ +/* ================================================= CC312_CHACHA_IV_0_REG ================================================= */ +/* ================================================= CC312_CHACHA_IV_1_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY0_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY1_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY2_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY3_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY4_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY5_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY6_REG ================================================= */ +/* ================================================= CC312_CHACHA_KEY7_REG ================================================= */ +/* =============================================== CC312_CHACHA_SW_RESET_REG =============================================== */ +/* =============================================== CC312_CHACHA_VERSION_REG ================================================ */ +/* ================================================= CC312_CLK_STATUS_REG ================================================== */ +/* =============================================== CC312_COMPONENT_ID_0_REG ================================================ */ +/* =============================================== CC312_COMPONENT_ID_1_REG ================================================ */ +/* =============================================== CC312_COMPONENT_ID_2_REG ================================================ */ +/* =============================================== CC312_COMPONENT_ID_3_REG ================================================ */ +/* ================================================= CC312_CONTEXT_ID_REG ================================================== */ +/* ================================================= CC312_CRYPTO_BUSY_REG ================================================= */ +/* ================================================= CC312_CRYPTO_CTL_REG ================================================== */ +/* ================================================= CC312_DIN_BUFFER_REG ================================================== */ +/* ============================================== CC312_DIN_CPU_DATA_SIZE_REG ============================================== */ +/* ============================================== CC312_DIN_FIFO_RST_PNTR_REG ============================================== */ +/* ============================================== CC312_DIN_MEM_DMA_BUSY_REG =============================================== */ +/* ============================================= CC312_DIN_SRAM_BYTES_LEN_REG ============================================== */ +/* ============================================== CC312_DIN_SRAM_DMA_BUSY_REG ============================================== */ +/* ============================================= CC312_DIN_SRAM_ENDIANNESS_REG ============================================= */ +/* =============================================== CC312_DMA_CLK_ENABLE_REG ================================================ */ +/* ================================================= CC312_DOUT_BUFFER_REG ================================================= */ +/* =============================================== CC312_DOUT_FIFO_EMPTY_REG =============================================== */ +/* ============================================== CC312_DOUT_MEM_DMA_BUSY_REG ============================================== */ +/* ============================================= CC312_DOUT_SRAM_BYTES_LEN_REG ============================================= */ +/* ============================================= CC312_DOUT_SRAM_DMA_BUSY_REG ============================================== */ +/* ============================================ CC312_DOUT_SRAM_ENDIANNESS_REG ============================================= */ +/* ================================================ CC312_DST_LLI_WORD0_REG ================================================ */ +/* ================================================ CC312_DST_LLI_WORD1_REG ================================================ */ +/* ================================================= CC312_EHR_DATA_0_REG ================================================== */ +/* ================================================= CC312_EHR_DATA_1_REG ================================================== */ +/* ================================================= CC312_EHR_DATA_2_REG ================================================== */ +/* ================================================= CC312_EHR_DATA_3_REG ================================================== */ +/* ================================================= CC312_EHR_DATA_4_REG ================================================== */ +/* ================================================= CC312_EHR_DATA_5_REG ================================================== */ +/* ================================================ CC312_FIFO_IN_EMPTY_REG ================================================ */ +/* ================================================= CC312_GHASH_BUSY_REG ================================================== */ +/* ================================================= CC312_GHASH_INIT_REG ================================================== */ +/* ================================================ CC312_GHASH_IV_0_0_REG ================================================= */ +/* ================================================ CC312_GHASH_IV_0_1_REG ================================================= */ +/* ================================================ CC312_GHASH_IV_0_2_REG ================================================= */ +/* ================================================ CC312_GHASH_IV_0_3_REG ================================================= */ +/* ============================================== CC312_GHASH_SUBKEY_0_0_REG =============================================== */ +/* ============================================== CC312_GHASH_SUBKEY_0_1_REG =============================================== */ +/* ============================================== CC312_GHASH_SUBKEY_0_2_REG =============================================== */ +/* ============================================== CC312_GHASH_SUBKEY_0_3_REG =============================================== */ +/* ============================================== CC312_HASH_AES_SW_RESET_REG ============================================== */ +/* ================================================== CC312_HASH_BUSY_REG ================================================== */ +/* =============================================== CC312_HASH_CLK_ENABLE_REG =============================================== */ +/* ================================================ CC312_HASH_CONTROL_REG ================================================= */ +/* =============================================== CC312_HASH_CUR_LEN_0_REG ================================================ */ +/* =============================================== CC312_HASH_CUR_LEN_1_REG ================================================ */ +/* =============================================== CC312_HASH_ENDIANESS_REG ================================================ */ +/* =================================================== CC312_HASH_H0_REG =================================================== */ +/* =================================================== CC312_HASH_H1_REG =================================================== */ +/* =================================================== CC312_HASH_H2_REG =================================================== */ +/* =================================================== CC312_HASH_H3_REG =================================================== */ +/* =================================================== CC312_HASH_H4_REG =================================================== */ +/* =================================================== CC312_HASH_H5_REG =================================================== */ +/* =================================================== CC312_HASH_H6_REG =================================================== */ +/* =================================================== CC312_HASH_H7_REG =================================================== */ +/* =================================================== CC312_HASH_H8_REG =================================================== */ +/* ================================================ CC312_HASH_PAD_CFG_REG ================================================= */ +/* ================================================= CC312_HASH_PAD_EN_REG ================================================= */ +/* ================================================= CC312_HASH_PARAM_REG ================================================== */ +/* ============================================== CC312_HASH_SEL_AES_MAC_REG =============================================== */ +/* ================================================ CC312_HASH_VERSION_REG ================================================= */ +/* ================================================ CC312_HASH_XOR_DIN_REG ================================================= */ +/* ============================================== CC312_HOST_AO_LOCK_BITS_REG ============================================== */ +/* ================================================== CC312_HOST_BOOT_REG ================================================== */ +/* =============================================== CC312_HOST_CC_IS_IDLE_REG =============================================== */ +/* ========================================= CC312_HOST_CORE_CLK_GATING_ENABLE_REG ========================================= */ +/* ============================================= CC312_HOST_CRYPTOKEY_SEL_REG ============================================== */ +/* ================================================ CC312_HOST_DCU_EN0_REG ================================================= */ +/* ================================================ CC312_HOST_DCU_EN1_REG ================================================= */ +/* ================================================ CC312_HOST_DCU_EN2_REG ================================================= */ +/* ================================================ CC312_HOST_DCU_EN3_REG ================================================= */ +/* =============================================== CC312_HOST_DCU_LOCK0_REG ================================================ */ +/* =============================================== CC312_HOST_DCU_LOCK1_REG ================================================ */ +/* =============================================== CC312_HOST_DCU_LOCK2_REG ================================================ */ +/* =============================================== CC312_HOST_DCU_LOCK3_REG ================================================ */ +/* =============================================== CC312_HOST_POWERDOWN_REG ================================================ */ +/* ========================================== CC312_HOST_REMOVE_CHACHA_ENGINE_REG ========================================== */ +/* ========================================== CC312_HOST_REMOVE_GHASH_ENGINE_REG =========================================== */ +/* ============================================= CC312_HOST_RGF_CC_SW_RST_REG ============================================== */ +/* =============================================== CC312_HOST_RGF_ENDIAN_REG =============================================== */ +/* ================================================ CC312_HOST_RGF_ICR_REG ================================================= */ +/* ================================================ CC312_HOST_RGF_IMR_REG ================================================= */ +/* ================================================ CC312_HOST_RGF_IRR_REG ================================================= */ +/* ============================================= CC312_HOST_RGF_SIGNATURE_REG ============================================== */ +/* =========================================== CC312_HOST_SHADOW_KCEICV_REG_REG ============================================ */ +/* ============================================= CC312_HOST_SHADOW_KCE_REG_REG ============================================= */ +/* ============================================= CC312_HOST_SHADOW_KCP_REG_REG ============================================= */ +/* ============================================= CC312_HOST_SHADOW_KDR_REG_REG ============================================= */ +/* ============================================ CC312_HOST_SHADOW_KPICV_REG_REG ============================================ */ +/* ================================================ CC312_LCS_IS_VALID_REG ================================================= */ +/* =================================================== CC312_LCS_REG_REG =================================================== */ +/* =============================================== CC312_LOAD_INIT_STATE_REG =============================================== */ +/* ================================================= CC312_MEMORY_MAP0_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP10_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP11_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP12_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP13_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP14_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP15_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP16_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP17_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP18_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP19_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP1_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP20_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP21_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP22_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP23_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP24_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP25_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP26_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP27_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP28_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP29_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP2_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP30_REG ================================================= */ +/* ================================================ CC312_MEMORY_MAP31_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP3_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP4_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP5_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP6_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP7_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP8_REG ================================================= */ +/* ================================================= CC312_MEMORY_MAP9_REG ================================================= */ +/* ============================================== CC312_NVM_DEBUG_STATUS_REG =============================================== */ +/* ================================================= CC312_NVM_IS_IDLE_REG ================================================= */ +/* =============================================== CC312_N_NP_T0_T1_ADDR_REG =============================================== */ +/* =================================================== CC312_OPCODE_REG ==================================================== */ +/* ============================================= CC312_OTP_ADDR_WIDTH_DEF_REG ============================================== */ +/* =============================================== CC312_PERIPHERAL_ID_0_REG =============================================== */ +/* =============================================== CC312_PERIPHERAL_ID_1_REG =============================================== */ +/* =============================================== CC312_PERIPHERAL_ID_2_REG =============================================== */ +/* =============================================== CC312_PERIPHERAL_ID_3_REG =============================================== */ +/* =============================================== CC312_PERIPHERAL_ID_4_REG =============================================== */ +/* ================================================ CC312_PIDRESERVED0_REG ================================================= */ +/* ================================================ CC312_PIDRESERVED1_REG ================================================= */ +/* ================================================ CC312_PIDRESERVED2_REG ================================================= */ +/* ================================================ CC312_PKA_BUFF_ADDR_REG ================================================ */ +/* =============================================== CC312_PKA_CLK_ENABLE_REG ================================================ */ +/* ================================================== CC312_PKA_DONE_REG =================================================== */ +/* =================================================== CC312_PKA_L0_REG ==================================================== */ +/* =================================================== CC312_PKA_L1_REG ==================================================== */ +/* =================================================== CC312_PKA_L2_REG ==================================================== */ +/* =================================================== CC312_PKA_L3_REG ==================================================== */ +/* =================================================== CC312_PKA_L4_REG ==================================================== */ +/* =================================================== CC312_PKA_L5_REG ==================================================== */ +/* =================================================== CC312_PKA_L6_REG ==================================================== */ +/* =================================================== CC312_PKA_L7_REG ==================================================== */ +/* ================================================ CC312_PKA_MON_READ_REG ================================================= */ +/* =============================================== CC312_PKA_MON_SELECT_REG ================================================ */ +/* ================================================ CC312_PKA_PIPE_RDY_REG ================================================= */ +/* ================================================ CC312_PKA_SRAM_ADDR_REG ================================================ */ +/* =============================================== CC312_PKA_SRAM_RADDR_REG ================================================ */ +/* =============================================== CC312_PKA_SRAM_RDATA_REG ================================================ */ +/* =============================================== CC312_PKA_SRAM_WDATA_REG ================================================ */ +/* =============================================== CC312_PKA_SRAM_WR_CLR_REG =============================================== */ +/* ================================================= CC312_PKA_STATUS_REG ================================================== */ +/* ================================================ CC312_PKA_SW_RESET_REG ================================================= */ +/* ================================================= CC312_PKA_VERSION_REG ================================================= */ +/* =============================================== CC312_PKA_WORD_ACCESS_REG =============================================== */ +/* =============================================== CC312_READ_ALIGN_LAST_REG =============================================== */ +/* ============================================== CC312_RND_SOURCE_ENABLE_REG ============================================== */ +/* ================================================== CC312_RNG_BUSY_REG =================================================== */ +/* =============================================== CC312_RNG_CLK_ENABLE_REG ================================================ */ +/* ============================================= CC312_RNG_DEBUG_EN_INPUT_REG ============================================== */ +/* =============================================== CC312_RNG_DMA_ENABLE_REG ================================================ */ +/* ============================================= CC312_RNG_DMA_SAMPLES_NUM_REG ============================================= */ +/* ============================================== CC312_RNG_DMA_SRAM_ADDR_REG ============================================== */ +/* ============================================== CC312_RNG_DMA_SRC_MASK_REG =============================================== */ +/* =============================================== CC312_RNG_DMA_STATUS_REG ================================================ */ +/* =================================================== CC312_RNG_ICR_REG =================================================== */ +/* =================================================== CC312_RNG_IMR_REG =================================================== */ +/* =================================================== CC312_RNG_ISR_REG =================================================== */ +/* ================================================ CC312_RNG_SW_RESET_REG ================================================= */ +/* ================================================= CC312_RNG_VERSION_REG ================================================= */ +/* ============================================== CC312_RNG_WATCHDOG_VAL_REG =============================================== */ +/* ============================================== CC312_RST_BITS_COUNTER_REG =============================================== */ +/* ================================================= CC312_SAMPLE_CNT1_REG ================================================= */ +/* ================================================== CC312_SRAM_ADDR_REG ================================================== */ +/* =============================================== CC312_SRAM_DATA_READY_REG =============================================== */ +/* ================================================== CC312_SRAM_DATA_REG ================================================== */ +/* =============================================== CC312_SRAM_DEST_ADDR_REG ================================================ */ +/* ================================================ CC312_SRAM_SRC_ADDR_REG ================================================ */ +/* ================================================ CC312_SRC_LLI_WORD0_REG ================================================ */ +/* ================================================ CC312_SRC_LLI_WORD1_REG ================================================ */ +/* ================================================= CC312_TRNG_CONFIG_REG ================================================= */ +/* ============================================= CC312_TRNG_DEBUG_CONTROL_REG ============================================== */ +/* ================================================= CC312_TRNG_VALID_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ CHIP_VERSION ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CHIP_ID1_REG ====================================================== */ +/* ===================================================== CHIP_ID2_REG ====================================================== */ +/* ===================================================== CHIP_ID3_REG ====================================================== */ +/* ===================================================== CHIP_ID4_REG ====================================================== */ +/* =================================================== CHIP_REVISION_REG =================================================== */ +/* ===================================================== CHIP_SWC_REG ====================================================== */ +/* ==================================================== CHIP_TEST1_REG ===================================================== */ +/* ==================================================== CHIP_TEST2_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ CLKCAL_BIF ================ */ +/* =========================================================================================================================== */ + +/* ============================================== ADC_DIG_CAL_WEIGHT_I_0_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_1_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_2_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_3_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_4_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_5_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_6_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_7_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_8_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_I_9_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_0_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_1_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_2_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_3_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_4_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_5_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_6_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_7_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_8_REG =============================================== */ +/* ============================================== ADC_DIG_CAL_WEIGHT_Q_9_REG =============================================== */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_0_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_1_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_2_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_3_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_4_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_5_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_6_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_7_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_8_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_I_9_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_0_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_1_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_2_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_3_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_4_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_5_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_6_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_7_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_8_REG ============================================= */ +/* ============================================ ADC_DIG_O_CALED_WEIGHT_Q_9_REG ============================================= */ +/* ==================================================== CLK_CAL_IRQ_REG ==================================================== */ +/* ==================================================== CLK_REF_CNT_REG ==================================================== */ +/* ==================================================== CLK_REF_SEL_REG ==================================================== */ +/* ==================================================== CLK_REF_VAL_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ CRG_APU ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== APU_AUD_CLK_REG ==================================================== */ +/* =================================================== APU_MCLK_CTRL_REG =================================================== */ +/* ==================================================== APU_SRC_CLK_REG ==================================================== */ +/* ================================================== APU_START_CTRL_REG =================================================== */ +/* =================================================== AUD_CLK_GATE_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ CRG_COM ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== DAC_10B_CFG_REG ==================================================== */ +/* ===================================================== DAC_CTRL_REG ====================================================== */ +/* ==================================================== DAC_FREQ_I_REG ===================================================== */ +/* ==================================================== DAC_FREQ_Q_REG ===================================================== */ +/* ===================================================== DAC_GAIN_REG ====================================================== */ +/* =================================================== EXT_INTB_CTRL_REG =================================================== */ +/* =================================================== EXT_INTB_SET_REG ==================================================== */ +/* ===================================================== FADC_CAL1_REG ===================================================== */ +/* ===================================================== FADC_CAL2_REG ===================================================== */ +/* ================================================== FADC_CAL_DONE_I_REG ================================================== */ +/* ================================================== FADC_CAL_DONE_Q_REG ================================================== */ +/* ===================================================== FADC_CFG0_REG ===================================================== */ +/* ===================================================== FADC_CFG1_REG ===================================================== */ +/* ================================================== FADC_DOUT_DELTA_REG ================================================== */ +/* ================================================== FADC_DOUT_ERROR_REG ================================================== */ +/* =================================================== IP1_BAND_GAP_REG ==================================================== */ +/* =================================================== IP2_BAND_GAP_REG ==================================================== */ +/* =================================================== IP4_DCDC_DIG_REG ==================================================== */ +/* =================================================== IP4_DCDC_FEM_REG ==================================================== */ +/* ================================================= IP4_POR_LDO_CTRL_REG ================================================== */ +/* ===================================================== LDO_CTRL_REG ====================================================== */ +/* ==================================================== MEMORY_CTRL_REG ==================================================== */ +/* ==================================================== MON_RF_TEST_REG ==================================================== */ +/* ================================================= NORMAL_TEST_CTRL_REG ================================================== */ +/* =================================================== PAD_LATCH_EN_REG ==================================================== */ +/* =================================================== PLL1_ARM_CTRL_REG =================================================== */ +/* =================================================== POWER_MANAGE_REG ==================================================== */ +/* ==================================================== PSRAM_DEBUG_REG ==================================================== */ +/* ===================================================== TEST_CFG_REG ====================================================== */ +/* =================================================== XTAL32K_CTRL_REG ==================================================== */ +/* =================================================== XTAL40M_CTRL_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ CRG_PER ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CLK_COM_REG ====================================================== */ +/* =================================================== RESET_CLK_COM_REG =================================================== */ +/* ==================================================== SET_CLK_COM_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ CRG_SYS ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CACHE_RAM_CTRL_REG =================================================== */ +/* ================================================== CRYPTO_RAM_CTRL_REG ================================================== */ +/* ================================================== DCACHE_RAM_CTRL_REG ================================================== */ +/* =================================================== HPI_CLK_CTRL_REG ==================================================== */ +/* =================================================== MEM_CLK_CTRL_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ CRG_TOP ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== AUX_CLK_DIV_REG ==================================================== */ +/* ===================================================== CLK_AMBA_REG ====================================================== */ +/* ===================================================== CLK_CTRL_REG ====================================================== */ +/* ===================================================== PMU_CTRL_REG ====================================================== */ +/* ==================================================== RADIO_RESET_REG ==================================================== */ +/* =================================================== RESET_FREEZE_REG ==================================================== */ +/* ==================================================== RESET_STAT_REG ===================================================== */ +/* ================================================== RETAIN_MEM_CTRL_REG ================================================== */ +/* ===================================================== RFMON_INT_REG ===================================================== */ +/* ===================================================== RST_CTRL_REG ====================================================== */ +/* ==================================================== SET_FREEZE_REG ===================================================== */ +/* ===================================================== SYS_CTRL_REG ====================================================== */ +/* ==================================================== SYS_STATUS_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ DAI ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== DAI_CONFIG_REG ===================================================== */ +/* ================================================= DAI_DATA_OUT_CTRL_REG ================================================= */ +/* ================================================= DAI_DATA_OUT_TEST_REG ================================================= */ +/* ==================================================== DAI_ENABLE_REG ===================================================== */ +/* ===================================================== DAI_MODE_REG ====================================================== */ +/* ================================================== DAI_OFFSET_LSB_REG =================================================== */ +/* ================================================== DAI_OFFSET_MSB_REG =================================================== */ +/* ==================================================== DAI_RX1_CH_REG ===================================================== */ +/* ====================================================== DAI_RX1_REG ====================================================== */ +/* ==================================================== DAI_RX2_CH_REG ===================================================== */ +/* ====================================================== DAI_RX2_REG ====================================================== */ +/* =================================================== DAI_SLOT_CNT_REG ==================================================== */ +/* =================================================== DAI_SR_CONFIG_REG =================================================== */ +/* =================================================== DAI_SYNC_WIN_REG ==================================================== */ +/* ==================================================== DAI_TX1_CH_REG ===================================================== */ +/* ====================================================== DAI_TX1_REG ====================================================== */ +/* ==================================================== DAI_TX2_CH_REG ===================================================== */ +/* ====================================================== DAI_TX2_REG ====================================================== */ +/* ==================================================== DAI_TX_MUX_REG ===================================================== */ +/* ===================================================== DAI_W_LEN_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ DCACHE ================ */ +/* =========================================================================================================================== */ + +/* ================================================= DCACHE_BASE_ADDR_REG ================================================== */ +/* ==================================================== DCACHE_CTRL_REG ==================================================== */ +/* ================================================== DCACHE_MRM_CTRL_REG ================================================== */ +/* ================================================= DCACHE_MRM_EVICTS_REG ================================================= */ +/* ============================================== DCACHE_MRM_EVICTS_THRES_REG ============================================== */ +/* ================================================== DCACHE_MRM_HITS_REG ================================================== */ +/* =============================================== DCACHE_MRM_HITS_THRES_REG =============================================== */ +/* ================================================= DCACHE_MRM_MISSES_REG ================================================= */ +/* ============================================== DCACHE_MRM_MISSES_THRES_REG ============================================== */ +/* ================================================== DCACHE_MRM_TINT_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* =================================================== DMA0_A_START_REG ==================================================== */ +/* =================================================== DMA0_B_START_REG ==================================================== */ +/* ===================================================== DMA0_CTRL_REG ===================================================== */ +/* ===================================================== DMA0_IDX_REG ====================================================== */ +/* ===================================================== DMA0_INT_REG ====================================================== */ +/* ===================================================== DMA0_LEN_REG ====================================================== */ +/* =================================================== DMA10_A_START_REG =================================================== */ +/* =================================================== DMA10_B_START_REG =================================================== */ +/* ==================================================== DMA10_CTRL_REG ===================================================== */ +/* ===================================================== DMA10_IDX_REG ===================================================== */ +/* ===================================================== DMA10_INT_REG ===================================================== */ +/* ===================================================== DMA10_LEN_REG ===================================================== */ +/* =================================================== DMA11_A_START_REG =================================================== */ +/* =================================================== DMA11_B_START_REG =================================================== */ +/* ==================================================== DMA11_CTRL_REG ===================================================== */ +/* ===================================================== DMA11_IDX_REG ===================================================== */ +/* ===================================================== DMA11_INT_REG ===================================================== */ +/* ===================================================== DMA11_LEN_REG ===================================================== */ +/* =================================================== DMA12_A_START_REG =================================================== */ +/* =================================================== DMA12_B_START_REG =================================================== */ +/* ==================================================== DMA12_CTRL_REG ===================================================== */ +/* ===================================================== DMA12_IDX_REG ===================================================== */ +/* ===================================================== DMA12_INT_REG ===================================================== */ +/* ===================================================== DMA12_LEN_REG ===================================================== */ +/* =================================================== DMA13_A_START_REG =================================================== */ +/* =================================================== DMA13_B_START_REG =================================================== */ +/* ==================================================== DMA13_CTRL_REG ===================================================== */ +/* ===================================================== DMA13_IDX_REG ===================================================== */ +/* ===================================================== DMA13_INT_REG ===================================================== */ +/* ===================================================== DMA13_LEN_REG ===================================================== */ +/* =================================================== DMA14_A_START_REG =================================================== */ +/* =================================================== DMA14_B_START_REG =================================================== */ +/* ==================================================== DMA14_CTRL_REG ===================================================== */ +/* ===================================================== DMA14_IDX_REG ===================================================== */ +/* ===================================================== DMA14_INT_REG ===================================================== */ +/* ===================================================== DMA14_LEN_REG ===================================================== */ +/* =================================================== DMA15_A_START_REG =================================================== */ +/* =================================================== DMA15_B_START_REG =================================================== */ +/* ==================================================== DMA15_CTRL_REG ===================================================== */ +/* ===================================================== DMA15_IDX_REG ===================================================== */ +/* ===================================================== DMA15_INT_REG ===================================================== */ +/* ===================================================== DMA15_LEN_REG ===================================================== */ +/* =================================================== DMA1_A_START_REG ==================================================== */ +/* =================================================== DMA1_B_START_REG ==================================================== */ +/* ===================================================== DMA1_CTRL_REG ===================================================== */ +/* ===================================================== DMA1_IDX_REG ====================================================== */ +/* ===================================================== DMA1_INT_REG ====================================================== */ +/* ===================================================== DMA1_LEN_REG ====================================================== */ +/* =================================================== DMA2_A_START_REG ==================================================== */ +/* =================================================== DMA2_B_START_REG ==================================================== */ +/* ===================================================== DMA2_CTRL_REG ===================================================== */ +/* ===================================================== DMA2_IDX_REG ====================================================== */ +/* ===================================================== DMA2_INT_REG ====================================================== */ +/* ===================================================== DMA2_LEN_REG ====================================================== */ +/* =================================================== DMA3_A_START_REG ==================================================== */ +/* =================================================== DMA3_B_START_REG ==================================================== */ +/* ===================================================== DMA3_CTRL_REG ===================================================== */ +/* ===================================================== DMA3_IDX_REG ====================================================== */ +/* ===================================================== DMA3_INT_REG ====================================================== */ +/* ===================================================== DMA3_LEN_REG ====================================================== */ +/* =================================================== DMA4_A_START_REG ==================================================== */ +/* =================================================== DMA4_B_START_REG ==================================================== */ +/* ===================================================== DMA4_CTRL_REG ===================================================== */ +/* ===================================================== DMA4_IDX_REG ====================================================== */ +/* ===================================================== DMA4_INT_REG ====================================================== */ +/* ===================================================== DMA4_LEN_REG ====================================================== */ +/* =================================================== DMA5_A_START_REG ==================================================== */ +/* =================================================== DMA5_B_START_REG ==================================================== */ +/* ===================================================== DMA5_CTRL_REG ===================================================== */ +/* ===================================================== DMA5_IDX_REG ====================================================== */ +/* ===================================================== DMA5_INT_REG ====================================================== */ +/* ===================================================== DMA5_LEN_REG ====================================================== */ +/* =================================================== DMA6_A_START_REG ==================================================== */ +/* =================================================== DMA6_B_START_REG ==================================================== */ +/* ===================================================== DMA6_CTRL_REG ===================================================== */ +/* ===================================================== DMA6_IDX_REG ====================================================== */ +/* ===================================================== DMA6_INT_REG ====================================================== */ +/* ===================================================== DMA6_LEN_REG ====================================================== */ +/* =================================================== DMA7_A_START_REG ==================================================== */ +/* =================================================== DMA7_B_START_REG ==================================================== */ +/* ===================================================== DMA7_CTRL_REG ===================================================== */ +/* ===================================================== DMA7_IDX_REG ====================================================== */ +/* ===================================================== DMA7_INT_REG ====================================================== */ +/* ===================================================== DMA7_LEN_REG ====================================================== */ +/* =================================================== DMA8_A_START_REG ==================================================== */ +/* =================================================== DMA8_B_START_REG ==================================================== */ +/* ===================================================== DMA8_CTRL_REG ===================================================== */ +/* ===================================================== DMA8_IDX_REG ====================================================== */ +/* ===================================================== DMA8_INT_REG ====================================================== */ +/* ===================================================== DMA8_LEN_REG ====================================================== */ +/* =================================================== DMA9_A_START_REG ==================================================== */ +/* =================================================== DMA9_B_START_REG ==================================================== */ +/* ===================================================== DMA9_CTRL_REG ===================================================== */ +/* ===================================================== DMA9_IDX_REG ====================================================== */ +/* ===================================================== DMA9_INT_REG ====================================================== */ +/* ===================================================== DMA9_LEN_REG ====================================================== */ +/* =================================================== DMA_CLEAR_INT_REG =================================================== */ +/* =================================================== DMA_INT_MASK_REG ==================================================== */ +/* ================================================== DMA_INT_STATUS_REG =================================================== */ +/* =================================================== DMA_REQ_MUX2_REG ==================================================== */ +/* =================================================== DMA_REQ_MUX3_REG ==================================================== */ +/* =================================================== DMA_REQ_MUX4_REG ==================================================== */ +/* ==================================================== DMA_REQ_MUX_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ FPLL ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== PLLD_CONFIG_REG ==================================================== */ +/* ===================================================== PLLD_CTRL_REG ===================================================== */ +/* ==================================================== PLLD_FBDIV_REG ===================================================== */ +/* =================================================== PLLD_IRQ_CLR_REG ==================================================== */ +/* =================================================== PLLD_IRQ_MASK_REG =================================================== */ +/* ===================================================== PLLD_IRQ_REG ====================================================== */ +/* ==================================================== PLLD_STATUS_REG ==================================================== */ +/* ===================================================== PLLD_TEST_REG ===================================================== */ +/* =================================================== PLLD_VCO_TRIM_REG =================================================== */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BIST_CTRL_REG ===================================================== */ +/* ===================================================== EMMC_MODE_REG ===================================================== */ +/* =================================================== GPIO_CLK_SEL_REG ==================================================== */ +/* ================================================== GPIO_INT_CLR_P0_REG ================================================== */ +/* ================================================== GPIO_INT_CLR_P1_REG ================================================== */ +/* ================================================== GPIO_INT_POL_P0_REG ================================================== */ +/* ================================================== GPIO_INT_POL_P1_REG ================================================== */ +/* ================================================== GPIO_INT_SEL_P0_REG ================================================== */ +/* ================================================== GPIO_INT_SEL_P1_REG ================================================== */ +/* ================================================== GPIO_INT_STS_P0_REG ================================================== */ +/* ================================================== GPIO_INT_STS_P1_REG ================================================== */ +/* =================================================== GPIO_SEL1_P0_REG ==================================================== */ +/* =================================================== GPIO_SEL1_P1_REG ==================================================== */ +/* ==================================================== GPIO_SEL_P0_REG ==================================================== */ +/* ==================================================== GPIO_SEL_P1_REG ==================================================== */ +/* ==================================================== P0_00_MODE_REG ===================================================== */ +/* ==================================================== P0_01_MODE_REG ===================================================== */ +/* ==================================================== P0_02_MODE_REG ===================================================== */ +/* ==================================================== P0_03_MODE_REG ===================================================== */ +/* ==================================================== P0_04_MODE_REG ===================================================== */ +/* ==================================================== P0_05_MODE_REG ===================================================== */ +/* ==================================================== P0_06_MODE_REG ===================================================== */ +/* ==================================================== P0_07_MODE_REG ===================================================== */ +/* ==================================================== P0_08_MODE_REG ===================================================== */ +/* ==================================================== P0_09_MODE_REG ===================================================== */ +/* ==================================================== P0_10_MODE_REG ===================================================== */ +/* ==================================================== P0_11_MODE_REG ===================================================== */ +/* ==================================================== P0_12_MODE_REG ===================================================== */ +/* ==================================================== P0_13_MODE_REG ===================================================== */ +/* ====================================================== P0_DATA_REG ====================================================== */ +/* =================================================== P0_RESET_DATA_REG =================================================== */ +/* ==================================================== P0_SET_DATA_REG ==================================================== */ +/* ==================================================== P1_00_MODE_REG ===================================================== */ +/* ==================================================== P1_01_MODE_REG ===================================================== */ +/* ==================================================== P1_02_MODE_REG ===================================================== */ +/* ==================================================== P1_03_MODE_REG ===================================================== */ +/* ==================================================== P1_04_MODE_REG ===================================================== */ +/* ==================================================== P1_05_MODE_REG ===================================================== */ +/* ==================================================== P1_06_MODE_REG ===================================================== */ +/* ==================================================== P1_07_MODE_REG ===================================================== */ +/* ==================================================== P1_08_MODE_REG ===================================================== */ +/* ==================================================== P1_09_MODE_REG ===================================================== */ +/* ==================================================== P1_10_MODE_REG ===================================================== */ +/* ==================================================== P1_11_MODE_REG ===================================================== */ +/* ==================================================== P1_12_MODE_REG ===================================================== */ +/* ==================================================== P1_13_MODE_REG ===================================================== */ +/* ==================================================== P1_14_MODE_REG ===================================================== */ +/* ==================================================== P1_15_MODE_REG ===================================================== */ +/* ====================================================== P1_DATA_REG ====================================================== */ +/* =================================================== P1_RESET_DATA_REG =================================================== */ +/* ==================================================== P1_SET_DATA_REG ==================================================== */ +/* ================================================== RAMBIST_ENABLE1_REG ================================================== */ +/* ================================================== RAMBIST_ENABLE2_REG ================================================== */ +/* ================================================== RAMBIST_RESULT1_REG ================================================== */ +/* ================================================== RAMBIST_RESULT2_REG ================================================== */ +/* ================================================== RAMBIST_RESULT3_REG ================================================== */ +/* ================================================== RAMBIST_STATUS1_REG ================================================== */ +/* ================================================== RAMBIST_STATUS2_REG ================================================== */ +/* ================================================== RAMBIST_STATUS3_REG ================================================== */ +/* ================================================== ROMBIST_RESULT_REG =================================================== */ +/* ===================================================== SDIO_MODE_REG ===================================================== */ +/* ===================================================== SW0_MODE_REG ====================================================== */ +/* ===================================================== SW1_MODE_REG ====================================================== */ +/* ====================================================== SW_DATA_REG ====================================================== */ +/* =================================================== SW_RESET_DATA_REG =================================================== */ +/* ==================================================== SW_SET_DATA_REG ==================================================== */ +/* ==================================================== TEST_CTRL2_REG ===================================================== */ +/* ===================================================== TEST_CTRL_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ GPREG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DEBUG_REG ======================================================= */ +/* ===================================================== GP_STATUS_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ HW_ACC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CRC_1_ADDR_MAX_REG =================================================== */ +/* ================================================== CRC_1_ADDR_MIN_REG =================================================== */ +/* =================================================== CRC_1_CAL_VAL_REG =================================================== */ +/* ================================================= CRC_1_CAL_VAL_REV_REG ================================================= */ +/* =================================================== CRC_1_CONFIG_REG ==================================================== */ +/* ==================================================== CRC_1_OP_EN_REG ==================================================== */ +/* ================================================= CRC_1_PSEUDO_VAL_REG ================================================== */ +/* ================================================== CRC_1_REQ_CTRL_REG =================================================== */ +/* ================================================== CRC_1_SEED_VAL_REG =================================================== */ +/* ===================================================== CRC_1_STA_REG ===================================================== */ +/* =================================================== CRC_ADDR_MAX_REG ==================================================== */ +/* =================================================== CRC_ADDR_MIN_REG ==================================================== */ +/* ==================================================== CRC_CAL_VAL_REG ==================================================== */ +/* ================================================== CRC_CAL_VAL_REV_REG ================================================== */ +/* ==================================================== CRC_CONFIG_REG ===================================================== */ +/* ===================================================== CRC_OP_EN_REG ===================================================== */ +/* ================================================== CRC_PSEUDO_VAL_REG =================================================== */ +/* =================================================== CRC_REQ_CTRL_REG ==================================================== */ +/* =================================================== CRC_SEED_VAL_REG ==================================================== */ +/* ====================================================== CRC_STA_REG ====================================================== */ +/* ================================================== HW_CHS_ADDR_MAX_REG ================================================== */ +/* ================================================== HW_CHS_ADDR_MIN_REG ================================================== */ +/* ================================================== HW_CHS_CAL_STA_REG =================================================== */ +/* ================================================== HW_CHS_CAL_VAL_REG =================================================== */ +/* =================================================== HW_CHS_CONFIG_REG =================================================== */ +/* =================================================== HW_CHS_OP_EN_REG ==================================================== */ +/* ================================================= HW_CHS_PSEUDO_VAL_REG ================================================= */ +/* ================================================== HW_CHS_REQ_CTRL_REG ================================================== */ +/* ==================================================== PRNG_OP_EN_REG ===================================================== */ +/* =================================================== PRNG_PAR_TYPE_REG =================================================== */ +/* =================================================== PRNG_REG_CAL_VAL ==================================================== */ +/* =================================================== PRNG_REQ_CLR_REG ==================================================== */ +/* ===================================================== PRNG_SEED_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C_ACK_GENERAL_CALL_REG ================================================ */ +/* ================================================= I2C_CLR_ACTIVITY_REG ================================================== */ +/* ================================================= I2C_CLR_GEN_CALL_REG ================================================== */ +/* =================================================== I2C_CLR_INTR_REG ==================================================== */ +/* ================================================== I2C_CLR_RD_REQ_REG =================================================== */ +/* ================================================== I2C_CLR_RX_DONE_REG ================================================== */ +/* ================================================== I2C_CLR_RX_OVER_REG ================================================== */ +/* ================================================= I2C_CLR_RX_UNDER_REG ================================================== */ +/* ================================================= I2C_CLR_START_DET_REG ================================================= */ +/* ================================================= I2C_CLR_STOP_DET_REG ================================================== */ +/* ================================================== I2C_CLR_TX_ABRT_REG ================================================== */ +/* ================================================== I2C_CLR_TX_OVER_REG ================================================== */ +/* ================================================== I2C_COMP_PARAM1_REG ================================================== */ +/* =================================================== I2C_COMP_TYPE_REG =================================================== */ +/* ================================================= I2C_COMP_VERSION_REG ================================================== */ +/* ====================================================== I2C_CON_REG ====================================================== */ +/* =================================================== I2C_DATA_CMD_REG ==================================================== */ +/* ==================================================== I2C_DMA_CR_REG ===================================================== */ +/* =================================================== I2C_DMA_RDLR_REG ==================================================== */ +/* =================================================== I2C_DMA_TDLR_REG ==================================================== */ +/* ==================================================== I2C_ENABLE_REG ===================================================== */ +/* ================================================= I2C_ENABLE_STATUS_REG ================================================= */ +/* ================================================== I2C_FS_SCL_HCNT_REG ================================================== */ +/* ================================================== I2C_FS_SCL_LCNT_REG ================================================== */ +/* =================================================== I2C_HS_MADDR_REG ==================================================== */ +/* ================================================== I2C_HS_SCL_HCNT_REG ================================================== */ +/* ================================================== I2C_HS_SCL_LCNT_REG ================================================== */ +/* ================================================= I2C_IC_FS_SPKLEN_REG ================================================== */ +/* ================================================= I2C_IC_HS_SPKLEN_REG ================================================== */ +/* =================================================== I2C_INTR_MASK_REG =================================================== */ +/* =================================================== I2C_INTR_STAT_REG =================================================== */ +/* ================================================= I2C_RAW_INTR_STAT_REG ================================================= */ +/* ===================================================== I2C_RXFLR_REG ===================================================== */ +/* ===================================================== I2C_RX_TL_REG ===================================================== */ +/* ====================================================== I2C_SAR_REG ====================================================== */ +/* =================================================== I2C_SDA_HOLD_REG ==================================================== */ +/* =================================================== I2C_SDA_SETUP_REG =================================================== */ +/* ================================================== I2C_SS_SCL_HCNT_REG ================================================== */ +/* ================================================== I2C_SS_SCL_LCNT_REG ================================================== */ +/* ==================================================== I2C_STATUS_REG ===================================================== */ +/* ====================================================== I2C_TAR_REG ====================================================== */ +/* ===================================================== I2C_TXFLR_REG ===================================================== */ +/* ================================================ I2C_TX_ABRT_SOURCE_REG ================================================= */ +/* ===================================================== I2C_TX_TL_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ I2C2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C2_ACK_GENERAL_CALL_REG =============================================== */ +/* ================================================= I2C2_CLR_ACTIVITY_REG ================================================= */ +/* ================================================= I2C2_CLR_GEN_CALL_REG ================================================= */ +/* =================================================== I2C2_CLR_INTR_REG =================================================== */ +/* ================================================== I2C2_CLR_RD_REQ_REG ================================================== */ +/* ================================================= I2C2_CLR_RX_DONE_REG ================================================== */ +/* ================================================= I2C2_CLR_RX_OVER_REG ================================================== */ +/* ================================================= I2C2_CLR_RX_UNDER_REG ================================================= */ +/* ================================================ I2C2_CLR_START_DET_REG ================================================= */ +/* ================================================= I2C2_CLR_STOP_DET_REG ================================================= */ +/* ================================================= I2C2_CLR_TX_ABRT_REG ================================================== */ +/* ================================================= I2C2_CLR_TX_OVER_REG ================================================== */ +/* ================================================= I2C2_COMP_PARAM1_REG ================================================== */ +/* ================================================== I2C2_COMP_TYPE_REG =================================================== */ +/* ================================================= I2C2_COMP_VERSION_REG ================================================= */ +/* ===================================================== I2C2_CON_REG ====================================================== */ +/* =================================================== I2C2_DATA_CMD_REG =================================================== */ +/* ==================================================== I2C2_DMA_CR_REG ==================================================== */ +/* =================================================== I2C2_DMA_RDLR_REG =================================================== */ +/* =================================================== I2C2_DMA_TDLR_REG =================================================== */ +/* ==================================================== I2C2_ENABLE_REG ==================================================== */ +/* ================================================ I2C2_ENABLE_STATUS_REG ================================================= */ +/* ================================================= I2C2_FS_SCL_HCNT_REG ================================================== */ +/* ================================================= I2C2_FS_SCL_LCNT_REG ================================================== */ +/* =================================================== I2C2_HS_MADDR_REG =================================================== */ +/* ================================================= I2C2_HS_SCL_HCNT_REG ================================================== */ +/* ================================================= I2C2_HS_SCL_LCNT_REG ================================================== */ +/* ================================================= I2C2_IC_FS_SPKLEN_REG ================================================= */ +/* ================================================= I2C2_IC_HS_SPKLEN_REG ================================================= */ +/* ================================================== I2C2_INTR_MASK_REG =================================================== */ +/* ================================================== I2C2_INTR_STAT_REG =================================================== */ +/* ================================================ I2C2_RAW_INTR_STAT_REG ================================================= */ +/* ==================================================== I2C2_RXFLR_REG ===================================================== */ +/* ==================================================== I2C2_RX_TL_REG ===================================================== */ +/* ===================================================== I2C2_SAR_REG ====================================================== */ +/* =================================================== I2C2_SDA_HOLD_REG =================================================== */ +/* ================================================== I2C2_SDA_SETUP_REG =================================================== */ +/* ================================================= I2C2_SS_SCL_HCNT_REG ================================================== */ +/* ================================================= I2C2_SS_SCL_LCNT_REG ================================================== */ +/* ==================================================== I2C2_STATUS_REG ==================================================== */ +/* ===================================================== I2C2_TAR_REG ====================================================== */ +/* ==================================================== I2C2_TXFLR_REG ===================================================== */ +/* ================================================ I2C2_TX_ABRT_SOURCE_REG ================================================ */ +/* ==================================================== I2C2_TX_TL_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ KDMA ================ */ +/* =========================================================================================================================== */ + +/* ============================================== KDMA_AHB_HPROT_11_TO_8_REG =============================================== */ +/* =============================================== KDMA_AHB_HPROT_3_TO_0_REG =============================================== */ +/* =============================================== KDMA_AHB_HPROT_7_TO_4_REG =============================================== */ +/* ============================================= KDMA_CFG_DESCRIPTOR_ADDR_REG ============================================== */ +/* ================================================ KDMA_CHANNEL_ENABLE_REG ================================================ */ +/* ==================================================== KDMA_ENABLE_REG ==================================================== */ +/* ================================================= KDMA_IRQ_DONE_CLR_REG ================================================= */ +/* =================================================== KDMA_IRQ_DONE_REG =================================================== */ +/* ================================================ KDMA_IRQ_DONE_TYPE_REG ================================================= */ +/* ================================================= KDMA_IRQ_ERR_CLR_REG ================================================== */ +/* =================================================== KDMA_IRQ_ERR_REG ==================================================== */ +/* ================================================= KDMA_LLI_COUNTER_REG ================================================== */ +/* ==================================================== KDMA_RESET_REG ===================================================== */ +/* ================================================ KDMA_STATUS_COUNTER_REG ================================================ */ +/* ============================================= KDMA_STATUS_DESC_ADDR_PRE_REG ============================================= */ +/* =============================================== KDMA_STATUS_DESC_ADDR_REG =============================================== */ +/* ================================================= KDMA_STATUS_DESC_REG ================================================== */ +/* ==================================================== KDMA_STATUS_REG ==================================================== */ +/* ================================================== KDMA_SW_REQUEST_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ MEMCTRL ================ */ +/* =========================================================================================================================== */ + +/* ================================================== MEMCTRL_AUD_ARB_REG ================================================== */ +/* ================================================= MEMCTRL_CC312_ARB_REG ================================================= */ +/* =============================================== MEMCTRL_CIS_BASE_ADDR_REG =============================================== */ +/* ============================================== MEMCTRL_DYNAMIC_CLK_ON_REG =============================================== */ +/* ================================================ MEMCTRL_MST_CLK_EN_REG ================================================= */ +/* ================================================= MEMCTRL_PRIO_ARB_REG ================================================== */ +/* =================================================== MEMCTRL_STALL_REG =================================================== */ +/* ============================================== MEMCTRL_STATIC_CLK_OFF_REG =============================================== */ +/* ================================================== MEMCTRL_STATUS_REG =================================================== */ +/* ================================================== MEMCTRL_SYS_ARB_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ OQSPIF ================ */ +/* =========================================================================================================================== */ + +/* ================================================== OQSPIF_BURSTBRK_REG ================================================== */ +/* ================================================= OQSPIF_BURSTCMDA_REG ================================================== */ +/* ================================================= OQSPIF_BURSTCMDB_REG ================================================== */ +/* ================================================= OQSPIF_CHCKERASE_REG ================================================== */ +/* ================================================== OQSPIF_CTRLBUS_REG =================================================== */ +/* ================================================== OQSPIF_CTRLMODE_REG ================================================== */ +/* ================================================== OQSPIF_CTR_CTRL_REG ================================================== */ +/* ================================================= OQSPIF_CTR_EADDR_REG ================================================== */ +/* ================================================ OQSPIF_CTR_KEY_0_3_REG ================================================= */ +/* =============================================== OQSPIF_CTR_KEY_12_15_REG ================================================ */ +/* =============================================== OQSPIF_CTR_KEY_16_19_REG ================================================ */ +/* =============================================== OQSPIF_CTR_KEY_20_23_REG ================================================ */ +/* =============================================== OQSPIF_CTR_KEY_24_27_REG ================================================ */ +/* =============================================== OQSPIF_CTR_KEY_28_31_REG ================================================ */ +/* ================================================ OQSPIF_CTR_KEY_4_7_REG ================================================= */ +/* ================================================ OQSPIF_CTR_KEY_8_11_REG ================================================ */ +/* =============================================== OQSPIF_CTR_NONCE_0_3_REG ================================================ */ +/* =============================================== OQSPIF_CTR_NONCE_4_7_REG ================================================ */ +/* ================================================= OQSPIF_CTR_SADDR_REG ================================================== */ +/* ================================================= OQSPIF_DUMMYDATA_REG ================================================== */ +/* ================================================= OQSPIF_ERASECMDA_REG ================================================== */ +/* ================================================= OQSPIF_ERASECMDB_REG ================================================== */ +/* ================================================= OQSPIF_ERASECMDC_REG ================================================== */ +/* ================================================= OQSPIF_ERASECTRL_REG ================================================== */ +/* ===================================================== OQSPIF_GP_REG ===================================================== */ +/* ================================================== OQSPIF_READDATA_REG ================================================== */ +/* ================================================== OQSPIF_RECVDATA_REG ================================================== */ +/* ================================================= OQSPIF_STATUSCMD_REG ================================================== */ +/* =================================================== OQSPIF_STATUS_REG =================================================== */ +/* ================================================= OQSPIF_WRITEDATA_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ OTPC ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== OTPC_MODE_REG ===================================================== */ +/* ===================================================== OTPC_STAT_REG ===================================================== */ +/* ================================================== OTPC_TEST_PWORD_REG ================================================== */ +/* ===================================================== OTPC_TEST_REG ===================================================== */ +/* ===================================================== OTPC_TIM1_REG ===================================================== */ +/* ===================================================== OTPC_TIM2_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ PSK ================ */ +/* =========================================================================================================================== */ + +/* =================================================== PSK_SHA1_CTRL_REG =================================================== */ +/* ================================================== PSK_SHA1_DATA_0_REG ================================================== */ +/* ================================================== PSK_SHA1_DATA_1_REG ================================================== */ +/* ================================================== PSK_SHA1_DATA_2_REG ================================================== */ +/* ================================================== PSK_SHA1_DATA_3_REG ================================================== */ +/* ================================================== PSK_SHA1_DATA_4_REG ================================================== */ +/* ================================================= PSK_SHA1_DIGEST_0_REG ================================================= */ +/* ================================================= PSK_SHA1_DIGEST_1_REG ================================================= */ +/* ================================================= PSK_SHA1_DIGEST_2_REG ================================================= */ +/* ================================================= PSK_SHA1_DIGEST_3_REG ================================================= */ +/* ================================================= PSK_SHA1_DIGEST_4_REG ================================================= */ +/* ================================================== PSK_SHA1_IHV1_0_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV1_1_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV1_2_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV1_3_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV1_4_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV2_0_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV2_1_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV2_2_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV2_3_REG ================================================== */ +/* ================================================== PSK_SHA1_IHV2_4_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ QSPIC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== QSPIC_AWRITECMD_REG ================================================== */ +/* ================================================== QSPIC_BURSTBRK_REG =================================================== */ +/* ================================================== QSPIC_BURSTCMDA_REG ================================================== */ +/* ================================================== QSPIC_BURSTCMDB_REG ================================================== */ +/* ================================================== QSPIC_CHCKERASE_REG ================================================== */ +/* =================================================== QSPIC_CTRLBUS_REG =================================================== */ +/* ================================================== QSPIC_CTRLMODE_REG =================================================== */ +/* ================================================== QSPIC_DUMMYDATA_REG ================================================== */ +/* ================================================== QSPIC_ERASECMDA_REG ================================================== */ +/* ================================================== QSPIC_ERASECMDB_REG ================================================== */ +/* ================================================== QSPIC_ERASECTRL_REG ================================================== */ +/* ===================================================== QSPIC_GP_REG ====================================================== */ +/* =================================================== QSPIC_MEMBLEN_REG =================================================== */ +/* ================================================== QSPIC_READDATA_REG =================================================== */ +/* ================================================== QSPIC_RECVDATA_REG =================================================== */ +/* ================================================== QSPIC_STATUSCMD_REG ================================================== */ +/* =================================================== QSPIC_STATUS_REG ==================================================== */ +/* ================================================== QSPIC_WRITEDATA_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ RETMEMCTRL ================ */ +/* =========================================================================================================================== */ + +/* ============================================= RETMEMCTRL_DYNAMIC_CLK_ON_REG ============================================= */ +/* =============================================== RETMEMCTRL_MST_CLK_EN_REG =============================================== */ +/* ================================================ RETMEMCTRL_PRIO_ARB_REG ================================================ */ +/* ================================================= RETMEMCTRL_STALL_REG ================================================== */ +/* ============================================= RETMEMCTRL_STATIC_CLK_OFF_REG ============================================= */ +/* ================================================= RETMEMCTRL_STATUS_REG ================================================= */ + +/* =========================================================================================================================== */ +/* ================ RFMON ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== RFMON_ADDR_REG ===================================================== */ +/* ================================================== RFMON_CRV_ADDR_REG =================================================== */ +/* =================================================== RFMON_CRV_LEN_REG =================================================== */ +/* ==================================================== RFMON_CTRL_REG ===================================================== */ +/* ===================================================== RFMON_LEN_REG ===================================================== */ +/* ==================================================== RFMON_STAT_REG ===================================================== */ + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== BCFM_IRQ_EN_REG ==================================================== */ +/* ================================================== BCFM_IRQ_STATUS_REG ================================================== */ +/* ==================================================== BCFM_OP_EN_REG ===================================================== */ +/* ================================================== BCFM_OP_STATUS_REG =================================================== */ +/* ================================================= BCFM_REQ_CLR_IRQ_REG ================================================== */ +/* =================================================== BCFM_TOT_CYC_REG ==================================================== */ +/* ==================================================== BOR_CIRCUIT_REG ==================================================== */ +/* ==================================================== CLK_XTAL32K_REG ==================================================== */ +/* ================================================== CNT_BASE_TESTI_REG =================================================== */ +/* ===================================================== CNT_TESTI_REG ===================================================== */ +/* ===================================================== COMP_INT_REG ====================================================== */ +/* =================================================== DCDC_CNTL_OFF_REG =================================================== */ +/* ==================================================== ENABLE_CTRL_REG ==================================================== */ +/* ===================================================== FRC_CNT_0_REG ===================================================== */ +/* ===================================================== FRC_CNT_1_REG ===================================================== */ +/* =================================================== GPIO_WAKEUP0_REG ==================================================== */ +/* =================================================== GPIO_WAKEUP1_REG ==================================================== */ +/* ====================================================== INT_THR_REG ====================================================== */ +/* ================================================= IP4_FLDO_BG_CONT_REG ================================================== */ +/* ==================================================== LDO_ENABLE2_REG ==================================================== */ +/* ==================================================== LDO_ENABLE_REG ===================================================== */ +/* ===================================================== PULSE_CNT_REG ===================================================== */ +/* ====================================================== RCX32K_REG ======================================================= */ +/* ==================================================== READ_STATUS_REG ==================================================== */ +/* =================================================== RTC_ACC_ADDR_REG ==================================================== */ +/* ================================================== RTC_ACC_AUTO_EN_REG ================================================== */ +/* =================================================== RTC_ACC_BUSY_REG ==================================================== */ +/* ================================================== RTC_ACC_OP_TYPE_REG ================================================== */ +/* ==================================================== RTC_ACC_REQ_REG ==================================================== */ +/* =================================================== RTC_ACC_WDATA_REG =================================================== */ +/* ================================================== RTC_CLK_GR_CYC_REG =================================================== */ +/* ==================================================== RTC_CLK_INV_REG ==================================================== */ +/* ===================================================== RTC_EDGE_REG ====================================================== */ +/* ================================================== RTC_EXP_CLR_IRQ_REG ================================================== */ +/* ================================================== RTC_EXP_IRQ_EN_REG =================================================== */ +/* ================================================== RTC_EXP_OP_STS_REG =================================================== */ +/* ==================================================== RTC_EXP_TH0_REG ==================================================== */ +/* ==================================================== RTC_EXP_TH1_REG ==================================================== */ +/* ================================================== RTC_FRC_STATUS_REG =================================================== */ +/* ====================================================== RTC_IF_REG ======================================================= */ +/* ==================================================== RTC_IRQ_EN_REG ===================================================== */ +/* ================================================== RTC_IRQ_STATUS_REG =================================================== */ +/* ==================================================== RTC_MIRROR_REG ===================================================== */ +/* ==================================================== RTC_MR_FRC0_REG ==================================================== */ +/* ==================================================== RTC_MR_FRC1_REG ==================================================== */ +/* ================================================== RTC_MR_SEL_8040_REG ================================================== */ +/* ====================================================== RTC_REQ_REG ====================================================== */ +/* ==================================================== RTM_CONTROL_REG ==================================================== */ +/* ================================================ TEST_ULDO_SLP_CTRL_REG ================================================= */ +/* ===================================================== ULDO_CONT_REG ===================================================== */ +/* =================================================== WAKEUP_CNT_0_REG ==================================================== */ +/* =================================================== WAKEUP_CNT_1_REG ==================================================== */ +/* ================================================== WAKEUP_SRC_CLR_REG =================================================== */ +/* ================================================ WAKEUP_SRC_CLR_SIG_REG ================================================= */ +/* ================================================= WDOG_CNT_BIT_POS_REG ================================================== */ +/* ==================================================== XADC12_CNTL_REG ==================================================== */ +/* =================================================== XADC12_SP_NUM_REG =================================================== */ +/* =================================================== XADC12_THR01_REG ==================================================== */ +/* =================================================== XADC12_THR23_REG ==================================================== */ +/* ================================================= XADC12_TIMER_SET_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ SDEMMC ================ */ +/* =========================================================================================================================== */ + +/* ============================================== SDEMMC_ADMAERRORSTATUS_REG =============================================== */ +/* ============================================= SDEMMC_ADMA_SYS_ADDR_LOW_REG ============================================== */ +/* ============================================ SDEMMC_ADMA_SYS_ADDR_UPPER_REG ============================================= */ +/* ============================================= SDEMMC_AUTOCMDERRORSTATUS_REG ============================================= */ +/* =================================================== SDEMMC_BLOCK_REG ==================================================== */ +/* ============================================= SDEMMC_BOOTTIMEOUT_CTRL__REG ============================================== */ +/* =============================================== SDEMMC_BUFFERDATAPORT_REG =============================================== */ +/* =============================================== SDEMMC_CAPABILITIES0_REG ================================================ */ +/* =============================================== SDEMMC_CAPABILITIES1_REG ================================================ */ +/* =============================================== SDEMMC_DEBUGSELECTION_REG =============================================== */ +/* ============================================ SDEMMC_FORCE_EVENET_ERRSTAT_REG ============================================ */ +/* ============================================= SDEMMC_GLB_ITNR_SIGNAL_EN_REG ============================================= */ +/* ============================================= SDEMMC_GLB_ITNR_STATUS_EN_REG ============================================= */ +/* ============================================== SDEMMC_GLB_ITNR_STATUS_REG =============================================== */ +/* ================================================ SDEMMC_HOST_CTRL_1_REG ================================================= */ +/* ============================================ SDEMMC_MAX_CUR_CAPABILITIES_REG ============================================ */ +/* =========================================== SDEMMC_NORMAL_ITNR_SIGNAL_EN_REG ============================================ */ +/* =========================================== SDEMMC_NORMAL_ITNR_STATUS_EN_REG ============================================ */ +/* ============================================= SDEMMC_NORMAL_ITNR_STATUS_REG ============================================= */ +/* ================================================ SDEMMC_PRESENTSTATE_REG ================================================ */ +/* ================================================ SDEMMC_PRESETVALUE0_REG ================================================ */ +/* ================================================ SDEMMC_PRESETVALUE1_REG ================================================ */ +/* ================================================ SDEMMC_PRESETVALUE2_REG ================================================ */ +/* ================================================ SDEMMC_PRESETVALUE3_REG ================================================ */ +/* ================================================= SDEMMC_RESPONSE0_REG ================================================== */ +/* ================================================= SDEMMC_RESPONSE1_REG ================================================== */ +/* ================================================= SDEMMC_RESPONSE2_REG ================================================== */ +/* ================================================= SDEMMC_RESPONSE3_REG ================================================== */ +/* =========================================== SDEMMC_SDMA_SYS_ADDR__ARGU_2_REG ============================================ */ +/* ============================================== SDEMMC_SHAREDBUS_CTRL__REG =============================================== */ +/* ============================================== SDEMMC_SLOT_ITNR_STATUS_REG ============================================== */ +/* ============================================ SDEMMC_TRANSFERMODE_COMMAND_REG ============================================ */ +/* =================================================== SDEMMC_VENDOR_REG =================================================== */ +/* ================================================== SDEMMC__ARGU_1_REG =================================================== */ +/* ================================================ SDEMMC__CLK__CTRL__REG ================================================= */ + +/* =========================================================================================================================== */ +/* ================ SDIO ================ */ +/* =========================================================================================================================== */ + +/* ============================================= SDIO_ADMA_SYSTEM_ADDRESS_REG ============================================== */ +/* ============================================== SDIO_AHB_FN0_INT_ENABLE_REG ============================================== */ +/* ================================================= SDIO_AHB_FN0_INT_REG ================================================== */ +/* ============================================== SDIO_AHB_FN1_INT_ENABLE_REG ============================================== */ +/* ================================================= SDIO_AHB_FN1_INT_REG ================================================== */ +/* ============================================== SDIO_AHB_SDIOTRANSCOUNT_REG ============================================== */ +/* ================================================ SDIO_AHB_TRANSCOUNT_REG ================================================ */ +/* =================================================== SDIO_ARGUMENT_REG =================================================== */ +/* ==================================================== SDIO_ARM_GP_REG ==================================================== */ +/* =================================================== SDIO_BLKSIZE_REG ==================================================== */ +/* =================================================== SDIO_CARDRDY_REG ==================================================== */ +/* ===================================================== SDIO_CCCR_REG ===================================================== */ +/* =============================================== SDIO_CLK_DELAY_TIMER_REG ================================================ */ +/* ================================================= SDIO_CLOCK_WAKEUP_REG ================================================= */ +/* ================================================= SDIO_CSA_POINTER_REG ================================================== */ +/* ===================================================== SDIO_FBR_REG ====================================================== */ +/* ==================================================== SDIO_FUNRDY_REG ==================================================== */ +/* ================================================= SDIO_GLB_INT_ENA_REG ================================================== */ +/* ================================================= SDIO_GLB_INT_STS_REG ================================================== */ +/* ================================================== SDIO_INTERRUPT_REG =================================================== */ +/* ===================================================== SDIO_IOR_REG ====================================================== */ +/* ================================================= SDIO_IO_ACC_MODE_REG ================================================== */ +/* =============================================== SDIO_LAST_FETCH_ADDR_REG ================================================ */ +/* ===================================================== SDIO_OCR_REG ====================================================== */ +/* ================================================ SDIO_POWER_CONTROL_REG ================================================= */ +/* ================================================= SDIO_POWER_STATE_REG ================================================== */ +/* =================================================== SDIO_RDBLKCNT_REG =================================================== */ +/* =================================================== SDIO_RDDATRDY_REG =================================================== */ +/* ================================================== SDIO_SD_HOST_GP_REG ================================================== */ +/* ================================================= SDIO_SOFT_RST_AHB_REG ================================================= */ +/* ================================================= SDIO_UHS_SUPPORT_REG ================================================== */ +/* =================================================== SDIO_WRBLKCNT_REG =================================================== */ + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SPI_CLOCK_REG ===================================================== */ +/* ==================================================== SPI_CONFIG_REG ===================================================== */ +/* =================================================== SPI_CS_CONFIG_REG =================================================== */ +/* ===================================================== SPI_CTRL_REG ====================================================== */ +/* ================================================== SPI_FIFO_CONFIG_REG ================================================== */ +/* =================================================== SPI_FIFO_READ_REG =================================================== */ +/* ================================================== SPI_FIFO_STATUS_REG ================================================== */ +/* ================================================== SPI_FIFO_WRITE_REG =================================================== */ +/* =================================================== SPI_IRQ_MASK_REG ==================================================== */ +/* ==================================================== SPI_STATUS_REG ===================================================== */ +/* ================================================ SPI_TXBUFFER_FORCE_REG ================================================= */ + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== SPI2_CLOCK_REG ===================================================== */ +/* ==================================================== SPI2_CONFIG_REG ==================================================== */ +/* ================================================== SPI2_CS_CONFIG_REG =================================================== */ +/* ===================================================== SPI2_CTRL_REG ===================================================== */ +/* ================================================= SPI2_FIFO_CONFIG_REG ================================================== */ +/* ================================================== SPI2_FIFO_READ_REG =================================================== */ +/* ================================================= SPI2_FIFO_STATUS_REG ================================================== */ +/* ================================================== SPI2_FIFO_WRITE_REG ================================================== */ +/* =================================================== SPI2_IRQ_MASK_REG =================================================== */ +/* ==================================================== SPI2_STATUS_REG ==================================================== */ +/* ================================================ SPI2_TXBUFFER_FORCE_REG ================================================ */ + +/* =========================================================================================================================== */ +/* ================ SRC_FIFO_IF ================ */ +/* =========================================================================================================================== */ + +/* ================================================= APU_DAI_FIFO_IN1_REG ================================================== */ +/* ================================================= APU_DAI_FIFO_IN2_REG ================================================== */ +/* ================================================= APU_DAI_FIFO_OUT1_REG ================================================= */ +/* ================================================= APU_DAI_FIFO_OUT2_REG ================================================= */ +/* ================================================== APU_FIFO_STATUS_REG ================================================== */ +/* ================================================= APU_SRC_FIFO_IN1_REG ================================================== */ +/* ================================================= APU_SRC_FIFO_IN2_REG ================================================== */ +/* ================================================= APU_SRC_FIFO_OUT1_REG ================================================= */ +/* ================================================= APU_SRC_FIFO_OUT2_REG ================================================= */ + +/* =========================================================================================================================== */ +/* ================ SRC_IF ================ */ +/* =========================================================================================================================== */ + +/* ================================================= APU_DAI_FIFO_CTRL_REG ================================================= */ +/* ================================================ APU_SRC_COEF0A_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF0A_SET2_REG ================================================ */ +/* ================================================ APU_SRC_COEF10_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF10_SET2_REG ================================================ */ +/* ================================================ APU_SRC_COEF32_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF32_SET2_REG ================================================ */ +/* ================================================ APU_SRC_COEF54_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF54_SET2_REG ================================================ */ +/* ================================================ APU_SRC_COEF76_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF76_SET2_REG ================================================ */ +/* ================================================ APU_SRC_COEF98_SET1_REG ================================================ */ +/* ================================================ APU_SRC_COEF98_SET2_REG ================================================ */ +/* =================================================== APU_SRC_CTRL_REG ==================================================== */ +/* ================================================= APU_SRC_FIFO_CTRL_REG ================================================= */ +/* ==================================================== APU_SRC_IN1_REG ==================================================== */ +/* ==================================================== APU_SRC_IN2_REG ==================================================== */ +/* =================================================== APU_SRC_IN_FS_REG =================================================== */ +/* =================================================== APU_SRC_OUT1_REG ==================================================== */ +/* =================================================== APU_SRC_OUT2_REG ==================================================== */ +/* ================================================== APU_SRC_OUT_FS_REG =================================================== */ + +/* =========================================================================================================================== */ +/* ================ SYS_WDOG ================ */ +/* =========================================================================================================================== */ + +/* =================================================== WATCHDOG_CTRL_REG =================================================== */ +/* ===================================================== WATCHDOG_REG ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS ================ */ +/* =========================================================================================================================== */ + +/* =================================================== AHB_DMA_CCLM1_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM2_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM3_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM4_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM5_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM6_REG =================================================== */ +/* =================================================== AHB_DMA_CCLM7_REG =================================================== */ +/* ================================================ AHB_DMA_DFLT_MASTER_REG ================================================ */ +/* ==================================================== AHB_DMA_PL1_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL2_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL3_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL4_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL5_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL6_REG ==================================================== */ +/* ==================================================== AHB_DMA_PL7_REG ==================================================== */ +/* ==================================================== AHB_DMA_TCL_REG ==================================================== */ +/* ================================================== AHB_DMA_VERSION_REG ================================================== */ +/* =================================================== AHB_DMA_WTEN_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ SYSBUS_ICM ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== AHBSYS_ARB_REG ===================================================== */ +/* ====================================================== OTP_ARB_REG ====================================================== */ +/* ==================================================== QSPIRAM_ARB_REG ==================================================== */ + +/* =========================================================================================================================== */ +/* ================ TDES ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CBC_IV_0_REG ====================================================== */ +/* ===================================================== CBC_IV_1_REG ====================================================== */ +/* =================================================== TDES_CBC_CTRL_REG =================================================== */ +/* =================================================== TDES_INPUT_0_REG ==================================================== */ +/* =================================================== TDES_INPUT_1_REG ==================================================== */ +/* ==================================================== TDES_KEY1_0_REG ==================================================== */ +/* ==================================================== TDES_KEY1_1_REG ==================================================== */ +/* ==================================================== TDES_KEY2_0_REG ==================================================== */ +/* ==================================================== TDES_KEY2_1_REG ==================================================== */ +/* ==================================================== TDES_KEY3_0_REG ==================================================== */ +/* ==================================================== TDES_KEY3_1_REG ==================================================== */ +/* =================================================== TDES_OUTPUT_0_REG =================================================== */ +/* =================================================== TDES_OUTPUT_1_REG =================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +/* ================================================ TIMER_CAPTURE_GPIO1_REG ================================================ */ +/* ================================================ TIMER_CAPTURE_GPIO2_REG ================================================ */ +/* ================================================ TIMER_CAPTURE_GPIO3_REG ================================================ */ +/* ================================================ TIMER_CAPTURE_GPIO4_REG ================================================ */ +/* ============================================== TIMER_CLEAR_GPIO_EVENT_REG =============================================== */ +/* =============================================== TIMER_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================== TIMER_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER_CTRL_REG ===================================================== */ +/* ================================================= TIMER_GPIO1_CONF_REG ================================================== */ +/* ================================================= TIMER_GPIO2_CONF_REG ================================================== */ +/* ================================================= TIMER_GPIO3_CONF_REG ================================================== */ +/* ================================================= TIMER_GPIO4_CONF_REG ================================================== */ +/* =============================================== TIMER_ONESHOT_TRIGGER_REG =============================================== */ +/* ================================================ TIMER_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER_PRE_SETTINGS_REG ================================================= */ +/* =============================================== TIMER_PULSE_CNT_CTRL_REG ================================================ */ +/* =============================================== TIMER_PULSE_GPIO_SEL_REG ================================================ */ +/* ================================================== TIMER_PWM_CTRL_REG =================================================== */ +/* ================================================== TIMER_PWM_SYNC_REG =================================================== */ +/* ================================================== TIMER_SETTINGS_REG =================================================== */ +/* ================================================== TIMER_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER_STATUS_REG ==================================================== */ +/* ================================================== TIMER_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER2_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER2_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER2_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER2_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER2_CTRL_REG ==================================================== */ +/* ================================================= TIMER2_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER2_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER2_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER2_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER2_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER2_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER2_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER2_SETTINGS_REG ================================================== */ +/* ================================================= TIMER2_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER2_STATUS_REG =================================================== */ +/* ================================================= TIMER2_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER3_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER3_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER3_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER3_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER3_CTRL_REG ==================================================== */ +/* ================================================= TIMER3_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER3_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER3_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER3_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER3_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER3_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER3_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER3_SETTINGS_REG ================================================== */ +/* ================================================= TIMER3_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER3_STATUS_REG =================================================== */ +/* ================================================= TIMER3_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER4 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER4_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER4_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER4_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER4_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER4_CTRL_REG ==================================================== */ +/* ================================================= TIMER4_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER4_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER4_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER4_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER4_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER4_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER4_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER4_SETTINGS_REG ================================================== */ +/* ================================================= TIMER4_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER4_STATUS_REG =================================================== */ +/* ================================================= TIMER4_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER5 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER5_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER5_CAPTURE_GPIO2_REG ================================================ */ +/* =============================================== TIMER5_CAPTURE_GPIO3_REG ================================================ */ +/* =============================================== TIMER5_CAPTURE_GPIO4_REG ================================================ */ +/* ============================================== TIMER5_CLEAR_GPIO_EVENT_REG ============================================== */ +/* ============================================== TIMER5_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER5_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER5_CTRL_REG ==================================================== */ +/* ================================================= TIMER5_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER5_GPIO2_CONF_REG ================================================= */ +/* ================================================= TIMER5_GPIO3_CONF_REG ================================================= */ +/* ================================================= TIMER5_GPIO4_CONF_REG ================================================= */ +/* ============================================== TIMER5_ONESHOT_TRIGGER_REG =============================================== */ +/* =============================================== TIMER5_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER5_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER5_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER5_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER5_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER5_PWM_SYNC_REG ================================================== */ +/* ================================================== TIMER5_SETTINGS_REG ================================================== */ +/* ================================================= TIMER5_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER5_STATUS_REG =================================================== */ +/* ================================================= TIMER5_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER6 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER6_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER6_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER6_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER6_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER6_CTRL_REG ==================================================== */ +/* ================================================= TIMER6_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER6_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER6_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER6_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER6_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER6_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER6_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER6_SETTINGS_REG ================================================== */ +/* ================================================= TIMER6_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER6_STATUS_REG =================================================== */ +/* ================================================= TIMER6_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER7 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER7_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER7_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER7_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER7_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER7_CTRL_REG ==================================================== */ +/* ================================================= TIMER7_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER7_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER7_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER7_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER7_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER7_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER7_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER7_SETTINGS_REG ================================================== */ +/* ================================================= TIMER7_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER7_STATUS_REG =================================================== */ +/* ================================================= TIMER7_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ TIMER8 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER8_CAPTURE_GPIO1_REG ================================================ */ +/* =============================================== TIMER8_CAPTURE_GPIO2_REG ================================================ */ +/* ============================================== TIMER8_CLEAR_IRQ_PULSE_REG =============================================== */ +/* ================================================= TIMER8_CLEAR_IRQ_REG ================================================== */ +/* ==================================================== TIMER8_CTRL_REG ==================================================== */ +/* ================================================= TIMER8_GPIO1_CONF_REG ================================================= */ +/* ================================================= TIMER8_GPIO2_CONF_REG ================================================= */ +/* =============================================== TIMER8_PRESCALER_VAL_REG ================================================ */ +/* ================================================ TIMER8_PRE_SETTINGS_REG ================================================ */ +/* =============================================== TIMER8_PULSE_CNT_CTRL_REG =============================================== */ +/* =============================================== TIMER8_PULSE_GPIO_SEL_REG =============================================== */ +/* ================================================== TIMER8_PWM_CTRL_REG ================================================== */ +/* ================================================== TIMER8_SETTINGS_REG ================================================== */ +/* ================================================= TIMER8_SHOTWIDTH_REG ================================================== */ +/* =================================================== TIMER8_STATUS_REG =================================================== */ +/* ================================================= TIMER8_TIMER_VAL_REG ================================================== */ + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== UART_CR_REG ====================================================== */ +/* ==================================================== UART_DMACR_REG ===================================================== */ +/* ====================================================== UART_DR_REG ====================================================== */ +/* ===================================================== UART_FBRD_REG ===================================================== */ +/* ====================================================== UART_FR_REG ====================================================== */ +/* ===================================================== UART_IBRD_REG ===================================================== */ +/* ===================================================== UART_ICR_REG ====================================================== */ +/* ===================================================== UART_IFLS_REG ===================================================== */ +/* ===================================================== UART_IMSC_REG ===================================================== */ +/* ==================================================== UART_LCR_H_REG ===================================================== */ +/* ===================================================== UART_MIS_REG ====================================================== */ +/* ===================================================== UART_RIS_REG ====================================================== */ +/* =================================================== UART_RS485EN_REG ==================================================== */ +/* ===================================================== UART_RSR_REG ====================================================== */ +/* ===================================================== UART_SWFC_REG ===================================================== */ +/* ====================================================== UART_WA_REG ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART2_CR_REG ====================================================== */ +/* ==================================================== UART2_DMACR_REG ==================================================== */ +/* ===================================================== UART2_DR_REG ====================================================== */ +/* ==================================================== UART2_FBRD_REG ===================================================== */ +/* ===================================================== UART2_FR_REG ====================================================== */ +/* ==================================================== UART2_IBRD_REG ===================================================== */ +/* ===================================================== UART2_ICR_REG ===================================================== */ +/* ==================================================== UART2_IFLS_REG ===================================================== */ +/* ==================================================== UART2_IMSC_REG ===================================================== */ +/* ==================================================== UART2_LCR_H_REG ==================================================== */ +/* ===================================================== UART2_MIS_REG ===================================================== */ +/* ===================================================== UART2_RIS_REG ===================================================== */ +/* =================================================== UART2_RS485EN_REG =================================================== */ +/* ===================================================== UART2_RSR_REG ===================================================== */ +/* ==================================================== UART2_SWFC_REG ===================================================== */ +/* ===================================================== UART2_WA_REG ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART3_CR_REG ====================================================== */ +/* ==================================================== UART3_DMACR_REG ==================================================== */ +/* ===================================================== UART3_DR_REG ====================================================== */ +/* ==================================================== UART3_FBRD_REG ===================================================== */ +/* ===================================================== UART3_FR_REG ====================================================== */ +/* ==================================================== UART3_IBRD_REG ===================================================== */ +/* ===================================================== UART3_ICR_REG ===================================================== */ +/* ==================================================== UART3_IFLS_REG ===================================================== */ +/* ==================================================== UART3_IMSC_REG ===================================================== */ +/* ==================================================== UART3_LCR_H_REG ==================================================== */ +/* ===================================================== UART3_MIS_REG ===================================================== */ +/* ===================================================== UART3_RIS_REG ===================================================== */ +/* =================================================== UART3_RS485EN_REG =================================================== */ +/* ===================================================== UART3_RSR_REG ===================================================== */ +/* ==================================================== UART3_SWFC_REG ===================================================== */ +/* ===================================================== UART3_WA_REG ====================================================== */ + +/** @} */ /* End of group EnumValue_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* DA1640X_H */ + +/** @} */ /* End of group DA1640x */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 000000000000..878526080a9f --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,202 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if BSP_MCU_GROUP_RA0E1 + #include "R7FA0E107.h" + #elif BSP_MCU_GROUP_RA0E2 + #include "R7FA0E209.h" + #elif BSP_MCU_GROUP_RA0L1 + #include "R7FA0L107.h" + #elif BSP_MCU_GROUP_RA2A1 + #include "R7FA2A1AB.h" + #elif BSP_MCU_GROUP_RA2A2 + #include "R7FA2A2AD.h" + #elif BSP_MCU_GROUP_RA2E1 + #include "R7FA2E1A9.h" + #elif BSP_MCU_GROUP_RA2E2 + #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2E3 + #include "R7FA2E307.h" + #elif BSP_MCU_GROUP_RA2L1 + #include "R7FA2L1AB.h" + #elif BSP_MCU_GROUP_RA2L2 + #include "R7FA2L209.h" + #elif BSP_MCU_GROUP_RA2T1 + #include "R7FA2T107.h" + #elif BSP_MCU_GROUP_RA4C1 + #include "R7FA4C1BD.h" + #elif BSP_MCU_GROUP_RA4E1 + #include "R7FA4E10D.h" + #elif BSP_MCU_GROUP_RA4E2 + #include "R7FA4E2B9.h" + #elif BSP_MCU_GROUP_RA4M1 + #include "R7FA4M1AB.h" + #elif BSP_MCU_GROUP_RA4M2 + #include "R7FA4M2AD.h" + #elif BSP_MCU_GROUP_RA4M3 + #include "R7FA4M3AF.h" + #elif BSP_MCU_GROUP_RA4T1 + #include "R7FA4T1BB.h" + #elif BSP_MCU_GROUP_RA4W1 + #include "R7FA4W1AD.h" + #elif BSP_MCU_GROUP_RA4L1 + #include "R7FA4L1BD.h" + #elif BSP_MCU_GROUP_RA6E1 + #include "R7FA6E10F.h" + #elif BSP_MCU_GROUP_RA6E2 + #include "R7FA6E2BB.h" + #elif BSP_MCU_GROUP_RA6M1 + #include "R7FA6M1AD.h" + #elif BSP_MCU_GROUP_RA6M2 + #include "R7FA6M2AF.h" + #elif BSP_MCU_GROUP_RA6M3 + #include "R7FA6M3AH.h" + #elif BSP_MCU_GROUP_RA6M4 + #include "R7FA6M4AF.h" + #elif BSP_MCU_GROUP_RA6M5 + #include "R7FA6M5BH.h" + #elif BSP_MCU_GROUP_RA6T1 + #include "R7FA6T1AD.h" + #elif BSP_MCU_GROUP_RA6T2 + #include "R7FA6T2BD.h" + #elif BSP_MCU_GROUP_RA6T3 + #include "R7FA6T3BB.h" + #elif BSP_MCU_GROUP_RA8D1 + #include "R7FA8D1BH.h" + #elif BSP_MCU_GROUP_RA8E1 + #include "R7FA8E1AF.h" + #elif BSP_MCU_GROUP_RA8E2 + #include "R7FA8E2AF.h" + #elif BSP_MCU_GROUP_RA8M1 + #include "R7FA8M1AH.h" + #elif BSP_MCU_GROUP_RA8P1 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8T1 + #include "R7FA8T1AH.h" + #elif BSP_MCU_GROUP_RA8T2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA6B1 + #if defined(BOARD_RA6B1_PRODK) + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/R7KA6B1BG.h" + #else + #if __has_include("../../../../../bsp/cmsis/Device/RENESAS/Include/D3108BA.h") + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/D3108BA.h" + #else + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/R7KA6B1BG.h" + #endif + #endif + #elif BSP_MCU_GROUP_RA6W1 + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/R7SA6W1CE.h" + #elif BSP_MCU_GROUP_RA6W3 + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/R7SA6W3xx.h" + #elif BSP_MCU_GROUP_RA6B2 + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/D3333.h" + #elif BSP_MCU_GROUP_RA6U1 + #if defined(BOARD_RA6U1_EK) + #include "../../../../../bsp/cmsis/Device/RENESAS/Include/R7KA6U1BG.h" + #endif + #else + #if __has_include("renesas_internal.h") + #include "renesas_internal.h" + #else + #warning "Unsupported MCU" + #endif + #endif + +/* + * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB + * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 + * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: + * + * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | + * |-----------|------------|------------------------| + * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | + * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | + * + * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ + * + * IAR is currently the only toolchain producing the correct __ARM_ARCH value. + * + *- See https://github.com/ARM-software/CMSIS_6/issues/159 + */ + #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 + #undef __ARM_ARCH + #define __ARM_ARCH 801 + #endif + + #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M4 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) + #define RENESAS_CORTEX_M23 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M33 + #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M85 + #else + #warning Unsupported Architecture + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 000000000000..30afe29e7e06 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 000000000000..bf21731c5216 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,316 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_TZ_SECURE_BUILD + #define BSP_TZ_STACK_SEAL_SIZE (8U) +#else + #define BSP_TZ_STACK_SEAL_SIZE (0U) +#endif + +#define BSP_PRV_MAGIC_WORD_ADDR (0x23010000) +#define BSP_PRV_MAGIC_WORD_0 (0xDEADBEEF) +#define BSP_PRV_MAGIC_WORD_1 (0xDEAD10CC) +#define BSP_PRV_DBG_DELAY_ITER (0x15000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Defines function pointers to be used with vector table. */ +typedef void (* exc_ptr_t)(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Default_Handler(void); +void Reset_Handler(void); + +#if defined(__ICCARM__) +extern void __iar_program_start(void); + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) +extern void _start(void); +static void bsp_gcc_call_init_array(void); + +#endif + +#if (!BSP_TZ_NONSECURE_BUILD) && (BSP_CFG_STARTUP_MAGIC_CHECK) +static void bsp_debugger_attach_poll(void); + +#endif + +#if (BSP_CFG_IVT_COPY_ENABLE) +static void bsp_vector_table_copy(void); + +#endif + +#if (BSP_CFG_WAKEUP_RESET_HANDLER_ENABLE) +BSP_PLACE_CODE_IN_RAM static void Wakeup_Reset_Handler(void); +static void bsp_wakeup_reset_handler_set(void); + +#endif + +/*******************************************************************************************************************//** + * MCU starts executing here out of reset. Main stack pointer is set up already. + **********************************************************************************************************************/ +void Reset_Handler (void) +{ +#if (!BSP_TZ_NONSECURE_BUILD) && (BSP_CFG_STARTUP_MAGIC_CHECK) + bsp_debugger_attach_poll(); +#endif + +#if (BSP_CFG_IVT_COPY_ENABLE) + bsp_vector_table_copy(); +#endif + +#if (BSP_CFG_WAKEUP_RESET_HANDLER_ENABLE) + bsp_wakeup_reset_handler_set(); +#endif + + /* Initialize system using BSP. */ + SystemInit(); + +#if defined(__ICCARM__) + __iar_program_start(); +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + bsp_gcc_call_init_array(); + extern int entry(void); + entry(); +#endif + + while (1) + { + /* Infinite Loop. */ + } +} + +/*******************************************************************************************************************//** + * Run init array entries without invoking newlib _start(). + **********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +static void bsp_gcc_call_init_array (void) +{ + extern void (* __preinit_array_start[])(void); + extern void (* __preinit_array_end[])(void); + extern void (* __init_array_start[])(void); + extern void (* __init_array_end[])(void); + + for (void (** p_func)(void) = __preinit_array_start; p_func < __preinit_array_end; p_func++) + { + (*p_func)(); + } + + for (void (** p_func)(void) = __init_array_start; p_func < __init_array_end; p_func++) + { + (*p_func)(); + } +} + +#endif + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1; + + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); + + while (1) + { + __NOP(); + } + + ; +} + +/* Main stack */ +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* Heap */ +BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle + * these exceptions in their code they should define their own function with the same name. + */ +#if defined(__ICCARM__) + #define WEAK_REF_ATTRIBUTE + + #pragma weak NMI_Handler = Default_Handler + #pragma weak MemManage_Handler = Default_Handler + #pragma weak BusFault_Handler = Default_Handler + #pragma weak UsageFault_Handler = Default_Handler + #pragma weak SecureFault_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak DebugMon_Handler = Default_Handler + #pragma weak PendSV_Handler = Default_Handler + #pragma weak SysTick_Handler = Default_Handler +#elif defined(__GNUC__) + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void HardFault_Handler(void); // Implemented in ARM assembly. +void NMI_Handler(void) WEAK_REF_ATTRIBUTE; +void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; +void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; +void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; +void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; +void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; + +/* Vector table. */ +BSP_DONT_REMOVE const exc_ptr_t __VECTOR_TABLE[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION( + BSP_SECTION_FIXED_VECTORS) = +{ + (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ +}; + +#if BSP_CFG_IVT_COPY_ENABLE +BSP_DONT_REMOVE exc_ptr_t RAM_VECTOR_TABLE_COPY[BSP_VECTOR_TABLE_MAX_ENTRIES] BSP_PLACE_IN_SECTION( + ".fsp_vector_table_copy"); +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION( + BSP_SECTION_APPLICATION_VECTORS) __attribute__((weak)); + +/*******************************************************************************************************************//** + * Relocate the vector table to RAM. Substitute the Reset_Handler with the Wakeup_Reset_Handler for low power mode + * support. + **********************************************************************************************************************/ +static void bsp_vector_table_copy (void) +{ + if (((uint32_t) RAM_VECTOR_TABLE_COPY) != SCB->VTOR) + { + /* Copy Vector Table to allocated space in RAM. */ + for (uint8_t it = 0; it < BSP_CORTEX_VECTOR_TABLE_ENTRIES; it++) + { + RAM_VECTOR_TABLE_COPY[it] = __VECTOR_TABLE[it]; + } + + for (uint8_t it = 0; it < BSP_ICU_VECTOR_MAX_ENTRIES; it++) + { + RAM_VECTOR_TABLE_COPY[BSP_CORTEX_VECTOR_TABLE_ENTRIES + it] = g_vector_table[it]; + } + + /* Update VTOR value. */ + SCB->VTOR = ((uint32_t) RAM_VECTOR_TABLE_COPY); + + #if !BSP_TZ_NONSECURE_BUILD + SYSB->INITSVTOR_REG = ((uint32_t) RAM_VECTOR_TABLE_COPY); + #else + SYSB->INITNSVTOR_REG = ((uint32_t) RAM_VECTOR_TABLE_COPY); + #endif + } +} + +#endif + +#if (BSP_CFG_WAKEUP_RESET_HANDLER_ENABLE) + +void wakeup_from_deepsleep(void); + +BSP_PLACE_CODE_IN_RAM static void Wakeup_Reset_Handler (void) +{ + /* If this register is zeroed then this is a wakeup from deepsleep. + * Otherwise it is a cold boot. + */ + if (CRG_TOP->RESET_STAT_REG != 0) + { + Reset_Handler(); + } + else + { + /* Call to assembly function that will restore the state of the SYSCPU. */ + wakeup_from_deepsleep(); + + /* Wakeup from deepsleep returns execution to the function that called sleep. + * This should not be reached. + */ + BSP_CHECK_FATAL(0); + } +} + +static void bsp_wakeup_reset_handler_set (void) +{ + uint32_t * p_vector_table = (uint32_t *) SCB->VTOR; + + p_vector_table[1] = (uint32_t) Wakeup_Reset_Handler; +} + +#endif + +#if (!BSP_TZ_NONSECURE_BUILD) && (BSP_CFG_STARTUP_MAGIC_CHECK) + +/*******************************************************************************************************************//** + * Block execution until a debugger is attached if certain magic words are located in RAM. + **********************************************************************************************************************/ +static void bsp_debugger_attach_poll (void) +{ + volatile uint32_t * p_magic = (uint32_t *) BSP_PRV_MAGIC_WORD_ADDR; + + if ((BSP_PRV_MAGIC_WORD_0 == p_magic[0]) && + (BSP_PRV_MAGIC_WORD_0 == p_magic[1]) && + (BSP_PRV_MAGIC_WORD_0 == p_magic[2]) && + (BSP_PRV_MAGIC_WORD_1 == p_magic[3])) + { + uint32_t debug_setting = CRG_TOP->SYS_CTRL_REG; + + /* Enable debugger. */ + CRG_TOP->SYS_CTRL_REG = debug_setting | CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk; + + /* Refresh Watchdog */ + WDTSYS->WDTSYS_REG = 0xFF; + + for (volatile uint32_t it = BSP_PRV_DBG_DELAY_ITER; it > 0; it--) + { + ; + } + + /* Clear magic so that this is skipped in the event of a SW reset. */ + p_magic[0] = 0; + + CRG_TOP->SYS_CTRL_REG = debug_setting; + } +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 000000000000..bc849f109a5f --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,721 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Mask to select CP bits( 0xF00000 ) */ +#define CP_MASK (0xFU << 20) + +/* Key code for writing PRCR register. */ +#if defined(__ICCARM__) + #ifndef __Vectors + #define __Vectors __vector_table + #endif +#endif +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5) + +#if defined(GPREG_DEBUG_REG_ETM_TRACE_MAP_ON_PINS_EN_Msk) + #define ETM_TRACE_ENABLE (GPREG->DEBUG_REG_b.ETM_TRACE_MAP_ON_PINS_EN) +#elif defined(GPREG_DEBUG_REG_ETM_ITM_TRACE_MAP_ON_PINS_EN_Msk) + #define ETM_TRACE_ENABLE (GPREG->DEBUG_REG_b.ETM_ITM_TRACE_MAP_ON_PINS_EN) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; +uint32_t g_bsp_reset_stat_reg BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +/* Initialize static constructors */ +#if defined(__ARMCC_VERSION) +extern void (* Image$$INIT_ARRAY$$Base[])(void); +extern void (* Image$$INIT_ARRAY$$Limit[])(void); +#elif defined(__GNUC__) + +extern void (* __init_array_start[])(void); + +extern void (* __init_array_end[])(void); +#elif defined(__ICCARM__) +extern void __call_ctors(void const *, void const *); + + #pragma section = "SHT$$PREINIT_ARRAY" const + #pragma section = "SHT$$INIT_ARRAY" const +#endif + +extern void * __VECTOR_TABLE[]; +extern uint8_t g_main_stack[]; + +extern void R_BSP_SecurityInit(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit(void); + +#endif + +#if defined(__ICCARM__) + +void R_BSP_WarmStart(bsp_warm_start_event_t event); + + #pragma weak R_BSP_WarmStart + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +#if BSP_CFG_EARLY_INIT +static void bsp_init_uninitialized_vars(void); + +#endif + +__STATIC_FORCEINLINE void bsp_debugger_enable(void); +__STATIC_FORCEINLINE void bsp_clock_div_early_init(void); +__STATIC_FORCEINLINE void bsp_etm_trace_setup(void); +static void SystemRuntimeInit(const uint32_t external); + +#if !BSP_TZ_NONSECURE_BUILD +__STATIC_FORCEINLINE void bsp_sys_force_active(void); +__STATIC_FORCEINLINE void bsp_power_domains_early_init(void); +__STATIC_FORCEINLINE void bsp_mem_retain_early_init(void); +static void bsp_rails_early_init(void); + +#endif + +BSP_WEAK_REFERENCE __NO_RETURN void _exit(int __status); + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ + /** In Trustzone enabled project the g_bsp_reset_stat_reg is updated exclusively from the S application, + * which is executed first. The g_bsp_reset_stat_reg status can be read by NS application by calling the + * R_BSP_ResetStatusGet() + */ +#if !BSP_TZ_NONSECURE_BUILD + g_bsp_reset_stat_reg = CRG_TOP->RESET_STAT_REG; + CRG_TOP->RESET_STAT_REG = 0; +#endif + +#if __FPU_USED + + /* Enable the FPU only when it is used. + * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ + + /* Set bits 20-23 (CP10 and CP11) to enable FPU. */ + SCB->CPACR = (uint32_t) CP_MASK; + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + FPU->FPCCR |= (FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Seal the main stack for secure projects. Reference: + * https://developer.arm.com/documentation/100720/0300 + * https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */ + uint32_t * p_main_stack_top = (uint32_t *) __Vectors[0]; + *p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE; +#endif + +#if BSP_CFG_EARLY_INIT + + /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */ + bsp_init_uninitialized_vars(); +#endif + + bsp_prv_halt_implementation_early_set(); + + /* TODO: Remove guard when device info is ready for other RAfW boards as well. */ +#if BSP_MCU_GROUP_RA6W1 + + /* Populate device information attributes. */ + BSP_CHECK_DEBUG(bsp_device_info_init()); +#endif + + bsp_debugger_enable(); + + /* Call pre clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + + /* + * Setup the dividers for HCLK and PCLK defined by the user. + */ + bsp_clock_div_early_init(); + +#if 0 + + // TODO: Identify whether this code will be executed. If yes, then implement this function properly + // for all RAfW devices. + + /* + * Check that the firmware and the chip that it runs on are compatible with each other. + */ + BSP_CHECK_DEBUG(bsp_device_info_compatibility_check()); +#endif + + SystemRuntimeInit(0); +#if !BSP_FEATURE_FLASH_IS_INTERNAL + + /* TODO: Consider case where we also have some external PSRAM, that + * has not been properly setup to be transparent for reads/writes. + * In this case RAM variables present in that memory are never initialized, + * or a BusFault occurs here. + */ + SystemRuntimeInit(1); +#endif + +#if !BSP_TZ_NONSECURE_BUILD + bsp_sys_force_active(); + + bsp_rails_early_init(); + + bsp_power_domains_early_init(); + + bsp_mem_retain_early_init(); +#endif + + bsp_etm_trace_setup(); + +#if BSP_TZ_CFG_SKIP_INIT + + /* Initialize clock variables to be used with R_BSP_SoftwareDelay. */ + bsp_clock_freq_var_init(); +#else + #ifdef BSP_PRV_TCS_HANDLING_READY + + /* Apply TCS values before initializing clocks */ + bsp_prv_tcs_init(); + #endif + + /* Configure system clocks. */ + bsp_clock_init(); +#endif + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + #if 33U == __CORTEX_M + + /* Use CM33 stack monitor. */ + __set_MSPLIM(BSP_PRV_STACK_LIMIT); + #else + #endif +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Initialize security features. */ + R_BSP_SecurityInit(); +#endif + + /* Initialize ELC events that will be used to trigger NVIC interrupts. */ + bsp_irq_cfg(); +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module + * is not in use. + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit (void) +{ + volatile uint8_t read_port = 0U; + FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning + + /* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example + * of initial setting flow for an unused circuit") */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Enable TRNG function (disable stop function) */ + #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2 + R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_BSP_HAS_SCE5 + R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Wait for at least 3 PCLKB cycles */ + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + + /* Disable TRNG function */ + #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2 + R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_BSP_HAS_SCE5 + R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example + * of initial setting flow for an unused circuit") */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +} + +#endif + +#if BSP_CFG_EARLY_INIT + +/*******************************************************************************************************************//** + * Initialize BSP variables not handled by C runtime startup. + **********************************************************************************************************************/ +static void bsp_init_uninitialized_vars (void) +{ + g_protect_pfswe_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) + { + g_protect_counters[i] = 0; + } + + extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[]; + for (uint32_t i = 0; i < 16; i++) + { + g_bsp_group_irq_sources[i] = 0; + } + + #if BSP_CFG_EARLY_INIT + + /* Set SystemCoreClock to MOCO */ + SystemCoreClock = BSP_RCLP_HZ; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Fallback weak implemenation of _exit(), which just hangs. + **********************************************************************************************************************/ +void _exit (int __status) +{ + FSP_PARAMETER_NOT_USED(__status); + while (1) + { + ; + } +} + +#if defined(__GNUC__) + +// TIN_HACK_WIFI + #ifdef BSP_MCU_GROUP_RA6W1 +BSP_WEAK_REFERENCE extern int _read(int fd, char * ptr, int len); +BSP_WEAK_REFERENCE extern int _write(int fd, char * ptr, int len); + +/*******************************************************************************************************************//** + * Stub to override _read(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE int _read (int fd, char * ptr, int len) +{ + FSP_PARAMETER_NOT_USED(fd); + FSP_PARAMETER_NOT_USED(ptr); + FSP_PARAMETER_NOT_USED(len); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _write(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE int _write (int fd, char * ptr, int len) +{ + FSP_PARAMETER_NOT_USED(fd); + FSP_PARAMETER_NOT_USED(ptr); + FSP_PARAMETER_NOT_USED(len); + + return -1; +} + + #else +extern _ssize_t _read_r(struct _reent * _reent, int _fd, void * _buff, size_t _cnt); + +/*******************************************************************************************************************//** + * Stub to override _read_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +_ssize_t _read_r (struct _reent * _reent, int _fd, void * _buff, size_t _cnt) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_fd); + FSP_PARAMETER_NOT_USED(_buff); + FSP_PARAMETER_NOT_USED(_cnt); + + return -1; +} + + #endif + +#if 0 +extern _off_t _lseek_r(struct _reent * _reent, int _fdes, _off_t _off, int _w); +extern int _kill_r(void * _reent, int _pid, int _signal); +extern int _getpid_r(void * _reent); +extern int _gettimeofday_r(void * _reent, void * _tp, void * _tzp); + + #if 0 + +struct stat; + +BSP_WEAK_REFERENCE extern int _open_r(struct _reent * _reent, const char * _path, int _flag, int _m); +BSP_WEAK_REFERENCE extern int _fstat_r(struct _reent * _reent, int _fd, struct stat * _buff); +BSP_WEAK_REFERENCE extern int _isatty_r(struct _reent * _reent, int _fd); +BSP_WEAK_REFERENCE extern int _close_r(struct _reent * _reent, int _fd); +BSP_WEAK_REFERENCE extern int _link_r(struct _reent * _reent, const char * _oldpath, const char * _newpath); +BSP_WEAK_REFERENCE extern int _unlink_r(struct _reent * _reent, const char * _path); + + #endif + +/*******************************************************************************************************************//** + * Stub to override _lseek_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +_off_t _lseek_r (struct _reent * _reent, int _fdes, _off_t _off, int _w) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_fdes); + FSP_PARAMETER_NOT_USED(_off); + FSP_PARAMETER_NOT_USED(_w); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _kill_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _kill_r (void * _reent, int _pid, int _signal) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_pid); + FSP_PARAMETER_NOT_USED(_signal); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _getpid_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _getpid_r (void * _reent) +{ + FSP_PARAMETER_NOT_USED(_reent); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _gettimeofday_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _gettimeofday_r (void * _reent, void * _tp, void * _tzp) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_tp); + FSP_PARAMETER_NOT_USED(_tzp); + + return -1; +} +#endif + + #if 0 + +/*******************************************************************************************************************//** + * Stub to override _open_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _open_r (struct _reent * _reent, const char * _path, int _flag, int _m) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_path); + FSP_PARAMETER_NOT_USED(_flag); + FSP_PARAMETER_NOT_USED(_m); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _fstat_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _fstat_r (struct _reent * _reent, int _fd, struct stat * _buff) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_fd); + FSP_PARAMETER_NOT_USED(_buff); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _isatty_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _isatty_r (struct _reent * _reent, int _fd) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_fd); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _close_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _close_r (struct _reent * _reent, int _fd) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_fd); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _link_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _link_r (struct _reent * _reent, const char * _oldpath, const char * _newpath) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_oldpath); + FSP_PARAMETER_NOT_USED(_newpath); + + return -1; +} + +/*******************************************************************************************************************//** + * Stub to override _unlink_r(), to silence a link warning when using recent gcc + **********************************************************************************************************************/ +int _unlink_r (struct _reent * _reent, const char * _path) +{ + FSP_PARAMETER_NOT_USED(_reent); + FSP_PARAMETER_NOT_USED(_path); + + return -1; +} + + #endif +#endif + +#if defined(__GNUC__) || defined(__ICCARM__) +__STATIC_FORCEINLINE void bsp_debugger_enable (void) +{ + #if BSP_CFG_DEBUGGER_ENABLE + CRG_TOP->SYS_CTRL_REG |= CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk; + #endif + + #if (BSP_CFG_CMAC_DEBUGGER_ENABLE) + CRG_TOP->SYS_CTRL_REG |= CRG_TOP_SYS_CTRL_REG_CMAC_DEBUGGER_ENABLE_Msk; + #endif +} + +__STATIC_FORCEINLINE void bsp_clock_div_early_init (void) +{ + uint32_t val = CRG_TOP->CLK_AMBA_REG; + + #if BSP_FEATURE_CGC_HAS_HCLK_DIV + FSP_REG_VAR_FIELD_SET(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, val, BSP_CFG_HCLK_DIV); + #endif + + #if BSP_FEATURE_CGC_HAS_PCLK_DIV + FSP_REG_VAR_FIELD_SET(CRG_TOP, CLK_AMBA_REG, PCLK_DIV, val, BSP_CFG_PCLK_DIV); + #endif + + CRG_TOP->CLK_AMBA_REG = val; +} + + #if !BSP_TZ_NONSECURE_BUILD +__STATIC_FORCEINLINE void bsp_sys_force_active (void) +{ + #if defined(CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos) + CRG_TOP->PMU_CTRL_REG_b.SYS_SLEEP = 0; + #endif +} + +static void bsp_rails_early_init (void) +{ + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6B2 || BSP_MCU_GROUP_RA6U1 + + /* XXX Setup rails based on HW recommendations (unchanged for RA6B1/RA6U1) */ + PMU_ANA->POWER_CTRL_REG_b.V18_ENABLE = 0x1; + PMU_ANA->POWER_CTRL_REG_b.VDD_ENABLE = 0x2; + + #ifndef BSP_MCU_GROUP_RA6B2 + PMU_ANA->POWER_CTRL_REG_b.V10_ENABLE = 0x2; + PMU_ANA->POWER_CTRL_REG_b.LDO_ANA_ENABLE = 0x1; + #endif + + /* V18EXT is not enabled since it is tied to a HW issue where the current required by all rails + * cannot be provided and the device crashes. The rail is only used by the external QSPI memory, + * and should only be enabled when that is used. + */ + #elif BSP_MCU_GROUP_RA6W1 + + /** + * TIN-TODO: Identify whether these are always needed or if we should only enable them for PLL. + * There is an issue with the external flash when the PLL clock is selected in Tin and the + * workaround to the HW bug is to increase the current provided to the pads. + * TIN-TODO: It is unclear why the clock for the DMA is enabled as well. + *//* Set QSPI pads drive current to 8 mA. Default was 2 mA. */ + OQSPIF->OQSPIF_GP_REG_b.OSPIC_PADS_DRV = 2; + + /* The following is required for BA. */ + CRG_TOP->CLK_AMBA_REG_b.GEN_DMA_ENABLE = 1; + #endif +} + +__STATIC_FORCEINLINE void bsp_power_domains_early_init (void) +{ +/* TIN-TODO: Identify if similar approach to other RAfW devices should be used, + * where all domains are enabled at startup. + */ + #if !BSP_MCU_GROUP_RA6W1 + bsp_pd_init(); + + /* Enable all power domains during startup. */ + for (uint8_t pd = 0; pd < BSP_PD_ID_COUNT; pd++) + { + bsp_pd_enable(pd); + } + #endif +} + +__STATIC_FORCEINLINE void bsp_mem_retain_early_init (void) +{ + // TIN-TODO: Identify whether RETAIN_MEM_CTRL_REG should be written here to enable retainment of cache. + #if !BSP_MCU_GROUP_RA6W1 + CRG_TOP->RAM_RETAIN_REG = UINT32_MAX; + #endif +} + + #endif + +__STATIC_FORCEINLINE void bsp_etm_trace_setup (void) +{ + /* TIN-TODO: Tin appears to have ETM support but the datasheet does not define any dedicated pins + * for the trace signals. + */ + #if !BSP_MCU_GROUP_RA6W1 + if (!ETM_TRACE_ENABLE) + { + /* No ETM trace required. Nothing to do. */ + return; + } + + uint32_t p0_etm_pins = 0; + + p0_etm_pins |= (1 << BSP_IO_PORT_00_PIN_19) | (1 << BSP_IO_PORT_00_PIN_20); /* TRACE_CLK & TRACE_DATA[0] */ + + /* Get trace port size from Current Parallel Port Size Register (CSPSR) */ + uint32_t trace_port_width = TPIU->CSPSR; + if (trace_port_width > 1) + { + p0_etm_pins |= (1 << BSP_IO_PORT_00_PIN_21); /* TRACE_DATA[1] */ + } + + if (trace_port_width == 8) + { + p0_etm_pins |= (1 << BSP_IO_PORT_00_PIN_22); /* TRACE_DATA[2] */ + p0_etm_pins |= (1 << BSP_IO_PORT_00_PIN_23); /* TRACE_DATA[3] */ + } + CRG_TOP->P0_SET_PAD_LATCH_REG = p0_etm_pins; + #endif +} + +static void SystemRuntimeInit (const uint32_t external) +{ + /* Initialize C runtime environment. */ + for (uint32_t i = 0; i < g_init_info.zero_count; i++) + { + if (external == g_init_info.p_zero_list[i].type.external) + { + uint32_t size = + ((uint32_t) g_init_info.p_zero_list[i].p_limit - (uint32_t) g_init_info.p_zero_list[i].p_base); + + #if defined(__ICCARM__) + size /= sizeof(uint32_t); + for (uint32_t it = 0; it < size; it++) + { + g_init_info.p_zero_list[i].p_base[it] = 0; + } + #else + fast_memset(g_init_info.p_zero_list[i].p_base, 0, size); + #endif + } + } + + for (uint32_t i = 0; i < g_init_info.copy_count; i++) + { + if (external == g_init_info.p_copy_list[i].type.external) + { + uint32_t size = + ((uint32_t) g_init_info.p_copy_list[i].p_limit - (uint32_t) g_init_info.p_copy_list[i].p_base); + + #if defined(__ICCARM__) + size /= sizeof(uint32_t); + for (uint32_t it = 0; it < size; it++) + { + g_init_info.p_copy_list[i].p_base[it] = g_init_info.p_copy_list[i].p_load[it]; + } + #else + fast_memcpy(g_init_info.p_copy_list[i].p_base, g_init_info.p_copy_list[i].p_load, size); + #endif + } + } +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_api_override.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_api_override.h new file mode 100644 index 000000000000..4ff8cde007b9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_api_override.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_API_OVERRIDE_H +#define BSP_API_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "./bsp_exceptions.h" + +/* BSP Common Includes. */ +#include "./bsp_common.h" + +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_tcs.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_tcs.h" +#elif BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_tcs.h" +#endif + + +/* BSP MCU Specific Includes. */ +#include "./bsp_irq.h" +#include "./bsp_io.h" +#include "./bsp_group_irq.h" +#include "./bsp_clocks.h" +#include "./bsp_module_stop.h" +#include "./bsp_security.h" + +/* Factory MCU information. */ +#include "../../../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ +#include "./bsp_delay.h" +#include "./bsp_mcu_api.h" + +#if __has_include("./internal/bsp_internal.h") + #include "./internal/bsp_internal.h" +#endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.c new file mode 100644 index 000000000000..833d5ba03d45 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.c @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_assert.h" +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#ifdef UNIT_TESTING + +void disable_irqs_mock(void); + + #define DISABLE_IRQS disable_irqs_mock() + +BSP_WEAK_REFERENCE void disable_irqs_mock (void) +{ + /* Do nothing. */ +} + +BSP_WEAK_REFERENCE void indicate_infinite_wait_hook(void); + + #define WAIT_FOREVER indicate_infinite_wait_hook() + +BSP_WEAK_REFERENCE void indicate_infinite_wait_hook (void) +{ + /* Do nothing. */ +} + +#else + #define DISABLE_IRQS __disable_irq() + #define WAIT_FOREVER do { /* Wait. */} while (1) + + #define MTB_MASTER_REG *((volatile uint32_t *) 0xE0043004) +#endif + +#define MTB_MASTER_EN_Pos 31 /* NOLINT(modernize-macro-to-enum) */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Pointer to the current handler of BSP_CHECK_DEBUG() and BSP_CHECK_FATAL(). + * It should end up halting execution, which might then be escalated to a system reset by the system watchdog. + * + * @note It is placed in the ".noinit" section, so that its value is controlled solely by + * bsp_prv_halt_implementation_early_set() and bsp_prv_halt_implementation_normal_set(). + **********************************************************************************************************************/ +bsp_on_error_cb_t g_halt_impl BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +TESTABLE_STATIC volatile uint32_t bsp_prv_scratch_registers[4]; + +__STATIC_FORCEINLINE void store_scratch_regs (const uint32_t * regs) +{ + bsp_prv_scratch_registers[0] = *regs++; + bsp_prv_scratch_registers[1] = *regs++; + bsp_prv_scratch_registers[2] = *regs++; + bsp_prv_scratch_registers[3] = *regs; +} + +__STATIC_FORCEINLINE void disable_tracing (void) +{ + MTB_MASTER_REG &= ~(1 << MTB_MASTER_EN_Pos); +} + +TESTABLE_STATIC void bsp_prv_early_halt (uintptr_t args) +{ + DISABLE_IRQS; + + store_scratch_regs((uint32_t *) args); + + disable_tracing(); + + R_BSP_PeripheralFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); + + // TODO add GPIO debugging (EXCEPTION_DEBUG == 1) + + WAIT_FOREVER; +} + +BSP_PLACE_CODE_IN_RAM +TESTABLE_STATIC void bsp_prv_normal_halt (uintptr_t args) +{ + DISABLE_IRQS; + + store_scratch_regs((uint32_t *) args); + + disable_tracing(); + + R_BSP_PeripheralFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); + + // TODO add GPIO debugging (EXCEPTION_DEBUG == 1) + + WAIT_FOREVER; +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/** + * @brief Set up the halt capability to use an implementation that is valid "early", i.e. before the C runtime is ready. + * + * Before the C runtime is ready, the halt implementation must be located in the default code storage, close to the + * Reset_Handler(), so that it can be safely called. + */ +void bsp_prv_halt_implementation_early_set (void) +{ + g_halt_impl = bsp_prv_early_halt; +} + +/** + * @brief Set up the halt capability to use an implementation that is optimized for the normal case, i.e. after the C + * runtime is ready. + * + * In the normal case, it's better for the halt implementation to be located in RAM, so that it's always usable. + */ +void bsp_prv_halt_implementation_normal_set (void) +{ + g_halt_impl = bsp_prv_normal_halt; +} + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.h new file mode 100644 index 000000000000..3bb161032288 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_assert.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ASSERT_H +#define BSP_ASSERT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_prv_halt_implementation_early_set(void); +void bsp_prv_halt_implementation_normal_set(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.c new file mode 100644 index 000000000000..6fda832f5e51 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.c @@ -0,0 +1,821 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" +#include "bsp_common.h" + +#if BSP_TZ_NONSECURE_BUILD + #include "bsp_guard.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#if BSP_FEATURE_CGC_HAS_RCX_CONTROL + #if defined(CRG_AON_AON_OSC_EN_REG_RCX_ENABLE_Msk) + #define RCX() CRG_AON->AON_OSC_EN_REG_b + #else + #define RCX() CRG_AON->CLK_RCX_REG_b + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_SOSC + #if defined(CRG_AON_AON_OSC_EN_REG_XTAL32K_ENABLE_Msk) + #define XTAL32K() CRG_AON->AON_OSC_EN_REG_b + #else + #define XTAL32K() CRG_AON->CLK_XTAL32K_REG_b + #endif +#endif + +/* The number of clocks is used to size the g_sys_clock_freq array. */ +#define BSP_PRV_NUM_SOURCE_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_DIGITAL + 1U) + +#define BSP_PRV_STABILIZE_PLL (1) +#define BSP_PRV_STABILIZE_XTAL32M (1) + +#define NSEC_TO_CLK_CYCLES(nsec, clk_freq_hz) ((((nsec) * ((clk_freq_hz) / 10000)) + 99999) / 100000) + +#if BSP_FEATURE_CGC_HAS_POWER_LVL_REG + #define BSP_PRV_1V2_FOR_PLL_ENABLE() do {CRG_TOP->POWER_LVL_REG_b.V12_LEVEL = 2;} while (0) +#else + #define BSP_PRV_1V2_FOR_PLL_ENABLE() do {CRG_TOP->POWER_CTRL_REG_b.VDD_LEVEL = 3;} while (0) +#endif + +#if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS + #define BSP_PRV_RUNNING_AT_RCHS_MASK CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RCHS_Msk +#else + #define BSP_PRV_RUNNING_AT_RCHS_MASK CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk +#endif + +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 || BSP_MCU_GROUP_RA6B2 + #define BSP_PRV_RUNNING_AT_XTALM CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL32M +#elif BSP_MCU_GROUP_RA6W1 || BSP_MCU_GROUP_RA6W3 + #define BSP_PRV_RUNNING_AT_XTALM CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL40M +#endif + +#ifdef CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL_Msk + #define BSP_PRV_RUNNING_AT_PLL_MASK CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL_Msk +#else + #define BSP_PRV_RUNNING_AT_PLL_MASK CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk +#endif + +#if BSP_MCU_GROUP_RA6W1 + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET (1) +#endif + +/*********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + +/** Low Power Clock Frequency */ +BSP_SECTION_EARLY_INIT uint32_t g_bsp_lp_clock; +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C + * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime + * environment is initialized. */ +uint32_t g_clock_freq[BSP_PRV_NUM_SOURCE_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ +#if BSP_FEATURE_CGC_HAS_RCHS +void bsp_clock_rchs_enable (bool enable) +{ + CRG_TOP->CLK_RCHS_REG_b.RCHS_ENABLE = enable; +} + +bool bsp_clock_rchs_is_enabled (void) +{ + return CRG_TOP->CLK_RCHS_REG_b.RCHS_ENABLE; +} + +#endif + +#if BSP_FEATURE_CGC_HAS_RCLP +void bsp_clock_rclp_enable (bool enable) +{ + CRG_TOP->CLK_RCLP_REG_b.RCLP_DISABLE = !enable; +} + +bool bsp_clock_rclp_is_enabled (void) +{ + return !CRG_TOP->CLK_RCLP_REG_b.RCLP_DISABLE; +} + +#endif + +#if BSP_FEATURE_CGC_HAS_RCX_CONTROL +void bsp_clock_rcx_enable (bool enable) +{ + RCX().RCX_ENABLE = enable; +} + +#endif + +#if BSP_FEATURE_CGC_HAS_RCX +bool bsp_clock_rcx_is_enabled (void) +{ + #if BSP_FEATURE_CGC_HAS_RCX_CONTROL + + return RCX().RCX_ENABLE; + #else + + return true; + #endif +} + +#endif + +#if BSP_FEATURE_CGC_HAS_SOSC + +void bsp_clock_xtalk_enable (bool enable) +{ + XTAL32K().XTAL32K_ENABLE = enable; +} + +bool bsp_clock_xtalk_is_enabled (void) +{ + return XTAL32K().XTAL32K_ENABLE; +} + +#endif + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + +static void bsp_prv_clock_xtalm_start (void) +{ + if (0 == BSP_PRV_RUNNING_AT_XTALM) + { + #if !BSP_MCU_GROUP_RA6W3 /* TODO: Workaround for OSPI XIP */ + BSP_CHECK_DEBUG(FSP_SUCCESS == bsp_clock_xtalm_preconditions_check()); + #endif + + bsp_clock_xtalm_enable(true); + + #if BSP_CLOCK_CFG_XTAL32M_STABILIZATION_USEC + R_BSP_SoftwareDelay(BSP_CLOCK_CFG_XTAL32M_STABILIZATION_USEC, BSP_DELAY_UNITS_MICROSECONDS); + #else + while (false == bsp_clock_xtalm_is_settled()) + { + /* Wait. */ + } + #endif + } +} + +bool bsp_clock_xtalm_is_enabled (void) +{ + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 || BSP_MCU_GROUP_RA6B2 + + return XTAL32M->XTAL32M_ENABLE_REG & + (XTAL32M_XTAL32M_ENABLE_REG_LDOXTAL_EN_Msk | + XTAL32M_XTAL32M_ENABLE_REG_EN_XTAL_BIAS_Msk | + XTAL32M_XTAL32M_ENABLE_REG_EN_XTAL_OSC_Msk); + #elif BSP_MCU_GROUP_RA6W3 + + return XTAL32M->XTAL40M_ENABLE_REG & + (XTAL32M_XTAL40M_ENABLE_REG_LDOXTAL_EN_Msk | + XTAL32M_XTAL40M_ENABLE_REG_EN_XTAL_BIAS_Msk | + XTAL32M_XTAL40M_ENABLE_REG_EN_XTAL_OSC_Msk); + #elif BSP_MCU_GROUP_RA6W1 + + return CRG_COM->XTAL40M_CTRL_REG_b.XTAL40M_RDY; + #endif +} + +#endif /* BSP_CLOCK_CFG_MAIN_OSC_POPULATED */ + +#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET +static void bsp_prv_clock_set_hard_reset(void); + +#endif + +#if BSP_TZ_SECURE_BUILD + +/* Callback used to notify the nonsecure project that the clock settings have changed. */ +static bsp_clock_update_callback_t g_bsp_clock_update_callback = NULL; + +/* Pointer to nonsecure memory to store the callback args. */ +static bsp_clock_update_callback_args_t * gp_callback_memory = NULL; + +/* Reentrant method of calling the clock_update_callback. */ +static void r_bsp_clock_update_callback_call (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_args) +{ + /* Allocate memory for saving global callback args on the secure stack. */ + bsp_clock_update_callback_args_t callback_args; + + /* Save current info stored in callback memory. */ + callback_args = *gp_callback_memory; + + /* Write the callback args to the nonsecure callback memory. */ + *gp_callback_memory = *p_callback_args; + + /* Call the callback to notifiy ns project about clock changes. */ + p_callback(gp_callback_memory); + + /* Restore the info in callback memory. */ + *gp_callback_memory = callback_args; +} + +/* Initialize the callback, callback memory and invoke the callback to ensure the nonsecure project has the correct clock settings. */ +void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + /* Store pointer to nonsecure callback memory. */ + gp_callback_memory = p_callback_memory; + + /* Store callback. */ + g_bsp_clock_update_callback = p_callback; + + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); +} + +#elif BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU + +bsp_clock_update_callback_args_t g_callback_memory; + #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +static void BSP_CMSE_NONSECURE_CALL g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #elif defined(__GNUC__) + +static BSP_CMSE_NONSECURE_CALL void g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #endif + +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_callback_args->pll_freq; + + /* Update the SystemCoreClock value based on the new g_sys_clock_freq settings. */ + SystemCoreClockUpdate(); +} + + #endif +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t clock_index = CRG_TOP->CLK_CTRL_REG_b.SYS_CLK_SEL; + + SystemCoreClock = g_clock_freq[clock_index] >> bsp_clock_ahb_div_get(); +} + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + +/*******************************************************************************************************************//** + * Update g_bsp_lp_clock variable based on current clock settings. + **********************************************************************************************************************/ +void R_BSP_LPClockUpdate (void) +{ + uint32_t clock_index = CRG_TOP->CLK_CTRL_REG_b.LP_CLK_SEL + BSP_CLOCKS_SOURCE_CLOCK_RCLP; + + g_bsp_lp_clock = g_clock_freq[clock_index]; +} + +#endif + +#if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS + +/*******************************************************************************************************************//** + * @brief Set the speed mode of the RCHS clock + * + * @param[in] speed the speed mode to use + **********************************************************************************************************************/ +void bsp_clock_rchs_speed_set (bsp_clock_rchs_speed_t speed) +{ + uint32_t value = 0; + uint32_t freq = BSP_RCHS_HZ; + FSP_CRITICAL_SECTION_DEFINE; + + if (BSP_CLOCK_RCHS_SPEED_64M == speed) + { + value = CRG_TOP_CLK_RCHS_REG_RCHS_SPEED_Msk; + freq = 2 * BSP_RCHS_HZ; + } + + FSP_CRITICAL_SECTION_ENTER; + FSP_REG_SET_MASKED(CRG_TOP, CLK_RCHS_REG, CRG_TOP_CLK_RCHS_REG_RCHS_SPEED_Msk, value); + FSP_CRITICAL_SECTION_EXIT; + + R_BSP_SourceClockHzSet(FSP_PRIV_CLOCK_RCHS, freq); +} + +#endif /* BSP_FEATURE_CGC_HAS_RCHS_SPEEDS */ + +#if BSP_FEATURE_CGC_HAS_RCLP_SPEEDS + +/*******************************************************************************************************************//** + * @brief Set the speed mode of the RCLP clock + * + * @param[in] speed the speed mode to use + **********************************************************************************************************************/ +void bsp_clock_rclp_speed_set (bsp_clock_rclp_speed_t speed) +{ + static const uint32_t mask = CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk | CRG_AON_RCLP_TRIM_REG_RCLP_TRIM_Msk; + uint32_t value; + uint32_t freq = BSP_RCLP_HZ; + FSP_CRITICAL_SECTION_DEFINE; + + if (BSP_CLOCK_RCLP_SPEED_512K == speed) + { + value = CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Msk; + } + else if (BSP_CLOCK_RCLP_SPEED_32K == speed) + { + value = CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk; + freq = BSP_RCLP_LOW_SPEED_FREQ_HZ; + } + else + { + value = 0; + } + + FSP_CRITICAL_SECTION_ENTER; + FSP_REG_SET_MASKED(CRG_TOP, CLK_RCLP_REG, mask, value); + FSP_CRITICAL_SECTION_EXIT; + + R_BSP_SourceClockHzSet(FSP_PRIV_CLOCK_RCLP, freq); +} + +#endif /* BSP_FEATURE_CGC_HAS_RCLP_SPEEDS */ + +/*******************************************************************************************************************//** + * Set System clock. + * + * \param[in] clock The new system clock. + * + * @note If any one of the lp clocks is requested, this function changes the system clock to the currently selected lp + * clock (whichever that is). + **********************************************************************************************************************/ +void bsp_clock_sysclk_set (fsp_priv_source_clock_t clock) +{ +#if BSP_FEATURE_CGC_HAS_XTALM_SWITCH + if ((FSP_PRIV_CLOCK_XTALM == clock) && CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_RCHS) + { + CRG_TOP->CLK_SWITCH2XTAL_REG_b.SWITCH2XTAL = 1; + } + else +#endif + { +#if BSP_FPGA + #if BSP_PRV_PLL_SUPPORTED + if (FSP_PRIV_CLOCK_PLL == clock) + { + bsp_clock_pll_enable(false); + bsp_clock_pll_enable(true); + } + #endif +#endif + uint32_t clock_index = clock > BSP_CLOCKS_SOURCE_CLOCK_PLL ? BSP_CLOCKS_SOURCE_CLOCK_RCLP : clock; + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + CRG_TOP->CLK_CTRL_REG_b.SYS_CLK_SEL = clock_index & + (CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk >> + CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos); + FSP_CRITICAL_SECTION_EXIT; + } + + /* Update the CMSIS core clock variable so that it reflects the new HCLK frequency. */ + SystemCoreClockUpdate(); + + /* Wait until the switch is done! */ + switch (clock) + { +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + case FSP_PRIV_CLOCK_XTALM: + { + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL32M) + #elif BSP_MCU_GROUP_RA6W1 || BSP_MCU_GROUP_RA6W3 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL40M) + #endif + { + } + + return; + } + + #if BSP_FEATURE_CGC_HAS_XTALM_DBLR + case FSP_PRIV_CLOCK_XTALM_DBLR: + { + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL64M) + #elif BSP_MCU_GROUP_RA6W3 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_XTAL80M) + #endif + { + } + + return; + } + #endif +#endif +#if BSP_FEATURE_CGC_HAS_RCHS + case FSP_PRIV_CLOCK_RCHS: + { + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_RCHS) + { + } + + return; + } +#endif +#if BSP_PRV_PLL_SUPPORTED + case FSP_PRIV_CLOCK_PLL: + { + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_PLL) + #elif BSP_MCU_GROUP_RA6W3 + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_PLL320M) + #endif + { + } + + return; + } +#endif + + case FSP_PRIV_CLOCK_RCLP: +#if BSP_FEATURE_CGC_ANY_LP_CLK_CAN_BE_SYS_CLK + #if BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + case FSP_PRIV_CLOCK_XTALK: + #endif + case FSP_PRIV_CLOCK_RCX: + case FSP_PRIV_CLOCK_DIGITAL: + { + /* Low-power clock */ + while (!CRG_TOP->CLK_CTRL_REG_b.RUNNING_AT_LP_CLK) + { + } + } +#endif /* BSP_FEATURE_CGC_ANY_LP_CLK_CAN_BE_SYS_CLK */ + + default: + { + BSP_CHECK_DEBUG(0); + break; + } + } +} + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. + * + * @param[in] clock Desired system clock + * @param[in] clk_amba_reg_div Value to set in dividers of CLK_AMBA_REG register + **********************************************************************************************************************/ +void bsp_clock_set (fsp_priv_source_clock_t clock, uint32_t clk_amba_reg_div) +{ + /* Set dividers. */ + uint32_t clk_amba_reg_val = (CRG_TOP->CLK_AMBA_REG & ~BSP_PRV_CLK_AMBA_REG_DIV) | + (clk_amba_reg_div & BSP_PRV_CLK_AMBA_REG_DIV); + + CRG_TOP->CLK_AMBA_REG = clk_amba_reg_val; + + /* Set lp clock if needed. */ +#if BSP_FEATURE_CGC_ANY_LP_CLK_CAN_BE_SYS_CLK + if ((FSP_PRIV_CLOCK_RCLP == clock) || (FSP_PRIV_CLOCK_RCX == clock) || + #if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + (FSP_PRIV_CLOCK_XTALK == clock) || + #endif + #endif + (FSP_PRIV_CLOCK_DIGITAL == clock)) + { + bsp_clock_lpclk_set(clock); + } +#endif + + /* Set system clock. */ + bsp_clock_sysclk_set(clock); +} + +#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + +static void bsp_prv_clock_set_hard_reset (void) +{ + /* Set the system source clock */ + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED && (BSP_CLOCKS_SOURCE_CLOCK_XTALM == BSP_CFG_CLOCK_SOURCE) + + /* Nothing to do. Xtal32m has already been set as system clock in bsp_clock_init(). */ + #elif BSP_CLOCK_CFG_MAIN_OSC_POPULATED && BSP_FEATURE_CGC_HAS_XTALM_DBLR && \ + (BSP_CLOCKS_SOURCE_CLOCK_XTALM_DBLR == BSP_CFG_CLOCK_SOURCE) + + bsp_clock_xtalm_64m_output_enable(true); + #elif (BSP_CLOCKS_SOURCE_CLOCK_RCHS == BSP_CFG_CLOCK_SOURCE) + #if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS && (BSP_RCHS_64M_SPEED_MODE == BSP_CFG_RCHS_FREQUENCY) + BSP_CHECK_DEBUG(FSP_SUCCESS == bsp_clock_rchs_high_speed_preconditions_check()); + #endif + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + bsp_clock_rchs_enable(true); + #endif + #elif BSP_PRV_PLL_SUPPORTED && (BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE) + bsp_clock_pll_enable(true); + + #if BSP_PRV_STABILIZE_PLL + while (!bsp_clock_pll_is_locked()) + { + } + #endif + + /* + * If ultra-fast wake-up mode is used, make sure that the startup state + * machine is finished and all power regulation is in order. + */ + while (0 == CRG_TOP->SYS_STAT_REG_b.POWER_IS_UP) + { + /* Wait. */ + } + #endif /* BSP_CFG_CLOCK_SOURCE */ + + #if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS + #if (BSP_CLOCKS_SOURCE_CLOCK_RCHS == BSP_CFG_CLOCK_SOURCE) + bsp_clock_rchs_speed_set((bsp_clock_rchs_speed_t) BSP_CFG_RCHS_FREQUENCY); + + /* Switching to/from 64 MHz requires >100us for the RCHS to settle */ + R_BSP_SoftwareDelay(150, BSP_DELAY_UNITS_MICROSECONDS); + #endif /* BSP_CFG_CLOCK_SOURCE */ + #endif /* BSP_FEATURE_CGC_HAS_RCHS_SPEEDS */ + + bsp_clock_sysclk_set((fsp_priv_source_clock_t) BSP_CFG_CLOCK_SOURCE); + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); + + /* Clocks are now at requested frequencies. */ +} + +#endif + +/*******************************************************************************************************************//** + * Initializes variable to store system clock frequencies. + **********************************************************************************************************************/ +#if BSP_TZ_NONSECURE_BUILD +void bsp_clock_freq_var_init (void) +#else +static void bsp_clock_freq_var_init (void) +#endif +{ + memset(g_clock_freq, 0, sizeof(g_clock_freq)); + + /* Initialize System Clock frequencies. */ +#if BSP_FEATURE_CGC_HAS_RCHS + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_RCHS] = BSP_RCHS_HZ; +#endif + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_XTALM] = BSP_CFG_XTALM_HZ; + #if BSP_FEATURE_CGC_HAS_XTALM_DBLR + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_XTALM_DBLR] = 2 * BSP_CFG_XTALM_HZ; + #endif +#endif + +#if BSP_PRV_PLL_SUPPORTED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_PLL_FREQ_HZ; +#endif + +#if BSP_FEATURE_CGC_HAS_RCLP + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_RCLP] = BSP_RCLP_HZ; +#endif + +#if BSP_FEATURE_CGC_HAS_RCX + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_RCX] = BSP_RCX_HZ; +#endif + +#if BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_XTALK] = BSP_CFG_XTALK_HZ; +#endif + +#if BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU + + /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */ + R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory); +#endif + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + + /* The g_bsp_lp_clock variable needs to be updated. */ + R_BSP_LPClockUpdate(); +#endif +} + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + bsp_clock_freq_var_init(); + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + bsp_clock_xtalm_configure(); + bsp_prv_clock_xtalm_start(); +#else + bsp_clock_rchs_enable(true); +#endif + +#if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + bsp_clock_xtalk_configure(); + #else + bsp_clock_xtalk_enable(false); + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_RCLP_SPEEDS + bsp_clock_rclp_speed_set((bsp_clock_rclp_speed_t) BSP_CFG_RCLP_FREQUENCY); +#endif + +#if BSP_CLOCKS_SOURCE_CLOCK_RCLP == BSP_CFG_LP_CLOCK_SOURCE + bsp_clock_rclp_enable(true); +#elif BSP_CLOCKS_SOURCE_CLOCK_RCX == BSP_CFG_LP_CLOCK_SOURCE + #if BSP_FEATURE_CGC_HAS_RCX_CONTROL + bsp_clock_rcx_enable(true); + #endif + + #if !defined(BSP_MCU_GROUP_RA6W1) && !defined(BSP_MCU_GROUP_RA6W3) + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + bsp_clock_msr_sel_t ref_clock = BSP_CLOCK_MSR_SEL_XTAL32M; + #else + bsp_clock_msr_sel_t ref_clock = BSP_CLOCK_MSR_SEL_DIVN; + #endif + + /* Perform initial measurement of RCX and update the value in the frequency table. */ + R_BSP_SourceClockHzSet(FSP_PRIV_CLOCK_RCX, + bsp_clock_measurement(BSP_CLOCK_MSR_SEL_RCX, ref_clock, BSP_CFG_CLOCK_CALIBRATION_CYCLES)); + #endif +#elif BSP_CLOCKS_SOURCE_CLOCK_XTALK == BSP_CFG_LP_CLOCK_SOURCE + #if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + bsp_clock_xtalk_enable(true); + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + + R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS); + #endif + #endif + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + bsp_clock_lpclk_set((fsp_priv_source_clock_t) BSP_CFG_LP_CLOCK_SOURCE); + + R_BSP_LPClockUpdate(); +#endif + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + + /* Switch to XTAL32M first in any case. */ + bsp_clock_sysclk_set(FSP_PRIV_CLOCK_XTALM); +#endif + + /* Set source clock and dividers. */ +#if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + #if BSP_TZ_SECURE_BUILD + + /* In case of soft reset, make sure callback pointer is NULL initially. */ + g_bsp_clock_update_callback = NULL; + #endif +#else + bsp_prv_clock_set_hard_reset(); +#endif +} + +/*******************************************************************************************************************//** + * Gets the frequency of a source clock. + * @param[in] clock Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock) +{ + BSP_CHECK_FATAL(clock <= FSP_PRIV_CLOCK_DIGITAL); + + uint32_t source_clock = 0; + + source_clock = g_clock_freq[clock]; + + return source_clock; +} + +/*******************************************************************************************************************//** + * Sets the frequency of a source clock. + * @param[in] clock Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @param[in] freq Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +void R_BSP_SourceClockHzSet (fsp_priv_source_clock_t clock, uint32_t freq) +{ + BSP_CHECK_FATAL(clock <= FSP_PRIV_CLOCK_DIGITAL); + + g_clock_freq[clock] = freq; + + SystemCoreClockUpdate(); +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + R_BSP_LPClockUpdate(); +#endif +} + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + +/*******************************************************************************************************************//** + * Set Low Power clock. + * + * \param[in] clock The new low power clock. + **********************************************************************************************************************/ +void bsp_clock_lpclk_set (fsp_priv_source_clock_t clock) +{ + uint32_t clock_index = clock - FSP_PRIV_CLOCK_RCLP; + uint32_t clk_ctrl_reg; + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + clk_ctrl_reg = CRG_TOP->CLK_CTRL_REG; + FSP_REG_VAR_FIELD_SET(CRG_TOP, CLK_CTRL_REG, LP_CLK_SEL, clk_ctrl_reg, clock_index); + CRG_TOP->CLK_CTRL_REG = clk_ctrl_reg; + + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Gets the frequency of the low power clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +uint32_t R_BSP_LPClockHzGet (void) +{ + return g_bsp_lp_clock; +} + +#endif + +#if BSP_FEATURE_RTC_IS_AVAILABLE + +/*******************************************************************************************************************//** + * RTC Initialization + * + * Configures the dividers for the 100kHz clock generation & the RTC_KEEP_RTC_REG. + **********************************************************************************************************************/ +void R_BSP_Init_RTC (void) +{ + uint16_t div_int; + uint16_t div_frac; + uint32_t clk_rtc_div; + uint32_t lp_clk_freq = R_BSP_LPClockHzGet(); + + div_int = (uint16_t) (lp_clk_freq / 100); // NOLINT + div_frac = (uint16_t) (10 * (lp_clk_freq - (div_int * 100))); // NOLINT + + clk_rtc_div = div_frac; + clk_rtc_div += div_int << CRG_AON_CLK_RTCDIV_REG_RTC_DIV_INT_Pos; + + clk_rtc_div += (CRG_TOP->CLK_CTRL_REG_b.LP_CLK_SEL) << CRG_AON_CLK_RTCDIV_REG_RTC_CLK_SEL_Pos; + + CRG_AON->CLK_RTCDIV_REG = clk_rtc_div; + + RTC->RTC_KEEP_RTC_REG = 1U; +} + +#endif + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.h new file mode 100644 index 000000000000..3bb7927e47ef --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_clocks.h @@ -0,0 +1,344 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +#if BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_clocks.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +#define BSP_CLOCKS_SOURCE_CLOCK_RCHS (0) +#define BSP_CLOCKS_SOURCE_CLOCK_XTALM (1) +#define BSP_CLOCKS_SOURCE_CLOCK_XTALM_DBLR (2) +#define BSP_CLOCKS_SOURCE_CLOCK_PLL (3) +#define BSP_CLOCKS_SOURCE_CLOCK_RCLP (4) +#define BSP_CLOCKS_SOURCE_CLOCK_RCX (5) +#define BSP_CLOCKS_SOURCE_CLOCK_XTALK (6) +#define BSP_CLOCKS_SOURCE_CLOCK_DIGITAL (7) // External square wave clock. + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_PRV_PLL_SUPPORTED (1) +#else + #define BSP_PRV_PLL_SUPPORTED (0) +#endif + +#if BSP_FEATURE_CGC_HAS_HCLK_DIV + #define BSP_PRV_HCLK_DIV_MASK (CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk) +#else + #define BSP_PRV_HCLK_DIV_MASK (0) +#endif + +#if BSP_FEATURE_CGC_HAS_PCLK_DIV + #define BSP_PRV_PCLK_DIV_MASK (CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk) +#else + #define BSP_PRV_PCLK_DIV_MASK (0) +#endif + +#if BSP_FEATURE_CGC_HAS_QCLK_DIV + #define BSP_PRV_QCLK_DIV_MASK (CRG_TOP_CLK_AMBA_REG_QSPI_SDR_DIV2_Msk) +#else + #define BSP_PRV_QCLK_DIV_MASK (0) +#endif + +#define BSP_PRV_CLK_AMBA_REG_DIV (BSP_PRV_HCLK_DIV_MASK | BSP_PRV_PCLK_DIV_MASK | BSP_PRV_QCLK_DIV_MASK) + +#if BSP_PRV_PLL_SUPPORTED + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTALM_HZ) +#endif +#if BSP_PRV_PLL2_SUPPORTED + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTALM_HZ) +#endif + +/* Frequencies of clocks with fixed frequencies. */ +#define BSP_DIVN_FREQ_HZ (32000000U) // DIVN frequency is 32 MHz +#if BSP_FEATURE_CGC_HAS_RCLP_SPEEDS + #define BSP_RCLP_DEFAULT_SPEED_MODE (0) + #define BSP_RCLP_32K_SPEED_MODE (1) + #define BSP_RCLP_512K_SPEED_MODE (2) + + #define BSP_RCLP_HIGH_SPEED_FREQ_HZ (512000U) + #define BSP_RCLP_LOW_SPEED_FREQ_HZ (32000U) +#endif + +#if BSP_PRV_PLL_SUPPORTED + #if BSP_FPGA + #define BSP_PLL_FREQ_HZ (32000000) + #else + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + #define BSP_PLL_FREQ_HZ (128000000) + #elif BSP_MCU_GROUP_RA6W1 + #define BSP_PLL_FREQ_HZ (480000000) + #endif + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS + #define BSP_RCHS_32M_SPEED_MODE (0) + #define BSP_RCHS_64M_SPEED_MODE (1) +#endif + +#if BSP_CLOCKS_SOURCE_CLOCK_RCHS == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_RCHS_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_XTALM == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTALM_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_XTALM_DBLR == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (2 * BSP_CFG_XTALM_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL_FREQUENCY_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_RCLP == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_RCLP_HZ) +#endif + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK + #if BSP_CLOCKS_SOURCE_CLOCK_RCLP == BSP_CFG_LP_CLOCK_SOURCE + #define BSP_STARTUP_LP_CLOCK_HZ (BSP_RCLP_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_RCX == BSP_CFG_LP_CLOCK_SOURCE + #define BSP_STARTUP_LP_CLOCK_HZ (BSP_RCX_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_XTALK == BSP_CFG_LP_CLOCK_SOURCE + #define BSP_STARTUP_LP_CLOCK_HZ (BSP_CFG_XTALK_HZ) + #endif +#endif + +#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0U) // System clock divided by 1. +#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1U) // System clock divided by 2. +#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2U) // System clock divided by 4. +#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3U) // System clock divided by 8. +#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4U) // HCLK divided by 16. + +/* SPI clock output divider options. */ +#define BSP_CLOCKS_SPI_CLK_DIV_8 (0U) // SPI clock divided by 8. +#define BSP_CLOCKS_SPI_CLK_DIV_4 (1U) // SPI clock divided by 4. +#define BSP_CLOCKS_SPI_CLK_DIV_2 (2U) // SPI clock divided by 2. +#define BSP_CLOCKS_SPI_CLK_DIV_14 (3U) // SPI clock divided by 14. + +/* QSPI clock output divider options. */ +#define BSP_CLOCKS_QSPI_CLK_DIV_1 (0U) // QSPI clock divided by 1. +#define BSP_CLOCKS_QSPI_CLK_DIV_2 (1U) // QSPI clock divided by 2. +#define BSP_CLOCKS_QSPI_CLK_DIV_4 (2U) // QSPI clock divided by 4. +#define BSP_CLOCKS_QSPI_CLK_DIV_8 (3U) // QSPI clock divided by 8. + +/* WDOG clock output divider options. */ +#define BSP_CLOCKS_WDOG_DIV_320 (1U) // WDOG clock is LP CLK divided by 320. + +/* Configuration option used to disable a clock, or to select DIV1/DIVN as source. */ +#define BSP_CLOCKS_SOURCE_CLOCK_DISABLED (0xFFU) +#define BSP_CLOCKS_SOURCE_CLOCK_DIV1 (0U) +#define BSP_CLOCKS_SOURCE_CLOCK_DIV2 (1U) +#define BSP_CLOCKS_SOURCE_CLOCK_DIVN (2U) +#define BSP_CLOCKS_SOURCE_CLOCK_DIVN_DIV2 (2U) // Only for GPADC. + +// NOLINTEND(modernize-macro-to-enum) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +typedef struct +{ + uint32_t pll_freq; +} bsp_clock_update_callback_args_t; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #endif + +#endif + +#if BSP_FEATURE_CGC_HAS_RCLP_SPEEDS + +/** + * @brief RCLP mode selection + */ +typedef enum e_bsp_clock_rclp_speed +{ + BSP_CLOCK_RCLP_SPEED_DEFAULT = BSP_RCLP_DEFAULT_SPEED_MODE, ///< Default RCLP speed mode (automatically switches to 32 + /// kHz during sleep and to 512 kHz during active) + BSP_CLOCK_RCLP_SPEED_32K = BSP_RCLP_32K_SPEED_MODE, ///< Low speed RCLP mode (32 kHz) + BSP_CLOCK_RCLP_SPEED_512K = BSP_RCLP_512K_SPEED_MODE, ///< High speed RCLP mode (512 kHz) +} bsp_clock_rclp_speed_t; +#endif /* BSP_FEATURE_CGC_HAS_RCLP_SPEEDS */ + +#if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS + +/** + * @brief RCHS mode selection + */ +typedef enum e_bsp_clock_rchs_speed +{ + BSP_CLOCK_RCHS_SPEED_32M = BSP_RCHS_32M_SPEED_MODE, ///< High speed RCHS speed (32 MHz) + BSP_CLOCK_RCHS_SPEED_64M = BSP_RCHS_64M_SPEED_MODE, ///< Low speed RCHS speed (64 MHz) +} bsp_clock_rchs_speed_t; +#endif /* BSP_FEATURE_CGC_HAS_RCHS_SPEEDS */ + +/** + * @brief The type of clock to be measured + */ +typedef enum e_bsp_clock_msr_sel +{ + BSP_CLOCK_MSR_SEL_RCLP = 0, + BSP_CLOCK_MSR_SEL_RCHS = 1, + BSP_CLOCK_MSR_SEL_RCX = 2, + BSP_CLOCK_MSR_SEL_XTAL32K = 3, + BSP_CLOCK_MSR_SEL_XTAL32M = 4, + BSP_CLOCK_MSR_SEL_XTAL64M = 5, + BSP_CLOCK_MSR_SEL_EXTERNAL = 6, + BSP_CLOCK_MSR_SEL_DIVN = 7, +} bsp_clock_msr_sel_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +#if BSP_FEATURE_CGC_HAS_LP_CLOCK +extern uint32_t g_bsp_lp_clock; /** System Clock Frequency (Low Power Clock) */ +extern uint32_t g_clock_freq[]; +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_clock_rchs_enable(bool enable); +bool bsp_clock_rchs_is_enabled(void); + +#if BSP_FEATURE_CGC_HAS_RCHS_SPEEDS +fsp_err_t bsp_clock_rchs_high_speed_preconditions_check(void); +void bsp_clock_rchs_speed_set(bsp_clock_rchs_speed_t speed); + +#endif + +void bsp_clock_rclp_enable(bool enable); +bool bsp_clock_rclp_is_enabled(void); + +#if BSP_FEATURE_CGC_HAS_RCLP_SPEEDS +void bsp_clock_rclp_speed_set(bsp_clock_rclp_speed_t speed); + +#endif + +#if BSP_FEATURE_CGC_HAS_RCX_CONTROL +void bsp_clock_rcx_enable(bool enable); + +#endif + +bool bsp_clock_rcx_is_enabled(void); + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED +fsp_err_t bsp_clock_xtalm_preconditions_check(void); +void bsp_clock_xtalm_configure(void); +void bsp_clock_xtalm_enable(bool enable); +bool bsp_clock_xtalm_is_enabled(void); +bool bsp_clock_xtalm_is_settled(void); + + #if BSP_FEATURE_CGC_HAS_XTALM_READY_COUNTER +int16_t bsp_clock_xtalm_ready_counter_update(void); + + #endif + #if BSP_FEATURE_CGC_HAS_XTALM_DBLR +void bsp_clock_xtalm_64m_output_enable(bool enable); +bool bsp_clock_xtalm_64m_output_is_enabled(void); + + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_SOSC +void bsp_clock_xtalk_enable(bool enable); + + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED +void bsp_clock_xtalk_configure(void); +bool bsp_clock_xtalk_is_enabled(void); + + #endif +#endif + +#if BSP_PRV_PLL_SUPPORTED +fsp_err_t bsp_clock_pll_preconditions_check(void); +void bsp_clock_check_core_voltage_before_switch_sysclk_to_pll(void); +void bsp_clock_pll_enable(bool enable); +bool bsp_clock_pll_is_enabled(void); +bool bsp_clock_pll_is_locked(void); + + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 +void bsp_clock_usbpll_enable(bool enable); +bool bsp_clock_usbpll_is_locked(void); + + #endif + +#endif + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK +void bsp_clock_lpclk_set(fsp_priv_source_clock_t clock); + +#endif + +void bsp_clock_sysclk_set(fsp_priv_source_clock_t clock); +void bsp_clock_set(fsp_priv_source_clock_t clock, uint32_t clk_amba_reg_div); +void bsp_clock_hclk_set(uint8_t sys_clock_sel, uint8_t hclk_div); + +#if !BSP_MCU_GROUP_RA6W1 && !BSP_MCU_GROUP_RA6W3 + +uint32_t bsp_clock_measurement(bsp_clock_msr_sel_t target, bsp_clock_msr_sel_t ref, uint32_t cycles); +void bsp_clock_measurement_configure(bsp_clock_msr_sel_t target, bsp_clock_msr_sel_t ref, uint32_t cycles); + +__STATIC_FORCEINLINE void bsp_clock_measurement_start (void) +{ + ANAMISC->CLK_REF_SEL_REG_b.REF_CAL_START = 1; +} + +__STATIC_FORCEINLINE uint32_t bsp_clock_measurement_read (void) +{ + return ANAMISC->CLK_REF_VAL_REG; +} + +#endif + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK +uint32_t R_BSP_LPClockHzGet(void); +void R_BSP_LPClockUpdate(void); + +#endif + +void bsp_clock_init(void); + +#if BSP_TZ_NONSECURE_BUILD +void bsp_clock_freq_var_init(void); + +#endif + +#if BSP_TZ_SECURE_BUILD +void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/* RTC Initialization */ +#if BSP_FEATURE_RTC_IS_AVAILABLE +void R_BSP_Init_RTC(void); + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_cmac.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_cmac.h new file mode 100644 index 000000000000..ec691073fc3a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_cmac.h @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CMAC_H +#define BSP_CMAC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define CMAC2SYS_IRQn ((IRQn_Type) 59) +#define TCM_SHARED_MEM (0x33200000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_cmac_callback_args_t +{ + void const * data; ///< Placeholder for user data. + uint32_t err_code; ///< CMAC error code returned. +} cmac_callback_args_t; + +typedef void (* p_callback)(cmac_callback_args_t * cb_data); + +typedef struct st_cmac_irq_ctx +{ + IRQn_Type irq; + uint8_t ipl; + p_callback callback; + void * cb_data; +} cmac_irq_ctx_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_cmac_start(void); +void bsp_cmac_stop(void); +bool bsp_cmac_is_active(void); +void bsp_cmac_cmac2sys_enable(cmac_irq_ctx_t * const ctx); +void bsp_cmac_cmac2sys_disable(cmac_irq_ctx_t * const ctx); +void cmac2sys_isr(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.c new file mode 100644 index 000000000000..3f42e2d9a873 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.c @@ -0,0 +1,311 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 +static bool bsp_valid_register_check(uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length); + +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .version_id_b = + { + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH + } +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Read a secure 8-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + // (uint32_t) &R_SYSTEM->SCKDIVCR2, + // (uint32_t) &R_SYSTEM->SCKSCR, + // (uint32_t) &R_SYSTEM->SPICKDIVCR, + // (uint32_t) &R_SYSTEM->SPICKCR, + // (uint32_t) &R_SYSTEM->SCICKDIVCR, + // (uint32_t) &R_SYSTEM->SCICKCR, + // (uint32_t) &R_SYSTEM->CANFDCKCR, + // (uint32_t) &R_SYSTEM->PLLCR, + // (uint32_t) &R_SYSTEM->PLL2CR, + // (uint32_t) &R_SYSTEM->MOCOCR, + // (uint32_t) &R_SYSTEM->OPCCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 16-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + // (uint32_t) &R_DTC->DTCSTS, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 32-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + // (uint32_t) &R_SYSTEM->SCKDIVCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) +{ + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#elif defined(__GNUC__) + +/* The default assert implementation for GCC brings in printing/formatting code. FSP overrides the default assert + * behavior to reduce code size. */ + + #if !BSP_CFG_USE_STANDARD_ASSERT + +/*******************************************************************************************************************//** + * Default implementation of assert for GCC. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * func, const char * expr) +{ + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + FSP_PARAMETER_NOT_USED(func); + FSP_PARAMETER_NOT_USED(expr); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + + #endif + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Check if a register address should be accessible by the non-secure application. + **********************************************************************************************************************/ +static bool bsp_valid_register_check (uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length) +{ + bool valid = false; + + /* Check if the given address is valid. */ + for (uint32_t i = 0; i < register_table_length; i++) + { + if (p_register_table[i] == register_address) + { + valid = true; + break; + } + } + + return valid; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.h new file mode 100644 index 000000000000..ae1fac5cace8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_common.h @@ -0,0 +1,1046 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/api/fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_linker_info.h" +#include "bsp_cfg.h" + +#ifdef BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_rtc.h" + #include "../ra6w1/bsp_tcs.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) +#define EMULATOR_BASE_CLOCK (170500) + +/* Version of this module's code and API. */ + +#if 1 == BSP_CFG_RTOS /* ThreadX */ + #include "tx_user.h" + #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) + #include "tx_api.h" + #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); + #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); + #else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE + #endif +#else + #define FSP_CONTEXT_SAVE do {} while (0) + #define FSP_CONTEXT_RESTORE do {} while (0) +#endif + +/** Macro that can be defined in order to enable logging in FSP modules. */ +#ifndef FSP_LOG_PRINT + #define FSP_LOG_PRINT(X) +#endif + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/** Push ARM Cortex-M scratch registers on stack. */ +#ifndef UNIT_TESTING + #if defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC) + #define BSP_PUSH_SCRATCH_REGISTERS \ + do { \ + __asm volatile ("PUSH {r0, r1, r2, r3}"); \ + } while (0) + + #else + + #define BSP_PUSH_SCRATCH_REGISTERS \ + do { \ + __ASM volatile ( \ + " .syntax unified \n" /* Prevent non-unified syntax */ \ + " push {r0, r1, r2, r3} \n" /* Push scratch registers on stack. */ \ + : /* Output operands: None */ \ + : /* Input operands: None */ \ + : /* Clobbers: None */ \ + ); \ + } while (0) + #endif +#else + #define BSP_PUSH_SCRATCH_REGISTERS do {} while (0) +#endif + +/** Get the value of the stack pointer. */ +#ifndef UNIT_TESTING + + #if defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC) +static inline uint32_t BSP_GET_SP_IAR (void) +{ + uint32_t ret; + __asm volatile ("MOV %0, sp" : "=r" (ret)); + + return ret; +} + + #define BSP_GET_SP() (BSP_GET_SP_IAR()) + #else + #define BSP_GET_SP() \ + ({ \ + uint32_t ret; \ + \ + __ASM volatile ( \ + " .syntax unified \n" /* Prevent non-unified syntax */ \ + " mov %[ret], sp \n" /* Move SP value on a general purpose register . */ \ + :[ret] "=r" (ret) /* Output operands: Store the SP value on ret */ \ + : /* Input operands: None */ \ + : /* Clobbers: None */ \ + ); \ + ret; \ + }) + #endif +#else + #define BSP_GET_SP() (0) +#endif + +/** + * @brief Stop execution if a condition is false, in non-production builds. + * + * Used to detect an unexpected state at run-time during development. + * + * @note In non-production builds, if the condition is false, g_halt_impl() is called. + * + * @note In production builds, the condition is evaluated but nothing else happens, regardless of the outcome. + */ +#define BSP_CHECK_DEBUG(a) \ + do { \ + if (!(a)) { \ + if (0 == BSP_CFG_PRODUCTION_BUILD) { \ + BSP_PUSH_SCRATCH_REGISTERS; \ + g_halt_impl((uintptr_t) BSP_GET_SP()); \ + } \ + } \ + } while (0) + +#ifndef UNIT_TESTING + #define BSP_FATAL_ERROR \ + do { \ + __disable_irq(); \ + __BKPT(2); \ + } while (0) +#else + #define BSP_FATAL_ERROR \ + g_halt_impl(0) +#endif + +/** + * @brief Stop execution if a condition is false. + * + * Used to log and recover from a fatal state at run-time. + * + * @note In non-production builds, if the condition is false, g_halt_impl() is called, which is identical to the + * behavior of BSP_CHECK_DEBUG(). + * + * @note In production builds, if the condition is false, interrupts are disabled and a SW breakpoint is issued. + * If a debugger is attached execution will halt. + * If a debugger is not attached, the breakpoint will be escalated to a Hard_Fault. + */ +#define BSP_CHECK_FATAL(a) \ + do { \ + if (!(a)) { \ + if (0 == BSP_CFG_PRODUCTION_BUILD) { \ + BSP_PUSH_SCRATCH_REGISTERS; \ + g_halt_impl((uintptr_t) BSP_GET_SP()); \ + } \ + else { \ + BSP_FATAL_ERROR; \ + } \ + } \ + } while (0) + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#ifndef FSP_REGISTER_READ + +/* Read a register and discard the result. */ + #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); +#endif + +#ifndef FSP_REG_VAR_FIELD_GET + +/** + * Return the value of a register field, with the register value being stored in a variable + * e.g. + * @code + * uint16_t tmp; + * int counter; + * tmp = CRG_TOP->TRIM_CTRL_REG; + * counter = FSP_REG_VAR_FIELD_GET(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); + * ... + * @endcode + */ + #define FSP_REG_VAR_FIELD_GET(base, reg, field, var) \ + ((var & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) +#endif + +#ifndef FSP_REG_VAR_FIELD_SET + +/** + * Set the value of a register field, with the register value being stored in a variable + * e.g. + * @code + * uint16_t tmp; + * + * tmp = CRG_TOP->TRIM_CTRL_REG; + * FSP_REG_VAR_FIELD_SET(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10); + * FSP_REG_VAR_FIELD_SET(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2); + * CRG_TOP->TRIM_CTRL_REG = tmp; + * ... + * @endcode + */ + #define FSP_REG_VAR_FIELD_SET(base, reg, field, var, val) \ + var = (((unsigned) var & ~((base ## _ ## reg ## _ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) +#endif + +/** + * @brief Sets register bits, indicated by the mask, to a value. + * + * e.g. + * @code + * FSP_REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); + * @endcode + */ +#define FSP_REG_SET_MASKED(base, reg, mask, value) \ + base->reg = ((base->reg & ~(mask)) | ((value) & (mask))) + +/** + * @brief Return the value of a memory field using a mask. + * + * e.g. + * @code + * uint32_t val; + * + * val = FSP_MEM_GET_MASKED(0x50000000, 0x1UL); + * ... + * @endcode + */ +#define FSP_MEM_GET_MASKED(addr, mask) \ + ((*(volatile uint32_t *) (addr) & (mask)) >> (__builtin_ctz(mask))) + +/** + * \brief Get the address of a register value by index (provided a register stride) + * + * \note The register stride should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the stride should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The stride value must be in bytes. The index value (0,1,2...) is multiplied by + * the stride value (in bytes) to find the actual offset of the register. + * + * Returns a register address value by index + */ +#define FSP_REG_ADDR_GET_INDEXED(base, reg, stride, index) \ + ((&base->reg) + (((intptr_t) (index)) * ((stride) / sizeof(base->reg)))) + +/** + * \brief Return the value of a register field by index (provided a register stride). + * + * e.g. + * \code + * uint16_t val; + * uint16_t index = 2 + * + * val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index) + * + * ... + * \endcode + * + * \note The register stride should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the stride should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The stride value must be in bytes. The index value (0,1,2...) is multiplied by + * the stride value (in bytes) to find the actual offset of the register. + * + */ +#define FSP_REG_FIELD_GET_INDEXED(base, reg, field, stride, index) \ + (((*FSP_REG_ADDR_GET_INDEXED(base, reg, (stride), (index))) & \ + (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * @brief Sets memory bits, indicated by the mask, to a value. + * + * e.g. + * @code + * FSP_MEM_SET_MASKED(0x50000000, 0xFF00, 0x1818); + * @endcode + */ +#define FSP_MEM_SET_MASKED(addr, mask, value) \ + (*(volatile uint32_t *) (addr)) = (((*(volatile uint32_t *) (addr)) & ~(mask)) | ((value) & (mask))) + +#define FSP_ARRAY_LENGTH(array) (sizeof((array)) / sizeof((array)[0])) + +/** + * Sets 32-bit wide register bits, indicated by the field, to a value v. + */ +#define FSP_REG_FIELD_SET_BITS32(base, reg, field, v) \ + ((uint32_t) (((uint32_t) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * Access register field mask. + * + * Returns a register field mask (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->SYS_STAT_REG; + * + * if (tmp & FSP_REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) { + * ... + * \endcode + */ +#define FSP_REG_MSK(base, reg, field) (base ## _ ## reg ## _ ## field ## _Msk) + +/** + * Macro to swap the bytes of a 32-bit variable + * + * @param[in] a The 32-bit variable + */ +#define FSP_SWAP32(a) (__REV(a)) + +/** + * Macro to swap the bytes of a 16-bit variable + * + * @param[in] a The 16-bit variable + */ +#define FSP_SWAP16(a) (__REVSH(a)) + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so + * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \ + defined(__ARM_ARCH_7EM__) // CM4 + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else // CM23 + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#ifndef UNIT_TESTING + #if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) + #else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) + #endif +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE() (0) + #define FSP_CRITICAL_SECTION_SET_STATE(x) (void) x + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ +#if (BSP_CFG_MCU_PART_SERIES == 8) + #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) +#else + #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) +#endif + +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif + +/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ +#if BSP_CFG_EARLY_INIT + #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) +#else + #define BSP_SECTION_EARLY_INIT +#endif + +#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); + +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/* + * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register + * from the secure application using the provided non-secure callable functions. + */ + #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) + #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) + #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) +#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/*******************************************************************************************************************//** + * Read a non-secure 8-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 16-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 32-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/* + * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register + * using the non-secure aliased address. + */ + #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) + #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) + #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) +#else + #define FSP_STYPE3_REG8_READ(X, S) (X) + #define FSP_STYPE3_REG16_READ(X, S) (X) + #define FSP_STYPE3_REG32_READ(X, S) (X) +#endif + +#ifdef UNIT_TESTING + #define TESTABLE_STATIC +#else + #define TESTABLE_STATIC static +#endif + +/*******************************************************************************************************************//** + * Macro to enable the debugger + * + ***********************************************************************************************************************/ +#define BSP_DEBUGGER_ENABLE (CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1) + +/*******************************************************************************************************************//** + * Macro to disable the debugger + * + ***********************************************************************************************************************/ +#define BSP_DEBUGGER_DISABLE (CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 0) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +// TIN_HACK_WIFI +#ifdef BSP_MCU_GROUP_RA6W1 + +/* Support 64bit time */ +typedef unsigned long long __time64_t; +typedef __time64_t ra6w1_time_t; +#endif + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C, ///< Called after clocks and C runtime environment have been set up + BSP_WARM_PM_WOKENUP, ///< Called after wake up when power management module is used + BSP_WARM_PM_SLEEP, ///< Called before sleep when power management module is used +} bsp_warm_start_event_t; + +/** + * @brief The AMBA High-Performance Bus (AHB) clock divider + */ +typedef enum e_ahb_clk_div +{ + BSP_AHB_CLK_DIV1 = 0, ///< Divide by 1 + BSP_AHB_CLK_DIV2 = 1, ///< Divide by 2 + BSP_AHB_CLK_DIV4 = 2, ///< Divide by 4 + BSP_AHB_CLK_DIV8 = 3, ///< Divide by 8 + BSP_AHB_CLK_DIV16 = 4, ///< Divide by 16 +#if BSP_MCU_GROUP_RA6W1 + BSP_AHB_CLK_DIV32 = 5, ///< Divide by 32 + BSP_AHB_CLK_DIV64 = 6, ///< Divide by 64 + BSP_AHB_CLK_DIV128 = 7, ///< Divide by 128 +#endif + BSP_AHB_CLK_DIV_INVALID = 8 +} ahb_clk_div_t; + +/* Private enum used in R_FSP_SystemClockHzGet(). */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_SYS_CLK = 0, +#ifndef BSP_MCU_GROUP_RA6W1 + FSP_PRIV_CLOCK_SYS_HCLK, // HCLK + FSP_PRIV_CLOCK_SYS_PCLK, // PCLK + FSP_PRIV_CLOCK_SYS_QCLK, // QSPI clock + FSP_PRIV_CLOCK_UART = 9, // UART clock +#else + FSP_PRIV_CLOCK_CC312 = 1, ///< Security IP + FSP_PRIV_CLOCK_OTP = 2, + FSP_PRIV_CLOCK_OQSPI_FLASH = 3, + FSP_PRIV_CLOCK_QSPI_RAM = 4, + FSP_PRIV_CLOCK_SPI = 5, + FSP_PRIV_CLOCK_TIMER = 6, + FSP_PRIV_CLOCK_I2C = 7, + FSP_PRIV_CLOCK_SDIO = 8, + FSP_PRIV_CLOCK_UART = 9, + FSP_PRIV_CLOCK_AUX_ADC = 10, + FSP_PRIV_CLOCK_WDT = 11, +#endif +} fsp_priv_clock_t; + +/* Private enum used in by bsp_prv_clock_set(), bsp_prv_sysclk_set() and bsp_prv_lpclk_set(). */ +typedef enum e_fsp_priv_source_clock +{ + FSP_PRIV_CLOCK_RCHS = 0, ///< The high-speed on-chip oscillator (RCHS) + FSP_PRIV_CLOCK_XTALM, ///< The main oscillator (XTAL32M) + FSP_PRIV_CLOCK_XTALM_DBLR, ///< The main oscillator (XTAL64M) + FSP_PRIV_CLOCK_PLL, ///< The PLL oscillator + FSP_PRIV_CLOCK_RCLP, ///< The middle-speed on-chip oscillator (RCLP) + FSP_PRIV_CLOCK_RCX, ///< The low-speed on-chip oscillator (RCX) + FSP_PRIV_CLOCK_XTALK, ///< The subclock oscillator (XTAL32K) + FSP_PRIV_CLOCK_DIGITAL, ///< The subclock oscillator (externally supplied digital clock) +} fsp_priv_source_clock_t; + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +typedef void (* bsp_on_error_cb_t)(uintptr_t args); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern bsp_on_error_cb_t g_halt_impl; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); +void R_BSP_SourceClockHzSet(fsp_priv_source_clock_t clock, uint32_t freq); + +// TIN_HACK_WIFI +#ifdef BSP_MCU_GROUP_RA6W1 +bool R_BSP_RetainedIoExecute(); + +#endif + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_FORCEINLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * @brief Get the Sys_clk divider for HCLK + * + * @return current HCLK_DIV value + **********************************************************************************************************************/ +__STATIC_INLINE ahb_clk_div_t bsp_clock_ahb_div_get (void) +{ + ahb_clk_div_t div = BSP_AHB_CLK_DIV1; + +#if BSP_FEATURE_CGC_HAS_HCLK_DIV + div = (ahb_clk_div_t) CRG_TOP->CLK_AMBA_REG_b.HCLK_DIV; + div = div > BSP_AHB_CLK_DIV16 ? BSP_AHB_CLK_DIV16 : div; +#endif + + return div; +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ +#if (BSP_FEATURE_CGC_HAS_PCLK_DIV) || (BSP_FEATURE_HAS_QCLK_DIV) + uint32_t clk_amba_reg = CRG_TOP->CLK_AMBA_REG; +#endif + + uint32_t div = 0; + uint32_t hclk_div = bsp_clock_ahb_div_get(); + uint32_t sys_clk_Hz = SystemCoreClock << hclk_div; + +#ifdef BSP_MCU_GROUP_RA6W1 + uint32_t HCLK = SystemCoreClock / 1; /* CLK_AMBA_REG.HCLK_DIV = 0 */ + uint32_t PERI_CLK = SystemCoreClock; /* due to XTAL mode */ +#endif + switch (clock) + { + case FSP_PRIV_CLOCK_SYS_CLK: + { + break; + } + +#ifndef BSP_MCU_GROUP_RA6W1 + case FSP_PRIV_CLOCK_SYS_HCLK: + { + div = hclk_div; + break; + } + +#else + case FSP_PRIV_CLOCK_CC312: + case FSP_PRIV_CLOCK_OTP: + { + sys_clk_Hz = HCLK; /* there are no dividers applied when SYS_CLK = XTAL40M */ + break; + } + + case FSP_PRIV_CLOCK_OQSPI_FLASH: + case FSP_PRIV_CLOCK_QSPI_RAM: + { + sys_clk_Hz = SystemCoreClock; + break; + } + + case FSP_PRIV_CLOCK_SPI: + { + uint32_t SPI_CLK = 0; + if (3 == CRG_TOP->CLK_CTRL_REG_b.SYS_CLK_SEL) /* SYS_CLK = SYS-PLL */ + { + uint8_t spi_clk_bit = CRG_TOP->CLK_CTRL_REG_b.PLL_SPI_CLK_SEL; + if (0 == spi_clk_bit) /* SPI_CLK = 120Mhz */ + { + SPI_CLK = 120000000; + } + else if (1 == spi_clk_bit) /* SPI_CLK = 96Mhz */ + { + SPI_CLK = 96000000; + } + else if (2 == spi_clk_bit) /* SPI_CLK = 80Mhz */ + { + SPI_CLK = 80000000; + } + else /* SPI_CLK = 53Mhz */ + { + SPI_CLK = 53000000; + } + } + else /* SYS_CLK = XTAL40M */ + { + SPI_CLK = SystemCoreClock; /* due to XTAL mode */ + } + + sys_clk_Hz = SPI_CLK; + break; + } + + case FSP_PRIV_CLOCK_TIMER: + case FSP_PRIV_CLOCK_I2C: + case FSP_PRIV_CLOCK_SDIO: + case FSP_PRIV_CLOCK_UART: + { + sys_clk_Hz = CRG_TOP->CLK_CTRL_REG_b.PLL_PERI_ENABLE ? 2 * PERI_CLK : PERI_CLK; + break; + } + + case FSP_PRIV_CLOCK_AUX_ADC: + { + uint32_t AUX_CLK = 15000000; /* 15 MHz */ + sys_clk_Hz = AUX_CLK; + break; + } + + case FSP_PRIV_CLOCK_WDT: + { + #if BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_XTALK + sys_clk_Hz = BSP_CFG_XTALK_HZ; + #else + sys_clk_Hz = BSP_RCX_HZ; + #endif + break; + } +#endif +#if BSP_FEATURE_CGC_HAS_PCLK_DIV + case FSP_PRIV_CLOCK_SYS_PCLK: + { + div = hclk_div + FSP_REG_VAR_FIELD_GET(CRG_TOP, CLK_AMBA_REG, PCLK_DIV, clk_amba_reg); + break; + } +#endif +#if BSP_FEATURE_HAS_QCLK_DIV + case FSP_PRIV_CLOCK_SYS_QCLK: + { + div = FSP_REG_VAR_FIELD_GET(CRG_TOP, CLK_AMBA_REG, QSPI_SDR_DIV2, clk_amba_reg); + break; + } +#endif +#if BSP_MCU_GROUP_RA6W3 + case FSP_PRIV_CLOCK_UART: + { + #if defined(BOARD_RA6W3XX_PAL) + sys_clk_Hz = EMULATOR_BASE_CLOCK; + #endif + break; + } +#endif + default: + { + BSP_CHECK_FATAL(0); + } + } + + return sys_clk_Hz >> div; +} + +/*******************************************************************************************************************//** + * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). + * + * @return Clock Divider + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) +{ + if (2U >= ckdivcr) + { + + /* clock_div: + * - Clock Divided by 1: 0 + * - Clock Divided by 2: 1 + * - Clock Divided by 4: 2 + */ + return 1 << ckdivcr; + } + else if (3U == ckdivcr) + { + + /* Clock Divided by 6 */ + return 6U; + } + else if (4U == ckdivcr) + { + + /* Clock Divided by 8 */ + return 8U; + } + else if (5U == ckdivcr) + { + + /* Clock Divided by 3 */ + return 3U; + } + + /* Clock Divided by 5 */ + return 5U; +} + +#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI/SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) +{ + uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; + uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; + + return R_BSP_SourceClockHzGet(scispicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_BSP_HAS_SPI_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) +{ + uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t spicksel = + (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> + R_SYSTEM_SPICKCR_CKSEL_Pos); + + return R_BSP_SourceClockHzGet(spicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_BSP_HAS_SCI_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) +{ + uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scicksel = + (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> + R_SYSTEM_SCICKCR_SCICKSEL_Pos); + + return R_BSP_SourceClockHzGet(scicksel) / clock_div; +} + +#endif + +/*******************************************************************************************************************//** + * Get unique ID for this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) +{ + + // TODO + return 0; +#if 0 + + return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; +#endif +} + +/*******************************************************************************************************************//** + * Disables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheDisable (void) +{ +#if BSP_FEATURE_BSP_FLASH_CACHE + R_FCACHE->FCACHEE = 0U; +#endif + +#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE + + /* Disable the C-Cache. */ + R_CACHE->CCACTL = 0U; +#endif +} + +/*******************************************************************************************************************//** + * Enables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheEnable (void) +{ +#if BSP_FEATURE_BSP_FLASH_CACHE + + /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache + * in the RA6M3 manual R01UH0878EJ0100). */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; +#endif + +#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE + + /* Configure the C-Cache line size. */ + R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; + + /* Enable the C-Cache. */ + R_CACHE->CCACTL = 1U; +#endif +} + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR or CUSTOM_BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if defined(CUSTOM_UNRECOVERABLE_ERROR_HANDLER) + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) CUSTOM_UNRECOVERABLE_ERROR_HANDLER +#elif !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** + * Streamlined version of memcpy(). + * + * It is optimized for the following cases: + * - dest and src are 32-bit aligned + * - if n is larger than 32, blocks of 32 bytes are copied, to the extent possible + * - if n is larger than 16, blocks of 16 bytes are copied, to the extent possible + */ +extern void * fast_memcpy(void * dest, const void * src, size_t n); + +/** + * Streamlined version of memset(). + * + * It is optimized for the following cases: + * - if n is larger than 32, blocks of 32 bytes are set, to the extent possible + * - if n is larger than 16, blocks of 16 bytes are set, to the extent possible + */ +extern void * fast_memset(void * b, int c, size_t len); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_compiler_support.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_compiler_support.h new file mode 100644 index 000000000000..69e11c232bb9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_compiler_support.h @@ -0,0 +1,124 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H + #define BSP_COMPILER_SUPPORT_H + + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include "arm_cmse.h" + #endif + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #ifndef BSP_SECTION_HEAP + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" + #endif + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_NO_INLINE __attribute__((noinline)) + #define BSP_READ_ONLY + #elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #ifndef BSP_SECTION_HEAP + #define BSP_SECTION_HEAP ".heap" + #endif + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_NO_INLINE __attribute__((noinline)) + #define BSP_READ_ONLY + #elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #ifndef BSP_SECTION_HEAP + #define BSP_SECTION_HEAP "HEAP" + #endif + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #define BSP_NO_INLINE _Pragma("inline=never") + #define BSP_READ_ONLY __ro_placement + #endif + + #ifndef BSP_SECTION_STACK + #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" + #endif + + #ifdef BSP_MCU_GROUP_RA6W1 + #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" + #else + #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".ram_noinit" + #endif + + #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" + #define BSP_SECTION_PREINIT ".preinit_array" + #define BSP_SECTION_INIT ".init_array" + #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" + #define BSP_SECTION_CODE_IN_RAM ".ram_code_from_flash" + +/* #define BSP_SECTION_ROM_REGISTERS ".rom_registers" */ +/* #define BSP_SECTION_ID_CODE ".id_code" */ + +/* Compiler neutral macros. */ + #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + + #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + + #define BSP_PLACE_CODE_IN_RAM BSP_PLACE_IN_SECTION(BSP_SECTION_CODE_IN_RAM) + +/* #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED */ + + #define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ + #define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * TrustZone definitions + **********************************************************************************************************************/ + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif + #else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY + #endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.c new file mode 100644 index 000000000000..f8a95090aa2e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.c @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" +#if dg_configUSE_CLOCK_MGR + #include "sys_clock_mgr.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_OVERHEAD_CYCLES (72) +#define BSP_CYCLES_PER_DELAY_REP (4) +#define BSP_MAX_DELAY_CYCLES (0xFFFFFFFF) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * + * @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires + * that the BSP has already initialized the CGC (which it does as part of the Sysinit). + * Care should be taken to ensure this remains the case if in the future this function were to be called as part + * of the BSP initialization. + * + * @note Delays may be longer than expected when compiler optimization is turned off. + **********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#pragma GCC push_options +#pragma GCC optimize ("O3") +#endif +BSP_PLACE_CODE_IN_RAM void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t cpu_clk_Mhz; + uint32_t reps = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + + static const uint8_t OVERHEAD_REPS = BSP_DELAY_OVERHEAD_CYCLES / BSP_CYCLES_PER_DELAY_REP; + +#if dg_configUSE_CLOCK_MGR + FSP_CRITICAL_SECTION_DEFINE; + + FSP_CRITICAL_SECTION_ENTER; + cpu_clk_Mhz = cm_cpu_clk_get_fromISR(); + FSP_CRITICAL_SECTION_EXIT; +#else + static const uint32_t DIVIDER = 1000000; + + cpu_clk_Mhz = SystemCoreClock / DIVIDER; /** Get the system clock frequency in Hz. */ +#endif + +#if BSP_FEATURE_CGC_HAS_HCLK_DIV + uint32_t hclk_div; + hclk_div = CRG_TOP->CLK_AMBA_REG_b.HCLK_DIV; + + cpu_clk_Mhz = cpu_clk_Mhz >> hclk_div; +#endif + + reps = cpu_clk_Mhz * total_us / BSP_CYCLES_PER_DELAY_REP; + +#ifdef CLK_DELAY_SANITY_CHECKS + BSP_CHECK_DEBUG(usec <= (BSP_MAX_DELAY_CYCLES / cpu_clk_Mhz)); // The requested delay is greater than the maximum delay this function can achieve + BSP_CHECK_DEBUG(reps > OVERHEAD_REPS); // The requested delay is smaller than the minimum delay this function can achieve. +#endif + + /** Only delay if the supplied parameters constitute a delay. */ + if ((reps <= OVERHEAD_REPS) || (total_us > (BSP_MAX_DELAY_CYCLES / cpu_clk_Mhz))) + { + return; + } + __asm volatile ( + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + "loop: nop \n" + " subs %[reps], %[reps], #1 \n" + " bne loop \n" + : // outputs + :[reps] "r" (reps - OVERHEAD_REPS) // inputs + : // clobbers + ); +} + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#pragma GCC pop_options +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.h new file mode 100644 index 000000000000..77b966a707b2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_delay.h @@ -0,0 +1,73 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #if defined(RENESAS_CORTEX_M85) + +/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for + * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in + * this case. */ + #if defined(__ICCARM__) + #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) + #else + #define BSP_DELAY_LOOP_CYCLES (1) + #endif + #else + #define BSP_DELAY_LOOP_CYCLES (4) + #endif +#endif + +/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_device_info.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_device_info.h new file mode 100644 index 000000000000..aadfafc511f7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_device_info.h @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DEVICE_INFO_H +#define BSP_DEVICE_INFO_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_device_info.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_device_info.h" +#elif BSP_MCU_GROUP_RA6B2 + #include "../ra6b2/bsp_device_info.h" +#elif BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_device_info.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_device_info.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* The following functions are defined in the device-specific source files. */ +bool bsp_device_info_init(void); +bool bsp_device_variant_detect(void); +bool bsp_device_info_check(uint32_t mask, uint32_t attribute); +uint32_t bsp_device_info_get(void); +bool bsp_device_info_compatibility_check(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_DEVICE_INFO_H */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_exceptions.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_exceptions.h new file mode 100644 index 000000000000..faa8da1086db --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_exceptions.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_EXCEPTIONS_H + #define BSP_EXCEPTIONS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + + #if !defined(BSP_API_OVERRIDE) + +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + #endif + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_freeze.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_freeze.h new file mode 100644 index 000000000000..4c63d47ea608 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_freeze.h @@ -0,0 +1,20 @@ +#ifndef BSP_FREEZE_H +#define BSP_FREEZE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_freeze.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_freeze.h" +#elif BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_freeze.h" +#elif BSP_MCU_GROUP_RA6B2 + #include "../ra6b2/bsp_freeze.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_freeze.h" +#endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.c new file mode 100644 index 000000000000..9e44c93730e4 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.c @@ -0,0 +1,181 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_MCU_GROUP_RA6W1 + #define BSP_GRP_IRQ_TOTAL_ITEMS (16U) +#else + #define BSP_GRP_IRQ_TOTAL_ITEMS (3U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** This array holds callback functions. */ +bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] BSP_SECTION_EARLY_INIT; + +static void (* g_bsp_group_nmi_cb)(const uint32_t * p_exception_args); + +BSP_WEAK_REFERENCE void NMI_HandlerC(unsigned long * exception_args); +BSP_WEAK_REFERENCE void HardFault_HandlerC(unsigned long * exception_args); +BSP_WEAK_REFERENCE void SecureFault_HandlerC(unsigned long * exception_args); + +#if BSP_FEATURE_BSP_HAS_ICU +static void bsp_group_irq_call(bsp_grp_irq_t irq); + +/*******************************************************************************************************************//** + * Calls the callback function for an interrupt if a callback has been registered. + * + * @param[in] irq Which interrupt to check and possibly call. + * + * @retval FSP_SUCCESS Callback was called. + * @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source. + * + * @warning This function is called from within an interrupt + **********************************************************************************************************************/ +static void bsp_group_irq_call (bsp_grp_irq_t irq) +{ + /** Check for valid callback */ + if (NULL != g_bsp_group_irq_sources[irq]) + { + /** Callback has been found. Call it. */ + g_bsp_group_irq_sources[irq](irq); + } +} + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] irq Interrupt for which to register a callback. + * @param[in] p_callback Pointer to function to call when interrupt occurs. + * + * @retval FSP_SUCCESS Callback registered + * @retval FSP_ERR_ASSERTION Callback pointer is NULL + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value. */ + FSP_ASSERT(p_callback); +#endif + + /* Register callback. */ + g_bsp_group_irq_sources[irq] = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Register a callback function for NMI. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] p_callback Pointer to function to call when NMI occurs. + * + * @retval FSP_SUCCESS Callback registered + * @retval FSP_ERR_ASSERTION Callback pointer is NULL + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupNmiWrite (void (* p_callback)(const uint32_t * p_exception_args)) +{ + g_bsp_group_nmi_cb = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because + * there are many sources that map to the NMI exception. + * + * @note NMI exception is caused due to watchdog timeout for DA1469x and hence the registered callback function + * for handling the WDT error is directly referred + **********************************************************************************************************************/ + +BSP_WEAK_REFERENCE void NMI_HandlerC (unsigned long * exception_args) +{ + FSP_PARAMETER_NOT_USED(exception_args); +#if BSP_FEATURE_BSP_HAS_ICU + uint32_t nmisr = ICU->ICU_NMISR_REG; + + /* Loop over all NMI status flags */ + bsp_grp_irq_t irq = BSP_GRP_IRQ_WDT_ERROR; + if (0U != (nmisr & (1U << irq))) + { + g_bsp_group_nmi_cb((uint32_t *) exception_args); + } + else + { + for ( ; irq <= (bsp_grp_irq_t) (BSP_GRP_IRQ_TOTAL_ITEMS - 1); irq++) + { + /* If the current irq status register is set call the irq callback. */ + if (0U != (nmisr & (1U << irq))) + { + (void) bsp_group_irq_call(irq); + } + } + } + + /* Clear status flags that have been handled. */ + ICU->ICU_NMICLR_REG = nmisr; +#else + if (g_bsp_group_nmi_cb != NULL) + { + g_bsp_group_nmi_cb((uint32_t *) exception_args); + } + else + { + /* Wait for the reset to occur */ + while (1) + { + } + } +#endif +} + +BSP_WEAK_REFERENCE void HardFault_HandlerC (unsigned long * exception_args) +{ + FSP_PARAMETER_NOT_USED(exception_args); + + while (1) + { + } +} + +BSP_WEAK_REFERENCE void SecureFault_HandlerC (unsigned long * exception_args) +{ + FSP_PARAMETER_NOT_USED(exception_args); + + while (1) + { + } +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.h new file mode 100644 index 000000000000..9c9e0df733ba --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_group_irq.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_GROUP_IRQ_T + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_WDT_ERROR = 0, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_VBATT = 1, ///< VBATT monitor interrupt + BSP_GRP_IRQ_TRUSTZONE = 2, ///< MPU Stack Error +} bsp_grp_irq_t; + +#endif + +/* Callback type. */ +typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_group_interrupt_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.c new file mode 100644 index 000000000000..03db6309c2a0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_guard.h" + +/* Only the secure project has nonsecure callable functions. */ +#if BSP_TZ_SECURE_BUILD + +extern uint32_t g_bsp_reset_stat_reg; + +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_ResetStatusGet (void) +{ + return g_bsp_reset_stat_reg; +} + +/* If the CGG Security Attribution is configured to secure access only. */ + #if BSP_CFG_CLOCKS_SECURE == 1 + +/*******************************************************************************************************************//** + * Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed. + * + * @retval FSP_SUCCESS Callback set. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + bsp_clock_update_callback_t p_callback_checked = + (bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE); + + bsp_clock_update_callback_args_t * p_callback_memory_checked = + (bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory, + sizeof(bsp_clock_update_callback_args_t), + CMSE_AU_NONSECURE); + FSP_ASSERT(p_callback == p_callback_checked); + FSP_ASSERT(p_callback_memory == p_callback_memory_checked); + + r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked); + + return FSP_SUCCESS; +} + + #endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.h new file mode 100644 index 000000000000..066477b67c65 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_guard.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_ResetStatusGet(void); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_io.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_io.h new file mode 100644 index 000000000000..78ff01ad9526 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_io.h @@ -0,0 +1,408 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/*********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ + +/* Gets MCU configuration information. */ +#include "bsp_api.h" + +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_io.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_io.h" +#elif BSP_MCU_GROUP_RA6B2 + #include "../ra6b2/bsp_io.h" +#elif BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_io.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_io.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define BSP_IO_PORT_BITS (0xC0U) +#define BSP_IO_PIN_BITS (0x3FU) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define BSP_IO_PORT_OFFSET (6U) + +#define BSP_IO_PXX_MODE_REG(_port, _pin) \ + *(&(GPIO->P0_00_MODE_REG) + (((_port) == 0) ? 0 : \ + ((_port) == 1) ? BSP_FEATURE_IO_PORT0_GPIO_COUNT : \ + BSP_FEATURE_IO_PORT0_GPIO_COUNT + BSP_FEATURE_IO_PORT1_GPIO_COUNT) + (_pin)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0x0, ///< Input + BSP_IO_DIRECTION_OUTPUT = 0x300, ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x00, ///< IO port 0 + BSP_IO_PORT_01 = 0x01, ///< IO port 1 + BSP_IO_PORT_02 = 0x02, ///< IO port 2 + + /** Marks end of enum */ + BSP_IO_PORT_MAX, +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x00, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x01, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_02 = 0x02, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_03 = 0x03, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_04 = 0x04, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_05 = 0x05, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_06 = 0x06, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_07 = 0x07, ///< IO port 0 pin 7 + BSP_IO_PORT_00_PIN_08 = 0x08, ///< IO port 0 pin 8 + BSP_IO_PORT_00_PIN_09 = 0x09, ///< IO port 0 pin 9 + BSP_IO_PORT_00_PIN_10 = 0x0A, ///< IO port 0 pin 10 + BSP_IO_PORT_00_PIN_11 = 0x0B, ///< IO port 0 pin 11 + BSP_IO_PORT_00_PIN_12 = 0x0C, ///< IO port 0 pin 12 + BSP_IO_PORT_00_PIN_13 = 0x0D, ///< IO port 0 pin 13 + BSP_IO_PORT_00_PIN_14 = 0x0E, ///< IO port 0 pin 14 + BSP_IO_PORT_00_PIN_15 = 0x0F, ///< IO port 0 pin 15 + BSP_IO_PORT_00_PIN_16 = 0x10, ///< IO port 0 pin 16 + BSP_IO_PORT_00_PIN_17 = 0x11, ///< IO port 0 pin 17 + BSP_IO_PORT_00_PIN_18 = 0x12, ///< IO port 0 pin 18 + BSP_IO_PORT_00_PIN_19 = 0x13, ///< IO port 0 pin 19 + BSP_IO_PORT_00_PIN_20 = 0x14, ///< IO port 0 pin 20 + BSP_IO_PORT_00_PIN_21 = 0x15, ///< IO port 0 pin 21 + BSP_IO_PORT_00_PIN_22 = 0x16, ///< IO port 0 pin 22 + BSP_IO_PORT_00_PIN_23 = 0x17, ///< IO port 0 pin 23 + BSP_IO_PORT_00_PIN_24 = 0x18, ///< IO port 0 pin 24 + BSP_IO_PORT_00_PIN_25 = 0x19, ///< IO port 0 pin 25 + BSP_IO_PORT_00_PIN_26 = 0x1A, ///< IO port 0 pin 26 + BSP_IO_PORT_00_PIN_27 = 0x1B, ///< IO port 0 pin 27 + BSP_IO_PORT_00_PIN_28 = 0x1C, ///< IO port 0 pin 28 + BSP_IO_PORT_00_PIN_29 = 0x1D, ///< IO port 0 pin 29 + BSP_IO_PORT_00_PIN_30 = 0x1E, ///< IO port 0 pin 30 + BSP_IO_PORT_00_PIN_31 = 0x1F, ///< IO port 0 pin 31 + BSP_IO_PORT_01_PIN_00 = 0x40, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x41, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_02 = 0x42, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_03 = 0x43, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_04 = 0x44, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_05 = 0x45, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_06 = 0x46, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_07 = 0x47, ///< IO port 1 pin 7 + BSP_IO_PORT_01_PIN_08 = 0x48, ///< IO port 1 pin 8 + BSP_IO_PORT_01_PIN_09 = 0x49, ///< IO port 1 pin 9 + BSP_IO_PORT_01_PIN_10 = 0x4A, ///< IO port 1 pin 10 + BSP_IO_PORT_01_PIN_11 = 0x4B, ///< IO port 1 pin 11 + BSP_IO_PORT_01_PIN_12 = 0x4C, ///< IO port 1 pin 12 + BSP_IO_PORT_01_PIN_13 = 0x4D, ///< IO port 1 pin 13 + BSP_IO_PORT_01_PIN_14 = 0x4E, ///< IO port 1 pin 14 + BSP_IO_PORT_01_PIN_15 = 0x4F, ///< IO port 1 pin 15 + BSP_IO_PORT_01_PIN_16 = 0x50, ///< IO port 1 pin 16 + BSP_IO_PORT_01_PIN_17 = 0x51, ///< IO port 1 pin 17 + + BSP_IO_PORT_02_PIN_00 = 0x80, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x81, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_02 = 0x82, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_03 = 0x83, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_04 = 0x84, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_05 = 0x85, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_06 = 0x86, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_07 = 0x87, ///< IO port 2 pin 7 + BSP_IO_PORT_02_PIN_08 = 0x88, ///< IO port 2 pin 8 + BSP_IO_PORT_02_PIN_09 = 0x89, ///< IO port 2 pin 9 + BSP_IO_PORT_02_PIN_10 = 0x8A, ///< IO port 2 pin 10 + BSP_IO_PORT_02_PIN_11 = 0x8B, ///< IO port 2 pin 11 + BSP_IO_PORT_02_PIN_12 = 0x8C, ///< IO port 2 pin 12 + + /* TIN-TODO: Only used in Tin, remove if possible. */ + BSP_IO_PORT_FF_PIN_FF = 0xFF, ///< Invalid IO port +} bsp_io_port_pin_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + uint32_t pin_id = pin & BSP_IO_PIN_BITS; + uint32_t port = pin >> BSP_IO_PORT_OFFSET; + __IOM uint32_t * reg = &(GPIO->P0_DATA_REG) + port; + + return ((*reg) >> pin_id) & 1U; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided. + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + uint32_t pin_id = pin & BSP_IO_PIN_BITS; + uint32_t port = pin >> BSP_IO_PORT_OFFSET; + __IOM uint32_t * reg; +#if !defined(BSP_MCU_GROUP_RA6W1) // TIN-TODO: Unify R_BSP_PinWrite() + BSP_IO_PXX_MODE_REG(port, pin_id) = GPIO_W_CFG_PORT_DIRECTION_OUTPUT; +#endif + + if (BSP_IO_LEVEL_LOW == level) + { + reg = &(GPIO->P0_RESET_DATA_REG) + port; + } + else + { + reg = &(GPIO->P0_SET_DATA_REG) + port; + } + + *reg = 1 << pin_id; +} + +/*******************************************************************************************************************//** + * Configure a pin. + * + * @param[in] pin The pin + * @param[in] cfg Configuration for the pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) +{ + uint32_t pin_id = pin & BSP_IO_PIN_BITS; + uint32_t port = pin >> BSP_IO_PORT_OFFSET; + +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + if (BSP_IO_PORT_01 == port) + { + PMU_ANA->POWER_CTRL_REG_b.EN_HSGND = 1; + FSP_HARDWARE_REGISTER_WAIT(PMU_ANA->ANA_STATUS_REG_b.HSGND_OK, 1U); + } +#endif + + BSP_IO_PXX_MODE_REG(port, pin_id) = cfg; +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + * + * @note: The DA HW does not provide such protection, so this function is a NOP. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /* Nothing to do. */ +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + * + * @note: The DA HW does not provide such protection, so this function is a NOP. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /* Nothing to do. */ +#endif +} + +#if BSP_FEATURE_IO_HAS_LATCHING + +/*******************************************************************************************************************//** + * Isolate pads, by disabling the latches of all GPIOs + * + * @note Effectively, the GPIO pads are disconnected from their internal drives and retain their + * current level. + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_io_pads_isolation_enable_all (void) +{ + CRG_TOP->P0_RESET_PAD_LATCH_REG = CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_OPEN_Msk; + CRG_TOP->P1_RESET_PAD_LATCH_REG = CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_OPEN_Msk; + #ifdef CRG_TOP_P2_RESET_PAD_LATCH_REG_P2_RESET_LATCH_OPEN_Msk + CRG_TOP->P2_RESET_PAD_LATCH_REG = CRG_TOP_P2_RESET_PAD_LATCH_REG_P2_RESET_LATCH_OPEN_Msk; + #endif +} + +/*******************************************************************************************************************//** + * De-isolate pads, by enabling the latches of all GPIOs + * + * @note Effectively, the GPIO pads are connected to their internal drives + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_io_pads_isolation_disable_all (void) +{ + CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_OPEN_Msk; + CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_OPEN_Msk; + #ifdef CRG_TOP_P2_SET_PAD_LATCH_REG_P2_SET_LATCH_OPEN_Msk + CRG_TOP->P2_SET_PAD_LATCH_REG = CRG_TOP_P2_SET_PAD_LATCH_REG_P2_SET_LATCH_OPEN_Msk; + #endif +} + +/*******************************************************************************************************************//** + * Disables the latch for the specific gpio. + * + * @param [in] pin The GPIO pin to unlatch + ***********************************************************************************************************************/ +__STATIC_INLINE void bsp_io_pad_isolation_enable (bsp_io_port_pin_t pin) +{ + bsp_io_port_pin_t pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) pin); + bsp_io_port_t port_id = + (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) pin) >> BSP_IO_PORT_OFFSET); + + if (BSP_IO_PORT_00 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT0_GPIO_COUNT); + CRG_TOP->P0_RESET_PAD_LATCH_REG = 1 << pin_id; + } + else if (BSP_IO_PORT_01 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT1_GPIO_COUNT); + CRG_TOP->P1_RESET_PAD_LATCH_REG = 1 << pin_id; + } + + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + else if (BSP_IO_PORT_02 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT2_GPIO_COUNT); + CRG_TOP->P2_RESET_PAD_LATCH_REG = 1 << pin_id; + } + #endif + else + { + /* Invalid port_id. */ + BSP_CHECK_DEBUG(0); + } +} + +/*******************************************************************************************************************//** + * Enables the latch for the specific gpio. + * + * @param[in] pin The GPIO pin to latch + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_io_pad_isolation_disable (bsp_io_port_pin_t pin) +{ + bsp_io_port_pin_t pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) pin); + bsp_io_port_t port_id = + (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) pin) >> BSP_IO_PORT_OFFSET); + + if (BSP_IO_PORT_00 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT0_GPIO_COUNT); + CRG_TOP->P0_SET_PAD_LATCH_REG = 1 << pin_id; + } + else if (BSP_IO_PORT_01 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT1_GPIO_COUNT); + CRG_TOP->P1_SET_PAD_LATCH_REG = 1 << pin_id; + } + + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + else if (BSP_IO_PORT_02 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT2_GPIO_COUNT); + CRG_TOP->P2_SET_PAD_LATCH_REG = 1 << pin_id; + } + #endif + else + { + /* Invalid port_id. */ + BSP_CHECK_DEBUG(0); + } +} + +/*******************************************************************************************************************//** + * Checks if the specific GPIO is latched or not. + * + * @param[in] pin The GPIO pin to check latch status for + **********************************************************************************************************************/ +__STATIC_INLINE bool bsp_io_pad_isolation_is_disabled (bsp_io_port_pin_t pin) +{ + bsp_io_port_pin_t pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) pin); + bsp_io_port_t port_id = + (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) pin) >> BSP_IO_PORT_OFFSET); + + if (BSP_IO_PORT_00 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT0_GPIO_COUNT); + + return CRG_TOP->P0_PAD_LATCH_REG & (1 << pin_id); + } + else if (BSP_IO_PORT_01 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT1_GPIO_COUNT); + + return CRG_TOP->P1_PAD_LATCH_REG & (1 << pin_id); + } + + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + else if (BSP_IO_PORT_02 == port_id) + { + BSP_CHECK_DEBUG(pin_id < BSP_FEATURE_IO_PORT2_GPIO_COUNT); + + return CRG_TOP->P2_PAD_LATCH_REG & (1 << pin_id); + } + #endif + else + { + /* Invalid port_id. */ + BSP_CHECK_DEBUG(0); + } + + return false; +} + +#endif + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.c new file mode 100644 index 000000000000..4be203e42650 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.c @@ -0,0 +1,103 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_BITS_PER_WORD (32) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_IRQ_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_HAS_ICU +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ +#if FSP_PRIV_TZ_USE_SECURE_REGS + #if !BSP_TZ_SECURE_BUILD + + /* Set the DMAC channels to secure access. */ + #ifdef BSP_TZ_CFG_ICUSARC + + // R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk; + #endif + #ifdef BSP_TZ_CFG_DMASARA + + // R_CPSCU->DMASARA = ~R_CPSCU_DMASARA_DMASARAn_Msk; + #endif + #endif + + /* Place all vectors in non-secure state unless they are used in the secure project. */ + uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD]; + memset(&interrupt_security_state, UINT8_MAX, sizeof(interrupt_security_state)); + + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + /* This is a secure vector. Clear the associated bit. */ + uint32_t index = i / BSP_PRV_BITS_PER_WORD; + uint32_t bit = i % BSP_PRV_BITS_PER_WORD; + interrupt_security_state[index] &= ~(1U << bit); + } + } + + /* The Secure Attribute managed within the ARM CPU NVIC must match the security attribution of IELSEn + * (Reference section 13.2.9 in the RA6M4 manual R01UH0890EJ0050). */ + + // uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARG; + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD; i++) + { + // p_icusarg[i] = interrupt_security_state[i]; + NVIC->ITNS[i] = interrupt_security_state[i]; + } +#endif + +#if BSP_FEATURE_BSP_HAS_ICU + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + volatile uint32_t * ielsr_reg = (&(ICU->ICU_IELSR0_REG) + i); + *ielsr_reg = (uint32_t) g_interrupt_event_link_select[i]; + } +#endif +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.h new file mode 100644 index 000000000000..77f3372f8be8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_irq.h @@ -0,0 +1,246 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +#if BSP_FEATURE_BSP_HAS_ICU + #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_IRQ_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ +#if BSP_FEATURE_BSP_HAS_ICU + + /* Clear the IR bit in the selected IELSR register. */ + volatile uint32_t * ielsr_reg = (&(ICU->ICU_IELSR0_REG) + irq); + *ielsr_reg &= ~ICU_ICU_IELSR0_REG_ICU_IR_Msk; + + /* Read back the IELSR register to ensure that the IR bit is cleared. */ + FSP_REGISTER_READ(ielsr_reg); +#else + (void) irq; +#endif +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ + __DMB(); + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +#if BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************//** + * Set the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to set the pending bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqSetPending (IRQn_Type irq) +{ + // TIN-TODO: This seems to be used to induce a GPIO_Px_IRQ interrupt after wakeup. + // But there is no clear test case/use case as to why this is needed in the Tin packs. + // This is probably something that is needed by a demo application and was included in the BSP. + // Ported for now only for Tin, and we should remove it later on and sanitize the relevant application. + uint32_t _irq = (uint32_t) irq; + NVIC->ISPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +#endif + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ +#if (4U == __CORTEX_M) + NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); +#else + NVIC_SetPriority(irq, priority); +#endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + + __COMPILER_BARRIER(); + NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + __COMPILER_BARRIER(); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_mcu_api.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_mcu_api.h new file mode 100644 index 000000000000..b722f0d632a1 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_mcu_api.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +#include "bsp_pd.h" +#include "bsp_pd_ctrl.h" +#include "bsp_device_info.h" +#include "bsp_linker_info.h" +#include "bsp_assert.h" + +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + #include "bsp_rsip.h" +#endif + +#include "bsp_freeze.h" +#if BSP_MCU_GROUP_RA6W1 + #include "bsp_otp.h" + #include "../ra6w1/bsp_io_isolation.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +fsp_err_t R_BSP_GroupNmiWrite(void (* p_callback)(const uint32_t * p_exception_args)); + +BSP_PLACE_CODE_IN_RAM void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_module_stop.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_module_stop.h new file mode 100644 index 000000000000..0fd3cfe6d8ec --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_module_stop.h @@ -0,0 +1,183 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/* MSTPCRA is located in R_MSTP for Star devices. */ + #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) +#else + +/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ + #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) +#endif + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ + +#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); +#else + #if (2U == BSP_FEATURE_ELC_VERSION) + #if BSP_MCU_GROUP_RA6T2 + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #endif + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #endif +#endif + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); +#else + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); +#endif +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_otp.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_otp.h new file mode 100644 index 000000000000..e48c7d4e0d90 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_otp.h @@ -0,0 +1,54 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_OTP_H +#define BSP_OTP_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#if BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_otp.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_otp.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_otp_init(void); +void bsp_otp_timings_set(uint32_t sysclk_freq_MHz); +void bsp_otp_mode_set(uint32_t mode); +void bsp_otp_close(void); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.c new file mode 100644 index 000000000000..ccb68b94ec01 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.c @@ -0,0 +1,270 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// Check if the RTC power domain exists in the MCU +#if (BSP_MCU_GROUP_RA6B1) || (BSP_MCU_GROUP_RA6U1) || (BSP_MCU_GROUP_RA6B2) || (BSP_MCU_GROUP_RA6W3) + #define PD_RTC_CHECK (BSP_PD_RTC == power_domain) // All power domains use PMU_CTRL_REG, except RTC which uses PMU_AON_CTRL_REG +#elif (BSP_MCU_GROUP_RA6W1) + #define PD_RTC_CHECK 0 +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef void (* power_domain_ctrl_func)(uint32_t mask, bool is_aon); + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +TESTABLE_STATIC uint8_t bsp_prv_pd_ref_cnt[BSP_PD_ID_COUNT]; + +__STATIC_FORCEINLINE bool valid_pd_check (uint32_t pd_id) +{ + return pd_id < BSP_PD_ID_COUNT; +} + +#ifdef UNIT_TESTING +BSP_WEAK_REFERENCE void hook_for_testable_busy_register_check(uintptr_t reg, uint32_t mask); + +BSP_WEAK_REFERENCE void hook_for_testable_busy_register_check (uintptr_t reg, uint32_t mask) +{ + /* Do nothing. */ + (void) reg; + (void) mask; +} + +#endif + +__STATIC_FORCEINLINE bool pd_is_up_check (uint32_t is_up_mask) +{ + if (0 == is_up_mask) + { + return true; + } + + return bsp_prv_pd_is_up_check(is_up_mask); +} + +__STATIC_FORCEINLINE bool nonzero_cnt_check (uint32_t pd_id) +{ + return bsp_prv_pd_ref_cnt[pd_id] > 0; +} + +__STATIC_FORCEINLINE void atomic_use_pd (bsp_power_domain_t power_domain, uint32_t mask) +{ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if ((0 == bsp_prv_pd_ref_cnt[power_domain]++) && (mask != 0)) + { + bsp_prv_pd_enable(mask, PD_RTC_CHECK); + } + + FSP_CRITICAL_SECTION_EXIT; +} + +__STATIC_FORCEINLINE void atomic_unuse_pd (bsp_power_domain_t power_domain, uint32_t mask) +{ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if ((0 == --bsp_prv_pd_ref_cnt[power_domain]) && (mask != 0)) + { + bsp_prv_pd_disable(mask, PD_RTC_CHECK); + } + + FSP_CRITICAL_SECTION_EXIT; +} + +__STATIC_FORCEINLINE void enable_with_counter (uint32_t pd_id) +{ + // compute masks before turning off interrupts + uint32_t sleep_mask; + uint32_t is_up_mask; + + bsp_prv_pd_masks_get((bsp_power_domain_t) pd_id, &sleep_mask, &is_up_mask); + atomic_use_pd((bsp_power_domain_t) pd_id, sleep_mask); + + while (!pd_is_up_check(is_up_mask)) + { +#ifdef UNIT_TESTING + hook_for_testable_busy_register_check((uintptr_t) &CRG_TOP->SYS_STAT_REG, is_up_mask); +#endif + } +} + +__STATIC_FORCEINLINE void disable_with_counter (bsp_power_domain_t power_domain) +{ + // compute masks before turning off interrupts + uint32_t sleep_mask; + uint32_t is_up_mask; + + bsp_prv_pd_masks_get(power_domain, &sleep_mask, &is_up_mask); + atomic_unuse_pd(power_domain, sleep_mask); +} + +__STATIC_FORCEINLINE void atomic_control (power_domain_ctrl_func func, bsp_power_domain_t power_domain) +{ + // compute masks before turning off interrupts + uint32_t sleep_mask; + uint32_t is_up_mask; + bool is_aon = PD_RTC_CHECK; + + bsp_prv_pd_masks_get(power_domain, &sleep_mask, &is_up_mask); + + if (0 == sleep_mask) + { + return; + } + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + func(sleep_mask, is_aon); + + FSP_CRITICAL_SECTION_EXIT; +} + +__STATIC_FORCEINLINE void atomic_enable (bsp_power_domain_t power_domain) +{ + atomic_control(bsp_prv_pd_enable, power_domain); +} + +__STATIC_FORCEINLINE void atomic_disable (bsp_power_domain_t power_domain) +{ + atomic_control(bsp_prv_pd_disable, power_domain); +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** + * Initialize (zero) the reference counters of all power domains + */ +void bsp_pd_init (void) +{ + for (bsp_power_domain_t pd = (bsp_power_domain_t) 0; pd < BSP_PD_ID_COUNT; pd++) + { + bsp_prv_pd_ref_cnt[pd] = 0; + } +} + +/** + * Denote starting the use of a power domain + * + * If the power domain \p pd_id was previously unused, it will be enabled. + * A per-power-domain reference counter is used to allow for nested calls of this function. + * + * @param [in] pd_id ID of the power domain to start using + * + * @sa bsp_pd_unuse + */ +BSP_PLACE_CODE_IN_RAM void bsp_pd_use (uint32_t pd_id) +{ + BSP_CHECK_DEBUG(valid_pd_check(pd_id)); + + enable_with_counter(pd_id); + + /* detect overflow */ + BSP_CHECK_FATAL(nonzero_cnt_check(pd_id)); +} + +/** + * Denote ending the use of a power domain + * + * A per-power-domain reference counter is used to allow for nested calls of this function. + * If the reference counter of the power domain \p pd_id reaches zero, the power domain will be disabled. + * + * @param [in] pd_id ID of the power domain to stop using + * + * @sa bsp_pd_use + */ +BSP_PLACE_CODE_IN_RAM void bsp_pd_unuse (uint32_t pd_id) +{ + BSP_CHECK_DEBUG(valid_pd_check(pd_id)); + + /* detect imminent underflow */ + BSP_CHECK_FATAL(nonzero_cnt_check(pd_id)); + + disable_with_counter((bsp_power_domain_t) pd_id); +} + +/** + * Check is a power domain is denoted as used (i.e. its reference counter is non-zero) + * + * @param [in] pd_id ID of the power domain to check + */ +BSP_PLACE_CODE_IN_RAM bool bsp_pd_used_check (uint32_t pd_id) +{ + return nonzero_cnt_check(pd_id); +} + +/** + * Return the "IS_UP" status of a power domain + * + * @param [in] pd_id ID of the power domain to check + * + * @retval true if the power domain is up (activated) + * @retval false if the power domain is down (deactivated) + */ +bool bsp_pd_is_up_check (uint32_t pd_id) +{ + uint32_t sleep_mask; + uint32_t is_up_mask; + + bsp_prv_pd_masks_get((bsp_power_domain_t) pd_id, &sleep_mask, &is_up_mask); + + return pd_is_up_check(is_up_mask); +} + +/** + * Enable (i.e. take out of power-down) a power domain + * + * @param [in] pd_id ID of the power domain to enable + */ +BSP_PLACE_CODE_IN_RAM void bsp_pd_enable (uint32_t pd_id) +{ + BSP_CHECK_DEBUG(valid_pd_check(pd_id)); + + atomic_enable((bsp_power_domain_t) pd_id); +} + +/** + * Disable (i.e. put in power-down) a power domain + * + * @param [in] pd_id ID of the power domain to disable + */ +BSP_PLACE_CODE_IN_RAM void bsp_pd_disable (uint32_t pd_id) +{ + BSP_CHECK_DEBUG(valid_pd_check(pd_id)); + + atomic_disable((bsp_power_domain_t) pd_id); +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.h new file mode 100644 index 000000000000..cff58e1d4afa --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_PD_H +#define BSP_PD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_pd.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_pd.h" +#elif BSP_MCU_GROUP_RA6B2 + #include "../ra6b2/bsp_pd.h" +#elif BSP_MCU_GROUP_RA6W1 + #include "../ra6w1/bsp_pd.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_pd.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_pd_init(void); + +BSP_PLACE_CODE_IN_RAM void bsp_pd_use(uint32_t pd_id); + +BSP_PLACE_CODE_IN_RAM void bsp_pd_unuse(uint32_t pd_id); + +BSP_PLACE_CODE_IN_RAM bool bsp_pd_used_check(uint32_t pd_id); + +bool bsp_pd_is_up_check(uint32_t pd_id); + +BSP_PLACE_CODE_IN_RAM void bsp_pd_enable(uint32_t pd_id); + +BSP_PLACE_CODE_IN_RAM void bsp_pd_disable(uint32_t pd_id); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.c new file mode 100644 index 000000000000..ae14cbd254c3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.c @@ -0,0 +1,284 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_pd_ctrl.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define BSP_PRV_DMA_CTRL_REG_OFFSET (8) +#define BSP_PRV_SENSE_REACT_TIMEOUT_ITERATIONS (1000) + +#if defined(BSP_MCU_GROUP_RA6B1) || defined(BSP_MCU_GROUP_RA6U1) || defined(BSP_MCU_GROUP_RA6W3) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static uint32_t bsp_pd_ctrl_prv_entry_translate(bsp_pd_ctrl_entry_t entry); +static bool bsp_prv_pd_ctrl_entry_match(bsp_pd_ctrl_entry_t entry, uint8_t idx); +static void bsp_pd_ctrl_prv_entry_reset(void); + +/*********************************************************************************************************************** + * Exported global variables and functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Read value of a specific PDC LUT entry. + * + * @param[in] idx Index of the entry that is to be read. Valid range: 0 - (BSP_FEATURE_PD_CTRL_VALID_ENTRIES-1) + * @param[out] p_value Pointer to value that was read from the PDC LUT at the given index. + **********************************************************************************************************************/ +void bsp_pd_ctrl_entry_read (uint32_t idx, uint32_t * p_value) +{ + *p_value = PDC->PDC_CTRL_REG[idx]; +} + +/*******************************************************************************************************************//** + * @brief Add a PDC LUT entry dynamically. Scans all LUT entries until it finds an unused one. A LUT entry shall be + * considered unused if it equals BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE. + * + * @param[in] entry Value to be written to the PDC look-up table entry. + * @param[out] p_idx Pointer to variable where index of entry written to the PDC LUT is stored. + * + * @retval BSP_PD_CTRL_SUCCESS Operation was successful and entry was written to the PDC LUT. + * @retval BSP_PD_CTRL_ERROR_PDC_LUT_FULL All PDC LUT entries are used. New entry cannot be added. + **********************************************************************************************************************/ +bsp_pd_ctrl_error_t bsp_pd_ctrl_entry_write (bsp_pd_ctrl_entry_t entry, uint32_t * p_idx) +{ + bool entry_found = false; + + for (uint32_t i = 0; i < BSP_FEATURE_PD_CTRL_VALID_ENTRIES; ++i) + { + if (BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE == PDC->PDC_CTRL_REG[i]) + { + *p_idx = i; + PDC->PDC_CTRL_REG[i] = bsp_pd_ctrl_prv_entry_translate(entry); + entry_found = true; + break; + } + } + + return entry_found ? BSP_PD_CTRL_SUCCESS : BSP_PD_CTRL_ERROR_PDC_LUT_FULL; +} + +/*******************************************************************************************************************//** + * @brief Get the first PDC LUT entry index matching specific criteria. + * + * @param[in] entry Search options provided in the form of a PDC LUT entry. Fields that should not be used to + * filter out potential candidates, must be set to BSP_PD_CTRL_FILTER_DONT_CARE. + * @param[in] start Index of starting search point in the PDC LUT. + * @param[out] p_idx Pointer to variable where index of found entry is stored. + * + * + * @retval BSP_PD_CTRL_SUCCESS Operation was successful, entry was found at index idx. + * @retval BSP_PD_CTRL_ERROR_ENTRY_NOT_FOUND Entry was not found in PDC LUT. + **********************************************************************************************************************/ +bsp_pd_ctrl_error_t bsp_pd_ctrl_entry_find (bsp_pd_ctrl_entry_t entry, uint32_t start, uint32_t * p_idx) +{ + for (uint32_t curr_idx = start; curr_idx < BSP_FEATURE_PD_CTRL_VALID_ENTRIES; ++curr_idx) + { + if (bsp_prv_pd_ctrl_entry_match(entry, (uint8_t) curr_idx)) + { + *p_idx = curr_idx; + + return BSP_PD_CTRL_SUCCESS; + } + } + + return BSP_PD_CTRL_ERROR_ENTRY_NOT_FOUND; +} + +/*******************************************************************************************************************//** + * @brief Remove a PDC LUT entry located in a specific index. Entry will contain BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE + * after the operation is complete. + * + * @param[in] idx Index of the entry that is to be removed. Valid range: 0 - (BSP_FEATURE_PD_CTRL_VALID_ENTRIES-1) + * @param[out] p_value The value of the entry that was removed from the provided index of the PDC LUT. + **********************************************************************************************************************/ +void bsp_pd_ctrl_entry_remove (uint32_t idx, uint32_t * p_value) +{ + bsp_pd_ctrl_entry_read(idx, p_value); + + PDC->PDC_CTRL_REG[idx] = BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE; +} + +/*******************************************************************************************************************//** + * @brief Reset the PDC look-up table. Keeps only the selected PDC LUT entries. All other entries are set to + * BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE. + * + * @param[in] p_keep Pointer to list of entries that should be kept. These entries are + * compared to the ones present in the PDC LUT. Fields that should not be used to + * filter out potential kept entries, must be set to BSP_PD_CTRL_FILTER_DONT_CARE. If + * pointer is null, then all entries are reset. + * @param[in] keep_len Number of entries in the list. + * @param[out] p_kept Pointer to bitmask of entries contained in p_keep that were found in PDC LUT and therefore + * were not removed. + **********************************************************************************************************************/ +void bsp_pd_ctrl_entry_reset (bsp_pd_ctrl_entry_t * p_keep, uint32_t keep_len, uint32_t * p_kept) +{ + uint32_t old_value; + + if (!p_keep) + { + /* keep list is empty */ + bsp_pd_ctrl_prv_entry_reset(); + + /* p_kept is ignored, as all entries are reset and therefore the mask of kept entries is 0. */ + return; + } + + if (p_kept) + { + *p_kept = 0; + } + + for (uint8_t idx = 0; idx < BSP_FEATURE_PD_CTRL_VALID_ENTRIES; idx++) + { + uint8_t keep_idx; + for (keep_idx = 0; keep_idx < keep_len; keep_idx++) + { + if (bsp_prv_pd_ctrl_entry_match(p_keep[keep_idx], idx)) + { + if (p_kept) + { + *p_kept |= (1 << keep_idx); + } + + break; + } + } + + /* Keep-list exhausted without a match, remove unmatched entry */ + if (keep_len == keep_idx) + { + bsp_pd_ctrl_entry_remove(idx, &old_value); + } + } +} + +/*******************************************************************************************************************//** + * @brief Set a PDC LUT entry as pending. + * + * @param[in] idx Index of the entry. Valid range: 0 - (BSP_FEATURE_PD_CTRL_VALID_ENTRIES-1) + * + * @retval BSP_PD_CTRL_SUCCESS Operation was successful. + * @retval BSP_PD_CTRL_ERROR_INVALID_LUT_ENTRY Entry contains invalid master and cannot be set pending. + **********************************************************************************************************************/ +bsp_pd_ctrl_error_t bsp_pd_ctrl_pending_set (uint32_t idx) +{ + uint32_t entry; + + bsp_pd_ctrl_entry_read(idx, &entry); + + if (0 == (entry & PDC_PDC_CTRL_REG_PDC_MASTER_Msk)) + { + return BSP_PD_CTRL_ERROR_INVALID_LUT_ENTRY; + } + + PDC->PDC_SET_PENDING_REG = idx; + + return BSP_PD_CTRL_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Get all pending PDC LUT entries. + * + * @param[out] p_status Pointer to a 16-bit value, where each bit indicates whether the corresponding + * PDC LUT entry is pending. + **********************************************************************************************************************/ +void bsp_pd_ctrl_pending_get (uint32_t * p_status) +{ + *p_status = PDC->PDC_PENDING_REG & PDC_PDC_PENDING_REG_PDC_PENDING_Msk; +} + +/*******************************************************************************************************************//** + * @brief Acknowledge a PDC LUT entry. + * + * @param[in] idx Index of the entry that is to be acknowledged. Valid range: 0 - (BSP_FEATURE_PD_CTRL_VALID_ENTRIES-1) + **********************************************************************************************************************/ +void bsp_pd_ctrl_acknowledge (uint32_t idx) +{ + PDC->PDC_ACKNOWLEDGE_REG = idx; +} + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function that translates the look-up entry structure to the actual 32-bit value + * that is to be written. + **********************************************************************************************************************/ +static uint32_t bsp_pd_ctrl_prv_entry_translate (bsp_pd_ctrl_entry_t entry) +{ + uint32_t reg_value; + + reg_value = (((entry.trig_select) << PDC_PDC_CTRL_REG_TRIG_SELECT_Pos) & PDC_PDC_CTRL_REG_TRIG_SELECT_Msk) | \ + (((entry.trig_id) << PDC_PDC_CTRL_REG_TRIG_ID_Pos) & PDC_PDC_CTRL_REG_TRIG_ID_Msk) | \ + entry.wakeup_options | \ + (((entry.wakeup_master) << PDC_PDC_CTRL_REG_PDC_MASTER_Pos) & PDC_PDC_CTRL_REG_PDC_MASTER_Msk); + + return reg_value; +} + +/*******************************************************************************************************************//** + * Helper function that checks if PDC LUT entry at index idx matches the one provided. + **********************************************************************************************************************/ +static bool bsp_prv_pd_ctrl_entry_match (bsp_pd_ctrl_entry_t entry, uint8_t idx) +{ + uint32_t mask = 0; + uint32_t pattern = 0; + uint32_t val; + + mask |= (entry.trig_select == BSP_PD_CTRL_FILTER_DONT_CARE) ? mask : PDC_PDC_CTRL_REG_TRIG_SELECT_Msk; + mask |= (entry.trig_id == BSP_PD_CTRL_FILTER_DONT_CARE) ? mask : PDC_PDC_CTRL_REG_TRIG_ID_Msk; + mask |= ((entry.wakeup_options == BSP_PD_CTRL_FILTER_DONT_CARE) ? mask : entry.wakeup_options); + mask |= (entry.wakeup_master == BSP_PD_CTRL_FILTER_DONT_CARE) ? mask : PDC_PDC_CTRL_REG_PDC_MASTER_Msk; + + entry.wakeup_options = + (entry.wakeup_options == BSP_PD_CTRL_FILTER_DONT_CARE) ? (bsp_pd_ctrl_options_t) 0 : entry.wakeup_options; + + pattern = bsp_pd_ctrl_prv_entry_translate(entry); + + bsp_pd_ctrl_entry_read(idx, &val); + + return (val & mask) == (pattern & mask); +} + +/*******************************************************************************************************************//** + * Reset PDC look-up table. All entries are set to BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE. + **********************************************************************************************************************/ +static void bsp_pd_ctrl_prv_entry_reset (void) +{ + for (uint32_t idx = 0; idx < BSP_FEATURE_PD_CTRL_VALID_ENTRIES; ++idx) + { + bsp_pd_ctrl_acknowledge(idx); + PDC->PDC_CTRL_REG[idx] = BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE; + } +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.h new file mode 100644 index 000000000000..7944f3244b03 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_pd_ctrl.h @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_PD_CTRL_H +#define BSP_PD_CTRL_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if BSP_MCU_GROUP_RA6B1 + #include "../ra6b1/bsp_pd_ctrl_ra6b1.h" +#elif BSP_MCU_GROUP_RA6U1 + #include "../ra6u1/bsp_pd_ctrl_ra6u1.h" +#elif BSP_MCU_GROUP_RA6W3 + #include "../ra6w3/bsp_pd_ctrl_ra6w3.h" +#endif + +#if defined(BSP_MCU_GROUP_RA6B1) || defined(BSP_MCU_GROUP_RA6U1) || defined(BSP_MCU_GROUP_RA6W3) + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used as an indication of an invalid index of the PDC look-up table. */ + #define BSP_PD_CTRL_INVALID_LUT_INDEX (0xFFFF) + +/** Used as an indication of an unused entry of the PDC look-up table. */ + #define BSP_PD_CTRL_UNUSED_LUT_ENTRY_VALUE (0UL) + +/*******************************************************************************************************************//** + * Used when searching for entries in the PDC look-up table, to indicate that a particular + * field will not be used to filter out potential candidates. + **********************************************************************************************************************/ + #define BSP_PD_CTRL_FILTER_DONT_CARE (0xFF) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Available wakeup source banks to be selected as a trigger in a PDC LUT entry. + **********************************************************************************************************************/ +typedef enum e_bsp_pd_ctrl_trig_select +{ + BSP_PD_CTRL_TRIG_SELECT_P0_GPIO = 0x0, ///< Trigger from GPIO Port 0 through WAKEUP block */ + BSP_PD_CTRL_TRIG_SELECT_P1_GPIO = 0x1, ///< Trigger from GPIO Port 1 through WAKEUP block */ + BSP_PD_CTRL_TRIG_SELECT_P2_GPIO = 0x2, ///< Trigger from GPIO Port 2 through WAKEUP block */ + BSP_PD_CTRL_TRIG_SELECT_PERIPHERAL = 0x3, ///< Trigger from peripheral IRQ, table from device header files */ +} bsp_pd_ctrl_trig_select_t; + +/*******************************************************************************************************************//** + * @brief Error codes specific to the PDC. + **********************************************************************************************************************/ +typedef enum e_bsp_pd_ctrl_error +{ + BSP_PD_CTRL_SUCCESS = 0x0, + BSP_PD_CTRL_ERROR_INVALID_LUT_ENTRY = 0x1, ///< LUT entry contains an invalid master. + BSP_PD_CTRL_ERROR_PDC_LUT_FULL = 0x2, ///< All PDC LUT entries are occupied. + BSP_PD_CTRL_ERROR_ENTRY_NOT_FOUND = 0x3, ///< Entry is not present in the PDC LUT. +} bsp_pd_ctrl_error_t; + +/*******************************************************************************************************************//** + * @brief PDC look-up entry structure. + **********************************************************************************************************************/ +typedef struct st_bsp_pd_ctrl_entry +{ + bsp_pd_ctrl_trig_select_t trig_select; ///< Triggering types. + uint8_t trig_id; ///< Trigger ID. + bsp_pd_ctrl_options_t wakeup_options; ///< Additional wakeup options. + bsp_pd_ctrl_master_t wakeup_master; ///< Wakeup Master ID. +} bsp_pd_ctrl_entry_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_pd_ctrl_entry_read(uint32_t idx, uint32_t * p_value); +bsp_pd_ctrl_error_t bsp_pd_ctrl_entry_write(bsp_pd_ctrl_entry_t entry, uint32_t * p_idx); +bsp_pd_ctrl_error_t bsp_pd_ctrl_entry_find(bsp_pd_ctrl_entry_t entry, uint32_t start, uint32_t * p_idx); +void bsp_pd_ctrl_entry_remove(uint32_t idx, uint32_t * p_value); +void bsp_pd_ctrl_entry_reset(bsp_pd_ctrl_entry_t * p_keep, uint32_t keep_len, uint32_t * p_kept); +bsp_pd_ctrl_error_t bsp_pd_ctrl_pending_set(uint32_t idx); +void bsp_pd_ctrl_pending_get(uint32_t * p_status); +void bsp_pd_ctrl_acknowledge(uint32_t idx); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_rsip.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_rsip.h new file mode 100644 index 000000000000..bfba69c419c9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_rsip.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_RSIP_H +#define BSP_RSIP_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + +/** + * \brief Retrieve key ring and shared key index values from NVR. + */ +BSP_PLACE_CODE_IN_RAM void bsp_prv_rsip_fetch_KeyIndex(void); + +/** + * \brief Get rsip_install_key_ring_index value. + */ +__STATIC_FORCEINLINE uint32_t R_BSP_InstallKeyRingIndexGet (void) +{ + extern volatile uint32_t rsip_install_key_ring_index; + + return rsip_install_key_ring_index; +} + +/** + * \brief Get rsip_SharedKeyIndex value. + */ +__STATIC_FORCEINLINE uint32_t R_BSP_SharedKeyIndexGet (void) +{ + extern volatile uint32_t rsip_SharedKeyIndex; + + return rsip_SharedKeyIndex; +} + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_sbrk.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_sbrk.c new file mode 100644 index 000000000000..341d765e672b --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_sbrk.c @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include "bsp_api.h" +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +caddr_t _sbrk(int incr); // NOLINT + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ + +caddr_t _sbrk (int incr) +{ +#if (BSP_CFG_HEAP_BYTES > 0) + extern uint8_t g_heap[BSP_CFG_HEAP_BYTES]; + + uint32_t bytes = (uint32_t) incr; + static uint32_t current_block_offset = 0; + char * current_block_address; + + current_block_address = (char *) &g_heap[current_block_offset]; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if (current_block_offset + bytes > BSP_CFG_HEAP_BYTES) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_block_offset += bytes; + + return (caddr_t) current_block_address; +#else + FSP_PARAMETER_NOT_USED(incr); + + /** Heap not allocated!!! */ + errno = ENOMEM; + + return (caddr_t) -1; +#endif +} + +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.c new file mode 100644 index 000000000000..fec6d80db7ed --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.c @@ -0,0 +1,308 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) + +/* Branch T3 Instruction (IMM11=-2) */ + #define BSP_PRV_INFINITE_LOOP (0xE7FE) + + #define BSP_SAU_REGION_ROM_NSC (0U) // SAU Region 0 + #define BSP_SAU_REGION_CODE_MRM_NS (1U) // SAU Region 1 + #define BSP_SAU_REGION_CODE_SRAM_NSC (2U) // SAU Region 2 + #define BSP_SAU_REGION_CODE_NVM_NSC (3U) // SAU Region 3 + #define BSP_SAU_REGION_CODE_SRAM_NS (4U) // SAU Region 4 + #define BSP_SAU_REGION_CODE_NVM_NS (5U) // SAU Region 5 + #define BSP_SAU_REGION_CODE_QSPI_NS (6U) // SAU Region 6 + #define BSP_SAU_REGION_DATA_PERIPH_NS (7U) // SAU Region 7 + +/* Non-secure regions defined by the IDAU. These regions must be defined as non-secure in the SAU. */ + +// TODO: Use BSP BASE Address macros instead of magic numbers to define the next addresses + + #define BSP_SAU_REGION_SROM_NSC_BASE_ADDRESS (0x0000010000U) + #define BSP_SAU_REGION_SROM_NSC_LIMIT_ADDRESS ((BSP_SAU_REGION_SROM_NSC_BASE_ADDRESS) +0x0000010000U) + + #define BSP_SAU_REGION_CODE_MRM_NS_BASE_ADDRESS (0x01000020U | BSP_FEATURE_TZ_NS_OFFSET) + #define BSP_SAU_REGION_CODE_MRM_NS_LIMIT_ADDRESS ((BSP_SAU_REGION_CODE_MRM_NS_BASE_ADDRESS) +0x0000003BU) + + #define BSP_SAU_REGION_CODE_SRAM_NS_BASE_ADDRESS (0x03000000U | BSP_FEATURE_TZ_NS_OFFSET) + #define BSP_SAU_REGION_CODE_SRAM_NS_LIMIT_ADDRESS ((BSP_SAU_REGION_CODE_SRAM_NS_BASE_ADDRESS) +0x00FFFFFFU) + + #define BSP_SAU_REGION_CODE_NVM_NS_BASE_ADDRESS (0x04000000U | BSP_FEATURE_TZ_NS_OFFSET) + #define BSP_SAU_REGION_CODE_NVM_NS_LIMIT_ADDRESS ((BSP_SAU_REGION_CODE_NVM_NS_BASE_ADDRESS) +0x00FFFFFFU) + + #define BSP_SAU_REGION_CODE_QSPI_NS_BASE_ADDRESS (0x06000000U | BSP_FEATURE_TZ_NS_OFFSET) + #define BSP_SAU_REGION_CODE_QSPI_NS_LIMIT_ADDRESS ((BSP_SAU_REGION_CODE_QSPI_NS_BASE_ADDRESS) +0x01FFFFFFU) + + #define BSP_SAU_REGION_DATA_PERIPH_NS_BASE_ADDRESS (0x30000000U) + #define BSP_SAU_REGION_DATA_PERIPH_NS_LIMIT_ADDRESS (0x5FFFFFFFU) + +/* Use partition macros for primary core */ + #define FLASH_NSC_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_C_START) + #define FLASH_NSC_LIMIT ((uint32_t) BSP_PARTITION_FLASH_CPU0_C_START + \ + BSP_PARTITION_FLASH_CPU0_C_SIZE - 1) + #define FLASH_NS_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_N_START) + #define RAMCODE_NSC_START ((uint32_t *) BSP_PARTITION_RAMCODE_CPU0_C_START) + #define RAMCODE_NSC_LIMIT ((uint32_t) BSP_PARTITION_RAMCODE_CPU0_C_START + \ + BSP_PARTITION_RAMCODE_CPU0_C_SIZE - 1) + #define RAMCODE_NS_START ((uint32_t *) BSP_PARTITION_RAMCODE_CPU0_N_START) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SecurityInit(void); +void R_BSP_PinCfgSecurityInit(void); +void R_BSP_ElcCfgSecurityInit(void); + +/*********************************************************************************************************************** + * External symbols + **********************************************************************************************************************/ + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); + #endif + + #if BSP_TZ_SECURE_BUILD + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter the non-secure code environment. + * + * This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler. + * + * @note This function (and therefore the non-secure code) should not return. + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter (void) +{ + /* The NS vector table is at the start of the NS section in flash */ + uint32_t const * p_ns_vector_table = (uint32_t *) ((uint32_t) FLASH_NS_START); + + /* Set up the NS Reset_Handler to be called */ + uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); + bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address); + + #if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + p_ns_reset = (bsp_nonsecure_func_t) ((uint32_t) RAM_NS_START); + + /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n )). */ + uint16_t * infinite_loop = (uint16_t *) ((uint32_t) RAM_NS_START); + *infinite_loop = BSP_PRV_INFINITE_LOOP; + + /* Set the NS stack pointer to a valid location in NS RAM. */ + __TZ_set_MSP_NS((uint32_t) RAM_NS_START + 0x20U); + + /* Jump to the infinite loop. */ + p_ns_reset(); +} + #endif + + /* Set the NS vector table address */ + SCB_NS->VTOR = (uint32_t) p_ns_vector_table; + + /* Set the NS stack pointer to the first entry in the NS vector table */ + __TZ_set_MSP_NS(p_ns_vector_table[0]); + + /* Jump to the NS Reset_Handler */ + p_ns_reset(); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Initialize security features for TrustZone. + * + * This function initializes ARM security register and Renesas SAR registers for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SecurityInit (void) +{ + #if __SAUREGION_PRESENT + ICU->ICU_NMIER_REG_b.ICU_TZ_EN = 0x1; // Enable TZ NMI + CRG_TOP->TZ_CFG_REG_b.TZ_EN = 0x1; // Enable TZ + CRG_TOP->TZ_CFG_REG_b.TZ_ERR_RESP = 0x1; // Set NMI response upon TZ error + CRG_TOP->TZ_ERR_STAT_REG_b.TZ_ERR_STAT = 0x1; // Enable TZ error + + // TODO: This register must be set based on the size of the S/NS applications. Temporary split of the NVM between S/NS worlds to enable NS + // TODO: application executed without raising a HardFault due to TZ violation. + SYSB->TZ_NVMB_REG_b.TZ_NVMB = (uint32_t) FLASH_NS_START & SYSB_TZ_NVMB_REG_TZ_NVMB_Msk; + SYSB->TZ_RAMB_REG_b.TZ_RAMB = (uint32_t) RAMCODE_NS_START & SYSB_TZ_RAMB_REG_TZ_RAMB_Msk; + + /* Maintain the default settings of SAU to ensure the SAU attribution for the entire ROM area remains secure. */ + SAU->RNR = BSP_SAU_REGION_ROM_NSC; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_SROM_NSC_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_SROM_NSC_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure MRM */ + SAU->RNR = BSP_SAU_REGION_CODE_MRM_NS; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_CODE_MRM_NS_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_CODE_MRM_NS_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure callable SRAM (Code). */ + SAU->RNR = BSP_SAU_REGION_CODE_SRAM_NSC; + SAU->RBAR = (uint32_t) RAMCODE_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (RAMCODE_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure callable NVM (Code). */ + SAU->RNR = BSP_SAU_REGION_CODE_NVM_NSC; + SAU->RBAR = (uint32_t) FLASH_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (FLASH_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure SRAM (Code). */ + SAU->RNR = BSP_SAU_REGION_CODE_SRAM_NS; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_CODE_SRAM_NS_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_CODE_SRAM_NS_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure NVM (Code). */ + SAU->RNR = BSP_SAU_REGION_CODE_NVM_NS; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_CODE_NVM_NS_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_CODE_NVM_NS_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for always Non-secure QSPI (Code). */ + SAU->RNR = BSP_SAU_REGION_CODE_QSPI_NS; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_CODE_QSPI_NS_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_CODE_QSPI_NS_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure NVM/SRAM (Data) and AHB/APB Peripherals. */ + + // TODO: Consider splitting this SAU region into multiple regions (Optional, as the final security attribution is overruled by IDAU). + SAU->RNR = BSP_SAU_REGION_DATA_PERIPH_NS; + SAU->RBAR = (uint32_t) BSP_SAU_REGION_DATA_PERIPH_NS_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_SAU_REGION_DATA_PERIPH_NS_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Enable the SAU. */ + SAU->CTRL = SAU_CTRL_ENABLE_Msk; + + // Configure Secure Fault Handler + SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk; + + /* Cache maintenance is required when changing security attribution of an address. + * Barrier instructions are required to guarantee intended operation + * (See Arm Cortex-M85 Technical Reference Manual Section 10.9.3). */ + + // SCB_InvalidateICache(); + #else + + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the + * system. */ + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + #endif + + /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from + * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the + * SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */ + #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + + /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target + * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + BSP_PRV_AIRCR_VECTKEY | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif + + #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + /* Configure whether the FPU can be accessed in the non-secure project. */ + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + /* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when + * switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */ + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); + #endif + + /* Initialize SSA Registers. */ + SYSB->TZ_SSA_REG = BSP_TZ_CFG_SSA_REG; + SYSB->TZ_SSA2_REG = BSP_TZ_CFG_SSA2_REG; + + /* Initialize Type 2 SARs. */ + + // TODO: Add Type 2 SARs initialization + + // TODO: Port it or drop it + #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \ + (defined(BSP_TZ_CFG_DMACCHSAR) && \ + ((BSP_TZ_CFG_DMACCHSAR & R_CPSCU_DMACCHSAR_DMACCHSARn_Msk) != R_CPSCU_DMACCHSAR_DMACCHSARn_Msk)) + + R_BSP_MODULE_START(FSP_IP_DMAC, 0); + + /* On MCUs with this implementation of trustzone, DMAST security attribution is set to secure after reset. */ + + /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ + + // R_DMA->DMAST = 1U; + #else + + /* On MCUs with this implementation of trustzone, DMACSAR security attribution is set to secure after reset. + * If the DMAC is not used in the secure application,then configure DMAST security attribution to non-secure. */ + + // R_CPSCU->DMACSAR = 1U; + #endif + + #if BSP_TZ_CFG_DTC_USED + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. */ + + /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ + + // R_DTC->DTCST = 1U; + #elif BSP_FEATURE_TZ_VERSION == 2 // TODO: consider removing it + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. + * If the DTC is not used in the secure application,then configure DTCST security attribution to non-secure. */ + + // R_CPSCU->DTCSAR = 1U; + #endif + + /* Initialize security attribution registers for Pins. */ + R_BSP_PinCfgSecurityInit(); + + /* Initialize security attribution registers for ELC. */ + R_BSP_ElcCfgSecurityInit(); +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void) +{ +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void) +{ +} + + #endif +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.h new file mode 100644 index 000000000000..616342507f3c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/bsp_security.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memcpy.S b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memcpy.S new file mode 100644 index 000000000000..b7d7e14bc614 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memcpy.S @@ -0,0 +1,104 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +#define BLOCK_SIZE_LARGE 32 +#define BLOCK_SIZE_SMALL 16 + + .syntax unified + + .text + .thumb + +/************************************************************************************//** + * @brief Optimized fast_memcpy for ARM Cortex-M33 + * + * void * fast_memcpy(void *dst, const void *src, size_t n); + ***************************************************************************************/ + .thumb_func + .align 1 + .globl fast_memcpy + .type fast_memcpy, %function +fast_memcpy: + /* save r0, as the return value must be "dst" */ + mov r12, r0 + + /* check if both src and dst are 32-bit aligned */ + movs r3, r0 + orrs r3, r1 + lsls r3, r3, #30 + bne .fast_memcpy_bytewise_copy + + /* check buffer size to select larger-block or small-block copying */ + cmp r2, #BLOCK_SIZE_LARGE + bcc .fast_memcpy_small_block + + push {r4-r10} + /* + * Decrement n in advance: we'll check for sign change and then add BLOCK_SIZE_LARGE. + * Assumes that n is less than 2GiB, i.e. its MSBit on entry is 0. + */ + subs r2, #BLOCK_SIZE_LARGE +.fast_memcpy_large_block_copy: + ldmia r1!, {r3-r10} + stmia r0!, {r3-r10} + subs r2, #BLOCK_SIZE_LARGE + bpl .fast_memcpy_large_block_copy + adds r2, #BLOCK_SIZE_LARGE + pop {r4-r10} + +.fast_memcpy_small_block: + /* check buffer size to select small-block or word copying */ + cmp r2, #BLOCK_SIZE_SMALL + bcc .fast_memcpy_word_copy + + push {r4-r6} + /* + * Decrement n in advance: we'll check for sign change and then add BLOCK_SIZE. + * Assumes that n is less than 2GiB, i.e. its MSBit on entry is 0. + */ + subs r2, #BLOCK_SIZE_SMALL +.fast_memcpy_small_block_copy: + ldmia r1!, {r3-r6} + stmia r0!, {r3-r6} + subs r2, #BLOCK_SIZE_SMALL + bpl .fast_memcpy_small_block_copy + adds r2, #BLOCK_SIZE_SMALL + pop {r4-r6} + + /* too little left for block copying, try word copying */ +.fast_memcpy_word_copy: + cmp r2, #3 + bls .fast_memcpy_bytewise_copy + + /* decrement n in advance: we'll check for sign change and then add 4 */ + subs r2, #4 +.fast_memcpy_word_copy_loop: + ldmia r1!, {r3} + stmia r0!, {r3} + subs r2, #4 + bpl .fast_memcpy_word_copy_loop + adds r2, #4 + +.fast_memcpy_bytewise_copy: + /* + * Whatever is left can only be copied byte-by-byte + * (either less than 4 bytes left, or at least one pointer + * is not 32-bit aligned). + */ + cmp r2, #0 + beq .fast_memcpy_exit + push {r4} + movs r4, #0 +.fast_memcpy_byte_copy: + ldrb r3, [r1, r4] + strb r3, [r0, r4] + adds r4, #1 + cmp r4, r2 + bne .fast_memcpy_byte_copy + pop {r4} + +.fast_memcpy_exit: + mov r0, r12 + bx lr + + .pool + .size fast_memcpy, . - fast_memcpy diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memset.S b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memset.S new file mode 100644 index 000000000000..239a52bd9c3c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/fast_memset.S @@ -0,0 +1,97 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + + .syntax unified + + .text + .thumb + +/************************************************************************************//** + * @brief Optimized fast_memset for ARM Cortex-M33 + * + * void * fast_memset(void *b, int c, size_t len); + ***************************************************************************************/ + .thumb_func + .align 1 + .globl fast_memset + .type fast_memset, %function +fast_memset: + push {r4-r6, lr} + mov r12, r0 /* preserve return value */ + + cbz r2, .Ldone + +/* ------------------------------------------------------------ + * Align destination to 4 bytes (byte stores) + * ------------------------------------------------------------ */ +.Lalign: + tst r0, #3 + beq .Lbuild + strb r1, [r0], #1 + subs r2, r2, #1 + bne .Lalign + b .Ldone + +/* ------------------------------------------------------------ + * Build 0xCCCCCCCC fill word + * ------------------------------------------------------------ */ +.Lbuild: + uxtb r1, r1 + orr r3, r1, r1, lsl #8 + orr r3, r3, r3, lsl #16 + mov r4, r3 + mov r5, r3 + mov r6, r3 + +/* ============================================================ + * Case 1: n >= 32 bytes + * 2 × STMIA (16B each) + * ============================================================ */ +.Lcase32: + cmp r2, #32 + blo .Lcase16 + +.Lloop32: + stmia r0!, {r3-r6} /* 16 bytes */ + stmia r0!, {r3-r6} /* 16 bytes */ + subs r2, r2, #32 + cmp r2, #32 + bhs .Lloop32 + +/* ============================================================ + * Case 2: 16 <= n < 32 + * ============================================================ */ +.Lcase16: + cmp r2, #16 + blo .Lcase4 + stmia r0!, {r3-r6} + subs r2, r2, #16 + +/* ============================================================ + * Case 3: 4 <= n < 16 + * ============================================================ */ +.Lcase4: + cmp r2, #4 + blo .Lcase1 + +.Lword_loop: + str r3, [r0], #4 + subs r2, r2, #4 + cmp r2, #4 + bhs .Lword_loop + +/* ============================================================ + * Case 4: n < 4 + * ============================================================ */ +.Lcase1: + cbz r2, .Ldone +.Lbyte_loop: + strb r1, [r0], #1 + subs r2, r2, #1 + bne .Lbyte_loop + +.Ldone: + mov r0, r12 + pop {r4-r6, pc} + + .pool + .size fast_memset, . - fast_memset diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/internal/bsp_device_definitions_internal.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/internal/bsp_device_definitions_internal.h new file mode 100644 index 000000000000..08875e6b8ae0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/all/internal/bsp_device_definitions_internal.h @@ -0,0 +1,347 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DEVICE_DEFINITIONS_INTERNAL_H +#define BSP_DEVICE_DEFINITIONS_INTERNAL_H + +/* + * All device information attributes are OR'ed in a 32-bit value, as indicated below: + * + * 31 21 20 17 16 13 12 11 9 8 4 3 0 + * +------------------+--------------------------+-----------+------------+----------+------------+-----------+ + * | | | | | Version | + * |------------------|--------------------------|-----------|------------+----------+------------+-----------+ + * | Family | Chip ID | Variant | FPGA | REV_x | SWC_x | STEP_x | + * |------------------+--------------------------+-----------+------------+----------+------------+-----------| + * | | 680 69X 59X 70X | | | | | | + * |------------------+--------------------------+-----------+------------+----------+------------+-----------| + * | 00000000000: INV | 0000: INV INV INV INV | 0000: INV | 0: Silicon | 000: INV | 00000: INV | 0000: INV | + * | 00000000001: 680 | 0001: 680 3080 3107 2634 | 0001: 0 | 1: FPGA | 001: D/C | 00001: D/C | 0001: D/C | + * | 00000000010: 69x | 0010: INV 2522 2798 INV | 0010: 1 | | 010: A | 00010: 0 | 0010: A | + * | 00000000011: 59x | | 0011: 2 | | 011: B | 00011: 1 | 0011: B | + * | 00000000100: 70x | | 0100: 3 | | 100: C | 00100: 2 | 0100: C | + * | 00000001000: 310x| | 0101: 4 | | 101: D | 00101: 3 | 0101: D | + * | | | 0111: 5 | | | 00111: 4 | 0111: E | + * | | | 1000: 6 | | | 01000: 5 | 1000: F | + * | | | 1001: 7 | | | 01001: 6 | 1001: G | + * | | | 1010: 8 | | | 01010: 7 | 1010: H | + * | | | 1011: 9 | | | 01011: 8 | | + * | | | | | | 01100: 9 | | + * | | | | | | 01101: 11 | | + * | | | | | | 01110: 12 | | + * | | | | | | 01111: 13 | | + * | | | | | | 10000: 14 | | + * | | | | | | 10001: 15 | | + * +------------------+--------------------------+-----------+------------+----------+------------+-----------+ + * + * INV: Invalid setting. None of the attributes should be 0, apart from the FPGA. + * D/C: Don't care + * RES: Reserved + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Make numerical value */ +#define _DEVICE_MK_NUM_VAL(field, value) (((value) << _DEVICE_ ## field ## _POS) & _DEVICE_ ## field ## _MASK) + +/* Device family definitions */ +#define _DEVICE_FAMILY_MASK 0xFFE00000 // 11 bits length +#define _DEVICE_FAMILY_POS 21 +#define _DEVICE_FAMILY_680 1 +#define _DEVICE_FAMILY_690 2 +#define _DEVICE_FAMILY_590 3 +#define _DEVICE_FAMILY_700 4 +#define _DEVICE_FAMILY_3100 5 +#define _DEVICE_FAMILY_W300 6 +#define _DEVICE_FAMILY_3333 7 +#define _DEVICE_MK_FAMILY(x) _DEVICE_MK_NUM_VAL(FAMILY, _DEVICE_FAMILY_ ## x) + +/* Device Chip ID definitions */ +#define _DEVICE_CHIP_ID_MASK 0x001E0000 // 4 bits length +#define _DEVICE_CHIP_ID_POS 17 +#define _DEVICE_CHIP_ID_680 1 +#define _DEVICE_CHIP_ID_3080 1 +#define _DEVICE_CHIP_ID_2522 2 +#define _DEVICE_CHIP_ID_2634 1 +#define _DEVICE_CHIP_ID_3107 1 +#define _DEVICE_CHIP_ID_2798 2 +#define _DEVICE_CHIP_ID_3108 1 +#define _DEVICE_CHIP_ID_3333 1 +#define _DEVICE_MK_CHIP_ID(x) _DEVICE_MK_NUM_VAL(CHIP_ID, _DEVICE_CHIP_ID_ ## x) + +/* Device variants definitions */ +#define _DEVICE_VARIANT_MASK 0x0001E000 // 4 bits length +#define _DEVICE_VARIANT_POS 13 +#define _DEVICE_VARIANT_XX0 1 +#define _DEVICE_VARIANT_XX1 2 +#define _DEVICE_VARIANT_XX2 3 +#define _DEVICE_VARIANT_XX3 4 +#define _DEVICE_VARIANT_XX4 5 +#define _DEVICE_VARIANT_XX5 6 +#define _DEVICE_VARIANT_XX6 7 +#define _DEVICE_VARIANT_XX7 8 +#define _DEVICE_VARIANT_XX8 9 +#define _DEVICE_VARIANT_XX9 10 +#define _DEVICE_MK_VARIANT(x) _DEVICE_MK_NUM_VAL(VARIANT, _DEVICE_VARIANT_XX ## x) +#define _DEVICE_MK_VARIANT_NUMERICAL(n) _DEVICE_MK_NUM_VAL(VARIANT, _DEVICE_VARIANT_XX0 + (n)) + +/* FPGA definitions */ +#define _DEVICE_FPGA_MASK 0x00001000 // 1 bit length +#define _DEVICE_FPGA_POS 12 + +#define _DEVICE_FPGA_VER_MASK 0x00000FFF // 12 bits length +#define _DEVICE_FPGA_VER_POS 0 +#define _DEVICE_MK_FPGA_VER(n) _DEVICE_MK_NUM_VAL(FPGA_VER, (n)) + +/* Device stepping major sub-revisions (I) */ +#define _DEVICE_REV_MASK 0x00000E00 // 3 bits length +#define _DEVICE_REV_POS 9 +#define _DEVICE_REV_DONT_CARE 1 +#define _DEVICE_REV_A 2 +#define _DEVICE_REV_B 3 +#define _DEVICE_REV_C 4 +#define _DEVICE_REV_D 5 +#define _DEVICE_MK_REV(x) _DEVICE_MK_NUM_VAL(REV, _DEVICE_REV_ ## x) +#define _DEVICE_MK_REV_NUMERICAL(n) _DEVICE_MK_NUM_VAL(REV, ((_DEVICE_REV_DONT_CARE) + (n) + 1)) + +/* Device SW Compatibility code (I) */ +#define _DEVICE_SWC_MASK 0x000001F0 // 5 bits length +#define _DEVICE_SWC_POS 4 +#define _DEVICE_SWC_DONT_CARE 1 +#define _DEVICE_SWC_0 2 +#define _DEVICE_SWC_1 3 +#define _DEVICE_SWC_2 4 +#define _DEVICE_SWC_3 5 +#define _DEVICE_SWC_4 6 +#define _DEVICE_SWC_5 7 +#define _DEVICE_SWC_6 8 +#define _DEVICE_SWC_7 9 +#define _DEVICE_SWC_8 10 +#define _DEVICE_SWC_9 11 +#define _DEVICE_SWC_10 12 +#define _DEVICE_SWC_11 13 +#define _DEVICE_SWC_12 14 +#define _DEVICE_SWC_13 15 +#define _DEVICE_SWC_14 16 +#define _DEVICE_SWC_15 17 +#define _DEVICE_MK_SWC(n) _DEVICE_MK_NUM_VAL(SWC, _DEVICE_SWC_ ## n) +#define _DEVICE_MK_SWC_NUMERICAL(n) _DEVICE_MK_NUM_VAL(SWC, ((_DEVICE_SWC_DONT_CARE) + (n) + 1)) + +/* Device stepping minor subrevisions (I) */ +#define _DEVICE_STEP_MASK 0x0000000F // 4 bits length +#define _DEVICE_STEP_POS 0 +#define _DEVICE_STEP_DONT_CARE 1 +#define _DEVICE_STEP_A 2 +#define _DEVICE_STEP_B 3 +#define _DEVICE_STEP_C 4 +#define _DEVICE_STEP_D 5 +#define _DEVICE_STEP_E 6 +#define _DEVICE_STEP_F 7 +#define _DEVICE_STEP_G 8 +#define _DEVICE_STEP_H 9 +#define _DEVICE_MK_STEP(y) _DEVICE_MK_NUM_VAL(STEP, _DEVICE_STEP_ ## y) +#define _DEVICE_MK_STEP_NUMERICAL(n) _DEVICE_MK_NUM_VAL(STEP, ((_DEVICE_STEP_DONT_CARE) + (n) + 1)) + +#define _DEVICE_MK_VER(x, n, y) (_DEVICE_MK_REV(x) | _DEVICE_MK_SWC(n) | _DEVICE_MK_STEP(y)) + +#define _DEVICE_MASK (_DEVICE_FAMILY_MASK | _DEVICE_CHIP_ID_MASK | \ + _DEVICE_VARIANT_MASK | _DEVICE_FPGA_MASK) + +/* Public definitions */ + +/* RRQ431xx Device Variants */ +#define RRQ43103 (_DEVICE_MK_FAMILY(3100) | _DEVICE_MK_VARIANT(3)) +#define RRQ43107 (_DEVICE_MK_FAMILY(3100) | _DEVICE_MK_VARIANT(7)) +#define RRQ43108 (_DEVICE_MK_FAMILY(3100) | _DEVICE_MK_VARIANT(8)) + +/* FPGA Device */ +#define D3108 (_DEVICE_MK_FAMILY(3100) | DEVICE_CHIP_ID_3108 | \ + _DEVICE_FPGA_MASK | DEVICE_REV_A) + +/* Family Wildcard */ +#define RRQ431XX (_DEVICE_MK_FAMILY(3100)) + +/* RA6B2XX Device Variants */ +/* Family Wildcard */ +#define RA6B2XX (_DEVICE_MK_FAMILY(3333)) + + +/* RA6W3xx Device Variants */ +/* Family Wildcard */ +#define RA6W3XX (_DEVICE_MK_FAMILY(W300)) + +/* DA1469X Device Variants */ +#define DA14691 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(1)) +#define DA14693 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(3)) +#define DA14695 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(5)) +#define DA14697 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(7)) +#define DA14699 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(9)) + +/* FPGA Device */ +#define D2522 (_DEVICE_MK_FAMILY(690) | DEVICE_CHIP_ID_2522 | \ + _DEVICE_FPGA_MASK | DEVICE_REV_A) + +/* Family Wildcard */ +#define DA1469X (_DEVICE_MK_FAMILY(690)) + +/* Device Chip ID */ +#define DEVICE_CHIP_ID_3108 (_DEVICE_MK_CHIP_ID(3108)) +#define DEVICE_CHIP_ID_3080 (_DEVICE_MK_CHIP_ID(3080)) +#define DEVICE_CHIP_ID_2522 (_DEVICE_MK_CHIP_ID(2522)) +#define DEVICE_CHIP_ID_3333 (_DEVICE_MK_CHIP_ID(3333)) + +/* Device Revision */ +#define DEVICE_REV_A (_DEVICE_MK_REV(A)) +#define DEVICE_REV_B (_DEVICE_MK_REV(B)) + +/* Define SWC */ +#define DEVICE_SWC_DONT_CARE (_DEVICE_MK_SWC(DONT_CARE)) +#define DEVICE_SWC_0 (_DEVICE_MK_SWC(0)) +#define DEVICE_SWC_1 (_DEVICE_MK_SWC(1)) +#define DEVICE_SWC_2 (_DEVICE_MK_SWC(2)) +#define DEVICE_SWC_3 (_DEVICE_MK_SWC(3)) +#define DEVICE_SWC_4 (_DEVICE_MK_SWC(4)) +#define DEVICE_SWC_5 (_DEVICE_MK_SWC(5)) +#define DEVICE_SWC_6 (_DEVICE_MK_SWC(6)) +#define DEVICE_SWC_7 (_DEVICE_MK_SWC(7)) +#define DEVICE_SWC_8 (_DEVICE_MK_SWC(8)) +#define DEVICE_SWC_9 (_DEVICE_MK_SWC(9)) +#define DEVICE_SWC_10 (_DEVICE_MK_SWC(10)) +#define DEVICE_SWC_11 (_DEVICE_MK_SWC(11)) +#define DEVICE_SWC_12 (_DEVICE_MK_SWC(12)) +#define DEVICE_SWC_13 (_DEVICE_MK_SWC(13)) +#define DEVICE_SWC_14 (_DEVICE_MK_SWC(14)) +#define DEVICE_SWC_15 (_DEVICE_MK_SWC(15)) + +/* Device Step */ +#define DEVICE_STEP_DONT_CARE (_DEVICE_MK_STEP(DONT_CARE)) +#define DEVICE_STEP_A (_DEVICE_MK_STEP(A)) +#define DEVICE_STEP_B (_DEVICE_MK_STEP(B)) +#define DEVICE_STEP_C (_DEVICE_MK_STEP(C)) +#define DEVICE_STEP_D (_DEVICE_MK_STEP(D)) +#define DEVICE_STEP_E (_DEVICE_MK_STEP(E)) +#define DEVICE_STEP_F (_DEVICE_MK_STEP(F)) +#define DEVICE_STEP_G (_DEVICE_MK_STEP(G)) +#define DEVICE_STEP_H (_DEVICE_MK_STEP(H)) + +/* Device Version */ +#define DEVICE_VER_A0 (_DEVICE_MK_VER(A, 0, DONT_CARE)) +#define DEVICE_VER_A1 (_DEVICE_MK_VER(A, 1, DONT_CARE)) +#define DEVICE_VER_AA (_DEVICE_MK_VER(A, DONT_CARE, A)) +#define DEVICE_VER_AB (_DEVICE_MK_VER(A, DONT_CARE, B)) + +/* + * A generic FPGA check, available for any device family. + */ +#define DEVICE_FPGA ((dg_configDEVICE & _DEVICE_FPGA_MASK) == _DEVICE_FPGA_MASK) + +/* + * Macros checking against specific device characteristics. + * Examples: + * #if (DEVICE_FAMILY == DA1468X) + * #if (DEVICE_CHIP_ID == DEVICE_CHIP_ID_3080) + * #if ((DEVICE_VARIANT == DA14695) || (DEVICE_VARIANT == DA14699)) + * #if (DEVICE_REVISION == DEVICE_REV_B) + * #if ((DEVICE_VERSION == DEVICE_VER_AB) || (DEVICE_VERSION == DEVICE_VER_AE)) + */ + +/* + * FIXME: + * Unused macros copied from SDK10. + * DEVICE_FAMILY commented-out because currently it has to be redefined in CMAC projects' CMakeLists + */ + +// #define DEVICE_FAMILY (dg_configDEVICE & _DEVICE_FAMILY_MASK) +#define DEVICE_CHIP_ID (dg_configDEVICE & _DEVICE_CHIP_ID_MASK) +#define DEVICE_VARIANT (dg_configDEVICE & (_DEVICE_FAMILY_MASK | _DEVICE_VARIANT_MASK)) +#define DEVICE_REVISION (dg_configDEVICE & _DEVICE_REV_MASK) +#define DEVICE_SWC (dg_configDEVICE & _DEVICE_SWC_MASK) +#define DEVICE_STEP (dg_configDEVICE & _DEVICE_STEP_MASK) +#define DEVICE_VERSION (dg_configDEVICE & (_DEVICE_REV_MASK | _DEVICE_SWC_MASK | _DEVICE_STEP_MASK)) + +/* + * Device information attributes masks + */ +#define DEVICE_FAMILY_MASK (_DEVICE_FAMILY_MASK) +#define DEVICE_CHIP_ID_MASK (_DEVICE_CHIP_ID_MASK) +#define DEVICE_VARIANT_MASK (_DEVICE_VARIANT_MASK) +#define DEVICE_REVISION_MASK (_DEVICE_REV_MASK) +#define DEVICE_SWC_MASK (_DEVICE_SWC_MASK) +#define DEVICE_STEP_MASK (_DEVICE_STEP_MASK) + +/* + * Use the next macros to get the minimum acceptable value of specific device information attribute + */ +#define DEVICE_INFO_ATTRIBUTE_MIN(mask) (1 << __CLZ(__RBIT(mask))) +#define DEVICE_FAMILY_MIN (1 << _DEVICE_FAMILY_POS) +#define DEVICE_CHIP_ID_MIN (1 << _DEVICE_CHIP_ID_POS) +#define DEVICE_VARIANT_MIN (1 << _DEVICE_VARIANT_POS) +#define DEVICE_REVISION_MIN (1 << _DEVICE_REV_POS) +#define DEVICE_SWC_MIN (1 << _DEVICE_SWC_POS) +#define DEVICE_STEP_MIN (1 << _DEVICE_STEP_POS) + +/* + * Use the next macros to get the maximum acceptable value of specific device information attribute + */ +#define DEVICE_INFO_ATTRIBUTE_MAX(mask) (mask) +#define DEVICE_FAMILY_MAX _DEVICE_FAMILY_MASK +#define DEVICE_CHIP_ID_MAX _DEVICE_CHIP_ID_MASK +#define DEVICE_VARIANT_MAX _DEVICE_VARIANT_MASK +#define DEVICE_REVISION_MAX _DEVICE_REV_MASK +#define DEVICE_SWC_MAX _DEVICE_SWC_MASK +#define DEVICE_STEP_MAX _DEVICE_STEP_MASK + +/* + * Use the next macros to convert (mask and shift) a specific device information attribute + * extracted from the corresponding registers to bit-field. + */ + +#define MAKE_DEVICE_FAMILY_ENCODING(family) _DEVICE_MK_NUM_VAL(FAMILY, family) +#define MAKE_DEVICE_CHIP_ID_ENCODING(id) _DEVICE_MK_NUM_VAL(CHIP_ID, id) +#define MAKE_DEVICE_VARIANT_ENCODING(variant) _DEVICE_MK_VARIANT_NUMERICAL(variant) +#define MAKE_DEVICE_REVISION_ENCODING(rev) _DEVICE_MK_REV_NUMERICAL(rev) +#define MAKE_DEVICE_SWC_ENCODING(swc) _DEVICE_MK_SWC_NUMERICAL(swc) +#define MAKE_DEVICE_STEP_ENCODING(step) _DEVICE_MK_STEP_NUMERICAL(step) + +#define RRQ43103_3108_00 (RRQ43103 | _DEVICE_MK_CHIP_ID(3108) | DEVICE_VER_A0) +#define RRQ43107_3108_00 (RRQ43107 | _DEVICE_MK_CHIP_ID(3108) | DEVICE_VER_A0) +#define RRQ43108_3108_00 (RRQ43108 | _DEVICE_MK_CHIP_ID(3108) | DEVICE_VER_A0) + +#define DA14691_2522_00 (DA14691 | _DEVICE_MK_CHIP_ID(2522) | _DEVICE_MK_VER(A, DONT_CARE, B)) +#define DA14693_2522_00 (DA14693 | _DEVICE_MK_CHIP_ID(2522) | _DEVICE_MK_VER(A, DONT_CARE, B)) +#define DA14695_2522_00 (DA14695 | _DEVICE_MK_CHIP_ID(2522) | _DEVICE_MK_VER(A, DONT_CARE, B)) +#define DA14697_2522_00 (DA14697 | _DEVICE_MK_CHIP_ID(2522) | _DEVICE_MK_VER(A, DONT_CARE, B)) +#define DA14699_2522_00 (DA14699 | _DEVICE_MK_CHIP_ID(2522) | _DEVICE_MK_VER(A, DONT_CARE, B)) + +#define DA14691_3080_00 (DA14691 | _DEVICE_MK_CHIP_ID(3080) | _DEVICE_MK_VER(A, DONT_CARE, A)) +#define DA14693_3080_00 (DA14693 | _DEVICE_MK_CHIP_ID(3080) | _DEVICE_MK_VER(A, DONT_CARE, A)) +#define DA14695_3080_00 (DA14695 | _DEVICE_MK_CHIP_ID(3080) | _DEVICE_MK_VER(A, DONT_CARE, A)) +#define DA14697_3080_00 (DA14697 | _DEVICE_MK_CHIP_ID(3080) | _DEVICE_MK_VER(A, DONT_CARE, A)) +#define DA14699_3080_00 (DA14699 | _DEVICE_MK_CHIP_ID(3080) | _DEVICE_MK_VER(A, DONT_CARE, A)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef union +{ + uint32_t value; + + struct + { + uint32_t step : 4; + uint32_t swc : 5; + uint32_t revision : 3; + uint32_t is_fpga : 1; + uint32_t variant : 4; + uint32_t chip_id : 4; + uint32_t family : 11; + } bits; +} bsp_device_info_t; + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_cache.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_cache.h new file mode 100644 index 000000000000..171f325aa758 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_cache.h @@ -0,0 +1,178 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CACHE_RA6W1_H +#define BSP_CACHE_RA6W1_H + +// TIN-TODO: This file was originally under cmsis/Device/RENESAS/Include, named hw_cache.h. The contents should be made FSP compliant. + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "sdk_defs.h" + +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* With a 64KB cacheable resolution (i.e. the target memory is addressed in blocks of 64KB), + * and a size of 131072KB of the target memory (MEMORY_OQSPIC_SIZE) the maximum cacheable length + * is 131072 = 131072KB / 64KB. In hex: 0x8000000 / 0x10000 = 0x800. */ +#define HW_CACHE_CACHEABLE_RESOLUTION 0x10000 /* Blocks of 64KB in size */ +#define HW_CACHE_CACHEABLE_LEN_MAX MEMORY_OQSPIC_SIZE / HW_CACHE_CACHEABLE_RESOLUTION + +#define HW_CACHE_FLASH_MIN_REGION_BASE 0xA00 // 0x1800 +#define HW_CACHE_FLASH_MAX_REGION_BASE 0xDFF // 0x1FFF +#define HW_CACHE_FLASH_DEFAULT_REGION_BASE (HW_CACHE_FLASH_MIN_REGION_BASE) + +#define HW_CACHE_FLASH_MIN_REGION_OFFSET 0x0 +#define HW_CACHE_FLASH_MAX_REGION_OFFSET 0xFFF +#define HW_CACHE_FLASH_DEFAULT_REGION_OFFSET (HW_CACHE_FLASH_MIN_REGION_OFFSET) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef uint16_t flash_region_base_t; +typedef uint16_t flash_region_offset_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** + * \brief Enables the iCache Controller + * + * The iCache Controller is enabled by setting the CACHERAM_MUX to '1'. This action enables + * the corresponding HW block, letting the RAM memory of the block be visible only to the + * iCache Controller for caching purposes. + * + */ +__STATIC_INLINE void hw_cache_enable (void) +{ + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX); + + /* Wait until the CACHERAM_MUX=1 (because of the APB Bridge). */ + while (REG_GETF(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX) != 1) + { + } +} + +/** + * \brief Disables the iCache Controller + * + * The iCache Controller is disabled by setting the CACHERAM_MUX to '0'. This action disables + * the corresponding HW block, bypassing the iCache Controller for all read requests + * and letting the RAM memory of the block be visible in the entire memory space. + * + */ +__STATIC_INLINE void hw_cache_disable (void) +{ + REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX); + + /* Wait until the CACHERAM_MUX=0 (because of the APB Bridge). */ + while (REG_GETF(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX) != 0) + { + } +} + +/** + * \brief Checks if the iCache Controller is enabled + * + * \return True if the iCache Controller is enabled, False otherwise. + * + * + */ +__STATIC_INLINE bool hw_cache_is_enabled (void) +{ + return REG_GETF(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX); +} + +/** + * \brief Enable flushing the iCache Controller (cache RAM cells) contents. For debugging only. + */ +__STATIC_INLINE void hw_cache_enable_flushing (void) +{ + REG_CLR_BIT(CACHE, CACHE_CTRL2_REG, CACHE_FLUSH_DISABLE); +} + +/** + * \brief Disable flushing the iCache Controller (cache RAM cells) contents. For debugging only. + */ +__STATIC_INLINE void hw_cache_disable_flushing (void) +{ + REG_SET_BIT(CACHE, CACHE_CTRL2_REG, CACHE_FLUSH_DISABLE); +} + +/** + * \brief Checks if the iCache Controller flushing is disabled. For debugging only. + * + * \return True if the iCache Controller flushing is disabled, False otherwise. + * + * + */ +__STATIC_INLINE bool hw_cache_is_flushing_disabled (void) +{ + return REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_FLUSH_DISABLE); +} + +/** + * \brief Check if the flushing process is complete + * + * \return True if flushing is complete, False if the iCache controller flushing is still + * in progress or there is no pending flushing termination indication as it + * will be cleared via a prior hw_cache_clear_flushed() call. + */ +__STATIC_INLINE bool hw_cache_is_flushed (void) +{ + return REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_FLUSHED); +} + +/** + * \brief Clear the indication that a prior flushing process is complete + */ +__STATIC_INLINE void hw_cache_clear_flushed (void) +{ + REG_CLR_BIT(CACHE, CACHE_CTRL2_REG, CACHE_FLUSHED); +} + +/** + * \brief Flush the cache contents + * + * Note: The very first flushing occurred after power on reset when the iCache Controller + * is enabled for the first time by the booter. + */ +__STATIC_INLINE void hw_cache_flush (void) +{ + if (!hw_cache_is_flushing_disabled()) + { + hw_cache_disable(); + hw_cache_enable(); + + /* Wait for the completion of the flushing process */ + while (hw_cache_is_flushed() == 0) + { + ; + } + + /* Clear the indication that the flushing is complete */ + hw_cache_clear_flushed(); + } +} + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.c new file mode 100644 index 000000000000..8f080113a914 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.c @@ -0,0 +1,842 @@ +/** + * \addtogroup BSP + \{ + * \addtogroup DEVICES + \{ + * \addtogroup CLK + \{ + */ + +/** + **************************************************************************************** + * + * @file ra6w1/bsp_clocks.c + * + * @brief Clock Driver + * + * Copyright (c) 2016-2020 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#if (DEVICE_FAMILY == DA1640X) + +#define USE_FAST_STARTUP 0 + +#include +#include "bsp_api.h" +#include "sdk_defs.h" +#include "bsp_clocks.h" + +#if (dg_configUSE_HW_CLK_DEBUG_GPIO == 1) + #include "hw_gpio.h" +#endif + +#if (dg_configUSE_HW_CLK_DEBUG_GPIO == 1) + #define HW_CLK_DEBUG_GPIO_HIGH() hw_gpio_set_active(HW_GPIO_PORT_1, HW_GPIO_PIN_10) + #define HW_CLK_DEBUG_GPIO_LOW() hw_gpio_set_inactive(HW_GPIO_PORT_1, HW_GPIO_PIN_10) +#else + #define HW_CLK_DEBUG_GPIO_HIGH() + #define HW_CLK_DEBUG_GPIO_LOW() +#endif + +/* macros to adjust RTC access timing */ +#define RTC_POP_ACCESS_TIMING() (RTC->RTC_IF_REG) +#define RTC_PUSH_ACCESS_TIMING(val) (RTC->RTC_IF_REG) = (val) +#define RTC_SET_ACCESS_TIMING(curval, fz, fh, sz) do { \ + (RTC->RTC_IF_REG) = \ + (curval & (~0x00000FFFuL)) \ + | ((sz & 0x0f) << 8) \ + | ((fh & 0x0f) << 4) \ + | ((fz & 0x0f) << 0); \ +} while (0) + +#if USE_FAST_STARTUP +typedef struct +{ + uint16_t temp_refpt; // reference point for temperature compensation + + uint16_t base_drive_cycles; // base drive cycles at room xtal32m_temp_refpt +} xtalm_otp_t; + +__RETAINED static xtalm_otp_t xtalm_otp_values; +#endif + +/*******************************************************************************************************************//** + * Checks if the main oscillator (XTALM) has settled. + * + * @return true if XTALM has settled, false if it hasn't. + **********************************************************************************************************************/ +bool bsp_clock_xtalm_is_settled (void) +{ + return true; +} + +/*********************************************************************************************************************** + * Configures the XTAL32M clock + **********************************************************************************************************************/ +void bsp_clock_xtalm_configure (void) +{ + /* No configuration for XTAL40M. */ +} + +fsp_err_t bsp_clock_xtalm_preconditions_check (void) +{ + /* No preconditions for XTAL40M. */ + return FSP_SUCCESS; +} + +void bsp_clock_xtalm_enable (bool enable) +{ + if (enable) + { + CRG_COM->XTAL40M_CTRL_REG |= CRG_COM_XTAL40M_CTRL_REG_XTAL40M_EN_Msk; + } + else + { + CRG_COM->XTAL40M_CTRL_REG &= ~CRG_COM_XTAL40M_CTRL_REG_XTAL40M_EN_Msk; + } +} + +__RETAINED_CODE void hw_clk_start_calibration(cal_clk_t clk_type, cal_ref_clk_t clk_ref_type, uint16_t cycles); + +__RETAINED_CODE void hw_clk_start_calibration (cal_clk_t clk_type, cal_ref_clk_t clk_ref_type, uint16_t cycles) +{ + uint32_t val = 0; + + /* Must be disabled */ + ASSERT_WARNING(!REG_GETF(CLKCAL_BIF, CLK_REF_SEL_REG, REF_CAL_START)); + + CLKCAL_BIF->CLK_REF_CNT_REG = cycles; // # of cal clock cycles + + if (clk_ref_type == CALIBRATE_REF_EXT) + { + REG_SET_FIELD(CLKCAL_BIF, CLK_REF_SEL_REG, EXT_CNT_EN_SEL, val, 1); + } + else + { + REG_SET_FIELD(CLKCAL_BIF, CLK_REF_SEL_REG, REF_CLK_SEL, val, clk_ref_type); + } + + REG_SET_FIELD(CLKCAL_BIF, CLK_REF_SEL_REG, CAL_CLK_SEL, val, clk_type); + + CLKCAL_BIF->CLK_REF_SEL_REG = val; + + REG_SET_BIT(CLKCAL_BIF, CLK_CAL_IRQ_REG, CLK_CAL_IRQ_EN); + + REG_SET_BIT(CLKCAL_BIF, CLK_REF_SEL_REG, REF_CAL_START); +} + +uint32_t hw_clk_get_calibration_data(void); + +uint32_t hw_clk_get_calibration_data (void) +{ + /* Wait until it's finished */ + while (REG_GETF(CLKCAL_BIF, CLK_REF_SEL_REG, REF_CAL_START)) + { + } + + return CLKCAL_BIF->CLK_REF_VAL_REG; +} + +#undef CLK_DELAY_SANITY_CHECKS +#pragma GCC push_options +#pragma GCC optimize ("O3") + +void hw_clk_delay_usec(uint32_t usec); + +void hw_clk_delay_usec (uint32_t usec) +{ + static const uint32_t DIVIDER = 1000000; + +#ifdef CLK_DELAY_SANITY_CHECKS + ASSERT_WARNING((dg_configXTAL40M_FREQ % DIVIDER) == 0); + ASSERT_WARNING((dg_configXTAL80M_FREQ % DIVIDER) == 0); + ASSERT_WARNING((dg_configPLL80M_FREQ % DIVIDER) == 0); + ASSERT_WARNING((HW_CLK_DELAY_OVERHEAD_CYCLES % HW_CLK_CYCLES_PER_DELAY_REP) == 0); +#endif + + static const uint8_t OVERHEAD_REPS = HW_CLK_DELAY_OVERHEAD_CYCLES / HW_CLK_CYCLES_PER_DELAY_REP; + static volatile uint32_t sys_freq_table[] = + { + 0, // SYS_CLK_IS_NONE + dg_configXTAL40M_FREQ / DIVIDER, // SYS_CLK_IS_XTAL40M + dg_configXTAL32K_FREQ / DIVIDER, // SYS_CLK_IS_LP + 0, // SYS_CLK_IS_PLL240M + 0, // SYS_CLK_IS_PLL192M + dg_configPLL160M_FREQ / DIVIDER, // SYS_CLK_IS_PLL160M + dg_configPLL137M_FREQ / DIVIDER, // SYS_CLK_IS_PLL137M + dg_configPLL106M_FREQ / DIVIDER, // SYS_CLK_IS_PLL106M + }; + + const uint32_t cycles_per_usec = sys_freq_table[hw_clk_get_sysclk()] >> hw_clk_get_hclk_div(), + reps = cycles_per_usec * usec / HW_CLK_CYCLES_PER_DELAY_REP; + +#ifdef CLK_DELAY_SANITY_CHECKS + ASSERT_WARNING(usec <= 0xFFFFFFFF / cycles_per_usec); // The requested delay is greater than the maximum delay this function can achieve + ASSERT_WARNING(reps > OVERHEAD_REPS); // The requested delay is smaller than the minimum delay this function can achieve. +#endif + + if (reps <= OVERHEAD_REPS) + { + return; + } + + __ASM volatile ( + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + "loop: nop \n" + " subs %[reps], %[reps], #1 \n" + " bne loop \n" + : // outputs + :[reps] "r" (reps - OVERHEAD_REPS) // inputs + : // clobbers + ); +} + +#pragma GCC pop_options +#if USE_FAST_STARTUP +static void xtal32m_readOTP (void) +{ + xtalm_otp_values.temp_refpt = 100; // reference point for temperature compensation + xtalm_otp_values.base_drive_cycles = 175; // base drive cycles at room xtal32m_temp_refpt +} + +#endif + +int16_t hw_clk_xtalm_update_rdy_cnt (void) +{ + int16_t xtalrdy_stat = 0; + + /* + * XXX On FPGA the value of XTALRDY_STAT_REG[XTALRDY_STAT] is always zero, so + * XXX there is no need to update XTALRDY_CTRL_REG[XTALRDY_CNT]. + */ +#if !DEVICE_FPGA + #if 0 + uint8_t xtalrdy_cnt = 0; + + // XXX review the following comments. normal vs fast mode + // XXX update IRQ time when in NORMAL startup mode: + // XXX (mis) use irq counter setting to do this + + if (REG_GETF(CRG_XTAL, XTALRDY_CTRL_REG, XTALRDY_CLK_SEL) == 0) + { + xtalrdy_cnt = REG_GETF(CRG_XTAL, XTALRDY_CTRL_REG, XTALRDY_CNT); + xtalrdy_stat = 3 - REG_GETF(CRG_XTAL, XTALRDY_STAT_REG, XTALRDY_STAT); + xtalrdy_cnt += xtalrdy_stat; + REG_SETF(CRG_XTAL, XTALRDY_CTRL_REG, XTALRDY_CNT, xtalrdy_cnt); + } + #endif +#endif + + return xtalrdy_stat; +} + +void hw_clk_xtalm_compensate_amp (void) +{ +#if USE_FAST_STARTUP + uint16_t T_drive, T_drive_lsb; + uint8_t N; + + // perform amplitude compensation + if (REG_GETF(CRG_XTAL, XTAL32M_CTRL0_REG, XTAL32M_RCOSC_XTAL_DRIVE) == 1) + { + uint16_t divisor = (0x8 << (0x7 - REG_GETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDRIVE))); + + T_drive = (xtalm_otp_values.base_drive_cycles * xtal32m_adcread()) / xtalm_otp_values.temp_refpt; + N = T_drive / divisor; + T_drive_lsb = T_drive - divisor * N; + + REG_SETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDRIVE_LSB, T_drive_lsb); + REG_SETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_DRIVE_CYCLES, N + 1); + } +#endif +} + +void hw_clk_xtalm_configure (void) +{ +#if 0 + #if USE_FAST_STARTUP + uint8_t settling_time; + uint8_t cxcomp_phi_trim; + + xtal32m_readOTP(); + + REG_SETF(CRG_XTAL, XTAL32M_CTRL0_REG, XTAL32M_CORE_CUR_SET, 3); // gmopt cur set. + + uint32_t reg = CRG_XTAL->XTAL32M_CTRL1_REG; + REG_SET_FIELD(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_RCOSC_SYNC_DELAY_TRIM, reg, 0); // synchronization delay trim + REG_SET_FIELD(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDISCHARGE, reg, 0); // discharge time in drive sequence + REG_SET_FIELD(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TSETTLE, reg, 5); // required settling time + settling_time = 6; + REG_SET_FIELD(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDRIVE, reg, settling_time); // unit drive length + CRG_XTAL->XTAL32M_CTRL1_REG = reg; + + REG_SETF(CRG_XTAL, XTAL32M_CTRL2_REG, XTAL32M_RCOSC_TRIM_SNS, 118); // sensitivity of rcosc + + // sets TSETTLE to half of TDRIVE + REG_SETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TSETTLE, settling_time); + + uint16_t T_drive, T_drive_lsb; + uint8_t N; + + uint16_t divisor = (0x8 << (0x7 - REG_GETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDRIVE))); + + // equate FASTBOOT drive-cycles + T_drive = xtalm_otp_values.base_drive_cycles; + N = T_drive / divisor; + T_drive_lsb = T_drive - divisor * N; + + REG_SETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_STARTUP_TDRIVE_LSB, T_drive_lsb); + REG_SETF(CRG_XTAL, XTAL32M_CTRL1_REG, XTAL32M_DRIVE_CYCLES, N + 1); + + // fast startup mode + REG_SETF(CRG_XTAL, TRIM_CTRL_REG, XTAL_TRIM_SELECT, 0x2); // always use direct trimming (disable legacy) + + // ~10us for ldo settling and 2 cycles for xtal voltage settling. IRQ handler also takes some time. + // hclk divider needs to be set to 0 + uint16_t xtalrdy_cnt = T_drive / 83 + 3 + 2; + + // Setup IRQ: + REG_SET_BIT(CRG_XTAL, XTALRDY_CTRL_REG, XTALRDY_CLK_SEL); // use 256kHz clock + REG_SETF(CRG_XTAL, XTALRDY_CTRL_REG, XTALRDY_CNT, xtalrdy_cnt); + REG_SET_BIT(CRG_XTAL, XTAL32M_CTRL0_REG, XTAL32M_RCOSC_CALIBRATE); + REG_CLR_BIT(CRG_XTAL, XTAL32M_CTRL0_REG, XTAL32M_CXCOMP_ENABLE); + #else + + // Configure OSF BOOST + uint8_t cxcomp_phi_trim = 0; + uint8_t cxcomp_trim_cap = REG_GETF(CRG_XTAL, XTAL32M_CTRL2_REG, XTAL32M_CXCOMP_TRIM_CAP); + + // set phi compensation + if (cxcomp_trim_cap < 37) + { + cxcomp_phi_trim = 3; + } + else + { + if (cxcomp_trim_cap < 123) + { + cxcomp_phi_trim = 2; + } + else + { + if (cxcomp_trim_cap < 170) + { + cxcomp_phi_trim = 1; + } + else + { + cxcomp_phi_trim = 0; + } + } + } + REG_SETF(CRG_XTAL, XTAL32M_CTRL2_REG, XTAL32M_CXCOMP_PHI_TRIM, cxcomp_phi_trim); + #endif +#endif +} + +/** + * \brief Enable the PLL. + */ +__RETAINED_CODE uint32_t hw_clk_pll_sys_on (void) +{ +#if DEVICE_FPGA + return 0; +#else + volatile uint32_t pllockcnt = 0, ldoisoff; + volatile uint32_t ldostabletime; + ahb_div_t bkup_ahbdiv, ahbdiv, scaler; + uint32_t bkup_rtcacctime; + + GLOBAL_INT_DISABLE(); + + // enable LDO for PLL + + /* 231024, NOTICE !!!!!!!!!! + * According to long-run testing, LDO settling time seems to be about 270~300 us. + * The NOP-loop (below while-loop) consists of 10 instructions. (approx. 12 cycles) */ + + // + // old condition: We managed to keep the time to 50us at least. + // 231024, test : unstable 50,55. stable 56(about 270 us),58,60,64 @ CPU 2.5MHz (XTAL 40MHz, AHB div 1/16) + // 231025, random test : + // long time, unstable 62(2.5>40). stable 64 + // short time, unstable 12(137>34). stable 16 + // 231026, pll management model has been updated for speed-up. + // 231027, (25<<4). long-run failed. changed to (30<<4) + // ahbdiv control scheme is fixed. + // 231030, HW_TIMER2 based time measurement was incorrect. changed to (640<<4, about 300 us) + + // backup ahbdiv & rtcacctime + bkup_ahbdiv = hw_clk_get_hclk_div(); + bkup_rtcacctime = RTC_POP_ACCESS_TIMING(); + + // forcing ahbdiv & rtcacctime + ahbdiv = ahb_div1; + + // We should access HCLK_DIV directly instead of calling hw_clk_set_hclk_div() + // to avoid the conflict with the nested call when using GLOBAL_INT_DISABLE. + // Trick to speed up RTC access. + HW_CLK_DEBUG_GPIO_HIGH(); + RTC_SET_ACCESS_TIMING(bkup_rtcacctime, 5, 7, 0); + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, ahbdiv); + HW_CLK_DEBUG_GPIO_LOW(); + + ldostabletime = (1 << 4); + for ( ; ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + switch (ahbdiv) + { + case ahb_div1: + { + scaler = 4; /*XTAL 40MHz*/ + break; + } + + case ahb_div2: + { + scaler = 3; /*XTAL 20MHz*/ + break; + } + + case ahb_div4: + { + scaler = 2; /*XTAL 10MHz*/ + break; + } + + case ahb_div8: + { + scaler = 1; /*XTAL 5MHz*/ + break; + } + + case ahb_div16: /*XTAL 2.5MHz*/ + default: + { + scaler = 0; + break; + } + } + + HW_CLK_DEBUG_GPIO_HIGH(); + if (REG_GETF(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1) == 0) + { + ldostabletime = (140 << 4); // when LDO is off for a long time. about 320 us + + REG_SET_BIT(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1); + ldoisoff = 1; + } + else + { + ldostabletime = 0; // when LDO and/or DPLL are turned on/off for a moment, + // or when LDO is turned on during waking up from deepsleep. + ldoisoff = 0; + } + + ldostabletime = ldostabletime >> (scaler); + for ( ; ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + HW_CLK_DEBUG_GPIO_LOW(); + + // set dpll1en & xtalen to activate PLL ( XTAL_GAIN(7) ) + // xtalen + REG_SET_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN); + + // xtal switch for DPLL + HW_CLK_DEBUG_GPIO_HIGH(); + if (REG_GETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_DPLL_EN) == 0) + { + ldostabletime = (0 << 4); // when XTAL40M_DPLL_EN is off for a long time. + + // 231101, these steps are changed to "gain control before DPLL.xtal_en" + // xtal gain + REG_SETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40_GAIN, 7); + + ldostabletime = ldostabletime >> (scaler); + for ( ; ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + // DPLL.xtal_en + REG_SET_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_DPLL_EN); + ldostabletime = (0 << 4); + } + else + { + ldostabletime = 0; // when XTAL40M_DPLL_EN is enabled, + } + + ldostabletime = ldostabletime >> (scaler); + for ( ; ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + HW_CLK_DEBUG_GPIO_LOW(); + + // disable PLL ( power-down ) + // first clear to make sure that the logic will be reseted + REG_CLR_BIT(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN); + + // wait until PLL is unlocked + pllockcnt = MAX_PLL_LCKCHK_TIME; /* x1 times */ + + HW_CLK_DEBUG_GPIO_HIGH(); + while (pllockcnt-- > 0) + { + if (REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK) == 0) + { + break; + } + } + + HW_CLK_DEBUG_GPIO_LOW(); + + // setup PLL to operate 480MHz + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_VCO_SEL, 0); + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_DIV_SEL, 24); + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_SHORT_S, 2); + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_LF_RCTRL, 0); + + // enable PLL ( power-up ) + REG_SET_BIT(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN); + + // wait until PLL is locked + pllockcnt = MAX_PLL_LCKCHK_TIME; /* x1 times */ + + HW_CLK_DEBUG_GPIO_HIGH(); + while (pllockcnt-- > 0) + { + if (REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK) != 0) + { + break; + } + } + + HW_CLK_DEBUG_GPIO_LOW(); + + // restore ahbdiv + HW_CLK_DEBUG_GPIO_HIGH(); + RTC_PUSH_ACCESS_TIMING(bkup_rtcacctime); + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, bkup_ahbdiv); + + ldostabletime = (1 << 4) >> (bkup_ahbdiv); + for ( ; ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + HW_CLK_DEBUG_GPIO_LOW(); + + GLOBAL_INT_RESTORE(); + + return (ldoisoff << 2) | ((MAX_PLL_LCKCHK_TIME - pllockcnt) << 3); +#endif +} + +/** + * \brief Disable the PLL. + * + * \warning The System clock must have been set to XTAL40M before calling this function! + */ +__RETAINED_CODE void hw_clk_pll_sys_off (void) +{ +#if DEVICE_FPGA +#else + volatile uint32_t pllockcnt = 0; + ahb_div_t bkup_ahbdiv, ahbdiv; + + GLOBAL_INT_DISABLE(); + + // backup ahbdiv + bkup_ahbdiv = hw_clk_get_hclk_div(); + + // forcing ahbdiv + ahbdiv = ahb_div1; + + // We should access HCLK_DIV directly instead of calling hw_clk_set_hclk_div() + // to avoid the conflict with the nested call when using GLOBAL_INT_DISABLE. + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, ahbdiv); + + // The PLL is not the system clk. + ASSERT_WARNING(!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL)); + + /* Turn off PLL. */ + REG_CLR_BIT(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN); + + // wait until PLL is unlocked + pllockcnt = MAX_PLL_LCKCHK_TIME; /* x1 times */ + while (pllockcnt-- > 0) + { + if (REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK) == 0) + { + break; + } + } + + /* LDO PLL disable. */ + REG_CLR_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_DPLL_EN); + + for (uint32_t ldostabletime = (1 << 4); ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + /* disable LDO for PLL */ + REG_CLR_BIT(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1); + + for (uint32_t ldostabletime = (1 << 4); ldostabletime > 0; ldostabletime--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + // restore ahbdiv + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, bkup_ahbdiv); + + GLOBAL_INT_RESTORE(); +#endif +} + +__RETAINED_CODE void pll_on (void) +{ +#if DEVICE_FPGA +#else + int i; + volatile uint32_t delay; + + /* Now turn on PLL */ + REG_SETF(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1, 1); // enable LDO for PLL + + /* it need 50us at least */ + for (delay = 50; delay > 0; delay--) + { + __asm__ volatile ( "nop"); + __asm__ volatile ( "nop"); + __asm__ volatile ( "nop"); + __asm__ volatile ( "nop"); + } + + REG_SETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_DPLL_EN, 1); // enable xtal path to DPLL + + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN, 0); // first clear to make sure that the logic will be reseted + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN, 1); + + /* And wait until lock. */ + while (REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK) == 0) + { + } + + REG_SETF(CRG_TOP, CLK_AMBA_REG, OQSPIF_DIV, 1); // oqspi divide first 40Mhz + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL, 2); // 160Mhz + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, 0); // AMBA 160Mhz + // REG_SETF(CRG_PER, CLK_COM_REG, UART_ENABLE, 0); // uart source 40Mhz + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_PERI_ENABLE, 1); // peri pll clock + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CPU_ENABLE, 1); + +/* + * REG_SETF(OQSPIF,OQSPIF_CTRLMODE_REG, OSPIC_PCLK_MD, 7); + * REG_SETF(OQSPIF,OQSPIF_CTRLMODE_REG, OSPIC_RPIPE_EN, 1); + */ + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, 3); + + for (i = 32; i > 0; i--) + { + __ASM volatile ("nop"); + __ASM volatile ("nop"); + } + + /* update UART clock */ +#endif +} + +__RETAINED_CODE void pll_off (void) +{ +#if DEVICE_FPGA +#else + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, 1); // XTAL + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CPU_ENABLE, 0); + REG_SETF(CRG_TOP, CLK_AMBA_REG, OQSPIF_DIV, 1); // oqspi divide first 80Mhz + + /* Now turn off PLL */ + REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN, 0); // first clear to make sure that the logic will be reseted + REG_SETF(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1, 0); // enable LDO for PLL + + REG_SETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_DPLL_EN, 0); // enable xtal path to DPLL +#endif +} + +/*******************************************************************************************************************//** + * Enable mirror for acessing RTC register. + * + * @note The RTC block uses a 32khz clock. + * Because of this, bus access also uses 32khz. + * Using a mirror, you can access the RTC register using the CPU's clock. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void bsp_prv_rtc_mirror_init (void) +{ + RTC->RTC_REQ_REG_b.RTC_REQ_CLR_IRQ = 1; + + if (RTC->RTC_REQ_REG_b.RTC_REQ_LOAD_MR == 0) + { + RTC->RTC_MIRROR_REG_b.RTC_OP_EN = 1; + RTC->RTC_MIRROR_REG_b.RTC_MR_EN = 1; + + RTC->RTC_REQ_REG_b.RTC_REQ_LOAD_MR = 1; + + /* Wait to done process */ + while ((RTC->RTC_IRQ_STATUS_REG_b.RTC_IRQ_STATUS) != 0x01) + { + ; + } + } +} + +/*******************************************************************************************************************//** + * Gets the current low power clock source selection. + * + * @return The current low power clock source type. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM lp_clk_is_t bsp_prv_lpclk_get () +{ + uint32_t sel, current_sel; + + sel = RTC->CLK_XTAL32K_REG_b.XTAL_CLK_SEL; + + if (sel == 0x00) + { + current_sel = LP_CLK_IS_RCX; + } + else if (sel == 0x01) + { + current_sel = LP_CLK_IS_XTAL32K; + } + else + { + current_sel = LP_CLK_IS_INVALID; + } + + return current_sel; +} + +/*******************************************************************************************************************//** + * @brief Selects the low power clock source. + * + * This function selects the low power clock source based on the input type. + * It checks the current clock selection and updates it if available. + * + * @param[in] type The desired low power clock source type. + * + * @return The selected low power clock source type. + * + * @note The lp clock has internal rcx and external xtal32k. + * It usually takes about 1 second after POR for XTAL_RDY_BAT_RD_STATUS to become 1. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t bsp_prv_lpclk_select (lp_clk_is_t type) +{ + fsp_err_t result = FSP_SUCCESS; + + if (bsp_prv_lpclk_get() == type) + { + /* If sel is same to type, it's return */ + return result; + } + + switch (type) + { + case LP_CLK_IS_RCX: + { + RTC->CLK_XTAL32K_REG_b.XTAL_CLK_SEL = 0; + RTC->CLK_XTAL32K_REG_b.XTAL_BAT_EN = 0; + break; + } + + case LP_CLK_IS_XTAL32K: + { +#if (BSP_CLOCK_CFG_SUBCLOCK_POPULATED == 1) + if (RTC->READ_STATUS_REG_b.XTAL_RDY_BAT_RD_STATUS) + { + RTC->CLK_XTAL32K_REG_b.XTAL_CLK_SEL = 1; + + /* For decrease current consumption, it's off OSC */ + RTC->RCX32K_REG = 0; + RTC->CLK_XTAL32K_REG_b.PDB_OSC_EN = 0; + } + else +#endif + { + result = FSP_ERR_NOT_STABILIZED; + } + + break; + } + + default: + { + break; + } + } + + return result; +} + +#endif /* DEVICE_FAMILY */ + +/** + \} + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.h new file mode 100644 index 000000000000..69a5fb92382d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_clocks.h @@ -0,0 +1,1146 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCKS_RA6W1_H +#define BSP_CLOCKS_RA6W1_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "../all/bsp_delay.h" +#include "../all/bsp_mcu_api.h" +#include "../all/bsp_clocks.h" + +/* TODO get rid of the following legacy definitions from sdk_defs.h: */ +#define REG_GETF(base, reg, field) \ + (((base->reg) & (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) + +#define REG_SETF(base, reg, field, new_val) \ + base->reg = ((base->reg & ~(base ## _ ## reg ## _ ## field ## _Msk)) | \ + ((base ## _ ## reg ## _ ## field ## _Msk) &((new_val) << (base ## _ ## reg ## _ ## field ## _Pos)))) + +#define GLOBAL_INT_DISABLE() \ + do { \ + unsigned int __l_irq_rest; \ + __ASM volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (__l_irq_rest) \ + : \ + : "r1" \ + ); \ + /*DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION);*/ + +#define GLOBAL_INT_RESTORE() \ + if (__l_irq_rest == 0) { \ + /*DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION);*/ \ + } \ + __ASM volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (__l_irq_rest) \ + : \ + ); \ +} \ + while (0) + +#define REG_SET_BIT(base, reg, field) \ + do { \ + base->reg |= (1 << (base ## _ ## reg ## _ ## field ## _Pos)); \ + } while (0) + +#define REG_CLR_BIT(base, reg, field) \ + do { \ + base->reg &= ~(base ## _ ## reg ## _ ## field ## _Msk); \ + } while (0) + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define HW_CLK_DELAY_OVERHEAD_CYCLES (72) +#define HW_CLK_CYCLES_PER_DELAY_REP (4) + +#define MAX_PLL_LCKCHK_TIME (0x00007FFF) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * \brief The type of the LP clock + */ +typedef enum lp_clk_is_type +{ + LP_CLK_IS_RCX, // 32K internal RC oscillator + LP_CLK_IS_XTAL32K, // 32K Crystal oscillator + LP_CLK_IS_SWCLK, // Test_clk + LP_CLK_IS_INVALID +} lp_clk_is_t; + +/** + * \} + */ + +/** + * \brief The AMBA High-Performance Bus (AHB) clock divider + */ +typedef enum ahbdiv_type +{ + ahb_div1 = 0, //!< Divide by 1 + ahb_div2, //!< Divide by 2 + ahb_div4, //!< Divide by 4 + ahb_div8, //!< Divide by 8 + ahb_div16, //!< Divide by 16 +} ahb_div_t; + +/** + * \brief The AMBA Peripheral Bus (APB) clock divider + */ +typedef enum apbdiv_type +{ + apb_div1 = 0, //!< Divide by 1 + apb_div2, //!< Divide by 2 + apb_div4, //!< Divide by 4 + apb_div8, //!< Divide by 8 + apb_div16, //!< Divide by 16 +} apb_div_t; + +/** + * \brief Get the divider of the AMBA High Speed Bus. + * + * \return The AMBA High Speed Bus divider + */ +__STATIC_FORCEINLINE ahb_div_t hw_clk_get_hclk_div (void) +{ + return (ahb_div_t) REG_GETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV); +} + +/** + * \brief Set the divider of the AMBA High Speed Bus. + * + * \param div The AMBA High Speed Bus divider + */ +__STATIC_FORCEINLINE void hw_clk_set_hclk_div (ahb_div_t div) +{ + BSP_CHECK_DEBUG(div <= ahb_div16); + + GLOBAL_INT_DISABLE(); + REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, div); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief The type of the system clock + */ +typedef enum sys_clk_is_type +{ + SYS_CLK_IS_NONE = 0, /* RUNNING_AT_LP_CLK */ + SYS_CLK_IS_XTAL40M, /* RUNNING_AT_XTAL40M */ + SYS_CLK_IS_LP, + SYS_CLK_IS_PLL240M, /* RUNNING_AT_PLL240M : descoped */ + SYS_CLK_IS_PLL192M, /* RUNNING_AT_PLL192M : descoped */ + SYS_CLK_IS_PLL160M, /* RUNNING_AT_PLL160M */ + SYS_CLK_IS_PLL137M, /* SYS_CLK_IS_PLL137M */ + SYS_CLK_IS_PLL106M, /* SYS_CLK_IS_PLL106M */ + SYS_CLK_IS_INVALID +} sys_clk_is_t; + +/** + * \} + */ + +/** + * \brief The type of clock to be calibrated + */ +typedef enum cal_clk_sel_type +{ + CALIBRATE_XTAL32K = 0, + CALIBRATE_RCX32K, + CALIBRATE_DIVN_CLK, +} cal_clk_t; + +/** + * \brief The reference clock used for calibration + */ +typedef enum cal_ref_clk_sel_type +{ + CALIBRATE_REF_XTAL32K = 0, + CALIBRATE_REF_RCX32K, + CALIBRATE_REF_DIVN_CLK, + CALIBRATE_REF_EXT, +} cal_ref_clk_t; + +/** + * \brief The system clock type + * + * \note Must only be used with functions cm_sys_clk_init/set() + */ +typedef enum sysclk_type +{ + sysclk_RC32 = 0, //!< RC32 + sysclk_XTAL40M = 2, //!< 40MHz + sysclk_PLL480 = 6, //!< 480MHz + sysclk_LP = 255, //!< not applicable +} sys_clk_t; + +/** + * \brief The CPU clock type (speed) + * + */ +typedef enum cpu_clk_type +{ + cpuclk_2M = 2, //!< 2.5 MHz, divided by 16 in XTAL + cpuclk_5M = 5, //!< 5 MHz, divided by 8 in XTAL + cpuclk_10M = 10, //!< 10 MHz, divided by 4 in XTAL + cpuclk_20M = 20, //!< 20 MHz, divided by 2 in XTAL + + cpuclk_26M = 26, //!< 26 MHz, divided by 4 in SYSCLK 106MHz + cpuclk_34M = 34, //!< 34 MHz, divided by 4 in SYSCLK 137MHz + cpuclk_40M = 40, //!< 40 MHz, divided by 4 in SYSCLK 160MHz + + cpuclk_53M = 53, //!< 53 MHz, divided by 2 in SYSCLK 106MHz + cpuclk_68M = 68, //!< 68 MHz, divided by 2 in SYSCLK 137MHz + cpuclk_80M = 80, //!< 80 MHz, divided by 2 in SYSCLK 160MHz + + cpuclk_106M = 106, //!< 106 MHz + cpuclk_137M = 137, //!< 137 MHz + cpuclk_160M = 160 //!< 160 MHz +} cpu_clk_t; + +/** + * \brief The type of the fpll clock + */ +typedef enum fpll_clock_type +{ + FPLL_98M = 0, + FPLL_90M = 1, + DIVN_40M = 2, +} fpll_clk_t; + +/** + * \brief The type of the fpll mode + */ +typedef enum fpll_clock_mode +{ + FPLL_MODE_USE_IRM = 0, + FPLL_MODE_NO_IRM = 1 +} fpll_mode_t; + +/** + * \brief Get the XTAL32M settling time. + * + * \return The number of 256KHz clock cycles required for XTAL40M to settle + */ +__STATIC_FORCEINLINE uint16_t hw_clk_get_xtalm_settling_time (void) +{ + /* TODO for DA1640x */ + return 0; +} + +/** + * \brief Check if the XTAL40M is enabled. + * + * \return true if the XTAL40M is enabled, else false. + */ +__STATIC_INLINE bool hw_clk_check_xtal40m_status (void) +{ + /* TODO for DA1640x */ + return true; +} + +/** + * \brief Activate the XTAL40M. + */ +__STATIC_INLINE void hw_clk_enable_xtal40m (void) +{ + /* Do nothing if XTAL40M is already up and running. */ + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL40M)) + { + return; + } + + // Check if TIM power domain is enabled +#if DEVICE_FPGA +#else + BSP_CHECK_DEBUG(REG_GETF(CRG_TOP, SYS_STATUS_REG, SYS_IS_UP)); +#endif + +#if DEVICE_FPGA + REG_SET_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN); +#else + REG_SET_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN); + +// Delay + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + BSP_CHECK_DEBUG(REG_GETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_RDY)); +#endif +} + +/** + * \brief Deactivate the XTAL40M. + */ +__STATIC_INLINE void hw_clk_disable_xtal40m (void) +{ + REG_CLR_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN); +} + +/** + * \brief Check if the XTAL40M has settled. + * + * \return true if the XTAL40M has settled, else false. + */ +__STATIC_INLINE bool hw_clk_is_xtalm_started (void) +{ + return true; +} + +/** + * \brief Return the clock used as the system clock. + * + * \return The type of the system clock + */ +__STATIC_FORCEINLINE sys_clk_is_t hw_clk_get_sysclk (void) +{ + sys_clk_is_t clk = SYS_CLK_IS_NONE; + + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL40M)) + { + clk = SYS_CLK_IS_XTAL40M; + } + else if (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)) + { + clk = SYS_CLK_IS_LP; + } + else if (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL)) + { + uint8_t mode = REG_GETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL); + clk = (sys_clk_is_t) (SYS_CLK_IS_PLL240M + mode); + } + + BSP_CHECK_DEBUG(clk < SYS_CLK_IS_INVALID); + + return clk; +} + +/** + * \brief Check whether the XTAL32K is the Low Power clock. + * + * \return true if XTAL32K is the LP clock, else false. + */ +__STATIC_INLINE bool hw_clk_lp_is_xtal32k (void) +{ + if (REG_GETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL) == LP_CLK_IS_XTAL32K) + { + return true; + } + + return false; +} + +/** + * \brief Set RCX as the Low Power clock. + * + * \warning The RCX must have been enabled before calling this function! + * + * \note Call with interrupts disabled to ensure that CLK_CTRL_REG + * read/modify/write operation is not interrupted + */ +__STATIC_INLINE void hw_clk_lp_set_rcx (void) +{ +#if DEVICE_FPGA +#else + BSP_CHECK_DEBUG(__get_PRIMASK() == 1 || __get_BASEPRI()); + BSP_CHECK_DEBUG(REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)); + + REG_SET_BIT(RTC, CLK_XTAL32K_REG, PDB_OSC_EN); + REG_SETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL, LP_CLK_IS_RCX); +#endif +} + +/** + * \brief Set XTAL32K as the Low Power clock. + * + * \warning The XTAL32K must have been enabled before calling this function! + * + * \note Call with interrupts disabled to ensure that CLK_CTRL_REG + * read/modify/write operation is not interrupted + */ +__STATIC_INLINE void hw_clk_lp_set_xtal32k (void) +{ + BSP_CHECK_DEBUG(__get_PRIMASK() == 1 || __get_BASEPRI()); +#if DEVICE_FPGA +#else + BSP_CHECK_DEBUG(REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)); +#endif + REG_SET_BIT(RTC, CLK_XTAL32K_REG, XTAL_BAT_EN); + REG_SETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL, LP_CLK_IS_XTAL32K); +} + +/** + * \brief Set an external SWCLK as the Low Power clock. + * + * \note Call with interrupts disabled to ensure that CLK_CTRL_REG + * read/modify/write operation is not interrupted + */ +__STATIC_INLINE void hw_clk_lp_set_swclk (void) +{ + BSP_CHECK_DEBUG(__get_PRIMASK() == 1 || __get_BASEPRI()); +#if DEVICE_FPGA +#else + BSP_CHECK_DEBUG(REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)); +#endif + REG_SETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL, LP_CLK_IS_SWCLK); +} + +/** + * \brief Enable RCX but does not set it as the LP clock. + */ +__STATIC_INLINE void hw_clk_enable_rcx (void) +{ + REG_SET_BIT(RTC, CLK_XTAL32K_REG, PDB_OSC_EN); +} + +/** + * \brief Disable RCX. + * + * \warning RCX must not be the LP clock + */ +__STATIC_INLINE void hw_clk_disable_rcx (void) +{ + if (REG_GETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL) != LP_CLK_IS_RCX) + { + REG_CLR_BIT(RTC, CLK_XTAL32K_REG, PDB_OSC_EN); + } +} + +/** + * \brief Enable XTAL32K but do not set it as the LP clock. + */ +__STATIC_INLINE void hw_clk_enable_xtal32k (void) +{ + REG_SET_BIT(RTC, CLK_XTAL32K_REG, XTAL_BAT_EN); +} + +/** + * \brief Enable XTAL32K from XTAL40MHz but do not set it as the LP clock. + */ +__STATIC_INLINE void hw_clk_enable_external (void) +{ +} + +/** + * \brief Disable XTAL32K. + * + * \warning XTAL32K must not be the LP clock. + */ +__STATIC_INLINE void hw_clk_disable_xtal32k (void) +{ + if (REG_GETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL) != LP_CLK_IS_XTAL32K) + { + REG_CLR_BIT(RTC, CLK_XTAL32K_REG, XTAL_BAT_EN); + } +} + +/** + * \brief Disable XTAL32K from XTAL40M. + * + * \warning XTAL32K must not be the LP clock. + */ +__STATIC_INLINE void hw_clk_disable_external (void) +{ + BSP_CHECK_DEBUG(REG_GETF(RTC, CLK_XTAL32K_REG, XTAL_CLK_SEL) == LP_CLK_IS_XTAL32K); + + REG_CLR_BIT(RTC, CLK_XTAL32K_REG, XTAL_BAT_EN); +} + +/** + * \brief Set System clock. + * + * \param[in] mode The new system clock. + * + * \note System clock switch to PLL is only allowed when current system clock is XTAL40M. + * System clock switch from PLL is only allowed when new system clock is XTAL40M. + */ +__STATIC_FORCEINLINE void hw_clk_set_sysclk (sys_clk_is_t mode) +{ + /* Make sure a valid sys clock is requested */ + BSP_CHECK_DEBUG(mode <= SYS_CLK_IS_PLL106M); +#if (0) + + /* Switch to PLL is only allowed when current system clock is XTAL32M */ + BSP_CHECK_DEBUG(mode != SYS_CLK_IS_PLL || + REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL32M) || + REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M)) + + /* Switch to PLL is only allowed when HDIV and PDIV are 0 */ + BSP_CHECK_DEBUG(mode != SYS_CLK_IS_PLL || (hw_clk_get_hclk_div() == ahb_div1 && hw_clk_get_pclk_div() == apb_div1)); + + /* Switch from PLL is only allowed when new system clock is XTAL32M */ + BSP_CHECK_DEBUG(!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M) || + mode == SYS_CLK_IS_XTAL40M || + mode == SYS_CLK_IS_PLL); +#endif + GLOBAL_INT_DISABLE(); + if (mode < SYS_CLK_IS_PLL240M) + { + // sys_clk_is_t clk = hw_clk_get_sysclk(); + if (mode == SYS_CLK_IS_XTAL40M) + { + REG_SET_BIT(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN); + } + else if (mode == SYS_CLK_IS_LP) + { + REG_SET_BIT(CRG_COM, XTAL32K_CTRL_REG, XTAL32K_ENABLE); + BSP_CHECK_DEBUG(0); + } + + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, mode); + } + else + { + sys_clk_is_t clk = hw_clk_get_sysclk(); + + if ((clk != SYS_CLK_IS_XTAL40M) && (clk != SYS_CLK_IS_LP)) + { + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, SYS_CLK_IS_XTAL40M); // XTAL + while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL)) + { + } + } + + /* PLL_CLK_SEL, + * 0: set to SYS_CLK=240Mhz + * 1: set to SYS_CLK=192Mhz + * 2: set to SYS_CLK=160Mhz + * 3: set to SYS_CLK=137.14Mhz + * 4: set to SYS_CLK=106Mhz + */ + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL, (unsigned) (mode - SYS_CLK_IS_PLL240M)); + + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CPU_ENABLE, 1); + + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, 3); // PLL + } + + GLOBAL_INT_RESTORE(); + + /* Wait until the switch is done! */ + switch (mode) + { + case SYS_CLK_IS_XTAL40M: + { + while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL40M)) + { + } + + return; + } + + case SYS_CLK_IS_LP: + { + while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_LP_CLK)) + { + } + + return; + } + + case SYS_CLK_IS_PLL160M: + case SYS_CLK_IS_PLL137M: + case SYS_CLK_IS_PLL106M: + { + while (!REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL)) + { + } + + return; + } + + default: + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Enable the PLL. + */ +uint32_t hw_clk_pll_sys_on(void); + +/** + * \brief Disable the PLL. + * + * \warning The System clock must have been set to XTAL40M before calling this function! + */ +void hw_clk_pll_sys_off(void); + +/** + * \brief Check if the PLL is enabled. + * + * \return true if the PLL is enabled, else false. + */ +__STATIC_FORCEINLINE bool hw_clk_check_pll_status (void) +{ +#if DEVICE_FPGA + return REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN); +#else + return REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN); +#endif +} + +/** + * \brief Check if the PLL is on and has locked. + * + * \return true if the PLL has locked, else false. + */ +__STATIC_FORCEINLINE bool hw_clk_is_pll_locked (void) +{ +#if DEVICE_FPGA + return REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK); +#else + return REG_GETF(CRG_COM, PLL1_ARM_CTRL_REG, PLL_LOCK); +#endif +} + +/** + * \brief Activate a System clock. + * + * \param[in] clk The clock to activate. + */ +__STATIC_FORCEINLINE void hw_clk_enable_sysclk (sys_clk_is_t clk) +{ + switch (clk) + { + case SYS_CLK_IS_LP: + { + if (hw_clk_lp_is_xtal32k() == false) + { + hw_clk_enable_xtal32k(); + } + + break; + } + + case SYS_CLK_IS_XTAL40M: + { + // REG_SETF(CRG_DIGPLL, PLL320M_CFG1_REG, ENABLE_PLL320M, 0); + hw_clk_enable_xtal40m(); + + // REG_SETF(CRG_TOP,CLK_CTRL_REG, DIVC_CLK_SEL, 0); // 0: div1, 1: div2 + break; + } + + case SYS_CLK_IS_PLL160M: + { + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL, 2); + break; + } + + case SYS_CLK_IS_PLL137M: + { + // REG_SETF(CRG_DIGPLL, PLL320M_CFG1_REG, ENABLE_PLL320M, 1); + // while(REG_GETF(CRG_DIGPLL, PLL320M_STATUS_REG,PLL320M_PLL_OK)==0); + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL, 3); + break; + } + + case SYS_CLK_IS_PLL106M: + { + // REG_SETF(CRG_DIGPLL, PLL320M_CFG1_REG, ENABLE_PLL320M, 1); + // while(REG_GETF(CRG_DIGPLL, PLL320M_STATUS_REG,PLL320M_PLL_OK)==0); + REG_SETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL, 4); + break; + } + + default: + + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Deactivate a System clock. + * + * \param[in] clk The clock to deactivate. + */ +__STATIC_FORCEINLINE void hw_clk_disable_sysclk (sys_clk_is_t clk) +{ + switch (clk) + { + case SYS_CLK_IS_XTAL40M: + { + hw_clk_disable_xtal40m(); + + return; + } + + case SYS_CLK_IS_LP: + { + hw_clk_disable_rcx(); + + return; + } + + case SYS_CLK_IS_PLL160M: + { + // TODO: + return; + } + + case SYS_CLK_IS_PLL137M: + { + // TODO: + return; + } + + case SYS_CLK_IS_PLL106M: + { + // TODO: + return; + } + + default: + + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Check if a System clock is enabled. + * + * \return true if the System clock is enabled, else false. + */ +__STATIC_INLINE bool hw_clk_is_enabled_sysclk (sys_clk_is_t clk) +{ + switch (clk) + { + case SYS_CLK_IS_XTAL40M: + { + return hw_clk_check_xtal40m_status(); + } + + case SYS_CLK_IS_PLL160M: + { + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL) == 2) + { + return true; + } + + break; + } + + case SYS_CLK_IS_PLL137M: + { + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL) == 3) + { + return true; + } + + break; + } + + case SYS_CLK_IS_PLL106M: + { + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, PLL_CLK_SEL) == 4) + { + return true; + } + + break; + } + + default: + { + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + break; + } + } + + return false; +} + +/** + * \brief Configure pin to connect an external digital clock. + */ +__STATIC_INLINE void hw_clk_configure_ext32k_pins (void) +{ +#if DEVICE_FPGA +#else + + // GPIO-> P0_23_MODE_REG = 0; +#endif +} + +/** + * \brief Activate a FPLL clock. + * + * \param[in] freq_type The clock to activate. + * \param[in] fpll_mode The clock to activate. + */ +__STATIC_INLINE void hw_clk_enable_fpll (fpll_clk_t freq_type, fpll_mode_t fpll_mode) +{ +#if DEVICE_FPGA +#else + REG_SETF(RTC, LDO_ENABLE_REG, LDO_EN_LDO_PLL1, 1); + REG_SETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_EN, 1); + +// REG_SETF(CRG_COM, PLL1_ARM_CTRL_REG, DPLL1_EN, 1); + REG_SETF(CRG_COM, XTAL40M_CTRL_REG, XTAL40M_FPLL_EN, 1); + if (freq_type == DIVN_40M) + { + REG_SETF(FPLL, PLLD_CTRL_REG, FPLL_EN, 1); + REG_SETF(FPLL, PLLD_CTRL_REG, BYPASS_SEL, 1); + + REG_SETF(FPLL, PLLD_CTRL_REG, PFD_CP_EN, 0); + REG_SETF(FPLL, PLLD_CTRL_REG, CLKOUT_EN, 0); + REG_SETF(FPLL, PLLD_CTRL_REG, VCO_EN, 0); + } + else if ((freq_type == FPLL_98M) || (freq_type == FPLL_90M)) + { + #if 1 + + // REG_SETF(FPLL, PLLD_CTRL_REG, FBDIV_SEL,fpll_mode); + REG_SETF(FPLL, PLLD_IRQ_MASK_REG, MIRQ_PLL_LOCK, 1); + REG_SETF(FPLL, PLLD_IRQ_MASK_REG, MIRQ_PLL_LOST_LOCK, 1); + + REG_SETF(FPLL, PLLD_CONFIG_REG, INDIV, 5); + REG_SETF(FPLL, PLLD_CONFIG_REG, OUTDIV, 3); + REG_SETF(FPLL, PLLD_CONFIG_REG, BIAS_HOLD, 0); + if (fpll_mode == FPLL_MODE_NO_IRM) + { + if (freq_type == FPLL_98M) + { + // DIV = 98.304*2 / 5 (freq after input divider)=39.3216, INT = int(DIV) = 39 (0x27), FRAC = (DIV-INT)*2^13 = 2634 (0x0A4A) + REG_SETF(FPLL, PLLD_FBDIV_REG, FBDIV, (0x27 << 13) | (0xA << 8) | (0x4A)); + } + else if (freq_type == FPLL_90M) + { + // DIV = 36.12672, INT = 36 (0x24), FRAC = 1038 (0x040E) + REG_SETF(FPLL, PLLD_FBDIV_REG, FBDIV, (0x24 << 13) | (0x4 << 8) | (0x0E)); + } + } + + REG_SETF(FPLL, PLLD_CTRL_REG, BYPASS_SEL, 1); + REG_SETF(FPLL, PLLD_CTRL_REG, VCO_EN, 1); + REG_SETF(FPLL, PLLD_CTRL_REG, FPLL_EN, 1); + REG_SETF(FPLL, PLLD_CTRL_REG, PFD_CP_EN, 1); + REG_SETF(FPLL, PLLD_CTRL_REG, CLKOUT_EN, 1); + + // Wait 5us +// for(i=0; i<50; i++) {;} +// REG_SETF(FPLL, PLLD_CONFIG_REG, BIAS_HOLD, 1); + + // Wait for flag_lock to go HIGH + while (REG_GETF(FPLL, PLLD_STATUS_REG, STA_PLL_LOCK) == 0) + { + ; + } + + REG_SETF(FPLL, PLLD_CTRL_REG, CLKOUT_EN, 1); + +// jason230810 REG_SETF(FPLL, PLLD_CTRL_REG, BYPASS_SEL, 0); + #else + +// LDO_ENABLE_REG.LDO_EN_LDO_PLL1 = 1 // DPLL & FPLL LDO EN +// XTAL40M_CTRL_REG.XTAL40M_EN = 1 // xtal 40M +// XTAL40M_CTRL_REG.XTAL40M_FPLL_EN =1 // xtal 40M (FPLL path) +// GPIO_CLK_SEL_REG.FPLL98M_OUTPUT_EN =1 // Pad dedicated setting +// PLLD_FBDIV_REG.FBDIV = 0x4EA0E // 39.3142 +// PLLD_CTRL_REG = 0x3E // FPLL EN +// PLLD_CONFIG_REG.OUTDIV = 1 // vco/2 + + if (fpll_mode == FPLL_MODE_NO_IRM) + { + if (freq_type == FPLL_98M) + { + REG_SETF(FPLL, PLLD_FBDIV_REG, FBDIV, 0x4ea4a); + } + else if (freq_type == FPLL_90M) + { + REG_SETF(FPLL, PLLD_FBDIV_REG, FBDIV, 0x4840e); + } + } + + FPLL->PLLD_CTRL_REG = 0x3e; + REG_SETF(FPLL, PLLD_CONFIG_REG, OUTDIV, 3); + while (REG_GETF(FPLL, PLLD_STATUS_REG, STA_PLL_LOCK) == 0) + { + ; + } + #endif + } + return; +#endif +} + +/** + * \brief Deactivate a System clock. + * + * \param[in] clk The clock to deactivate. + */ +__STATIC_INLINE void hw_clk_disable_fpll (sys_clk_is_t clk) +{ + switch (clk) + { + case SYS_CLK_IS_XTAL40M: + { + hw_clk_disable_xtal40m(); + + return; + } + + default: + + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Configure XTAL40M. + */ +void hw_clk_xtalm_configure(void); + +/** + * \brief Perform XTAL40M RCOSC amplitude temperature compensation. + */ +void hw_clk_xtalm_compensate_amp(void); + +/** + * \brief Update XTAL40M Ready IRQ counter. + * + * \return The difference between the new and the old XTAL40M Ready IRQ counter + * in cycles of 32KHz clocks. + */ +int16_t hw_clk_xtalm_update_rdy_cnt(void); + +/** + * \brief Enable PLL + * + * \details + */ +void pll_on(void); + +/** + * \brief Disable PLL + * + * \details + */ +void pll_off(void); + +/** + * \brief Set Low Power clock. + * + * \param[in] mode The new low power clock. + */ +__STATIC_INLINE void hw_clk_set_lpclk (lp_clk_is_t mode) +{ + GLOBAL_INT_DISABLE(); + switch (mode) + { + case LP_CLK_IS_RCX: + { + hw_clk_lp_set_rcx(); + break; + } + + case LP_CLK_IS_SWCLK: + { + hw_clk_lp_set_swclk(); + break; + } + + case LP_CLK_IS_XTAL32K: + { + hw_clk_lp_set_xtal32k(); + break; + } + + default: + { + BSP_CHECK_DEBUG(0); + break; + } + } + + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Activate a Low Power clock. + * + * \param[in] clk The clock to activate. + */ +__STATIC_INLINE void hw_clk_enable_lpclk (lp_clk_is_t clk) +{ + switch (clk) + { + case LP_CLK_IS_RCX: + { + hw_clk_enable_rcx(); + + return; + } + + case LP_CLK_IS_XTAL32K: + { + hw_clk_enable_xtal32k(); + + return; + } + + case LP_CLK_IS_SWCLK: + { + // Nothing to do for SWCLK LP clock + return; + } + + default: + + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Deactivate a Low Power clock. + * + * \param[in] clk The clock to deactivate. + */ +__STATIC_INLINE void hw_clk_disable_lpclk (lp_clk_is_t clk) +{ + switch (clk) + { + case LP_CLK_IS_RCX: + { + hw_clk_disable_rcx(); + + return; + } + + case LP_CLK_IS_XTAL32K: + { + hw_clk_disable_xtal32k(); + + return; + } + + case LP_CLK_IS_SWCLK: + { + // Nothing to do for SWCLK LP clock + return; + } + + default: + + /* An invalid clock is requested */ + BSP_CHECK_DEBUG(0); + } +} + +/** + * \brief Enable clock for specific UART channel + * + * \param[in] channel UART channel to activate clock + */ +__STATIC_INLINE void hw_clk_enable_uart_w_clk (uint8_t channel) +{ + CRG_TOP->CLK_AMBA_REG_b.PERI_CLK_ENABLE = 1; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case 0: + { + CRG_PER->CLK_COM_REG_b.UART_ENABLE = 1; + break; + } + + case 1: + { + CRG_PER->CLK_COM_REG_b.UART2_ENABLE = 1; + break; + } + + case 2: + { + CRG_PER->CLK_COM_REG_b.UART3_ENABLE = 1; + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; +} + +/** + * \brief Disable clock for specific UART channel + * + * \param[in] channel UART channel to deactivate clock + */ +__STATIC_INLINE void hw_clk_disable_uart_w_clk (uint8_t channel) +{ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case 0: + { + CRG_PER->CLK_COM_REG_b.UART_ENABLE = 0; + break; + } + + case 1: + { + CRG_PER->CLK_COM_REG_b.UART2_ENABLE = 0; + break; + } + + case 2: + { + CRG_PER->CLK_COM_REG_b.UART3_ENABLE = 0; + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * @brief Enable the low-power crystal oscillator. + * + * This function enables the low-power 32kHz crystal oscillator by setting the XTAL_BAT_EN bit in the RTC register. + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_prv_lpclk_xtal_on () +{ + RTC->CLK_XTAL32K_REG_b.XTAL_BAT_EN = 1; +} + +/*******************************************************************************************************************//** + * @brief Enable the low-power oscillator. + * + * This function enables the low-power internal RC oscillator by setting the PDB_OSC_EN bit in the RTC register. + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_prv_lpclk_osc_on () +{ + RTC->CLK_XTAL32K_REG_b.PDB_OSC_EN = 1; +} + +lp_clk_is_t bsp_prv_lpclk_get(); +fsp_err_t bsp_prv_lpclk_select(lp_clk_is_t type); +void bsp_prv_rtc_mirror_init(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.c new file mode 100644 index 000000000000..32c3eb575473 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.c @@ -0,0 +1,62 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define ASCII_3095 (('3' << 24) | ('0' << 16) | ('9' << 8) | '5') /* 0x33303935 = '3' '0' '9' '5' */ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +static uint32_t bsp_prv_chip_revision BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +/*******************************************************************************************************************//** + * Check whether we are running on RA6W1 revision A. + * + * @retval true if we are running on RA6W1 revision A, false otherwise. + **********************************************************************************************************************/ +bool bsp_is_chip_revision_a (void) +{ + return bsp_prv_chip_revision == 0; +} + +/*******************************************************************************************************************//** + * Initialize chip revision and check whether we are running on RA6W1 chip. + * + * @retval true if we are running on RA6W1 chip, false otherwise. + **********************************************************************************************************************/ +bool bsp_device_info_init (void) +{ + union + { + uint8_t arr[4]; + uint32_t value; + } device_chip_id; + + /* Initial chip revision is 'A'. Subtract 'A' to get numeric value. */ + bsp_prv_chip_revision = CHIP_VERSION->CHIP_REVISION_REG_b.CHIP_REVISION - 'A'; + + device_chip_id.arr[3] = CHIP_VERSION->CHIP_ID1_REG_b.CHIP_ID1; + device_chip_id.arr[2] = CHIP_VERSION->CHIP_ID2_REG_b.CHIP_ID2; + device_chip_id.arr[1] = CHIP_VERSION->CHIP_ID3_REG_b.CHIP_ID3; + device_chip_id.arr[0] = CHIP_VERSION->CHIP_ID4_REG_b.CHIP_ID4; + + return device_chip_id.value == ASCII_3095; +} + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.h new file mode 100644 index 000000000000..1bf0682cd008 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_device_info.h @@ -0,0 +1,43 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DEVICE_INFO_RA6W1_H +#define BSP_DEVICE_INFO_RA6W1_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "bsp_freeze.h" +#include "bsp_dmac.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +bool bsp_is_chip_revision_a(void); +bool bsp_device_info_init(void); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dmac.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dmac.h new file mode 100644 index 000000000000..a6f1ac8a536c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dmac.h @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DMAC_H +#define BSP_DMAC_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Channel request trigger */ +typedef enum e_bsp_dmac_trig_ra6w1 +{ + BSP_DMAC_TRIG_SPI1_RX = 0x0, + BSP_DMAC_TRIG_SPI1_TX = 0x1, + BSP_DMAC_TRIG_SPI2_RX = 0x2, + BSP_DMAC_TRIG_SPI2_TX = 0x3, + BSP_DMAC_TRIG_UART1_RX = 0x4, + BSP_DMAC_TRIG_UART1_TX = 0x5, + BSP_DMAC_TRIG_UART2_RX = 0x6, + BSP_DMAC_TRIG_UART2_TX = 0x7, + BSP_DMAC_TRIG_UART3_RX = 0x8, + BSP_DMAC_TRIG_UART3_TX = 0x9, + BSP_DMAC_TRIG_I2C1_RX = 0xA, + BSP_DMAC_TRIG_I2C1_TX = 0xB, + BSP_DMAC_TRIG_I2C2_RX = 0xC, + BSP_DMAC_TRIG_I2C2_TX = 0xD, + BSP_DMAC_TRIG_AUXADC0 = 0xE, + BSP_DMAC_TRIG_AUXADC1 = 0xF, + BSP_DMAC_TRIG_AUXADC2 = 0x10, + BSP_DMAC_TRIG_AUXADC3 = 0x11, + BSP_DMAC_TRIG_SRC_IN = 0x12, + BSP_DMAC_TRIG_SRC_OUT = 0x13, + BSP_DMAC_TRIG_DAI_TX = 0x14, + BSP_DMAC_TRIG_DAI_RX = 0x15, + BSP_DMAC_TRIG_NONE = 0x1F +} bsp_dmac_trig_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************/ /** + * Check whether specified DMA trigger is edge sensitive or not. + * + * @param[in] trigger DMA trigger. + * + * @retval true Trigger is (positive) edge-sensitive. + * @retval false Trigger is level-sensitive. + **********************************************************************************************************************/ +__STATIC_INLINE bool R_BSP_DMAC_IsEdgeSensitiveTrigger (bsp_dmac_trig_t trigger) +{ + FSP_PARAMETER_NOT_USED(trigger); + + return false; +} + +/*******************************************************************************************************************/ /** + * Enable interrupt generation by specified DMA channel. + * + * @param[in] channel DMA channel. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_DMAC_ChannelInterruptsEnable (uint8_t channel) +{ + FSP_CRITICAL_SECTION_DEFINE; + + FSP_CRITICAL_SECTION_ENTER; + DMA->DMA_INT_MASK_REG |= 1U << channel; + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************/ /** + * Disable interrupt generation by specified DMA channel. + * + * @param[in] channel DMA channel. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_DMAC_ChannelInterruptsDisable (uint8_t channel) +{ + FSP_CRITICAL_SECTION_DEFINE; + + FSP_CRITICAL_SECTION_ENTER; + DMA->DMA_INT_MASK_REG &= ~(1U << channel); + FSP_CRITICAL_SECTION_EXIT; +} + +/** @} (end addtogroup BSP_MCU) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.c new file mode 100644 index 000000000000..2451883fcf16 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.c @@ -0,0 +1,552 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include +#include + +#include "bsp_dump_mem.h" +#include "sdk_defs.h" + +#if CFG_WIFI +#include "rm_wifi_config.h" +#endif /* CFG_WIFI */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#define COLOR_LEN 10 +#define MAX_FAULT 5 + +#if !defined(ARRAY_SIZE) + #define ARRAY_SIZE(x) (long) (sizeof(x) / sizeof(x)[0]) +#endif + +/* Retention Macro definitions */ +#define OOPS_STACK_SIZE 97 +#define OOPS_STACK_STRING_CODE 0XABBADEAD +#define OOPS_STACK_STRING_CHAR_SIZE 80 +#define OOPS_STACK_STRING_UINT_SIZE (OOPS_STACK_STRING_CHAR_SIZE / sizeof(uint32_t)) +#define OOPS_THREAD_SIZE 43 +#define OOPS_FAIL_MARK 0xCAFEBABA +#define OOPS_INIT_MARK 0xDEADBEEF +#define OOPS_STACK_PICS 19 +#define OOPS_STACK_SICS (7 + 6) + +typedef struct st_oops_tag_info +{ + uint32_t tag; + + /* Application Mark */ + uint16_t mark; + + /* Dump Length */ + uint16_t length; + + /* Fault type */ + uint32_t mode; + + /* RTC Time Stamp */ + uint32_t rtc[2]; +} oops_tag_type_t; + +typedef struct st_monitor_info +{ + uint32_t fault_PC; + uint8_t fault_CNT; + uint8_t autoRebootStopFlag; + uint8_t reserved_26; + uint8_t reserved_27; +} monitor_info_t; + +oops_tag_type_t g_bsp_mem_dump_oops_tag BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +uint32_t g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE + 1 + OOPS_STACK_STRING_UINT_SIZE] BSP_PLACE_IN_SECTION( + BSP_SECTION_NOINIT); +uint32_t g_bsp_mem_dump_oops_thread_ctxt[OOPS_THREAD_SIZE] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); +volatile monitor_info_t g_bsp_mem_dump_continuous_fault_info BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +volatile monitor_info_t * g_bsp_mem_dump_monitor_info_ptr = &g_bsp_mem_dump_continuous_fault_info; + +char g_bsp_mem_dump_halt_color[COLOR_LEN]; +char g_bsp_mem_dump_halt_color[COLOR_LEN]; +char g_bsp_mem_dump_clear_color[COLOR_LEN]; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static void bsp_save_assert_string(const char * format, ...); +static void bsp_set_stop_auto_reboot(void); +static void bsp_clear_stop_auto_reboot(void); +static void bsp_increase_fault_count(void); +static void bsp_check_fault_pc(uint32_t faultPC); +static void bsp_display_oops_dump_thread_info(void); +static void bsp_print_fault_pc(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +BSP_WEAK_REFERENCE uint16_t BSP_SaveOopsDumpThreadInfo (void) // freeRTOS port +{ + uint16_t info_length = 0; + + return info_length; +} + +/*******************************************************************************************************************//** + * Default implementation of assert for GCC. + **********************************************************************************************************************/ + +void __assert_func (const char * file, int line, const char * func, const char * expr) +{ + const char * filename = strrchr(file, '/') ? strrchr(file, '/') + 1 : file; + + bsp_save_assert_string("%s:%d ASSERT(%s) @%s\n", filename, line, expr, func); + + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +static void bsp_set_stop_auto_reboot (void) +{ + g_bsp_mem_dump_monitor_info_ptr->autoRebootStopFlag = 1; +} + +static void bsp_clear_stop_auto_reboot (void) +{ + g_bsp_mem_dump_monitor_info_ptr->autoRebootStopFlag = 0; +} + +static void bsp_increase_fault_count (void) +{ + ++g_bsp_mem_dump_monitor_info_ptr->fault_CNT; +} + +static void bsp_check_fault_pc (uint32_t faultPC) +{ + bsp_increase_fault_count(); + + if ((BSP_GetFaultCount() >= MAX_FAULT) && (BSP_GetFaultPc() == faultPC)) + { + BSP_SetFaultCount(0); + BSP_SetFaultPc(0); + bsp_set_stop_auto_reboot(); + + return; + } + + if (BSP_GetFaultPc() != faultPC) + { + BSP_SetFaultCount(1); + BSP_SetFaultPc(faultPC); + } + + bsp_clear_stop_auto_reboot(); +} + +static void bsp_save_assert_string (const char * format, ...) +{ + va_list args; + va_start(args, format); + + // Safely format into the global buffer + vsnprintf((char *) (&g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE + 1]), OOPS_STACK_STRING_CHAR_SIZE, format, + args); + + va_end(args); + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE] = OOPS_STACK_STRING_CODE; +} + +void BSP_SaveOopsDump (uint32_t * mspfile, uint32_t * pspfile, uint32_t mode) +{ + uint32_t i, dumpaddr; + + memset(g_bsp_mem_dump_oops_stack_ctxt, 0, sizeof(int) * OOPS_STACK_SIZE); + + /* R0-R3 */ + for (i = 0; i < 4; i++) + { + g_bsp_mem_dump_oops_stack_ctxt[i] = mspfile[i]; + } + + /* R4-R11 */ + for (i = 4; i < 12; i++) + { + g_bsp_mem_dump_oops_stack_ctxt[i] = pspfile[i - 4]; + } + + /* R12 */ + g_bsp_mem_dump_oops_stack_ctxt[12] = mspfile[4]; + + /* SP */ + g_bsp_mem_dump_oops_stack_ctxt[13] = (uint32_t) (&(mspfile[8])); + + /* LR */ + g_bsp_mem_dump_oops_stack_ctxt[14] = mspfile[5]; + + /* PC */ + g_bsp_mem_dump_oops_stack_ctxt[15] = mspfile[6]; + + bsp_check_fault_pc(mspfile[6]); + + /* PSR */ + g_bsp_mem_dump_oops_stack_ctxt[16] = mspfile[7]; + + /* EXC_RETURN */ + g_bsp_mem_dump_oops_stack_ctxt[17] = pspfile[8]; + + dumpaddr = g_bsp_mem_dump_oops_stack_ctxt[13]; + + for (i = 0; i < 48; i++) + { + if (dumpaddr <= (uint32_t) (&__ddsc_RAM_END)) + { + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + i] = *((uint32_t *) (dumpaddr)); + dumpaddr = dumpaddr + sizeof(uint32_t); + } + else + { + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + i] = 0; + break; + } + } + + g_bsp_mem_dump_oops_stack_ctxt[18] = i; + + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 0] = SCB->SHCSR; + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 1] = SCB->CFSR; + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 2] = SCB->HFSR; + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 3] = SCB->DFSR; + + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 4] = SCB->MMFAR; + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 5] = SCB->BFAR; + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + 6] = SCB->AFSR; + + g_bsp_mem_dump_oops_tag.length = sizeof(uint32_t) * (OOPS_STACK_PICS + 48 + OOPS_STACK_SICS); + g_bsp_mem_dump_oops_tag.length += BSP_SaveOopsDumpThreadInfo(); + g_bsp_mem_dump_oops_tag.mode = mode; + + if (g_bsp_mem_dump_oops_tag.tag != OOPS_INIT_MARK) + { + g_bsp_mem_dump_oops_tag.tag = OOPS_FAIL_MARK; + BSP_DisplayOopsDump(NULL, NULL, NULL); + } + else + { + g_bsp_mem_dump_oops_tag.tag = OOPS_FAIL_MARK; + + SWRESET; + } + + for (i = 0; i < 0x10000; i++) + { + __asm__ volatile ( "nop \n"); + } +} + +void BSP_InitOopsData (void) +{ + memset(&g_bsp_mem_dump_oops_tag, 0, sizeof(oops_tag_type_t)); + memset(g_bsp_mem_dump_oops_stack_ctxt, 0, sizeof(int) * OOPS_STACK_SIZE); + g_bsp_mem_dump_oops_tag.tag = OOPS_INIT_MARK; +} + +uint32_t BSP_GetFaultPc (void) +{ + return g_bsp_mem_dump_monitor_info_ptr->fault_PC; +} + +void BSP_SetFaultPc (uint32_t pc) +{ + g_bsp_mem_dump_monitor_info_ptr->fault_PC = pc; +} + +uint8_t BSP_GetFaultCount (void) +{ + return g_bsp_mem_dump_monitor_info_ptr->fault_CNT; +} + +void BSP_SetFaultCount (uint8_t cnt) +{ + g_bsp_mem_dump_monitor_info_ptr->fault_CNT = cnt; +} + +#ifndef TEST_HAS_OWN_EXCEPTION_HDL +void HardFault_HandlerC (unsigned long * exception_args) +{ + (void) exception_args; + + __asm("tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + "push {r4-r11,lr} \n" + "mov r1, sp \n" + "mov r2, #0 \n" + "bl BSP_SaveOopsDump \n"); + while (1) + { + } +} + +void MemManage_Handler (void) +{ + __asm("tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + "push {r4-r11,lr} \n" + "mov r1, sp \n" + "mov r2, #1 \n" + "bl BSP_SaveOopsDump \n"); + while (1) + { + } +} + +void BusFault_Handler (void) +{ + __asm("tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + "push {r4-r11,lr} \n" + "mov r1, sp \n" + "mov r2, #2 \n" + "bl BSP_SaveOopsDump \n"); + while (1) + { + } +} + +void UsageFault_Handler (void) +{ + __asm("tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + "push {r4-r11,lr} \n" + "mov r1, sp \n" + "mov r2, #3 \n" + "bl BSP_SaveOopsDump \n"); + while (1) + { + } +} + +#endif + +static void bsp_print_fault_pc (void) +{ + printf(g_bsp_mem_dump_halt_color); + printf("\n Stop auto--reboot (Fault_count:%d Fault_PC:0x%lx) \n", BSP_GetFaultCount(), BSP_GetFaultPc()); + printf(g_bsp_mem_dump_clear_color); +} + +static void bsp_display_oops_dump_thread_info (void) +{ + uint32_t i, dumpaddr; + + printf("\n\n Current Thread\n"); + + /* TaskName */ + if (strlen((char *) &g_bsp_mem_dump_oops_thread_ctxt[0]) > 0) + { + printf(g_bsp_mem_dump_halt_color); + printf("\t Thread: %s\r\n", (char *) &g_bsp_mem_dump_oops_thread_ctxt[0]); + printf(g_bsp_mem_dump_clear_color); + printf("\t stack ptr : 0x%lx\n", g_bsp_mem_dump_oops_thread_ctxt[5]); + printf("\t stack base: 0x%lx\n", g_bsp_mem_dump_oops_thread_ctxt[6]); + printf("\t stack end : 0x%lx\n", g_bsp_mem_dump_oops_thread_ctxt[7]); + printf("\t stack high: 0x%lx\n", g_bsp_mem_dump_oops_thread_ctxt[8]); + printf("\t max usage : 0x%lx\n", g_bsp_mem_dump_oops_thread_ctxt[7] - g_bsp_mem_dump_oops_thread_ctxt[5] + 1); + printf("\t suspend : %08lx\n", g_bsp_mem_dump_oops_thread_ctxt[9]); + + printf("\n Thread Stack (%ld)", g_bsp_mem_dump_oops_thread_ctxt[10]); + + dumpaddr = ((uint32_t) &(g_bsp_mem_dump_oops_thread_ctxt[11])); + + for (i = 0; i < g_bsp_mem_dump_oops_thread_ctxt[10]; i++) + { + if (dumpaddr <= (uint32_t) (&__ddsc_RAM_END)) + { + if ((i % 8) == 0) + { + printf("\n [0x%08lx] : ", (g_bsp_mem_dump_oops_thread_ctxt[5] + (i * sizeof(uint32_t)))); + } + + printf("%08lX ", *((uint32_t *) dumpaddr)); + + dumpaddr = dumpaddr + sizeof(uint32_t); + } + else + { + break; + } + } + } +} + +uint32_t * BSP_GetOopsThreadPtr (void) +{ + return &g_bsp_mem_dump_oops_thread_ctxt[0]; +} + +uint16_t BSP_GetOopsThreadSize (void) +{ + return (uint16_t) (sizeof(uint32_t) * OOPS_THREAD_SIZE); +} + +void BSP_DisplayOopsDump (char * halt_color_ptr, char * bold_color_ptr, char * clear_color_ptr) +{ + const char * exception_title[] = {"Hard", "MPU", "BUS", "Usage", "Stack", "Wdog"}; + const char * reg_msg_format = "\t%s :%08x%s"; + const char * regdelimiter[] = + { + "R0 ", "R1 ", + "R2 ", "R3 ","R4 ", "R5 ", "R6 ", "R7 ", + "R8 ", "R9 ","R10", "R11", "R12", "SP ", + "LR ", "PC ","PSR", "EXC" + }; + const char * faultdelimiter[] = + { + "SHCSR", "CFSR ", "HFSR ", "DFSR ", "MMFAR", "BFAR ", "AFSR " + }; + + uint32_t i, dumpaddr; + + if (halt_color_ptr) + { + strncpy(g_bsp_mem_dump_halt_color, halt_color_ptr, COLOR_LEN - 1); + g_bsp_mem_dump_halt_color[COLOR_LEN - 1] = '\0'; + } + else + { + g_bsp_mem_dump_halt_color[0] = '\0'; + } + + if (bold_color_ptr) + { + strncpy(g_bsp_mem_dump_halt_color, bold_color_ptr, COLOR_LEN - 1); + g_bsp_mem_dump_halt_color[COLOR_LEN - 1] = '\0'; + } + else + { + g_bsp_mem_dump_halt_color[0] = '\0'; + } + + if (clear_color_ptr) + { + strncpy(g_bsp_mem_dump_clear_color, clear_color_ptr, COLOR_LEN - 1); + g_bsp_mem_dump_clear_color[COLOR_LEN - 1] = '\0'; + } + else + { + g_bsp_mem_dump_clear_color[0] = '\0'; + } + +#if WIFI_CFG_WATCHDOG_SERVICE_ENABLE + extern volatile uint32_t g_watchdog_service_w_nmi_event_data[9]; + + if (0xDEADBEEFU == g_watchdog_service_w_nmi_event_data[0]) + { + printf(g_bsp_mem_dump_halt_color); + printf("\n [%s Fault Exception]\n", exception_title[5]); + printf(g_bsp_mem_dump_clear_color); + printf("\n Register-Dump\n"); + printf("\tR0 :%08lX, R1 :%08lX, R2 :%08lX, R3 :%08lX\n", + g_watchdog_service_w_nmi_event_data[1], + g_watchdog_service_w_nmi_event_data[2], + g_watchdog_service_w_nmi_event_data[3], + g_watchdog_service_w_nmi_event_data[4]); + + printf("\tR12 :%08lX, LR :%08lX, PC :%08lX, PSR :%08lX\n", + g_watchdog_service_w_nmi_event_data[5], + g_watchdog_service_w_nmi_event_data[6], + g_watchdog_service_w_nmi_event_data[7], + g_watchdog_service_w_nmi_event_data[8]); + + bsp_display_oops_dump_thread_info(); + printf("\n"); + + g_watchdog_service_w_nmi_event_data[0] = 0U; + + return; + } +#endif + + if (g_bsp_mem_dump_oops_tag.tag == OOPS_FAIL_MARK) + { + g_bsp_mem_dump_oops_tag.tag = 0; + } + else + { + return; + } + + printf(g_bsp_mem_dump_halt_color); + printf("\n [%s Fault Exception]\n", exception_title[g_bsp_mem_dump_oops_tag.mode]); + printf(g_bsp_mem_dump_clear_color); + + printf("\n Register-Dump\n"); + for (i = 0; i < ARRAY_SIZE(regdelimiter); i++) + { + printf(reg_msg_format, regdelimiter[i], g_bsp_mem_dump_oops_stack_ctxt[i], ((i % 4 == 3) ? "\n" : ",")); + } + + printf("\n Fault Status\n"); + for (i = 0; i < ARRAY_SIZE(faultdelimiter); i++) + { + printf(reg_msg_format, faultdelimiter[i], g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS + 48 + i], + ((i % 3 == 2) ? "\r\n" : ",")); + } + + printf("\n Stack-Dump (%ld)", g_bsp_mem_dump_oops_stack_ctxt[18]); + dumpaddr = ((uint32_t) &(g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_PICS])); + + for (i = 0; i < g_bsp_mem_dump_oops_stack_ctxt[18]; i++) + { + if (dumpaddr <= (uint32_t) (&__ddsc_RAM_END)) + { + if ((i % 8) == 0) + { + printf("\r\n [0x%08lx] : " + , + (g_bsp_mem_dump_oops_stack_ctxt[13] + (i * sizeof(uint32_t)))); + } + + printf("%08lX ", *((uint32_t *) dumpaddr)); + + dumpaddr = dumpaddr + sizeof(uint32_t); + } + else + { + break; + } + } + + /* Dump thread info */ + bsp_display_oops_dump_thread_info(); + + printf("\n"); + bsp_print_fault_pc(); + printf("\n"); + + if (OOPS_STACK_STRING_CODE == g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE]) + { + printf("\n Assert at\n"); + printf("\t%s\n", (char *) (&g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE + 1])); + g_bsp_mem_dump_oops_stack_ctxt[OOPS_STACK_SIZE] = 0; + } +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.h new file mode 100644 index 000000000000..a57faec54e94 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_dump_mem.h @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DUMP_MEM_H +#define BSP_DUMP_MEM_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/* Retention section definitions */ +extern uint32_t __ddsc_RAM_END; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +uint32_t BSP_GetFaultPc(void); +void BSP_SetFaultPc(uint32_t pc); +uint8_t BSP_GetFaultCount(void); +void BSP_SetFaultCount(uint8_t cnt); +void BSP_SaveOopsDump(uint32_t * mspfile, uint32_t * pspfile, uint32_t mode); +uint16_t BSP_SaveOopsDumpThreadInfo(void); +void BSP_InitOopsData(void); +void BSP_DisplayOopsDump(char * halt_color_ptr, char * bold_color_ptr, char * clear_color_ptr); +uint32_t * BSP_GetOopsThreadPtr(void); +uint16_t BSP_GetOopsThreadSize(void); + +#ifndef TEST_HAS_OWN_EXCEPTION_HDL +void HardFault_HandlerC(unsigned long * exception_args); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_feature.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_feature.h new file mode 100644 index 000000000000..05306b0407c3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_feature.h @@ -0,0 +1,171 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* TODO remove the following code when we finally drop AA chip revision: */ +#ifndef DEVICE_REV_A + #define DEVICE_REV_A ((((1 << 0) << 8) & 0x00000F00)) +#endif +#ifndef DEVICE_REV_B + #define DEVICE_REV_B ((((1 << 1) << 8) & 0x00000F00)) +#endif +#ifndef BSP_DEVICE_REVISION + #define BSP_DEVICE_REVISION DEVICE_REV_B +#endif + +#define BSP_FEATURE_BSP_HAS_ICU (0U) + +/* + * \brief TCS - Trimmed Configuration Script + * + * Enabling this feature the system will always use the trimmed configuration values + * stored by the TCS in OTP + */ +#define BSP_FEATURE_BSP_USE_TCS (1U) + +// TIN-TODO Is this a BSP_FEATURE ? +#define BSP_FEATURE_BLOCK_MEDIA_SPI_W_BLOCK_SIZE (4096U) + +#define BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS (4U) + +#define BSP_FEATURE_CGC_HAS_HCLK_DIV (1U) +#define BSP_FEATURE_CGC_HAS_PCLK_DIV (0U) +#define BSP_FEATURE_CGC_HAS_QCLK_DIV (0U) +#define BSP_FEATURE_CGC_HAS_LP_CLOCK (0U) +#define BSP_FEATURE_CGC_HAS_RCHS (0U) +#define BSP_FEATURE_CGC_HAS_RCLP (0U) +#define BSP_FEATURE_CGC_HAS_RCX (1U) +#define BSP_FEATURE_CGC_HAS_RCX_CONTROL (0U) +#define BSP_FEATURE_CGC_HAS_XTALM_SWITCH (0U) + +// Crypto Features +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_CC312 (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) + +#define BSP_FEATURE_DMAC_W (1) +#define BSP_FEATURE_DMAC_HAS_SHARED_IRQ (1U) +#define BSP_FEATURE_DMAC_MAX_CHANNEL (16U) + +#define BSP_FEATURE_ELC_MISSING (1U) + +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) +#define BSP_FEATURE_FLASH_HP_VERSION (0) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) +#define BSP_FEATURE_FLASH_LP_VERSION (0) +#define BSP_FEATURE_FLASH_IS_INTERNAL (0) + +#define BSP_FEATURE_I2C_VERSION (1) +#define BSP_FEATURE_I2C_VALID_CHANNEL_MASK (0x06U) +#define BSP_FEATURE_I2C_HAS_DEDICATED_IRQS (0) +#define BSP_FEATURE_I2C_HAS_SEPARATE_PD (0) +#define BSP_FEATURE_I2C_IRQ_TRIGGER_EDGE (1) + +// I2S Features +#define BSP_FEATURE_I2S_FIFO_NUM_STAGES (4U) +#define BSP_FEATURE_I2S_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFFFFFU) + +#define BSP_FEATURE_IO_HAS_LATCHING (0U) +#define BSP_FEATURE_IO_PORT_COUNT (2U) +#define BSP_FEATURE_IO_PORT0_GPIO_COUNT (14U) +#define BSP_FEATURE_IO_PORT1_GPIO_COUNT (18U) +#define BSP_FEATURE_IO_PORT2_GPIO_COUNT (0U) + +/* LPM_B */ +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) +#define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (0U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) + +/* OSPI_W + * RA6W1 has only one channel for OSPI_W + */ +#define BSP_FEATURE_OSPI_W_DEVICE_0_START_ADDRESS (0x2A000000U) +#define BSP_FEATURE_OSPI_W_DEVICE_1_START_ADDRESS (0x0U) /* not supported */ +#define BSP_FEATURE_FLASH_DATA_FLASH_START (BSP_FEATURE_OSPI_W_DEVICE_0_START_ADDRESS | 0x00300000U) + +/* QSPI_W */ +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x24000000U) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS_DATA (0x24000000U) +#define BSP_FEATURE_QSPI_MAX_CHANNEL (1U) +#define BSP_FEATURE_QSPI_HAS_DDR_SUPPORT (0U) + +#define BSP_FEATURE_SPI_VALID_CHANNEL_MASK (0x06U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_TCS_APPLY (0U) +#define BSP_FEATURE_TCS_SYS_RAM (1U) + +#define BSP_FEATURE_TIM_W_VALID_CHANNEL_MASK (0x1FEU) +#define BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS (0x4U) +#define BSP_FEATURE_TIM_W_HAS_IRQ_PER_CAPTURE_CHANNEL (0x0U) +#define BSP_FEATURE_TIM_W_LINEAR_SRC_DIV_STEP (0x1U) +#define BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH (0x0U) +#define BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY (0x0U) +#define BSP_FEATURE_TIM_W_SUPPORTS_SEQ_CAPTURES (0x0U) +#define BSP_FEATURE_TIM_W_SUPPORTS_OVERFLOW_UNDERFLOW (0x0U) +#define BSP_FEATURE_TIM_W_SUPPORTS_RESET_NATIVELY (0x0U) + +#define BSP_FEATURE_TRANSFER_HAS_DTC (0) + +#define BSP_FEATURE_UART_W_VALID_CHANNEL_MASK (0x0EU) +#define BSP_FEATURE_UART_W_FIFO_DEPTH (32U) + +#define BSP_FEATURE_WDT_CLOCK_FREQUENCY (100U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_freeze.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_freeze.h new file mode 100644 index 000000000000..9a27519693b2 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_freeze.h @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_FREEZE_RA6W1_H +#define BSP_FREEZE_RA6W1_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Peripheral to freeze */ +typedef enum e_bsp_freeze_peripheral_ra6w1 +{ + BSP_FREEZE_PERIPHERAL_WKUPTIM = 0, + BSP_FREEZE_PERIPHERAL_SWTIM = 1, + BSP_FREEZE_PERIPHERAL_SWTIM2 = 2, + BSP_FREEZE_PERIPHERAL_SWTIM3 = 3, + BSP_FREEZE_PERIPHERAL_SWTIM4 = 4, + BSP_FREEZE_PERIPHERAL_SWTIM5 = 5, + BSP_FREEZE_PERIPHERAL_SWTIM6 = 6, + BSP_FREEZE_PERIPHERAL_SWTIM7 = 7, + BSP_FREEZE_PERIPHERAL_SWTIM8 = 8, + BSP_FREEZE_PERIPHERAL_SYS_WDOG = 9, + BSP_FREEZE_PERIPHERAL_DMA = 11, + BSP_FREEZE_PERIPHERAL_KDMA = 12, +} bsp_freeze_peripheral_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************/ /** + * Suspend activity of specified peripheral on MCU. + * + * @param[in] peripheral Peripheral to freeze. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PeripheralFreeze (bsp_freeze_peripheral_t peripheral) +{ + CRG_TOP->SET_FREEZE_REG = (uint32_t) (1 << peripheral); +} + +/*******************************************************************************************************************/ /** + * Check whether specified peripheral is frozen or not. + * + * @param[in] peripheral Peripheral to check. + * + * @retval true Peripheral is frozen. + * @retval false Peripheral is active. + **********************************************************************************************************************/ +__STATIC_INLINE bool R_BSP_IsPeripheralFrozen (bsp_freeze_peripheral_t peripheral) +{ + return !!(CRG_TOP->SET_FREEZE_REG & ((uint32_t) (1 << peripheral))); +} + +/*******************************************************************************************************************/ /** + * Resume activity of specified peripheral on MCU. + * + * @param[in] peripheral Peripheral to unfreeze. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PeripheralUnFreeze (bsp_freeze_peripheral_t peripheral) +{ + CRG_TOP->RESET_FREEZE_REG = (uint32_t) (1 << peripheral); +} + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_init.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_init.c new file mode 100644 index 000000000000..1a7c0021ebb8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_init.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#if BSP_FEATURE_BSP_USE_TCS + #include "bsp_tcs.h" + #include "bsp_otp.h" +#endif +#include +#include +#include "bsp_rand.h" +#ifdef RM_STDIO_W +#include "rm_stdio_w_cfg.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define TRNG_SYS_RETRY_LIMIT (1000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef void (* bsp_init_func_ptr)(void); + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +extern void R_BSP_WarmStart(bsp_warm_start_event_t event); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void bsp_wdt_freeze_cfg(void); +static void ra6w1_SystemInitPostC(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Handle WDT Freeze. + * + * WDT is enabled after reset by default. + * In case r_wdog_w module is not included in the project, WDT should be disabled by BSP. + * bsp_wdt_freeze_cfg weak function - will disable WDT in case r_wdog_w module is not included. + * bsp_wdt_freeze_cfg normal function - will do nothing, hence WDT remains enabled, in case r_wdog_w is included. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE void bsp_wdt_freeze_cfg (void) +{ + CRG_TOP->SET_FREEZE_REG_b.FRZ_SYS_WDOG = 1; +} + +static void ra6w1_SystemInitPostC (void) +{ + /* + * TIN-TODO: This is a weak function that freezes the watchdog. It is redefined in + * r_wdog_w, where it does nothing. I suppose that it is helpful as it allows for test + * runners that do not need to explicitly freeze the watchdog, but from an SDK point of view + * the watchdog is the applications responsibility. The startup code should only refresh it where + * necessary. + *//* If WDT watchdog is not used - freeze it */ + uint32_t s = 0U; + + for (int tries = 0; tries < TRNG_SYS_RETRY_LIMIT; tries++) + { + s = trng_rand() & (uint32_t) HW_ACC_PRNG_SEED_REG_PRNG_SEED_VAL_Msk; + + if (s != 0U) + { + break; + } + } + + bsp_wdt_freeze_cfg(); + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + +#if BSP_FEATURE_BSP_USE_TCS + + /* enable OTP to read TCS values */ + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + + /* get TCS values */ + bsp_tcs_get_trim_values_from_cs(); + + /* Close OTP */ + bsp_otp_close(); +#endif + +#if defined(CONFIG_RETARGET) || defined(CONFIG_RTT) + /* This is needed to initialize stdout, so that it can be used by putchar (that doesn't initialize stdout, + * contrary to printf). Putchar is needed by the Unity test framework + * This also has the side effect of changing stdout to unbuffered (which seems more reasonable) + */ + setvbuf(stdout, NULL, _IONBF, 0); +#endif + + /* TIN_HACK_WIFI: This was here in fsp-rrq and was removed in fsp-da but did not go anywhere else? + * TODO: the following clock configuration must be removed, see TVR-398 + */ + REG_SETF(CRG_TOP, CLK_AMBA_REG, PERI_CLK_ENABLE, 1); + REG_SETF(CRG_TOP, CLK_AMBA_REG, TIMER_CLK_ENABLE, 1); + + /* Initialize SystemWakeupSource variable. */ + SystemWakeupSourceUpdate(); + +#if !BSP_CFG_OSPI_8_LINES_SUPPORT + + /* Use pins PIN1_00-PIN1_03 as GPIO instead of OQSPI lines. */ + CRG_TOP->CLK_AMBA_REG_b.OQSPI_GPIO_MODE = 1; +#endif + + // TIN-TODO: This does not seem secure at all, since the initial seed is a constant. + + /* Initiate the seed with TRNG */ + if (s == 0U) + { + s = 1U; + } + + srand(s); + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); +} + +/* + * Add pointer to ra6w1_SystemInitPostC() in an array that will go in the .init_array section. + * __libc_init_array() (which is called by _start()) calls all function pointers in .init_array. + */ +BSP_PLACE_IN_SECTION(BSP_SECTION_INIT) BSP_ALIGN_VARIABLE(__alignof__(bsp_init_func_ptr)) +static bsp_init_func_ptr ra6w1_init_array_entry[] = +{ + ra6w1_SystemInitPostC, +}; + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io.h new file mode 100644 index 000000000000..7ae4d538da3d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io.h @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_RA6W1_H +#define BSP_IO_RA6W1_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define BSP_IO_PXX_SEL_REG(_port) *(&(GPIO->GPIO_SEL_P0_REG) + (_port)) +#define BSP_IO_PXX_SEL1_REG(_port) *(&(GPIO->GPIO_SEL1_P0_REG) + (_port)) +#define BSP_IO_PXX_POL_REG(_port) *(&(GPIO->GPIO_INT_POL_P0_REG) + (_port)) +#define BSP_IO_PXX_INT_STS_REG(_port) *(&(GPIO->GPIO_INT_STS_P0_REG) + (_port)) +#define BSP_IO_PXX_INT_CLR_REG(_port) *(&(GPIO->GPIO_INT_CLR_P0_REG) + (_port)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Clocks that can be mapped to dedicated BSP_IO */ +typedef enum e_bsp_io_clk_output_ra6w1 +{ + BSP_IO_CLK_XTAL40M_OUT = (GPIO_GPIO_CLK_SEL_REG_XTAL40M_OUTPUT_EN_Msk >> 4), /**< Map clock XTAL40M to dedicated GPIO */ + BSP_IO_CLK_RC10M_OUT = (GPIO_GPIO_CLK_SEL_REG_RC10M_OUTPUT_EN_Msk >> 4), /**< Map clock RC10M to dedicated GPIO */ + BSP_IO_CLK_XTAL32K_OUT = (GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Msk >> 4), /**< Map clock XTAL32K to dedicated GPIO */ + BSP_IO_CLK_OSC32K_OUT = (GPIO_GPIO_CLK_SEL_REG_OSC32K_OUTPUT_EN_Msk >> 4), /**< Map clock OSC32K to dedicated GPIO */ + BSP_IO_CLK_FPLL98M_OUT = (GPIO_GPIO_CLK_SEL_REG_FPLL98M_OUTPUT_EN_Msk >> 4), /**< Map clock FPLL98M to dedicated GPIO */ + BSP_IO_CLK_DPLL480M_OUT = (GPIO_GPIO_CLK_SEL_REG_DPLL480M_OUTPUT_EN_Msk >> 4), /**< Map clock FPLL98M to dedicated GPIO */ + BSP_IO_CLK_MCLK_OUT = (GPIO_GPIO_CLK_SEL_REG_MCLK_OUTPUT_EN_Msk >> 4), /**< Map clock MCLK to dedicated GPIO */ + BSP_IO_CLK_NONE_OUT = 0, +} bsp_io_clk_output_t; + +/** Clocks that can be mapped to GPIO function FUNC_CLOCK */ +typedef enum e_bsp_io_clk_func_ra6w1 +{ + BSP_IO_CLK_XTAL40M_FUNC = 1, /**< Map clock XTAL40M to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_RC10M_FUNC = 2, /**< Map clock RC10M to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_XTAL32K_FUNC = 3, /**< Map clock XTAL32K to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_OSC32K_FUNC = 4, /**< Map clock OSC32K to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_FPLL98M_FUNC = 5, /**< Map clock FPLL98M to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_DPLL480M_FUNC = 6, /**< Map clock DPLL480M to GPIO function FUNC_CLOCK */ + BSP_IO_CLK_DIVN_FUNC = 7, /**< Map clock DIVn to GPIO function FUNC_CLOCK */ +} bsp_io_clk_func_t; + +/** @} (end addtogroup BSP_IO) */ +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.c new file mode 100644 index 000000000000..59ea0bf1ff91 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.c @@ -0,0 +1,266 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_io_isolation.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define RTM_RETENTION_IO_ADDR (dg_configBOOTER_RTM_ADDR + 0x60) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +bsp_io_retained_t * g_retention_gpio = (bsp_io_retained_t *) RTM_RETENTION_IO_ADDR; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +__STATIC_INLINE uint32_t bsp_check_gpio_retention_domain (bsp_io_port_pin_t pin, uint32_t * domain) +{ + if (pin <= BSP_IO_PORT_00_PIN_03) + { + *domain |= IO_RETENTION_VBAT; + } + else if ((pin >= BSP_IO_PORT_00_PIN_04) && (pin <= BSP_IO_PORT_00_PIN_07)) + { + *domain |= IO_RETENTION_DIO1_1; + } + else if ((pin >= BSP_IO_PORT_00_PIN_08) && (pin <= BSP_IO_PORT_00_PIN_13)) + { + *domain |= IO_RETENTION_DIO1_2; + } + else if ((pin >= BSP_IO_PORT_01_PIN_00) && (pin <= BSP_IO_PORT_01_PIN_09)) + { + *domain |= IO_RETENTION_FDIO; + } + else if ((pin >= BSP_IO_PORT_01_PIN_10) && (pin <= BSP_IO_PORT_01_PIN_15)) + { + *domain |= IO_RETENTION_DIO2; + } + + return true; +} + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_pio_function_set (bsp_io_port_pin_t pin, bsp_io_retained_type_t type) +{ + switch (type) + { + case BSP_IO_REATAINED_INPUT: + { + R_BSP_PinCfg(pin, GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_INPUT); + break; + } + + case BSP_IO_REATAINED_INPUT_PULLUP: + { + R_BSP_PinCfg(pin, GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_PULLUP_ENABLE); + break; + } + + case BSP_IO_REATAINED_INPUT_PULLDOWN: + { + R_BSP_PinCfg(pin, GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_PULLDOWN_ENABLE); + break; + } + + case BSP_IO_REATAINED_OUTPUT_HIGH: + { + R_BSP_PinCfg(pin, GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_OUTPUT); + R_BSP_PinWrite(pin, BSP_IO_LEVEL_HIGH); + break; + } + + case BSP_IO_REATAINED_OUTPUT_LOW: + { + R_BSP_PinCfg(pin, GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_OUTPUT); + R_BSP_PinWrite(pin, BSP_IO_LEVEL_LOW); + break; + } + + default: + { + break; + } + } +} + +static void r_bsp_RetainedIo_config_pin_from_ret (uint32_t pin, uint8_t port) +{ + uint8_t pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + + if (port == 0) + { + R_BSP_PinCfg(pin, (g_retention_gpio->pio0[pin_id] & ~(1U << 15))); + R_BSP_PinWrite((bsp_io_port_pin_t)pin, + (uint32_t)g_retention_gpio->pio0[pin_id] >> 15 ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); + } + else + { + R_BSP_PinCfg(pin, (g_retention_gpio->pio1[pin_id] & ~(1U << 15))); + R_BSP_PinWrite((bsp_io_port_pin_t)pin, + (uint32_t)g_retention_gpio->pio1[pin_id] >> 15 ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); + } +} + +/*******************************************************************************************************************//** + * This function release setting retain pio and recovery pio status by setting user + * + * @param [in] clear clear retention information in retain memory. + * @return true/false + **********************************************************************************************************************/ +void R_BSP_RetainedIoRecovery (uint16_t clear) +{ + uint32_t pin; + uint32_t pin_id = 0; + + /* Loop through the PORT0 */ + for (pin = BSP_IO_PORT_00_PIN_00; pin <= BSP_IO_PORT_00_PIN_13; pin++) + { + pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + + if ((g_retention_gpio->pio0[pin_id] >= BSP_IO_REATAINED_INPUT) && + (g_retention_gpio->pio0[pin_id] <= BSP_IO_REATAINED_OUTPUT_LOW)) + { + bsp_pio_function_set((bsp_io_port_pin_t) pin, (bsp_io_retained_type_t) g_retention_gpio->pio0[pin_id]); + } + else if (g_retention_gpio->pio0[pin_id] != BSP_IO_REATAINED_RESERVED_STATUS && g_retention_gpio->pio0[pin_id]) + { + /* Restore the pin mode and state and saved again as retain */ + r_bsp_RetainedIo_config_pin_from_ret(pin, 0); + R_BSP_RetainedIoSet(pin); + } + else + { + /* Restore the pin mode and state */ + r_bsp_RetainedIo_config_pin_from_ret(pin, 0); + } + + if (clear) + { + g_retention_gpio->pio0[pin_id] = BSP_IO_REATAINED_UNUSED; + } + } + + /* Loop through the PORT1 */ + for (pin = BSP_IO_PORT_01_PIN_00; pin <= BSP_IO_PORT_01_PIN_15; pin++) + { + pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + + if ((g_retention_gpio->pio1[pin_id] >= BSP_IO_REATAINED_INPUT) && + (g_retention_gpio->pio1[pin_id] <= BSP_IO_REATAINED_OUTPUT_LOW)) + { + bsp_pio_function_set((bsp_io_port_pin_t) pin, (bsp_io_retained_type_t) g_retention_gpio->pio1[pin_id]); + } + else if (g_retention_gpio->pio1[pin_id] != BSP_IO_REATAINED_RESERVED_STATUS && g_retention_gpio->pio1[pin_id]) + { + /* Restore the pin mode and state and saved again as retain */ + r_bsp_RetainedIo_config_pin_from_ret(pin, 1); + R_BSP_RetainedIoSet(pin); + } + else + { + /* Restore the pin mode and state */ + r_bsp_RetainedIo_config_pin_from_ret(pin, 1); + } + + if (clear) + { + g_retention_gpio->pio1[pin_id] = BSP_IO_REATAINED_UNUSED; + } + } + + RTC->RTM_CONTROL_REG_b.RTM_CTRL_IO_RETEN_CTRL = 0; +} + +/*******************************************************************************************************************//** + * This function execute to retain GPIO as using hw_gpio_retention_pin_set. + * + * @return true/false + **********************************************************************************************************************/ +bool R_BSP_RetainedIoExecute (void) +{ + uint32_t pin; + uint16_t pin_id; + uint32_t domain = 0; + + for (pin = BSP_IO_PORT_00_PIN_00; pin <= BSP_IO_PORT_00_PIN_13; pin++) + { + pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + + if (g_retention_gpio->pio0[pin_id] == BSP_IO_REATAINED_RESERVED_STATUS) + { + bsp_check_gpio_retention_domain((bsp_io_port_pin_t)pin, &domain); + g_retention_gpio->pio0[pin_id] = (uint16_t) (BSP_IO_PXX_MODE_REG(BSP_IO_PORT_00, pin_id) | (R_BSP_PinRead((bsp_io_port_pin_t)pin) << 15)); + } + else if (g_retention_gpio->pio0[pin_id] >= BSP_IO_REATAINED_INPUT && g_retention_gpio->pio0[pin_id] <= BSP_IO_REATAINED_OUTPUT_LOW) + { + /* For legacy compatible define */ + bsp_pio_function_set((bsp_io_port_pin_t) pin, (bsp_io_retained_type_t) g_retention_gpio->pio0[pin_id]); + bsp_check_gpio_retention_domain((bsp_io_port_pin_t) pin, &domain); + } + else + { + g_retention_gpio->pio0[pin_id] = (uint16_t) (BSP_IO_PXX_MODE_REG(BSP_IO_PORT_00, pin_id) | (R_BSP_PinRead((bsp_io_port_pin_t)pin) << 15)); + } + } + + for (pin = BSP_IO_PORT_01_PIN_00; pin <= BSP_IO_PORT_01_PIN_15; pin++) + { + pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + + if (g_retention_gpio->pio1[pin_id] == BSP_IO_REATAINED_RESERVED_STATUS) + { + bsp_check_gpio_retention_domain((bsp_io_port_pin_t)pin, &domain); + g_retention_gpio->pio1[pin_id] = (uint16_t) (BSP_IO_PXX_MODE_REG(BSP_IO_PORT_01, pin_id) | (R_BSP_PinRead((bsp_io_port_pin_t)pin) << 15)); + } + else if (g_retention_gpio->pio1[pin_id] >= BSP_IO_REATAINED_INPUT && g_retention_gpio->pio1[pin_id] <= BSP_IO_REATAINED_OUTPUT_LOW) + { + /* For legacy compatible define */ + bsp_pio_function_set((bsp_io_port_pin_t) pin, (bsp_io_retained_type_t) g_retention_gpio->pio1[pin_id]); + bsp_check_gpio_retention_domain((bsp_io_port_pin_t) pin, &domain); + } + else + { + g_retention_gpio->pio1[pin_id] = (uint16_t) (BSP_IO_PXX_MODE_REG(BSP_IO_PORT_01, pin_id) | (R_BSP_PinRead((bsp_io_port_pin_t)pin) << 15)); + } + } + + RTC->RTM_CONTROL_REG_b.RTM_CTRL_IO_RETEN_CTRL = domain & IO_RETENTION_MSK; + + return true; +} + +void R_BSP_RetainedIoClear (void) +{ + memset(g_retention_gpio, 0, sizeof(bsp_io_retained_t)); +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.h new file mode 100644 index 000000000000..e17448a5f23a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_io_isolation.h @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_ISOLATION_H +#define BSP_IO_ISOLATION_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "config/bsp_memory_defaults_ra6w1.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/* + * Retention io is adjusted on a domain basis. + * Therefore, find the block of the pin for which retention-io is specified and assign retention to that domain. + * + * IO_RETENTION_VBAT contains the XTAL32k port, so it cannot be retained. + * IO_RETENTION_FDIO cannot be retained during FLASH-XIP + */ +#define IO_RETENTION_VBAT (0x10) ///< P0_00 ~ P0_03 +#define IO_RETENTION_FDIO (0x08) ///< P1_00 ~ P1_09 +#define IO_RETENTION_DIO2 (0x04) ///< P1_10 ~ P1_15 +#define IO_RETENTION_DIO1_2 (0x02) ///< P0_08 ~ P0_13 +#define IO_RETENTION_DIO1_1 (0x01) ///< P0_04 ~ P0_07 + +/* All execpt VBAT and FDIO */ +#define IO_RETENTION_MSK (IO_RETENTION_DIO2 | IO_RETENTION_DIO1_2 | IO_RETENTION_DIO1_1) + +typedef enum e_retained_type +{ + BSP_IO_REATAINED_UNUSED = 0x0, + BSP_IO_REATAINED_INPUT = 0x6f, + BSP_IO_REATAINED_INPUT_PULLUP, + BSP_IO_REATAINED_INPUT_PULLDOWN, + BSP_IO_REATAINED_OUTPUT_HIGH, + BSP_IO_REATAINED_OUTPUT_LOW, + BSP_IO_REATAINED_RESERVED_STATUS = 0xff, +} bsp_io_retained_type_t; + +typedef struct st_io_retained +{ + uint16_t pio0[16]; + uint16_t pio1[16]; +} bsp_io_retained_t; + +extern bsp_io_retained_t * g_retention_gpio; + +/*******************************************************************************************************************//** + * This function keeps the GPIO pin type during sleep. + * Save the io-state in retention memory before sleep. so that the io-state before sleep is maintained when waking up. + * + * @param[in] pin the GPIO pin + * + * @return true/false + **********************************************************************************************************************/ +__STATIC_INLINE bool R_BSP_RetainedIoSet (bsp_io_port_pin_t pin) +{ + uint32_t pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + uint32_t port = ((uint16_t) pin) >> BSP_IO_PORT_OFFSET; + + if (port == BSP_IO_PORT_00) + { + g_retention_gpio->pio0[pin_id] = BSP_IO_REATAINED_RESERVED_STATUS; + } + else if (port == BSP_IO_PORT_01) + { + g_retention_gpio->pio1[pin_id] = BSP_IO_REATAINED_RESERVED_STATUS; + } + + return true; +} + +/*******************************************************************************************************************//** + * This function determines which pin will keeping IO status during sleep. + * The PIN and its status are saved in retention memory so that the specified io-state is maintained when waking up. + * + * @param[in] pin the GPIO pin + * @param[in] type type of the GPIO PIN + * + * @return true/false + **********************************************************************************************************************/ +__STATIC_INLINE bool R_BSP_RetainedIoStatusSet (bsp_io_port_pin_t pin, bsp_io_retained_type_t type) +{ + uint32_t pin_id = (uint8_t) pin & BSP_IO_PIN_BITS; + uint32_t port = ((uint16_t) pin) >> BSP_IO_PORT_OFFSET; + + if (port == BSP_IO_PORT_00) + { + g_retention_gpio->pio0[pin_id] = type; + } + else if (port == BSP_IO_PORT_01) + { + g_retention_gpio->pio1[pin_id] = type; + } + + return true; +} + +void R_BSP_RetainedIoRecovery(uint16_t clear); + +bool R_BSP_RetainedIoExecute(); + +void R_BSP_RetainedIoClear(void); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_linker.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_linker.c new file mode 100644 index 000000000000..aad81131ddd3 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_linker.c @@ -0,0 +1,21 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_mcu_info.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_mcu_info.h new file mode 100644 index 000000000000..9e4585bff8bd --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_mcu_info.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.c new file mode 100644 index 000000000000..e07be18e5eaa --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.c @@ -0,0 +1,397 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif + +#include "bsp_otp.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +static const uint32_t g_tim1[] = +{ + /* Default 40MHz */ + (39 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos) | + (3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos) | + (0x09 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos) | + (0x09 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos), + + /* 80MHz */ + (80 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos) | + (8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos) | + (0x09 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos) | + (0x09 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos), +}; + +/*******************************************************************************************************************//** + * Set OTP cell timing parameters. + * + * @param[in] clk_speed OTPC clock speed. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void bsp_otpc_set_speed (bsp_otpc_clk_freq_t clk_speed) +{ + OTPC->OTPC_TIM1_REG = g_tim1[clk_speed]; +} + +/*******************************************************************************************************************//** + * Get OTP cell address. + * + * @param[in] cell_offset OTP cell offset. + * @return OTP cell address. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE volatile uint32_t * bsp_prv_otpc_addr (uint32_t cell_offset) +{ + return (volatile uint32_t *) (MEMORY_OTP_BASE + (4 * cell_offset)); +} + +/*******************************************************************************************************************//** + * Verify data stored in OTP. + * + * @param[in] p_data A pointer to the data that is expected to be stored in the OTP. + * It shall be at least of (num_words * 4) bytes long. + * @param[in] cell_offset OTP cell offset where data is expected to be stored. + * @param[in] num_words Number of words to verify. + * @param[in] mode OTP mode + **********************************************************************************************************************/ +static bool bsp_otp_read_verif (const uint32_t * p_data, uint32_t cell_offset, uint32_t num_words, bsp_otpc_mode_t mode) +{ + bsp_otp_mode_set(mode); + + for (uint32_t i = 0; i < num_words; i++) + { + if (*p_data != *bsp_prv_otpc_addr(cell_offset)) + { + return false; + } + + cell_offset++; + p_data++; + } + + return true; +} + +#ifdef UNIT_TESTING + +BSP_WEAK_REFERENCE void bsp_prv_otp_testable_busy_loop_hook (uintptr_t reg, uint32_t param) +{ + /* Do nothing */ + FSP_PARAMETER_NOT_USED(reg); + FSP_PARAMETER_NOT_USED(param); +} + +#endif + +/*******************************************************************************************************************//** + * Set OTP mode. + * + * @param[in] mode The new OTP mode. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void bsp_prv_otp_mode_set (bsp_otpc_mode_t mode) +{ + /* Change mode only if new mode is different than the old one */ + if (mode != OTPC->OTPC_MODE_REG_b.OTPC_MODE_MODE) + { + OTPC->OTPC_MODE_REG_b.OTPC_MODE_MODE = mode; + } +} + +/*******************************************************************************************************************//** + * Wait for OTP mode to be applied. + **********************************************************************************************************************/ +static void bsp_prv_otp_mode_change_wait (void) +{ + while (0 == OTPC->OTPC_STAT_REG_b.OTPC_STAT_MRDY) + { +#ifdef UNIT_TESTING + bsp_prv_otp_testable_busy_loop_hook((uintptr_t) &OTPC->OTPC_STAT_REG, OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Pos); +#endif + } +} + +/*******************************************************************************************************************//** + * Set OTP mode and wait for it to be applied. + * + * @param[in] mode The new OTP mode. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void bsp_prv_otp_mode_wait_until_set (bsp_otpc_mode_t mode) +{ + bsp_prv_otp_mode_set(mode); + bsp_prv_otp_mode_change_wait(); +} + +/*******************************************************************************************************************//** + * Wait for OTP programming to finish. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void bsp_otpc_wait_while_busy_programming (void) +{ + while (!OTPC->OTPC_STAT_REG_b.OTPC_STAT_PRDY) + { + ; + } +} + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the OTP controller. + * + * @note Among other things, it enables the clock of the OTP controller. + * TODO this shall not be the case, see WIFISWTIN-1591. + **********************************************************************************************************************/ +void bsp_otp_init (void) +{ + uint32_t lock; + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + while (CC312->CC312_NVM_IS_IDLE_REG_b.CC312_NVM_IS_IDLE_STATUS != 1) + { + ; + } + + /* Check PLL clock */ + if (CRG_TOP->CLK_CTRL_REG_b.PLL_PERI_ENABLE == 1) + { + bsp_otpc_set_speed(BSP_OTPC_CLK_FREQ_80MHz); + } + else + { + bsp_otpc_set_speed(BSP_OTPC_CLK_FREQ_40MHz); + } + + /* Default read mode */ + bsp_otp_mode_set(BSP_OTP_MODE_READ); + + /* Read out OTP lock bit first without below read out, it can not write to the OTP */ + lock = *bsp_prv_otpc_addr(511); + FSP_PARAMETER_NOT_USED(lock); + + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Set OTP timing for the given sysclk frequency. + * + * @param [in] sysclk_freq_MHz The target sysclk frequency, in MHz. + * + * @note Only specific frequencies are supported, depending on the device. + * TODO this function shall be updated/deleted, see WIFISWTIN-1591. + **********************************************************************************************************************/ +void bsp_otp_timings_set (uint32_t sysclk_freq_MHz) +{ + switch (sysclk_freq_MHz) + { + case 40: + { + bsp_otpc_set_speed(BSP_OTPC_CLK_FREQ_40MHz); + break; + } + + case 80: + { + bsp_otpc_set_speed(BSP_OTPC_CLK_FREQ_80MHz); + break; + } + + case 160: + { + /* TODO implement */ + break; + } + + default: + { + BSP_CHECK_DEBUG(0); + } + } +} + +/*******************************************************************************************************************//** + * Set OTP mode and wait for the change to finish. + * + * @param [in] mode The new OTP mode. + **********************************************************************************************************************/ +void bsp_otp_mode_set (uint32_t mode) +{ + bsp_prv_otp_mode_wait_until_set(mode); +} + +/*******************************************************************************************************************//** + * Read word from OTP. + * + * @param[in] cell_offset OTP cell offset. + * @return word read from OTP. + **********************************************************************************************************************/ +uint32_t bsp_otp_word_read (uint32_t cell_offset) +{ + bsp_otp_mode_set(BSP_OTP_MODE_READ); + + return *bsp_prv_otpc_addr(cell_offset); +} + +/*******************************************************************************************************************//** + * Read data from OTP. + * + * @param[out] p_data A pointer to the buffer to store OTP data into. + * It shall be at least of (num_words * 4) bytes long. + * @param[in] cell_offset OTP cell offset to start reading from. + * @param[in] num_words Number of words to read from OTP. + **********************************************************************************************************************/ +void bsp_otp_read (uint32_t * p_data, uint32_t cell_offset, uint32_t num_words) +{ + bsp_otp_mode_set(BSP_OTP_MODE_READ); + + for (uint32_t i = 0; i < num_words; i++) + { + *p_data = *bsp_prv_otpc_addr(cell_offset + i); + p_data++; + } +} + +/*******************************************************************************************************************//** + * Program word to OTP. + * + * @param[in] data A word to be programmed to OTP. + * @param[in] cell_offset OTP cell offset to start programming into. + **********************************************************************************************************************/ +uint32_t bsp_otp_word_prog (uint32_t data, uint32_t cell_offset) +{ + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + *bsp_prv_otpc_addr(cell_offset) = data; + bsp_otpc_wait_while_busy_programming(); + + return bsp_otp_word_read(cell_offset); +} + +/*******************************************************************************************************************//** + * Program data to OTP. + * + * @param[in] p_data A pointer to the data to be programmed to OTP. + * It shall be at least of (num_words * 4) bytes long. + * @param[in] cell_offset OTP cell offset to start programming into. + * @param[in] num_words Number of words to program to OTP. + **********************************************************************************************************************/ +void bsp_otp_prog (const uint32_t * p_data, uint32_t cell_offset, uint32_t num_words) +{ + uint32_t i; + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + + for (i = 0; i < num_words; i++) + { + *bsp_prv_otpc_addr(cell_offset + i) = *p_data++; + bsp_otpc_wait_while_busy_programming(); + } +} + +/*******************************************************************************************************************//** + * Program data to OTP and verify it has been programmed successfully. + * + * @param[in] p_data A pointer to the data to be programmed to OTP. + * It shall be at least of (num_words * 4) bytes long. + * @param[in] cell_offset OTP cell offset to start programming into. + * @param[in] num_words Number of words to program to OTP. + **********************************************************************************************************************/ +bool bsp_otp_prog_and_verify (const uint32_t * p_data, uint32_t cell_offset, uint32_t num_words) +{ + bsp_otp_prog(p_data, cell_offset, num_words); + + if (!bsp_otp_read_verif(p_data, cell_offset, num_words, BSP_OTP_MODE_PVFY)) + { + return false; + } + + if (!bsp_otp_read_verif(p_data, cell_offset, num_words, BSP_OTP_MODE_RINI)) + { + return false; + } + + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + + return true; +} + +/*******************************************************************************************************************//** + * Lock OTP cell region. + * + * @param[in] cell_region OTP cell region to lock. + * @return OTP lock region > 0 on success, 0 on failure (invalid cell_region). + **********************************************************************************************************************/ +uint32_t bsp_otp_lock (uint8_t cell_region) +{ + uint32_t otp_lock_region; + + if (cell_region > 30) + { + return 0; + } + + otp_lock_region = 0x01 << (cell_region); + bsp_otp_prog(&otp_lock_region, BSP_OTP_LOCK_OFFSET, 1); + + return bsp_otp_get_lock_region(); +} + +/*******************************************************************************************************************//** + * Get OTP lock region. + * + * @return OTP lock region > 0. + **********************************************************************************************************************/ +uint32_t bsp_otp_get_lock_region (void) +{ + return bsp_otp_word_read(BSP_OTP_LOCK_OFFSET); +} + +/*******************************************************************************************************************//** + * Put OTP controller in standby mode and disable it. + **********************************************************************************************************************/ +void bsp_otp_close (void) +{ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + bsp_prv_otp_mode_wait_until_set(BSP_OTP_MODE_DSTBY); + + FSP_CRITICAL_SECTION_EXIT; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.h new file mode 100644 index 000000000000..83e5c5642993 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_otp.h @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_OTP_RA6W1_H +#define BSP_OTP_RA6W1_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define BSP_OTP_CELL_NUM (0x1FF) /* Max number of OTP cells, each cell size is 4 bytes last offset is used for OTP lock */ +#define BSP_OTP_LOCK_OFFSET (0x1FF) /* Max number of OTP cells, each cell size is 4 bytes last offset is used for OTP lock */ +#define MEMORY_OTP_BASE 0x400F2000UL +#define MEMORY_OTP_END 0x400F2800UL + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** OTP Controller modes */ +typedef enum e_bsp_otpc_mode +{ + BSP_OTP_MODE_DSTBY = 0, /**< OTP cell is powered on LDO is inactive*/ + BSP_OTP_MODE_STBY = 1, /**< OTP cell and LDO are powered on, chip select is deactivated*/ + BSP_OTP_MODE_READ = 2, /**< OTP cell can be read*/ + BSP_OTP_MODE_PROG = 3, /**< OTP cell can be programmed*/ + BSP_OTP_MODE_PVFY = 4, /**< OTP cell can be read in PVFY margin read mode*/ + BSP_OTP_MODE_RINI = 5 /**< OTP cell can be read in RINI margin read mode*/ +} bsp_otpc_mode_t; + +/** System clock frequency in MHz */ +typedef enum e_bsp_otpc_clk_freq +{ + BSP_OTPC_CLK_FREQ_40MHz = 0, + BSP_OTPC_CLK_FREQ_80MHz = 1, +} bsp_otpc_clk_freq_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +uint32_t bsp_otp_word_read(uint32_t cell_offset); +void bsp_otp_read(uint32_t * p_data, uint32_t cell_offset, uint32_t num_words); +uint32_t bsp_otp_word_prog(uint32_t data, uint32_t cell_offset); +void bsp_otp_prog(const uint32_t * p_data, uint32_t cell_offset, uint32_t num_words); +bool bsp_otp_prog_and_verify(const uint32_t * p_data, uint32_t cell_offset, uint32_t num_words); +uint32_t bsp_otp_lock(uint8_t cell_region); +uint32_t bsp_otp_get_lock_region(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_override.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_override.h new file mode 100644 index 000000000000..2fc00aee4a43 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_override.h @@ -0,0 +1,178 @@ +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ +#define BSP_OVERRIDE_TIMER_MODE_T +#define BSP_OVERRIDE_TIMER_EVENT_T +#define BSP_OVERRIDE_TIMER_SOURCE_DIV_T + +// #define BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T +#define BSP_OVERRIDE_LPM_DEEP_STANDBY_WAKE_SOURCE_T +#define BSP_OVERRIDE_LPM_SNOOZE_REQUEST_T +#define BSP_OVERRIDE_LPM_SNOOZE_END_T +#define BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T +#define BSP_OVERRIDE_ADC_INCLUDE + +#define BSP_OVERRIDE_ADC_EVENT_T + +/** ADC callback event definitions */ +typedef enum e_adc_event +{ + ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_C, ///< Group C scan complete + ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete + ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete + ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested + ADC_EVENT_CONVERSION_ERROR, ///< Scan error + ADC_EVENT_OVERFLOW, ///< Overflow occurred + ADC_EVENT_LIMIT_CLIP, ///< Limiter clipping occurred + ADC_EVENT_FIFO_READ_REQUEST, ///< FIFO read requested + ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred + ADC_EVENT_THD_UNDER, ///< Conversion result was below the threshold + ADC_EVENT_THD_OVER, ///< Conversion result exceeded the threshold +} adc_event_t; + +#define BSP_OVERRIDE_ADC_RESOLUTION_T + +/** ADC data resolution definitions */ +typedef enum e_adc_resolution +{ + ADC_RESOLUTION_12_BIT = 0, ///< 12 bit resolution + ADC_RESOLUTION_10_BIT = 1, ///< 10 bit resolution + ADC_RESOLUTION_7_BIT = 2, ///< 7 bit resolution + ADC_RESOLUTION_4_BIT = 3, ///< 4 bit resolution +} adc_resolution_t; + +#define BSP_OVERRIDE_ADC_INFO_T + +/** ADC Information Structure for Transfer Interface */ +typedef struct st_adc_info +{ + void * p_address; ///< The address to start reading the data from + uint32_t length; ///< The total number of transfers to read +} adc_info_t; + +#define BSP_OVERRIDE_WDT_TIMEOUT_T + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Options to configure pin functions */ +typedef enum e_gpio_w_cfg_options +{ + /* PUPD */ + GPIO_W_CFG_PERIPHERAL_PIN = 0x00000000, ///< Enables pin to operate as a peripheral pin + GPIO_W_CFG_PULLDOWN_ENABLE = 0x00000200, ///< Enables pull down + GPIO_W_CFG_PULLUP_ENABLE = 0x00000100, ///< Enables pull up + GPIO_W_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input + GPIO_W_CFG_PORT_DIRECTION_OUTPUT = 0x00000300, ///< Sets the pin direction to output + + /* PPOD */ + GPIO_W_CFG_OPEN_DRAIN_ENABLE = 0x00000700, ///< Enables open-drain output + + /* PAD input selection */ + GPIO_W_CFG_SCHMITT_TRIG_ENABLE = 0x00000800, ///< Enables Schmitt trigger for input pin + + /* Drive Strength */ + GPIO_W_CFG_DRV_2mA = 0x00000000, ///< 2mA + GPIO_W_CFG_DRV_4mA = 0x00001000, ///< 4mA + GPIO_W_CFG_DRV_8mA = 0x00002000, ///< 8mA + GPIO_W_CFG_DRV_14mA = 0x00003000, ///< 14mA + + /* Standard PAD slew rate control */ + GPIO_W_CFG_SLW_FAST = 0x00000000, ///< Fast + GPIO_W_CFG_SLW_SLOW = 0x00004000, ///< Slow + + /* Standard PAD Parametric Output control, parametric inverted data */ + + // TIN-TODO: Most probably the name of this field was copy pasted from the corresponding RA enum & needs to be changed to match the actual functionality of the corresponding register field. + GPIO_W_CFG_ANALOG_ENABLE = 0x00008000, ///< Enabled + + /* PIN LEVEL */ + GPIO_W_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + GPIO_W_CFG_PORT_OUTPUT_HIGH = 0x00400000, ///< Sets the pin level to high + + /* GPIO CFG */ + GPIO_W_CFG_RETENTION = 0x20000000, ///< The pin should not float during sleep + GPIO_W_CFG_IRQ_ENABLE = 0x40000000, ///< Enables IRQ +} gpio_w_cfg_options_t; + +typedef uint32_t wdt_timeout_t; + +/** Timer operational modes */ +typedef enum e_timer_mode +{ + TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses. + TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses. + TIMER_MODE_PWM, ///< Timer generates square-wave PWM output. + TIMER_MODE_EDGE_DETECT, ///< Timer asynchronously counting up edges. +} timer_mode_t; + +/** Events that can trigger a callback function */ +typedef enum e_timer_event +{ + TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around + TIMER_EVENT_PULSE_CNT_CYCLE_END, ///< Requested number of pulses were triggered + TIMER_EVENT_SEQUENTIAL_CAPTURE_CYCLE_END, ///< Requested number of captures were triggered + TIMER_EVENT_OVERFLOW, ///< Timer overflow event (counter reached 32-bit value) + TIMER_EVENT_UNDERFLOW, ///< Timer underflow event (counter went under zero (0) value) + TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A + TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B + TIMER_EVENT_CAPTURE_C, ///< A capture has occurred on signal C + TIMER_EVENT_CAPTURE_D, ///< A capture has occurred on signal D + TIMER_EVENT_CAPTURE_E, ///< A capture has occurred on signal E + TIMER_EVENT_CAPTURE_F, ///< A capture has occurred on signal F + TIMER_EVENT_CAPTURE_G, ///< A capture has occurred on signal G + TIMER_EVENT_CAPTURE_H, ///< A capture has occurred on signal H + TIMER_EVENT_COMPARE_A, ///< A compare has occurred on signal A + TIMER_EVENT_COMPARE_B, ///< A compare has occurred on signal B + TIMER_EVENT_COMPARE_C, ///< A compare has occurred on signal C + TIMER_EVENT_COMPARE_D, ///< A compare has occurred on signal D + TIMER_EVENT_COMPARE_E, ///< A compare has occurred on signal E + TIMER_EVENT_COMPARE_F, ///< A compare has occurred on signal F + TIMER_EVENT_COMPARE_G, ///< A compare has occurred on signal G + TIMER_EVENT_COMPARE_H, ///< A compare has occurred on signal H +} timer_event_t; + +typedef enum e_timer_source_div +{ + TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 + TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2 + TIMER_SOURCE_DIV_3 = 2, ///< Timer clock source divided by 3 + TIMER_SOURCE_DIV_4 = 3, ///< Timer clock source divided by 4 + TIMER_SOURCE_DIV_5 = 4, ///< Timer clock source divided by 5 + TIMER_SOURCE_DIV_6 = 5, ///< Timer clock source divided by 6 + TIMER_SOURCE_DIV_7 = 6, ///< Timer clock source divided by 7 + TIMER_SOURCE_DIV_8 = 7, ///< Timer clock source divided by 8 + TIMER_SOURCE_DIV_9 = 8, ///< Timer clock source divided by 9 + TIMER_SOURCE_DIV_10 = 9, ///< Timer clock source divided by 10 + TIMER_SOURCE_DIV_11 = 10, ///< Timer clock source divided by 11 + TIMER_SOURCE_DIV_12 = 11, ///< Timer clock source divided by 12 + TIMER_SOURCE_DIV_13 = 12, ///< Timer clock source divided by 13 + TIMER_SOURCE_DIV_14 = 13, ///< Timer clock source divided by 14 + TIMER_SOURCE_DIV_15 = 14, ///< Timer clock source divided by 15 + TIMER_SOURCE_DIV_16 = 15, ///< Timer clock source divided by 16 + TIMER_SOURCE_DIV_17 = 16, ///< Timer clock source divided by 17 + TIMER_SOURCE_DIV_18 = 17, ///< Timer clock source divided by 18 + TIMER_SOURCE_DIV_19 = 18, ///< Timer clock source divided by 19 + TIMER_SOURCE_DIV_20 = 19, ///< Timer clock source divided by 20 + TIMER_SOURCE_DIV_21 = 20, ///< Timer clock source divided by 21 + TIMER_SOURCE_DIV_22 = 21, ///< Timer clock source divided by 22 + TIMER_SOURCE_DIV_23 = 22, ///< Timer clock source divided by 23 + TIMER_SOURCE_DIV_24 = 23, ///< Timer clock source divided by 24 + TIMER_SOURCE_DIV_25 = 24, ///< Timer clock source divided by 25 + TIMER_SOURCE_DIV_26 = 25, ///< Timer clock source divided by 26 + TIMER_SOURCE_DIV_27 = 26, ///< Timer clock source divided by 27 + TIMER_SOURCE_DIV_28 = 27, ///< Timer clock source divided by 28 + TIMER_SOURCE_DIV_29 = 28, ///< Timer clock source divided by 29 + TIMER_SOURCE_DIV_30 = 29, ///< Timer clock source divided by 30 + TIMER_SOURCE_DIV_31 = 30, ///< Timer clock source divided by 31 + TIMER_SOURCE_DIV_32 = 31, ///< Timer clock source divided by 32 +} timer_source_div_t; +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.c new file mode 100644 index 000000000000..92857531d07d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.c @@ -0,0 +1,493 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_pd.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* System Wakeup Source */ +uint32_t SystemCoreWakeupSource BSP_SECTION_EARLY_INIT; + +/* System Wakeup Pin */ +uint32_t SystemCoreWakeupSourcePin BSP_SECTION_EARLY_INIT; + +/* RTC Brown-out and Black-out callback types */ +BSP_RTC_BOD_CALLBACK_TYPE bsp_rtc_brown_callback, bsp_rtc_black_callback; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void RTC_IF_BLACK_Handler(void); +void RTC_IF_BROWN_Handler(void); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** + * @brief Get the SLEEP/IS_UP register-field masks of a power domain. + * + * @param [in] power_domain power domain + * @param [out] sleep_mask mask for the power domain's SLEEP status bit + * @param [out] is_up_mask mask for the power domain's IS_UP status bit + * + * @note If \p power_domain is invalid, 0 is returned for both masks + */ +void bsp_prv_pd_masks_get (bsp_power_domain_t power_domain, uint32_t * sleep_mask, uint32_t * is_up_mask) +{ + switch (power_domain) + { + case BSP_PD_PHY: + { + *sleep_mask = CRG_TOP_PMU_CTRL_REG_PHY_SLEEP_Msk; + *is_up_mask = CRG_TOP_SYS_STATUS_REG_PHY_IS_UP_Msk; + break; + } + + case BSP_PD_MAC: + { + *sleep_mask = CRG_TOP_PMU_CTRL_REG_MAC_SLEEP_Msk; + *is_up_mask = CRG_TOP_SYS_STATUS_REG_MAC_IS_UP_Msk; + break; + } + + default: + { + *sleep_mask = 0; + *is_up_mask = 0; + break; + } + } +} + +/*******************************************************************************************************************//** + * Updates the SystemCoreWakeupSource and SystemCoreWakeupSourcePin variables based on the current state + * of the RTC registers. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void SystemWakeupSourceUpdate (void) +{ + SystemCoreWakeupSource = 0; + SystemCoreWakeupSource = RTC->WAKEUP_SRC_CLR_SIG_REG & 0x7f; + + /* Clear wakeup source */ + RTC->DCDC_CNTL_OFF_REG_b.DCDC_PWR_OFF = 0; + RTC->ENABLE_CTRL_REG_b.SLEEP3_EN = 0; + RTC->ENABLE_CTRL_REG_b.WATCHDOG_OUT_INT_EN = 0; + + if (SystemCoreWakeupSource & 0x30) + { + SystemCoreWakeupSource = (SystemCoreWakeupSource & ~(0x30U)) | BSP_WAKEUP_SOURCE_SENSOR; + } + + SystemCoreWakeupSource |= (RTC->RTM_CONTROL_REG_b.RTM_INFO << 7); + + if (SystemCoreWakeupSource & BSP_WAKEUP_SOURCE_POR) + { + if (!bsp_is_chip_revision_a()) + { + RTC->LDO_ENABLE_REG_b.CTRL_ST_PA_DCDC = 0x18; + } + + SystemCoreWakeupSource = BSP_WAKEUP_SOURCE_POR; + } + + SystemCoreWakeupSourcePin = 0; + SystemCoreWakeupSourcePin = RTC->GPIO_WAKEUP1_REG_b.GPIO_WAKEUP_SRC; +} + +/*******************************************************************************************************************//** + * Gets the wakeup source stored in the SystemCoreWakeupSource variable. + * + * @return The wakeup source. + * + * @note Since the wakeup source may change after booting, the value is stored in SystemCoreWakeupSource during the + * initialization process (through SystemWakeupSourceUpdate), and it is checked as a static value. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM bsp_wakeup_source_mask_t R_BSP_WakeupSourceGet (void) +{ + return (bsp_wakeup_source_mask_t) SystemCoreWakeupSource; +} + +/*******************************************************************************************************************//** + * Clears the specified wakeup source. + * + * @param[in] clear Boolean indicating whether to clear the wakeup source. + **********************************************************************************************************************/ +void R_BSP_WakeupSourceClear (bool clear) +{ + uint32_t regtemp = 0xFE; + if (clear) + { + RTC->WAKEUP_SRC_CLR_SIG_REG = regtemp; + } + + RTC->ENABLE_CTRL_REG &= ~(RTC_ENABLE_CTRL_REG_SLEEP3_EN_Msk | RTC_ENABLE_CTRL_REG_WATCHDOG_OUT_INT_EN_Msk); + RTC->DCDC_CNTL_OFF_REG &= ~(RTC_DCDC_CNTL_OFF_REG_DCDC_PWR_OFF_Msk); +} + +/*******************************************************************************************************************//** + * Gets the wakeup source pin mask stored in the SystemCoreWakeupSourcePin variable. + * + * @return The wakeup pin mask. + * + * @note Since the wakeup pin may change after booting, the value is stored in SystemCoreWakeupSourcePin during the + * initialization process (through SystemWakeupSourceUpdate), and it is checked as a static value. + **********************************************************************************************************************/ +bsp_io_wakeup_pin_t R_BSP_WakeupSourcePinGet (void) +{ + return (bsp_io_wakeup_pin_t) SystemCoreWakeupSourcePin; +} + +/*******************************************************************************************************************//** + * Clears the wakeup source pin mask. + **********************************************************************************************************************/ +void R_BSP_WakeupSourcePinClear (void) +{ + RTC->WAKEUP_SRC_CLR_SIG_REG_b.GPIO_WAKE_UP_DETECT = 1; +} + +/*******************************************************************************************************************//** + * Sets the specified GPIO pin as a wakeup source. + * + * @param[in] pin The GPIO pin to set as a wakeup source. + * @param[in] edge The edge type (active high or active low) for the wakeup source. + **********************************************************************************************************************/ +void R_BSP_WakeupSourcePinSet (bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge) +{ + uint32_t temp; + temp = RTC->GPIO_WAKEUP1_REG_b.GPIO_WAKEUP_EN_SEL; + temp |= pin; + RTC->GPIO_WAKEUP1_REG_b.GPIO_WAKEUP_EN_SEL = temp & 0x7FFU; + + temp = RTC->GPIO_WAKEUP0_REG_b.GPIO_WAKEUP_EDGE_INVERSION_SEL; + temp &= ~pin; + temp |= (edge == 0) ? pin : 0; + RTC->GPIO_WAKEUP0_REG_b.GPIO_WAKEUP_EDGE_INVERSION_SEL = temp & 0x7FFU; +} + +/*******************************************************************************************************************//** + * Sets the specified GPIO pin as a wakeup source. + * + * @param[in] pin The GPIO pin to set as a wakeup source. + * @param[in] edge The edge type (active high or active low) for the wakeup source. + **********************************************************************************************************************/ +void R_BSP_WakeupSourcePinSetRetained (bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge) +{ + bsp_io_port_pin_t port_pin = bsp_prv_wakeup_pin_to_port_pin(pin); + R_BSP_RetainedIoSet(port_pin); + R_BSP_WakeupSourcePinSet(pin, edge); +} + +/*******************************************************************************************************************//** + * Unsets the specified GPIO pin as a wakeup source. + * + * @param[in] pin The GPIO pin to unset as a wakeup source. + **********************************************************************************************************************/ +void R_BSP_WakeupSourcePinUnSet (bsp_io_wakeup_pin_t pin) +{ + uint32_t temp; + temp = RTC->GPIO_WAKEUP1_REG_b.GPIO_WAKEUP_EN_SEL; + temp &= ~pin; + RTC->GPIO_WAKEUP1_REG_b.GPIO_WAKEUP_EN_SEL = temp & 0x7FFU; +} + +/*******************************************************************************************************************//** + * @brief Convert PORT_PIN to WAKEUP_GPIO + * + * @param[in] port_pin bsp_io_port_pin_t + * + * @return bsp_io_wakeup_pin_t + **********************************************************************************************************************/ +bsp_io_wakeup_pin_t bsp_prv_port_pin_to_wakeup_gpio (bsp_io_port_pin_t port_pin) +{ + if (port_pin == BSP_IO_PORT_00_PIN_00) + { + return BSP_WAKEUP_GPIO_P0_00; + } + else if (port_pin == BSP_IO_PORT_00_PIN_08) + { + return BSP_WAKEUP_GPIO_P0_08; + } + else if (port_pin == BSP_IO_PORT_00_PIN_09) + { + return BSP_WAKEUP_GPIO_P0_09; + } + else if (port_pin == BSP_IO_PORT_00_PIN_10) + { + return BSP_WAKEUP_GPIO_P0_10; + } + else if (port_pin == BSP_IO_PORT_00_PIN_11) + { + return BSP_WAKEUP_GPIO_P0_11; + } + else if (port_pin == BSP_IO_PORT_00_PIN_12) + { + return BSP_WAKEUP_GPIO_P0_12; + } + else if (port_pin == BSP_IO_PORT_00_PIN_13) + { + return BSP_WAKEUP_GPIO_P0_13; + } + else if (port_pin == BSP_IO_PORT_01_PIN_10) + { + return BSP_WAKEUP_GPIO_P1_10; + } + else if (port_pin == BSP_IO_PORT_01_PIN_11) + { + return BSP_WAKEUP_GPIO_P1_11; + } + else if (port_pin == BSP_IO_PORT_01_PIN_12) + { + return BSP_WAKEUP_GPIO_P1_12; + } + else if (port_pin == BSP_IO_PORT_01_PIN_13) + { + return BSP_WAKEUP_GPIO_P1_13; + } + else + { + return 0; + } +} + +/*******************************************************************************************************************//** + * @brief Convert WAKEUP_GPIO to PORT_PIN + * + * @param[in] wakeup_gpio bsp_io_wakeup_pin_t + * + * @return bsp_io_port_pin_t + **********************************************************************************************************************/ +bsp_io_port_pin_t bsp_prv_wakeup_pin_to_port_pin (bsp_io_wakeup_pin_t wakeup_gpio) +{ + if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_00) + { + return BSP_IO_PORT_00_PIN_00; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_08) + { + return BSP_IO_PORT_00_PIN_08; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_09) + { + return BSP_IO_PORT_00_PIN_09; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_10) + { + return BSP_IO_PORT_00_PIN_10; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_11) + { + return BSP_IO_PORT_00_PIN_11; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_12) + { + return BSP_IO_PORT_00_PIN_12; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P0_13) + { + return BSP_IO_PORT_00_PIN_13; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P1_10) + { + return BSP_IO_PORT_01_PIN_10; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P1_11) + { + return BSP_IO_PORT_01_PIN_11; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P1_12) + { + return BSP_IO_PORT_01_PIN_12; + } + else if (wakeup_gpio == BSP_WAKEUP_GPIO_P1_13) + { + return BSP_IO_PORT_01_PIN_13; + } + else + { + return BSP_IO_PORT_FF_PIN_FF; + } +} + +/*******************************************************************************************************************//** + * Sets the retention flag in the RTC register to indicate that retention memory is being used. + * + * @note During sleep, the RTC register is always on. The software records the status in the RTM_INFO register to + * indicate whether retention memory is being used. When reading the wakeup source, set RTM_INFO to bit 7 to + * check this. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void R_BSP_RetainedMemFlagSet (void) +{ + RTC->RTM_CONTROL_REG_b.RTM_INFO = 1; +} + +/*******************************************************************************************************************//** + * Clears the retention memory flag in the RTC register. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void R_BSP_RetainedMemFlagClear (void) +{ + RTC->RTM_CONTROL_REG_b.RTM_INFO = 0; +} + +/*******************************************************************************************************************//** + * Gets the retention memory flag. + * + * @return The retention memory flag. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM uint32_t R_BSP_RetainedMemFlagGet (void) +{ + return RTC->RTM_CONTROL_REG_b.RTM_INFO; +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * @brief Gets the sleep ID used when the system enters sleep mode. + * + * @return The sleep ID. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM uint32_t bsp_prv_pd_sleep_id_get (void) +{ + return RTC->RTM_CONTROL_REG_b.RTM_CTRL_PWR_DN_INFO; +} + +/*******************************************************************************************************************//** + * Sets the target wakeup time and sleep ID. + * + * @param[in] sleep_id The sleep ID for which to set the wakeup time. + * @param[in] wakeup_time The target wakeup time. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void bsp_prv_pd_wakeup_counter_set (uint32_t sleep_id, uint64_t wakeup_time) +{ + RTC->RTM_CONTROL_REG_b.RTM_CTRL_PWR_DN_INFO = sleep_id & 0xf; + RTC->WAKEUP_CNT_1_REG_b.WAKEUP_CNT_1 = (uint32_t) (wakeup_time >> 32) & 0xf; + RTC->WAKEUP_CNT_0_REG_b.WAKEUP_CNT_0 = (uint32_t) (wakeup_time) & 0xffffffff; +} + +/*******************************************************************************************************************//** + * Gets the current value of the wake-up counter, which operates at 32kHz. + * + * @return The current wakeup time, represented as a 64-bit value. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM uint64_t bsp_prv_pd_wakeup_counter_get (void) +{ + uint64_t ret_time; + uint32_t * pret_time = (uint32_t *) &ret_time; + uint32_t temp1, temp2; + + /* Read wakeup counter */ + temp2 = RTC->WAKEUP_CNT_0_REG; + temp1 = RTC->WAKEUP_CNT_1_REG & 0x0f; + + memcpy(pret_time, &temp2, 4); + memcpy(pret_time + 1, &temp1, 4); + + return ret_time; +} + +/*******************************************************************************************************************//** + * @brief Enable RTC brown-out and black-out detection. + * + * This function enables the RTC brown-out and black-out detection circuits and sets the corresponding callback functions. + * + * @param[in] brown_callback The callback function to be called on a brown-out event. + * @param[in] black_callback The callback function to be called on a black-out event. + **********************************************************************************************************************/ +void bsp_rtc_enable_bod (BSP_RTC_BOD_CALLBACK_TYPE brown_callback, BSP_RTC_BOD_CALLBACK_TYPE black_callback) +{ + FSP_PARAMETER_NOT_USED(brown_callback); + FSP_PARAMETER_NOT_USED(black_callback); +#if BSP_DEVICE_REVISION == DEVICE_REV_A + if (brown_callback) + { + bsp_rtc_brown_callback = brown_callback; + } + + if (black_callback) + { + bsp_rtc_black_callback = black_callback; + } + + NVIC_EnableIRQ(RTC_IF_BROWN_IRQn); + NVIC_EnableIRQ(RTC_IF_BLACK_IRQn); + + RTC->BOR_CIRCUIT_REG_b.BR_OUT_CTRL = 0x05; + RTC->BOR_CIRCUIT_REG_b.BL_OUT_CTRL = 0x04; + + RTC->BOR_CIRCUIT_REG_b.BR_OUT_EN = 0x01; + RTC->BOR_CIRCUIT_REG_b.BL_OUT_EN = 0x01; + + RTC->ENABLE_CTRL_REG_b.BROWN_OUT_INT_EN = 0x01; + RTC->ENABLE_CTRL_REG_b.BLACK_OUT_INT_EN = 0x01; +#endif +} + +/*******************************************************************************************************************//** + * @brief Disable RTC brown-out and black-out detection. + * + * This function disables the RTC brown-out and black-out detection circuits. + **********************************************************************************************************************/ +void bsp_rtc_disable_bod (void) +{ + NVIC_DisableIRQ(RTC_IF_BROWN_IRQn); + NVIC_DisableIRQ(RTC_IF_BLACK_IRQn); + + RTC->BOR_CIRCUIT_REG_b.BR_OUT_EN = 0x00; + RTC->BOR_CIRCUIT_REG_b.BL_OUT_EN = 0x00; +} + +/*******************************************************************************************************************//** + * @brief Get the brown-out status. + * + * This function returns the current status of the brown-out detection circuit. + * + * @return The brown-out status. + **********************************************************************************************************************/ +int bsp_rtc_get_brown_out_status (void) +{ + return (int) RTC->BOR_CIRCUIT_REG_b.BR_STATUS_READ; +} + +/*******************************************************************************************************************//** + * @brief RTC black-out interrupt handler. + * + * This function is the interrupt handler for the RTC black-out event. It calls the registered black-out callback function. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void RTC_IF_BLACK_Handler (void) +{ + if (bsp_rtc_black_callback) + { + bsp_rtc_black_callback(); + } +} + +/*******************************************************************************************************************//** + * @brief RTC brown-out interrupt handler. + * + * This function is the interrupt handler for the RTC brown-out event. It calls the registered brown-out callback function. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM void RTC_IF_BROWN_Handler (void) +{ + if (bsp_rtc_brown_callback) + { + bsp_rtc_brown_callback(); + } +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.h new file mode 100644 index 000000000000..d012f645a548 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_pd.h @@ -0,0 +1,229 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_PD_RA6W1_H +#define BSP_PD_RA6W1_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_rtc.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** + * Number of Power Domain IDs defined for this device + */ +#define BSP_PD_ID_COUNT (3) + +/* For retention memory bank*/ +#define RETENTION_MEM_NONE 0x00 +#define RETENTION_MEM_BANK0 0x01 // 0x00180000 ~ 0x00181fff +#define RETENTION_MEM_BANK1 0x02 // 0x00182000 ~ 0x00184000 +#define RETENTION_MEM_BANK2 0x04 // 0x00184000 ~ +#define RETENTION_MEM_BANK_ALL 0x07 // All + +/* Alias name of BSP_WAKEUP_RESET_WITH_RETENTION */ +#define BSP_WAKEUP_RETENTION (BSP_WAKEUP_RESET_WITH_RETENTION) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Hardware power domains.*/ +typedef enum e_bsp_power_domain +{ + BSP_PD_AON = 0, ///< Always on power domain + BSP_PD_PHY = 1, ///< PHY power domain + BSP_PD_MAC = 2, ///< MAC power domain +} bsp_power_domain_t; + +/* Wakeup edge for individual pins */ +typedef enum e_bsp_wakeup_edge +{ + BSP_WAKEUP_EDGE_LOW = 0, ///< Low + BSP_WAKEUP_EDGE_HIGH ///< High +} bsp_io_wakeup_edge_t; + +/* Wakeup pins */ +typedef enum e_bsp_wakeup_pin +{ + BSP_WAKEUP_GPIO_P0_00 = (0x01 << 0), + BSP_WAKEUP_GPIO_P0_08 = (0x01 << 1), + BSP_WAKEUP_GPIO_P0_09 = (0x01 << 2), + BSP_WAKEUP_GPIO_P0_10 = (0x01 << 3), + BSP_WAKEUP_GPIO_P0_11 = (0x01 << 4), + BSP_WAKEUP_GPIO_P0_12 = (0x01 << 5), + BSP_WAKEUP_GPIO_P0_13 = (0x01 << 6), + BSP_WAKEUP_GPIO_P1_10 = (0x01 << 7), + BSP_WAKEUP_GPIO_P1_11 = (0x01 << 8), + BSP_WAKEUP_GPIO_P1_12 = (0x01 << 9), + BSP_WAKEUP_GPIO_P1_13 = (0x01 << 10), +} bsp_io_wakeup_pin_t; + +// TIN-TODO: This enum was located in bsp_common and guarded with the same features as the RTC function. +// Consider moving this under a header file of the power manager. + +/* + * The value below consists of a bit mask and the rest is a combination of the corresponding values. + * These values are based on RTC->WAKEUP_SRC_CLR_SIG_REG + * BSP_WAKEUP_RESET 0x00 + * BSP_WAKEUP_SOURCE_GPIO 0x01 + * BSP_WAKEUP_SOURCE_WAKEUP_COUNTER 0x02 + * BSP_WAKEUP_SOURCE_POR 0x04 + * BSP_WAKEUP_SOURCE_WATCHDOG 0x08 + * BSP_WAKEUP_SENSOR 0x10 + * BSP_WAKEUP_PULSE 0x20 + * BSP_WAKEUP_TIMER 0x40 - Only in sleep 4/5 + * + * This value is based on RTC->RTM_INFO, written by software + * BSP_WAKEUP_RESET_WITH_RETENTION 0x80 + */ +typedef enum e_bsp_wakeup_source_mask +{ + BSP_WAKEUP_RESET = 0x00, ///< Internal reset + BSP_WAKEUP_SOURCE_GPIO = 0x01, ///< Boot from GPIO wake up signal + BSP_WAKEUP_SOURCE_WAKEUP_COUNTER = 0x02, ///< Boot from wake up counter + BSP_WAKEUP_GPIO_WAKEUP_COUNTER = 0x03, ///< Boot from wake up counter or GPIO wakeup + BSP_WAKEUP_SOURCE_POR = 0x04, ///< Boot from power on reset + BSP_WAKEUP_SOURCE_POR_GPIO = 0x05, ///< FPGA only + BSP_WAKEUP_SOURCE_WATCHDOG = 0x08, ///< Boot from RTC_watch dog (not cpu watchdog) + BSP_WAKEUP_WATCHDOG_GPIO = 0x09, ///< Boot from watch dog or GPIO wakeup + BSP_WAKEUP_SOURCE_SENSOR = 0x10, ///< Boot from sensor (ADC) + BSP_WAKEUP_SOURCE_PULSE = 0x20, ///< Boot from pulse sensor + + BSP_WAKEUP_SENSOR_GPIO = 0x11, ///< Boot from sensor or GPIO wakeup + BSP_WAKEUP_SENSOR_WAKEUP_COUNTER = 0x12, ///< Boot from sensor or wakeup counter + BSP_WAKEUP_SENSOR_GPIO_COUNTER = 0x13, ///< Boot from sensor or external or wakeup counter + BSP_WAKEUP_SENSOR_WATCHDOG = 0x18, ///< Boot from sensor or RTC watch dog + BSP_WAKEUP_SENSOR_GPIO_WATCHDOG = 0x19, ///< Boot from sensor or GPIO or watch dog + BSP_WAKEUP_RESET_WITH_RETENTION = 0x80, ///< Boot from internal reset and have retention info + BSP_WAKEUP_GPIO_WITH_RETENTION = 0x81, ///< Boot from GPIO and have retention info + BSP_WAKEUP_COUNTER_WITH_RETENTION = 0x82, ///< Boot from counter and have retention info (most common) + BSP_WAKEUP_GPIO_WAKEUP_COUNTER_WITH_RETENTION = 0x83, ///< Boot from GPIO or wakeup counter with retention + BSP_WAKEUP_WATCHDOG_WITH_RETENTION = 0x88, ///< Boot from RTC watch dog with retention + BSP_WAKEUP_WATCHDOG_GPIO_WITH_RETENTION = 0x89, ///< Boot from watch dog or GPIO + BSP_WAKEUP_SENSOR_WITH_RETENTION = 0x90, ///< Boot from sensor with retention + BSP_WAKEUP_SENSOR_GPIO_WITH_RETENTION = 0x91, ///< Boot from sensor or GPIO with retention + BSP_WAKEUP_SENSOR_WAKEUP_COUNTER_WITH_RETENTION = 0x92, ///< Boot from sensor or wakeup counter with retention + BSP_WAKEUP_SENSOR_GPIO_COUNTER_WITH_RETENTION = 0x93, ///< Boot from sensor or GPIO or wakeup counter with retention + BSP_WAKEUP_SENSOR_WATCHDOG_WITH_RETENTION = 0x98, ///< Boot from sensor or watchdog with retention + BSP_WAKEUP_SENSOR_GPIO_WATCHDOG_WITH_RETENTION = 0x99, ///< Boot from sensor or GPIO or watchdog with retention + + BSP_WAKEUP_ALLTIMER_WITH_RETENTION = 0xC2, ///< Boot from rtc, hw & mac-timer and have retention info (most common) + BSP_WAKEUP_HWTIMER_WITH_RETENTION = 0xC0, ///< Boot from hw & mac-timer and have retention info (most common) + + BSP_WAKEUP_SOURCE_UNKNOWN = 0xff, +} bsp_wakeup_source_mask_t; + +typedef uint32_t bsp_wakeup_source_t; + +typedef void (* BSP_RTC_BOD_CALLBACK_TYPE)(void); + +typedef struct +{ + void (* func)(void *); + void * param; +} BSP_RTC_TIME_EXP_CALLBACK_TYPE; + +/* Wakeup edge for individual pins */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Used internaly by bsp_pd.c */ +void bsp_prv_pd_masks_get(bsp_power_domain_t power_domain, uint32_t * sleep_mask, uint32_t * is_up_mask); + +/** + * @brief Enable a power domain by clearing its sleep status bit + * + * @param [in] sleep_mask mask for the power domain's SLEEP status bit + * @param [in] is_aon whether the power domain is part of the AON domain group + * + * @note Multiple power domains may be enabled if more than one bits are set in \p sleep_mask + */ +__STATIC_INLINE void bsp_prv_pd_enable (uint32_t sleep_mask, bool is_aon) +{ + FSP_PARAMETER_NOT_USED(is_aon); + + CRG_TOP->PMU_CTRL_REG &= ~sleep_mask; +} + +/** + * @brief Disable a power domain by setting its sleep status bit + * + * @param [in] sleep_mask mask for the power domain's SLEEP status bit + * @param [in] is_aon whether the power domain is part of the AON domain group + * + * @note Multiple power domains may be disabled if more than one bits are set in \p sleep_mask + */ +__STATIC_INLINE void bsp_prv_pd_disable (uint32_t sleep_mask, bool is_aon) +{ + FSP_PARAMETER_NOT_USED(is_aon); + CRG_TOP->PMU_CTRL_REG |= sleep_mask; +} + +/** + * @brief Check if a power domain by checking its is-up status bit + * + * @param [in] is_up_mask mask for the power domain's IS_UP status bit + * + * @return True iff the power domains corresponding to the set bits in \p is_up_mask are up. + * + * @note Multiple power domains may be checked if more than one bits are set in \p is_up_mask + */ +__STATIC_INLINE bool bsp_prv_pd_is_up_check (uint32_t is_up_mask) +{ + return (CRG_TOP->SYS_STATUS_REG & is_up_mask) == is_up_mask; +} + +bsp_wakeup_source_mask_t R_BSP_WakeupSourceGet(void); + +void SystemWakeupSourceUpdate(void); +void R_BSP_WakeupSourceClear(bool clear); + +bsp_io_wakeup_pin_t bsp_prv_port_pin_to_wakeup_gpio(bsp_io_port_pin_t port_pin); +bsp_io_port_pin_t bsp_prv_wakeup_pin_to_port_pin(bsp_io_wakeup_pin_t wakeup_gpio); +bsp_io_wakeup_pin_t R_BSP_WakeupSourcePinGet(void); +void R_BSP_WakeupSourcePinClear(void); +void R_BSP_WakeupSourcePinSet(bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge); +void R_BSP_WakeupSourcePinSetRetained(bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge); +void R_BSP_WakeupSourcePinUnSet(bsp_io_wakeup_pin_t pin); + +void R_BSP_RetainedMemFlagSet(void); +void R_BSP_RetainedMemFlagClear(void); +uint32_t R_BSP_RetainedMemFlagGet(void); + +void bsp_prv_pd_wakeup_counter_set(uint32_t sleep_id, uint64_t wakeup_time); +uint64_t bsp_prv_pd_wakeup_counter_get(void); +uint32_t bsp_prv_pd_sleep_id_get(void); + +void bsp_rtc_enable_bod(BSP_RTC_BOD_CALLBACK_TYPE brown_callback, BSP_RTC_BOD_CALLBACK_TYPE black_callback); +void bsp_rtc_disable_bod(void); +int bsp_rtc_get_brown_out_status(void); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.c new file mode 100644 index 000000000000..d3b97e5748d1 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.c @@ -0,0 +1,208 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include +#include + +#include "bsp_api.h" +#include "bsp_rand.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +uint32_t prng_rand (void) +{ + uint32_t old_value, new_value; + + HW_ACC->PRNG_OP_EN_REG = 1U; + old_value = HW_ACC->PRNG_REG_CAL_VAL; + + do + { + HW_ACC->PRNG_REQ_CLR_REG = HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_GET_Msk; + new_value = HW_ACC->PRNG_REG_CAL_VAL; + + if ((new_value == 0) && (old_value == 0)) + { + /* Sometimes we hang indefinitely in this do-while loop (new_value is always zero, just as old_value). + * It is reproducible without critical sections for a sequence like: + * + * srand(rand()); + * rand(); + * + * It seems to be a HW design issue. This workaround solves it as far as I can test. + * PRNG has not been revised, so it should behave in the same way for both AA and BA hardware revisions. + * Note: adding busy-wait loops before/after rand()/srand() doesn't seem to help.. + * TODO: + * - How can we confirm that previous PRNG operation is finished and we can issue next one? + */ + HW_ACC->PRNG_REQ_CLR_REG = HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_CLR_Msk; + } + } while (new_value == old_value); + + HW_ACC->PRNG_OP_EN_REG = 0; + + return new_value; +} + +uint32_t trng_rand(void) +{ + uint32_t val = 0; + + if (!trng_init_regs()) + { + return 0; + } + + for (int tries = 0; tries < TRNG_RETRY_LIMIT; tries++) + { + if (trng_is_valid()) + { + /* Clear up the interrupt status register */ + CC312->CC312_RNG_ICR_REG = ~0UL; + val = CC312->CC312_EHR_DATA_0_REG; + goto out; + } + + /* Clear interrupt/status and try again */ + CC312->CC312_RNG_ICR_REG = ~0UL; + } + +out: + + /* Disable signal for the random source */ + CC312->CC312_RND_SOURCE_ENABLE_REG = 0; + + /* Disable the HW RNG clock */ + CC312->CC312_RNG_CLK_ENABLE_REG = 0; + + return val; +} + +bool trng_init_regs (void) +{ + int poll_retry_limit = 0; + + /* Reset the RNG block */ + CC312->CC312_RNG_SW_RESET_REG = 0x1; + + do + { + /* enable the HW RNG clock */ + CC312->CC312_RNG_CLK_ENABLE_REG = 1; + + /* Set the number of rng_clk cycles between two consecutive samples. + * If the Von-Neumann is bypassed, the minimum value for sample counter + * must not be less than decimal seventeen - set to 20 dec + */ + CC312->CC312_SAMPLE_CNT1_REG = TRNG_DEF_SAMPLES_CNT; + + if (++poll_retry_limit == TRNG_REG_POLL_RETRY_LIMIT) + { + return false; + } + + /* Enable the HW RNG clock and set sample counter value until it is set correctly */ + } while (CC312->CC312_SAMPLE_CNT1_REG != TRNG_DEF_SAMPLES_CNT); + + /* Set the length of the oscillator ring to longest possible length - 3 */ + CC312->CC312_TRNG_CONFIG_REG_b.CC312_RND_SRC_SEL = 3; + + /* Bypass auto correlate, VNC and CRNGT are not bypassed and kept activated */ + CC312->CC312_TRNG_DEBUG_CONTROL_REG_b.CC312_VNC_BYPASS = 1; + CC312->CC312_TRNG_DEBUG_CONTROL_REG_b.CC312_TRNG_CRNGT_BYPASS = 0; + CC312->CC312_TRNG_DEBUG_CONTROL_REG_b.CC312_AUTO_CORRELATE_BYPASS = 1; + + /* Enable signal for the random source */ + CC312->CC312_RND_SOURCE_ENABLE_REG = 1; + + return true; +} + +bool trng_is_valid (void) +{ + int poll_retry_limit = 0; + + while ((CC312->CC312_TRNG_VALID_REG != 1) && + (CC312->CC312_RNG_ISR_REG_b.CC312_RNG_ISR_EHR_VALID != 1)) + { + if (++poll_retry_limit == TRNG_REG_POLL_RETRY_LIMIT) + { + return false; + } + } + + if (CC312->CC312_RNG_ISR_REG_b.CC312_RNG_ISR_AUTOCORR_ERR != 0) + { + return false; + } + + poll_retry_limit = 0; + + while ((CC312->CC312_EHR_DATA_0_REG == 0x0) || (CC312->CC312_EHR_DATA_0_REG == 0x80000000)) + { + if (++poll_retry_limit == TRNG_REG_POLL_RETRY_LIMIT) + { + return false; + } + } + + return true; +} + +/*******************************************************************************************************************//** + * Implementation of srand() function from standard C library. + * + * @param[in] seed A seed value to use for a new sequence of pseudo-random integers to be returned by rand(). These + * sequences are repeatable by calling srand() with the same seed value. + * + * @note RA6W1 PRNG is using polynomial calculation, which is similar to CRC. Providing the same seed to PRNG after POR + * boot (not SW reset), results in PRNG generating a deterministic sequence (the same pattern). However PRNG seed + * is designed to accumulate the current calculation without resetting the poly calculation. Hence to implement + * proper standard C library srand() semantics, need to use hardware CRC/SHA/AES instead of PRNG. + **********************************************************************************************************************/ +void srand (unsigned seed) +{ + uint32_t prng_seed = (uint32_t) seed & HW_ACC_PRNG_SEED_REG_PRNG_SEED_VAL_Msk; + + /* Seeding prng with a 0 not allowed because: + * - causes constant 0 output from prng + * - causes infinite loop in prng_rand() due to constant 0 output + */ + if (prng_seed == 0U) + { + prng_seed = 1U; + } + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + HW_ACC->PRNG_OP_EN_REG = 1U; + HW_ACC->PRNG_PAR_TYPE_REG = PRNG_PAR_TYPE_32_BITS; + HW_ACC->PRNG_SEED_REG = prng_seed; + HW_ACC->PRNG_REQ_CLR_REG = HW_ACC_PRNG_REQ_CLR_REG_PRNG_REQ_CLR_Msk; + HW_ACC->PRNG_OP_EN_REG = 0U; + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Implementation of rand() function from standard C library. + * + * @retval a pseudo-random integer in the range 0 to RAND_MAX inclusive. + * @note This function is not reentrant. + **********************************************************************************************************************/ +int rand (void) +{ + return (int) (prng_rand() % (((uint32_t) RAND_MAX) + 1U)); +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.h new file mode 100644 index 000000000000..a3f362a867d9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rand.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_RAND_RA6W1_H +#define BSP_RAND_RA6W1_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define PRNG_PAR_TYPE_32_BITS (2U) +#define TRNG_DEF_SAMPLES_CNT 0X14 +#define TRNG_REG_POLL_RETRY_LIMIT 10000 +#define TRNG_RETRY_LIMIT 8 + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +bool trng_init_regs(void); +bool trng_is_valid(void); +uint32_t prng_rand(void); +uint32_t trng_rand(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtc.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtc.h new file mode 100644 index 000000000000..0750f0a54077 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtc.h @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_RTC_RA6W1_H +#define BSP_RTC_RA6W1_H + +#include "bsp_api.h" +#ifdef UNIT_TESTING + #include "fake_regs.h" +#endif +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_RTC_CLOCK_TO_SEC(clk) (((unsigned long long) clk) >> 15ULL) +#define __uptime() BSP_PRV_RTC_CLOCK_TO_SEC(R_BSP_SystemRtcCountGet()) // Get elapsed time after system power up(for 64bit) + +// TIN-TODO: This macro was located in bsp_common and guarded with the same features as the RTC function. +// Consider moving this under a header file of the power manager. + +/* Alias name of BSP_WAKEUP_RESET_WITH_RETENTION */ +#define BSP_WAKEUP_RETENTION (BSP_WAKEUP_RESET_WITH_RETENTION) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Gets the clock count of RTC. + * + * @return The value of the RTC free running counter. + **********************************************************************************************************************/ +static inline uint64_t R_BSP_SystemRtcCountGet (void) +{ + volatile uint64_t ret_time = 0; + + /* Check RTC register mirror done */ + if (RTC->RTC_IRQ_STATUS_REG_b.RTC_IRQ_STATUS == 0x01) + { + /* faster to access register on rtc thourgh mirror.*/ + ret_time |= RTC->RTC_MR_FRC0_REG; + ret_time |= (uint64_t) (RTC->RTC_MR_FRC1_REG) << 32; + } + else + { + /* direct to access register on rtc */ + ret_time |= RTC->FRC_CNT_0_REG; + ret_time |= (uint64_t) RTC->FRC_CNT_1_REG << 32; + } + + return ret_time; +} + +/*******************************************************************************************************************//** + * Calculate difference between two RTC values. Both values are assumed to be 36 bits wide. + * + * @param [in] from The first 36-bit value. + * @param [in] to The second 36-bit value. + * + * @return The RTC difference between the two values. + **********************************************************************************************************************/ +static inline uint64_t R_BSP_SystemRtcDiff (uint64_t from, uint64_t to) +{ + const int64_t full_range = (1LL << 36); + const int64_t half_range = full_range >> 1; + const int64_t diff = (int64_t) to - (int64_t) from; + + if (diff >= 0) + { + /* 'from' comes after 'to', but it wrapped : 'to' comes after 'from', no wrapping */ + return diff >= half_range ? 0 : (uint64_t) (diff); + } + else + { + /* 'from' comes after 'to', no wrapping : 'to' comes after 'from', but it wrapped */ + return diff >= -half_range ? 0 : (uint64_t) (diff + full_range); + } +} + +/*******************************************************************************************************************//** + * Busy wait function based on the RTC clock. + * + * @param [in] delay_clk The number of RTC clock cycles that this function will block for. + **********************************************************************************************************************/ +static inline void R_BSP_SystemRtcWaitClk (int32_t delay_clk) +{ + uint64_t prev_clk = R_BSP_SystemRtcCountGet(); + do + { + uint64_t curr_clk = R_BSP_SystemRtcCountGet(); + + if (prev_clk != curr_clk) + { + delay_clk--; + prev_clk = curr_clk; + } + } while (delay_clk > 0); +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtm.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtm.h new file mode 100644 index 000000000000..5f71f707098d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_rtm.h @@ -0,0 +1,43 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +// TIN-TODO: The definitions were moved here from Tin's bsp_common.h. Consider removing them from here +// and adding them to another header file. + +#ifndef BSP_RTM_RA6W1_H +#define BSP_RTM_RA6W1_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define RTM_TIME_PTR ((time_in_rtm_t *) dg_configAPPSUPP_RTM_ADDR) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Temporary global time rtm structure located in parallel to ‘_dpm_flag_in_rtm’ structure, + * till dpm rtm mapping re-order (moving it to a common place) will be done. */ +typedef struct _time_in_rtm +{ + long __timezone; /* timezone */ + unsigned long long systime_offset; /* msec */ + unsigned long long rtc_oldtime; /* msec */ +} time_in_rtm_t; + +/* Support 64bit time */ +typedef unsigned long long __time64_t; +typedef __time64_t ra6w1_time_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.c new file mode 100644 index 000000000000..6498dbcdb086 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.c @@ -0,0 +1,169 @@ +/** + **************************************************************************************** + * + * @file bsp_src.c + * + * @brief Implementation of the Audio Unit SRC Low Level Driver. + * + * Copyright (c) 2016-2020 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ +#include "bsp_src.h" + +#define SRC_CLK 32000 /* SRC_CLK must be 32000 Hz according to design limitation */ + +/** + * \brief Clear the SRC over/underflow indications + * + * \param [in] id identifies SRC1, SRC2 + * \param[in] io Input/Output selection (IN or OUT) + */ +#define HW_SRC_CLEAR_FLOW_ERROR(id, io) \ + while (SRC_IF->APU_SRC_CTRL_REG_b.SRC_ ## io ## _OVFLOW || \ + SRC_IF->APU_SRC_CTRL_REG_b.SRC_ ## io ## _UNFLOW) { \ + SRC_IF->APU_SRC_CTRL_REG_b.SRC_ ## io ## _FLOWCLR = 1; \ + } \ + SRC_IF->APU_SRC_CTRL_REG_b.SRC_ ## io ## _FLOWCLR = 0; + +static uint32_t R_BSP_src_calc_sampling_frequency (uint32_t sample_rate, uint8_t divider, uint8_t * iir_setting) +{ + FSP_ASSERT(divider > 0); + FSP_ASSERT(iir_setting != NULL); + + if (sample_rate > 170000) + { + *iir_setting = 3; + } + else if (sample_rate > 85000) + { + *iir_setting = 1; + } + else + { + *iir_setting = 0; + } + + sample_rate /= (*iir_setting) + 1; + uint64_t sampling_frequency = 4096 * (uint64_t) sample_rate * (uint64_t) divider; + + return (sampling_frequency / 100) & 0xFFFFFF; +} + +void R_BSP_src_init (HW_SRC_ID id, bsp_src_config_t * config) +{ + uint8_t divider = 1; + uint8_t iir_setting; + + config->id = id; + + CRG_APU->APU_SRC_CLK_REG_b.SRC_CLK_DIV = 1; + CRG_APU->APU_AUD_CLK_REG_b.AUD_PCLK_DIV = 1; + + CRG_APU->APU_SRC_CLK_REG_b.SRC_CLK_EN = 0; + CRG_APU->APU_SRC_CLK_REG_b.SRC_CLK_DIV = (uint8_t) (divider & 0x0F); + CRG_APU->APU_SRC_CLK_REG_b.SRC_CLK_EN = 1; + + if (config->in_sample_rate > 0) + { + uint32_t sampling_frequency = R_BSP_src_calc_sampling_frequency(config->in_sample_rate, divider, &iir_setting); + SRC_IF->APU_SRC_IN_FS_REG_b.SRC_IN_FS = (uint32_t) (sampling_frequency & 0xFFFFFF); + SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_DS = (uint8_t) (iir_setting & 0x03); + } + + if (config->out_sample_rate > 0) + { + uint32_t sampling_frequency = R_BSP_src_calc_sampling_frequency(config->out_sample_rate, divider, &iir_setting); + SRC_IF->APU_SRC_OUT_FS_REG_b.SRC_OUT_FS = (uint32_t) (sampling_frequency & 0xFFFFFF); + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_US = (uint8_t) (iir_setting & 0x03); + } + + ///////////////////////////////////////////// + ///////// CRG_APU + ///////////////////////////////////////////// + + CRG_APU->APU_AUD_CLK_REG_b.AUD_CLK_DIV = 1; + CRG_APU->APU_AUD_CLK_REG_b.AUD_CLK_EN = 1; + + APU_AUD->APU_MAIN_DIV_REG_b.APU_MAIN_DIV_EN = 1; + APU_AUD->APU_MAIN_DIV_REG_b.APU_MAIN_DIV = 1; + + CRG_APU->APU_SRC_CLK_REG_b.SRC_CLK_EN = 1; + + SRC_IF->APU_SRC_CTRL_REG_b.SRC_RESYNC = 1; + + // Clear input data registers + R_BSP_src_write_input(config->id, 1, 0); + R_BSP_src_write_input(config->id, 2, 0); + + HW_SRC_CLEAR_FLOW_ERROR(config->id, IN); + HW_SRC_CLEAR_FLOW_ERROR(config->id, OUT); +} + +BSP_SRC_FLOW_STATUS R_BSP_src_get_flow_status (HW_SRC_ID id, BSP_SRC_DIRECTION direction) +{ + BSP_SRC_FLOW_STATUS status = HW_SRC_FLOW_OK; + FSP_PARAMETER_NOT_USED(id); + + switch (direction) + { + case HW_SRC_IN: + { + if (SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_OVFLOW) + { + status |= HW_SRC_FLOW_OVER; + } + + if (SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_UNFLOW) + { + status |= HW_SRC_FLOW_UNDER; + } + + HW_SRC_CLEAR_FLOW_ERROR(id, IN); + break; + } + + case HW_SRC_OUT: + { + if (SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_OVFLOW) + { + status |= HW_SRC_FLOW_OVER; + } + + if (SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_UNFLOW) + { + status |= HW_SRC_FLOW_UNDER; + } + + HW_SRC_CLEAR_FLOW_ERROR(id, OUT); + break; + } + + default: + { + break; + } + } + + return status; +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.h new file mode 100644 index 000000000000..dfa00339d559 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_src.h @@ -0,0 +1,580 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** + **************************************************************************************** + * + * @file bsp_src.h + * + * @brief Definition of the API for the Audio Unit SRC Low Level Driver. + * + * Copyright (c) 2016-2020 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_SRC_RA6W1_H +#define BSP_SRC_RA6W1_H + +#include +#include +#include "bsp_api.h" + +typedef void * HW_SRC_ID; + +#define HW_SRC1 ((void *) SRC_IF_BASE) + +#define SRC_FIFO_ENABLE (0x1 << 0) +#define SRC_FIFO_ENABLE_CH1_INPUT (0x1 << 10) +#define SRC_FIFO_ENABLE_CH2_INPUT (0x1 << 11) +#define SRC_FIFO_ENABLE_CH1_OUTPUT (0x1 << 26) +#define SRC_FIFO_ENABLE_CH2_OUTPUT (0x1 << 27) + +/** + * \brief Input/Output direction + */ +typedef enum +{ + HW_SRC_IN, /**< SRC input */ + HW_SRC_OUT, /**< SRC output */ +} BSP_SRC_DIRECTION; + +/** + * \brief Flow status + */ +typedef enum +{ + HW_SRC_FLOW_OK = 0, /**< No flow errors */ + HW_SRC_FLOW_OVER, /**< Overflow errors */ + HW_SRC_FLOW_UNDER, /**< Underflow errors */ + HW_SRC_FLOW_OVER_UNDER, /**< Both overflow and underflow errors */ +} BSP_SRC_FLOW_STATUS; + +/** + * \brief Input/Output selection + */ +typedef enum +{ + HW_SRC_PCM = 1, /**< PCM interface */ + HW_SRC_PDM, /**< PDM interface */ + HW_SRC_REGS, /**< SRC registers */ + HW_SRC_FIFO, /**< SRC FIFO */ + HW_SRC_SELECTION_SIZE +} BSP_SRC_SELECTION; + +/** + * \brief SRC sync multiplexer + * + */ +typedef enum +{ + HW_SRC_INPUT_MUX_SRC_IN_REG, /**< SRC IN REG */ + HW_SRC_INPUT_MUX_SRC_OUT_REG, /**< SRC OUT REG */ + HW_SRC_INPUT_MUX_PCM_OUT_REG, /**< set to PCM_OUT_REG */ + HW_SRC_INPUT_MUX_SYNC_DIV, /**< set to SYNC DIV */ + HW_SRCx_MUX_IN_SIZE +} BSP_SRC_SYNC; + +/** + * \brief SRC configuration structure definition + */ +typedef struct +{ + HW_SRC_ID id; /**< identifies SRC */ + uint16_t src_clk; /**< SRC clock in kHz with allowed values (in kHz): + * 128, 160, 200, 250, 256, 320, 400, 500, 640, 800, + * 1000, 1280, 1600, 2000, 3200, 4000, 6400, 8000, 16000, 32000 */ + uint32_t in_sample_rate; /**< Input sampling rate in Hz with allowed values: + * 0, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 96000, 192000 */ + uint32_t out_sample_rate; /**< Input sampling rate in Hz with allowed values: + * 0, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 96000, 192000 */ + BSP_SRC_SELECTION data_input; /**< The SRC input */ + BSP_SRC_SELECTION data_output; /**< The SRC output */ +} bsp_src_config_t; + +/* ************************************************************************* + * + * ENABLE-DISABLE FUNCTIONS + * + * ************************************************************************* */ + +/** + * \brief Enable SRC + * + * \param [in] id identifies SRC1 + */ +__STATIC_INLINE void R_BSP_src_enable (HW_SRC_ID id) +{ + FSP_PARAMETER_NOT_USED(id); + + /* + * The under/overflows that occur due to the reconfiguration can be + * ignored, so we disable under/overflow notifications until + * (SRC_IN_OK == 1 && SRC_OUT_OK == 1). + */ + SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_FLOWCLR = 1; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_FLOWCLR = 1; + + SRC_IF->APU_SRC_CTRL_REG_b.SRC_EN = 1; +#if 0 + while (REG_GETF(SRC_IF, APU_SRC_CTRL_REG, SRC_IN_OK) == 0 && + REG_GETF(SRC_IF, APU_SRC_CTRL_REG, SRC_OUT_OK) == 0) + { + ; + } +#endif + while (SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_OK == 0 && + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_OK == 0) + { + ; + } + + SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_FLOWCLR = 0; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_FLOWCLR = 0; +} + +/** + * \brief Disable SRC + * + * \param [in] id identifies SRC1 + */ +__STATIC_INLINE void R_BSP_src_disable (HW_SRC_ID id) +{ + FSP_PARAMETER_NOT_USED(id); + SRC_IF->APU_SRC_CTRL_REG_b.SRC_EN = 0; +} + +/** + * \brief Check if SRC is enabled + * + * \param [in] id identifies SRC1, + * \return + * \retval True if it is enabled + * \retval False if it is disabled + * + */ +__STATIC_INLINE bool R_BSP_src_is_enabled (HW_SRC_ID id) +{ + FSP_PARAMETER_NOT_USED(id); + + return SRC_IF->APU_SRC_CTRL_REG_b.SRC_EN; +} + +/** + * \brief Enable SRC FIFO. FIFO is used to store samples from/to SRC + * + * \param [in] id identifies SRC1 + * \param[in] direction The SRC FIFO direction. + * HW_SRC_IN - FIFO is used to store samples from memory to SRC + * HW_SRC_OUT - FIFO is used to store samples from SRC to memory + */ + +__STATIC_INLINE void R_BSP_src_enable_fifo (HW_SRC_ID id, BSP_SRC_DIRECTION direction) +{ + FSP_PARAMETER_NOT_USED(id); + uint32_t reg_rd = SRC_IF->APU_SRC_FIFO_CTRL_REG_b.FIFO_CTRL; + switch (direction) + { + case HW_SRC_IN: + { + SRC_IF->APU_SRC_FIFO_CTRL_REG_b.FIFO_CTRL = reg_rd | SRC_FIFO_ENABLE | SRC_FIFO_ENABLE_CH1_INPUT | + SRC_FIFO_ENABLE_CH2_INPUT; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_FIFO_IN1_ENABLE = 1; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_FIFO_IN2_ENABLE = 1; + break; + } + + case HW_SRC_OUT: + { + SRC_IF->APU_SRC_FIFO_CTRL_REG_b.FIFO_CTRL = reg_rd | SRC_FIFO_ENABLE | SRC_FIFO_ENABLE_CH1_OUTPUT | + SRC_FIFO_ENABLE_CH2_OUTPUT; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_FIFO_OUT1_ENABLE = 1; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_FIFO_OUT2_ENABLE = 1; + break; + } + + default: + { + break; + } + } +} + +/** + * \brief Disable SRC FIFO. On each SRC request, one sample is serviced. + * + * \param [in] id identifies SRC1 + */ +__STATIC_INLINE void R_BSP_src_disable_fifo (HW_SRC_ID id) +{ + FSP_PARAMETER_NOT_USED(id); + SRC_IF->APU_SRC_FIFO_CTRL_REG_b.FIFO_CTRL = 0; + SRC_IF->APU_SRC_CTRL_REG_b.SRC_FIFO_OUT2_ENABLE = 0; +} + +/** + * \brief Check if SRC FIFO is enabled. FIFO is used to store samples from/to SRC + * + * \param [in] id identifies SRC1 + * \return + * \retval True if it is enabled + * \retval False if it is disabled + */ +__STATIC_INLINE bool R_BSP_src_is_fifo_enabled (HW_SRC_ID id) +{ + FSP_PARAMETER_NOT_USED(id); + FSP_ASSERT(id == HW_SRC1); + + return SRC_IF->APU_SRC_FIFO_CTRL_REG_b.FIFO_CTRL; +} + +/* ************************************************************************* + * + * SET FUNCTIONS + * + * ************************************************************************* */ + +/** + * \brief Set Automatic Conversion mode + * + * \param [in] id identifies SRC1 + * \param[in] direction Input/Output direction of data flow allowed values: + * HW_SRC_IN, HW_SRC_OUT + */ +__STATIC_INLINE void R_BSP_src_set_automode (HW_SRC_ID id, BSP_SRC_DIRECTION direction) +{ + FSP_PARAMETER_NOT_USED(id); + if (direction == HW_SRC_IN) + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_AMODE = 1; + } + else + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_AMODE = 1; + } +} + +/** + * \brief Clear Automatic Conversion mode. Use manual mode + * + * \param [in] id identifies SRC1 + * \param[in] direction Input/Output direction of data flow allowed values: + * HW_SRC_IN, HW_SRC_OUT + */ +__STATIC_INLINE void R_BSP_src_set_manual_mode (HW_SRC_ID id, BSP_SRC_DIRECTION direction) +{ + FSP_PARAMETER_NOT_USED(id); + if (direction == HW_SRC_IN) + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_AMODE = 0; + } + else + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_AMODE = 0; + } +} + +/** + * \brief Set Automatic Conversion mode sync + * + * \param [in] id identifies SRC1 + * \param[in] direction Input/Output direction of data flow allowed values: + * HW_SRC_IN, HW_SRC_OUT + * \param[in] sync SRC Automode sync + */ +__STATIC_INLINE void R_BSP_src_set_automode_sync (HW_SRC_ID id, BSP_SRC_DIRECTION direction, BSP_SRC_SYNC sync) +{ + FSP_PARAMETER_NOT_USED(id); + if (direction == HW_SRC_IN) + { + APU_DSP->APU_SYNC_SRC1IN_SEL_REG_b.SRC1_IN_A_SEL = sync; + } + else + { + APU_DSP->APU_SYNC_SRC1OUT_SEL_REG_b.SRC1_OUT_A_SEL = sync; + } +} + +/** + * \brief Select the SRC mux + * + * \note call this function once SRC interface initialization is done + * + * \param[in] input the SRC input + * \param[in] output the SRC output + * \param[in, out] config the configuration structure of SRC + */ +__STATIC_INLINE void R_BSP_src_select_mux (BSP_SRC_SELECTION input, BSP_SRC_SELECTION output, bsp_src_config_t * config) +{ + uint32_t temp_read; + + config->data_input = input; + + switch (input) + { + case HW_SRC_PDM: + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_PDM_EN = 1; + break; + } + + case HW_SRC_PCM: + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_PDM_EN = 0; + temp_read = APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL; + APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL = (uint8_t) (temp_read & ~(0x3UL)); + break; + } + + case HW_SRC_REGS: + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_PDM_EN = 0; + temp_read = APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL; + APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL = (uint8_t) (temp_read | (0x1 << 0)); + + break; + } + + case HW_SRC_FIFO: + { + SRC_IF->APU_SRC_CTRL_REG_b.SRC_PDM_EN = 0; + temp_read = APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL; + APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL = (uint8_t) ((temp_read | (0x1 << 1)) & ~(0x1UL << 0)); + break; + } + + default: + { + break; + } + } + + switch (output) + { + case HW_SRC_REGS: + { + temp_read = APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL; + APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL = (uint8_t) ((temp_read | (0x1 << 2)) & ~(0x1UL << 3)); + break; + } + + case HW_SRC_FIFO: + { + temp_read = APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL; + APU_DSP->APU_MUX_CTRL_REG_b.APU_DSP_MUX_CTL = (uint8_t) ((temp_read | (0x1 << 3)) & ~(0x1UL << 2)); + break; + } + + default: + { + break; + } + } +} + +/** + * \brief Write data to an input SRC register + * + * \param [in] id identifies SRC1 + * \param[in] stream The input stream (1 or 2) + * \param[in] value The data to be written + */ +__STATIC_INLINE void R_BSP_src_write_input (HW_SRC_ID id, uint8_t stream, uint32_t value) +{ + FSP_PARAMETER_NOT_USED(id); + switch (stream) + { + case 1: + { + SRC_IF->APU_SRC_IN1_REG_b.SRC_IN = value; + break; + } + + case 2: + { + SRC_IF->APU_SRC_IN2_REG_b.SRC_IN = value; + break; + } + + default: + { + break; + } + } +} + +/** + * \brief Write data to an input SRC FIFO register + * + * \param [in] id identifies SRC1 + * \param[in] stream The input stream (1 or 2) + * \param[in] value The data to be written + */ +__STATIC_INLINE void R_BSP_src_write_fifo_input (HW_SRC_ID id, uint8_t stream, uint32_t value) +{ + FSP_PARAMETER_NOT_USED(id); + switch (stream) + { + case 1: + { + SRC_FIFO_IF->APU_SRC_FIFO_IN1_REG_b.SRC_IN = value; + break; + } + + case 2: + { + SRC_FIFO_IF->APU_SRC_FIFO_IN2_REG_b.SRC_IN = value; + break; + } + + default: + { + break; + } + } +} + +/* ************************************************************************* + * + * GET FUNCTIONS + * + * ************************************************************************* */ + +/** + * \brief Get the mode + * + * \param [in] id identifies SRC1 + * \param[in] direction Input/Output direction of data flow allowed values: + * HW_SRC_IN, HW_SRC_OUT + * \return mode + * \retval 0 for manual mode + * \retval 1 for automatic mode + */ +__STATIC_INLINE bool R_BSP_src_is_auto_mode (HW_SRC_ID id, BSP_SRC_DIRECTION direction) +{ + FSP_ASSERT(id == HW_SRC1); + + if (direction == HW_SRC_IN) + { + return SRC_IF->APU_SRC_CTRL_REG_b.SRC_IN_AMODE; + } + else + { + return SRC_IF->APU_SRC_CTRL_REG_b.SRC_OUT_AMODE; + } +} + +/** + * \brief Read data from an output SRC register + * + * \param [in] id identifies SRC1 + * \param[in] stream The output stream (1 or 2) + * + * \return The data read + */ +__STATIC_INLINE uint32_t R_BSP_src_read_output (HW_SRC_ID id, uint8_t stream) +{ + FSP_ASSERT(id == HW_SRC1); + + switch (stream) + { + case 1: + { + return SRC_IF->APU_SRC_OUT1_REG_b.SRC_OUT; + } + + case 2: + { + return SRC_IF->APU_SRC_OUT2_REG_b.SRC_OUT; + } + + default: + FSP_ASSERT(0); + + return 0; + } +} + +/** + * \brief Read data from an output SRC FIFO register + * + * \param [in] id identifies SRC1 + * \param[in] stream The output stream (1 or 2) + * + * \return The data read + */ +__STATIC_INLINE uint32_t R_BSP_src_read_fifo_output (HW_SRC_ID id, uint8_t stream) +{ + FSP_ASSERT(id == HW_SRC1); + + switch (stream) + { + case 1: + { + return SRC_FIFO_IF->APU_SRC_FIFO_OUT1_REG_b.SRC_OUT; + } + + case 2: + { + return SRC_FIFO_IF->APU_SRC_FIFO_OUT2_REG_b.SRC_OUT; + } + + default: + FSP_ASSERT(1); + + return 0; + } +} + +/** + * \brief Check if SRC flow errors have occurred and clear the indication + * + * \param [in] id identifies SRC1 + * \param[in] direction Input/Output direction + * + * \return The flow status + */ +BSP_SRC_FLOW_STATUS R_BSP_src_get_flow_status(HW_SRC_ID id, BSP_SRC_DIRECTION direction); + +/** + * \brief Initialize the SRC + * + * Configure the SRC sampling frequencies, the input down-sampler and output up-sampler IIR filters, + * the conversion modes, the divider of the internally generated clock and enable the clock + * + * \note call R_BSP_src_enable() once SRC interface initialization is done + * + * \param[in] id identifies SRC1 + * \param[out] config configuration structure of SRC + */ +void R_BSP_src_init(HW_SRC_ID id, bsp_src_config_t * config); + +#endif /* BSP_SRC_RA6W1_H */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.c new file mode 100644 index 000000000000..01e3cc98cf74 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.c @@ -0,0 +1,1735 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_tcs.h" +#include "config/bsp_memory_defaults_ra6w1.h" +#include +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define OTP_CS_END (0x0000C0 * 4) +#define OTP_CS_SIZE (640) + +#define CS_START_CMD 0xA5A5A5A5 +#define CS_BOOTER_VAL 0xE6000000 + +#define CS_DATA_TYPE_MASK 0xFF000000 +#define CS_DATA_TYPE_FILED 0x80000000 + +#define CS_DATA_VAL 0xE1000000 +#define CS_SDK_VAL 0xE9000000 +#define CS_STX_CONFIG 0xE8000000 // 2 bytes of data follow +#define CS_HW_CFG_VAL 0xEC000000 // 1 byte of data follow +#define CS_MIN_FW_VAL 0xEB000000 +#define CS_DELAYCMD 0xED000000 // 1 byte of data follow +#define CS_CRC_SKIP 0xEE000000 // 1 byte of data follow +#define CS_STOP_CMD 0x00000000 +#define CS_EMPTY_VAL 0xFFFFFFFF + +#define CS_SDK_VAL_GID_MASK 0x000000FF +#define CS_SDK_VAL_LEN_MASK 0x0000FF00 +#define CS_SDK_VAL_SETID_MASK 0x00FF0000 + +#define OTP_CS_ADDRESS 0x00000100 +#define CS_MAX_SIZE (TCS_DATA_SIZE * 4) // 256 entries of 4 bytes + +/* 0x50060F9C value used in booter code */ +#define MAX_REG_ADDR 0x5100155C + +#define EMPTY 0xFF +#define NOT_RETAINED 0 +#define RETAINED 1 + +#define MAX_ATTRIBUTE 20 +#define MAX_DATA_SIZE 100 +#define HEADER_SIZE 0x60 +#define HEADER_STRUCT_SIZE 0x10 +#define SIZE_RETAINED_TCS_ATTRIBUTES (0xFF - HEADER_SIZE) + +#define CS_VALID_PATTERN 0xA5A5 + +#define XTAL_REG 0x400C0204 +#define TCS_TAG_MAC_ADDR 0xe9000221 +#define RENESAS_MAC_UAP_LOWER_MASK 0xff000000 + +#define T2_NULL_DATA_SIZE 0x7 +#define T2_PROGRAM_VER_START 0x21U +#define T2_PROGRAM_VER_END 0x23U + +/** + * The TCS data placed in shared memory + */ +#define SYS_TCS_SHARED (shared_tcs.sys_tcs_shared) +#define SYS_TCS_RETAINED (retained_tcs->sys_tcs_shared) +#define SYS_TCS (current_tcs->sys_tcs_shared) + +/* For fixing T2 production */ +#define TCS_PATCH_BASE 0x75 +#define TCS_PROD_MAC 0xe9000221 +#define TCS_PROD_VER 0xe90001c3 + +#if TCS_INFO + #define INFO_PRINTF(...) printf(__VA_ARGS__) +#else + #define INFO_PRINTF(...) +#endif + +#define SOURCE_DATA_INIT(base, sections) \ + { \ + .base_address = base, \ + .num_sections = FSP_ARRAY_LENGTH(sections), \ + .section_addresses = sections, \ + } + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct +{ + uint32_t reg_address; + bool trimmed; +} reg_trimmed_t; + +typedef struct +{ + bsp_tcs_shared_t sys_tcs_shared; +} tcs_t; + +typedef struct +{ + uint32_t base_address; + uint8_t num_sections; + const uint32_t * section_addresses; +} source_data_t; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +static const uint32_t renesas_oui_list[] = {0x749050, 0x7c152d}; + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +tcs_t * current_tcs; +tcs_t * retained_tcs = (tcs_t *) dg_configTCS_RTM_ADDR; +bsp_tcs_attr_t * retained_tcs_attributes = (bsp_tcs_attr_t *) (dg_configTCS_RTM_ADDR + HEADER_STRUCT_SIZE); +uint32_t * retained_tcs_buffer = (uint32_t *) (dg_configTCS_RTM_ADDR + HEADER_SIZE); + +/** + * Pointer to the TCS data as parser by the TCS parser + * \note This variable is initialized to a value other than zero + * so to be placed in the .data section + */ +uint32_t * tcs_data = (uint32_t *) 0xFFFFFFFF; +bsp_tcs_source_t tcs_source = EMPTY; + +#if BSP_FEATURE_TCS_SYS_RAM +tcs_t shared_tcs; +bsp_tcs_attr_t tcs_attributes[MAX_ATTRIBUTE]; +uint32_t tcs_buffer[MAX_DATA_SIZE]; + +static const uint32_t default_section[] = {0}; +static const uint32_t otp_sections[] = {0, 0x300}; +#endif + +/* Max of array is 52 bytes, current it's 52 bytes (row is 4 bytes, current 13) */ +static const bsp_tcs_attr_t based_on_tcs_attributes[MAX_ATTRIBUTE] = +{ + {BSP_TCS_GROUP_MAC_ADDR, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, 0}, + {BSP_TCS_GROUP_SKIP, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_PD_SYS, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PD_SYS, BSP_TCS_TYPE_REG_PAIR, BSP_TCS_DOMAIN_PD_SYS, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PD_ADC, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_PD_COM, + NOT_RETAINED, EMPTY, + 0}, + + {BSP_TCS_GROUP_PD_WIFI_TRIM_RF_HPI, BSP_TCS_TYPE_REG_PAIR, BSP_TCS_DOMAIN_PD_RAD, + RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PD_WIFI_TRIM_LUT, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_PD_RAD, + RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL, BSP_TCS_TYPE_REG_PAIR, BSP_TCS_DOMAIN_PD_RAD, + RETAINED, EMPTY, + 0}, + + /* Production Test Section */ + {BSP_TCS_GROUP_CHIP_ID, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PROD_INFO, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PROD_WAFER, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_TESTPROGRAM_VERSION, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, + 0}, + {BSP_TCS_GROUP_PROD_SW_IP, BSP_TCS_TYPE_TRIM_VAL, BSP_TCS_DOMAIN_NA, + NOT_RETAINED, EMPTY, + 0}, + {0, BSP_TCS_TYPE_RESERVED, 0, + 0, 0, + 0} +}; /* GID 18 */ + +#if BSP_FEATURE_TCS_SYS_RAM +static const bsp_tcs_source_t tcs_parsing_order[] = +{ + BSP_TCS_OTP, + BSP_TCS_OQSPI, + #if (USE_TCS_NVMS == 1) + #ifdef MEMORY_NVMS_OTP_ADDRESS + BSP_TCS_NVMS, + #endif /* MEMORY_NVMS_OTP_ADDRESS */ + #endif /* USE_TCS_NVMS == 1*/ +}; + +static const source_data_t source_data[] = +{ + /* TCS_OTP */ + SOURCE_DATA_INIT(MEMORY_OTP_BASE + OTP_CS_ADDRESS, otp_sections), + + /* TCS_OQSPI */ + SOURCE_DATA_INIT(MEMORY_OQSPIC_S_BASE, default_section), +}; + +static const uint32_t zero_parttern[7] = {0, }; +#endif + +/*********************************************************************************************************************** + * Private functions + **********************************************************************************************************************/ +static uint32_t bsp_mac_reverse (register uint32_t x) +{ + x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); + x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); + + return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); +} + +static bool bsp_mac_is_renesas_oui (uint32_t upper_mac, uint32_t lower_mac) +{ + uint8_t idx = 0; + + for (idx = 0; idx < sizeof(renesas_oui_list) / sizeof(renesas_oui_list[0]); ++idx) + { + uint32_t rev_oui = bsp_mac_reverse(renesas_oui_list[idx]); + + if ((upper_mac == (rev_oui >> 8)) && + ((lower_mac & RENESAS_MAC_UAP_LOWER_MASK) >> 24 == (rev_oui & 0xFF))) + { + return true; + } + } + + return false; +} + +static uint16_t bsp_based_attributes_size (void) +{ + return sizeof(based_on_tcs_attributes) / sizeof(based_on_tcs_attributes[0]); +} + +static uint16_t bsp_based_gid_to_idx (uint16_t gid) +{ + uint16_t i; + for (i = 0; i < sizeof(based_on_tcs_attributes) / sizeof(based_on_tcs_attributes[0]); i++) + { + if (gid == based_on_tcs_attributes[i].value_gid) + { + return i; + } + } + + return --i; +} + +static uint16_t bsp_tcs_gid_to_idx (uint16_t gid) +{ + uint16_t i; + for (i = 0; i < SYS_TCS.tcs_attributes_size; i++) + { + if (gid == SYS_TCS.tcs_attributes[i].value_gid) + { + return i; + } + } + + return --i; +} + +#if BSP_FEATURE_TCS_SYS_RAM +static uint16_t bsp_retained_gid_to_idx (uint16_t gid) +{ + uint16_t i; + for (i = 0; i < SYS_TCS_RETAINED.tcs_attributes_size; i++) + { + if (gid == SYS_TCS_RETAINED.tcs_attributes[i].value_gid) + { + return i; + } + } + + return --i; +} + +static bsp_tcs_type_t bsp_tcs_get_value_type (bsp_tcs_gid_t gid) +{ + BSP_CHECK_DEBUG(gid < BSP_TCS_GROUP_MAX); + + if (bsp_tcs_gid_to_idx(gid) == (SYS_TCS.tcs_attributes_size - 1)) + { + return BSP_TCS_TYPE_RESERVED; + } + + return SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].value_type; +} + +static bool bsp_tcs_set_tcs (bsp_tcs_gid_t gid, uint32_t is_set) +{ + if (is_set) + { + if (bsp_based_gid_to_idx(gid) == (bsp_based_attributes_size() - 1)) + { + current_tcs = &shared_tcs; + + return false; + } + + if (based_on_tcs_attributes[bsp_based_gid_to_idx(gid)].is_retained == false) + { + #if BSP_FEATURE_TCS_SYS_RAM + current_tcs = &shared_tcs; + #else + current_tcs = retained_tcs; + #endif + } + else + { + current_tcs = retained_tcs; + } + } + else + { + #if BSP_FEATURE_TCS_SYS_RAM + current_tcs = &shared_tcs; + tcs_data = SYS_TCS_SHARED.tcs_data; + #endif + } + + if (SYS_TCS.cs_valid != CS_VALID_PATTERN) + { + return false; + } + + return true; +} + +static void init_tcs_attributes_array (void) +{ + memset(tcs_buffer, 0, sizeof(tcs_buffer)); + + memcpy(tcs_attributes, based_on_tcs_attributes, sizeof(based_on_tcs_attributes)); + SYS_TCS_SHARED.tcs_data = tcs_buffer; + SYS_TCS_SHARED.tcs_attributes = tcs_attributes; + + memset(retained_tcs_buffer, 0, SIZE_RETAINED_TCS_ATTRIBUTES); + + SYS_TCS_RETAINED.tcs_data = retained_tcs_buffer; + SYS_TCS_RETAINED.tcs_attributes = retained_tcs_attributes; +} + +static uint32_t fetch_tcs_entry (bsp_tcs_source_t source, uint32_t address) +{ + uint32_t cs_value = CS_EMPTY_VAL; + + if (source < FSP_ARRAY_LENGTH(source_data)) + { + cs_value = *((uint32_t *) ((uint32_t) source_data[source].base_address + address)); + } + + return cs_value; +} + +#endif + +static void store_tcs (uint32_t address, uint8_t gid_len, bsp_tcs_source_t source, bool reverse) +{ + int i = 0; + uint16_t index; + BSP_CHECK_DEBUG(tcs_data); + + /* Address --> GID header */ + uint32_t value = fetch_tcs_entry(source, address); + bsp_tcs_gid_t gid = (uint8_t) (value & CS_SDK_VAL_GID_MASK); + + if (gid >= BSP_TCS_GROUP_MAX) + { + return; + } + + if (bsp_tcs_gid_to_idx(gid) == (SYS_TCS.tcs_attributes_size - 1)) + { + return; + } + + bsp_tcs_type_t type = bsp_tcs_get_value_type(gid); + + if (type == BSP_TCS_TYPE_TRIM_VAL) + { + /* BSP_TCS_TYPE_TRIM_VAL could have different sizes during parsing + * it is acceptable multiple instances with same GID to have different sizes, + * only the newest will be finally stored. We cannot identify the newest but + * at least the ones that fit will be stored until the newest is parsed + */ + if (gid_len != SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size) + { + return; + } + } + + /* Start of storing TCS entries */ + index = SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].start; + + /* For BSP_TCS_TYPE_REG_PAIR search tcs_data to find empty slot + * For BSP_TCS_TYPE_TRIM_VAL fragmentation is not supported and always the newest entries are stored + */ + if (type == BSP_TCS_TYPE_REG_PAIR) + { + uint16_t gid_start = index; + uint8_t gid_size = SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size; + + /* Search tcs_data to find empty slot */ + while (tcs_data[index] != 0) + { + /* Check if the index is inside the allocated space in tcs_data[] for this GID */ + BSP_CHECK_DEBUG(index < (gid_start + gid_size)); + if (index >= (gid_start + gid_size)) + { + return; + } + + /* Go to next register address */ + index += 2; + } + } + + while (i < gid_len) /* 4 bytes entries */ + { + address += 4; + if (reverse == true) + { + tcs_data[index] = bsp_mac_reverse(fetch_tcs_entry(source, address)); + } + else + { + tcs_data[index] = fetch_tcs_entry(source, address); + } + + index++; + i++; + } +} + +/* The calculated size in bytes, that is the number + * of entries * sizeof(int) + * returns the size in bytes + */ +static uint16_t get_size_of_cs (bsp_tcs_source_t source) +{ + uint32_t value = 0; + uint32_t address = 0; + uint16_t max_size = CS_MAX_SIZE; + uint16_t size = 0; + uint32_t i; + + for (i = 0; i < source_data[source].num_sections; i++) + { + address = source_data[source].section_addresses[i]; + if ((value = fetch_tcs_entry(source, address)) != CS_START_CMD) + { + /* This section does not contain CS */ + continue; + } + + /* Check next entry */ + address += 4; + while (address < max_size) + { + value = fetch_tcs_entry(source, address); + + if ((value == CS_STOP_CMD) || (value == CS_EMPTY_VAL)) + { + /* End of CS */ + break; + } + else if (value <= MAX_REG_ADDR) + { + /* Address value pair parsed by bootrom, skip this value */ + if (value == XTAL_REG) + { + SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL)].size = 2; + } + + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) > CS_DATA_TYPE_FILED) && ((value & CS_DATA_TYPE_MASK) < CS_DATA_VAL)) + { + address += 0x4; + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) == CS_BOOTER_VAL) || ((value & CS_DATA_TYPE_MASK) == CS_STX_CONFIG) || + (value == CS_MIN_FW_VAL)) + { + address += 0x4; + } + else if ((value & CS_DATA_TYPE_MASK) == CS_SDK_VAL) + { + /* SDK value */ + uint8_t tcs_len = (value & CS_SDK_VAL_LEN_MASK) >> 8; + bsp_tcs_gid_t gid = (uint8_t) (value & CS_SDK_VAL_GID_MASK); + uint8_t setid = (value & CS_SDK_VAL_SETID_MASK) >> 16; + + /* Skip next tcs values. */ + + if ((gid >= BSP_TCS_GROUP_MAX) || (setid != 0x00)) + { + /* Skip this entry */ + address += tcs_len * 4; + address += 0x4; + continue; + } + + if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_TRIM_VAL) + { + /*always keep the last found size */ + if (SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size != tcs_len) + { + uint32_t tmp_dest[10]; + for (i = 0; i < 10; i++) + { + tmp_dest[i] = fetch_tcs_entry(source, address + (i * 4)); + } + + if (((tmp_dest[1] >= T2_PROGRAM_VER_START)) && (tmp_dest[9] == TCS_TAG_MAC_ADDR)) + { + /* H/W workaround T2 production */ + if (tmp_dest[2] == XTAL_REG) + { + SYS_TCS_SHARED.tcs_attributes + [bsp_tcs_gid_to_idx(BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL)].size = 2; + } + + if (!memcmp(tmp_dest + 2, zero_parttern, 7 * sizeof(uint32_t)) || + !memcmp(tmp_dest + 4, zero_parttern, 5 * sizeof(uint32_t))) + { + tcs_len += T2_NULL_DATA_SIZE; + } + } + + /* Update with new size */ + size -= (uint16_t) (4 * SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size); + size += (uint16_t) (4 + tcs_len); + SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size = tcs_len & 0xf; + } + + address += tcs_len * 4; // Skip next tcs values. + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_REG_PAIR) + { + /* Check that BSP_TCS_TYPE_REG_PAIR values are of an even number */ + if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_REG_PAIR) + { + BSP_CHECK_DEBUG((tcs_len & 0x01) == 0); + } + + /* Size should be in bytes */ + size += (uint16_t) (4 * tcs_len); + SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size += tcs_len; + address += tcs_len * 4; // Skip next tcs values. + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_HPI_REG_PAIR) + { + /* Size should be in bytes */ + size += (uint16_t) (4 * tcs_len); + SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size += tcs_len; + address += tcs_len * 4; // Skip next tcs values. + } + else + { + address += tcs_len * 4; + } + } + + /* Go to next word this value is not related to TCS */ + address += 0x4; + } + } + + return size; +} + +static void store_cs_attributes (bsp_tcs_source_t source, uint16_t size) +{ + uint32_t value = 0; + uint32_t index = 0; + uint32_t address; + uint32_t i; + + for (i = 0; i < source_data[source].num_sections; i++) + { + address = source_data[source].section_addresses[i]; + if ((value = fetch_tcs_entry(source, address)) != CS_START_CMD) + { + /* This section does not contain CS */ + continue; + } + + address += 4; + + while (address < size) + { + value = fetch_tcs_entry(source, address); + + if ((value == CS_STOP_CMD) || (value == CS_EMPTY_VAL)) + { + /* End of CS */ + break; + } + else if (value <= MAX_REG_ADDR) + { + /* Address - value pair */ + if (value == XTAL_REG) + { + index = + SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL)].start; + tcs_data[index] = fetch_tcs_entry(source, address); + tcs_data[index + 1] = fetch_tcs_entry(source, address + 4); + } + + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) > CS_DATA_TYPE_FILED) && ((value & CS_DATA_TYPE_MASK) < CS_DATA_VAL)) + { + address += 0x4; + address += 0x4; + } + else if ((value == CS_BOOTER_VAL) || (value == CS_MIN_FW_VAL) || + ((value & CS_DATA_TYPE_MASK) == CS_STX_CONFIG)) + { + /* Skip booter value and minimun FW version value */ + address += 0x4; + } + else if ((value & CS_DATA_TYPE_MASK) == CS_SDK_VAL) + { + /* SDK value */ + uint8_t gid_len = (value & CS_SDK_VAL_LEN_MASK) >> 8; + uint8_t setid = (value & CS_SDK_VAL_SETID_MASK) >> 16; + bsp_tcs_gid_t gid = (uint8_t) (value & CS_SDK_VAL_GID_MASK); + uint32_t tmp_dest[10]; + uint32_t tmp_address = address + 4; + + if (gid == BSP_TCS_GROUP_TESTPROGRAM_VERSION) + { + for (i = 0; i < 10; i++) + { + tmp_dest[i] = fetch_tcs_entry(source, address + (i * 4)); + } + + if (((tmp_dest[1] >= T2_PROGRAM_VER_START)) && (tmp_dest[9] == TCS_TAG_MAC_ADDR)) + { + /* H/W workaround T2 production */ + if (tmp_dest[2] == XTAL_REG) + { + index = + SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL)].start; + tcs_data[index] = tmp_dest[2]; + tcs_data[index + 1] = tmp_dest[3]; + } + + if (!memcmp(tmp_dest + 2, zero_parttern, 7 * sizeof(uint32_t)) || + !memcmp(tmp_dest + 4, zero_parttern, 5 * sizeof(uint32_t))) + { + gid_len += T2_NULL_DATA_SIZE; + } + } + + store_tcs(address, gid_len, source, 0); + } + else if (gid == BSP_TCS_GROUP_MAC_ADDR) + { + tmp_dest[0] = fetch_tcs_entry(source, tmp_address); + tmp_dest[1] = fetch_tcs_entry(source, tmp_address + 4); + if ((gid == BSP_TCS_GROUP_MAC_ADDR) && bsp_mac_is_renesas_oui(tmp_dest[1], tmp_dest[0])) + { + store_tcs(address, gid_len, source, 1); + } + else + { + store_tcs(address, gid_len, source, 0); + } + } + else if (setid == 0x00) + { + /* store entries with SET ID 0x00 */ + store_tcs(address, gid_len, source, 0); + } + + /* Skip next tcs values. */ + address += gid_len * 4; + } + + /* Advance address by 4 bytes */ + address += 0x4; + } + } +} + +static bool bsp_tcs_get_item_in_otp_cs (const uint32_t item, uint32_t * dest, uint16_t * size) +{ + volatile bsp_tcs_source_t source = BSP_TCS_OTP; + volatile uint32_t address, tmp_address; + volatile uint32_t value = 0; + volatile uint16_t max_size = CS_MAX_SIZE; + volatile uint32_t i, e; + volatile bool ret = false; + + *size = 0; + for (i = 0; i < source_data[source].num_sections; i++) + { + address = source_data[source].section_addresses[i]; + value = fetch_tcs_entry(source, address); + if (value != CS_START_CMD) + { + continue; + } + + address += 0x4; + + while (address < max_size) + { + value = fetch_tcs_entry(source, address); + if ((value == CS_STOP_CMD) || (value == CS_EMPTY_VAL)) + { + /* End of CS */ + break; + } + else if (value <= MAX_REG_ADDR) + { + /* Address - value pair */ + if (item == value) + { + *dest = fetch_tcs_entry(source, address + 4); + *size = 1; + } + + /* Skip value entry */ + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) > CS_DATA_TYPE_FILED) && ((value & CS_DATA_TYPE_MASK) < CS_DATA_VAL)) + { + address += 0x4; + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) == CS_BOOTER_VAL) || ((value & CS_DATA_TYPE_MASK) == CS_STX_CONFIG) || + (value == CS_MIN_FW_VAL)) + { + address += 0x4; + } + else if ((value & CS_DATA_TYPE_MASK) == CS_SDK_VAL) + { + uint8_t tcs_len = (value & CS_SDK_VAL_LEN_MASK) >> 8; + bsp_tcs_gid_t gid = (uint8_t) (value & CS_SDK_VAL_GID_MASK); + uint8_t setid = (value & CS_SDK_VAL_SETID_MASK) >> 16; + uint32_t tmp_dest[10]; + + if ((item > MAX_REG_ADDR) && (gid == (item & CS_SDK_VAL_GID_MASK))) + { + tmp_address = address + 4; + *size = tcs_len; + if (gid == BSP_TCS_GROUP_MAC_ADDR) + { + tmp_dest[0] = fetch_tcs_entry(source, tmp_address); + tmp_dest[1] = fetch_tcs_entry(source, tmp_address + 4); + if (bsp_mac_is_renesas_oui(tmp_dest[1], tmp_dest[0])) + { + for (e = 0; e < tcs_len; e++) + { + dest[e] = bsp_mac_reverse(fetch_tcs_entry(source, tmp_address + e * 4)); + } + } + else + { + for (e = 0; e < tcs_len; e++) + { + dest[e] = fetch_tcs_entry(source, tmp_address + e * 4); + } + } + } + else + { + for (e = 0; e < tcs_len; e++) + { + dest[e] = fetch_tcs_entry(source, tmp_address + e * 4); + } + } + } + + if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_TRIM_VAL) + { + if (gid == BSP_TCS_GROUP_TESTPROGRAM_VERSION) + { + for (i = 0; i < 10; i++) + { + tmp_dest[i] = fetch_tcs_entry(source, address + (i * 4)); + } + + if (((tmp_dest[1] >= T2_PROGRAM_VER_START)) && (tmp_dest[9] == TCS_TAG_MAC_ADDR)) + { + /* H/W workaround T2 production */ + if (tmp_dest[2] == XTAL_REG) + { + dest[0] = tmp_dest[3]; + } + + if (!memcmp(tmp_dest + 2, zero_parttern, 7 * sizeof(uint32_t)) || + !memcmp(tmp_dest + 4, zero_parttern, 5 * sizeof(uint32_t))) + { + tcs_len += T2_NULL_DATA_SIZE; + } + } + } + + address += tcs_len * 4; // Skip next tcs values + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_REG_PAIR) + { + if ((item > MAX_REG_ADDR) && (gid == (item & CS_SDK_VAL_GID_MASK))) + { + address += tcs_len * 4; // Skip next tcs values. + } + else + { + tmp_address = address + 4; + for (e = 0; e < tcs_len / 2; e += 2) + { + value = fetch_tcs_entry(source, tmp_address + e * 4); + if (item == value) + { + *dest = fetch_tcs_entry(source, tmp_address + e * 4 + 1); + *size = 1; + } + } + + address += tcs_len * 4; // Skip next tcs values. + } + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_HPI_REG_PAIR) + { + address += tcs_len * 4; // Skip next tcs values. + } + else + { + address += tcs_len * 4; // Skip next tcs values. + } + + if ((gid >= BSP_TCS_GROUP_MAX) || (setid != 0x00)) + { + address += 0x4; // Skip this entry + continue; + } + } + + address += 0x4; // advance address by 4 bytes + } + + ret = true; + } + + return ret; +} + +static uint32_t bsp_tcs_get_otp_size (uint16_t * size, uint32_t item, uint16_t * item_count) +{ + uint32_t value = 0; + uint32_t address = 0; + uint32_t i = 0; + uint16_t max_size = CS_MAX_SIZE; + + *size = 0; + *item_count = 0; + + address = source_data[BSP_TCS_OTP].section_addresses[0]; + if ((value = fetch_tcs_entry(BSP_TCS_OTP, address)) != CS_START_CMD) + { + + // This section does not contain CS + return 0; + } + + /* Check next entry */ + address += 4; + while (address < max_size) + { + value = fetch_tcs_entry(BSP_TCS_OTP, address); + + if ((value == CS_STOP_CMD) || (value == CS_EMPTY_VAL)) + { + /* End of CS */ + break; + } + + if (value <= MAX_REG_ADDR) + { + /* Address-value pair parsed by bootrom, skip this value */ + address += 0x4; + if (item == value) + { + (*item_count)++; + } + } + else if (((value & CS_DATA_TYPE_MASK) > CS_DATA_TYPE_FILED) && ((value & CS_DATA_TYPE_MASK) < CS_DATA_VAL)) + { + address += 0x4; + address += 0x4; + } + else if (((value & CS_DATA_TYPE_MASK) == CS_BOOTER_VAL) || ((value & CS_DATA_TYPE_MASK) == CS_STX_CONFIG) || + (value == CS_MIN_FW_VAL)) + { + address += 0x4; + } + else if ((value & CS_DATA_TYPE_MASK) == CS_SDK_VAL) + { + uint8_t tcs_len = (value & CS_SDK_VAL_LEN_MASK) >> 8; + bsp_tcs_gid_t gid = (uint8_t) (value & CS_SDK_VAL_GID_MASK); + uint8_t setid = (value & CS_SDK_VAL_SETID_MASK) >> 16; + uint32_t tmp_address = 0; + uint32_t e = 0; + + if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_TRIM_VAL) + { + uint32_t tmp_dest[10]; + for (i = 0; i < 10; i++) + { + tmp_dest[i] = fetch_tcs_entry(BSP_TCS_OTP, address + (i * 4)); + } + + if (((tmp_dest[1] >= T2_PROGRAM_VER_START)) && (tmp_dest[9] == TCS_TAG_MAC_ADDR)) + { + /* H/W workaround T2 production */ + if (!memcmp(tmp_dest + 2, zero_parttern, 7 * sizeof(uint32_t)) || + !memcmp(tmp_dest + 4, zero_parttern, 5 * sizeof(uint32_t))) + { + tcs_len += T2_NULL_DATA_SIZE; + } + } + + address += tcs_len * 4; // Skip next tcs values. + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_REG_PAIR) + { + for (e = 0; e < tcs_len / 2; e += 2) + { + value = fetch_tcs_entry(BSP_TCS_OTP, tmp_address + e * 4); + if (item == value) + { + fetch_tcs_entry(BSP_TCS_OTP, tmp_address + e * 4 + 1); + (*item_count)++; + } + } + + address += tcs_len * 4; // Skip next tcs values. + } + else if (bsp_tcs_get_value_type(gid) == BSP_TCS_TYPE_HPI_REG_PAIR) + { + address += tcs_len * 4; // Skip next tcs values. + } + else + { + address += tcs_len * 4; // Skip next tcs values. + } + + if ((item > MAX_REG_ADDR) && (gid == (item & CS_SDK_VAL_GID_MASK))) + { + (*item_count)++; + } + + if ((gid >= BSP_TCS_GROUP_MAX) || (setid != 0x00)) + { + address += 0x4; // Skip this entry + continue; + } + } + + /* Go to next word this value is not related to TCS */ + address += 0x4; + } + + *size = (uint16_t) address; + + return true; +} + +static bool t2_production_patch (void) +{ + uint32_t src[15] = {0, }; + uint32_t result = 0; + const uint32_t fix_blank1[2] = {0xe9000602, 0x0}; + const uint32_t fix_blank2[2] = {0xe9000402, 0x0}; + + /* Read OTP data */ + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_read(src, TCS_PATCH_BASE, 15); + + /* Enter programming mode */ + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + + if ((src[9] != TCS_PROD_MAC) || (src[0] != TCS_PROD_VER)) + { + goto exit; + } + + /* Check conditions and apply patch */ + if (!memcmp(src + 2, zero_parttern, 7 * sizeof(uint32_t))) + { + bsp_otp_prog((uint32_t *) fix_blank1, TCS_PATCH_BASE + 2, 1); + printf("-fix1 success\r\n"); + } + else if (!memcmp(src + 4, zero_parttern, 5 * sizeof(uint32_t))) + { + bsp_otp_prog((uint32_t *) fix_blank2, TCS_PATCH_BASE + 4, 1); + printf("-fix2 success\r\n"); + } + else + { + result = false; + printf("-fix fail\r\n"); + } + +exit: + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_close(); + + return result; +} + +static bool bsp_tcs_read_item (uint32_t item, uint32_t * dest) +{ + uint16_t item_size = 0; + + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + if (item > MAX_REG_ADDR) + { + bsp_tcs_get_item_in_otp_cs(item, dest, &item_size); + + if (item_size > 0) + { + return true; + } + else + { + return false; + } + } + else + { + bsp_tcs_get_item_in_otp_cs(item, dest, &item_size); + if (item_size > 0) + { + return true; + } + else + { + return false; + } + } +} + +static bool bsp_tcs_write_item (uint32_t item, uint32_t * dest, uint32_t word_size, check_option_t check_option) +{ + uint16_t otp_size = 0, size = 0; + uint16_t item_write_count; + uint32_t cs_start[2] = {CS_START_CMD, 0}; + uint32_t tmp_dest[30]; + uint32_t i; + bool ret = 0; + + if (word_size > 30) + { + return false; + } + + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + + switch (check_option) + { + case CHECK_OPTION_FORCE: + { + /* Force write */ + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + if (otp_size == 0) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(cs_start, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 2, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_close(); + ret = true; + } + else if (otp_size < (OTP_CS_SIZE - ((word_size + 1) * 4))) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + ret = true; + } + else + { + INFO_PRINTF("[TCS] Over size otp \r\n"); + ret = false; + } + + break; + } + + case CHECK_OPTION_EMPTY: + { + /* Write if only empty, success if write, */ + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + if (otp_size == 0) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(cs_start, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 2, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_close(); + ret = true; + } + else if ((otp_size < (OTP_CS_SIZE - ((word_size + 1) * 4))) && (item_write_count == 0)) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + ret = true; + } + else + { + ret = false; + } + + break; + } + + case CHECK_OPTION_DIFFERENT: + { + /* Write if different success if write to compare between existing mac and new mac */ + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + bsp_tcs_get_item_in_otp_cs(item, tmp_dest, &size); + if (otp_size == 0) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(cs_start, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 2, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_close(); + ret = true; + } + else if (memcmp(tmp_dest, dest, word_size * 4) == 0) + { + ret = false; + } + else if ((otp_size < (OTP_CS_SIZE - ((word_size + 1) * 4)))) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + ret = true; + } + else + { + ret = false; + } + + break; + } + + case CHECK_OPTION_SKIP_EXISTS: + { + /* Skip if already written */ + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + if (otp_size == 0) + { + ret = false; + } + else if ((item_write_count > 0)) + { + ret = true; + } + else if ((otp_size < (OTP_CS_SIZE - ((word_size + 1) * 4))) && (item_write_count == 0)) + { + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + bsp_otp_prog(&item, (OTP_CS_ADDRESS / 4) + otp_size / 4, 1); + bsp_otp_prog(dest, (OTP_CS_ADDRESS / 4) + otp_size / 4 + 1, word_size); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + ret = true; + } + else + { + ret = false; + } + + break; + } + + default: + { + /* For only test */ + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + bsp_tcs_get_item_in_otp_cs(item, tmp_dest, &size); + INFO_PRINTF( + "\t[TCS] -skip write item otp_size:%x(%d), item_write_count:%x, item:%lx, dest:%d, word_size:%lx\r\n", + otp_size / 4, + otp_size / 4, + item_write_count, + item, + (int) dest, + word_size); + INFO_PRINTF("\t[TCS] read: tmp_data -"); + + for (i = 0; i < word_size; i++) + { + INFO_PRINTF("%08lx,", tmp_dest[i]); + } + + INFO_PRINTF("\r\n"); + + ret = true; + break; + } + } + + bsp_tcs_get_otp_size(&otp_size, item, &item_write_count); + + bsp_otp_close(); + + return ret; +} + +/*********************************************************************************************************************** + * Exported global functions + **********************************************************************************************************************/ +void bsp_tcs_get_trim_values_from_cs (void) +{ + uint16_t size; + bsp_tcs_source_t source; + uint32_t value = CS_STOP_CMD; + uint8_t count = 0; + uint32_t i, j; + uint8_t gid_offset = 0; + uint16_t gid = 0; + +#if (BSP_FEATURE_BSP_USE_TCS == 0) + + return; +#endif + + init_tcs_attributes_array(); + + for (i = 0; i < FSP_ARRAY_LENGTH(tcs_parsing_order); i++) + { + source = tcs_parsing_order[i]; + + for (j = 0; j < source_data[source].num_sections; j++) + { + uint32_t address = source_data[source].section_addresses[j]; + if ((value = fetch_tcs_entry(source, address)) != CS_START_CMD) + { + continue; + } + else + { + break; + } + } + + if (value == CS_START_CMD) + { + break; + } + + tcs_source = source; + } + + if (value != CS_START_CMD) + { + + /* No CS found */ + return; + } + + current_tcs = &shared_tcs; + SYS_TCS_SHARED.tcs_attributes_size = sizeof(based_on_tcs_attributes) / sizeof(based_on_tcs_attributes[0]); + + size = get_size_of_cs(source); + + /* The calculated size in bytes, taking into account that one entry is 4 bytes */ + BSP_CHECK_DEBUG(size < CS_MAX_SIZE); + + /* Static allocation for tcs_data */ + tcs_data = SYS_TCS_SHARED.tcs_data; + + /* Convert sizes to offsets in the tcs table and + * set the sizes of the GID attributes */ + gid_offset = 0; + for (gid = 0; gid < BSP_TCS_GROUP_MAX; gid++) + { + if (SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size != 0) + { + SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].start = gid_offset; + gid_offset += SYS_TCS_SHARED.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size; + } + } + + /* store the tcs_data used size*/ + SYS_TCS_SHARED.tcs_data_size = gid_offset; + store_cs_attributes(source, CS_MAX_SIZE); + + /* Static allocation for tcs_data */ + current_tcs = retained_tcs; + tcs_data = SYS_TCS_RETAINED.tcs_data; + + for (i = 0; i < SYS_TCS_SHARED.tcs_attributes_size; i++) + { + if (SYS_TCS_SHARED.tcs_attributes[i].is_retained == RETAINED) + { + memcpy(&SYS_TCS_RETAINED.tcs_attributes[count], &SYS_TCS_SHARED.tcs_attributes[i], sizeof(bsp_tcs_attr_t)); + count++; + } + } + + memset(&SYS_TCS_RETAINED.tcs_attributes[count], 0, sizeof(bsp_tcs_attr_t)); + SYS_TCS_RETAINED.tcs_attributes_size = count + 1; + + /* Convert sizes to offsets in the tcs table and + * set the sizes of the GID attributes */ + gid_offset = 0; + for (gid = 0; gid < BSP_TCS_GROUP_MAX; gid++) + { + if ((SYS_TCS_RETAINED.tcs_attributes[bsp_retained_gid_to_idx(gid)].is_retained == RETAINED) && + (SYS_TCS_RETAINED.tcs_attributes[bsp_retained_gid_to_idx(gid)].size != 0)) + { + SYS_TCS_RETAINED.tcs_attributes[bsp_retained_gid_to_idx(gid)].start = gid_offset; + gid_offset += SYS_TCS_RETAINED.tcs_attributes[bsp_retained_gid_to_idx(gid)].size; + } + } + + /* store the tcs_data used size*/ + SYS_TCS_RETAINED.tcs_data_size = gid_offset; + store_cs_attributes(source, CS_MAX_SIZE); + + current_tcs = &shared_tcs; + tcs_data = SYS_TCS_SHARED.tcs_data; + SYS_TCS_RETAINED.cs_valid = CS_VALID_PATTERN; + SYS_TCS_SHARED.cs_valid = CS_VALID_PATTERN; +} + +void bsp_tcs_get_custom_values (bsp_tcs_gid_t gid, uint32_t ** values, uint8_t * size) +{ + if (bsp_based_gid_to_idx(gid) == (bsp_based_attributes_size() - 1)) + { + return; + } + + if (!bsp_tcs_set_tcs(gid, true)) + { + return; + } + + BSP_CHECK_DEBUG(gid < BSP_TCS_GROUP_MAX); + BSP_CHECK_DEBUG(SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].value_type == BSP_TCS_TYPE_TRIM_VAL); + + if (SYS_TCS.tcs_data == NULL) + { + + /* TCS is not initialize */ + return; + } + + if (size == NULL) + { + + /* size is mandatory */ + return; + } + + *size = SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size; + + if (values) + { + if (*size == 0) + { + *values = NULL; + } + else + { + /* if size is not zero then start is different than EMPTY for this GID + * so CS parsing for TCS data is done and TCS_DATA is valid */ + *values = &SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].start]; + } + } + + bsp_tcs_set_tcs(gid, false); +} + +bool bsp_tcs_apply_custom_values (bsp_tcs_gid_t gid, bsp_tcs_custom_values_cb cb, void * user_data) +{ + uint32_t * values = NULL; + uint8_t size = 0; + + if (bsp_based_gid_to_idx(gid) == (bsp_based_attributes_size() - 1)) + { + return false; + } + + if (based_on_tcs_attributes[bsp_based_gid_to_idx(gid)].is_retained == false) + { + current_tcs = &shared_tcs; + } + else + { + current_tcs = retained_tcs; + } + + if (SYS_TCS.cs_valid != CS_VALID_PATTERN) + { + return false; + } + + if (SYS_TCS.tcs_data == NULL) + { + return false; + } + + if (cb) + { + bsp_tcs_get_custom_values(gid, &values, &size); + if (size != 0) + { + cb(gid, user_data, values, size); + } + else + { + return false; + } + } + + current_tcs = &shared_tcs; + tcs_data = SYS_TCS_SHARED.tcs_data; + + return true; +} + +bool bsp_tcs_apply_reg_pairs (bsp_tcs_gid_t gid) +{ + if (bsp_based_gid_to_idx(gid) == bsp_based_attributes_size() - 1) + { + return false; + } + + if (based_on_tcs_attributes[bsp_based_gid_to_idx(gid)].is_retained == false) + { + current_tcs = &shared_tcs; + } + else + { + current_tcs = retained_tcs; + } + + if (SYS_TCS.cs_valid != CS_VALID_PATTERN) + { + return false; + } + + if (SYS_TCS.tcs_data == NULL) + { + return false; + } + + BSP_CHECK_DEBUG(gid < BSP_TCS_GROUP_MAX); + BSP_CHECK_DEBUG(SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].value_type == BSP_TCS_TYPE_REG_PAIR || + SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].value_type == BSP_TCS_TYPE_HPI_REG_PAIR); + + uint8_t start = SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].start; + int size = (int) SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].size; + + if (size == 0) + { + return false; + } + + if (SYS_TCS.tcs_attributes[bsp_tcs_gid_to_idx(gid)].value_type == BSP_TCS_TYPE_REG_PAIR) + { + while (size > 0) + { + if ((SYS_TCS.tcs_data[start]) != 0) + { + *(volatile uint32_t *) SYS_TCS.tcs_data[start] = SYS_TCS.tcs_data[start + 1]; + } + + size -= 2; + start += 2; + } + } + + current_tcs = &shared_tcs; + tcs_data = SYS_TCS_SHARED.tcs_data; + + return true; +} + +#if TCS_INFO +void bsp_tcs_info_printf (bool match) +{ + FSP_PARAMETER_NOT_USED(match); + uint32_t i, e, dest = 0; + uint16_t item_count = 0, size = 0, word_size = 0; + static const char * tcs_type[] = + { + "TYPE_TRIM_VAL", + "TYPE_REG_PAIR", + "TYPE_HPI_REG_PAIR", + "TYPE_RESERVE" + }; + static const char * tcs_domain[] = + { + "SYS_TCS_DOMAIN_PD_SYS", + "SYS_TCS_DOMAIN_PD_COM", + "SYS_TCS_DOMAIN_PD_MEM", + "SYS_TCS_DOMAIN_PD_TMR", + "SYS_TCS_DOMAIN_PD_PER", + "SYS_TCS_DOMAIN_PD_RAD", + "SYS_TCS_DOMAIN_PD_SYN", + "SYS_TCS_DOMAIN_NA" + }; + + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_tcs_get_trim_values_from_cs(); + current_tcs = &shared_tcs; + for (i = 0; i < sizeof(based_on_tcs_attributes) / sizeof(based_on_tcs_attributes[0]); i++) + { + if (SYS_TCS.tcs_attributes[i].size > 0) + { + INFO_PRINTF("Group ID = %x, TYPE = %s, domain = %s, RETAINED %ud\r\n", + SYS_TCS.tcs_attributes[i].value_gid, + tcs_type[SYS_TCS.tcs_attributes[i].value_type], + tcs_domain[SYS_TCS.tcs_attributes[i].value_domain], + SYS_TCS.tcs_attributes[i].is_retained); + if (SYS_TCS.tcs_attributes[i].value_type == BSP_TCS_TYPE_REG_PAIR) + { + for (e = 0; e < SYS_TCS.tcs_attributes[i].size; e += 2) + { + INFO_PRINTF("%08lx - %08lx", + SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e], + SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e + 1]); + INFO_PRINTF(" : matched %d(%lx)\r\n", + *(volatile uint32_t *) SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e] == + SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e + 1], + *(volatile uint32_t *) SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e]); + } + } + else + { + for (e = 0; e < SYS_TCS.tcs_attributes[i].size; e++) + { + INFO_PRINTF("%08lx\r\n", SYS_TCS.tcs_data[SYS_TCS.tcs_attributes[i].start + e]); + } + } + } + } + + INFO_PRINTF("\r\n - INFO \r\n"); + bsp_tcs_get_item_in_otp_cs(XTAL_REG, &dest, &word_size); + INFO_PRINTF("XTAL40M_CTRL_REG(0x400c0204) = %lx\r\n", dest); + bsp_tcs_get_otp_size(&size, XTAL_REG, &item_count); + INFO_PRINTF("OTP Start Address: 0x400f2100, top =%x(%d), otp size = %x(%d), \r\n", (OTP_CS_ADDRESS + size) / 4, + (OTP_CS_ADDRESS + size) / 4, size / 4, size / 4); + + INFO_PRINTF("\r\n - RAW DATA \r\n"); + for (i = 0; i < (uint32_t) (size / 4 + 1); i++) + { + INFO_PRINTF("%08lx, ", *(volatile uint32_t *) (MEMORY_OTP_BASE + OTP_CS_ADDRESS + i * 4)); + if ((i % 4 == 3) && (i != 0)) + { + INFO_PRINTF("\r\n"); + } + } + + INFO_PRINTF("\r\n"); +} + +#endif + +bool bsp_tcs_otp_read_xtal (uint32_t * dest) +{ + return bsp_tcs_read_item(XTAL_REG, dest); +} + +bool bsp_tcs_otp_write_xtal (uint32_t * dest, check_option_t check_option) +{ + *dest = ((*dest & 0xff0000) | 0x76f); + + return bsp_tcs_write_item(XTAL_REG, dest, 1, check_option); +} + +bool bsp_tcs_otp_read_mac (uint32_t * mac) +{ + return bsp_tcs_read_item(BSP_TCS_GROUP_MAC_ADDR | (2 << 8) | (CS_SDK_VAL), mac); +} + +bool bsp_tcs_otp_write_mac (uint32_t * mac, check_option_t check_option) +{ + return bsp_tcs_write_item(BSP_TCS_GROUP_MAC_ADDR | (2 << 8) | (CS_SDK_VAL), mac, 2, check_option); +} + +uint16_t bsp_tcs_otp_mac_cnt (void) +{ + uint16_t otp_size = 0; + uint16_t item_write_count; + + bsp_tcs_get_otp_size(&otp_size, BSP_TCS_GROUP_MAC_ADDR | (2 << 8) | (CS_SDK_VAL), &item_write_count); + + return item_write_count; +} + +uint32_t bsp_tcs_read_timestamp (void) +{ + uint8_t size; + uint32_t * cs_timestamp_ptr = NULL; + + bsp_tcs_get_custom_values(BSP_TCS_GROUP_PROD_INFO, &cs_timestamp_ptr, &size); + if (size == 0) + { + return 0; + } + + return cs_timestamp_ptr[1]; +} + +uint32_t bsp_tcs_read_program_version (void) +{ + uint8_t size; + uint32_t * cs_program_version_ptr = NULL; + + bsp_tcs_get_custom_values(BSP_TCS_GROUP_TESTPROGRAM_VERSION, &cs_program_version_ptr, &size); + if (size == 0) + { + return 0; + } + + return *cs_program_version_ptr; +} + +uint32_t bsp_tcs_read_wafer (void) +{ + uint8_t size; + uint32_t * cs_wafer_ptr = NULL; + bsp_tcs_get_custom_values(BSP_TCS_GROUP_PROD_WAFER, &cs_wafer_ptr, &size); + if (size == 0) + { + return 0; + } + + return *cs_wafer_ptr; +} + +bool bsp_tcs_otp_add (uint32_t * dest, uint32_t word_size) +{ + uint16_t otp_size = 0; + uint16_t item_write_count; + uint32_t cs_start[2] = {CS_START_CMD, 0}; + bool ret = 0; + + if (!dest || (word_size == 0) || (word_size > 30)) + { + return false; + } + + bsp_otp_init(); + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_tcs_get_otp_size(&otp_size, 0, &item_write_count); + + if (otp_size == 0) + { + t2_production_patch(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + + /* First write - need to write start pattern */ + uint32_t write_offset = (OTP_CS_ADDRESS / 4); + bsp_otp_prog(cs_start, write_offset, 1); + bsp_otp_prog(dest, write_offset + 1, word_size); + + ret = true; + } + else if (otp_size < (OTP_CS_SIZE - (word_size * 4))) + { + t2_production_patch(); + bsp_otp_mode_set(BSP_OTP_MODE_PROG); + + uint32_t write_offset = (OTP_CS_ADDRESS / 4) + otp_size / 4;; + bsp_otp_prog(dest, write_offset, word_size); + ret = true; + } + else + { + INFO_PRINTF("[TCS] Over size otp \r\n"); + ret = false; + } + + bsp_otp_mode_set(BSP_OTP_MODE_READ); + bsp_otp_close(); + + return ret; +} + +void bsp_tcs_custom_values_system_cb (bsp_tcs_gid_t gid, void * user_data, uint32_t * val, uint8_t len) +{ + FSP_PARAMETER_NOT_USED(gid); + FSP_PARAMETER_NOT_USED(user_data); + FSP_PARAMETER_NOT_USED(val); + FSP_PARAMETER_NOT_USED(len); +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.h new file mode 100644 index 000000000000..ed26beaf0aee --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/bsp_tcs.h @@ -0,0 +1,346 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_TCS_RA6W1_H +#define BSP_TCS_RA6W1_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define TCS_ATTRIBUTE_SIZE 20 +#define TCS_DATA_SIZE 200 /**< max number of entries in words (4 bytes). */ +#define GID_EMPTY 0x1FF + +/* + * Reset values of trimmed registers + */ +#define DEFAULT_CHARGER_TEST_CTRL_REG 0x00001F28 + +/* + * OTP Memory + */ +#define MEMORY_OTP_BASE 0x400F2000UL +#define MEMORY_OTP_END 0x400F2800UL + +/* + * OQSPI AHB-C(ode) bus (cached). Accesses through this bus + * are restricted according to CACHE_FLASH_REG. + */ +#define MEMORY_OQSPIC_BASE (0x0A000000) // before (0x19000000UL) +#define MEMORY_OQSPIC_END (0x0DFFFFFF) // before (0x1D000000UL) + +#define MEMORY_OQSPIC_SIZE (MEMORY_OQSPIC_END - MEMORY_OQSPIC_BASE) + +/* + * OQSPI AHB-S(ystem) bus (Not cached). Accesses through this bus + * are not affected by CACHE_FLASH_REG. + */ +#define MEMORY_OQSPIC_S_BASE (0x2A000000) // before (0x3A000000UL) +#define MEMORY_OQSPIC_S_END (0x2DFFFFFF) // before (0x3E000000UL) + +/* + * QSPI AHB-C(ode) bus (cached). Accesses through this bus + * are restricted according to CACHE_FLASH_REG. + */ +#define MEMORY_QSPIF_BASE (0x24000000UL) +#define MEMORY_QSPIF_END (MEMORY_QSPIF_BASE + 0x4000000UL) + +/* + * QSPI Data + */ +#define MEMORY_QSPID_BASE (0x24000000UL) +#define MEMORY_QSPID_END (0x28000000UL) +#define MEMORY_QSPID_SIZE (MEMORY_QSPID_END - MEMORY_QSPID_BASE) + +/* + * DCACHE controller + */ +#define MEMORY_DCACHE_BASE (0x21014000UL) +#define MEMORY_DCACHE_SIZE (0x2000UL) +#define MEMORY_DCACHE_END (MEMORY_DCACHE_BASE + MEMORY_DCACHE_SIZE) + +#define TCS_INFO 1 + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @enum bsp_tcs_type_t + * @brief custom TCS value type. + */ +typedef enum +{ + BSP_TCS_TYPE_TRIM_VAL = 0, /**< trimmed value */ + BSP_TCS_TYPE_REG_PAIR = 1, /**< register pair value */ + BSP_TCS_TYPE_HPI_REG_PAIR = 2, + BSP_TCS_TYPE_RESERVED = 3, +} bsp_tcs_type_t; + +/** + * @enum bsp_tcs_domain_t + * @brief power domain of each TCS group. + */ +typedef enum +{ + BSP_TCS_DOMAIN_PD_SYS = 0, /**< System power domain */ + BSP_TCS_DOMAIN_PD_COM, /**< Communication power domain */ + BSP_TCS_DOMAIN_PD_MEM, /**< Memory power domain */ + BSP_TCS_DOMAIN_PD_TMR, /**< Timers power domain */ + BSP_TCS_DOMAIN_PD_PER, /**< Peripherals power domain */ + BSP_TCS_DOMAIN_PD_RAD, /**< Radio power domain */ + BSP_TCS_DOMAIN_PD_SYNTH, /**< Synth power domain */ + BSP_TCS_DOMAIN_NA /**< No power domain */ +} bsp_tcs_domain_t; + +/** + * @enum bsp_tcs_gid_t + * @brief the configured group ids. + */ +typedef enum +{ + BSP_TCS_GROUP_RESERVED = 0x0, + BSP_TCS_GROUP_COMMON = 0x1, + BSP_TCS_GROUP_SKIP = 0x2, + + /* Power Domains Section */ + BSP_TCS_GROUP_PD_SYS = 0x20, + BSP_TCS_GROUP_MAC_ADDR = 0x21, + BSP_TCS_GROUP_PD_ADC = 0x22, + BSP_TCS_GROUP_PD_WIFI_TRIM_RF_HPI = 0x81, + BSP_TCS_GROUP_PD_WIFI_TRIM_TX_HPI = 0x82, + BSP_TCS_GROUP_PD_WIFI_TRIM_DCORE = 0x80, + BSP_TCS_GROUP_PD_WIFI_TRIM_LUT = 0x83, + BSP_TCS_GROUP_PD_WIFI_TRIM_TXIQ = 0x84, + BSP_TCS_GROUP_PD_WIFI_TRIM_XTAL = 0x90, + + /* System Section */ + BSP_TCS_GROUP_BD_ADDR = 0x20, /**< BD_ADDR group id */ + + /* Production Test Section */ + BSP_TCS_GROUP_CHIP_ID = 0xC0, /**< CHIP_ID group id */ + BSP_TCS_GROUP_PROD_INFO = 0xC1, /**< PROD_INFO group id */ + BSP_TCS_GROUP_PROD_WAFER = 0xC2, /**< PROD_WAFER group id */ + BSP_TCS_GROUP_TESTPROGRAM_VERSION = 0xC3, /**< TESTPROGRAM_VERSION group id */ + BSP_TCS_GROUP_PROD_SW_IP = 0xC4, /**< PROD_SW_IP group id */ + + BSP_TCS_GROUP_MAX = 0xE0 /**< Maximum supported group id */ +} bsp_tcs_gid_t; + +/** + * @struct bsp_tcs_source_t + * @brief Parsing order for the configuration script + */ +typedef enum +{ + BSP_TCS_OTP = 0, /* CS in OTP */ + BSP_TCS_OQSPI, /* CS in Flash */ + BSP_TCS_QSPI, /* CS in QSPI Flash */ + BSP_TCS_NVMS, /* CS in NVMS */ +} bsp_tcs_source_t; + +typedef enum e_check_option +{ + CHECK_OPTION_FORCE = 0, ///< Force write + CHECK_OPTION_EMPTY = 1, ///< Write if only empty item. + CHECK_OPTION_DIFFERENT = 2, ///< Write if only different item. + CHECK_OPTION_SKIP_EXISTS = 3, ///< Skip if already written +} check_option_t; + +/** + * @struct bsp_tcs_attr_t + * @brief attributes per custom value group id + */ +typedef struct +{ + uint32_t value_gid : 8; /* bsp_tcs_gid_t */ + uint32_t value_type : 2; /* bsp_tcs_type_t - < TCS entry type */ + uint32_t value_domain : 4; /* bsp_tcs_domain_t */ + uint32_t is_retained : 2; + uint32_t start : 8; /* < TCS entry start position */ + uint32_t size : 8; /* < TCS entry type size in words */ +} bsp_tcs_attr_t; + +/** + * @struct bsp_tcs_shared_t + * @brief This structure is used to hold the TCS shared-memory data in specific order + * to prevent compiler optimization when building for both (SYSCPU and CMAC) CPUs. + */ +typedef struct +{ + uint32_t * tcs_data; /*!< The CS data as read by the TCS parser */ + uint8_t tcs_data_size; /*!< Number of words in the tcs_data */ + uint8_t tcs_attributes_size; + bsp_tcs_attr_t * tcs_attributes; /*!< The TCS attributes */ + uint16_t cs_otp_program_version; /*!< The version of the CS as described by the BSP_TCS_GROUP_TESTPROGRAM_VERSION attribute*/ + uint16_t cs_valid; +} bsp_tcs_shared_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief TCS custom trim values callback + * @param[in] values_group the TCS group id custom trim values belong to + * @param[in] user_data user specific data + * @param[in] values custom trim values + * @param[in] size the number of the custom trim values + */ +typedef void (* bsp_tcs_custom_values_cb)(bsp_tcs_gid_t values_group, void * user_data, uint32_t * values, + uint8_t size); + +/** + * @brief retrieve the TCS values from CS located in OTP or flash and then store + * TCS register pair address, value and/or custom value custom_trim_value in the Global TCS array + */ +void bsp_tcs_get_trim_values_from_cs(void); + +/** + * @brief Reads the timestamp from the parsed CS + * + * @returns The timestamp value. The function returns 0 in case timestamp does not exist in the CS + */ +uint32_t bsp_tcs_read_timestamp(void); + +/** + * @brief Reads the program version from the parsed CS + * + * @returns The version number. The function returns 0 in case version does not exist in the CS\n + * Example: 01000501 The program revision is 1.00.05.01 + */ +uint32_t bsp_tcs_read_program_version(void); + +/** + * @brief Reads the Wafer position from the parsed CS + * + * @returns The wafer position. The function returns 0 in case wafer does not exist in the CS\n + * B2: Wafer number B1: Y coord B0: X coord. if this is QFN or BGA, it is 0. + */ +uint32_t bsp_tcs_read_wafer(void); + +/** + * @brief Get register value pairs contained in a group id of the TCS array + * @param[in] gid the group id + * @param[out] values the pointer to the start of the register pair values + * @param[out] size the number of the register pair values + * + * @warning if size is zero then values is not a valid pointer. size should have been + * initialized to zero + */ +void bsp_tcs_get_reg_pairs(bsp_tcs_gid_t gid, uint32_t ** values, uint8_t * size); + +/** + * @brief Get the custom_trim_values per gid + * + * @param[in] gid the TCS group id of the requested custom trim values + * @param[out] values the pointer to the start of the custom trim values + * @param[out] size the number of the custom trim values + * + * @warning if size is zero then there are no custom trim values for this gid, + * values points to invalid data. size should have been initialized to zero + */ +void bsp_tcs_get_custom_values(bsp_tcs_gid_t gid, uint32_t ** values, uint8_t * size); + +/** + * @brief Apply the register value pairs contained in a group id of the TCS array. + * @param [in] gid the group id + */ +bool bsp_tcs_apply_reg_pairs(bsp_tcs_gid_t gid); + +/** + * @brief handles the custom_trim_values per gid according to callback + * + * @param[in] gid the TCS group id of custom trim values to apply + * @param[in] cb the callback that applies the custom trim values + * @param[in] user_data the argument to callback function + * + * @warning callback is called only if custom trim values are configured + */ +bool bsp_tcs_apply_custom_values(bsp_tcs_gid_t gid, bsp_tcs_custom_values_cb cb, void * user_data); + +/** + * @brief Retrieve the configured group ids belong to a specific power domain + * + * @param[in] domain the power domain + * @param[out] gids pointer to the array which will filled with the group ids. + * @param[in] size the length of the gids + * The last valid entry in the array is before BSP_TCS_GROUP_RESERVED which marks the end. + */ +void bsp_tcs_get_gid_per_domain(bsp_tcs_domain_t domain, uint8_t * gids, uint8_t size); + +/** + * @brief handles the custom_trim_values per gid according to callback + * + * @param[in] gid the TCS group id of custom trim values to apply + * @param[in] user_data the argument to callback function + * @param[in] val pointer to the returned values + * @param[in] len size of returned values (bytes) + * + * @warning callback is called only if custom trim values are configured + */ +void bsp_tcs_custom_values_system_cb(bsp_tcs_gid_t gid, void * user_data, uint32_t * val, uint8_t len); + +/** + * @brief Read XTAL_REG value on TCS + * + * @param[out] dest XTAL regiter value + */ +bool bsp_tcs_otp_read_xtal(uint32_t * dest); + +/** + * @brief Write XTAL_REG value on TCS + * + * @param[in] dest XTAL regiter value + * @param[in] check_option TCS written check option + */ +bool bsp_tcs_otp_write_xtal(uint32_t * dest, check_option_t check_option); + +/** + * @brief Read MAC address on TCS + * + * @param[out] mac MAC address array - uint32_t mac[2] + */ +bool bsp_tcs_otp_read_mac(uint32_t * mac); + +/** + * @brief Write MAC address on TCS + * + * @param[in] mac MAC address array -uint32_t mac[2] + * @param[in] check_option TCS written check option + */ +bool bsp_tcs_otp_write_mac(uint32_t * mac, check_option_t check_option); + +/** + * @brief Read MAC written count on TCS + * + * @return the number of MAC written count + */ +uint16_t bsp_tcs_otp_mac_cnt(void); + +/** + * @brief Add data to TCS (Trim Calibration Section) on OTP + * + * @param[in] dest Pointer to data array to be added to TCS + * @param[in] word_size Size of data in 32-bit words + * + * @return true if data was successfully added to TCS + * @return false if addition failed + * + * @note This function adds the provided data to the TCS of OTP area. + * The data must be aligned to 32-bit words. + */ +bool bsp_tcs_otp_add(uint32_t * dest, uint32_t word_size); + +#if TCS_INFO +void bsp_tcs_info_printf(bool match); + +#endif +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/clib.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/clib.h new file mode 100644 index 000000000000..a4be4bd32cad --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/clib.h @@ -0,0 +1,125 @@ +/** + **************************************************************************************** + * + * @file clib.h + * + * @brief C Library + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __clib_h__ +#define __clib_h__ + +#include + +#include "bsp_api.h" +#include "bsp_sflash_map_ra6w1.h" + +__STATIC_INLINE unsigned char toint (char c) +{ + unsigned char rslt; + + if ((c >= '0') && (c <= '9')) + { + rslt = (c - '0'); + } + else if ((c >= 'a') && (c <= 'f')) + { + rslt = (c - 'a' + (unsigned char) 10); + } + else if ((c >= 'A') && (c <= 'F')) + { + rslt = (c - 'A' + (unsigned char) 10); + } + else + { + rslt = (unsigned char) 0; + } + + return rslt; +} + +__STATIC_INLINE unsigned int htoi (char * s) +{ + unsigned int sum = 0; + + while ((*s >= '0') && (*s <= 'f')) + { + sum = sum * 16 + toint(*s++); + } + + return sum; +} + +__STATIC_INLINE int btoi (char * s) +{ + short sum = 0; + + while ((*s >= '0') && (*s <= '1')) + { + sum = (short) (sum * 2 + toint(*s++)); + } + + return sum; +} + +__STATIC_INLINE unsigned int ctoi (char * s) +{ + unsigned int sum = 0; + + while ((*s >= '0') && (*s <= '9')) + { + sum = sum * 10 + toint(*s++); + } + + return sum; +} + +__STATIC_INLINE int stoi (char * s) +{ + int sum = 0, sign; + + if (*s == '-') + { + sign = -1; + s++; + } + else + { + sign = 1; + } + + while (*s) + { + sum = sum * 10 + toint(*s++); + } + + sum = sign * sum; + + return sum; +} + +#endif /* __clib_h__ */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_compile_opt.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_compile_opt.h new file mode 100644 index 000000000000..07763511ea36 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_compile_opt.h @@ -0,0 +1,41 @@ +/** + **************************************************************************************** + * + * @file common_compile_opt.h + * + * @brief Define for common system features + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __COMMON_COMPILE_OPT__ +#define __RA6WX_COMPILE_OPT__ + +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wsign-conversion" + +#endif // __COMMON_COMPILE_OPT__ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_def.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_def.h new file mode 100644 index 000000000000..bbd7b3636024 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/common_def.h @@ -0,0 +1,764 @@ +/** + **************************************************************************************** + * + * @file common_def.h + * + * @brief Define for common variables for SDK + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __COMMON_DEF_H__ + #define __COMMON_DEF_H__ + + #include "FreeRTOS.h" + #include "sdk_defs.h" + #ifdef RM_STDIO_W + #include "rm_stdio_w_cfg.h" + #endif + #ifdef RM_MAP_PERSISTANT_W + #include "rm_map_persistant_w.h" + #endif + + #define NVR_MAGIC_CODE 0x7E7EBEAF + #define NVR_KEY_MAGIC_CODE "INIT_MAGIC" + + #define NVR_KEY_SETUP_MODE "SETUP_MODE" + + #define NVR_KEY_SYSMODE ENV_SYS_MODE + + #define NVR_KEY_PROFILE_0 "N0_Profile" + #define NVR_KEY_PROFILE_1 "N1_Profile" + + #define NVR_KEY_SSID_0 "N0_ssid" + #define NVR_KEY_SSID_1 "N1_ssid" + #define NVR_KEY_MODE_0 "N0_mode" + #define NVR_KEY_MODE_1 "N1_mode" + #define NVR_KEY_NETMODE_0 "0:NETMODE" + #define NVR_KEY_NETMODE_1 "1:NETMODE" + #define NVR_KEY_COUNTRY_CODE "country_code" + #define NVR_KEY_IPADDR_0 "0:IP_Address" + #define NVR_KEY_IPADDR_1 "1:IP_Address" + #define NVR_KEY_NETMASK_0 "0:NETMASK" + #define NVR_KEY_NETMASK_1 "1:NETMASK" + #define NVR_KEY_GATEWAY_0 "0:GATEWAY" + #define NVR_KEY_GATEWAY_1 "1:GATEWAY" + #define NVR_KEY_DNSSVR_0 "0:DNSSVR" + #define NVR_KEY_DNSSVR_0_2ND "0:DNSSVR2" + #define NVR_KEY_DNSSVR_1 "1:DNSSVR" + #define NVR_KEY_DHCPD "USEDHCPD" + #define NVR_KEY_DHCPD_IPCNT "DHCPD_IPCNT" + + #define NVR_KEY_DHCP_S_IP "1:DHCPD_S_IP" + #define NVR_KEY_DHCP_E_IP "1:DHCPD_E_IP" + #define NVR_KEY_DHCP_TIME "1:DHCPD_TIME" + #define NVR_KEY_DHCP_DNS_IP "1:DHCPD_DNS" + #define NVR_KEY_DHCP_RESP_DELAY "1:DHCPD_RESP_DELAY" + + #define NVR_KEY_DPM_MODE "dpm_mode" + #define NVR_KEY_DPM_KEEPALIVE_TIME "DPM_KEEPALIVE" + #define NVR_KEY_DPM_USER_WAKEUP_TIME "DPM_USER_WU_TIME" + #define NVR_KEY_DPM_TIM_WAKEUP_TIME "DPM_TIM_WU_TIME" + #define NVR_KEY_DPM_AB_WF_CONN_RETRY "DPM_AB_WIFI_CONN_RETRY_CNT" + #define NVR_KEY_DPM_ABNORM_STOP "dpm_abnorm_stop" + #define NVR_KEY_DPM_IP_CONDITION "dpm_ip_condition" + + #define WIFI_CONN_WAIT_NAME "DPM_AB_WIFI_CONN_WAIT" + #define DHCP_RSP_WAIT_NAME "DPM_AB_DHCP_RSP_WAIT" + #define ARP_RSP_WAIT_NAME "DPM_AB_ARP_RSP_WAIT" + #define UNKNOWN_DPM_FAIL_WAIT_NAME "DPM_AB_DPM_FAIL_WAIT" + #define WIFI_CONN_RETRY_CNT_NAME "DPM_AB_WIFI_CONN_RETRY_CNT" + +/* + * For DPM abnormal functions ... + */ + #define DPM_ABNORM_WIFI_CONN_WAIT 0 + #define DPM_ABNORM_DHCP_RSP_WAIT 1 + #define DPM_ABNORM_ARP_RSP_WAIT 2 + #define DPM_ABNORM_DPM_FAIL_WAIT 3 + #define DPM_ABNORM_DPM_WIFI_RETRY_CNT 4 + + #define NVR_UART2_MONITOR_DISABLE "UART2_MONITOR_DISABLE" + + #define NVR_KEY_DL_CLI_PERIOD "dl_cli_period" + #define NVR_KEY_DL_SVC_SVR_IP "dl_svc_svr_ip" + + #define NVR_KEY_IPERF_C "USEIPERF" + + #define NVR_KEY_CoAP "USECoAP" + #define NVR_KEY_HTTP_S "USEHTTPServer" + #define NVR_KEY_ICMP_S "USEICMPServer" + #define NVR_KEY_ICMP_C "USEICMPClient" + #define NVR_KEY_ACS "USEACS" + #define NVR_KEY_SNTP_C "SNTP_RUN_FLAG" + #define NVR_KEY_DHCP_C "USEDHCPClient" + #define NVR_KEY_CHANNEL "N1_frequency" + #define NVR_KEY_PROACTKEY_C "N1_proActKeyCaching" + + #define NVR_KEY_SNTP_SERVER_DOMAIN "SNTP_SVR" + #define NVR_KEY_SNTP_SERVER_DOMAIN_1 "SNTP_SVR_1" + #define NVR_KEY_SNTP_SERVER_DOMAIN_2 "SNTP_SVR_2" + #define NVR_KEY_SNTP_SYNC_PERIOD "SNTP_PERIOD" + + #define NVR_KEY_TIMEZONE "TZONE" + #define NVR_KEY_OTA_UPDATE "OTA_Update" + #define NVR_KEY_OTA_TIMEOUT "OTA_op_timeout" + #define NVR_KEY_OTA_UP_SVR_DOMAIN "OTA_Svr_Domain" + #define NVR_KEY_OTA_UP_SVR_IP "OTA_Svr_IP" + #define NVR_KEY_OTA_PTIM "OTA_ptim" + #define NVR_KEY_OTA_RAMLIB "OTA_rlib" + #define NVR_KEY_OTA_RTOS "OTA_rtos" + #define NVR_KEY_OTA_INDOOR "OTA_indoor" + #define NVR_KEY_OTA_OUTDOOR "OTA_outdoor" + + #define NVR_KEY_OTA_UPDATE_PERIOD "OTA_Period" + #define NVR_KEY_WLANMODE_0 "N0_wifi_mode" + #define NVR_KEY_WLANMODE_1 "N1_wifi_mode" + + #define NVR_KEY_AUTH_TYPE_0 "N0_key_mgmt" + #define NVR_KEY_ENC_TYPE_0 "N0_pairwise" + + #define NVR_KEY_WEPTYPE_0 "N0_wep_type" /* need del */ + #define NVR_KEY_WEPINDEX_0 "N0_wep_tx_keyidx" /* chg */ + #define NVR_KEY_WEPKEYTYPE_0 "N0_wepkey_type" /* need del */ + #define NVR_KEY_WEPKEY64_0 "N0_wep_key" /* need del */ + #define NVR_KEY_WEPKEY128_0 "N0_wep_key" /* need del */ + #define NVR_KEY_WEPKEY_0 "N0_wep_key" /* chg */ + #define NVR_KEY_WEPKEY0_0 "N0_wep_key0" /* chg */ + #define NVR_KEY_WEPKEY1_0 "N0_wep_key1" /* chg */ + #define NVR_KEY_WEPKEY2_0 "N0_wep_key2" /* chg */ + #define NVR_KEY_WEPKEY3_0 "N0_wep_key3" /* chg */ + + #define NVR_KEY_ENCKEY_0 "N0_psk" + +// for __SUPPORT_FAST_CONN_SLEEP_12__ + #define NVR_KEY_PSK_RAW_0 "N0_PSK_RAW_KEY" + + #define NVR_KEY_PROTO_0 "N0_proto" + #define NVR_KEY_SAE_PASS_0 "N0_sae_password" + #define NVR_KEY_PMF_0 "N0_ieee80211w" + + #define NVR_KEY_AUTH_TYPE_1 "N1_key_mgmt" + #define NVR_KEY_ENC_TYPE_1 "N1_pairwise" + + #define NVR_KEY_WEPTYPE_1 "N1_wep_type" /* need del */ + #define NVR_KEY_WEPINDEX_1 "N1_wep_tx_keyidx" /* chg */ + #define NVR_KEY_WEPKEYTYPE_1 "N1_wepkey_type" /* need del */ + #define NVR_KEY_WEPKEY64_1 "N1_wep_key" /* need del */ + #define NVR_KEY_WEPKEY128_1 "N1_wep_key" /* need del */ + #define NVR_KEY_WEPKEY_1 "N1_wep_key" /* chg */ + #define NVR_KEY_WEPKEY0_1 "N1_wep_key0" /* chg */ + #define NVR_KEY_WEPKEY1_1 "N1_wep_key1" /* chg */ + #define NVR_KEY_WEPKEY2_1 "N1_wep_key2" /* chg */ + #define NVR_KEY_WEPKEY3_1 "N1_wep_key3" /* chg */ + + #define NVR_KEY_ENCKEY_1 "N1_psk" + #define NVR_KEY_PROTO_1 "N1_proto" + + #define NVR_KEY_SAE_PASS_1 "N1_sae_password" + #define NVR_KEY_PMF_1 "N1_ieee80211w" + #define NVR_KEY_GROUP_0 "N0_group" + #define NVR_KEY_GROUP_1 "N1_group" + + #define NVR_KEY_P2P_GO "P2P_GO" + #define NVR_KEY_P2P_DEV_NAME "dev_name" + #define NVR_KEY_P2P_LISTEN_CH "p2p_listen_channel" + #define NVR_KEY_P2P_GO_INTENT "p2p_go_intent" + #define NVR_KEY_P2P_GO_OP_CH "p2p_oper_channel" + +// for __SUPPORT_FAST_CONN_SLEEP_12__ + #define NVR_KEY_FST_CONNECT "N0_FST_CONNECT" /* Station Only */ + +// for __SUPPORT_ASSOC_CHANNEL__ + #define NVR_KEY_ASSOC_CH "N0_ASSOC_CH" /* Station Only */ + + #define NVR_KEY_VOL_UID "VOL_UID" + + #define NVR_KEY_DBG_TXPWR "DBG_TXPWR_L" + #define NVR_KEY_DBG_TXPWR_2G_OFDM "DBG_TXPWR_L_2GO" + #define NVR_KEY_DBG_TXPWR_2G_DSSS "DBG_TXPWR_L_2GD" + #define NVR_KEY_DBG_TXPWR_5G_PWR "DBG_TXPWR_L_5GP" + #define NVR_KEY_DBG_TXPWR_5G_FLAG "DBG_TXPWR_L_5GF" + + #define NVR_KEY_PWR_CTRL "pwr_ctrl_grade" + #define NVR_KEY_PWR_CTRL_SAME_IDX_TBL "SAME_PWR_IDX_VAL" /* same index value table */ + + #define CLI_DELIMIT_TAB "\t" + + #define ENABLE_DHCP_CLIENT DHCPCLIENT + #define ENABLE_STATIC_IP STATIC_IP + + #define CHANNEL_1_FREQ 2412 + #define CHANNEL_2_FREQ 2417 + #define CHANNEL_3_FREQ 2422 + #define CHANNEL_4_FREQ 2427 + #define CHANNEL_5_FREQ 2432 + #define CHANNEL_6_FREQ 2437 + #define CHANNEL_7_FREQ 2442 + #define CHANNEL_8_FREQ 2447 + #define CHANNEL_9_FREQ 2452 + #define CHANNEL_10_FREQ 2457 + #define CHANNEL_11_FREQ 2462 + #define CHANNEL_12_FREQ 2467 + #define CHANNEL_13_FREQ 2472 + #define CHANNEL_14_FREQ 2484 + + #define MODE_AUTH_OPEN_STR "NONE" + #define MODE_AUTH_WEP_STR "????" + #define MODE_AUTH_WPA_PSK_STR "WPA-PSK" + #define MODE_AUTH_WPA2_PSK_STR "?????" + #define MODE_AUTH_WPA_AUTO_PSK_STR "??????" + + #define proto_WPA "WPA" + #define proto_RSN "RSN" + #define proto_WPA2 "WPA2" + #define proto_OSEN "OSEN" + + #define key_mgmt_WPA_PSK "WPA-PSK" + #define key_mgmt_WPA_EAP "WPA-EAP" + #define key_mgmt_IEEE8021X "IEEE8021X" + #define key_mgmt_NONE "????" + #define key_mgmt_WPA_NONE "WPA-NONE" + #define key_mgmt_FT_PSK "FT-PSK" + #define key_mgmt_FT_EAP "FT-EAP" + #define key_mgmt_WPA_PSK_SHA256 "WPA-PSK-SHA256" + #define key_mgmt_WPA_EAP_SHA256 "WPA-EAP-SHA256" + #define key_mgmt_WPS "WPS" + #define key_mgmt_WPA3_OWE "OWE" + #define key_mgmt_WPA3_SAE "SAE" + #define key_mgmt_WPA_PSK_WPA3_SAE "WPA-PSK SAE" + #define key_mgmt_WPA3_ENT192B "WPA-EAP-SUITE-B-192" + + #define pairwise_CCMP "CCMP" + #define pairwise_TKIP "TKIP" + #define pairwise_GCMP_256 "GCMP-256" + #define group_TKIP_CCMP "TKIP WEP104 WEP40" + + #define MODE_11BGN 0 + #define MODE_11GN 1 + #define MODE_11BG 2 + #define MODE_11N 3 + #define MODE_11G 4 + #define MODE_11B 5 + + #define MODE_AUTH_OPEN 0 + #define MODE_AUTH_WEP 1 + #define MODE_AUTH_WPA_PSK 2 + #define MODE_AUTH_WPA2_PSK 3 + #define MODE_AUTH_WPA_AUTO_PSK 4 + + #define MODE_WEP_64 0 + #define MODE_WEP_128 1 + + #define MODE_WEP_TYPE_ASCII 0 + #define MODE_WEP_TYPE_HEXA 1 + + #define MODE_WEP_INDEX0 0 + #define MODE_WEP_INDEX1 1 + #define MODE_WEP_INDEX2 2 + #define MODE_WEP_INDEX3 3 + + #define MODE_ENC_TKIP 0 + #define MODE_ENC_AES 1 + #define MODE_ENC_AUTO 2 + + #define MODE_ENABLE 1 + #define MODE_DISABLE 0 + + #define SNTPCLINET_ENABLE 1 + #define SNTPCLINET_DISABLE 0 + + #define VIRTUAL_DEV0 0 + #define VIRTUAL_DEV1 1 + #define VIRTUAL_DEV2 2 + #define VIRTUAL_DEV3 3 + +/****************************/ +/*** Default value/string ***/ +/****************************/ + #define DFLT_SYSMODE WIFI_DEVICE_MODE_EXT_AP + #define DFLT_WLANMODE MODE_11BGN + #define DFLT_MODE_AUTH MODE_AUTH_OPEN + #define DFLT_MODE_AUTH_STR MODE_AUTH_OPEN_STR + #define DFLT_MODE_WEP MODE_WEP_128 + #define DFLT_MODE_WEP_TYPE MODE_WEP_TYPE_ASCII + #define DFLT_MODE_WEP_INDEX MODE_WEP_INDEX3 + #define DFLT_MODE_ENC MODE_ENC_AUTO + + #define DFLT_NETMODE_0 DEFAULT_NETMODE_WLAN0 + #define DFLT_NETMODE_1 DEFAULT_NETMODE_WLAN1 + #define DFLT_DHCP_S_LEASE_IP_CNT DEFAULT_DHCP_LEASE_COUNT + #define DFLT_DHCP_S_LEASE_IP_CNT_MAX MAX_DHCP_LEASE_COUNT + #define DFLT_DHCP_S_LEASE_TIME DEFAULT_DHCP_SERVER_LEASE_TIME + #define DFLT_DHCP_S_LEASE_TIME_MAX MAX_DHCP_SERVER_LEASE_TIME + #define DFLT_DHCP_S_LEASE_TIME_MIN MIN_DHCP_SERVER_LEASE_TIME + #define DFLT_HTTP_SERVER_PORT DEFAULT_HTTP_SERVER_PORT + #define DFLT_AP_IP DEFAULT_IPADDR_WLAN1 + #define DFLT_AP_SUBNET DEFAULT_SUBNET_WLAN1 + #define DFLT_AP_GW DEFAULT_GATEWAY_WLAN1 + #define DFLT_AP_DNS DEFAULT_DNS_WLAN1 + #define DFLT_STA_IP DEFAULT_IPADDR_WLAN0 + #define DFLT_STA_SUBNET DEFAULT_SUBNET_WLAN0 + #define DFLT_STA_GW DEFAULT_GATEWAY_WLAN0 + #define DFLT_STA_DNS DEFAULT_DNS_WLAN0 + + #define DFLT_AP_SSID "\"RA6W1\"" + #define DFLT_STA_SSID "\"RA6W1\"" + + #define DFLT_P2P_DEV_NAME "RA6W1" + #define DFLT_P2P_LISTEN_CH 1 + #define DFLT_P2P_GO_INTENT 3 + #define DFLT_P2P_GO_OP_CH 1 + #define DFLT_P2P_GO MODE_DISABLE + + #define DFLT_DHCP_S_S_IP "10.0.0.2" + #define DFLT_DHCP_S_E_IP "10.0.0.11" + #define DFLT_DHCP_S_DNS_IP "8.8.8.8" + + #define DFLT_AP_COUNTRY_CODE "KR" + #define DFLT_STA_COUNTRY_CODE "KR" + #define DFLT_AP_ACS MODE_DISABLE + #define DFLT_AP_DHCP_S MODE_ENABLE + #define DFLT_DHCP_C MODE_ENABLE + #define DFLT_AP_FREQ CHANNEL_1_FREQ + #define DFLT_AP_CHANNEL 1 + + #define DFLT_HTTP_S MODE_DISABLE + #define DFLT_CoAP MODE_DISABLE + #define DFLT_ICMP_S MODE_DISABLE + #define DFLT_ICMP_C MODE_ENABLE + + #define DFLT_SNTP_C MODE_DISABLE + #define DFLT_SNTP_SERVER_DOMAIN "pool.ntp.org" + #define DFLT_SNTP_SERVER_DOMAIN_1 "1.pool.ntp.org" + #define DFLT_SNTP_SERVER_DOMAIN_2 "2.pool.ntp.org" + #define DFLT_SNTP_SYNC_PERIOD (3600 * 36) + + #define DFLT_OTA_UPDATE MODE_ENABLE + #define DFLT_OTA_UP_SVR_DOMAIN "ota.diasemi.com" + #define DFLT_OTA_UP_SVR_IP "10.20.30.40" /* TEMPORARY */ + #define DFLT_OTA_UPDATE_RUN_MODE 0 /* Manual / Auto = 1 */ + #define DFLT_OTA_UPDATE_PERIOD_MIN 10 /* minute */ + #define DFLT_OTA_UPDATE_PERIOD_MAX 44640 /* (31 days) minute */ + #define DFLT_OTA_UPDATE_PERIOD DFLT_OTA_UPDATE_PERIOD_MAX // 1440 /* (1 day) )minute */ + + #define DFLT_DPM MODE_ENABLE + +/* DPM WAKEUP TYPE */ + #define DPM_WAKEUP_TYPE_ALL 0 + #define DPM_WAKEUP_TYPE_UNICAST 1 + #define DPM_WAKEUP_TYPE_BROADCAST 2 + #define DPM_WAKEUP_TYPE_NONE 3 + #define DFLT_DPM_WAKEUP_TYPE DPM_WAKEUP_TYPE_ALL + + #define DFLT_DPM_TEST_APP 0 /* Disable */ + + #define USER_DPM_TIM_WAKEUP_COUNT 10 /* DTIM */ + + #ifdef USER_DPM_TIM_WAKEUP_COUNT + #define DFLT_DPM_TIM_WAKEUP_COUNT USER_DPM_TIM_WAKEUP_COUNT + #else + #define DFLT_DPM_TIM_WAKEUP_COUNT 10 /* default tim wakeup */ + #endif + + #define DPM_WAKEUP_CONDITION_ALL 0 + #define DPM_WAKEUP_CONDITION_UNICAST 1 + #define DPM_WAKEUP_CONDITION_BROADCAST 2 + #define DPM_WAKEUP_CONDITION_NONE 3 + #define DPM_WAKEUP_CONDITION_BCMC_FILTER 4 /* BC & MC wakeup disable */ + + #define DFLT_DPM_WAKEUP_CONDITION DPM_WAKEUP_CONDITION_ALL + +/* Dynamic Period Set */ + #define DFLT_DPM_DYNAMIC_PERIOD_SET 0 + +/* Keepalive Time */ + #define DFLT_DPM_KEEPALIVE_TIME (30 * 1000) + #define MIN_DPM_KEEPALIVE_TIME 1000 /* ms */ + #define MAX_DPM_KEEPALIVE_TIME (600 * 1000) /* ms, 10 minutes */ + +/* User Wakeup Time */ + #define DFLT_DPM_USER_WAKEUP_TIME 0 /* ms */ + #define MIN_DPM_USER_WAKEUP_TIME 1000 /* ms */ + #define MAX_DPM_USER_WAKEUP_TIME (86400 * 1000) /* ms, 24h */ + +/* DPM TIM Wakeup Time */ + #define MIN_DPM_TIM_WAKEUP_COUNT 1 /* 1= 102.4 ms */ + #define MAX_DPM_TIM_WAKEUP_COUNT 6000 /* 255 DTIM Interval */ + #define MAX_DPM_TIM_WAKEUP_COUNT_DDPS 30 + + #define DFLT_DL_CLI_PERIOD 1800 + #define DFLT_DL_SVC_SVR_IP "10.20.30.40" /* TEMPORARY IP */ + + #define DFLT_IPERF_C MODE_DISABLE + + #define DFLT_DNS_SD MODE_ENABLE + #define DFLT_DNS_SD_SVC_NAME "RA6W1" + #define DFLT_DNS_SD_SVC_TYPE "_service._tcp" + #define DFLT_DNS_SD_SVC_PORT 9110 + #define DFLT_DNS_SD_SVC_DESCRIPT "RA6WX Device" + #define DFLT_MDNS MODE_ENABLE + #define DFLT_MDNS_NAME "RA6W1" + #define DFLT_XMDNS MODE_ENABLE + #define DFLT_XMDNS_NAME "RA6W1" + + #define DFLT_NONE 0 + + #define HEXA_ON 1 + #define HEXA_OFF 0 + +/* ANSI CODE */ + #define ESCCODE "\33" + + #define BLACK_COLOR "\33[1;30m" + #define RED_COLOR "\33[1;31m" + #define GREEN_COLOR "\33[1;32m" + #define YELLOW_COLOR "\33[1;33m" + #define BLUE_COLOR "\33[1;34m" + #define MAGENTA_COLOR "\33[1;35m" + #define CYAN_COLOR "\33[1;36m" + #define WHITE_COLOR "\33[1;37m" + #define CLEAR_COLOR "\33[0m" + + #define RED_COL RED_COLOR + #define GRN_COL GREEN_COLOR + #define YEL_COL YELLOW_COLOR + #define BLU_COL BLUE_COLOR + #define MAG_COL MAGENTA_COLOR + #define CYN_COL CYAN_COLOR + #define WHT_COL WHITE_COLOR + #define CLR_COL CLEAR_COLOR + +/* Set Attributes */ + #define ANSI_BOLD "\33[1m" + #define ANSI_UNDERLINE "\33[4m" + #define ANSI_BLINK "\33[5m" + #define ANSI_REVERSE "\33[7m" + + #define ANSI_R_BOLD "\33[21m" + #define ANSI_R_UNDERLINE "\33[24m" + #define ANSI_R_BLINK "\33[25m" + #define ANSI_R_REVERSE "\33[27m" + +/* Rset Attributes */ + #define ANSI_NORMAL "\33[0m" + #define ANSI_RESET_BOLD "\33[21m" + #define ANSI_RESET_UNDERLINE "\33[24m" + #define ANSI_RESET_BLINK "\33[25m" + #define ANSI_RESET_REVERSE "\33[27m" + +/* Control */ + #define ANSI_CLEAR "\33[2J" + #define ANSI_CURON "\33[?25h" + #define ANSI_CUROFF "\33[?25l" + #define ANSI_BELL "\7" + #define ANSI_ERASE "\33[0J" + #define ANSI_LEFT "\33[1D" + #define ANSI_RIGHT "\33[1C" + +/* Foreground Color (text) */ + #define ANSI_COLOR_BLACK "\33[30m" + #define ANSI_COLOR_RED "\33[31m" + #define ANSI_COLOR_GREEN "\33[32m" + #define ANSI_COLOR_YELLOW "\33[33m" + #define ANSI_COLOR_BLUE "\33[34m" + #define ANSI_COLOR_MAGENTA "\33[35m" + #define ANSI_COLOR_CYAN "\33[36m" + #define ANSI_COLOR_WHITE "\33[37m" + #define ANSI_COLOR_LIGHT_RED "\33[1;31m" + #define ANSI_COLOR_LIGHT_GREEN "\33[1;32m" + #define ANSI_COLOR_LIGHT_YELLOW "\33[1;33m" + #define ANSI_COLOR_LIGHT_BLUE "\33[1;34m" + #define ANSI_COLOR_LIGHT_MAGENTA "\33[1;35m" + #define ANSI_COLOR_LIGHT_CYAN "\33[1;36m" + #define ANSI_COLOR_LIGHT_WHITE "\33[1;37m" + #define ANSI_COLOR_DEFULT "\33[0;39m" + +/* Background Color */ + #define ANSI_BCOLOR_BLACK "\33[40m" + #define ANSI_BCOLOR_RED "\33[41m" + #define ANSI_BCOLOR_GREEN "\33[42m" + #define ANSI_BCOLOR_YELLOW "\33[43m" + #define ANSI_BCOLOR_BLUE "\33[44m" + #define ANSI_BCOLOR_MAGENTA "\33[45m" + #define ANSI_BCOLOR_CYAN "\33[46m" + #define ANSI_BCOLOR_WHITE "\33[47m" + #define ANSI_BCOLOR_LIGHT_RED "\33[1;41m" + #define ANSI_BCOLOR_LIGHT_GREEN "\33[1;42m" + #define ANSI_BCOLOR_LIGHT_YELLOW "\33[1;43m" + #define ANSI_BCOLOR_LIGHT_BLUE "\33[1;44m" + #define ANSI_BCOLOR_LIGHT_MAGENTA "\33[1;45m" + #define ANSI_BCOLOR_LIGHT_CYAN "\33[1;46m" + #define ANSI_BCOLOR_LIGHT_WHITE "\33[1:47m" + #define ANSI_BCOLOR_DEFULT "\33[0;49m" + + #define VT_CLEAR printf("\33[2J") + #define VT_CURPOS(X, Y) printf("\33[%d;%dH", Y, X) + #define VT_NORMAL printf("\33[0m") + #define VT_BOLD printf("\33[1m") + #define VT_BLINK printf("\33[5m") + #define VT_REVERSE printf("\33[7m") + #define VT_CURON printf("\33[?25h") + #define VT_CUROFF printf("\33[?25l") + #define VT_BELL printf("\007") + #define VT_ERASE printf("\33[0J") + #define VT_LEFT printf("\33[1D") + #define VT_RIGHT printf("\33[1C") + #define VT_LINECLEAR(X) VT_CURPOS(1, X); printf("\33[2K") + #define VT_COLORBLACK printf("\33[30m") + #define VT_COLORRED printf("\33[31m") + #define VT_COLORGREEN printf("\33[32m") + #define VT_COLORYELLOW printf("\33[33m") + #define VT_COLORBLUE printf("\33[34m") + #define VT_COLORMAGENTA printf("\33[35m") + #define VT_COLORCYAN printf("\33[36m") + #define VT_COLORWHITE printf("\33[37m") + #define VT_COLORDEFULT printf("\33[39m") + #define VT_BCOLORBLACK printf("\33[40m") + #define VT_BCOLORRED printf("\33[41m") + #define VT_BCOLORGREEN printf("\33[42m") + #define VT_BCOLORYELLOW printf("\33[43m") + #define VT_BCOLORBLUE printf("\33[44m") + #define VT_BCOLORMAGENTA printf("\33[45m") + #define VT_BCOLORCYAN printf("\33[46m") + #define VT_BCOLORWHITE printf("\33[47m") + #define VT_BDEFULT printf("\33[49m") + #define VT_COLOROFF VT_BOLD; VT_BCOLORBLACK; VT_COLORWHITE + + #define vt_CLEAR printf("\33[2J") + #define vt_CURPOS(X, Y) printf("\33[%d;%dH", Y, X) + #define vt_NORMAL printf("\33[0m") + #define vt_BOLD printf("\33[1m") + #define vt_BLINK printf("\33[5m") + #define vt_REVERSE printf("\33[7m") + #define vt_CURON printf("\33[?25h") + #define vt_CUROFF printf("\33[?25l") + #define vt_BELL printf("\007") + #define vt_ERASE printf("\33[0J") + #define vt_LEFT printf("\33[1D") + #define vt_RIGHT printf("\33[1C") + #define vt_LINECLEAR(X) vt_CURPOS(1, X); printf("\33[2K") + #define vt_COLORBLACK printf("\33[30m") + #define vt_COLORRED printf("\33[31m") + #define vt_COLORGREEN printf("\33[32m") + #define vt_COLORYELLOW printf("\33[33m") + #define vt_COLORBLUE printf("\33[34m") + #define vt_COLORMAGENTA printf("\33[35m") + #define vt_COLORCYAN printf("\33[36m") + #define vt_COLORWHITE printf("\33[37m") + #define vt_COLORDEFULT printf("\33[39m") + #define vt_BCOLORBLACK printf("\33[40m") + #define vt_BCOLORRED printf("\33[41m") + #define vt_BCOLORGREEN printf("\33[42m") + #define vt_BCOLORYELLOW printf("\33[43m") + #define vt_BCOLORBLUE printf("\33[44m") + #define vt_BCOLORMAGENTA printf("\33[45m") + #define vt_BCOLORCYAN printf("\33[46m") + #define vt_BCOLORWHITE printf("\33[47m") + #define vt_BDEFULT printf("\33[49m") + #define vt_COLOROFF vt_BCOLORBLACK; vt_COLORWHITE + +// ISDIGIT onderzoekt of een karakter numeric is + #define ISDIGIT(c) ((c < '0' || c > '9') ? 0 : 1) + + #define UNDEF_PORT 0 + + #define HTTP_SVR_PORT 80 + #define HTTPS_SVR_PORT 443 + #define OTA_UPDATE_PORT 8048 + #define TCP_TRX_PORT 8049 + #define UDP_TRX_PORT 8047 + #define TCP_TRX_SRC_PORT 8050 + #define UDP_TRX_SRC_PORT 8051 + #define TCP_TX_SRC_PORT 8877 + #define TCP_TX_PORT 8878 + #define TCP_RX_PORT 8879 + #define DL_SERVICE_PORT 8046 + #define MON_SERVICE_PORT 8047 + #define MULTICAST_PORT 5353 + #define RTSP_PORT 8554 + + #define CM_UDP_PORT 6060 + #define DEMO_SERVICE_UDP_PORT 6123 + + #define UART1_BAUDRATE 115200 + #define UART2_BAUDRATE 115200 + + #define ENV_ASD_ENABLED "ENV_ASD_ENABLED" + + #define NVR_KEY_AP_LIVING_TIME "ap_living_time" + #define DFLT_AP_LIVING_TIME 60000 /* 1 Min */ + + #define NVR_KEY_UART2_BAUDRATE "UART2_BAUDRATE" + #define NVR_KEY_UART2_BITS "UART2_BITS" + #define NVR_KEY_UART2_PARITY "UART2_PARITY" + #define NVR_KEY_UART2_STOPBIT "UART2_STOPBIT" + #define NVR_KEY_UART2_FLOWCTRL "UART2_FLOWCTRL" + + #define NVR_KEY_UART3_BAUDRATE "UART3_BAUDRATE" + #define NVR_KEY_UART3_BITS "UART3_BITS" + #define NVR_KEY_UART3_PARITY "UART3_PARITY" + #define NVR_KEY_UART3_STOPBIT "UART3_STOPBIT" + #define NVR_KEY_UART3_FLOWCTRL "UART3_FLOWCTRL" + + #define DPM_REG_NAME_TIMER "dpm_timer_test" + #define DPM_TCP_TIMER "dpm_tcp_timer" + + #define DPM_MON_RETRY_CNT 10 + +// For DHCP Client hostname + #define NVR_DHCPC_HOSTNAME "DHCPC_HOSTNAME" + #define DHCP_HOSTNAME_MAX_LEN 32 + +/// For Country Code +struct country_ch_power_level +{ + char * country; + UCHAR ch[14]; +}; + +extern void trc_que_proc_print(UINT16 tag, const char * fmt, ...); + +/* Easy Setup */ + #define REPLY_FAIL "FAIL" + + #define SCAN_BSSID_IDX 0 + #define SCAN_FREQ_IDX 1 + #define SCAN_SIGNAL_IDX 2 + #define SCAN_FLGA_IDX 3 + #define SCAN_SSID_IDX 4 + + #define HIDDEN_SSID_DETECTION_CHAR '\t' + #define CLI_SCAN_RSP_BUF_SIZE 6144 + #define SCAN_RESULT_BUF_SIZE 6144 + #define SSID_BASE64_LEN_MAX 48 + #define DEFAULT_BSS_MAX_COUNT 80 + + #define FREERTOS_MAJOR_VERSION tskKERNEL_VERSION_MAJOR + #define FREERTOS_MINOR_VERSION tskKERNEL_VERSION_MINOR + #define FREERTOS_SUB_VERSION tskKERNEL_VERSION_BUILD + +/* API input parameters and general constants. */ + + #define _AND ((UINT) 2) + #define _AND_CLEAR ((UINT) 3) + #define _OR ((UINT) 0) + #define _OR_CLEAR ((UINT) 1) + + #define _1_ULONG ((UINT) 1) + #define _2_ULONG ((UINT) 2) + #define _4_ULONG ((UINT) 4) + #define _8_ULONG ((UINT) 8) + #define _16_ULONG ((UINT) 16) + + #define _NO_TIME_SLICE ((ULONG) 0) + #define _AUTO_START ((UINT) 1) + #define _DONT_START ((UINT) 0) + #define _AUTO_ACTIVATE ((UINT) 1) + + #define _INHERIT ((UINT) 1) + #define _NO_INHERIT ((UINT) 0) + +/* Thread execution state values. */ + #define TASK_READY ((UINT) 0) + #define TASK_COMPLETED ((UINT) 1) + #define TASK_TERMINATED ((UINT) 2) + + #define LOWER_16_MASK ((ULONG) 0x0000FFFF) + #define SHIFT_BY_16 16 + + #define PRINTF(...) printf(__VA_ARGS__) + #define Vprintf(...) + + #if dg_configUSE_CONSOLE && CFG_CLI +extern int getchar_nowait(); + + #define GETC() getchar() + #define GETC_NOWAIT() getchar_nowait() + #else + #define GETC() getchar() + #define GETC_NOWAIT() + #endif + + #define PUTC(ch) + #define PUTS(s) + + #define BUILD_OPT_RA6W1_ASIC + #define BUILD_OPT_RA6W1_LIBNDK + #define BUILD_OPT_RA6W1_CACHEXIP + #define BUILD_OPT_RA6W1_SLR + #define BUILD_OPT_RA6W1_MAC + + #undef SFLASH_DEBUGGING /* FOR_DEBUGGING */ + #undef SFLASH_NVEDIT_DEBUGGING /* FOR_DEBUGGING */ + #undef SFLASH_ENV_DEBUGGING /* FOR_DEBUGGING */ + #undef SFLASH_SYS_CFG_DEBUGGING /* FOR_DEBUGGING */ + #undef SFLASH_XFC_DEBUGGING /* FOR_DEBUGGING */ + + #define USING_HEAP_5 + +// For Wi-Fi Connection call-back event + #define WIFI_CONN_NOTI_WAIT_TICK (portCONVERT_MS_2_TICKS(100)) + + #define WIFI_CONN_SUCC_STA 0x1 + #define WIFI_CONN_FAIL_STA 0x2 + #define WIFI_DISCONN_STA 0x4 + #define WIFI_CONN_SUCC_SOFTAP 0x10 + #define WIFI_CONN_FAIL_SOFTAP 0x20 + #define WIFI_DISCONN_SOFTAP 0x40 + + #define WIFI_CONN_SUCC_STA_4_BLE 0x100 + #define WIFI_CONN_FAIL_STA_4_BLE 0x200 + +// common_utils.c function... + +void pntdumpbin(unsigned char * pbyBin, int nLen, int simple); + + #ifdef __cplusplus +extern "C" { + #endif +int ra6w1_cli_reply(char * cmdline, char * delimit, char * cli_reply); + + #ifdef __cplusplus +} + #endif +int factory_reset(int reboot_flag); +long subnetRangeLastIP(long ip, long subnet); +UINT writeDataToFlash(UINT * destFlashAddr, UINT * srcMemAddr, UINT size); + + #undef ISR_SEPARATE + #define WATCH_DOG_ENABLE + #undef USING_RAMLIB + +typedef enum __system_reboot__ +{ + SYS_RESET, + SYS_REBOOT_POR, + SYS_REBOOT +} SYSTEM_REBOOT; + +#endif /* __COMMON_DEF_H__ */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/default_partition_table.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/default_partition_table.h new file mode 100644 index 000000000000..6d4c70eb54f0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/default_partition_table.h @@ -0,0 +1,74 @@ +/** + **************************************************************************************** + * + * @file ra6w1/config/4MB/default_partition_table.h + * + * @brief Partition map for RA6W1 4MB SFLASH + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* $code_snippet START table_partition */ + +#define NVMS_PRODUCT_HEADER_PART_START 0x000000 +#define NVMS_PRODUCT_HEADER_PART_SIZE 0x002000 +#define NVMS_FIRMWARE_PART_START 0x002000 /* Alignment to 512KB is dictated by the default FLASH_REGION_SIZE. */ +#define NVMS_FIRMWARE_PART_SIZE 0x1FE000 + +/* +------------------2MB---------------------+ */ + +#define NVMS_GENERIC_PART_START 0x200000 +#define NVMS_GENERIC_PART_SIZE 0x020000 +#define NVMS_PLATFORM_PARAMS_PART_START 0x220000 +#define NVMS_PLATFORM_PARAMS_PART_SIZE 0x07F000 +#define NVMS_PARAM_PART_START 0x29F000 +#define NVMS_PARAM_PART_SIZE 0x001000 /* Recommended location, 4KB before the end of the 1st flash section. */ + +/* +------------------2MB---------------------+ */ + +#define NVMS_LOG_PART_START 0x2A0000 +#define NVMS_LOG_PART_SIZE 0x070000 +#define NVMS_BIN_PART_START 0x310000 +#define NVMS_BIN_PART_SIZE 0x0EF000 +#define NVMS_PARTITION_TABLE_START 0x3FF000 +#define NVMS_PARTITION_TABLE_SIZE 0x001000 /* Recommended location, 4KB before the end of the flash. */ +#ifdef NVMS_QSPI_TEST_PART + #define NVMS_QSPI_TEST_PART_START (QSPI_MEM1_VIRTUAL_BASE_ADDR + 0x000000) + #define NVMS_QSPI_TEST_PART_SIZE 0x080000 +#endif /* NVMS_QSPI_TEST_PART */ + +PARTITION2(NVMS_PRODUCT_HEADER_PART, 0) +PARTITION2(NVMS_FIRMWARE_PART, 0) +PARTITION2(NVMS_GENERIC_PART, PARTITION_FLAG_VES) +PARTITION2(NVMS_PLATFORM_PARAMS_PART, PARTITION_FLAG_READ_ONLY) +PARTITION2(NVMS_PARAM_PART, 0) +PARTITION2(NVMS_LOG_PART, 0) +PARTITION2(NVMS_BIN_PART, 0) +PARTITION2(NVMS_PARTITION_TABLE, PARTITION_FLAG_READ_ONLY) +#ifdef NVMS_QSPI_TEST_PART +PARTITION2(NVMS_QSPI_TEST_PART, PARTITION_FLAG_VES) +#endif /* NVMS_QSPI_TEST_PART */ + +/* $code_snippet END */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/partition_table.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/partition_table.h new file mode 100644 index 000000000000..4025bde502e4 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/partition_table.h @@ -0,0 +1,67 @@ +/** + **************************************************************************************** + * + * @file ra6w1/config/4MB/partition_table.h + * + * @brief Partition map for RA6W1 4MB SFLASH + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* $code_snippet START table_partition */ + +#define NVMS_PRODUCT_HEADER_PART_START SF_BASE_ADDR +#define NVMS_PRODUCT_HEADER_PART_SIZE (SF_PRODUCT_HDR_SIZE * 2) // Header + Header-Backup + +#define NVMS_FIRMWARE_PART_START SF_RTOS_0 +#define NVMS_FIRMWARE_PART_SIZE SF_RTOS_SIZE + +#define NVMS_LOG_PART_START SF_TLS_CERT_BASE_ADDR +#define NVMS_LOG_PART_SIZE SF_USER_AREA_SIZE + +#define NVMS_GENERIC_PART_START SF_NVRAM_AREA +#define NVMS_GENERIC_PART_SIZE (SF_NVRAM_SIZE * 2) + +/* +------------------ 2 MB ---------------------+ */ + +#define NVMS_BIN_PART_START SF_USER_AREA +#define NVMS_BIN_PART_SIZE SF_USER_AREA_SIZE + +#define NVMS_PARTITION_TABLE_START SF_PARTITION_TBL +#define NVMS_PARTITION_TABLE_SIZE SF_PARTITION_TBL_SIZE /* Recommended location, 4KB before the end of the flash. */ + +/* +------------------ 4 MB ---------------------+ */ + +/* + * Partition information + */ +PARTITION2(NVMS_PRODUCT_HEADER_PART, 0) // Product Header +PARTITION2(NVMS_FIRMWARE_PART, 0) // RTOS #0 +PARTITION2(NVMS_LOG_PART, 0) // User Area #0 or TLS certificates +PARTITION2(NVMS_GENERIC_PART, PARTITION_FLAG_VES) // NVRAM +PARTITION2(NVMS_BIN_PART, 0) // User Area #1 +PARTITION2(NVMS_PARTITION_TABLE, PARTITION_FLAG_READ_ONLY) // Partition Table + +/* $code_snippet END */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/suota/partition_table.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/suota/partition_table.h new file mode 100644 index 000000000000..69e44da3305d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/4MB/suota/partition_table.h @@ -0,0 +1,69 @@ +/** + **************************************************************************************** + * + * @file 4MB/suota/partition_table.h + * + * @brief Partition table selection. Image partition's size definition. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* $code_snippet START suota_4MB_flash_partition_table */ + +#define NVMS_PRODUCT_HEADER_PART_START SF_BASE_ADDR +#define NVMS_PRODUCT_HEADER_PART_SIZE (SF_PRODUCT_HDR_SIZE * 2) // Header + Header-Backup +#define NVMS_FW_EXEC_PART_START SF_RTOS_0 /* Alignment to 512KB is dictated by the default FLASH_REGION_SIZE. */ +#define NVMS_FW_EXEC_PART_SIZE SF_RTOS_SIZE + +#define NVMS_LOG_PART_START SF_TLS_CERT_BASE_ADDR +#define NVMS_LOG_PART_SIZE SF_TLS_AREA_SIZE + +#define NVMS_GENERIC_PART_START SF_NVRAM_AREA +#define NVMS_GENERIC_PART_SIZE (SF_NVRAM_SIZE * AD_NVMS_VES_MULTIPLIER) + +/* +------------------ 2 MB ---------------------+ */ + +#define NVMS_FW_UPDATE_PART_START SF_RTOS_1 /* Alignment to 512KB is dictated by the default FLASH_REGION_SIZE. */ +#define NVMS_FW_UPDATE_PART_SIZE SF_RTOS_SIZE +#define NVMS_BIN_PART_START SF_USER_AREA +#define NVMS_BIN_PART_SIZE SF_USER_AREA_SIZE + +#define NVMS_PARTITION_TABLE_START SF_PARTITION_TBL +#define NVMS_PARTITION_TABLE_SIZE SF_PARTITION_TBL_SIZE /* Recommended location, 4KB before the end of the flash. */ + +/* +------------------ 4 MB ---------------------+ */ + +/* + * Partition information + */ +PARTITION2(NVMS_PRODUCT_HEADER_PART, 0) // Product Header +PARTITION2(NVMS_FW_EXEC_PART, 0) // RTOS #0 +PARTITION2(NVMS_LOG_PART, 0) // User Area #0 or TLS certificates +PARTITION2(NVMS_GENERIC_PART, PARTITION_FLAG_VES) // NVRAM +PARTITION2(NVMS_FW_UPDATE_PART, 0) // RTOS #1 +PARTITION2(NVMS_BIN_PART, 0) // User Area #1 +PARTITION2(NVMS_PARTITION_TABLE, PARTITION_FLAG_READ_ONLY) // Partition Table + +/* $code_snippet END */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/8MB/at25sl/suota/partition_table.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/8MB/at25sl/suota/partition_table.h new file mode 100644 index 000000000000..a08db0b8975a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/8MB/at25sl/suota/partition_table.h @@ -0,0 +1,75 @@ +/** + **************************************************************************************** + * + * @file 8MB/at25sl/suota/partition_table.h + * + * @brief Partition table selection. Image partition's size definition. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* START suota_8MB_flash_partition_table for AT25SL series */ + +#define NVMS_PRODUCT_HEADER_PART_START SF_BASE_ADDR +#define NVMS_PRODUCT_HEADER_PART_SIZE (SF_PRODUCT_HDR_SIZE * 2) // Header + Header-Backup + +#define NVMS_FW_EXEC_PART_START SF_RTOS_0 +#define NVMS_FW_EXEC_PART_SIZE SF_RTOS_SIZE + +/* +------------------ 3 MB ---------------------+ */ + +#define NVMS_GENERIC_PART_START SF_NVRAM_AREA +#define NVMS_GENERIC_PART_SIZE (SF_NVRAM_SIZE * AD_NVMS_VES_MULTIPLIER) + +#define NVMS_LOG_PART_START SF_TLS_CERT_BASE_ADDR +#define NVMS_LOG_PART_SIZE SF_TLS_AREA_SIZE + +/* +------------------ 4 MB ---------------------+ */ + +#define NVMS_FW_UPDATE_PART_START SF_RTOS_1 +#define NVMS_FW_UPDATE_PART_SIZE SF_RTOS_SIZE + +/* +------------------ 7 MB ---------------------+ */ + +#define NVMS_BIN_PART_START SF_USER_AREA +#define NVMS_BIN_PART_SIZE SF_USER_AREA_SIZE + +#define NVMS_PARTITION_TABLE_START SF_PARTITION_TBL +#define NVMS_PARTITION_TABLE_SIZE SF_PARTITION_TBL_SIZE /* Recommended location, 4KB before the end of the flash. */ + +/* +------------------ 8 MB ---------------------+ */ + +/* + * Partition information + */ +PARTITION2(NVMS_PRODUCT_HEADER_PART, 0) // Product Header +PARTITION2(NVMS_FW_EXEC_PART, 0) // RTOS #0 +PARTITION2(NVMS_GENERIC_PART, PARTITION_FLAG_VES) // NVRAM +PARTITION2(NVMS_LOG_PART, 0) // TLS certificates +PARTITION2(NVMS_FW_UPDATE_PART, 0) // RTOS #1 +PARTITION2(NVMS_BIN_PART, 0) // User Area +PARTITION2(NVMS_PARTITION_TABLE, PARTITION_FLAG_READ_ONLY) // Partition Table + +/* $code_snippet END */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/ad_nvparam_defs.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/ad_nvparam_defs.h new file mode 100644 index 000000000000..b24dd1b180c4 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/ad_nvparam_defs.h @@ -0,0 +1,131 @@ +/** + **************************************************************************************** + * + * @file ad_nvparam_defs.h + * + * @brief NV-Parameters definitions + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* + * DO NOT MODIFY THIS FILE!!! + * + * NV-Parameters configuration shall be done in platform_nvparam.h!!! + * + */ + +#ifndef AD_NVPARAM_DEFS_H_ +#define AD_NVPARAM_DEFS_H_ + +#ifndef IN_AD_NVPARAM_C + +/* + * If this is included outside of ad_nvparam.c, we just define empty macros so nothing but tag + * definitions are created from platform_nvparam.h + */ +#define NVPARAM_AREA(NAME, PARTITION) +#define NVPARAM_PARAM(TAGNAME, LENGTH) +#define NVPARAM_VARPARAM(TAGNAME, LENGTH) +#define NVPARAM_AREA_END() + +#else + +/* + * If this is included inside of ad_nvparam.c, we will create proper configuration structure. + */ + +/* + * First we create configurations of each area - this will create "area_XXX" symbol for each defined + * area in platform_nvparam.h. It contains all parameters defined for given area. + */ +#define NVPARAM_AREA(NAME, PARTITION) \ + static /*const*/ parameter_t area_ ## NAME[] = { +#define NVPARAM_PARAM(TAGNAME, LENGTH) \ + { \ + .name = TAGNAME, \ + .attr.flags = 0, \ + .attr.length = LENGTH, \ + }, +#define NVPARAM_VARPARAM(TAGNAME, LENGTH) \ + { \ + .name = TAGNAME, \ + .attr.flags = FLAG_VARIABLE_LEN, \ + .attr.length = LENGTH, \ + }, +#define NVPARAM_AREA_END() \ + }; + +#undef PLATFORM_NVPARAM_H_ +#if (dg_configNVPARAM_APP_AREA == 2) + #undef APP_NVPARAM_H_ + #if defined(dg_configADNVPARAM_PROJ_FILE) + #include dg_configADNVPARAM_PROJ_FILE + #else + #error "dg_configADNVPARAM_PROJ_FILE is not exist !!" + #endif +#else + #include "platform_nvparam.h" +#endif + + +/* + * Next, using the same platform_nvparam.h, we define list of areas. Each has proper attributes set + * and pointer to corresponding area structure. + */ +#undef NVPARAM_AREA +#undef NVPARAM_PARAM +#undef NVPARAM_VARPARAM +#undef NVPARAM_AREA_END +#define NVPARAM_AREA(NAME, PARTITION) \ + { \ + .name = #NAME, \ + .parameters = area_ ## NAME, \ + .num_parameters = sizeof(area_ ## NAME) / sizeof(area_ ## NAME[0]), \ + }, +#define NVPARAM_PARAM(TAGNAME, LENGTH) +#define NVPARAM_VARPARAM(TAGNAME, LENGTH) +#define NVPARAM_AREA_END() + +static const area_t areas[] = +{ +#undef PLATFORM_NVPARAM_H_ +#if (dg_configNVPARAM_APP_AREA == 2) + #undef APP_NVPARAM_H_ + #if defined(dg_configADNVPARAM_PROJ_FILE) + #include dg_configADNVPARAM_PROJ_FILE + #else + #error "dg_configADNVPARAM_PROJ_FILE is not exist !!" + #endif +#else + #include "platform_nvparam.h" +#endif +}; + +#define num_areas (sizeof(areas) / sizeof(areas[0])) + +#endif /* IN_AD_NVPARAM_C */ + +#endif /* AD_NVPARAM_DEFS_H_ */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/boards/brd_io_config_ra6w1.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/boards/brd_io_config_ra6w1.h new file mode 100644 index 000000000000..5b7d3f60d0e9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/boards/brd_io_config_ra6w1.h @@ -0,0 +1,104 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup PLA_BSP_CFG_BOARDS + * \{ + */ + +/** + **************************************************************************************** + * + * @file brd_io_config_ra6w1.h + * + * @brief Board Support Package. RA6W1 Board I/O configuration. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BRD_IO_CONFIG_RA6W1_H +#define BRD_IO_CONFIG_RA6W1_H + +#ifdef BSP_MCU_GROUP_RA6W1 + #include "bsp_pin_cfg.h" +#endif + +#ifdef EXT_INTR1_PIN + #define BTN_FR EXT_INTR1_PIN +#endif + +#ifdef EXT_INTR2_PIN + #define BTN_WPS EXT_INTR2_PIN +#endif + +/* LED configuration section */ +#ifdef LED0 + #define LED0_PORT (LED0 >> BSP_IO_PORT_OFFSET) + #define LED0_PIN (LED0 & BSP_IO_PIN_BITS) + #define LED0_MODE (GPIO_W_CFG_PORT_DIRECTION_OUTPUT) + #define LED0_FUNC (GPIO_W_PERIPHERAL_GPIO) +#endif + +/*WAKUP PIN*/ +#define RTC_WAKEUP_IO (BSP_WAKEUP_GPIO_P0_11) +#define RTC_WAKEUP_IO_EDGE (BSP_WAKEUP_EDGE_LOW) + +#define BTN_WAKEUP_MODE (GPIO_W_CFG_PULLUP_ENABLE) +#define BTN_WAKEUP_FUNC (GPIO_W_PERIPHERAL_GPIO) + +#define ADC_WAKEUP_MODE (GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_ANALOG_ENABLE) + +#ifdef BTN_FR + #define BTN_FR_PORT (BTN_FR >> BSP_IO_PORT_OFFSET) + #define BTN_FR_PIN (BTN_FR & BSP_IO_PIN_BITS) + #define BTN_FR_MODE (GPIO_W_CFG_PULLUP_ENABLE | GPIO_W_CFG_RETENTION) + #define BTN_FR_FUNC (GPIO_W_PERIPHERAL_GPIO) + #define BTN_FR_INT_POL (BSP_IO_LEVEL_HIGH) + #define BTN_FR_INT_SEL (HW_GPIO_INT_EDGE) + #define BTN_FR_CHK_TIME 5 /* 5 sec. */ +#endif + +#ifdef BTN_WPS + #define BTN_WPS_PORT (BTN_WPS >> BSP_IO_PORT_OFFSET) + #define BTN_WPS_PIN (BTN_WPS & BSP_IO_PIN_BITS) + #define BTN_WPS_MODE (GPIO_W_CFG_PULLUP_ENABLE | GPIO_W_CFG_RETENTION) + #define BTN_WPS_FUNC (GPIO_W_PERIPHERAL_GPIO) + #define BTN_WPS_INT_POL (BSP_IO_LEVEL_HIGH) + #define BTN_WPS_INT_SEL (HW_GPIO_INT_EDGE) + #define BTN_WPS_CHK_TIME 1 /* 1 sec. */ +#endif + +#ifdef LED0 + #define FR_WPS_LED_PORT (LED0_PORT) + #define FR_WPS_LED_PIN (LED0_PIN) + #define FR_WPS_LED_MODE (LED0_MODE) + #define FR_WPS_LED_FUNC (LED0_FUNC) +#endif + +#endif /* BRD_IO_CONFIG_RA6W1_H */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_debug.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_debug.h new file mode 100644 index 000000000000..d6a63ae31cbe --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_debug.h @@ -0,0 +1,1099 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup BSP_DEBUG Debug Configuration + * \brief Board debug support configuration definitions + * \{ + */ + +/** + **************************************************************************************** + * + * @file bsp_debug.h + * + * @brief Board Support Package. Debug Configuration. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEBUG_H_ +#define BSP_DEBUG_H_ + +/** + * \addtogroup DEBUG_SETTINGS + * + * \brief Debugging settings + * + * \{ + */ + +/* -------------------------------------- Debug settings ---------------------------------------- */ + +/** + * \brief Enable debugger + */ +#ifndef dg_configENABLE_DEBUGGER + #define dg_configENABLE_DEBUGGER (1) +#endif + +/** + * \brief Use SW cursor + */ +#ifndef dg_configUSE_SW_CURSOR + #define dg_configUSE_SW_CURSOR (0) + #define SW_CURSOR_PORT (0) + #define SW_CURSOR_PIN (0) +#else + #if (DEVICE_FAMILY == DA1468X) + #if dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D + #if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN + #define SW_CURSOR_PORT (0) + #define SW_CURSOR_PIN (7) + #endif + #else + #if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN + #define SW_CURSOR_PORT (2) + #define SW_CURSOR_PIN (3) + #endif + #endif + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN + #define SW_CURSOR_PORT (0) + #define SW_CURSOR_PIN (16) + #endif + #endif +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup DEBUG_SETTINGS + * \{ + * \addtogroup SYSTEM_VIEW + * + * \brief System View configuration settings + * \{ + */ + +/* ----------------------------- Segger System View configuration ------------------------------- */ + +/** + * \brief Segger's System View + * + * When enabled the application should also call SEGGER_SYSVIEW_Conf() to enable system monitoring. + * configTOTAL_HEAP_SIZE should be increased by dg_configSYSTEMVIEW_STACK_OVERHEAD bytes for each system task. + * For example, if there are 8 system tasks configTOTAL_HEAP_SIZE should be increased by + * (8 * dg_configSYSTEMVIEW_STACK_OVERHEAD) bytes. + * + * - 0 : Disabled + * - 1 : Enabled + * + */ +#ifndef dg_configSYSTEMVIEW + #define dg_configSYSTEMVIEW (0) +#endif + +/** + * \brief Stack size overhead when System View API is used + * + * All thread stack sizes plus the the stack of IRQ handlers will be increased by that amount + * to avoid stack overflow when System View is monitoring the system. + */ +#ifndef dg_configSYSTEMVIEW_STACK_OVERHEAD + #define dg_configSYSTEMVIEW_STACK_OVERHEAD (256) +#endif + +/* + * Enable/Disable System View monitoring time critical interrupt handlers (CPM, USB). + * Disabling ISR monitoring could help reducing assertions triggered by System View monitoring overhead. + * + */ + +/** + * \brief Let System View monitor CPM related ISRs (SWTIM1_Handler / WKUP_GPIO_Handler). + * + * - 0 : Disabled + * - 1 : Enabled + */ +#ifndef dg_configSYSTEMVIEW_MONITOR_CPM_ISR + #define dg_configSYSTEMVIEW_MONITOR_CPM_ISR (1) +#endif + +/** + * \brief Let System View monitor USB related ISRs (USB_Handler / VBUS_Handler). + * + * - 0 : Disabled + * - 1 : Enabled + */ +#ifndef dg_configSYSTEMVIEW_MONITOR_USB_ISR + #define dg_configSYSTEMVIEW_MONITOR_USB_ISR (1) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + * \} + */ + +/* --------------------------------- DEBUG GPIO handling macros --------------------------------- */ +#if (DEVICE_FAMILY == DA1468X) + #define DBG_CONFIGURE(flag, name, func) \ + { \ + if (flag == 1) { \ + name ## _MODE_REG = 0x300 + func; \ + } \ + } + + #define DBG_CONFIGURE_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + name ## _SET_REG = name ## _PIN; \ + name ## _MODE_REG = 0x300; \ + } \ + } + + #define DBG_CONFIGURE_LOW(flag, name) \ + { \ + if (flag == 1) { \ + name ## _RESET_REG = name ## _PIN; \ + name ## _MODE_REG = 0x300; \ + } \ + } + + #define DBG_SET_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + name ## _SET_REG = name ## _PIN; \ + } \ + } + + #define DBG_SET_LOW(flag, name) \ + { \ + if (flag == 1) { \ + name ## _RESET_REG = name ## _PIN; \ + } \ + } +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + + #define DBG_GET_SET_PAD_LATCH_REG(name) *(((volatile uint32_t *) (&name ## _SET_REG) == \ + (volatile uint32_t *) (&GPIO->P0_SET_DATA_REG)) ? &CRG_TOP-> \ + P0_SET_PAD_LATCH_REG : &CRG_TOP->P1_SET_PAD_LATCH_REG) + #define DBG_GET_RESET_PAD_LATCH_REG(name) *(((volatile uint32_t *) (&name ## _SET_REG) == \ + (volatile uint32_t *) (&GPIO->P0_SET_DATA_REG)) ? &CRG_TOP-> \ + P0_RESET_PAD_LATCH_REG : &CRG_TOP-> \ + P1_RESET_PAD_LATCH_REG) + #define DBG_TOGGLE_PIN_PAD_LATCH(name) DBG_GET_SET_PAD_LATCH_REG(name) = name ## _PIN; \ + DBG_GET_RESET_PAD_LATCH_REG(name) = name ## _PIN + #define DBG_SET_PIN_REG(name) name ## _SET_REG = name ## _PIN + #define DBG_RESET_PIN_REG(name) name ## _RESET_REG = name ## _PIN + + #define DBG_CONFIGURE(flag, name, func) \ + { \ + if (flag == 1) { \ + ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, COM_IS_UP) == 1); \ + name ## _MODE_REG = 0x300 + func; \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_CONFIGURE_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1); \ + name ## _MODE_REG = 0x300; \ + DBG_SET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_CONFIGURE_LOW(flag, name) \ + { \ + if (flag == 1) { \ + ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1); \ + name ## _MODE_REG = 0x300; \ + DBG_RESET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_SET_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1); \ + name ## _MODE_REG = 0x300; \ + DBG_SET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_SET_LOW(flag, name) \ + { \ + if (flag == 1) { \ + ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1); \ + name ## _MODE_REG = 0x300; \ + DBG_RESET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + +#elif (DEVICE_FAMILY == DA1640X) + + #define DBG_GET_SET_PAD_LATCH_REG(name) // *(((volatile uint32_t *)(&name##_SET_REG) == (volatile uint32_t *)(&GPIO->P0_SET_DATA_REG)) ? &CRG_TOP->P0_SET_PAD_LATCH_REG : &CRG_TOP->P1_SET_PAD_LATCH_REG) + #define DBG_GET_RESET_PAD_LATCH_REG(name) // *(((volatile uint32_t *)(&name##_SET_REG) == (volatile uint32_t *)(&GPIO->P0_SET_DATA_REG)) ? &CRG_TOP->P0_RESET_PAD_LATCH_REG : &CRG_TOP->P1_RESET_PAD_LATCH_REG) + #define DBG_TOGGLE_PIN_PAD_LATCH(name) /* DBG_GET_SET_PAD_LATCH_REG(name) = name##_PIN; */ \ + /* DBG_GET_RESET_PAD_LATCH_REG(name) = name##_PIN */ + #define DBG_SET_PIN_REG(name) // name##_SET_REG = name##_PIN + #define DBG_RESET_PIN_REG(name) // name##_RESET_REG = name##_PIN + + #define DBG_CONFIGURE(flag, name, func) \ + { \ + if (flag == 1) { \ + /*ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, COM_IS_UP) == 1);*/ \ + name ## _MODE_REG = 0x300 + func; \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_CONFIGURE_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + /*ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1);*/ \ + name ## _MODE_REG = 0x300; \ + DBG_SET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_CONFIGURE_LOW(flag, name) \ + { \ + if (flag == 1) { \ + /*ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1);*/ \ + name ## _MODE_REG = 0x300; \ + DBG_RESET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_SET_HIGH(flag, name) \ + { \ + if (flag == 1) { \ + /*ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1);*/ \ + name ## _MODE_REG = 0x300; \ + DBG_SET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + + #define DBG_SET_LOW(flag, name) \ + { \ + if (flag == 1) { \ + /*ASSERT_WARNING(REG_GETF(CRG_TOP, SYS_STAT_REG, AUD_IS_UP) == 1);*/ \ + name ## _MODE_REG = 0x300; \ + DBG_RESET_PIN_REG(name); \ + DBG_TOGGLE_PIN_PAD_LATCH(name); \ + } \ + } + +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* ---------------------------------- HardFault or NMI event ------------------------------------ */ + +#ifndef EXCEPTION_DEBUG + #define EXCEPTION_DEBUG (0) // Requires GPIO config. +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* --------------------------------- Clock and Power Manager ------------------------------------ */ + +#if (DEVICE_FAMILY == DA1468X) + + #ifndef CPM_DEBUG + #define CPM_DEBUG (0) + #endif + + #ifndef CPM_USE_FUNCTIONAL_DEBUG + #define CPM_USE_FUNCTIONAL_DEBUG (0) // Requires GPIO config. + #endif + + #ifndef CPM_USE_TIMING_DEBUG + #define CPM_USE_TIMING_DEBUG (0) // Requires GPIO config. + #endif + + #ifndef CPM_USE_RCX_DEBUG + #define CPM_USE_RCX_DEBUG (0) // Requires logging. + #endif + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X) || (DEVICE_FAMILY == DA1640X)) + + #ifndef PWR_MGR_DEBUG + #define PWR_MGR_DEBUG (0) + #endif + + #ifndef SYS_TIM_DEBUG + #define SYS_TIM_DEBUG (0) + #endif + + #ifndef PWR_MGR_FUNCTIONAL_DEBUG + #define PWR_MGR_FUNCTIONAL_DEBUG (0) // Requires GPIO config. + #endif + + #ifndef PWR_MGR_USE_TIMING_DEBUG + #define PWR_MGR_USE_TIMING_DEBUG (0) // Requires GPIO config. + #endif + + #ifndef CLK_MGR_USE_TIMING_DEBUG + #define CLK_MGR_USE_TIMING_DEBUG (0) // Requires GPIO config. + #endif + +#endif + +/* Controls which RAM blocks will be retained when the MEASURE_SLEEP_CURRENT test mode is used + * (optional). */ +#ifndef dg_configTESTMODE_RETAIN_RAM + #define dg_configTESTMODE_RETAIN_RAM (0x1F) +#endif + +/* Controls whether the Cache will be retained when the MEASURE_SLEEP_CURRENT test mode is used + * (optional). */ +#ifndef dg_configTESTMODE_RETAIN_CACHE + #define dg_configTESTMODE_RETAIN_CACHE (0) +#endif + +/* Controls whether the ECC RAM will be retained when the MEASURE_SLEEP_CURRENT test mode is used + * (optional). */ +#ifdef dg_config_TESTMODE_RETAIN_ECCRAM + #error "dg_config_TESTMODE_RETAIN_ECCRAM is no longer supported. " +"Use dg_configTESTMODE_RETAIN_ECCRAM instead (no underscore)!" +#endif + +#ifndef dg_configTESTMODE_RETAIN_ECCRAM + #define dg_configTESTMODE_RETAIN_ECCRAM (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* --------------------------------------- USB Charger ------------------------------------------ */ + +#if (DEVICE_FAMILY == DA1468X) + + #ifndef DEBUG_USB_CHARGER + #define DEBUG_USB_CHARGER (0) + #endif + + #ifndef DEBUG_USB_CHARGER_FSM + #define DEBUG_USB_CHARGER_FSM (0) + #endif + + #ifndef DEBUG_USB_CHARGER_PRINT + #define DEBUG_USB_CHARGER_PRINT (0) + #endif + + #ifndef USB_CHARGER_TIMING_DEBUG + #define USB_CHARGER_TIMING_DEBUG (0) // Requires GPIO config. + #endif + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + + #ifndef SYS_CHARGER_TIMING_DEBUG + #define SYS_CHARGER_TIMING_DEBUG (0) + #endif + +#endif /* DEVICE_FAMILY */ + +/* ---------------------------------------------------------------------------------------------- */ + +/* ------------------------------------------ Flash --------------------------------------------- */ +#ifndef FLASH_DEBUG + #define FLASH_DEBUG (0) // Requires GPIO config. +#endif + +#ifndef __DBG_QSPI_ENABLED + #define __DBG_QSPI_ENABLED (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* ------------------------------------------ Common -------------------------------------------- */ +#ifndef CMN_TIMING_DEBUG + #define CMN_TIMING_DEBUG (0) // Requires GPIO config. +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* ------------------------------------ GPIO configuration -------------------------------------- */ + +/* Enable/Disable GPIO pin assignment conflict detection + */ +#define DEBUG_GPIO_ALLOC_MONITOR_ENABLED (0) + +/* Exception handling debug configuration + * + */ +#if (EXCEPTION_DEBUG == 0) + +// Dummy values to suppress compiler errors + #define EXCEPTIONDBG_MODE_REG *(volatile int *) 0x20000000 + #define EXCEPTIONDBG_SET_REG *(volatile int *) 0x20000000 + #define EXCEPTIONDBG_RESET_REG *(volatile int *) 0x20000000 + #define EXCEPTIONDBG_PIN (0) + +#else + + #if (DEVICE_FAMILY == DA1468X) + +// Tick (P3[0]) + #define EXCEPTIONDBG_MODE_REG GPIO->P30_MODE_REG + #define EXCEPTIONDBG_SET_REG GPIO->P3_SET_DATA_REG + #define EXCEPTIONDBG_RESET_REG GPIO->P3_RESET_DATA_REG + #define EXCEPTIONDBG_PIN (1 << 0) + + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + +// Tick + #define EXCEPTIONDBG_MODE_REG GPIO->P0_30_MODE_REG + #define EXCEPTIONDBG_SET_REG GPIO->P0_SET_DATA_REG + #define EXCEPTIONDBG_RESET_REG GPIO->P0_RESET_DATA_REG + #define EXCEPTIONDBG_PIN (1 << 30) + + #endif /* DEVICE_FAMILY */ + +#endif /* EXCEPTION_DEBUG */ + +/* Functional debug configuration + * + * Note that GPIO overlapping is allowed if the tracked events are discrete and the initial GPIO + * configuration is the same! No checking is performed for erroneous configuration though! + * + */ +#if (DEVICE_FAMILY == DA1468X) + + #if (CPM_USE_FUNCTIONAL_DEBUG == 0) + +// Tick (initial configuration: low) + #define CPMDBG_TICK_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_TICK_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_TICK_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_TICK_PIN (0) + +// External Wake-up (initial configuration: low) + #define CPMDBG_EXT_WKUP_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_EXT_WKUP_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_EXT_WKUP_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_EXT_WKUP_PIN (0) + +// Active / Sleep (initial configuration: high) + #define CPMDBG_POWERUP_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_POWERUP_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_POWERUP_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_POWERUP_PIN (0) + + #else + +// Tick (P2[3]) + #define CPMDBG_TICK_MODE_REG GPIO->P23_MODE_REG + #define CPMDBG_TICK_SET_REG GPIO->P2_SET_DATA_REG + #define CPMDBG_TICK_RESET_REG GPIO->P2_RESET_DATA_REG + #define CPMDBG_TICK_PIN (1 << 3) + +// External Wake-up (P3[0]) + #define CPMDBG_EXT_WKUP_MODE_REG GPIO->P30_MODE_REG + #define CPMDBG_EXT_WKUP_SET_REG GPIO->P3_SET_DATA_REG + #define CPMDBG_EXT_WKUP_RESET_REG GPIO->P3_RESET_DATA_REG + #define CPMDBG_EXT_WKUP_PIN (1 << 0) + +// Active / Sleep (P1[4]) + #define CPMDBG_POWERUP_MODE_REG GPIO->P14_MODE_REG + #define CPMDBG_POWERUP_SET_REG GPIO->P1_SET_DATA_REG + #define CPMDBG_POWERUP_RESET_REG GPIO->P1_RESET_DATA_REG + #define CPMDBG_POWERUP_PIN (1 << 4) + #endif + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + + #if (PWR_MGR_FUNCTIONAL_DEBUG == 0) + +// Dummy values to suppress compiler errors + #define PWRDBG_TICK_MODE_REG *(volatile int *) 0x20000000 + #define PWRDBG_TICK_SET_REG *(volatile int *) 0x20000000 + #define PWRDBG_TICK_RESET_REG *(volatile int *) 0x20000000 + #define PWRDBG_TICK_PIN (0) + + #define PWRDBG_POWERUP_MODE_REG *(volatile int *) 0x20000000 + #define PWRDBG_POWERUP_SET_REG *(volatile int *) 0x20000000 + #define PWRDBG_POWERUP_RESET_REG *(volatile int *) 0x20000000 + #define PWRDBG_POWERUP_PIN (0) + + #else + +// Tick + #define PWRDBG_TICK_MODE_REG GPIO->P0_19_MODE_REG + #define PWRDBG_TICK_SET_REG GPIO->P0_SET_DATA_REG + #define PWRDBG_TICK_RESET_REG GPIO->P0_RESET_DATA_REG + #define PWRDBG_TICK_PIN (1 << 19) + +// Active / Sleep + #define PWRDBG_POWERUP_MODE_REG GPIO->P0_21_MODE_REG + #define PWRDBG_POWERUP_SET_REG GPIO->P0_SET_DATA_REG + #define PWRDBG_POWERUP_RESET_REG GPIO->P0_RESET_DATA_REG + #define PWRDBG_POWERUP_PIN (1 << 21) + + #endif /* PWR_MGR_FUNCTIONAL_DEBUG */ + +#endif /* DEVICE_FAMILY */ + +/* Timing debug configuration + * + * Note that in this mode the pad latches are removed immediately after the execution resumes from + * the __WFI(). Because of this, it is not advised to use this feature in projects that use GPIOS. + * Nevertheless, in case it is used, make sure that the "peripheral initialization" is also done + * at that point, modifying sys_power_mgr.c accordingly. + * + * Note also that GPIO overlapping is allowed if the tracked events are discrete and the initial + * GPIO configuration is the same! No checking is performed for erroneous configuration though! + * + */ +#if (DEVICE_FAMILY == DA1468X) + + #if (CPM_USE_TIMING_DEBUG == 0) + +// CPM: sleep or idle entry (until __WFI() is called) (initial configuration: high) + #define CPMDBG_SLEEP_ENTER_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_ENTER_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_ENTER_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_ENTER_PIN (0) + +// CPM: sleep or idle exit (initial configuration: low) + #define CPMDBG_SLEEP_EXIT_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_EXIT_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_EXIT_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_SLEEP_EXIT_PIN (0) + +// Low clocks (initial configuration: low) + #define CPMDBG_LOWER_CLOCKS_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_LOWER_CLOCKS_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_LOWER_CLOCKS_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_LOWER_CLOCKS_PIN (0) + +// XTAL16M settling (initial configuration: low) + #define CPMDBG_XTAL16M_SETTLED_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_XTAL16M_SETTLED_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_XTAL16M_SETTLED_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_XTAL16M_SETTLED_PIN (0) + + #else + +// CPM: sleep or idle entry (until __WFI() is called) (P1[7]) + #define CPMDBG_SLEEP_ENTER_MODE_REG GPIO->P17_MODE_REG + #define CPMDBG_SLEEP_ENTER_SET_REG GPIO->P1_SET_DATA_REG + #define CPMDBG_SLEEP_ENTER_RESET_REG GPIO->P1_RESET_DATA_REG + #define CPMDBG_SLEEP_ENTER_PIN (1 << 7) + +// CPM: sleep or idle exit (P1[6]) + #define CPMDBG_SLEEP_EXIT_MODE_REG GPIO->P16_MODE_REG + #define CPMDBG_SLEEP_EXIT_SET_REG GPIO->P1_SET_DATA_REG + #define CPMDBG_SLEEP_EXIT_RESET_REG GPIO->P1_RESET_DATA_REG + #define CPMDBG_SLEEP_EXIT_PIN (1 << 6) + +// Low clocks (P1[5]) + #define CPMDBG_LOWER_CLOCKS_MODE_REG GPIO->P15_MODE_REG + #define CPMDBG_LOWER_CLOCKS_SET_REG GPIO->P1_SET_DATA_REG + #define CPMDBG_LOWER_CLOCKS_RESET_REG GPIO->P1_RESET_DATA_REG + #define CPMDBG_LOWER_CLOCKS_PIN (1 << 5) + +// XTAL16M settling (P1[4]) + #define CPMDBG_XTAL16M_SETTLED_MODE_REG GPIO->P14_MODE_REG + #define CPMDBG_XTAL16M_SETTLED_SET_REG GPIO->P1_SET_DATA_REG + #define CPMDBG_XTAL16M_SETTLED_RESET_REG GPIO->P1_RESET_DATA_REG + #define CPMDBG_XTAL16M_SETTLED_PIN (1 << 4) + + #endif /* CPM_USE_TIMING_DEBUG */ + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X) || (DEVICE_FAMILY == DA1640X)) + + #if (PWR_MGR_USE_TIMING_DEBUG == 0) + +// Dummy values to suppress compiler errors + #define PWRDBG_SLEEP_ENTER_MODE_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_ENTER_SET_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_ENTER_RESET_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_ENTER_PIN (0) + + #define PWRDBG_SLEEP_EXIT_MODE_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_EXIT_SET_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_EXIT_RESET_REG *(volatile int *) 0x20000000 + #define PWRDBG_SLEEP_EXIT_PIN (0) + + #else + +// Power manager: sleep or idle entry (until __WFI() is called) + #define PWRDBG_SLEEP_ENTER_MODE_REG GPIO->P0_17_MODE_REG + #define PWRDBG_SLEEP_ENTER_SET_REG GPIO->P0_SET_DATA_REG + #define PWRDBG_SLEEP_ENTER_RESET_REG GPIO->P0_RESET_DATA_REG + #define PWRDBG_SLEEP_ENTER_PIN (1 << 17) + +// Power manager: sleep or idle exit + #define PWRDBG_SLEEP_EXIT_MODE_REG GPIO->P0_18_MODE_REG + #define PWRDBG_SLEEP_EXIT_SET_REG GPIO->P0_SET_DATA_REG + #define PWRDBG_SLEEP_EXIT_RESET_REG GPIO->P0_RESET_DATA_REG + #define PWRDBG_SLEEP_EXIT_PIN (1 << 18) + + #endif /* CLK_MGR_USE_TIMING_DEBUG */ + + #if (CLK_MGR_USE_TIMING_DEBUG == 0) + +// Dummy values to suppress compiler errors + #define CLKDBG_LOWER_CLOCKS_MODE_REG *(volatile int *) 0x20000000 + #define CLKDBG_LOWER_CLOCKS_SET_REG *(volatile int *) 0x20000000 + #define CLKDBG_LOWER_CLOCKS_RESET_REG *(volatile int *) 0x20000000 + #define CLKDBG_LOWER_CLOCKS_PIN (0) + + #define CLKDBG_XTAL32M_SETTLED_MODE_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_SETTLED_SET_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_SETTLED_RESET_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_SETTLED_PIN (0) + + #define CLKDBG_XTAL32M_READY_MODE_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_READY_SET_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_READY_RESET_REG *(volatile int *) 0x20000000 + #define CLKDBG_XTAL32M_READY_PIN (0) + + #define CLKDBG_PLL_ON_MODE_REG *(volatile int *) 0x20000000 + #define CLKDBG_PLL_ON_SET_REG *(volatile int *) 0x20000000 + #define CLKDBG_PLL_ON_RESET_REG *(volatile int *) 0x20000000 + #define CLKDBG_PLL_ON_PIN (0) + + #else + +// Low clocks + #define CLKDBG_LOWER_CLOCKS_MODE_REG GPIO->P0_26_MODE_REG + #define CLKDBG_LOWER_CLOCKS_SET_REG GPIO->P0_SET_DATA_REG + #define CLKDBG_LOWER_CLOCKS_RESET_REG GPIO->P0_RESET_DATA_REG + #define CLKDBG_LOWER_CLOCKS_PIN (1 << 26) + +// XTAL32M settling + #define CLKDBG_XTAL32M_SETTLED_MODE_REG GPIO->P0_27_MODE_REG + #define CLKDBG_XTAL32M_SETTLED_SET_REG GPIO->P0_SET_DATA_REG + #define CLKDBG_XTAL32M_SETTLED_RESET_REG GPIO->P0_RESET_DATA_REG + #define CLKDBG_XTAL32M_SETTLED_PIN (1 << 27) + +// XTAL32M Ready IRQ + #define CLKDBG_XTAL32M_READY_MODE_REG GPIO->P0_28_MODE_REG + #define CLKDBG_XTAL32M_READY_SET_REG GPIO->P0_SET_DATA_REG + #define CLKDBG_XTAL32M_READY_RESET_REG GPIO->P0_RESET_DATA_REG + #define CLKDBG_XTAL32M_READY_PIN (1 << 28) + +// PLL is on + #define CLKDBG_PLL_ON_MODE_REG GPIO->P0_29_MODE_REG + #define CLKDBG_PLL_ON_SET_REG GPIO->P0_SET_DATA_REG + #define CLKDBG_PLL_ON_RESET_REG GPIO->P0_RESET_DATA_REG + #define CLKDBG_PLL_ON_PIN (1 << 29) + + #endif /* CLK_MGR_USE_TIMING_DEBUG */ + +#endif /* DEVICE_FAMILY */ + +#if (DEVICE_FAMILY == DA1468X) + + #if (USB_CHARGER_TIMING_DEBUG == 0) + +// CHRG: Inside critical section (initial configuration: low) + #define CHRGDBG_CRITICAL_SECTION_MODE_REG *(volatile int *) 0x20000000 + #define CHRGDBG_CRITICAL_SECTION_SET_REG *(volatile int *) 0x20000000 + #define CHRGDBG_CRITICAL_SECTION_RESET_REG *(volatile int *) 0x20000000 + #define CHRGDBG_CRITICAL_SECTION_PIN (0) + +// CHRG: FSM task (initial configuration: low) + #define CHRGDBG_FSM_TASK_MODE_REG *(volatile int *) 0x20000000 + #define CHRGDBG_FSM_TASK_SET_REG *(volatile int *) 0x20000000 + #define CHRGDBG_FSM_TASK_RESET_REG *(volatile int *) 0x20000000 + #define CHRGDBG_FSM_TASK_PIN (0) + +// CHRG: Control task (initial configuration: low) + #define CPMDBG_CONTROL_TASK_MODE_REG *(volatile int *) 0x20000000 + #define CPMDBG_CONTROL_TASK_SET_REG *(volatile int *) 0x20000000 + #define CPMDBG_CONTROL_TASK_RESET_REG *(volatile int *) 0x20000000 + #define CPMDBG_CONTROL_TASK_PIN (0) + + #else + +// CHRG: Inside critical section (P3[2]) + #define CHRGDBG_CRITICAL_SECTION_MODE_REG GPIO->P32_MODE_REG + #define CHRGDBG_CRITICAL_SECTION_SET_REG GPIO->P3_SET_DATA_REG + #define CHRGDBG_CRITICAL_SECTION_RESET_REG GPIO->P3_RESET_DATA_REG + #define CHRGDBG_CRITICAL_SECTION_PIN (1 << 2) + +// CHRG: FSM task (P3[3]) + #define CHRGDBG_FSM_TASK_MODE_REG GPIO->P33_MODE_REG + #define CHRGDBG_FSM_TASK_SET_REG GPIO->P3_SET_DATA_REG + #define CHRGDBG_FSM_TASK_RESET_REG GPIO->P3_RESET_DATA_REG + #define CHRGDBG_FSM_TASK_PIN (1 << 3) + +// CHRG: Control task (P3[4]) + #define CPMDBG_CONTROL_TASK_MODE_REG GPIO->P34_MODE_REG + #define CPMDBG_CONTROL_TASK_SET_REG GPIO->P3_SET_DATA_REG + #define CPMDBG_CONTROL_TASK_RESET_REG GPIO->P3_RESET_DATA_REG + #define CPMDBG_CONTROL_TASK_PIN (1 << 4) + + #endif /* USB_CHARGER_TIMING_DEBUG */ + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #if (SYS_CHARGER_TIMING_DEBUG == 0) + + #define SYS_CHARGER_DBG_VBUS_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_VBUS_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_VBUS_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_VBUS_PIN (0) + + #define SYS_CHARGER_DBG_CH_EVT_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_EVT_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_EVT_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_EVT_PIN (0) + + #define SYS_CHARGER_DBG_PRE_CH_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_PRE_CH_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_PRE_CH_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_PRE_CH_PIN (0) + + #define SYS_CHARGER_DBG_CH_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_CH_PIN (0) + + #define SYS_CHARGER_DBG_EOC_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_EOC_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_EOC_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_EOC_PIN (0) + + #define SYS_CHARGER_DBG_ENUM_DONE_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_ENUM_DONE_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_ENUM_DONE_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_ENUM_DONE_PIN (0) + + #define SYS_CHARGER_DBG_SUS_MODE_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_SUS_SET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_SUS_RESET_REG *(volatile int *) 0x20000000 + #define SYS_CHARGER_DBG_SUS_PIN (0) + + #else + + #define SYS_CHARGER_DBG_VBUS_MODE_REG GPIO->P1_10_MODE_REG + #define SYS_CHARGER_DBG_VBUS_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_VBUS_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_VBUS_PIN (1 << 10) + + #define SYS_CHARGER_DBG_CH_EVT_MODE_REG GPIO->P1_11_MODE_REG + #define SYS_CHARGER_DBG_CH_EVT_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_CH_EVT_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_CH_EVT_PIN (1 << 11) + + #define SYS_CHARGER_DBG_PRE_CH_MODE_REG GPIO->P1_12_MODE_REG + #define SYS_CHARGER_DBG_PRE_CH_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_PRE_CH_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_PRE_CH_PIN (1 << 12) + + #define SYS_CHARGER_DBG_CH_MODE_REG GPIO->P1_13_MODE_REG + #define SYS_CHARGER_DBG_CH_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_CH_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_CH_PIN (1 << 13) + + #define SYS_CHARGER_DBG_EOC_MODE_REG GPIO->P1_14_MODE_REG + #define SYS_CHARGER_DBG_EOC_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_EOC_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_EOC_PIN (1 << 14) + + #define SYS_CHARGER_DBG_ENUM_DONE_MODE_REG GPIO->P1_15_MODE_REG + #define SYS_CHARGER_DBG_ENUM_DONE_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_ENUM_DONE_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_ENUM_DONE_PIN (1 << 15) + + #define SYS_CHARGER_DBG_SUS_MODE_REG GPIO->P1_16_MODE_REG + #define SYS_CHARGER_DBG_SUS_SET_REG GPIO->P1_SET_DATA_REG + #define SYS_CHARGER_DBG_SUS_RESET_REG GPIO->P1_RESET_DATA_REG + #define SYS_CHARGER_DBG_SUS_PIN (1 << 16) + + #endif /* SYS_CHARGER_TIMING_DEBUG */ +#endif /* DEVICE_FAMILY */ + +#if (CMN_TIMING_DEBUG == 0) + +// Common: Inside critical section (initial configuration: low) + #define CMNDBG_CRITICAL_SECTION_MODE_REG *(volatile int *) 0x20000000 + #define CMNDBG_CRITICAL_SECTION_SET_REG *(volatile int *) 0x20000000 + #define CMNDBG_CRITICAL_SECTION_RESET_REG *(volatile int *) 0x20000000 + #define CMNDBG_CRITICAL_SECTION_PIN (0) + +#else + + #if (DEVICE_FAMILY == DA1468X) + +// Common: Inside critical section (P4[0]) + #define CMNDBG_CRITICAL_SECTION_MODE_REG GPIO->P40_MODE_REG + #define CMNDBG_CRITICAL_SECTION_SET_REG GPIO->P4_SET_DATA_REG + #define CMNDBG_CRITICAL_SECTION_RESET_REG GPIO->P4_RESET_DATA_REG + #define CMNDBG_CRITICAL_SECTION_PIN (1 << 0) + + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + +// Common: Inside critical section + #define CMNDBG_CRITICAL_SECTION_MODE_REG GPIO->P0_24_MODE_REG + #define CMNDBG_CRITICAL_SECTION_SET_REG GPIO->P0_SET_DATA_REG + #define CMNDBG_CRITICAL_SECTION_RESET_REG GPIO->P0_RESET_DATA_REG + #define CMNDBG_CRITICAL_SECTION_PIN (1 << 24) + + #endif /* DEVICE_FAMILY */ + +#endif /* CMN_TIMING_DEBUG */ + +/* Flash debug configuration + * + */ +#if (FLASH_DEBUG == 0) + +// Write page (initial configuration: low) + #define FLASHDBG_PAGE_PROG_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_PIN (0) + +// Program page wait loop (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_PIN (0) + +// Program page wait loop - pending irq check (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (0) + +// Suspend op (initial configuration: low) + #define FLASHDBG_SUSPEND_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_PIN (0) + +// Erase sector cmd (initial configuration: low) + #define FLASHDBG_SECTOR_ERASE_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SECTOR_ERASE_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SECTOR_ERASE_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SECTOR_ERASE_PIN (0) + +// Notify task (initial configuration: low) + #define FLASHDBG_TASK_NOTIFY_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_TASK_NOTIFY_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_TASK_NOTIFY_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_TASK_NOTIFY_PIN (0) + +// Suspend action (low level) (initial configuration: low) + #define FLASHDBG_SUSPEND_ACTION_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_ACTION_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_ACTION_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_SUSPEND_ACTION_PIN (0) + +// Resume op (initial configuration: low) + #define FLASHDBG_RESUME_MODE_REG *(volatile int *) 0x20000000 + #define FLASHDBG_RESUME_SET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_RESUME_RESET_REG *(volatile int *) 0x20000000 + #define FLASHDBG_RESUME_PIN (0) + +#else + + #if (DEVICE_FAMILY == DA1468X) + +// Write page (initial configuration: low) + #define FLASHDBG_PAGE_PROG_MODE_REG GPIO->P30_MODE_REG + #define FLASHDBG_PAGE_PROG_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_PIN (1 << 0) + +// Program page wait loop (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_MODE_REG GPIO->P31_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_PIN (1 << 1) + +// Program page wait loop - pending irq check (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG GPIO->P32_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (1 << 2) + +// Suspend op (initial configuration: low) + #define FLASHDBG_SUSPEND_MODE_REG GPIO->P33_MODE_REG + #define FLASHDBG_SUSPEND_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_SUSPEND_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_SUSPEND_PIN (1 << 3) + +// Erase sector cmd (initial configuration: low) + #define FLASHDBG_SECTOR_ERASE_MODE_REG GPIO->P34_MODE_REG + #define FLASHDBG_SECTOR_ERASE_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_PIN (1 << 4) + +// Notify task (initial configuration: low) + #define FLASHDBG_TASK_NOTIFY_MODE_REG GPIO->P35_MODE_REG + #define FLASHDBG_TASK_NOTIFY_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_PIN (1 << 5) + +// Suspend action (low level) (initial configuration: low) + #define FLASHDBG_SUSPEND_ACTION_MODE_REG GPIO->P36_MODE_REG + #define FLASHDBG_SUSPEND_ACTION_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_PIN (1 << 6) + +// Resume op (initial configuration: low) + #define FLASHDBG_RESUME_MODE_REG GPIO->P37_MODE_REG + #define FLASHDBG_RESUME_SET_REG GPIO->P3_SET_DATA_REG + #define FLASHDBG_RESUME_RESET_REG GPIO->P3_RESET_DATA_REG + #define FLASHDBG_RESUME_PIN (1 << 7) + + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + + #if DEVICE_FPGA + + #if (PWR_MGR_FUNCTIONAL_DEBUG == 1) || (PWR_MGR_USE_TIMING_DEBUG == 1) || (CLK_MGR_USE_TIMING_DEBUG == 1) + #error "Flash debug pins are also used by clock manager and power manager" + #endif + +// Write page (initial configuration: low) + #define FLASHDBG_PAGE_PROG_MODE_REG GPIO->P0_18_MODE_REG + #define FLASHDBG_PAGE_PROG_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_PIN (1 << 18) + +// Program page wait loop (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_MODE_REG GPIO->P0_19_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_PIN (1 << 19) + +// Program page wait loop - pending irq check (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG GPIO->P0_20_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (1 << 20) + +// Suspend op (initial configuration: low) + #define FLASHDBG_SUSPEND_MODE_REG GPIO->P0_21_MODE_REG + #define FLASHDBG_SUSPEND_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_SUSPEND_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_SUSPEND_PIN (1 << 21) + +// Erase sector cmd (initial configuration: low) + #define FLASHDBG_SECTOR_ERASE_MODE_REG GPIO->P0_26_MODE_REG + #define FLASHDBG_SECTOR_ERASE_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_PIN (1 << 26) + +// Notify task (initial configuration: low) + #define FLASHDBG_TASK_NOTIFY_MODE_REG GPIO->P0_27_MODE_REG + #define FLASHDBG_TASK_NOTIFY_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_PIN (1 << 27) + +// Suspend action (low level) (initial configuration: low) + #define FLASHDBG_SUSPEND_ACTION_MODE_REG GPIO->P0_28_MODE_REG + #define FLASHDBG_SUSPEND_ACTION_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_PIN (1 << 28) + +// Resume op (initial configuration: low) + #define FLASHDBG_RESUME_MODE_REG GPIO->P0_29_MODE_REG + #define FLASHDBG_RESUME_SET_REG GPIO->P0_SET_DATA_REG + #define FLASHDBG_RESUME_RESET_REG GPIO->P0_RESET_DATA_REG + #define FLASHDBG_RESUME_PIN (1 << 29) + + #else + +// Write page (initial configuration: low) + #define FLASHDBG_PAGE_PROG_MODE_REG GPIO->P1_01_MODE_REG + #define FLASHDBG_PAGE_PROG_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_PIN (1 << 1) + +// Program page wait loop (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_MODE_REG GPIO->P1_02_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_PIN (1 << 2) + +// Program page wait loop - pending irq check (initial configuration: low) + #define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG GPIO->P1_03_MODE_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (1 << 3) + +// Suspend op (initial configuration: low) + #define FLASHDBG_SUSPEND_MODE_REG GPIO->P1_04_MODE_REG + #define FLASHDBG_SUSPEND_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_SUSPEND_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_SUSPEND_PIN (1 << 4) + +// Erase sector cmd (initial configuration: low) + #define FLASHDBG_SECTOR_ERASE_MODE_REG GPIO->P1_05_MODE_REG + #define FLASHDBG_SECTOR_ERASE_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_SECTOR_ERASE_PIN (1 << 5) + +// Notify task (initial configuration: low) + #define FLASHDBG_TASK_NOTIFY_MODE_REG GPIO->P1_06_MODE_REG + #define FLASHDBG_TASK_NOTIFY_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_TASK_NOTIFY_PIN (1 << 6) + +// Suspend action (low level) (initial configuration: low) + #define FLASHDBG_SUSPEND_ACTION_MODE_REG GPIO->P1_07_MODE_REG + #define FLASHDBG_SUSPEND_ACTION_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_SUSPEND_ACTION_PIN (1 << 7) + +// Resume op (initial configuration: low) + #define FLASHDBG_RESUME_MODE_REG GPIO->P1_08_MODE_REG + #define FLASHDBG_RESUME_SET_REG GPIO->P1_SET_DATA_REG + #define FLASHDBG_RESUME_RESET_REG GPIO->P1_RESET_DATA_REG + #define FLASHDBG_RESUME_PIN (1 << 8) + + #endif /* DEVICE_FPGA */ + + #endif /* DEVICE_FAMILY */ + +#endif /* FLASH_DEBUG */ + +#endif /* BSP_DEBUG_H_ */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults.h new file mode 100644 index 000000000000..e00f97b8176c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults.h @@ -0,0 +1,662 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup BSP_CONFIG_DEFAULTS BSP Default Configuration Values + * + * \brief Board support package default configuration values + * \{ + */ + +/** + **************************************************************************************** + * + * @file bsp_defaults.h + * + * @brief Board Support Package. System configuration default values. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEFAULTS_H_ +#define BSP_DEFAULTS_H_ + +#include "../bsp_feature.h" + +/* ---------------------------------------------------------------------------------------------- */ + +#if DEVICE_FPGA + +/* Use FPGA-specific definitions first! */ + #include "bsp_defaults_fpga.h" +#endif + +/* ----------------------------------- Deprecated Configuration --------------------------------- */ + +/* Deprecated configuration options must not be defined by the application. */ + +#define DG_CONFIG_DEPRECATED_MSG " must not be defined by the application. This option is NO LONGER SUPPORTED" +#define DG_CONFIG_NOT_APPLICABLE_MSG " must not be defined by the application. It is NOT APPLICABLE" + +#ifdef dg_configPOWER_CONFIG + #error "dg_configPOWER_CONFIG must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " There's a single power configuration setup." +#endif + +#ifdef dg_configFORCE_DEEP_SLEEP + #error "dg_configFORCE_DEEP_SLEEP must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " Forcing the system to enter into clockless sleep during deep sleep is no longer supported." +#endif + +#ifdef dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE + #error \ + "dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE must not be defined by the application. This option is NO LONGER SUPPORTED." +#endif + +#ifdef dg_configUSE_ADC + #error "dg_configUSE_ADC must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " Specify the ADC block you wish to configure (i.e. dg_configUSE_HW_GPADC)." +#endif + +#ifdef dg_configCONFIG_HEADER_IN_FLASH + #error "dg_configCONFIG_HEADER_IN_FLASH must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " The values of the trim registers are not anymore taken from the Flash." +#endif + +#ifdef dg_configPOWER_EXT_1V8_PERIPHERALS + #error "dg_configPOWER_EXT_1V8_PERIPHERALS must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " Use dg_configPOWER_1V8P instead!" +#endif + +#ifdef dg_configUSE_HW_TEMPSENS + #error "dg_configUSE_HW_TEMPSENS must not be defined by the application. This option is NO LONGER SUPPORTED." \ + " Use dg_configUSE_HW_GPADC and HW_GPADC_INPUT_SE_TEMPSENS instead!" +#endif + +#ifdef dg_configINITIAL_SLEEP_DELAY_TIME + #pragma message "dg_configINITIAL_SLEEP_DELAY_TIME" DG_CONFIG_DEPRECATED_MSG ". At startup, the system will stay " \ + "active for at least dg_configXTAL32K_SETTLE_TIME before it is allowed to go to sleep." +#endif + +#ifdef dg_configPOWER_FLASH + #pragma message "dg_configPOWER_FLASH" DG_CONFIG_DEPRECATED_MSG + #undef dg_configPOWER_FLASH +#endif + +/* --------------------------------- Clock settings -------------------------------------------- */ + +/** + * \addtogroup CLOCK_SETTINGS Clock Settings (Low Power, XTAL etc.) + * + * \brief Settings for the different clock-types of the chip + * \{ + */ + +/** + * \brief Source of Low Power clock used (LP_CLK_IS_ANALOG, LP_CLK_IS_DIGITAL) + */ +#ifndef dg_configLP_CLK_SOURCE + #define dg_configLP_CLK_SOURCE LP_CLK_IS_ANALOG +#endif + +#if ((dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) && (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX)) + #error "When the LP source is digital (External), the option BSP_CLOCKS_SOURCE_LP_CLK_RCX is invalid!" +#endif + +/** + * \brief External LP type + * + * - 0: a crystal is connected to XTAL32Kp and XTALK32Km + * - 1: a digital clock is provided. + * + * \note the frequency of the digital clock must be 32KHz or 32.768KHz and be always running. + */ +#ifndef dg_configEXT_LP_IS_DIGITAL + #define dg_configEXT_LP_IS_DIGITAL (0) +#endif + +/** + * \brief Minimum sleep time + * + * No power savings if we enter sleep when the sleep time is less than N LP cycles. + * + * \note It should be ~3msec but this may vary. + */ +#ifndef dg_configMIN_SLEEP_TIME + #if (DEVICE_FAMILY == DA1640X) + + #ifndef BSP_DEVICE_REVISION + #error "BSP_DEVICE_REVISION is not defined" + #endif + #ifndef DEVICE_REV_A + #error "DEVICE_REV_A is not defined" + #endif + #ifndef DEVICE_REV_B + #error "DEVICE_REV_B is not defined" + #endif + + #if BSP_DEVICE_REVISION == DEVICE_REV_B + #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) + #define MIN_SCALE_MS (6) /* BA min 6 msec */ + #else + #define MIN_SCALE_MS (4) /* BA min 4 msec */ + #endif + #else // BSP_DEVICE_REVISION == DEVICE_REV_B + #if (dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) + #define MIN_SCALE_MS (7) /* AA min 7 msec */ + #else + #define MIN_SCALE_MS (6) /* AA min 6 msec */ + #endif + #endif // (DEVICE_VERSION == DEVICE_VER_B) + + #if ((BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) || \ + (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_XTAL32K)) + #define dg_configMIN_SLEEP_TIME (33 * MIN_SCALE_MS) + #elif (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) + #define dg_configMIN_SLEEP_TIME cm_rcx_us_2_lpcycles_low_acc((1000 * MIN_SCALE_MS)) + #else /* LP_CLK_ANY */ +/* Must be defined in the custom_config_<>.h file. It should be ~3msec but this may vary. */ + #endif + #else // (DEVICE_FAMILY != DA1640X) + #if ((BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) || \ + (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_XTAL32K)) + #define dg_configMIN_SLEEP_TIME (33 * 3) /* 3 msec */ + #elif (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) + #define dg_configMIN_SLEEP_TIME cm_rcx_us_2_lpcycles_low_acc(3000) /* 3 msec */ + #else /* LP_CLK_ANY */ +/* Must be defined in the custom_config_<>.h file. It should be ~3msec but this may vary. */ + #endif + #endif // (DEVICE_FAMILY == DA1640X) +#endif + +/** + * \} + */ + +/* ----------------------------------- Image Configuration -------------------------------------- */ + +/** + * \addtogroup IMAGE_CONFIGURATION_SETTINGS Image configuration settings + * + * \brief Image configuration settings + * + * \{ + */ + +/** + * \brief The motherboard revision we compile for. + */ +#ifndef dg_configBLACK_ORCA_MB_REV + #define dg_configBLACK_ORCA_MB_REV BLACK_ORCA_MB_REV_D +#endif + +/** + * \brief Controls how the image is built. + * + * - DEVELOPMENT_MODE: various debugging options are included. + * - PRODUCTION_MODE: all code used for debugging is removed. + */ +#ifndef dg_configIMAGE_SETUP + #define dg_configIMAGE_SETUP DEVELOPMENT_MODE +#endif + +/** + * \brief When set to 1, the delay at the start of execution of the Reset_Handler is skipped. + * + * \details This delay is added in order to facilitate proper programming of the Flash or QSPI\n + * launcher invocation. Without it, there is no guarantee that the execution of the image\n + * will not proceed, altering the default configuration of the system from the one that the\n + * bootloader leaves it. + */ +#ifndef dg_configSKIP_MAGIC_CHECK_AT_START + #define dg_configSKIP_MAGIC_CHECK_AT_START (0) +#endif + +/** + * \brief When set to 1, the QSPI copy will be emulated when in DEVELOPMENT_MODE (Not Applicable!). + */ +#ifndef dg_configEMULATE_QSPI_COPY + #define dg_configEMULATE_QSPI_COPY (0) +#endif + +/** + * \} + */ + +/* ----------------------------------- System Configuration ------------------------------------- */ + +/** + * \addtogroup SYSTEM_CONFIGURATION_SETTINGS System configuration settings + * + * \brief Generic System Configuration Settings + * + * \{ + */ + +/** + * \brief Image copy time + * + * The number of LP cycles needed for the application's image data to be copied from the OTP + * (or QSPI) to the RAM in mirrored mode. + * + * \warning MUST BE SMALLER THAN dg_configMIN_SLEEP_TIME !!! + */ +#if (dg_configEXEC_MODE != MODE_IS_MIRRORED) + #undef dg_configIMAGE_COPY_TIME + #define dg_configIMAGE_COPY_TIME (0) +#elif !defined(dg_configIMAGE_COPY_TIME) + #if ((BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) || \ + (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_XTAL32K)) + #define dg_configIMAGE_COPY_TIME (64) + #elif (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) + #define dg_configIMAGE_COPY_TIME cm_rcx_us_2_lpcycles(1950) + #endif +#endif + +/** + * \brief Brown-out Detection + * + * - 1: used + * - 0: not used + */ +#ifndef dg_configUSE_BOD + #define dg_configUSE_BOD (0) +#endif + +/** + * \brief Reset value for Watchdog. + * + * See WATCHDOG_REG:WDOG_VAL field. + */ +#ifndef dg_configWDOG_RESET_VALUE + #define dg_configWDOG_RESET_VALUE (0xFF) +#endif + +/** + * \brief Watchdog notify interval + * + * Interval (in milliseconds) for common timer which can be used to trigger tasks in order to notify + * watchdog. Can be set to 0 in order to disable timer code entirely. + */ +#ifndef dg_configWDOG_NOTIFY_TRIGGER_TMO + #define dg_configWDOG_NOTIFY_TRIGGER_TMO (0) +#endif + +/** + * \brief Abort a clock modification if it will cause an error to the SysTick counter + * + * - 1: on + * - 0: off + */ +#ifndef dg_configABORT_IF_SYSTICK_CLK_ERR + #define dg_configABORT_IF_SYSTICK_CLK_ERR (0) +#endif + +/** + * \brief Maximum adapters count + * + * Should be equal to the number of Adapters used by the Application. It can be larger (up to 254) + * than needed, at the expense of increased Retention Memory requirements. It cannot be 0. + */ +#ifndef dg_configPM_MAX_ADAPTERS_CNT + #define dg_configPM_MAX_ADAPTERS_CNT (16) +#endif + +/** + * \brief Maximum sleep defer time + * + * The maximum time sleep can be deferred via a call to pm_defer_sleep_for(). It is in clock cycles + * in the case of the XTAL32K and in usec in the case of RCX. + * \note It should be > 3.5msec. + */ +#ifndef dg_configPM_MAX_ADAPTER_DEFER_TIME + #if ((BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) || \ + (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_XTAL32K)) + #define dg_configPM_MAX_ADAPTER_DEFER_TIME (128) + #elif (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) + #define dg_configPM_MAX_ADAPTER_DEFER_TIME cm_rcx_us_2_lpcycles(4000) + #else /* LP_CLK_ANY */ +/* Must be defined in the custom_config_<>.h file. It should be > 3.5msec. */ + #endif +#endif + +/** + * \brief Apply ADC Gain Error correction. + * + * - 1: used + * - 0: not used + * + * The default setting is: 1. + */ +#ifndef dg_configUSE_ADC_GAIN_ERROR_CORRECTION + #define dg_configUSE_ADC_GAIN_ERROR_CORRECTION (1) +#endif + +/** + * \brief Image copy time + * + * The number of LP cycles needed for the application's image data to be copied from the OTP + * (or QSPI) to the RAM in mirrored mode. + * + * \warning MUST BE SMALLER THAN dg_configMIN_SLEEP_TIME !!! + */ +#if (dg_configEXEC_MODE != MODE_IS_MIRRORED) + #undef dg_configIMAGE_COPY_TIME + #define dg_configIMAGE_COPY_TIME (0) +#elif !defined(dg_configIMAGE_COPY_TIME) + #if ((BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) || \ + (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_XTAL32K)) + #define dg_configIMAGE_COPY_TIME (64) + #elif (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_LP_CLK_RCX) + #define dg_configIMAGE_COPY_TIME cm_rcx_us_2_lpcycles(1950) + #else /* LP_CLK_ANY */ +/* Must be defined in the custom_config_<>.h file. */ + #endif +#endif + +/** + * \brief When set to 1, the system will go to sleep and never exit allowing for the sleep current to be + * measured. + */ +#ifndef dg_configTESTMODE_MEASURE_SLEEP_CURRENT + #define dg_configTESTMODE_MEASURE_SLEEP_CURRENT (0) +#endif + +/** + * \} + */ + +/* ----------------------------------- USB Configuration ---------------------------------------- */ + +/** + * \addtogroup USB_SETTINGS USB configuration settings + * + * \brief USB configuration settings + * + * \{ + */ + +/** + * \brief Controls how the system will behave when the USB i/f is suspended. + * + * \details When the USB Node is suspended by the USB Host, the application may have to act in + * order to comply with the USB specification (consume less than 2.5mA). The available + * options are: + * 0: do nothing + * 1: pause system clock => the LP clock is stopped and only VBUS and USB irqs are handled + * 2: pause application => The system is not paused but the application must stop all + * timers and make sure all tasks are blocked. + * + * Both in modes 1 and 2, the application must make sure that all external peripherals are + * either powered off or placed in the lowest power consumption mode. + */ +#ifndef dg_configUSB_SUSPEND_MODE + #define dg_configUSB_SUSPEND_MODE USB_SUSPEND_MODE_NONE +#endif + +/** + * \brief Enable the DMA for reading/writing data to USB EP.\n + * By default the USB DMA is not enabled.\n + * To enable the DMA for the USB, set this the macro to value (1) in the custom_config_xxx.h file.\n + * When the USB DMA is enabled, the default end points with DMA are EP1 and EP2. \n + * It is possible only one TX and one RX end point to use DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the end points using DMA, set in the the custom_config_xxx.h file the desired values for the macros: + * \par \c dg_configUSB_TX_DMA_EP + * valid values: 1,3,5\n + * default value: 1 + * \par \c dg_configUSB_RX_DMA_EP + * valid values: 2,4,6\n + * default value: 2 + */ +#ifndef dg_configUSB_DMA_SUPPORT + #define dg_configUSB_DMA_SUPPORT (0) +#endif + +/** + * \brief The USB TX end point (D-->H) to enable the DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the TX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. + * \par \c dg_configUSB_TX_DMA_EP + * valid values: 1,3,5\n + * default value: 1 + */ +#ifndef dg_configUSB_TX_DMA_EP + #define dg_configUSB_TX_DMA_EP (1) +#endif + +/** + * \brief The USB RX end point (D-->H) to enable the DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the RX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. + * \par \c dg_configUSB_RX_DMA_EP + * valid values: 2,4,6\n + * default value: 2 + */ +#ifndef dg_configUSB_RX_DMA_EP + #define dg_configUSB_RX_DMA_EP (2) +#endif + +/** + * \} + */ + +/* ----------------------------------- Flash Configuration -------------------------------------- */ + +/** + * \addtogroup FLASH_SETTINGS Flash configuration settings + * + * \brief Flash configuration settings + * + * \{ + */ + +/* Backward compatibility check */ + +#if defined(dg_configPOWER_FLASH) || defined(dg_configFLASH_POWER_OFF) + #define PRINT_POWER_RAIL_SETUP +#endif + +/** + * \brief Enable the Flash Auto-detection mode for QSPIC + * + * \warning THIS WILL GREATLY INCREASE THE CODE SIZE AND RETRAM USAGE!!! MAKE SURE YOUR PROJECT + * CAN SUPPORT THIS. + */ +#ifndef dg_configFLASH_AUTODETECT + #define dg_configFLASH_AUTODETECT (0) +#endif + +/** + * \brief Offset of the image if not placed at the beginning of QSPI Flash. + */ +#ifndef dg_configIMAGE_FLASH_OFFSET + #define dg_configIMAGE_FLASH_OFFSET (0) +#endif + +/** + * \brief Set the flash page size. + */ +#ifndef dg_configFLASH_MAX_WRITE_SIZE + #define dg_configFLASH_MAX_WRITE_SIZE (128) +#endif + +/** + * \brief Disable background operations. + * + * When enabled, outstanding QSPI operations will take place during sleep time + * increasing the efficiency. + * + * - 1 : Disabled + * - 0 : Enabled + */ +#ifndef dg_configDISABLE_BACKGROUND_FLASH_OPS + #define dg_configDISABLE_BACKGROUND_FLASH_OPS (1) +#endif + +/** + * \} + */ + +/* ----------------------------------- Cache Configuration -------------------------------------- */ + +/** + * \addtogroup CACHE_SETTINGS Cache configuration settings + * + * \brief Cache configuration settings + * + * \{ + */ + +/** + * \brief Set the size (in bytes) of the QSPI flash cacheable area. + * + * All reads from offset 0 up to (not including) offset dg_configCACHEABLE_QSPI_AREA_LEN + * will be cached. In addition, any writes to this area will trigger cache flushing, to + * avoid any cache incoherence. + * + * The size must be 64KB-aligned, due to the granularity of CACHE_CTRL2_REG[CACHE_LEN]. + * + * Special values: + * * 0 : Turn off cache. + * * -1 : Don't configure cacheable area size (i.e. leave as set by booter). + */ +#ifndef dg_configCACHEABLE_QSPI_AREA_LEN + #define dg_configCACHEABLE_QSPI_AREA_LEN (-1) +#endif + +/** + * \brief Set the associativity of the cache. + * + * Available values: + * 0 /// direct-mapped + * 1 /// 2-way set associative + * 2 /// 4-way set associative + * 3 /// leave as set by the ROM booter + */ +#ifndef dg_configCACHE_ASSOCIATIVITY + #define dg_configCACHE_ASSOCIATIVITY (2) +#endif + +/** + * \brief Set the line size of the cache. + * + * Available values: + * 0 /// 8 bytes + * 1 /// 16 bytes + * 2 /// 32 byte + * 3 /// leave as set by the ROM booter + */ +#ifndef dg_configCACHE_LINESZ + #define dg_configCACHE_LINESZ (0) +#endif + +/** + * \} + */ + +/* ----------------------------------- UART settings -------------------------------------------- */ + +/** + * \addtogroup UART_SETTINGS UART configuration settings + * + * \brief UART configuration settings + * + * \{ + */ + +/** + * \brief Circular DMA support for RX + */ +#ifndef dg_configUART_RX_CIRCULAR_DMA + #define dg_configUART_RX_CIRCULAR_DMA (0) +#endif + +/** + * \brief UART1's Circular DMA buffer size for RX + */ +#ifndef dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE + #define dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE (0) +#endif + +/** + * \brief UART2's Circular DMA buffer size for RX + */ +#ifndef dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE + #define dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE (0) +#endif + +/** + * \} + */ + +/* ----------------------------------- RF Configuration ----------------------------------------- */ + +/** + * \addtogroup RF_DRIVER_SETTINGS Radio Driver Settings + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * \{ + */ + +/** + * \brief Set to 1 to enable the recalibration procedure. + */ +#if defined(CONFIG_USE_BLE) + #ifndef dg_configRF_ENABLE_RECALIBRATION + #define dg_configRF_ENABLE_RECALIBRATION (1) + #endif +#endif + +/** + * \} + */ + +/* ----------------------------------- DEVICE-SPECIFIC CONFIGURATION ---------------------------- */ + +#if (DEVICE_FAMILY == DA1640X) + + #include "bsp_defaults_ra6w1.h" + +#endif + +/* ----------------------------------- DEBUG CONFIGURATION ------------------ ------------------- */ + +#include "bsp_debug.h" + +/* ----------------------------------- MEMORY LAYOUT CONFIGURATION ------------------------------ */ + +#include "bsp_memory_defaults.h" + +/* XXX ------------------------------- UNDISCLOSED DEFINITIONS ---------------------------------- */ + +#include "bsp_undisclosed_defs.h" + +#endif /* BSP_DEFAULTS_H_ */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults_ra6w1.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults_ra6w1.h new file mode 100644 index 000000000000..4f93b310c518 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_defaults_ra6w1.h @@ -0,0 +1,904 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup BSP_CONFIG_DEFAULTS + * \{ + */ + +/** + **************************************************************************************** + * + * @file bsp_defaults_ra6w1.h + * + * @brief Board Support Package. Device-specific system configuration default values. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEFAULTS_RA6W1_H_ +#define BSP_DEFAULTS_RA6W1_H_ + +#if (DEVICE_FAMILY == DA1640X) + +/* Deprecated configuration options must not be defined by the application. */ + + #define DG_CONFIG_NA_87X_MSG DG_CONFIG_NOT_APPLICABLE_MSG " for the DA1640x device family." + #define DG_CONFIG_NA_87X_FORCE_ZERO_MSG DG_CONFIG_NA_87X_MSG " Forcing to 0 (not used)." + #define DG_CONFIG_TIMER_NA_MSG DG_CONFIG_NA_87X_MSG " Use the generic dg_configUSE_HW_TIMER instead." + + #ifdef dg_configTim1Prescaler + #pragma message "dg_configTim1Prescaler" DG_CONFIG_NA_87X_MSG + #undef dg_configTim1Prescaler + #endif + + #ifdef dg_configTim1PrescalerBitRange + #pragma message "dg_configTim1PrescalerBitRange" DG_CONFIG_NA_87X_MSG + #undef dg_configTim1PrescalerBitRange + #endif + + #ifdef dg_configEXT_CRYSTAL_FREQ + #pragma message "dg_configEXT_CRYSTAL_FREQ" DG_CONFIG_NA_87X_MSG + #undef dg_configEXT_CRYSTAL_FREQ + #endif + + #ifdef dg_configUSER_CAN_USE_TIMER1 + #pragma message "dg_configUSER_CAN_USE_TIMER1" DG_CONFIG_NA_87X_MSG + #undef dg_configUSER_CAN_USE_TIMER1 + #endif + + #if (dg_configUSE_HW_RF != 0) + #pragma message "dg_configUSE_HW_RF" DG_CONFIG_NA_87X_FORCE_ZERO_MSG + #undef dg_configUSE_HW_RF + #define dg_configUSE_HW_RF 0 + #endif + + #if (dg_configUSE_HW_ECC != 0) + #pragma message "dg_configUSE_HW_ECC" DG_CONFIG_NA_87X_FORCE_ZERO_MSG + #undef dg_configUSE_HW_ECC + #define dg_configUSE_HW_ECC 0 + #endif + + #if (dg_configUSE_IF_PDM != 0) + #pragma message "dg_configUSE_IF_PDM" DG_CONFIG_NA_87X_FORCE_ZERO_MSG + #undef dg_configUSE_IF_PDM + #define dg_configUSE_IF_PDM 0 + #endif + + #if (dg_configUSE_HW_IRGEN != 0) + #pragma message "dg_configUSE_HW_TEMPSENS" DG_CONFIG_NA_87X_FORCE_ZERO_MSG + #undef dg_configUSE_HW_IRGEN + #define dg_configUSE_HW_IRGEN 0 + #endif + + #if (dg_configUSE_HW_SOC != 0) + #pragma message "dg_configUSE_HW_SOC" DG_CONFIG_NA_87X_FORCE_ZERO_MSG + #undef dg_configUSE_HW_SOC + #define dg_configUSE_HW_SOC 0 + #endif + + #if (dg_configUSE_HW_TIMER0 != 0) + #pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG + #undef dg_configUSE_HW_TIMER0 + #define dg_configUSE_HW_TIMER0 0 + #endif + + #if (dg_configUSE_HW_TIMER1 != 0) + #pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG + #undef dg_configUSE_HW_TIMER1 + #define dg_configUSE_HW_TIMER1 0 + #endif + + #if (dg_configUSE_HW_TIMER2 != 0) + #pragma message "dg_configUSE_HW_TIMERX" DG_CONFIG_TIMER_NA_MSG + #undef dg_configUSE_HW_TIMER2 + #define dg_configUSE_HW_TIMER2 0 + #endif + +/* ------------------------------- Peripherals -------------------------------------------------- */ + +/** + * \addtogroup PERIPHERALS_690 Peripherals for DA1487x + * + * \brief Peripheral Selection for the DA1487x Device Family + * + * When enabled the specific low level driver is included in the compilation of the SDK. + * - 0 : Disabled + * - 1 : Enabled + * + * The default option can be overridden in the application configuration file. + * + * \{ + * Driver | Setting | Default option + * ------------------------------ | -------------------------------------- | :------------------: + * AES HASH | dg_configUSE_HW_AES_HASH | 0 + * Cache Controller | dg_configUSE_HW_CACHE | 1 + * HW charger | dg_configUSE_HW_CHARGER | 0 + * Clock driver | dg_configUSE_HW_CLK | 1 + * Clock and Power Manager | dg_configUSE_HW_CPM | 1 + * Direct Memory Access | dg_configUSE_HW_DMA | 1 + * Haptic Controller / ERM | dg_configUSE_HW_ERM | 0 + * General Purpose A-D Converter | dg_configUSE_HW_GPADC | 1 + * General Purpose I/O | dg_configUSE_HW_GPIO | 1 + * Inter-Integrated Circuit | dg_configUSE_HW_I2C | 0 + * ISO7816 | dg_configUSE_HW_ISO7816 | 0 + * LCD controller | dg_configUSE_HW_LCDC | 0 + * Haptic Controller / LRA | dg_configUSE_HW_LRA | 0 + * Memory Protection Unit | dg_configUSE_HW_MPU | 0 + * OQSPI controller | dg_configUSE_HW_OQSPI | 1 + * OTP controller | dg_configUSE_HW_OTPC | 1 + * Domain Driver | dg_configUSE_HW_PD | 1 + * Power Domains Controller | dg_configUSE_HW_PDC | 1 + * Power Manager | dg_configUSE_HW_PMU | 1 + * QSPI controller | dg_configUSE_HW_QSPI | 0 + * Real Time Clock | dg_configUSE_HW_RTC | 1 + * Analog-Digital Converter | dg_configUSE_HW_SDADC | 1 + * Sensor Node Controller | dg_configUSE_HW_SENSOR_NODE | 0 + * Motor Controller | dg_configUSE_HW_SMOTOR | 0 + * Serial Peripheral Interface | dg_configUSE_HW_SPI | 0 + * System | dg_configUSE_HW_SYS | 1 + * Timer | dg_configUSE_HW_TIMER | 1 + * True Random Generator | dg_configUSE_HW_TRNG | 1 + * UART | dg_configUSE_HW_UART | 1 + * USB | dg_configUSE_HW_USB | 0 + * USB charger | dg_configUSE_HW_USB_CHARGER | 0 + * Wakeup timer | dg_configUSE_HW_WKUP | 1 + * PCM | dg_configUSE_HW_PCM | 0 + * PDM | dg_configUSE_HW_PDM | 0 + * APU SRC | dg_configUSE_HW_APU_SRC | 0 + */ + +/* -------------------------------- Peripherals (hw_*) selection -------------------------------- */ + + #ifndef dg_configUSE_HW_AES_HASH + #define dg_configUSE_HW_AES_HASH (0) + #endif + + #ifndef dg_configUSE_HW_CACHE + #define dg_configUSE_HW_CACHE (1) + #endif + + #ifndef dg_configUSE_HW_CHARGER + #define dg_configUSE_HW_CHARGER (0) + #endif + + #ifndef dg_configUSE_HW_CLK + #define dg_configUSE_HW_CLK (1) + #endif + + #ifndef dg_configUSE_HW_CPM + #define dg_configUSE_HW_CPM (0) + #endif + + #ifndef dg_configUSE_HW_DMA + #define dg_configUSE_HW_DMA (1) + #endif + + #ifndef dg_configUSE_HW_KDMA + #define dg_configUSE_HW_KDMA (0) + #endif + + #ifndef dg_configUSE_HW_ERM + #define dg_configUSE_HW_ERM (0) + #endif + + #ifndef dg_configUSE_HW_GPADC + #define dg_configUSE_HW_GPADC (0) + #endif + + #if 0 /* TODO : Check this needs */ +/* XXX workaround for bug2522A_155: PLL calibration does not work properly */ +/* XXX GPADC is used for PLL workaround in case there isn't trimmed value for PLL_SYS_CTRL3_REG */ + #if !DEVICE_FPGA + #if (dg_configUSE_HW_GPADC == 0) + #error "dg_configUSE_HW_GPADC should be 1 in order to properly trim the PLL clock" + #endif + #endif + #endif + + #ifndef dg_configUSE_HW_GPIO + #define dg_configUSE_HW_GPIO (1) + #endif + + #ifndef dg_configUSE_HW_I2C + #define dg_configUSE_HW_I2C (0) + #endif + + #ifndef dg_configUSE_HW_ISO7816 + #define dg_configUSE_HW_ISO7816 (0) + #endif + + #ifndef dg_configUSE_HW_LCDC + #define dg_configUSE_HW_LCDC (0) + #endif + + #ifndef dg_configUSE_HW_LRA + #define dg_configUSE_HW_LRA (0) + #endif + + #ifndef dg_configUSE_HW_MPU + #define dg_configUSE_HW_MPU (0) + #endif + + #ifndef dg_configUSE_HW_OQSPI + #define dg_configUSE_HW_OQSPI (1) + #endif + + #ifndef dg_configUSE_HW_OTPC + #define dg_configUSE_HW_OTPC (1) + #endif + + #ifndef dg_configUSE_HW_PD + #define dg_configUSE_HW_PD (0) + #endif + + #ifndef dg_configUSE_HW_PDC + #define dg_configUSE_HW_PDC (0) + #endif + + #ifndef dg_configUSE_HW_PMU + #define dg_configUSE_HW_PMU (0) + #endif + + #ifndef dg_configUSE_HW_QSPI + #define dg_configUSE_HW_QSPI (0) + #endif + + #ifndef dg_configUSE_HW_QSPI2 + #define dg_configUSE_HW_QSPI2 (0) + #elif (dg_configUSE_HW_QSPI2 == 1) + #error "DA1640X has no QSPI2" + #endif + + #ifndef dg_configUSE_HW_RTC + #define dg_configUSE_HW_RTC (1) + #endif + + #ifndef dg_configUSE_HW_SDADC + #define dg_configUSE_HW_SDADC (0) + #endif + + #ifndef dg_configUSE_HW_SENSOR_NODE + #define dg_configUSE_HW_SENSOR_NODE (0) + #endif + + #ifndef dg_configUSE_HW_SMOTOR + #define dg_configUSE_HW_SMOTOR (0) + #endif + + #ifndef dg_configUSE_HW_SPI + #define dg_configUSE_HW_SPI (0) + #endif + + #ifndef dg_configUSE_HW_SYS + #define dg_configUSE_HW_SYS (0) + #endif + + #ifndef dg_configUSE_HW_TIMER + #define dg_configUSE_HW_TIMER (1) + #endif + + #ifndef dg_configUSE_HW_TRNG + #define dg_configUSE_HW_TRNG (0) + #endif + + #ifndef dg_configUSE_HW_UART + #define dg_configUSE_HW_UART (1) + #endif + + #ifndef dg_configUSE_HW_USB + #define dg_configUSE_HW_USB (0) + #endif + + #ifndef dg_configUSE_HW_USB_CHARGER + #define dg_configUSE_HW_USB_CHARGER (0) + #endif + + #ifndef dg_configUSE_HW_WKUP + #define dg_configUSE_HW_WKUP (0) + #endif + + #ifndef dg_configUSE_HW_PCM + #define dg_configUSE_HW_PCM (0) + #endif + + #ifndef dg_configUSE_HW_PDM + #define dg_configUSE_HW_PDM (0) + #endif + + #ifndef dg_configUSE_HW_APU_SRC + #define dg_configUSE_HW_APU_SRC (0) + #endif + + #ifndef dg_configUSE_HW_SDEMMC + #define dg_configUSE_HW_SDEMMC (1) + #endif + + #ifndef dg_configUSE_HW_SDIO + #define dg_configUSE_HW_SDIO (1) + #endif + + #ifndef dg_configUSE_HW_PRNG + #define dg_configUSE_HW_PRNG (1) + #endif + +/** + * \} + */ + +/* ------------------------------- Clock Settings ----------------------------------------------- */ + +/** + * \addtogroup CLOCK_SETTINGS + * + * \{ + */ + + #if (BSP_CFG_LP_CLOCK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_RCX) && \ + (BSP_CFG_LP_CLOCK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_XTALK) + #error "BSP_CFG_LP_CLOCK_SOURCE has invalid setting" + #endif + + #ifndef dg_configXTAL40M_FREQ + #define dg_configXTAL40M_FREQ (40000000) + #endif + + #ifndef dg_configXTAL80M_FREQ + #define dg_configXTAL80M_FREQ (80000000) + #endif + + #ifndef dg_configDIVN_FREQ + #define dg_configDIVN_FREQ (40000000) + #endif + + #ifndef dg_configPLL480M_FREQ + #define dg_configPLL480M_FREQ (480000000) + #endif + + #ifndef dg_configPLL320M_FREQ + #define dg_configPLL320M_FREQ (320000000) + #endif + + #ifndef dg_configPLL192M_FREQ + #define dg_configPLL192M_FREQ (192000000) + #endif + + #ifndef dg_configPLL160M_FREQ + #define dg_configPLL160M_FREQ (160000000) + #endif + + #ifndef dg_configPLL137M_FREQ + #define dg_configPLL137M_FREQ (137142857) + #endif + + #ifndef dg_configPLL106M_FREQ + #define dg_configPLL106M_FREQ (106666666) + #endif + + #ifndef dg_configPLL80M_FREQ + #define dg_configPLL80M_FREQ (80000000) + #endif + + #ifndef dg_configPERI80M_FREQ + #define dg_configPERI80M_FREQ (80000000) + #endif + + #ifndef dg_configPERI40M_FREQ + #define dg_configPERI40M_FREQ (40000000) + #endif + + #ifndef dg_configPERIOCS32K_FREQ + #define dg_configPERIOCS32K_FREQ (32000) + #endif + + #ifndef dg_configPERICRY32K_FREQ + #define dg_configPERICRY32K_FREQ (32768) + #endif + +/** + * \brief Vaule of the RC32K oscilator frequency in Hz + */ + #ifndef dg_configRC32K_FREQ + #define dg_configRC32K_FREQ (32000) + #endif + + #ifndef dg_configXTAL32K_FREQ + #define dg_configXTAL32K_FREQ (32768) + #endif + + #ifndef dg_configXTAL40M_32K_FREQ + #define dg_configXTAL40M_32K_FREQ (32000) + #endif + +/** + * \brief Acceptable clock tick drift (in parts per million) for the Low-power clock + */ + #ifndef dg_configLP_CLK_DRIFT + #if BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_RCX + #define dg_configLP_CLK_DRIFT (500) // ppm + #else + #define dg_configLP_CLK_DRIFT (50) // ppm + #endif + #endif + +/** + * \brief Time needed for the settling of the LP clock, in msec. + */ + #ifndef dg_configXTAL32K_SETTLE_TIME + #if dg_configLP_CLK_SOURCE == LP_CLK_IS_ANALOG + #define dg_configXTAL32K_SETTLE_TIME (1300) + #else + #define dg_configXTAL32K_SETTLE_TIME (1000) + #endif + #endif + +/** + * \brief XTAL40M settle time + * + * Time needed for the settling of the XTAL40M, in usec. + * + * \note If set to zero, the settling time will be automatically adjusted. + */ + #ifndef dg_configXTAL40M_SETTLE_TIME_IN_USEC + #define dg_configXTAL40M_SETTLE_TIME_IN_USEC (0x0) + #endif + +/** + * \brief Enable XTAL40M upon system wake-up + * + * If set to 1 the PDC will enable XTAL40M when it wakes-up M33 + * + */ + #ifndef dg_configENABLE_XTAL40M_ON_WAKEUP + #define dg_configENABLE_XTAL40M_ON_WAKEUP (1) + #endif + +/** + * \brief The number of LP clock cycles required to check the voltage of an LDO during startup + */ + #ifndef dg_configVOLTAGE_CHECK_LP_CYCLES + #define dg_configVOLTAGE_CHECK_LP_CYCLES (5) + #endif + +/** + * \brief The number of LP clock cycles required for the HW FSM to detect the wake-up signal + */ + #ifndef dg_configHW_FSM_WAKEUP_CYCLES + #define dg_configHW_FSM_WAKEUP_CYCLES (3) + #endif + +/** + * \brief The number of LP clock cycles required for the system to start-up + */ + #ifndef dg_configSYSTEM_STARTUP_CYCLES + +// 4 @ SRAM Boot +// unstable 12, stable 16?/20 @ Cache Boot 1.8V, Fully discharged PWR +// unstable 33, stable 36?/40 @ Cache Boot 3.3V, Fully discharged PWR +// max 100 @ VSIM contidion + #define dg_configSYSTEM_STARTUP_CYCLES (100) + #endif + +/** + * \brief RC32 wake-up time in slow wake-up mode + * + * This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code + * using RC32 in slow wake-up mode. + * + * \note Wake-up time calculation: + * dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up + * 1 additional cycle for slow wake-up + * 2 cycles for V30 (worst case Vclamp -> 3V) + * 1 cycle for BG + * dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V12 and V14 + * dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V18P + * dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V18 + * dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up + */ + #define dg_configWAKEUP_RC32_TIME_SLOW (dg_configHW_FSM_WAKEUP_CYCLES + 4 + \ + 3 * dg_configVOLTAGE_CHECK_LP_CYCLES + \ + dg_configSYSTEM_STARTUP_CYCLES) + +/** + * \brief RC32 wake-up time in fast wake-up mode + * + * This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code + * using RC32 in fast wake-up mode. + * + * \note Wake-up time calculation: + * dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up + * dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V12 (worst case 0.75V -> 0.9V) + * dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up + */ + #define dg_configWAKEUP_RC32_TIME_FAST (dg_configHW_FSM_WAKEUP_CYCLES + \ + dg_configVOLTAGE_CHECK_LP_CYCLES + \ + dg_configSYSTEM_STARTUP_CYCLES) + +/** + * \brief RC32 wake-up time + * + * This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code + * using RC32 in ultra-fast wake-up mode. + * + * \note Wake-up time calculation: + * dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up + * dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up + */ + #define dg_configWAKEUP_RC32_TIME_ULTRA_FAST (dg_configHW_FSM_WAKEUP_CYCLES + \ + dg_configSYSTEM_STARTUP_CYCLES) + +/** + * \brief XTAL32M trimming default settings + */ + #ifndef dg_configDEFAULT_CLK_FREQ_TRIM_REG__XTAL32M_TRIM__VALUE + #define dg_configDEFAULT_CLK_FREQ_TRIM_REG__XTAL32M_TRIM__VALUE (0x120) + #endif + + #ifndef dg_configDEFAULT_XTAL32M_CTRL0_REG__XTAL32M_CXCOMP_ENABLE__VALUE + #define dg_configDEFAULT_XTAL32M_CTRL0_REG__XTAL32M_CXCOMP_ENABLE__VALUE (0x0) + #endif + + #ifndef dg_configUSE_CLOCK_MGR + #ifdef OS_BAREMETAL + #define dg_configUSE_CLOCK_MGR (0) + #elif defined(OS_FREERTOS) + #define dg_configUSE_CLOCK_MGR (0) + #endif + #endif + +/** + * \} + */ + +/* ------------------------------- System configuration settings -------------------------------- */ + +/** + * \addtogroup SYSTEM_CONFIGURATION_SETTINGS + * + * \{ + */ + +/** + * \brief Reset value for Watchdog when system is idle. + */ + #ifndef dg_configWDOG_IDLE_RESET_VALUE + #define dg_configWDOG_IDLE_RESET_VALUE (SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk >> SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos) + #endif + +/** + * \brief Maximum watchdog tasks + * + * Maximum number of tasks that the Watchdog Service can monitor. It can be larger (up to 32) than + * needed, at the expense of increased Retention Memory requirement. + */ + #ifndef dg_configWDOG_MAX_TASKS_CNT + #define dg_configWDOG_MAX_TASKS_CNT (64) + #endif + +/** + * \brief Extend maximum watchdog tasks + * + * When set to 1, maximum number of tasks can be larger (up to 64). + */ + #ifndef dg_configWDOG_EXT + #define dg_configWDOG_EXT (1) + #endif + +/* + * \brief When set to 1, the LEDs are used from M33. + * When set to 0, the LEDs are used from SNC. + */ + #ifndef dg_configM33_USES_LEDS + #define dg_configM33_USES_LEDS (1) + #endif + +/* + * \brief When set to 1, the GPIO configuration becomes static, i.e. it does not change during runtime. + * When set to 0, the GPIO configuration can change during runtime. + * + * \note If SNC is enabled (i.e. dg_configUSE_HW_SENSOR_NODE == 1), the GPIO configuration must be + * static, thus dg_configUSE_STATIC_IO_CONFIG is set to 1 + */ + #if dg_configUSE_HW_SENSOR_NODE + #undef dg_configUSE_STATIC_IO_CONFIG + #define dg_configUSE_STATIC_IO_CONFIG (1) + #else + #ifndef dg_configUSE_STATIC_IO_CONFIG + #define dg_configUSE_STATIC_IO_CONFIG (0) + #endif + #endif + +/** + * \} + */ + +/* -------------------------------------- Flash settings ---------------------------------------- */ + +/** + * \addtogroup FLASH_SETTINGS + * + * \{ + */ + +/** + * \brief When set to 1, the 1V8 rail is powered, when the system is in active state. + * When set to 2 the rail configuration will be defined by the application + */ + #ifndef dg_configPOWER_1V8_ACTIVE + #define dg_configPOWER_1V8_ACTIVE (2) + #else + #if (dg_configPOWER_1V8_ACTIVE == 0) && (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) + #error \ + "Flash is connected to the 1V8 rail but the rail is turned off. Please do not set dg_configPOWER_1V8_ACTIVE to 0." + #endif + #endif + +/** + * \brief When set to 1, the 1V8 is powered during sleep. + * When set to 2 the rail configuration will be defined by the application + */ + #ifndef dg_configPOWER_1V8_SLEEP + #define dg_configPOWER_1V8_SLEEP (2) + #endif + +/** + * \brief When set to 1, the 1V8P rail is powered. + */ + #ifdef dg_configPOWER_1V8P + #if defined(dg_configPOWER_1V8P_ACTIVE) || defined(dg_configPOWER_1V8P_SLEEP) + #error "dg_configPOWER_1V8P cannot be used when dg_configPOWER_1V8P_ACTIVE or dg_configPOWER_1V8P_SLEEP is used" + #else + #if dg_configPOWER_1V8P == 1 + #define dg_configPOWER_1V8P_ACTIVE (1) + #define dg_configPOWER_1V8P_SLEEP (1) + #else + #error \ + "GPADC digital logic is connected to the 1V8P rail but the rail is turned off. Please do not set dg_configPOWER_1V8P to 0." + #endif + #endif + #endif + +/** + * \brief When set to 1, the 1V8P rail is powered, when the system is in active state. + * When set to 2 the rail configuration will be defined by the application + */ + #ifndef dg_configPOWER_1V8P_ACTIVE + #define dg_configPOWER_1V8P_ACTIVE (2) + #else + #if dg_configPOWER_1V8P_ACTIVE == 0 + #error \ + "GPADC digital logic is connected to the 1V8P rail but the rail is turned off. Please do not set dg_configPOWER_1V8P_ACTIVE to 0." + #endif + #endif + + #if defined(dg_configPOWER_1V8P_ACTIVE) && (dg_configPOWER_1V8P_ACTIVE == 0) && \ + (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P || dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8F) + #error \ + "Flash is connected to the 1V8P rail but the rail is turned off. Please do not set dg_configPOWER_1V8P_ACTIVE to 0." + #endif + + #if (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P || dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8F) \ + && defined(dg_configFLASH_POWER_OFF) && defined(dg_configPOWER_1V8P_SLEEP) && (dg_configPOWER_1V8P_SLEEP == 0) + #error \ + "Both dg_configFLASH_POWER_OFF and dg_configPOWER_1V8P_SLEEP are defined! Please use dg_configPOWER_1V8P_SLEEP only!" + #endif + + #if (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) && defined(dg_configFLASH_POWER_OFF) && \ + defined(dg_configPOWER_1V8_SLEEP) + #error \ + "Both dg_configFLASH_POWER_OFF and dg_configPOWER_1V8_SLEEP are defined. Please use dg_configPOWER_1V8_SLEEP only!" + #endif + +/** + * \brief When set to 1, the 1V8P is powered during sleep. + * When set to 2 the rail configuration will be defined by the application + */ + #ifndef dg_configPOWER_1V8P_SLEEP + #define dg_configPOWER_1V8P_SLEEP (2) + #else + #if dg_configPOWER_1V8P_SLEEP == 0 + #error \ + "GPADC digital logic is connected to the 1V8P rail but the rail is turned off. Please do not set dg_configPOWER_1V8P_SLEEP to 0." + #endif + #endif + +/** + * \brief When set to 1, the Flash is powered off during sleep. + */ + #ifndef dg_configFLASH_POWER_OFF + +// dg_configFLASH_POWER_OFF will only be allowed to be defined to 1 if dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P or FLASH_CONNECTED_TO_1V8F +// and dg_configPOWER_1V8P_SLEEP == 1 + #if (((dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) && defined(dg_configPOWER_1V8_SLEEP) && \ + (dg_configPOWER_1V8_SLEEP == 0)) || \ + ((dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P || dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8F) \ + && defined(dg_configPOWER_1V8P_SLEEP) && (dg_configPOWER_1V8P_SLEEP == 0))) + #define dg_configFLASH_POWER_OFF (1) + #else + #define dg_configFLASH_POWER_OFF (0) + #endif + #endif /* dg_configFLASH_POWER_OFF */ + +/** + * \brief Enable the Auto-detection mode for QSPIC2 device + * + * \warning THIS WILL GREATLY INCREASE THE CODE SIZE AND RETRAM USAGE!!! MAKE SURE YOUR PROJECT + * CAN SUPPORT THIS. + */ + #ifndef dg_configQSPIC2_DEV_AUTODETECT + #define dg_configQSPIC2_DEV_AUTODETECT (0) + #endif + + #if dg_configQSPIC2_DEV_AUTODETECT == 0 + +/** + * \brief The QSPI 2 Driver header file to include + * + * The header file must be in the include path of the compiler + */ + #ifndef dg_configQSPIC2_DEV_HEADER_FILE + #define dg_configQSPIC2_DEV_HEADER_FILE "psram_aps6404jsq.h" + #endif + +/** + * \brief The QSPI 2 Driver configuration structure + * + * The configuration structure must be in the include path of the compiler + */ + #ifndef dg_configQSPIC2_DEV_CONFIG + #define dg_configQSPIC2_DEV_CONFIG psram_aps6404jsq_config + #endif + + #endif /* dg_configQSPIC2_DEV_AUTODETECT == 0 */ + + #if dg_configFLASH_AUTODETECT == 0 + +/** + * \brief The Flash Driver header file to include + * + * The header file must be in the include path of the compiler + */ + #ifndef dg_configFLASH_HEADER_FILE + #define dg_configFLASH_HEADER_FILE "qspi_mx25u3235.h" + #endif /* dg_configFLASH_HEADER_FILE */ + +/** + * \brief The Flash Driver configuration structure + * + * The configuration structure must be in the include path of the compiler + */ + #ifndef dg_configFLASH_CONFIG + #define dg_configFLASH_CONFIG flash_mx25u3235_config + #endif /* dg_configFLASH_CONFIG */ + + #endif /* dg_configFLASH_AUTODETECT == 0 */ + + #if (dg_configUSE_HW_QSPI == 1) + +/** + * \brief The base address for accessing the Flash memory connected to QSPIC2 + * + * The base address is used in qspi_automode. Automode is using a single zero-based address region + * for accessing the QSPI Flash devices connected to both QSPI controllers (QSPIC1 and QSPIC2). + * Two address sub-regions are defined: + * Address region 1: 0..dg_configQSPI2_FLASH_BASE_ADDR-1 + * Address region 2: starting at dg_configQSPI2_FLASH_BASE_ADDR + * When QSPI Flash address is in region 1 then the device connected to QSPIC1 is accessed. + * When QSPI Flash address is in region 2 then the device connected to QSPIC2 is accessed. + * The maximum region size handled by each QSPI controller in automode is 32MBytes. The + * default value of dg_configQSPI2_FLASH_BASE_ADDR is 0x2000000 allowing 32MBytes region + * for each controller. The default value can be overridden and set to the size of the QSPI + * Flash device connected to QSPIC1 to allow a continuous address space for both devices. + */ + #ifndef dg_configQSPI2_FLASH_BASE_ADDR + #define dg_configQSPI2_FLASH_BASE_ADDR 0x2000000 + #endif + + #endif /* dg_configUSE_HW_QSPI */ + + #if (dg_configFLASH_AUTODETECT == 0) || (dg_configQSPIC2_DEV_AUTODETECT == 0) + +/** + * \brief Flash device configuration verification. + * + * When set to 1, the Flash device id configuration is checked against the JEDEC ID read + * from the controller. + * + * Applicable only when flash auto detection is not enabled. + */ + #ifndef dg_configFLASH_CONFIG_VERIFY + #define dg_configFLASH_CONFIG_VERIFY (0) + #endif + #endif /* (dg_configFLASH_AUTODETECT == 0) || (dg_configQSPIC2_DEV_AUTODETECT == 0) */ + +/** + * \} + */ + +/* ----------------------------------- Charger settings ----------------------------------------- */ + +/** + * \addtogroup CHARGER_SETTINGS Charger configuration settings + * + * \{ + */ + +/** + * \brief When set to 1, State of Charge function is enabled. + */ + #ifndef dg_configUSE_SOC + #define dg_configUSE_SOC (0) + #endif + +/** + * \} + */ + +/* ----------------------------------- UART settings -------------------------------------------- */ + +/** + * \addtogroup UART_SETTINGS + * + * \{ + */ + +/** + * \brief UART3's software FIFO size + */ + #ifndef dg_configUART3_SOFTWARE_FIFO_SIZE + #define dg_configUART3_SOFTWARE_FIFO_SIZE (0) + #endif + +/** + * \brief UART3's Circular DMA buffer size for RX + */ + #ifndef dg_configUART3_RX_CIRCULAR_DMA_BUF_SIZE + #define dg_configUART3_RX_CIRCULAR_DMA_BUF_SIZE (0) + #endif + +/** + * \} + */ + +/* + */ + +/*------------------------------------ BOARDS DEFINITIONS ----------------------------------------*/ + +/** + * \brief Set the board that is used. + */ + #ifndef dg_configUSE_BOARD + #include "boards/brd_io_config_ra6w1.h" + #define dg_configUSE_BOARD + #endif + +#endif /* DA1640X */ + +#endif /* BSP_DEFAULTS_RA6W1_H_ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_definitions.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_definitions.h new file mode 100644 index 000000000000..254e55d2260e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_definitions.h @@ -0,0 +1,175 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup BSP_CONFIG_DEFINITIONS Configuration Definitions + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * + *\{ + */ + +/** + **************************************************************************************** + * + * @file bsp_definitions.h + * + * @brief Board Support Package. System Configuration file definitions. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEFINITIONS_H_ +#define BSP_DEFINITIONS_H_ + +/* ------------------------------------ DEVICE DEFINITIONS -------------------------------------- */ + +#include "bsp_device_definitions.h" + +/* ------------------------------------ Generic definitions ------------------------------------- */ + +#define PRO_DK_DA1469x_BRD 1 +#define PRO_DK_DA1468x_BRD 2 +#define FPGA_DA1469x_BRD 3 +#define FPGA_DA1468x_BRD 4 + +#define LP_CLK_IS_ANALOG 0 +#define LP_CLK_IS_DIGITAL 1 + +#define MODE_IS_MIRRORED 0 +#define MODE_IS_CACHED 1 +#define MODE_IS_RAM MODE_IS_MIRRORED + +#define NON_VOLATILE_IS_OTP 0 // Code is in OTP +#define NON_VOLATILE_IS_FLASH 1 // Code is in QSPI Flash +#define NON_VOLATILE_IS_NONE 2 // Debug mode! Code is in RAM! + +#define EXT_CRYSTAL_IS_16M 0 +#define EXT_CRYSTAL_IS_32M 1 + +#define DEVELOPMENT_MODE 0 // Code is built for debugging +#define PRODUCTION_MODE 1 // Code is built for production + +#define FLASH_IS_NOT_CONNECTED 0 +#define FLASH_CONNECTED_TO_1V8 1 +#define FLASH_CONNECTED_TO_1V8P 2 +#define FLASH_CONNECTED_TO_1V8F 3 + +#define BATTERY_TYPE_2xNIMH 0 +#define BATTERY_TYPE_3xNIMH 1 +#define BATTERY_TYPE_LICOO2 2 // 2.5V discharge voltage, 4.20V charge voltage +#define BATTERY_TYPE_LIMN2O4 3 // 2.5V discharge voltage, 4.20V charge voltage +#define BATTERY_TYPE_NMC 4 // 2.5V discharge voltage, 4.20V charge voltage +#define BATTERY_TYPE_LIFEPO4 5 // 2.5V discharge voltage, 3.65V charge voltage +#define BATTERY_TYPE_LINICOAIO2 6 // 3.0V discharge voltage, 4.20V charge voltage +#define BATTERY_TYPE_CUSTOM 7 +#define BATTERY_TYPE_NO_RECHARGE 8 +#define BATTERY_TYPE_NO_BATTERY 9 + +#define BATTERY_TYPE_2xNIMH_ADC_VOLTAGE (2785) +#define BATTERY_TYPE_3xNIMH_ADC_VOLTAGE (4013) +#define BATTERY_TYPE_LICOO2_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_LIMN2O4_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_NMC_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_LIFEPO4_ADC_VOLTAGE (2989) +#define BATTERY_TYPE_LINICOAIO2_ADC_VOLTAGE (3440) + +/* + * Legacy DK motherboards, which are not supported by the SDK. + * The definitions exist just so that we don't break compilation of old projects. + */ +#define BLACK_ORCA_MB_REV_A 0 +#define BLACK_ORCA_MB_REV_B 1 + +/* + * The supported DK motherboards. + */ +#define BLACK_ORCA_MB_REV_D 2 + +#if (DEVICE_FAMILY == DA1468X) + +/* + * The cache associativity options. + */ + #define CACHE_ASSOC_AS_IS (-1) /// leave as set by the ROM booter + #define CACHE_ASSOC_DIRECT_MAP 0 /// direct-mapped + #define CACHE_ASSOC_2_WAY 1 /// 2-way set associative + #define CACHE_ASSOC_4_WAY 2 /// 4-way set associative + +/* + * The cache line size options. + */ + #define CACHE_LINESZ_AS_IS (-1) /// leave as set by the ROM booter + #define CACHE_LINESZ_8_BYTES 0 /// 8 bytes + #define CACHE_LINESZ_16_BYTES 1 /// 16 bytes + #define CACHE_LINESZ_32_BYTES 2 /// 32 bytes +#endif /* DA1468X */ + +/* + * The supported RF Front-End Modules + */ +#define FEM_NOFEM 0 +#define FEM_SKY66112_11 1 + +/* + * The BLE event notification user hook types + */ +#define BLE_EVENT_NOTIF_USER_ISR 0 /// User-defined hooks directly from ISR context +#define BLE_EVENT_NOTIF_USER_TASK 1 /// Notification of the user task, using task notifications. + +/* + * Definitions for the different USB suspend modes. + */ +#define USB_SUSPEND_MODE_NONE 0 /// No action, just stop the PLL clock +#define USB_SUSPEND_MODE_PAUSE 1 /// Pause the system and wake only from VBUS and USB interrupts +#define USB_SUSPEND_MODE_IDLE 2 /// System state changes to idle + +#define COEX_NONE 0 +#define COEX_LEGACY 1 +#define COEX_2WAY 2 +#define COEX_3WAY 3 + +/* + * Definitions DRIVE_STRENGTH for AA + */ +#define DRIVE_STRENGTH_2MA (0) ///< Sets pad drive strength 2 mA +#define DRIVE_STRENGTH_12MA (1) ///< Sets pad drive strength 12 mA +#define DRIVE_STRENGTH_4MA (2) ///< Sets pad drive strength 4 mA +#define DRIVE_STRENGTH_18MA (3) ///< Sets pad drive strength 18 mA + +/* + * Definitions DRIVE_STRENGTH for BA + */ +#define DRIVE_STRENGTH_BA_2MA (0) ///< Sets pad drive strength 2 mA +#define DRIVE_STRENGTH_BA_4MA (1) ///< Sets pad drive strength 4 mA +#define DRIVE_STRENGTH_BA_8MA (2) ///< Sets pad drive strength 8 mA +#define DRIVE_STRENGTH_BA_14MA (3) ///< Sets pad drive strength 14 mA + +#endif /* BSP_DEFINITIONS_H_ */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions.h new file mode 100644 index 000000000000..d4279c2ef539 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions.h @@ -0,0 +1,172 @@ +/** + * \addtogroup BSP_CONFIG_DEFINITIONS + * \{ + * \addtogroup BSP_CFG_DEF_DEVICE_MAP Device-Map Definitions + * + * \brief Device-Map Definitions. Macros for all the devices supported by SDK10. + * + *\{ + */ + +/** + **************************************************************************************** + * + * @file bsp_device_definitions.h + * + * @brief Board Support Package. Device-Map definitions. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEVICE_DEFINITIONS_H_ +#define BSP_DEVICE_DEFINITIONS_H_ + +/* + * Available public macros characterizing each product supported by SDK10. + * The variable dg_configDEVICE *MUST* take one of the following values + * i.e. dg_configDEVICE=DA14680_01 + * The variable *MUST* be visible to both the compiler and the assembler. + */ +#define DA14680_01 (DA14680 | _DEVICE_MK_IC_VER(A, E)) +#define DA14681_01 (DA14681 | _DEVICE_MK_IC_VER(A, E)) +#define DA14682_00 (DA14682 | _DEVICE_MK_IC_VER(B, B)) +#define DA14683_00 (DA14683 | _DEVICE_MK_IC_VER(B, B)) + +#define DA14691_00 (DA14691 | _DEVICE_MK_IC_VER(A, B)) +#define DA14693_00 (DA14693 | _DEVICE_MK_IC_VER(A, B)) +#define DA14695_00 (DA14695 | _DEVICE_MK_IC_VER(A, B)) +#define DA14697_00 (DA14697 | _DEVICE_MK_IC_VER(A, B)) +#define DA14699_00 (DA14699 | _DEVICE_MK_IC_VER(A, B)) + +#define DA14870_00 (DA14870 | _DEVICE_MK_IC_VER(A, A)) +#define DA14871_00 (DA14871 | _DEVICE_MK_IC_VER(A, A)) +#define DA14872_00 (DA14872 | _DEVICE_MK_IC_VER(A, A)) +#define DA14873_00 (DA14873 | _DEVICE_MK_IC_VER(A, A)) + +#define DA16400_00 (DA16400 | _DEVICE_MK_IC_VER(A, A)) +#define DA16400_10 (DA16400 | _DEVICE_MK_IC_VER(B, A)) + +#define D3095_10 (D3095 | _DEVICE_MK_IC_VER(B, A)) + +#ifndef dg_configDEVICE + #define dg_configDEVICE DA16400_00 +#endif + +#include "bsp_device_definitions_internal.h" + +/* + * Backward compatibility macros. + * Useful for applications developed with older SDK versions. + * DEVICE_DA146XX can be assigned the desired device. + */ + +/* DA14680 family substitution (with the exception of uartboot loader) */ +#define DEVICE_DA14680 DA14683_00 + +/* DA14690 family substitution */ +#define DEVICE_DA1469x DA14699_00 + +#if 0 + +/* + * Test Section. + * Helpful when changing the macro functionality. + */ + #if (DEVICE_FPGA) + #pragma message "DEVICE_FPGA true" + #elif !(DEVICE_FPGA) && !DEVICE_FPGA + #pragma message "DEVICE_FPGA false" + #endif + + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) && !(DEVICE_FAMILY != DA1469X) + #pragma message "Family DA1469X" + + #if !(DEVICE_FPGA) + #if (DEVICE_VARIANT == DA14699) && !(DEVICE_VARIANT != DA14699) + #pragma message "Variant DA14699" + #elif (DEVICE_VARIANT == DA14697) && !(DEVICE_VARIANT != DA14697) + #pragma message "Variant DA14697" + #elif (DEVICE_VARIANT == DA14695) && !(DEVICE_VARIANT != DA14695) + #pragma message "Variant DA14695" + #elif (DEVICE_VARIANT == DA14693) && !(DEVICE_VARIANT != DA14693) + #pragma message "Variant DA14693" + #elif (DEVICE_VARIANT == DA14691) && !(DEVICE_VARIANT != DA14691) + #pragma message "Variant DA14691" + #else + #error "690 VARIANT ERROR!" + #endif + #endif /* !FPGA */ + + #elif (DEVICE_FAMILY == DA1468X) && !(DEVICE_FAMILY != DA1468X) + #pragma message "Family DA1468X" + + #if !(DEVICE_FPGA) + #if (DEVICE_VARIANT == DA14680) && !(DEVICE_VARIANT != DA14680) + #pragma message "Variant DA14680" + #elif (DEVICE_VARIANT == DA14681) && !(DEVICE_VARIANT != DA14681) + #pragma message "Variant DA14681" + #elif (DEVICE_VARIANT == DA14682) && !(DEVICE_VARIANT != DA14682) + #pragma message "Variant DA14682" + #elif (DEVICE_VARIANT == DA14683) && !(DEVICE_VARIANT != DA14683) + #pragma message "Variant DA14683" + #else + #error "680 VARIANT ERROR!" + #endif + #endif /* !FPGA */ + + #else + #error "FAMILY ERROR!" + #endif + + #if !(DEVICE_FPGA) + #if (DEVICE_REVISION == DEVICE_REV_A) && !(DEVICE_REVISION != DEVICE_REV_A) + #pragma message "Revision A" + #elif (DEVICE_REVISION == DEVICE_REV_B) && !(DEVICE_REVISION != DEVICE_REV_B) + #pragma message "Revision B" + #else + #error "REVISION" + #endif + #endif + + #if !(DEVICE_FPGA) + #if (DEVICE_VERSION == DEVICE_VER_AE) && !(DEVICE_VERSION != DEVICE_VER_AE) + #pragma message "Revision A Step E" + #elif (DEVICE_VERSION == DEVICE_VER_AB) && !(DEVICE_VERSION != DEVICE_VER_AB) + #pragma message "Revision A Step B" + #elif (DEVICE_VERSION == DEVICE_VER_BB) && !(DEVICE_VERSION != DEVICE_VER_BB) + #pragma message "Revision B Step B" + #else + #error "VERSION" + #endif + #endif + +#endif /* Test section */ + +#endif /* BSP_DEVICE_DEFINITIONS_H_ */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions_internal.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions_internal.h new file mode 100644 index 000000000000..3fce8716bb58 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_device_definitions_internal.h @@ -0,0 +1,334 @@ +/** + **************************************************************************************** + * + * @file ra6w1/config/bsp_device_definitions_internal.h + * + * @brief Board Support Package. Device-Map definitions. + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_DEVICE_DEFINITIONS_INTERNAL_H_ +#define BSP_DEVICE_DEFINITIONS_INTERNAL_H_ + +/* + * 31 23 22 13 12 11 8 7 0 + * +--------------+-------------------+------------+---------------+---------------+ + * | Chip Family | Chip Variant | 0: silicon | chip revision | chip stepping | + * | | | | |r|r|r|r| |s|s|s|s|s|s|s|s| + * | |.|.|6|6|x|x|x|x|x|x|x|x|x|x| | |D|C|B|A| |H|G|F|E|D|C|B|A| + * | |.|.|9|8|y|y|y|y|y|y|y|y|y|y|--------------------------------------------| + * | |.|.|z|z|9|8|7|6|5|4|3|2|1|0| 1: FPGA | FPGA version | + * | | | | (numerical 0-4095) | + * +--------------+-------------------+------------+-------------------------------+ + * + * The device is described by a 32-bit value with the following bit encoding: + * + * [11:0] HW version, meaning depends on bit 12: + * For FPGA (bit 12 is 1): + * [11:0] FPGA image version: + * 0-4095: numerical version matching single FPGA image version + * For silicon (bit 12 is 0): + * [ 7:0] Bit field of chip stepping (e.g. xB) + * 0: A, + * 1: B, + * 2: C, + * 3: D, + * 4: E, + * 5: F, + * 6: G, + * 7: H + * [11:8] Bit field of chip revision (e.g. Ax) + * 0: A, + * 1: B, + * 2: C, + * 3: D + * [12] Bit for selecting FPGA/silicon chip version + * 0: silicon, + * 1: FPGA + * [22:13] Bit field that matches one or more chip family variant(s) (up to 10 variants): + * 0x000: invalid for silicon, used for FPGA only + * 0x001: variant xy0 + * 0x002: variant xy1 + * 0x004: variant xy2 + * 0x008: variant xy3 + * 0x010: variant xy4 + * 0x020: variant xy5 + * 0x040: variant xy6 + * 0x080: variant xy7 + * 0x100: variant xy9 + * + * + * [31:23] Bit field that matches one or more chip family/families (up to 9 families): + * 0x0001: 68z + * 0x0002: 69z + * + * Example: + * DA14683_00 (_DEVICE_FAMILY_680 | _DEVICE_VARIANT_3 | _DEVICE_IC_REV_B | _DEVICE_IC_STEP_B) + * + */ + +/* + * Internal definitions + */ + +/* Make bit field value */ +#define _DEVICE_MK_BF_VAL(field, value) (((1 << value) << _DEVICE_ ## field ## _POS) & _DEVICE_ ## field ## _MASK) + +/* Make numerical value */ +#define _DEVICE_MK_NUM_VAL(field, value) (((value) << _DEVICE_ ## field ## _POS) & _DEVICE_ ## field ## _MASK) + +/* Device family definitions */ +#define _DEVICE_FAMILY_MASK 0xFF800000 +#define _DEVICE_FAMILY_POS 23 +#define _DEVICE_FAMILY_680 0 +#define _DEVICE_FAMILY_690 1 + +/* XXX 2 is reserved for 590 */ +#define _DEVICE_FAMILY_870 3 + +/* DA16400 */ +#define _DEVICE_FAMILY_400 4 +#define _DEVICE_FAMILY_6100 4 +#define _DEVICE_MK_FAMILY(x) _DEVICE_MK_BF_VAL(FAMILY, _DEVICE_FAMILY_ ## x) + +/* Device variants definitions */ +#define _DEVICE_VARIANT_MASK 0x007FE000 +#define _DEVICE_CHIP_ID_MASK 0x007FE000 +#define _DEVICE_VARIANT_POS 13 +#define _DEVICE_VARIANT_XX0 0 +#define _DEVICE_CHIP_ID_6100 0 +#define _DEVICE_VARIANT_XX1 1 +#define _DEVICE_VARIANT_XX2 2 +#define _DEVICE_VARIANT_XX3 3 +#define _DEVICE_VARIANT_XX4 4 +#define _DEVICE_VARIANT_XX5 5 +#define _DEVICE_VARIANT_XX6 6 +#define _DEVICE_VARIANT_XX7 7 +#define _DEVICE_VARIANT_XX8 8 +#define _DEVICE_VARIANT_XX9 9 +#define _DEVICE_MK_VARIANT(x) _DEVICE_MK_BF_VAL(VARIANT, _DEVICE_VARIANT_XX ## x) +#define _DEVICE_MK_VARIANT_NUMERICAL(n) _DEVICE_MK_BF_VAL(VARIANT, _DEVICE_VARIANT_XX0 + (n)) +#define _DEVICE_MK_CHIP_ID(x) _DEVICE_MK_BF_VAL(VARIANT, _DEVICE_CHIP_ID_ ## x) + +/* FPGA definitions */ +#define _DEVICE_FPGA_MASK 0x00001000 +#define _DEVICE_FPGA_POS 12 + +#define _DEVICE_FPGA_VER_MASK 0x00000FFF +#define _DEVICE_FPGA_VER_POS 0 +#define _DEVICE_MK_FPGA_VER(n) _DEVICE_MK_BF_VAL(FPGA_VER, (n)) + +/* Device stepping major subrevisions */ +#define _DEVICE_IC_REV_MASK 0x00000F00 +#define _DEVICE_IC_REV_POS 8 + +#define _DEVICE_IC_REV_A 0 +#define _DEVICE_IC_REV_B 1 +#define _DEVICE_IC_REV_C 2 +#define _DEVICE_IC_REV_D 3 +#define _DEVICE_MK_IC_REV(x) _DEVICE_MK_BF_VAL(IC_REV, _DEVICE_IC_REV_ ## x) +#define _DEVICE_MK_REV_NUMERICAL(n) _DEVICE_MK_BF_VAL(IC_REV, n) + +/* Device stepping minor subrevisions */ +#define _DEVICE_IC_STEP_MASK 0x000000FF +#define _DEVICE_IC_STEP_POS 0 +#define _DEVICE_IC_STEP_A 0 +#define _DEVICE_IC_STEP_B 1 +#define _DEVICE_IC_STEP_C 2 +#define _DEVICE_IC_STEP_D 3 +#define _DEVICE_IC_STEP_E 4 +#define _DEVICE_IC_STEP_F 5 +#define _DEVICE_IC_STEP_G 6 +#define _DEVICE_IC_STEP_H 7 +#define _DEVICE_MK_IC_STEP(y) _DEVICE_MK_BF_VAL(IC_STEP, _DEVICE_IC_STEP_ ## y) +#define _DEVICE_MK_IC_VER(x, y) (_DEVICE_MK_IC_REV(x) | _DEVICE_MK_IC_STEP(y)) +#define _DEVICE_MK_STEP_NUMERICAL(n) _DEVICE_MK_BF_VAL(IC_STEP, n) +#define _DEVICE_MASK (_DEVICE_FAMILY_MASK | _DEVICE_VARIANT_MASK | _DEVICE_FPGA_MASK) + +/* + * 680 device family. + */ + +/* Variants */ +#define DA14680 (_DEVICE_MK_FAMILY(680) | _DEVICE_MK_VARIANT(0)) +#define DA14681 (_DEVICE_MK_FAMILY(680) | _DEVICE_MK_VARIANT(1)) +#define DA14682 (_DEVICE_MK_FAMILY(680) | _DEVICE_MK_VARIANT(2)) +#define DA14683 (_DEVICE_MK_FAMILY(680) | _DEVICE_MK_VARIANT(3)) + +/* FPGA Device */ +#define DA1468X_FPGA (_DEVICE_MK_FAMILY(680) | _DEVICE_FPGA_MASK) + +/* Family Wildcard */ +#define DA1468X (_DEVICE_MK_FAMILY(680)) + +/* + * 690 device family. + */ + +/* Variants */ +#define DA14691 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(1)) +#define DA14693 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(3)) +#define DA14695 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(5)) +#define DA14697 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(7)) +#define DA14699 (_DEVICE_MK_FAMILY(690) | _DEVICE_MK_VARIANT(9)) + +/* FPGA Device */ +#define D2522 (_DEVICE_MK_FAMILY(690) | _DEVICE_FPGA_MASK) + +/* Family Wildcard */ +#define DA1469X (_DEVICE_MK_FAMILY(690)) + +/* + * 870 device family. + */ + +/* Variants */ +#define DA14870 (_DEVICE_MK_FAMILY(870) | _DEVICE_MK_VARIANT(0)) +#define DA14871 (_DEVICE_MK_FAMILY(870) | _DEVICE_MK_VARIANT(1)) +#define DA14872 (_DEVICE_MK_FAMILY(870) | _DEVICE_MK_VARIANT(2)) +#define DA14873 (_DEVICE_MK_FAMILY(870) | _DEVICE_MK_VARIANT(3)) + +/* FPGA Device */ +#define D2924 (_DEVICE_MK_FAMILY(870) | _DEVICE_FPGA_MASK) + +/* Family Wildcard */ +#define DA1487X (_DEVICE_MK_FAMILY(870)) + +/* + * DA16400 device family. + */ + +/* Variants */ +#define DA16400 (_DEVICE_MK_FAMILY(400) | _DEVICE_MK_VARIANT(0)) +#define RA6W1 (_DEVICE_MK_FAMILY(6100) | _DEVICE_MK_VARIANT(0)) + +/* Device Chip ID */ +#define DEVICE_CHIP_ID_61000 (_DEVICE_MK_CHIP_ID(6100)) + +/* FPGA Device */ +#define D3095 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(0)) +#define D3095KUS (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(0)) +#define D3095KUMAC (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(0)) +#define D3095KUMAC1 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(1)) +#define D3095KUMAC2 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(2)) +#define D3095KUMAC3 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(3)) +#define D3095KUMAC4 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(4)) +#define D3095KUMAC5 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(5)) +#define D3095KUMAC6 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(6)) +#define D3095KUMAC7 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(7)) + +#define D3095KUPER1 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(251)) +#define D3095KUPER2 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(252)) +#define D3095KUPER3 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(253)) +#define D3095K7 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(256)) +#define D3095K7PER1 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(257)) +#define D3095K7PER2 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(258)) +#define D3095K7PER3 (_DEVICE_MK_FAMILY(400) | _DEVICE_FPGA_MASK | _DEVICE_MK_FPGA_VER(259)) + +/* Family Wildcard */ +#define DA1640X (_DEVICE_MK_FAMILY(400)) + +/* + * The supported chip revisions used for runtime checks. + */ +#define DEVICE_IC_REV_A _DEVICE_IC_REV_A +#define DEVICE_IC_REV_B _DEVICE_IC_REV_B + +/* + * The supported chip steppings used for runtime checks. + */ +#define DEVICE_IC_STEP_A _DEVICE_IC_STEP_A +#define DEVICE_IC_STEP_B _DEVICE_IC_STEP_B +#define DEVICE_IC_STEP_C _DEVICE_IC_STEP_C +#define DEVICE_IC_STEP_D _DEVICE_IC_STEP_D +#define DEVICE_IC_STEP_E _DEVICE_IC_STEP_E +#define DEVICE_IC_STEP_F _DEVICE_IC_STEP_F +#define DEVICE_IC_STEP_G _DEVICE_IC_STEP_G +#define DEVICE_IC_STEP_H _DEVICE_IC_STEP_H + +/* + * Generic Revision and Step Macros. + */ +#ifndef DEVICE_REV_A + #define DEVICE_REV_A (_DEVICE_MK_IC_REV(A)) +#endif +#ifndef DEVICE_REV_B + #define DEVICE_REV_B (_DEVICE_MK_IC_REV(B)) +#endif + +#define DEVICE_VER_AA (_DEVICE_MK_IC_VER(A, A)) +#define DEVICE_VER_AB (_DEVICE_MK_IC_VER(A, B)) +#define DEVICE_VER_AE (_DEVICE_MK_IC_VER(A, E)) +#define DEVICE_VER_BA (_DEVICE_MK_IC_VER(B, A)) +#define DEVICE_VER_BB (_DEVICE_MK_IC_VER(B, B)) + +/* + * A generic FPGA check, available for any device family. + */ +#define DEVICE_FPGA ((dg_configDEVICE & _DEVICE_FPGA_MASK) == _DEVICE_FPGA_MASK) + +#define DEVICE_FPGA_VER_KUS (_DEVICE_MK_FPGA_VER(0)) +#define DEVICE_FPGA_VER_KUMAC (_DEVICE_MK_FPGA_VER(0)) +#define DEVICE_FPGA_VER_KUMAC1 (_DEVICE_MK_FPGA_VER(1)) +#define DEVICE_FPGA_VER_KUMAC2 (_DEVICE_MK_FPGA_VER(2)) +#define DEVICE_FPGA_VER_KUMAC3 (_DEVICE_MK_FPGA_VER(3)) +#define DEVICE_FPGA_VER_KUMAC4 (_DEVICE_MK_FPGA_VER(4)) +#define DEVICE_FPGA_VER_KUMAC5 (_DEVICE_MK_FPGA_VER(5)) +#define DEVICE_FPGA_VER_KUMAC6 (_DEVICE_MK_FPGA_VER(6)) +#define DEVICE_FPGA_VER_KUMAC7 (_DEVICE_MK_FPGA_VER(7)) + +#define DEVICE_FPGA_VER_KUPER1 (_DEVICE_MK_FPGA_VER(251)) +#define DEVICE_FPGA_VER_KUPER2 (_DEVICE_MK_FPGA_VER(252)) +#define DEVICE_FPGA_VER_KUPER3 (_DEVICE_MK_FPGA_VER(253)) +#define DEVICE_FPGA_VER_K7 (_DEVICE_MK_FPGA_VER(256)) +#define DEVICE_FPGA_VER_K7PER1 (_DEVICE_MK_FPGA_VER(257)) +#define DEVICE_FPGA_VER_K7PER2 (_DEVICE_MK_FPGA_VER(258)) +#define DEVICE_FPGA_VER_K7PER3 (_DEVICE_MK_FPGA_VER(259)) + +/* + * Macros checking against specific device characteristics. + * Examples: + * #if (DEVICE_FAMILY == DA1468X) + * #if ((DEVICE_VARIANT == DA14695) || (DEVICE_VARIANT == DA14699)) + * #if (DEVICE_REVISION == DEVICE_REV_B) + * #if ((DEVICE_VERSION == DEVICE_VER_AB) || (DEVICE_VERSION == DEVICE_VER_AE)) + */ +#define DEVICE_FAMILY (dg_configDEVICE & _DEVICE_FAMILY_MASK) +#define DEVICE_VARIANT (dg_configDEVICE & (_DEVICE_FAMILY_MASK | _DEVICE_VARIANT_MASK)) +#define DEVICE_REVISION (dg_configDEVICE & _DEVICE_IC_REV_MASK) +#define DEVICE_VERSION (dg_configDEVICE & (_DEVICE_IC_REV_MASK | _DEVICE_IC_STEP_MASK)) + +/* + * Device information attributes masks + */ +#define DEVICE_FAMILY_MASK (_DEVICE_FAMILY_MASK) +#define DEVICE_CHIP_ID_MASK (_DEVICE_CHIP_ID_MASK) +#define DEVICE_VARIANT_MASK (_DEVICE_IC_VARIANT_MASK) +#define DEVICE_REVISION_MASK (_DEVICE_IC_REV_MASK) +#define DEVICE_SWC_MASK (_DEVICE_IC_SWC_MASK) +#define DEVICE_STEP_MASK (_DEVICE_IC_STEP_MASK) + +#endif /* BSP_DEVICE_DEFINITIONS_INTERNAL_H_ */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults.h new file mode 100644 index 000000000000..ad4cfc5ab282 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults.h @@ -0,0 +1,80 @@ +/** + * \addtogroup PLA_BSP_CONFIG + * \{ + * \addtogroup BSP_MEMORY_DEFAULTS Memory Default Configuration Values + * + * \brief BSP memory default configuration values + * \{ + */ + +/** + **************************************************************************************** + * + * @file bsp_memory_defaults.h + * + * @brief Board Support Package. Memory Configuration file default values. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_MEMORY_DEFAULTS_H_ +#define BSP_MEMORY_DEFAULTS_H_ + +#define PARTITION2(...) +#include "partition_table.h" +#undef PARTITION2 + +/* ---------------------------------------------------------------------------------------------- */ + +/*************************************************************************************************\ + * Default configuration for retention RAM + */ +#if !defined(RELEASE_BUILD) && (dg_configOPTIMAL_RETRAM == 1) + +/* WARNING: retRAM optimizations are disabled in DEBUG builds! */ + #undef dg_configOPTIMAL_RETRAM + #define dg_configOPTIMAL_RETRAM (0) +#elif (dg_configEXEC_MODE != MODE_IS_CACHED) + +/* WARNING: retRAM optimizations are not applicable in MIRRORED mode! */ + #undef dg_configOPTIMAL_RETRAM + #define dg_configOPTIMAL_RETRAM (0) +#endif + +/* -------------------------- INCLUDE MEMORY LAYOUT CONFIGURATION ------------------------------- */ + +#if (DEVICE_FAMILY == DA1640X) + #include "bsp_memory_defaults_ra6w1.h" +#endif + +#endif /* BSP_MEMORY_DEFAULTS_H_ */ + +/** + * \} + * + * \} + */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults_ra6w1.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults_ra6w1.h new file mode 100644 index 000000000000..46c4c2f44af8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_memory_defaults_ra6w1.h @@ -0,0 +1,136 @@ +/** + * \addtogroup BSP_MEMORY_DEFAULTS + * \{ + * + * \addtogroup MEMORY_LAYOUT_SETTINGS Memory Layout Configuration Settings + * + * \brief Memory Layout Configuration Settings + * \{ + * + */ + +/** + **************************************************************************************** + * + * @file bsp_memory_defaults_ra6w1.h + * + * @brief Board Support Package. Device-specific system configuration default values. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __BSP_MEMORY_DEFAULTS_RA6W1_H__ +#define __BSP_MEMORY_DEFAULTS_RA6W1_H__ + +#if (DEVICE_FAMILY == DA1640X) + +// +// RTM Allocation v6 +// + +/// Booter Configuration: Base 0x08600000, 256 Bytes + #define dg_configBOOTER_RTM_ADDR (0x28600000) // == 0x08600000 + #define dg_configBOOTER_RTM_SIZE (0x100) + +/// Scheduler Configuration: Base 0x08600100, 512 Bytes + #define dg_configSCHEDULER_RTM_ADDR ((dg_configBOOTER_RTM_ADDR) + (dg_configBOOTER_RTM_SIZE)) + #define dg_configSCHEDULER_RTM_SIZE (0x200) + +/// MAC DPM Configuration: Base 0x08600300, 768 Bytes + #define dg_configMAC_RTM_ADDR ((dg_configSCHEDULER_RTM_ADDR) + (dg_configSCHEDULER_RTM_SIZE)) + #define dg_configMAC_RTM_SIZE (0x300) + +/// APP SUPP DPM Configuration: Base 0x08600600, 1968 Bytes + #define dg_configAPPSUPP_RTM_ADDR ((dg_configMAC_RTM_ADDR) + (dg_configMAC_RTM_SIZE)) + #define dg_configAPPSUPP_RTM_SIZE (0x7b0) + +/// PHY PARAM: Base 0x08600DB0, 100 Bytes + #define dg_configPHYPARAM_RTM_ADDR ((dg_configAPPSUPP_RTM_ADDR) + (dg_configAPPSUPP_RTM_SIZE)) + #define dg_configPHYPARAM_RTM_SIZE (0x64) + +/// FADC CAL: Base 0x08600E14, 80 Bytes + #define dg_configFADCAL_RTM_ADDR ((dg_configPHYPARAM_RTM_ADDR) + (dg_configPHYPARAM_RTM_SIZE)) + #define dg_configFADCAL_RTM_SIZE (0x50) + +/// TCS: Base 0x08600E64, 256 Bytes + #define dg_configTCS_RTM_ADDR ((dg_configFADCAL_RTM_ADDR) + (dg_configFADCAL_RTM_SIZE)) + #define dg_configTCS_RTM_SIZE (0x100) + +/// DPMST: Base 0x08600F64, 6432 Bytes + #define dg_configDPMST_RTM_ADDR ((dg_configTCS_RTM_ADDR) + (dg_configTCS_RTM_SIZE)) + #define dg_configDPMST_RTM_SIZE (0x1920) + +/// TCPKAT: Base 0x08602884, 48 Bytes + #define dg_configTCPKAT_RTM_ADDR ((dg_configDPMST_RTM_ADDR) + (dg_configDPMST_RTM_SIZE)) + #define dg_configTCPKAT_RTM_SIZE (0x30) + +/// PAD: Base 0x086028B4, 316 Bytes + #define dg_configPAD_RTM_ADDR ((dg_configTCPKAT_RTM_ADDR) + (dg_configTCPKAT_RTM_SIZE)) + #define dg_configPAD_RTM_SIZE (0x13C) + +/// PTIM Image Header: Base 0x086029F0, 16 Bytes + #define dg_configPTIMG_HDR_ADDR ((dg_configPAD_RTM_ADDR) + (dg_configPAD_RTM_SIZE)) + #define dg_configPTIMG_HDR_SIZE (0x10) + +/// The address to load the PTIM image into RTM: Base 0x08602A00, 41984 Bytes + #define dg_configPTIMG_ADDR ((dg_configPTIMG_HDR_ADDR) + (dg_configPTIMG_HDR_SIZE)) + #define dg_configPTIMG_SIZE (0xA400) + +/// TCP: Base 0x0860CE00, 2256 Bytes (Max TCP Session count : 8) + #define dg_configTCP_RTM_ADDR ((dg_configPTIMG_ADDR) + (dg_configPTIMG_SIZE)) + #define dg_configTCP_RTM_SIZE (0x8d0) + +/// APP SUPP DPM EXT Configuration: Base 0x08600D6D0, 384 Bytes + #define dg_configAPPSUPP_EXT_RTM_ADDR ((dg_configTCP_RTM_ADDR) + (dg_configTCP_RTM_SIZE)) + #define dg_configAPPSUPP_EXT_RTM_SIZE (0x180) + +/// User RTM Header: Base 0x0860D850, 64 Bytes + #define dg_configUSERHDR_RTM_ADDR ((dg_configAPPSUPP_EXT_RTM_ADDR) + (dg_configAPPSUPP_EXT_RTM_SIZE)) + #define dg_configUSERHDR_RTM_SIZE (0x40) + +/// User RTM: Base 0x0860D890, 10096 Bytes + #define dg_configUSER_RTM_ADDR ((dg_configUSERHDR_RTM_ADDR) + (dg_configUSERHDR_RTM_SIZE)) + #define dg_configUSER_RTM_SIZE (0x2770) + +/// RTM End: Base 0x08610000, 0 Bytes + #define dg_configEND_RTM_ADDR ((dg_configUSER_RTM_ADDR) + (dg_configUSER_RTM_SIZE)) + #define dg_configEND_RTM_SIZE (0x0) + + #if ((dg_configEND_RTM_ADDR) > (0x28610000)) + #error RTM Memory Overflow!!! + #endif + + #if ((dg_configPTIMG_ADDR) % 512) + #error PTIM address not aligned!!! + #endif + +#endif /* DA1640X */ + +#endif /* __BSP_MEMORY_DEFAULTS_RA6W1_H__ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_sflash_map_ra6w1.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_sflash_map_ra6w1.h new file mode 100644 index 000000000000..860d975ed03d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_sflash_map_ra6w1.h @@ -0,0 +1,629 @@ +/** + **************************************************************************************** + * + * @file bsp_sflash_map_ra6w1.h + * + * @brief RA6W1_SFLASH Map + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#if !defined(__BSP_SFLASH_MAP_RA6W1_H__) +#define __BSP_SFLASH_MAP_RA6W1_H__ + +/* + * USER configurable fields ........................................................... + * SFLASH type for RA6W1 SDK + */ +#define RENESAS_AT25SL_8MB_OTA // Default Renesas AT25SL 8MB w/ OTA +#undef RENESAS_AT25SL_8MB // Default Renesas AT25SL 8MB w/o OTA +#undef NORMAL_4MB_OTA // Normal 4MB SFLASH w/ OTA +#undef NORMAL_4MB // Normal 4MB SFLASH w/o OTA + +// +// USER configurable fields ........................................................... +// Need to config by USER +#define CERT_WPA_ENT_USED (1) // Used = 1, Unused = 0 +#define CERT_OTA_USED (1) // Used = 1, Unused = 0 +#define CERT_HTTPS_CLI_USED (1) // Used = 1, Unused = 0 +#define CERT_HTTPS_SVR_USED (1) // Used = 1, Unused = 0 +#define CERT_MQTTS_CLI_USED (1) // Used = 1, Unused = 0 +#define CERT_ATCMD_USED (1) // Used = 1, Unused = 0 +#define CERT_AWS_USED (1) // Used = 1, Unused = 0 +#define CERT_MATTER_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC1_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC2_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC3_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC4_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC5_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC6_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC7_USED (1) // Used = 1, Unused = 0 +#define CERT_MISC8_USED (1) // Used = 1, Unused = 0 +// .................................................................................... + +////////////////////////// SFLASH_MAP ////////////////////////////////// + +#if defined(RENESAS_AT25SL_8MB_OTA) // ==================== + +/* + * !!! Notice !!! + * + * Renese AT25SL Series 8MB SFLASH requires mutual exclusion operation + * in 1MB units for Write/Erase + Read operation. + * + */ + +/* + * < RA6W1 Renesas AT25SL 8MB SFALSH Map - w/ OTA > + * + * ............................................................................... + * 0x0000_0000 Product Header 4 KB + * 0x0000_1000 Product Header - Backup 4 KB + * + * 0x0000_2000 RTOS #0 2,560 KB + * 0x0028_2000 Reserved 508 KB + * .. 3MB ........................................................................ + * 0x0030_0000 NVRAM 40 KB + * 0x0030_A000 NVRAM - Backup (Multiplier 8) 280 KB + * + * 0x0035_0000 TLS_Cert_Base 704 KB + * 0x0035_0000 TLS Certificate WPA_Enterprise 16 KB or Unused + * 0x0035_4000 TLS Certificate OTA_Update 16 KB or Unused + * 0x0035_8000 TLS Certificate HTTPs Client 16 KB or Unused + * 0x0035_C000 TLS Certificate HTTPs Server 16 KB or Unused + * 0x0036_0000 TLS Certificate MQTTs Client 16 KB or Unused + * 0x0036_4000 TLS Certificate AT-CMD #0 ~ #15 64 KB ( 4KB * 16 ) or Unused + * 0x0037_4000 TLS Certificate AWS 20 KB or Unused + * 0x0037_9000 TLS Certificate Matter 20 KB or Unused + * 0x0037_E000 TLS Certificate MISC1 20 KB or Unused + * 0x0038_3000 TLS Certificate MISC2 20 KB or Unused + * 0x0038_8000 TLS Certificate MISC3 20 KB or Unused + * 0x0038_D000 TLS Certificate MISC4 20 KB or Unused + * 0x0039_2000 TLS Certificate MISC5 20 KB or Unused + * 0x0039_7000 TLS Certificate MISC6 20 KB or Unused + * 0x0039_C000 TLS Certificate MISC7 20 KB or Unused + * 0x003A_1000 TLS Certificate MISC8 20 KB or Unused + * 0x003F_E000 Secure Asset Product Area 4 KB or Unused + * .. 4MB ........................................................................ + * 0x0040_0000 RTOS #1 2,560 KB + * 0x0068_0000 Reserved 512 KB + * .. 7MB ........................................................................ + * 0x0070_0000 User Area #1 1,020 KB + * 0x007F_F000 Partition Table 4 KB + * .. 8MB ........................................................................ + * + */ + +// Area size + #define SF_PRODUCT_HDR_SIZE 0x00001000 // 4 KB + #define SF_RTOS_SIZE 0x00280000 // 2,048 KB + 64 KB * 8 + + #define SF_NVRAM_SIZE 0x0000A000 // 40 KB + #define SF_NVRAM_AREA_SIZE 0x00050000 // 320 KB + + #define SF_SYS_TLS_CERT_SIZE 0x00004000 // 16 KB + #define SF_SYS_TLS_ADD_CERT_SIZE 0x00005000 // 20 KB + #define SF_ATCMD_TLS_CERT_SIZE 0x00010000 // 64 KB + #define SF_TLS_AREA_SIZE 0x000B0000 // 704 KB + + #define SF_SECURE_ASSET_SIZE 0x00001000 // 4 KB + #define SF_USER_AREA_SIZE_ORI 0x000FF000 // 1,020 KB + + #define SF_PARTITION_TBL_SIZE 0x00001000 // 4 KB + +// Defined SFLASH address + #define SF_BASE_ADDR 0x00000000 + #define SF_NVRAM_BASE_ADDR 0x00300000 + #define SF_ASSET_PROD_BASE_ADDR 0x003FE000 + #define SF_RTOS_1_BASE_ADDR 0x00400000 + #if (TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (defined(BSP_MCU_RRQ61051_208) || defined(BSP_MCU_RRQ61051_408))) + #define SF_USER_AREA_BASE_ADDR 0x00720000 + #else + #define SF_USER_AREA_BASE_ADDR 0x00700000 + #endif /* TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (BSP_MCU_RRQ61051_208 || BSP_MCU_RRQ61051_408) */ + + #define SF_PRODUCT_HDR (SF_BASE_ADDR) + #define SF_PRODUCT_HDR_BACKUP (SF_BASE_ADDR + SF_PRODUCT_HDR_SIZE) + #define SF_RTOS_0 (SF_PRODUCT_HDR_BACKUP + SF_PRODUCT_HDR_SIZE) + + #define SF_NVRAM_AREA (SF_NVRAM_BASE_ADDR) + #define SF_NVRAM_BACKUP_AREA (SF_NVRAM_AREA + SF_NVRAM_SIZE) + + #define SF_TLS_CERT_BASE_ADDR (SF_NVRAM_AREA + SF_NVRAM_AREA_SIZE) + #define SF_TLS_CERT_WPA_ENT (SF_TLS_CERT_BASE_ADDR) + #define SF_TLS_CERT_OTA (SF_TLS_CERT_WPA_ENT + (SF_SYS_TLS_CERT_SIZE * CERT_WPA_ENT_USED)) + #define SF_TLS_CERT_HTTPS_CLI (SF_TLS_CERT_OTA + (SF_SYS_TLS_CERT_SIZE * CERT_OTA_USED)) + #define SF_TLS_CERT_HTTPS_SVR (SF_TLS_CERT_HTTPS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_CLI_USED)) + #define SF_TLS_CERT_MQTTS_CLI (SF_TLS_CERT_HTTPS_SVR + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_SVR_USED)) + #define SF_TLS_CERT_ATCMD (SF_TLS_CERT_MQTTS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_MQTTS_CLI_USED)) + #define SF_TLS_CERT_AWS (SF_TLS_CERT_ATCMD + (SF_ATCMD_TLS_CERT_SIZE * CERT_ATCMD_USED)) + #define SF_TLS_CERT_MATTER (SF_TLS_CERT_AWS + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_AWS_USED)) + #define SF_TLS_CERT_MISC1 (SF_TLS_CERT_MATTER + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MATTER_USED)) + #define SF_TLS_CERT_MISC2 (SF_TLS_CERT_MISC1 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC1_USED)) + #define SF_TLS_CERT_MISC3 (SF_TLS_CERT_MISC2 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC2_USED)) + #define SF_TLS_CERT_MISC4 (SF_TLS_CERT_MISC3 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC3_USED)) + #define SF_TLS_CERT_MISC5 (SF_TLS_CERT_MISC4 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC4_USED)) + #define SF_TLS_CERT_MISC6 (SF_TLS_CERT_MISC5 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC5_USED)) + #define SF_TLS_CERT_MISC7 (SF_TLS_CERT_MISC6 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC6_USED)) + #define SF_TLS_CERT_MISC8 (SF_TLS_CERT_MISC7 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC7_USED)) + + #define SF_SECURE_ASSET_PROD (SF_ASSET_PROD_BASE_ADDR) + + #define SF_RTOS_1 (SF_RTOS_1_BASE_ADDR) + + #define SF_USER_AREA (SF_USER_AREA_BASE_ADDR) + #define SF_USER_AREA_SIZE (SF_USER_AREA_SIZE_ORI) + + #define SF_PARTITION_TBL (SF_USER_AREA + SF_USER_AREA_SIZE) // Fixed - Mandatory + #define SF_END (SF_PARTITION_TBL + SF_PARTITION_TBL_SIZE) + +#elif defined(RENESAS_AT25SL_8MB) // =========================================================== + +/* + * !!! Notice !!! + * + * Renese AT25SL Series 8MB SFLASH requires mutual exclusion operation + * in 1MB units for Write/Erase + Read operation. + * + */ + +/* + * < RA6W1 Renesas AT25SL 8MB SFALSH Map - w/o OTA > + * + * ............................................................................... + * 0x0000_0000 Product Header 4 KB + * 0x0000_1000 Product Header - Backup 4 KB + * + * 0x0000_2000 RTOS #0 2,560 KB + * 0x0028_2000 Reserved 508 KB + * .. 3MB ........................................................................ + * 0x0030_0000 NVRAM 40 KB + * 0x0030_A000 NVRAM - Backup (Multiplier 8) 280 KB + * 0x0035_0000 TLS_Cert_Base 704 KB + * 0x0035_2000 TLS Certificate WPA_Enterprise 16 KB or Unused + * 0x0035_6000 TLS Certificate OTA_Update 16 KB or Unused + * 0x0035_A000 TLS Certificate HTTPs Client 16 KB or Unused + * 0x0035_E000 TLS Certificate HTTPs Server 16 KB or Unused + * 0x0036_2000 TLS Certificate MQTTs Client 16 KB or Unused + * 0x0036_6000 TLS Certificate CoAPs Client 16 KB or Unused + * 0x0036_A000 TLS Certificate CoAPs Server 16 KB or Unused + * 0x0036_E000 TLS Certificate AT-CMD #0 ~ #15 64 KB ( 4KB * 16 ) or Unused + * 0x003F_E000 Secure Asset Product Area 128 B or Unused + * .. 4MB ........................................................................ + * 0x0040_0000 User Area 3,964 KB + * 0x007F_F000 Partition Table 4 KB + * .. 8MB ........................................................................ + * + */ + +// Area size + #define SF_PRODUCT_HDR_SIZE 0x00001000 // 4 KB + #define SF_RTOS_SIZE 0x00280000 // 2,048 KB + 64 KB * 8 + + #define SF_NVRAM_SIZE 0x0000A000 // 40 KB + #define SF_NVRAM_AREA_SIZE 0x00050000 // 320 KB + + #define SF_SYS_TLS_CERT_SIZE 0x00004000 // 16 KB + #define SF_SYS_TLS_ADD_CERT_SIZE 0x00005000 // 20 KB + #define SF_ATCMD_TLS_CERT_SIZE 0x00010000 // 64 KB + #define SF_TLS_AREA_SIZE 0x000B0000 // 704 KB + + #define SF_SECURE_ASSET_SIZE 0x00001000 // 4 KB + #define SF_USER_AREA_SIZE_ORI 0x003FF000 // 4,092 KB + + #define SF_PARTITION_TBL_SIZE 0x00001000 // 4 KB + +// Defined SFLASH address + #define SF_BASE_ADDR 0x00000000 + #define SF_NVRAM_BASE_ADDR 0x00300000 + #define SF_ASSET_PROD_BASE_ADDR 0x003FE000 + #define SF_USER_AREA_BASE_ADDR 0x00400000 + + #define SF_PRODUCT_HDR (SF_BASE_ADDR) + #define SF_PRODUCT_HDR_BACKUP (SF_BASE_ADDR + SF_PRODUCT_HDR_SIZE) + #define SF_RTOS_0 (SF_PRODUCT_HDR_BACKUP + SF_PRODUCT_HDR_SIZE) + + #define SF_TLS_CERT_BASE_ADDR (SF_NVRAM_AREA + SF_NVRAM_AREA_SIZE) + #define SF_TLS_CERT_WPA_ENT (SF_TLS_CERT_BASE_ADDR) + #define SF_TLS_CERT_OTA (SF_TLS_CERT_WPA_ENT + (SF_SYS_TLS_CERT_SIZE * CERT_WPA_ENT_USED)) + #define SF_TLS_CERT_HTTPS_CLI (SF_TLS_CERT_OTA + (SF_SYS_TLS_CERT_SIZE * CERT_OTA_USED)) + #define SF_TLS_CERT_HTTPS_SVR (SF_TLS_CERT_HTTPS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_CLI_USED)) + #define SF_TLS_CERT_MQTTS_CLI (SF_TLS_CERT_HTTPS_SVR + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_SVR_USED)) + #define SF_TLS_CERT_ATCMD (SF_TLS_CERT_MQTTS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_MQTTS_CLI_USED)) + #define SF_TLS_CERT_AWS (SF_TLS_CERT_ATCMD + (SF_ATCMD_TLS_CERT_SIZE * CERT_ATCMD_USED)) + #define SF_TLS_CERT_MATTER (SF_TLS_CERT_AWS + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_AWS_USED)) + #define SF_TLS_CERT_MISC1 (SF_TLS_CERT_MATTER + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MATTER_USED)) + #define SF_TLS_CERT_MISC2 (SF_TLS_CERT_MISC1 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC1_USED)) + #define SF_TLS_CERT_MISC3 (SF_TLS_CERT_MISC2 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC2_USED)) + #define SF_TLS_CERT_MISC4 (SF_TLS_CERT_MISC3 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC3_USED)) + #define SF_TLS_CERT_MISC5 (SF_TLS_CERT_MISC4 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC4_USED)) + #define SF_TLS_CERT_MISC6 (SF_TLS_CERT_MISC5 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC5_USED)) + #define SF_TLS_CERT_MISC7 (SF_TLS_CERT_MISC6 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC6_USED)) + #define SF_TLS_CERT_MISC8 (SF_TLS_CERT_MISC7 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC7_USED) + + #define SF_NVRAM_AREA (SF_NVRAM_BASE_ADDR) + #define SF_NVRAM_BACKUP_AREA (SF_NVRAM_AREA + SF_NVRAM_SIZE) + + #define SF_SECURE_ASSET_PROD (SF_ASSET_PROD_BASE_ADDR) + + #define SF_USER_AREA (SF_USER_AREA_BASE_ADDR) + #define SF_USER_AREA_SIZE (SF_USER_AREA_SIZE_ORI) + + #define SF_PARTITION_TBL (SF_USER_AREA + SF_USER_AREA_SIZE) // Fixed - Mandatory + #define SF_END (SF_PARTITION_TBL + SF_PARTITION_TBL_SIZE) + +#elif defined(NORMAL_4MB_OTA) // =============================================================== + +/* + * < RA6W1 Normal 4MB SFALSH Map - w/ OTA > + * + * ............................................................................... + * 0x0000_0000 Product Header 4 KB + * 0x0000_1000 Product Header - Backup 4 KB + * 0x0000_2000 RTOS #0 1,792 KB + * 0x001C_2000 TLS_Cert_Base 208 KB + * 0x001C_2000 TLS Certificate WPA_Enterprise 16 KB or Unused + * 0x001C_6000 TLS Certificate OTA_Update 16 KB or Unused + * 0x001C_A000 TLS Certificate HTTPs Client 16 KB or Unused + * 0x001C_E000 TLS Certificate HTTPs Server 16 KB or Unused + * 0x001D_2000 TLS Certificate MQTTs Client 16 KB or Unused + * 0x001D_6000 TLS Certificate CoAPs Client 16 KB or Unused + * 0x001D_A000 TLS Certificate CoAPs Server 16 KB or Unused + * 0x001D_E000 TLS Certificate AT-CMD #0 ~ #15 64 KB ( 4KB * 16 ) or Unused + * 0x001F_6000 NVRAM 20 KB + * 0x001F_B000 NVRAM - Backup 20 KB + * ............................................................................... + * 0x0020_0000 RTOS #1 1,792 KB + * ............................................................................... + * 0x003C_0000 User Area 248 KB + * 0x003F_E000 Secure Asset Product Area 4 KB + * 0x003F_F000 Partition Table 4 KB + * ............................................................................... + */ + +// Area size + #define SF_PRODUCT_HDR_SIZE 0x00001000 // 4 KB + #define SF_RTOS_SIZE 0x001C0000 // 1,792 KB + #define SF_SYS_TLS_CERT_SIZE 0x00004000 // 16 KB + #define SF_SYS_TLS_ADD_CERT_SIZE 0x00005000 // 20 KB + #define SF_ATCMD_TLS_CERT_SIZE 0x00010000 // 64 KB + #define SF_TLS_AREA_SIZE 0x00034000 // 208 KB + #define SF_NVRAM_SIZE 0x00005000 // 20 KB + #define SF_SECURE_ASSET_SIZE 0x00001000 // 4 KB + #define SF_USER_AREA_SIZE_ORI 0x0003E000 // 248 KB + #define SF_PARTITION_TBL_SIZE 0x00001000 // 4 KB + +// Defined SFLASH address + #define SF_BASE_ADDR 0x00000000 + #define SF_ASSET_PROD_BASE_ADDR 0x003FE000 + + #define SF_PRODUCT_HDR (SF_BASE_ADDR) + #define SF_PRODUCT_HDR_BACKUP (SF_BASE_ADDR + SF_PRODUCT_HDR_SIZE) + #define SF_RTOS_0 (SF_PRODUCT_HDR_BACKUP + SF_PRODUCT_HDR_SIZE) + + #define SF_TLS_CERT_BASE_ADDR (SF_RTOS_0 + SF_RTOS_SIZE) + #define SF_TLS_CERT_WPA_ENT (SF_TLS_CERT_BASE_ADDR) + #define SF_TLS_CERT_OTA (SF_TLS_CERT_WPA_ENT + (SF_SYS_TLS_CERT_SIZE * CERT_WPA_ENT_USED)) + #define SF_TLS_CERT_HTTPS_CLI (SF_TLS_CERT_OTA + (SF_SYS_TLS_CERT_SIZE * CERT_OTA_USED)) + #define SF_TLS_CERT_HTTPS_SVR (SF_TLS_CERT_HTTPS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_CLI_USED)) + #define SF_TLS_CERT_MQTTS_CLI (SF_TLS_CERT_HTTPS_SVR + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_SVR_USED)) + #define SF_TLS_CERT_ATCMD (SF_TLS_CERT_MQTTS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_MQTTS_CLI_USED)) + #define SF_TLS_CERT_AWS (SF_TLS_CERT_ATCMD + (SF_ATCMD_TLS_CERT_SIZE * CERT_ATCMD_USED)) + #define SF_TLS_CERT_MATTER (SF_TLS_CERT_AWS + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_AWS_USED)) + #define SF_TLS_CERT_MISC1 (SF_TLS_CERT_MATTER + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MATTER_USED)) + #define SF_TLS_CERT_MISC2 (SF_TLS_CERT_MISC1 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC1_USED)) + #define SF_TLS_CERT_MISC3 (SF_TLS_CERT_MISC2 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC2_USED)) + #define SF_TLS_CERT_MISC4 (SF_TLS_CERT_MISC3 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC3_USED)) + #define SF_TLS_CERT_MISC5 (SF_TLS_CERT_MISC4 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC4_USED)) + #define SF_TLS_CERT_MISC6 (SF_TLS_CERT_MISC5 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC5_USED)) + #define SF_TLS_CERT_MISC7 (SF_TLS_CERT_MISC6 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC6_USED)) + #define SF_TLS_CERT_MISC8 (SF_TLS_CERT_MISC7 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC7_USED) + + #define SF_NVRAM_AREA (SF_TLS_CERT_BASE_ADDR + SF_TLS_AREA_SIZE) + #define SF_NVRAM_BACKUP_AREA (SF_NVRAM_AREA + SF_NVRAM_SIZE) + + #define SF_RTOS_1 (SF_NVRAM_BACKUP_AREA + SF_NVRAM_SIZE) + + #define SF_SECURE_ASSET_PROD (SF_ASSET_PROD_BASE_ADDR) + + #define SF_USER_AREA_BASE (SF_RTOS_1 + SF_RTOS_SIZE) + + #define SF_USER_AREA (SF_USER_AREA_BASE) + #define SF_USER_AREA_SIZE (SF_USER_AREA_SIZE_ORI) + + #define SF_PARTITION_TBL (SF_USER_AREA + SF_USER_AREA_SIZE) + #define SF_END (SF_PARTITION_TBL + SF_PARTITION_TBL_SIZE) + +#elif defined(NORMAL_4MB) // ================================================================ + +/* + * < RA6W1 Normal 4MB SFALSH Map - w/o OTA > + * + * ............................................................................... + * 0x0000_0000 Product Header 4 KB + * 0x0000_1000 Product Header - Backup 4 KB + * 0x0000_2000 RTOS #0 1,792 KB + * 0x001C_2000 TLS_Cert_Base 208 KB + * 0x001C_2000 TLS Certificate WPA_Enterprise 16 KB or Unused + * 0x001C_6000 TLS Certificate OTA_Update 16 KB or Unused + * 0x001C_A000 TLS Certificate HTTPs Client 16 KB or Unused + * 0x001C_E000 TLS Certificate HTTPs Server 16 KB or Unused + * 0x001D_2000 TLS Certificate MQTTs Client 16 KB or Unused + * 0x001D_6000 TLS Certificate CoAPs Client 16 KB or Unused + * 0x001D_A000 TLS Certificate CoAPs Server 16 KB or Unused + * 0x001D_E000 TLS Certificate AT-CMD #0 ~ #15 64 KB ( 4KB * 16 ) or Unused + * 0x001F_6000 NVRAM 20 KB + * 0x001F_B000 NVRAM - Backup 20 KB + * ............................................................................... + * 0x0020_0000 User Area 2,040 KB + * 0x003F_E000 Secure Asset Product Area 4 KB + * 0x003F_F000 Partition Table 4 KB + * ............................................................................... + */ + +// Area size + #define SF_PRODUCT_HDR_SIZE 0x00001000 // 4 KB + #define SF_RTOS_SIZE 0x001C0000 // 1,792 KB + #define SF_SYS_TLS_CERT_SIZE 0x00004000 // 16 KB + #define SF_SYS_TLS_ADD_CERT_SIZE 0x00005000 // 20 KB + #define SF_ATCMD_TLS_CERT_SIZE 0x00010000 // 64 KB + #define SF_TLS_AREA_SIZE 0x00034000 // 208 KB + #define SF_NVRAM_SIZE 0x00005000 // 20 KB + #define SF_SECURE_ASSET_SIZE 0x00001000 // 4 KB + #define SF_USER_AREA_SIZE_ORI 0x0023E000 // 2,044 KB + #define SF_PARTITION_TBL_SIZE 0x00001000 // 4 KB + +// Defined SFLASH address + #define SF_BASE_ADDR 0x00000000 + #define SF_ASSET_PROD_BASE_ADDR 0x003FE000 + + #define SF_PRODUCT_HDR (SF_BASE_ADDR) + #define SF_PRODUCT_HDR_BACKUP (SF_BASE_ADDR + SF_PRODUCT_HDR_SIZE) + #define SF_RTOS_0 (SF_PRODUCT_HDR_BACKUP + SF_PRODUCT_HDR_SIZE) + + #define SF_TLS_CERT_BASE_ADDR (SF_RTOS_0 + SF_RTOS_SIZE) + #define SF_TLS_CERT_WPA_ENT (SF_TLS_CERT_BASE_ADDR) + #define SF_TLS_CERT_OTA (SF_TLS_CERT_WPA_ENT + (SF_SYS_TLS_CERT_SIZE * CERT_WPA_ENT_USED)) + #define SF_TLS_CERT_HTTPS_CLI (SF_TLS_CERT_OTA + (SF_SYS_TLS_CERT_SIZE * CERT_OTA_USED)) + #define SF_TLS_CERT_HTTPS_SVR (SF_TLS_CERT_HTTPS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_CLI_USED)) + #define SF_TLS_CERT_MQTTS_CLI (SF_TLS_CERT_HTTPS_SVR + (SF_SYS_TLS_CERT_SIZE * CERT_HTTPS_SVR_USED)) + #define SF_TLS_CERT_ATCMD (SF_TLS_CERT_MQTTS_CLI + (SF_SYS_TLS_CERT_SIZE * CERT_MQTTS_CLI_USED)) + #define SF_TLS_CERT_AWS (SF_TLS_CERT_ATCMD + (SF_ATCMD_TLS_CERT_SIZE * CERT_ATCMD_USED)) + #define SF_TLS_CERT_MATTER (SF_TLS_CERT_AWS + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_AWS_USED)) + #define SF_TLS_CERT_MISC1 (SF_TLS_CERT_MATTER + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MATTER_USED)) + #define SF_TLS_CERT_MISC2 (SF_TLS_CERT_MISC1 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC1_USED)) + #define SF_TLS_CERT_MISC3 (SF_TLS_CERT_MISC2 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC2_USED)) + #define SF_TLS_CERT_MISC4 (SF_TLS_CERT_MISC3 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC3_USED)) + #define SF_TLS_CERT_MISC5 (SF_TLS_CERT_MISC4 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC4_USED)) + #define SF_TLS_CERT_MISC6 (SF_TLS_CERT_MISC5 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC5_USED)) + #define SF_TLS_CERT_MISC7 (SF_TLS_CERT_MISC6 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC6_USED)) + #define SF_TLS_CERT_MISC8 (SF_TLS_CERT_MISC7 + (SF_SYS_TLS_ADD_CERT_SIZE * CERT_MISC7_USED) + + #define SF_NVRAM_AREA (SF_TLS_CERT_BASE_ADDR + SF_TLS_AREA_SIZE) + #define SF_NVRAM_BACKUP_AREA (SF_NVRAM_AREA + SF_NVRAM_SIZE) + + #define SF_SECURE_ASSET_PROD (SF_ASSET_PROD_BASE_ADDR) + + #define SF_USER_AREA_BASE (SF_NVRAM_BACKUP_AREA + SF_NVRAM_SIZE) + + #define SF_USER_AREA (SF_USER_AREA_BASE) + #define SF_USER_AREA_SIZE (SF_USER_AREA_SIZE_ORI) + + #define SF_PARTITION_TBL (SF_USER_AREA + SF_USER_AREA_SIZE) // Fixed - Mandatory + #define SF_END (SF_PARTITION_TBL + SF_PARTITION_TBL_SIZE) + +#else // Undefind SFLASH type ===================================================================== + + #error "Not defined SFLASH type/map !!!" + +#endif // __DEFAULT_4MB_SFLASH__ ================================================================== + +/* TLS Certificate detailed addresses */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate WPA_ENT */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#define SF_TLS_CERT_WPA_ENT_CA_ADDR SF_TLS_CERT_WPA_ENT +#define SF_TLS_CERT_WPA_ENT_CERTIFICATE_ADDR (SF_TLS_CERT_WPA_ENT_CA_ADDR + 0x1000) +#define SF_TLS_CERT_WPA_ENT_PRIVATE_KEY_ADDR (SF_TLS_CERT_WPA_ENT_CA_ADDR + 0x2000) +#define SF_TLS_CERT_WPA_ENT_DH_PARAMETER_ADDR (SF_TLS_CERT_WPA_ENT_CA_ADDR + 0x3000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate OTA */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_OTA_CA_ADDR SF_TLS_CERT_OTA +#define SF_TLS_CERT_OTA_CERTIFICATE_ADDR (SF_TLS_CERT_OTA_CA_ADDR + 0x1000) +#define SF_TLS_CERT_OTA_PRIVATE_KEY_ADDR (SF_TLS_CERT_OTA_CA_ADDR + 0x2000) +#define SF_TLS_CERT_OTA_DH_PARAMETER_ADDR (SF_TLS_CERT_OTA_CA_ADDR + 0x3000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Key HTTPS_CLI */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_HTTPS_CLI_CA_ADDR SF_TLS_CERT_HTTPS_CLI +#define SF_TLS_CERT_HTTPS_CLI_CERTIFICATE_ADDR (SF_TLS_CERT_HTTPS_CLI_CA_ADDR + 0x1000) +#define SF_TLS_CERT_HTTPS_CLI_PRIVATE_KEY_ADDR (SF_TLS_CERT_HTTPS_CLI_CA_ADDR + 0x2000) +#define SF_TLS_CERT_HTTPS_CLI_DH_PARAMETER_ADDR (SF_TLS_CERT_HTTPS_CLI_CA_ADDR + 0x3000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate HTTPS_SVR */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_HTTPS_SVR_CA_ADDR SF_TLS_CERT_HTTPS_SVR +#define SF_TLS_CERT_HTTPS_SVR_CERTIFICATE_ADDR (SF_TLS_CERT_HTTPS_SVR_CA_ADDR + 0x1000) +#define SF_TLS_CERT_HTTPS_SVR_PRIVATE_KEY_ADDR (SF_TLS_CERT_HTTPS_SVR_CA_ADDR + 0x2000) +#define SF_TLS_CERT_HTTPS_SVR_DH_PARAMETER_ADDR (SF_TLS_CERT_HTTPS_SVR_CA_ADDR + 0x3000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Key MQTT_CLI */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MQTT_CLI_CA_ADDR SF_TLS_CERT_MQTTS_CLI +#define SF_TLS_CERT_MQTT_CLI_CERTIFICATE_ADDR (SF_TLS_CERT_MQTT_CLI_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MQTT_CLI_PRIVATE_KEY_ADDR (SF_TLS_CERT_MQTT_CLI_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MQTT_CLI_DH_PARAMETER_ADDR (SF_TLS_CERT_MQTT_CLI_CA_ADDR + 0x3000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate ATCMD */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SFLASH_ATCMD_TLS_CERT_01 (SF_TLS_CERT_ATCMD) +#define SFLASH_ATCMD_TLS_CERT_02 (SFLASH_ATCMD_TLS_CERT_01 + 0x1000) +#define SFLASH_ATCMD_TLS_CERT_03 (SFLASH_ATCMD_TLS_CERT_01 + 0x2000) +#define SFLASH_ATCMD_TLS_CERT_04 (SFLASH_ATCMD_TLS_CERT_01 + 0x3000) +#define SFLASH_ATCMD_TLS_CERT_05 (SFLASH_ATCMD_TLS_CERT_01 + 0x4000) +#define SFLASH_ATCMD_TLS_CERT_06 (SFLASH_ATCMD_TLS_CERT_01 + 0x5000) +#define SFLASH_ATCMD_TLS_CERT_07 (SFLASH_ATCMD_TLS_CERT_01 + 0x6000) +#define SFLASH_ATCMD_TLS_CERT_08 (SFLASH_ATCMD_TLS_CERT_01 + 0x7000) +#define SFLASH_ATCMD_TLS_CERT_09 (SFLASH_ATCMD_TLS_CERT_01 + 0x8000) +#define SFLASH_ATCMD_TLS_CERT_10 (SFLASH_ATCMD_TLS_CERT_01 + 0x9000) +#define SFLASH_ATCMD_TLS_CERT_11 (SFLASH_ATCMD_TLS_CERT_01 + 0xA000) +#define SFLASH_ATCMD_TLS_CERT_12 (SFLASH_ATCMD_TLS_CERT_01 + 0xB000) +#define SFLASH_ATCMD_TLS_CERT_13 (SFLASH_ATCMD_TLS_CERT_01 + 0xC000) +#define SFLASH_ATCMD_TLS_CERT_14 (SFLASH_ATCMD_TLS_CERT_01 + 0xD000) +#define SFLASH_ATCMD_TLS_CERT_15 (SFLASH_ATCMD_TLS_CERT_01 + 0xE000) +#define SFLASH_ATCMD_TLS_CERT_16 (SFLASH_ATCMD_TLS_CERT_01 + 0xF000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate AWS */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_AWS_CA_ADDR SF_TLS_CERT_AWS +#define SF_TLS_CERT_AWS_INITIAL_CERT_ADDR (SF_TLS_CERT_AWS_CA_ADDR + 0x1000) +#define SF_TLS_CERT_AWS_INITIAL_PRIV_KEY_ADDR (SF_TLS_CERT_AWS_CA_ADDR + 0x2000) +#define SF_TLS_CERT_AWS_UNIQUE_CERT_ADDR (SF_TLS_CERT_AWS_CA_ADDR + 0x3000) +#define SF_TLS_CERT_AWS_UNIQUE_PRIV_KEY_ADDR (SF_TLS_CERT_AWS_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate MATTER */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_MATTER_CERT_CD_ADDR SF_TLS_CERT_MATTER +#define SF_MATTER_CERT_DAC_CERTIFICATE_ADDR (SF_MATTER_CERT_CD_ADDR + 0x1000) +#define SF_MATTER_CERT_PAI_CERTIFICATE_ADDR (SF_MATTER_CERT_CD_ADDR + 0x2000) +#define SF_MATTER_CERT_DAC_PRIVATE_KEY_ADDR (SF_MATTER_CERT_CD_ADDR + 0x3000) +#define SF_MATTER_CERT_DAC_PUBLIC_KEY_ADDR (SF_MATTER_CERT_CD_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 1 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC1_CA_ADDR SF_TLS_CERT_MISC1 +#define SF_TLS_CERT_MISC1_CERTIFICATE_ADDR (SF_TLS_CERT_MISC1_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC1_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC1_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC1_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC1_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC1_EXCHANGE_ADDR (SF_TLS_CERT_MISC1_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 2 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC2_CA_ADDR SF_TLS_CERT_MISC2 +#define SF_TLS_CERT_MISC2_CERTIFICATE_ADDR (SF_TLS_CERT_MISC2_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC2_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC2_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC2_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC2_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC2_EXCHANGE_ADDR (SF_TLS_CERT_MISC2_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 3 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC3_CA_ADDR SF_TLS_CERT_MISC3 +#define SF_TLS_CERT_MISC3_CERTIFICATE_ADDR (SF_TLS_CERT_MISC3_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC3_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC3_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC3_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC3_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC3_EXCHANGE_ADDR (SF_TLS_CERT_MISC3_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 4 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC4_CA_ADDR SF_TLS_CERT_MISC4 +#define SF_TLS_CERT_MISC4_CERTIFICATE_ADDR (SF_TLS_CERT_MISC4_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC4_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC4_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC4_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC4_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC4_EXCHANGE_ADDR (SF_TLS_CERT_MISC4_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 5 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC5_CA_ADDR SF_TLS_CERT_MISC5 +#define SF_TLS_CERT_MISC5_CERTIFICATE_ADDR (SF_TLS_CERT_MISC5_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC5_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC5_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC5_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC5_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC5_EXCHANGE_ADDR (SF_TLS_CERT_MISC5_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 6 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC6_CA_ADDR SF_TLS_CERT_MISC6 +#define SF_TLS_CERT_MISC6_CERTIFICATE_ADDR (SF_TLS_CERT_MISC6_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC6_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC6_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC6_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC6_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC6_EXCHANGE_ADDR (SF_TLS_CERT_MISC6_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 7 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC7_CA_ADDR SF_TLS_CERT_MISC7 +#define SF_TLS_CERT_MISC7_CERTIFICATE_ADDR (SF_TLS_CERT_MISC7_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC7_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC7_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC7_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC7_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC7_EXCHANGE_ADDR (SF_TLS_CERT_MISC7_CA_ADDR + 0x4000) + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +/* TLS Certificate Miscellanoeous Application 8 */ + +// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#define SF_TLS_CERT_MISC8_CA_ADDR SF_TLS_CERT_MISC8 +#define SF_TLS_CERT_MISC8_CERTIFICATE_ADDR (SF_TLS_CERT_MISC8_CA_ADDR + 0x1000) +#define SF_TLS_CERT_MISC8_PRIVATE_KEY_ADDR (SF_TLS_CERT_MISC8_CA_ADDR + 0x2000) +#define SF_TLS_CERT_MISC8_DH_PARAMETER_ADDR (SF_TLS_CERT_MISC8_CA_ADDR + 0x3000) +#define SF_TLS_CERT_MISC8_EXCHANGE_ADDR (SF_TLS_CERT_MISC8_CA_ADDR + 0x4000) +#endif /* __BSP_SFLASH_MAP_RA6W1_H__ */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_undisclosed_defs.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_undisclosed_defs.h new file mode 100644 index 000000000000..8c54a8c4125b --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/bsp_undisclosed_defs.h @@ -0,0 +1,65 @@ +/** + **************************************************************************************** + * + * @file bsp_undisclosed_defs.h + * + * @brief + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef BSP_UNDISCLOSED_DEFS_H_ +#define BSP_UNDISCLOSED_DEFS_H_ + +#ifdef BSP_UNDISCLOSED_SANITY_CHECK + +/* Add more defs, if needed, above dg_configUNDISCLOSED_LAST_DEF */ + + #if defined(dg_configUNDISCLOSED_HAPTIC_DIAGN_CONFIG) || \ + defined(dg_configUNDISCLOSED_UNSUPPORTED_FLASH_DEVICES) || \ + defined(dg_configUNDISCLOSED_LAST_DEF) || \ + defined(dg_configAUTOTEST_ENABLE) + + #error "dg_configUNDISCLOSED_XXX cannot be defined!!!" + #endif + +#endif /* BSP_UNDISCLOSED_SANITY_CHECK */ + +/* Enable Haptic diagnostic signals. */ +#ifndef dg_configUNDISCLOSED_HAPTIC_DIAGN_CONFIG + #define dg_configUNDISCLOSED_HAPTIC_DIAGN_CONFIG (0) +#endif + +/* Enable qspi-flash driver modules not supported officially by the SDK. */ +#ifndef dg_configUNDISCLOSED_UNSUPPORTED_FLASH_DEVICES + #define dg_configUNDISCLOSED_UNSUPPORTED_FLASH_DEVICES (0) +#endif + +/* Enable AUTOTEST. */ +#ifndef dg_configAUTOTEST_ENABLE + #define dg_configAUTOTEST_ENABLE (0) +#endif + +#endif /* BSP_UNDISCLOSED_DEFS_H_ */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/custom_config_sdk.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/custom_config_sdk.h new file mode 100644 index 000000000000..0164850e4732 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/custom_config_sdk.h @@ -0,0 +1,752 @@ +/** + **************************************************************************************** + * + * @file custom_config_sdk.h + * + * @brief Configuration for Generic-SDK + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __CUSTOM_CONFIG_SDK_H__ +#define __CUSTOM_CONFIG_SDK_H__ + +/// Global Define : Chipset Model +#if (TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (defined(BSP_MCU_RRQ61051_208) || defined(BSP_MCU_RRQ61051_408))) + #define CHIPSET_NAME "RA6W2-RRQ61051" +#else + #define CHIPSET_NAME "RA6W1-RRQ61001" +#endif /* TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (BSP_MCU_RRQ61051_208 || BSP_MCU_RRQ61051_408) */ + +/// +/// Features for RA6W1/RA6W2 SDK +/// + +#if (SIGMA_TEST_APP == 1) + #define SIGMA_TEST_ENABLE + #define STA_CERT_ENABLE + #undef ATCMD_IF_SUPPORT + #undef ATCMD_SECURE_CHANNEL +#endif + +// SDK Name +// Show the kind of SDK displayed by the "ver" command in the console. +// +// - SDK Version : VX.Y.Z.R SDK_NAME +// +#undef SDK_NAME +#define SDK_NAME "" // Default No name tag. + +// SDK Version number +// Define the SDK version number by the "ver" command in the console. +// +// - SDK Version : X.M.Y.Z.R +// +// #define SDK_VER_PRODUCT_LINE X // SDK Product line number +// #define SDK_VER_MODE M // SDK Mode number (Standalone:0 / Linux Driver:1) +// #define SDK_VER_TARGET Y // SDK Target release +// #define SDK_VER_BRANCH Z // SDK Branch number +// #define SDK_VER_R R // SDK R&D build number +// +#include "sdk_ver.h" +#if (CFG_WIFI == 1) + #include "rm_wifi.h" +#endif + +/////////////////////////////////////////////////////////////////////// +// +// Software module features of RA6W1/RA6W2 SDK +// +/////////////////////////////////////////////////////////////////////// + +// ----------------------- +// HW Related Features +// ----------------------- + +// +// Enable/Disable WPS button +// +// To enable this feature, +// : EVK board configuration +// connect BTN2 to P0_12 (Default PIN, See EVK Board manual) +// : customer can change its configuration +// ~/sdk/bsp/config/boards/brd_io_config_rrq61x.h +// +#define __SUPPORT_WPS_BTN__ + +// +// Enable/Disable Factory Reset button +// +// To enable this feature, +// : EVK board configuration +// connect BTN1 to P0_13 (Default PIN, See EVK Board manual) +// : customer can change its configuration +// ~/sdk/bsp/config/boards/brd_io_config_rrq61x.h +// +#define __SUPPORT_FACTORY_RESET_BTN__ + +// +// Enable/Disable RF antenna share for Wi-Fi & BT co-existence +// +#undef __SUPPORT_BTCOEX__ + +// +// UART2 interface connect to MCU for AT-CMD +// This interface (UART2) initialize when AT-CMD module start... +// +// When enable this feature, +// customer can change the default values for UART2 +// - DEFAULT_UART_BAUD : 115,200bps +// - UART_BITPERCHAR : 8bits +// - UART_PARITY : No parity +// - UART_STOPBIT : 1 stopbit +// - UART_FLOW_CTRL : No flow-control +// +// : Or can change UART2 configuration values thought ATB command. +// See AT-CMD user manual. +#undef __SUPPORT_UART2__ + +// +// Enable/Disable OSPI sflash api +// Remove it after FSP merged +#ifndef RRQ61X_OSPI_W_ENABLED + #define RRQ61X_OSPI_W_ENABLED +#endif /* RRQ61X_OSPI_W_ENABLED */ + +// ----------------------- +// Wi-Fi Features +// ----------------------- + +// +// Support Wi-Fi WPA3-Personal features. ( SAE, OWE ) +// +// Note #1) See Wi-Fi specification to understand WPA3 SAE and OWE operation. +// Note #2) If "__SUPPORT_ATCMD__" is enabled, this feature is default enabled also. +// +// +#define __SUPPORT_WPA3_PERSONAL__ + +// +// Support Wi-Fi WPA Enterprise feature. +// +// This feature is internal feature in ~/library/libsupplicant.a +// When enable this feature, more detail features are support below sub-features. +// In sub-feature, WPA3-Enterprise feature will be selected. Default is Enable. +// +// Note) If "__SUPPORT_ATCMD__" is enabled, this feature is default enabled also. +// Refer to AT-CMD user's guide document for how to use it. +// +#define __SUPPORT_WPA_ENTERPRISE__ + +// +// Support customer call-back functions to notify Wi-Fi connection status. +// +// This features notify the Wi-Fi connection status through registered customer call-back function. +// - Wi-Fi connection status +// - Wi-Fi disconnection status +// - Wi-Fi connection failed status +// +// Customers can change these call-back function to whatever operation they want. +// - static void user_wifi_conn(void *arg) +// - static void user_wifi_conn_fail(void *arg) +// - static void user_wifi_disconn(void *arg) +// +// These functions are registered through the "void rm_wifi_register_wifi_notify_cb(void)" +// in ~/projects/rrq61x/rrq61x/src/user_app.c +// And when start the RA6W1/RA6W2, "register_wifi_notifi_cb()" is called in net_stack_init(). +// +// In case of enabled "AT-CMD feature", the RA6W1/RA6W2 notifies the connection status to MCU. +// Customer can check this function "atcmd_asynchony_event()" +// in ~/sdk/interfaces/wifi/system/src/at_cmd/atcmd.c +// These notification are reported through internal events operation. +// +// - STA connect OK +// : +WFJAP:1,TEST_SSID,IP_ADDR +// - STA connect Fail +// : +WFJAP:0,TIMEOUT +// : +WFJAP:0,WRONGPWD +// : +WFJAP:0,ACCESSLIMIT +// : +WFJAP:0,OTHER,reason_code +// - STA disconnect +// : +WFDAP:0,AUTH_NOT_VALID +// : +WFDAP:0,DEAUTH +// : +WFDAP:0,INACTIVITY +// : +WFDAP:0,APBUSY +// : +WFDAP:0,OTHER,reason_code +// +#undef __SUPPORT_WIFI_CONN_CB__ + +// +// Support Wi-Fi Concurrent-mode. +// +// Wi-Fi Concurrent mode means two interface will be enabled. +// One (wlan0) is STA and the other (wlan1) is Soft-AP. +// +// In easy-setup, three types of Wi-Fi operation mode will be provided. +// SYSMODE(WLAN MODE) ? +// 1. Station +// 2. Soft-AP +// 3. Station & SOFT-AP <= Wi-Fi Concurrent-mode +// MODE ? [1/2/3/Quit] (Default Station) : +// +#define __SUPPORT_WIFI_CONCURRENT__ + +// ----------------------- +// System Features +// ----------------------- + +// +// Fast Connection on SLEEP mode 2 +// +// Enable/Disable Fast-connection feature. +// This function is internal one and Customer just can select enable/disable when SDK rebuild. +// +// And AT-CMD mode, two AT-CMDs are supported to handle by MCU. +// : AT+GETFASTCONN +// : AT+SETFASTCONN +// +#define __SUPPORT_FAST_CONN_SLEEP_2__ + +// +// Support cipher suites of TLS session by H/W engine. +// +// When enable this feature, only HW cipher-suites of CC312 HW enbine are used to communicate for TLS. +// This operation set in each TLS application to start TLS operation. +// +// #if defined(__SUPPORT_TLS_HW_CIPHER_SUITES__) +// preset = MBEDTLS_SSL_PRESET_RRQ_HW; +// #endif /* __SUPPORT_TLS_HW_CIPHER_SUITES__ */ +#undef __SUPPORT_TLS_HW_CIPHER_SUITES__ + +// +// Enable/Disable AT-CMD module +// +// When this feature is enabled, more detailed sub-features are supported. +// Customer can check all AT-CMDs in ~/sdk/interfaces/wifi/system/src/at_cmd/atcmd.c +// +#if (ATCMD_IF_SUPPORT == 1) + #define __SUPPORT_ATCMD__ +#else + #undef __SUPPORT_ATCMD__ +#endif // (ATCMD_IF_SUPPORT == 1) + +// +// Support FAT filesystem +// +// Configurations are defined in ~/sdk/middleware/storage/fat/ffconf.h +#undef __SUPPORT_FAT_FS__ + +// ----------------------- +// Network Features +// ----------------------- + +// +// Support IPv6 feature +// Sub feature is defined in ~/sdk/interfaces/wifi/stack/lwip/src/include/lwipopts.h +// +#ifndef __SUPPORT_IPV4__ + #define __SUPPORT_IPV4__ 1 +#endif + +#ifndef __SUPPORT_IPV6__ + #define __SUPPORT_IPV6__ 1 +#endif + +// +// Support DHCP Server on the RA6W1/RA6W2 Soft-AP mode. +// +#define __SUPPORT_DHCP_SVR__ + +// +// Support SNTP Client feature +// +// This feature enable SNTP client to get current time from the defined Internet time server. +// +#if (CFG_WIFI == 1) + #define __SUPPORT_SNTP_CLIENT__ +#endif + +// +// Support Websocket Client +// +// This feature enable Websocket client to communicate with peer Websocket server. +// +#define __SUPPORT_WEBSOCKET_CLIENT__ + +// +// Support "nslookup" network utility +// +// This function is used to get IP-address from doman-name. +// Support console-command under "net" command layer. +// +// Default disabled. +// +#define __SUPPORT_NSLOOKUP__ + +// +// Support Auto-start HTTP server application when system starting. +// +// Customer can check this task in ~/core/system/src/common/main/sys_apps.c +// +// static const app_task_info_t sys_apps_table[] = { +// ... +// #if defined ( __HTTP_SVR_AUTO_START__ ) +// { APP_HTTP_SVR, auto_run_http_svr, 256, (OS_TASK_PRIORITY_NORMAL + 6), TRUE, FALSE, HTTP_SVR_PORT, RUN_AP_MODE }, +// #endif // __HTTP_SVR_AUTO_START__ +// +// Note) If "__SUPPORT_ATCMD__" is enabled, this feature is default enabled also. +// Refer to AT-CMD user's guide document for how to use it. +// +#undef __HTTP_SVR_AUTO_START__ + +// +// Support CLI command on Console for HTTP-Server operation +// This feature supports to check the operation status with console command. +// +// NET : Network +// ------- : -------------------------------- +// http-server : http-server -I [wlan0|wlan1] [start|stop] +// +// These commands operate with own IP-address and 80 port number as default. +// +#undef __SUPPORT_HTTP_SERVER_FOR_CLI__ + +// +// Support CLI command on Console for HTTP-Client operation +// This feature supports to check the operation status with console command. +// +// NET : Network +// ------- : -------------------------------- +// http-client : http-client help +// +// [/RRQ61000/NET] # http-client +// +// Usage: HTTP Client +// Name +// http-client - HTTP Client +// SYNOPSIS +// http-client [OPTION]...URL +// DESCRIPTION +// Request client's method to URL +// -i [wlan0|wlan1] +// Set interface of HTTP Client +// -status +// Display status of HTTP Client +// -help +// Display help +// -head +// Request HEAD method to URI +// -get +// Request GET method to URI +// -post RESOURCE +// Request POST method to URI with RESOURCE +// -put RESOURCE +// Request PUT method to URI with RESOURCE +// -incoming Size +// Set incoming buffer size of TLS Contents +// -outgoing Size +// Set outgoing buffer size of TLS Contents +// -sni +// Set SNI for TLS extension +// -alpn +// Set ALPN for TLS extension +// +#undef __SUPPORT_HTTP_CLIENT_FOR_CLI__ + +// +// Support DNS 2nd cache internally. +// +// This function supports semi-cache operation to reduce DNS query time. +// The address found as a new domain name is stored in the memory, +// and when a new DNS Query is performed, the address is first found in the cache area. +// This caching IP addresses are also save in NVRAM to reload when booting time. +// +// Stores up to 25 domain-names and IP address. +// The maximum length of domain name is 128 Bytes. +// +// Note) If this feature is enabled, +// do not use 4KB from SFLASH_USER_AREA_START area for other purpose. +// +#undef __DNS_2ND_CACHE_SUPPORT__ + +#ifdef __DNS_2ND_CACHE_SUPPORT__ + #undef __DNS_2ND_CACHE_INFO__ +#endif /* __DNS_2ND_CACHE_SUPPORT__ */ + +// +// Support "dns cache" info utility +// +// This function is for viewing DNS cache information. +// Support console-command under "net" command layer. +// +// Default disabled. +#undef __DNS_CACHE_INFO__ + +// +// Support User DHCP-client hostname function. +// +// This feature support to set user DHCP hostname rather than default value (RA6WX-XXYY). +// When enable this feature, console command is enabled. +// +// Note #1) This feature complies with RFCs(952, 1123). +// : RFCs(952, 1123) mandate that a hostname's labels may contain only +// the ASCII letters 'a' through 'z' (case-insensitive), +// the digits '0' through '9', and the hyphen. +// Hostname labels cannot begin or end with a hyphen. +// No other symbols, punctuation characters, or blank spaces are permitted. +// +// Note #2) If "__SUPPORT_ATCMD__" is enabled, this feature is default enabled also. +// +// - AT+NWDHCHN +// - AT+NWDHCHNDEL +// +// Refer to AT-CMD user's guide document for how to use it. +// +#undef __USER_DHCP_HOSTNAME__ + +// +// Support iPerf tool for network performance measurement. +// +// This test operation can operate using by console commands. +// +// Note) iPerf 2.X version is compatible but don't compatible with iPerf V3.X on peer device. +// +// [/RRQ61000/NET] # iperf -help +// Usage: iperf -I [WLAN0|WLAN1] [-s|-c host][options] +// iperf [-h] [-v] +// +// Client/Server: +// -I Interface [WLAN0|WLAN1] +// -i seconds between periodic bandwidth reports +// -u use UDP rather than TCP +// -p, # server port to listen on/connect to +// -f, [kmKM] format to report: Kbits, Mbits, KBytes, MBytes +// -d finsh service +// ex) iperf -I [wlan0|wlan1] -d -c -u : udp clinet +// iperf -I [wlan0|wlan1] -d -c : tcp clinet +// iperf -I [wlan0|wlan1] -d -u : udp server +// iperf -I [wlan0|wlan1] -d : tcp server +// +// Server specific: +// -s run in server mode +// -T # Rx Time Out Min:1 sec. 'F' Forever +// +// Client specific: +// -c run in client mode, connecting to +// -t # time in seconds to transmit for (default 10 secs) +// -x # tcp API mode default:basic tcp(API) 1:Altcp 2:Socket +// -y # Transmit delay, tick 1 ~ 100 +// -l # PacketSize option (UDP default 1470, IPv6 1448 TCP 1000) +// -n # UDP Tx packet number +// -P, # Pair Index (0,1,2) +// (default Max, Step 1~100 Mbps) +// -O use Main Packet Pool +// +// Miscellaneous: +// -h print this message +// -v print version +// +// Refer to "RA6W1/RA6W2 Getting Started Guide" document for more detailed information +// to use iPerf tool on the RA6W1/RA6W2. +// +#if (CFG_WIFI == 1) + #define __SUPPORT_IPERF__ // support iperf + #undef __SUPPORT_IPERF3__ // support iperf3 + #define __SUPPORT_WIFI_DBG__ // support wifi debug +#endif + +// +// Easy-setup on console +// +// Support CLI command on Console to create/save Wi-Fi connection profile in NVRAM. +// +#if CFG_WIFI +#define __SUPPORT_EASY_SETUP__ // Easy Setup application. +#endif +// ------------------- +// User Features +// ------------------- + +// +// User can set maximum size of http-client's tx buffer. (Default 4KB, Available 2KB~8KB) +// +// HTTPC_REQ_DATA_MAX_SIZE affects the size of TX_PAYLOAD_MAX_SIZE and USER_ATCMD_BUF defined in atcmd.h. +// TX_PAYLOAD_MAX_SIZE and USER_ATCMD_BUF must always be greater than HTTPC_REQ_DATA_MAX_SIZE. +// +// #define TX_PAYLOAD_MAX_SIZE HTTPC_REQ_DATA_MAX_SIZE +// #define USER_ATCMD_BUF (TX_PAYLOAD_MAX_SIZE + 32) +// +#define HTTPC_REQ_DATA_MAX_SIZE (1024 * 4) +#if (HTTPC_REQ_DATA_MAX_SIZE < (1024 * 2)) + #error "Supporting buffer size error : Too small !!!" +#elif (HTTPC_REQ_DATA_MAX_SIZE > (1024 * 8)) + #error "Supporting buffer size error : Too large !!!" +#endif + +/////////////////////////////////////////////////////////////////////// +// +// SUB-features for Generic-SDK +// +/////////////////////////////////////////////////////////////////////// +// + +#if !defined(RENESAS_AT25SL_8MB_OTA) && !defined(NORMAL_4MB_OTA) + #undef __SUPPORT_OTA__ +#endif // !RENESAS_AT25SL_8MB_OTA && !NORMAL_4MB_OTA + +#if defined(CONFIG_PLT_TEST) + #define __SUPPORT_PRODTEST__ + #ifndef __SUPPORT_ATCMD__ + #define __SUPPORT_ATCMD__ + #endif +#endif + +#if defined __SUPPORT_FAST_CONN_SLEEP_2__ + #define __SUPPORT_DHCPC_IP_TO_STATIC_IP__ + #undef __BOOT_CONN_TIME_PRINT__ +#endif // __SUPPORT_FAST_CONN_SLEEP_2__ + +#if defined(__SUPPORT_ATCMD__) + +// +// Default interface of RRQ61x EVK is UART2. +// Customer can change the type of host-interfaces among four types listed below. +// __ATCMD_IF_UART2__ / __ATCMD_IF_UART3__ / __ATCMD_IF_SPI__ / __ATCMD_IF_SDIO__ +// When one is enabled, the other 3 should be disabled. +// + #if (ATCMD_IF_SUPPORT == 1) + #undef __ATCMD_IF_UART2__ // AT-CMD over UART2 + #undef __ATCMD_IF_UART3__ // AT-CMD over UART3 + #undef __ATCMD_IF_SPI__ // AT-CMD over SPI + #undef __ATCMD_IF_SDIO__ // AT-CMD over SDIO + #else + +/* UART3 is dedicated to FSP, so UART2 is used for AT-CMD */ + #define __ATCMD_IF_UART2__ // AT-CMD over UART2 + #undef __ATCMD_IF_UART3__ // AT-CMD over UART3 + #undef __ATCMD_IF_SPI__ // AT-CMD over SPI + #undef __ATCMD_IF_SDIO__ // AT-CMD over SDIO + #endif // (ATCMD_IF_SUPPORT == 1) + + #define __SUPPORT_TCP_RECVDATA_HEX_MODE__ // Support AT+TCPDATAMODE command + #undef __ENABLE_TXFIFO_CHK_IN_LOW_BAUDRATE__ + #define __SUPPORT_NOTIFY_RTC_WAKEUP__ + #undef __USER_UART_CONFIG__ // Support Customer's UART configuration + + #undef __TRIGGER_DPM_MCU_WAKEUP__ // MCU Wakeup-triggering when DPM UC wakeup + #define __DPM_WAKEUP_NOTICE_ADDITIONAL__ // Report DPM Wakeup RTC/ETC + #undef __SUPPORT_DPM_ABNORM_MSG__ // Send message to MCU when wake-up from DPM Abnormal stat + #undef __SUPPORT_DPM_EXT_WU_MON__ // DPM monitor for External Wakeup + #if defined(__SUPPORT_DPM_EXT_WU_MON__) + #undef __SUPPORT_UC_WU_MON__ // DPM monitor for UC Wakeup + #endif // __SUPPORT_DPM_EXT_WU_MON__ + + #undef __DISABLE_ESC_DATA_ECHO__ // Echo ESC data input ( Data Tx Mode ) + #if defined(__DISABLE_ESC_DATA_ECHO__) + #define __ENABLE_ESC_DATA_DUMP__ // Tx Data dump on UART2 + #endif // __DISABLE_ESC_DATA_ECHO__ + + #undef __SUPPORT_HTTP_SERVER_FOR_ATCMD__ // HTTP server + #undef __SUPPORT_HTTP_SERVER_FOR_CLI__ + + #undef __SUPPORT_HTTP_CLIENT_FOR_ATCMD__ // HTTP client + #undef __SUPPORT_HTTP_CLIENT_FOR_CLI__ + +// +// Support User-format to send HTTP-Client request ( header + body ) +// +// When a customer requests an http-client using AT-CMD, +// the header format already defined in http_client.c is not used, but the header is written in free form. +// If there is data to be sent, such as PUT or POST, it can be configured in the form of header + data. +// +// This function is used by MCU through AT-CMDs. +// : AT+NWHTC=,message,'XXXXX' +// +// Note) Refer to AT-CMD user's guide document for how to use it. +// + #define __SUPPORT_HTTP_CLIENT_USER_MSG__ + + #define __SUPPORT_WPA3_PERSONAL__ // Wi-Fi WPA3-Personal ( SAE, OWE ) + #define __SUPPORT_WPA_ENTERPRISE__ // Wi-Fi WPA Enterprise + #define __SUPPORT_FAST_CONN_SLEEP_2__ + + #undef __ENABLE_TRANSFER_MNG__ // Ring-Buffer for throughput + #define __USER_DHCP_HOSTNAME__ // User DHCP-client hostname + #define __SUPPORT_DETAILED_ERR_CODE__ // Support detailed error code + + #define __SUPPORT_RSSI_CMD__ // AT+WFRSSI + #if (ATCMD_IF_SUPPORT == 1) + #define __SUPPORT_ATCMD_TLS__ // TLS session + #else + #undef __SUPPORT_ATCMD_TLS__ // TLS session + #endif // (ATCMD_IF_SUPPORT == 1) + #undef __SUPPORT_USER_CMD_HELP__ // User AT-CMD Help + #undef __SUPPORT_PERI_CTRL__ // Support LED/I2C/PWM/ADC over AT-CMD + #undef __SUPPORT_LMAC_RF_CMD__ // AT-CMDs for LMAC/RF + #undef __SUPPORT_PERI_CMD__ // AT-CMDs for peripheral devices + +// Reconfig for AT-CMD + #undef __SUPPORT_HELLO_WORLD__ +#endif // __SUPPORT_ATCMD__ + +// If RAM build mode then always enable LMAC RF CMDs ... +#if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE) && defined(CONFIG_PLT_TEST) + #undef __SUPPORT_FAST_CONN_SLEEP_2__ + #undef __SUPPORT_OTA__ + #undef __SUPPORT_MQTT__ + #undef __SUPPORT_HTTP_SERVER_FOR_ATCMD__ // HTTP server + #undef __SUPPORT_HTTP_CLIENT_FOR_ATCMD__ // HTTP client + #undef __SUPPORT_WPA3_PERSONAL__ // Wi-Fi WPA3-Personal ( SAE, OWE ) + #undef __SUPPORT_WPA_ENTERPRISE__ // Wi-Fi WPA Enterprise +#endif + +#if defined(__SUPPORT_PRODTEST__) + #define __USER_UART_CONFIG__ // Set to default, not to read from NVRam + #define __SUPPORT_PRODTEST_CONSOLE__ // Enable if requires for quick test + #define __SUPPORT_TCS_CMD__ + #ifdef __SUPPORT_TCS_CMD__ + #define TEST_TCS_OTP // For test OTP + #endif + #ifndef __SUPPORT_LMAC_RF_CMD__ + #define __SUPPORT_LMAC_RF_CMD__ + #endif +#endif + +#if defined(__SUPPORT_BTCOEX__) + #undef __SUPPORT_BTCOEX_1PIN__ // 1PIN BTCOEX +#endif // __SUPPORT_BTCOEX__ + +#if defined(__SUPPORT_FACTORY_RESET_BTN__) + #define __SUPPORT_FACTORY_RST_APMODE__ // Factory reset AP-Mode + #undef __SUPPORT_FACTORY_RST_STAMODE__ // Factory reset STA-Mode +#endif // __SUPPORT_FACTORY_RESET_BTN__ + +#if defined(__SUPPORT_OTA__) + #undef __OTA_UPDATE_MCU_FW__ + #if defined(__OTA_UPDATE_MCU_FW__) && !defined(__ATCMD_IF_SPI__) && !defined(__ATCMD_IF_SDIO__) + #if (ATCMD_IF_SUPPORT == 1) + #undef __SUPPORT_UART2__ + #else + #define __SUPPORT_UART2__ + #endif // (ATCMD_IF_SUPPORT == 1) + #endif // __OTA_UPDATE_MCU_FW__ ... +#endif // __SUPPORT_OTA__ + +#if defined(__SUPPORT_WPA_ENTERPRISE__) + #define __SUPPORT_WPA3_ENTERPRISE__ + + #if defined(__SUPPORT_WPA3_ENTERPRISE__) + #define __SUPPORT_WPA3_ENTERPRISE_192B__ // Unsupported on RA6W1/RA6W2 + #endif // __SUPPORT_WPA3_ENTERPRISE__ +#endif /* __SUPPORT_WPA_ENTERPRISE__ */ + +#if defined(__SUPPORT_IPERF__) + #undef __IPERF_BANDWIDTH__ // Debug only + #undef __IPERF_PRINT_MIB__ // Print iPerf MIB Info. + #undef __LIB_IPERF_PRINT_MIB__ // Print iPerf MIB Info. +#endif // __SUPPORT_IPERF__ + +#if defined(__SUPPORT_EASY_SETUP__) + #define __SUPPORT_APP_CONSOLE_INPUT__ // Handle application's console input + #undef __SUPPORT_DFS_CH_IN_SOFTAP__ // Support DFS channel in SoftAP +#endif // __SUPPORT_EASY_SETUP__ + +#if defined(__SUPPORT_WPS_BTN__) || defined(__SUPPORT_FACTORY_RESET_BTN__) + +// +// Enable LED for WPS PBC and Factory Reset +// +// To enable this feature, +// : EVK board configuration +// connect LED0 to P1_14 (Default PIN, See EVK Board manual) +// : customer can change its configuration +// ~/sdk/bsp/config/boards/brd_io_config_rrq61x.h +// + #if defined (LED0) + #define __SUPPORT_EVK_LED__ + #endif + #define __SUPPORT_FACTORY_RST_CONCURR_MODE__ +#endif /* defined (__SUPPORT_WPS_BTN__) || defined (__SUPPORT_FACTORY_RESET_BTN__) */ + +/////////////////////////////////////////////////////////////////////// +// +// DEPENDENT-features for customer SDK +// +/////////////////////////////////////////////////////////////////////// + +#if defined(__SUPPORT_ATCMD__) + #if defined(__ATCMD_IF_SDIO__) + #undef __SUPPORT_WPS_BTN__ // WPS button + #undef __SUPPORT_FACTORY_RESET_BTN__ // Factory reset Button + #endif // __ATCMD_IF_SDIO__ + + #if defined(__SUPPORT_OTA__) + #define __OTA_UPDATE_MCU_FW__ + #if defined(__OTA_UPDATE_MCU_FW__) && !defined(__ATCMD_IF_SPI__) && !defined(__ATCMD_IF_SDIO__) + #if (ATCMD_IF_SUPPORT == 1) + #undef __SUPPORT_UART2__ + #else + #define __SUPPORT_UART2__ + #endif // (ATCMD_IF_SUPPORT == 1) + #endif // __OTA_UPDATE_MCU_FW__ + #endif // __SUPPORT_OTA__ + + #if defined(__SUPPORT_WIFI_PROVISIONING__) + #define __PROVISION_ATCMD__ // provisioining at cmd + #endif // __SUPPORT_WIFI_PROVISIONING__ + + #ifdef __SUPPORT_WEBSOCKET_CLIENT__ + #define __SUPPORT_WEBSOCKET_CLIENT_FOR_ATCMD__ + #endif // __SUPPORT_WEBSOCKET_CLIENT__ + + #if defined(__SUPPORT_LMAC_RF_CMD__) + #define __ENABLE_LMAC_CMD__ + #define __ENABLE_LMAC_TX_CMD__ + #define __ENABLE_RF_CMD__ + #endif // __SUPPORT_LMAC_RF_CMD__ +#endif // __SUPPORT_ATCMD__ + +#if defined(__SUPPORT_HTTP_SERVER_FOR_CLI__) || defined(__SUPPORT_HTTP_SERVER_FOR_ATCMD__) + #undef __HTTP_SVR_AUTO_START__ +#endif // __SUPPORT_HTTP_SERVER_FOR_CLI__ || __SUPPORT_HTTP_SERVER_FOR_ATCMD__ + +//////////////////////////////////////////////////////////////////////////// +// +// !!! Notice !!! +// Do not remove this line and do not move the location in this file. +// + +#include "sys_feature_sdk.h" + +//////////////////////////////////////////////////////////////////////////// + +#if (CFG_WIFI == 0) + #undef __SUPPORT_SNTP_CLIENT__ + #undef __SUPPORT_P2P__ +#endif + +#endif // __CUSTOM_CONFIG_SDK_H__ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sdk_ver.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sdk_ver.h new file mode 100644 index 000000000000..abb06b8f97ac --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sdk_ver.h @@ -0,0 +1,66 @@ +/** + **************************************************************************************** + * + * @file sdk_ver.h + * + * @brief Configuration for SDK Version + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __SDK_VER_H__ +#define __SDK_VER_H__ + +// SDK Version number +#undef SDK_VER_PRODUCT_LINE +#undef SDK_VER_MODE +#undef SDK_VER_TARGET +#if (TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (defined (BSP_MCU_RRQ61051_208) || defined (BSP_MCU_RRQ61051_408))) + #define SDK_VER_PRODUCT_LINE 8 // SDK Product line number + #define SDK_VER_MODE 0 // SDK Mode number (Standalone:0 / Linux Driver:1) + #define SDK_VER_TARGET 3 // SDK Target release + #define SDK_VER_BRANCH 0 // SDK Branch number + #define SDK_VER_R 6 // SDK R&D build number +#else + #define SDK_VER_PRODUCT_LINE 8 // SDK Product line number + #define SDK_VER_MODE 0 // SDK Mode number (Standalone:0 / Linux Driver:1) + #define SDK_VER_TARGET 3 // SDK Target release + #define SDK_VER_BRANCH 0 // SDK Branch number + #define SDK_VER_R 6 // SDK R&D build number +#endif /* TIN_SKU_BUILD_ID == TIN_SKU_WIFI6_B24_5_BLE || (BSP_MCU_RRQ61051_208 || BSP_MCU_RRQ61051_408) */ + +#ifdef SIGMA_TEST_ENABLE +#define t_XSTR(i) #i +#define t_STR(i) t_XSTR(i) +#define SIGMA_SDK_VERSION (t_STR(SDK_VER_PRODUCT_LINE) "." \ + t_STR(SDK_VER_MODE) "." \ + t_STR(SDK_VER_TARGET) "." \ + t_STR(SDK_VER_BRANCH) "." \ + t_STR(SDK_VER_R)) +#endif //SIGMA_TEST_ENABLE + +#endif // __SDK_VER_H__ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sys_feature_sdk.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sys_feature_sdk.h new file mode 100644 index 000000000000..93b1cb537afb --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/include/sys_feature_sdk.h @@ -0,0 +1,106 @@ +/** + **************************************************************************************** + * + * @file sys_feature_sdk.h + * + * @brief Define for common system features + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __SYS_COMMON_FEATURES_H__ +#define __SYS_COMMON_FEATURES_H__ + +#if CFG_WIFI +// Wi-Fi configuration features +#include "ra6w1_wifi_features.h" +#endif /* CFG_WIFI */ + +// Console Prompt +#define PROMPT "/" CHIPSET_NAME + +/////////////////////////////////////////////////////////////////////// +// +// Main features for customer SDK +// +/////////////////////////////////////////////////////////////////////// + +// +// System features ................................................... +// + +// wifi re-connect stops when wifi conn fail by wrong key +#undef __WIFI_CONN_RETRY_STOP_AT_WK_CONN_FAIL__ + +// Log message for Code run-time +#undef __RUNTIME_CALCULATION__ + +// SIGMA Throughput Test for Wi-Fi Certification +#undef __SUPPORT_SIGMA_TEST__ + + +/////////////////////////////////////////////////////////////////////// +// +// Sub features +// +/////////////////////////////////////////////////////////////////////// + +#if defined (__WIFI_CONN_RETRY_STOP_AT_WK_CONN_FAIL__) + #undef __DPM_ABN_SLEEP1_BY_WK_CONN_FAIL__ // optional: dpm abnormal sleep1 when wifi conn fail by wrong key +#endif // __WIFI_CONN_RETRY_STOP_AT_WK_CONN_FAIL__ + +// Wi-Fi Certification features +#if defined ( __SUPPORT_SIGMA_TEST__ ) + #define __SUPPORT_SIGMA_THROUGHPUT__ + #define __SUPPORT_SIGMA_UAPSD__ +#endif // __SUPPORT_SIGMA_TEST__ + +/////////////////////////////////////////////////////////////////////// +// +// Dependent features for customer SDK +// +/////////////////////////////////////////////////////////////////////// + +// Wi-Fi Certification features +#if defined ( __SUPPORT_SIGMA_TEST__ ) + #undef __SUPPORT_WPS_BTN__ + + #define __SUPPORT_UART2__ + #undef __SUPPORT_ATCMD__ + + #define __SUPPORT_IEEE80211W__ // IEEE 802.11W(PMF) +#endif // __SUPPORT_SIGMA_TEST__ + +#if defined ( __ENABLE_UMAC_CMD__ ) + #define __ENABLE_LMAC_TX_CMD__ +#endif // __ENABLE_UMAC_CMD__ + +#if defined (__SUPPORT_WPS_BTN__) || defined (__SUPPORT_FACTORY_RESET_BTN__) +#include "sdk_defs.h" +#endif // __SUPPORT_WPS_BTN__ || __SUPPORT_FACTORY_RESET_BTN__ + +#endif // __SYS_COMMON_FEATURES_H__ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/middleware_defaults.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/middleware_defaults.h new file mode 100644 index 000000000000..5758d59bd78a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/middleware_defaults.h @@ -0,0 +1,495 @@ +/** + * \{ + * \addtogroup MIDDLEWARE_CONFIG_DEFAULTS + * + * \brief Middleware default configuration values + * + * The following tags are used to describe the type of each configuration option. + * \{ + */ + +/** + **************************************************************************************** + * + * @file middleware_defaults.h + * + * @brief Middleware. System Configuration file default values. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef MIDDLEWARE_DEFAULTS_H_ +#define MIDDLEWARE_DEFAULTS_H_ + +/** + * \addtogroup ADAPTER_SELECTION Adapters enabled by default + * + * \brief Adapter selection + * + * When enabled the specific adapter is included in the compilation of the SDK. + * - 0 : Disabled + * - 1 : Enabled + * + * The default option can be overridden in the application configuration file. + * + * \{ + * Adapter | Setting | Default option + * ------------------------------ | -------------------------------------- | :------------------: + * Table not yet fixed | dg_configXXXXX_ADAPTER | 1 + * + */ + +/* -------------------------------- Adapters (ad_*) selection -------------------------------- */ + +#ifndef dg_configFLASH_ADAPTER + #define dg_configFLASH_ADAPTER (0) +#endif + +#ifndef dg_configI2C_ADAPTER + #define dg_configI2C_ADAPTER (0) +#endif + +#ifndef dg_configNVMS_ADAPTER + #define dg_configNVMS_ADAPTER (0) +#endif + +#ifndef dg_configNVMS_FLASH_CACHE + #define dg_configNVMS_FLASH_CACHE (0) +#endif + +#ifndef dg_configNVMS_VES + #define dg_configNVMS_VES (0) +#endif + +#ifndef dg_configSPI_ADAPTER + #define dg_configSPI_ADAPTER (0) +#endif + +#ifndef dg_configUART_ADAPTER + #define dg_configUART_ADAPTER (0) +#endif + +#ifndef dg_configGPADC_ADAPTER + #define dg_configGPADC_ADAPTER (0) +#endif + +#ifndef dg_configSDADC_ADAPTER + #define dg_configSDADC_ADAPTER (0) +#endif + +#ifdef dg_configTEMPSENS_ADAPTER + #error "Configuration option dg_configTEMPSENS_ADAPTER is no longer supported" +#endif + +#ifdef dg_configBATTERY_ADAPTER + #error "Configuration option dg_configBATTERY_ADAPTER is no longer supported" +#endif + +#ifndef dg_configNVPARAM_ADAPTER + #define dg_configNVPARAM_ADAPTER (0) +#endif + +#ifndef dg_configNVPARAM_APP_AREA + #define dg_configNVPARAM_APP_AREA (0) +#endif + +#ifndef dg_configCRYPTO_ADAPTER + #define dg_configCRYPTO_ADAPTER (0) +#endif + +#ifndef dg_configKEYBOARD_SCANNER_ADAPTER + #define dg_configKEYBOARD_SCANNER_ADAPTER (0) +#endif + +#if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #ifndef dg_configSYS_AUDIO_MGR + #define dg_configSYS_AUDIO_MGR (0) + #endif +#endif /* DEVICE_FAMILY */ + +#if (DEVICE_FAMILY == DA1468X) + + #ifndef dg_configRF_ADAPTER + #define dg_configRF_ADAPTER (0) + #endif + + #if (dg_configSNC_ADAPTER == 1) + #error "dg_configSNC_ADAPTER is not supported in DA14680 devices" + #else + #undef dg_configSNC_ADAPTER + #define dg_configSNC_ADAPTER (0) + #endif + + #if (dg_configISO7816_ADAPTER == 1) + #error "dg_configISO7816_ADAPTER is not supported in DA14680 devices" + #else + #undef dg_configISO7816_ADAPTER + #define dg_configISO7816_ADAPTER (0) + #endif + + #if (dg_configLCDC_ADAPTER == 1) + #error "dg_configLCDC_ADAPTER is not supported in DA14680 devices" + #else + #undef dg_configLCDC_ADAPTER + #define dg_configLCDC_ADAPTER (0) + #endif + + #if (dg_configPMU_ADAPTER == 1) + #error "dg_configPMU_ADAPTER is not supported in DA14680 devices" + #else + #undef dg_configPMU_ADAPTER + #define dg_configPMU_ADAPTER (0) + #endif + + #if (dg_configHAPTIC_ADAPTER == 1) + #error "dg_configHAPTIC_ADAPTER is not supported in DA14680 devices" + #else + #undef dg_configHAPTIC_ADAPTER + #define dg_configHAPTIC_ADAPTER (0) + #endif + +#elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + + #ifndef dg_configSNC_ADAPTER + #define dg_configSNC_ADAPTER (0) + #endif + + #ifndef dg_configISO7816_ADAPTER + #define dg_configISO7816_ADAPTER (0) + #endif + + #ifndef dg_configLCDC_ADAPTER + #define dg_configLCDC_ADAPTER (0) + #endif + + #ifndef dg_configPMU_ADAPTER + #define dg_configPMU_ADAPTER (0) + #endif + + #ifndef dg_configHAPTIC_ADAPTER + #define dg_configHAPTIC_ADAPTER (0) + #elif dg_configHAPTIC_ADAPTER + #if (!(dg_configUSE_HW_ERM || dg_configUSE_HW_LRA)) + #error \ + "Configuration option dg_configHAPTIC_ADAPTER also requires either the dg_configUSE_HW_LRA or the dg_configUSE_HW_ERM configuration options to be set." + #endif + #endif + + #ifdef dg_configRF_ADAPTER + #error "dg_configRF_ADAPTER is not supported in DA14690 devices" + #endif + +#endif /* DEVICE_FAMILY */ + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup CONSOLE_IO_SETTINGS Console I/O Settings + * + * \brief Console IO configuration settings + * + * \{ + * Description | Setting | Default option + * ----------------------------------------- | -------------------------- | :---------------: + * Enable serial console module | dg_configUSE_CONSOLE | 0 + * Enable serial console stubbed API | dg_configUSE_CONSOLE_STUBS | 0 + * Enable Command Line Interface module | dg_configUSE_CLI | 0 + * Enable Command Line Interface stubbed API | dg_configUSE_CLI_STUBS | 0 + * + * \see console.h cli.h + * + * \note CLI module requires dg_configUSE_CONSOLE to be enabled. + */ + +/* -------------------------------------- Console IO configuration settings --------------------- */ + +#ifndef dg_configUSE_CONSOLE + #define dg_configUSE_CONSOLE (0) +#endif + +#ifndef dg_configUSE_CONSOLE_STUBS + #define dg_configUSE_CONSOLE_STUBS (0) +#endif + +#ifndef dg_configUSE_CLI + #define dg_configUSE_CLI (0) +#endif + +#ifndef dg_configUSE_CLI_STUBS + #define dg_configUSE_CLI_STUBS (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup MIDDLEWARE_DEBUG_SETTINGS Debug Settings + * + * \{ + */ + +/* -------------------------------------- Debug settings ---------------------------------------- */ + +/** + * \brief Enable task monitoring. + * + * \note Task monitoring can only be enabled if RTT or RETARGET is enabled + */ +#ifndef dg_configENABLE_TASK_MONITORING + #define dg_configENABLE_TASK_MONITORING (0) +#endif + +#if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + +/** + * \brief Enable Micro Trace Buffer + * + * \note MTB is available only on Cortex-M33. + * + */ + #ifndef dg_configENABLE_MTB + #define dg_configENABLE_MTB (0) + #endif +#endif /* DEVICE_FAMILY */ + +/* ---------------------------------------------------------------------------------------------- */ + +/* ---------------------------------- OS related configuration ---------------------------------- */ + +/** + * \brief Monitor OS heap allocations + */ +#ifndef dg_configTRACK_OS_HEAP + #define dg_configTRACK_OS_HEAP (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ---------------------------------- SYSTEM CONFIGURATION ------------------------------------ */ + +/** + * \brief Enable gpadc monitoring. + * + * \note The application must not explicitly set dg_configUSE_SYS_ADC to 1.\n + * Use instead dg_configRF_ENABLE_RECALIBRATION\n + */ + +#ifndef dg_configUSE_SYS_ADC + #define dg_configUSE_SYS_ADC (0) +#endif + +/** + * \brief When set to 1, the sys charger service is used to charge the battery. + */ +#ifndef dg_configUSE_SYS_CHARGER + #define dg_configUSE_SYS_CHARGER (0) +#endif + +/** + * \brief When set to 1, the sys usb service is used to manage: + * - VBUS attach / detach and USB suspend / resume operations. + * - Notifications towards SDK and applications. + * - Suspend / resume sleep. + * - Suspend / resume DC/DC if in use. + * + * \note The service is automatically enabled when charging or USB enumeration + * are involved (see dg_configUSE_SYS_CHARGER , dg_configUSE_USB_ENUMERATION). + * It's recommended to be enabled when: + * - The power supply is a non rechargeable battery and the application is not + * interested in USB enumeration. + * - The only source of power supply is VBUS e.g a USB dongle. + */ +#ifndef dg_configUSE_SYS_USB + #define dg_configUSE_SYS_USB (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* ----------------------------------- Driver dependencies -------------------------------------- */ + +/* If USB charger is enebled, we need to enable GPADC and Battery adapters as well */ +#if (dg_configUSE_USB_CHARGER == 1) + #undef dg_configGPADC_ADAPTER + #define dg_configGPADC_ADAPTER (1) +#endif + +/* + * SYS_CHARGER will else enable SYS_USB which implements the USB and VBUS interrupt handlers + */ +#if (dg_configUSE_SYS_CHARGER == 1) + #undef dg_configUSE_HW_USB_CHARGER + #define dg_configUSE_HW_USB_CHARGER (1) + #undef dg_configUSE_HW_CHARGER + #define dg_configUSE_HW_CHARGER (1) + #undef dg_configUSE_HW_USB + #define dg_configUSE_HW_USB (1) + #undef dg_configUSE_SYS_USB + #define dg_configUSE_SYS_USB (1) +#endif + +/* + * For USB_ENUMERATION to work, SYS_USB is also enabled, and library usb_lib needs to be linked + * with the active project + */ +#if (dg_configUSE_USB_ENUMERATION == 1) + #undef dg_configUSE_SYS_USB + #define dg_configUSE_SYS_USB (1) + #ifndef dg_configUSB_SUSPEND_MODE + #define dg_configUSB_SUSPEND_MODE USB_SUSPEND_MODE_NONE + #elif (dg_configUSB_SUSPEND_MODE == USB_SUSPEND_MODE_PAUSE) + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #error "USB_SUSPEND_MODE_PAUSE is currently not supported" + #endif + #endif +#endif + +/* + * SYS_USB can be explicitly enabled, even if dg_configUSE_SYS_CHARGER and dg_configUSE_USB_ENUMERATION + * are not used. This will enable the VBUS and USB interrupt handlers, but no functionality will be + * attached to them + */ +#if (dg_configUSE_SYS_USB == 1) + #undef dg_configUSE_HW_USB + #define dg_configUSE_HW_USB (1) + #if (DEVICE_FAMILY == DA1468X) + #undef dg_configUSE_HW_USB_CHARGER + #define dg_configUSE_HW_USB_CHARGER (1) + #endif +#endif + +/* If RF recalibration is enabled or RCX is used as low power clock, we need to enable SNC and GPADC as well */ +#if (dg_configRF_ENABLE_RECALIBRATION || (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_RCX && \ + defined(OS_FREERTOS))) + #undef dg_configUSE_HW_GPADC + #define dg_configUSE_HW_GPADC (1) + #undef dg_configGPADC_ADAPTER + #define dg_configGPADC_ADAPTER (1) + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #if (dg_configRF_ENABLE_RECALIBRATION) + #undef dg_configUSE_SYS_ADC + #define dg_configUSE_SYS_ADC (1) + #endif + #undef dg_configUSE_SNC_HW_GPADC + #define dg_configUSE_SNC_HW_GPADC (1) + #undef dg_configUSE_HW_SENSOR_NODE + #define dg_configUSE_HW_SENSOR_NODE (1) + #undef dg_configSNC_ADAPTER + #define dg_configSNC_ADAPTER (1) + #undef dg_configUSE_STATIC_IO_CONFIG + #define dg_configUSE_STATIC_IO_CONFIG (1) + #endif +#endif + +/** + * + * \brief RTC-to-PDC event period, in 10ms + * + * When RCX is set as the low power clock or RF calibration is enabled and Real Time Clock is used + * dg_configRTC_PDC_EVENT_PERIOD defines the RTC-to-PDC event period that will be used for RTC event controller + * configuration. + * + */ +#if (dg_configRF_ENABLE_RECALIBRATION || (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_RCX && \ + defined(OS_FREERTOS))) + #ifndef dg_configRTC_PDC_EVENT_PERIOD + #define dg_configRTC_PDC_EVENT_PERIOD (100) // in 10ms + #endif +#else + #ifdef dg_configRTC_PDC_EVENT_PERIOD + #undef dg_configRTC_PDC_EVENT_PERIOD + #endif +#endif + +/** + * + * \brief RCX calibration polling interval counter + * + * dg_configRCX_CAL_POLL_INT defines the number of RTC-to-PDC events that SYS_RCX ucode should wait before executing its code. + * + */ +#if (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_RCX && defined(OS_FREERTOS)) + #ifndef dg_configRCX_CAL_POLL_INT + #define dg_configRCX_CAL_POLL_INT (1) // in dg_configRTC_PDC_EVENT_PERIOD * 10ms - calibration interval = 1sec + #endif +#endif + +/** + * + * \brief RF calibration polling interval counter + * + * dg_configRF_CAL_POLL_INT defines the number of RTC-to-PDC events that SYS_ADC ucode should wait before executing its code + * when RF calibration is enabled. + * + */ +#if (dg_configRF_ENABLE_RECALIBRATION) + #ifndef dg_configRF_CAL_POLL_INT + #define dg_configRF_CAL_POLL_INT (1) // in dg_configRTC_PDC_EVENT_PERIOD * 10ms - calibration interval = 1sec + #endif +#endif + +/* If RF is enabled, we need to enable GPADC adapter as well */ +#if dg_configRF_ADAPTER + #undef dg_configGPADC_ADAPTER + #define dg_configGPADC_ADAPTER (1) +#endif + +/* + * \brief Enable the RTC correction mechanism + * + * When RCX is set as the low power clock and Real Time Clock is used (i.e. dg_configUSE_HW_RTC is defined), + * setting this macro to 1 enables the RTC correction mechanism. + */ +#if (BSP_CFG_LP_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_RCX && defined(OS_FREERTOS) && dg_configUSE_HW_RTC) + #ifndef dg_configRTC_CORRECTION + #define dg_configRTC_CORRECTION (1) + #endif +#else + #if dg_configRTC_CORRECTION + #pragma \ + message "dg_configRTC_CORRECTION is only used in RTOS based projects when RCX is set as low power clock. Forcing to 0." + #undef dg_configRTC_CORRECTION + #define dg_configRTC_CORRECTION (0) + #endif +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +#endif /* MIDDLEWARE_DEFAULTS_H_ */ + +/** + \} + \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/partition_table.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/partition_table.h new file mode 100644 index 000000000000..7007fddd7bb7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/config/partition_table.h @@ -0,0 +1,89 @@ +/** + **************************************************************************************** + * + * @file ra6w1/config/partition_table.h + * + * @brief Partition table selection. Image partition's size definition. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +/* + * When partition_table is not overridden by adding a custom partition_table.h file to a project + * then this file is used to select partition table by macro definition. + * + * To use layout other than SDK one, add include path into the project settings that will point + * to a folder with the custom partition_table file. + */ + +#if ((DEVICE_FAMILY == DA1640X)) + + #if defined(RENESAS_AT25SL_8MB_OTA) + #include "8MB/at25sl/suota/partition_table.h" + #elif defined(RENESAS_AT25SL_8MB) + #include "8MB/at25sl/partition_table.h" + #elif defined(NORMAL_4MB_OTA) + #include "4MB/suota/partition_table.h" + #elif defined(NORMAL_4MB) + #include "4MB/partition_table.h" + #elif defined(NORMAL_8MB_OTA) + #include "8MB/suota/partition_table.h" + #elif defined(NORMAL_8MB) + #include "8MB/partition_table.h" + #else + #if defined OS_BAREMETAL + #include "4MB/default_partition_table.h" + #else + #error "Not defined SFLASH partition !!!" + #endif + #endif + +#else + + #include "4MB/partition_table.h" // Temporary ... for FPGA + +#endif /* DEVICE_FAMILY */ + +/* + * Define a maximal size of the image which could be written to QSPI - based on the partition sizes. + */ + +#if defined(NVMS_FW_EXEC_PART_SIZE) && defined(NVMS_FW_UPDATE_PART_SIZE) // for dual image by OTA + + #if (NVMS_FW_EXEC_PART_SIZE < NVMS_FW_UPDATE_PART_SIZE) + #define IMAGE_PARTITION_SIZE NVMS_FW_EXEC_PART_SIZE + #else + #define IMAGE_PARTITION_SIZE NVMS_FW_UPDATE_PART_SIZE + #endif /* NVMS_FW_EXEC_PART_SIZE < NVMS_FW_UPDATE_PART_SIZE */ + +#elif defined(NVMS_FIRMWARE_PART_SIZE) // for single image + + #define IMAGE_PARTITION_SIZE NVMS_FIRMWARE_PART_SIZE + +#else + #error "At least one partition where application could be placed should be defined!" +#endif /* defined(NVMS_FW_EXEC_PART_SIZE) && defined(NVMS_FW_UPDATE_PART_SIZE) */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/hw_sys.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/hw_sys.h new file mode 100644 index 000000000000..d09f0427a3c1 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/hw_sys.h @@ -0,0 +1,473 @@ +/** + * \addtogroup PLA_DRI_PER_ANALOG + \{ + * \addtogroup HW_SYS System Hardware Driver + \{ + * \brief System Driver + */ + +/** + **************************************************************************************** + * + * @file hw_sys.h + * + * @brief System Driver header file. + * + * Copyright (C) 2017-2020 Dialog Semiconductor. + * This computer program includes Confidential, Proprietary Information + * of Dialog Semiconductor. All Rights Reserved. + * + **************************************************************************************** + */ + +#ifndef HW_SYS_H_ +#define HW_SYS_H_ + +#include "sdk_defs.h" + +typedef enum +{ + HW_SYS_REMAP_ADDRESS_0_TO_ROM, + HW_SYS_REMAP_ADDRESS_0_TO_OTP, + HW_SYS_REMAP_ADDRESS_0_TO_QSPI_FLASH, + HW_SYS_REMAP_ADDRESS_0_TO_RAM, + + /* XXX Values for test/debugging purposes are omitted */ +} HW_SYS_REMAP_ADDRESS_0; + +static inline HW_SYS_REMAP_ADDRESS_0 hw_sys_get_memory_remapping (void) +{ + HW_SYS_REMAP_ADDRESS_0 value; + GLOBAL_INT_DISABLE(); + value = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); + GLOBAL_INT_RESTORE(); + + return value; +} + +#if (DEVICE_FAMILY == DA1468X) || ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #if dg_configUSE_HW_SYS + + #include "sdk_defs.h" + #include "hw_pd.h" + + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + #include + +/* \brief Specifies the HW BSR mask used for accessing the SW BSR */ + #define SW_BSR_HW_BSR_MASK (0x3) + +/* + * \brief Enumerations used when accessing the HW BSR register + */ +typedef enum +{ + HW_BSR_MASTER_NONE = 0, + HW_BSR_MASTER_SNC = 1, + HW_BSR_MASTER_SYSCPU = 2, + HW_BSR_MASTER_CMAC = 3, + HW_BSR_MASTER_NUM, +} HW_BSR_MASTER_ID; + +/* + * \brief HW BSR position + */ +typedef enum +{ + HW_BSR_SW_POS = 0, + HW_BSR_PLL_ENABLE_POS = 2, + HW_BSR_POWER_CTRL_POS = 28, + HW_BSR_WAKEUP_CONFIG_POS = 30, +} HW_BSR_POS; + +/* + * \brief Enumerations used when accessing the SW BSR variable + */ +typedef enum +{ + SW_BSR_MASTER_NONE = 1 << HW_BSR_MASTER_NONE, + SW_BSR_MASTER_SNC = 1 << HW_BSR_MASTER_SNC, + SW_BSR_MASTER_SYSCPU = 1 << HW_BSR_MASTER_SYSCPU, + SW_BSR_MASTER_CMAC = 1 << HW_BSR_MASTER_CMAC, +} SW_BSR_MASTER_ID; + +typedef enum +{ + BSR_PERIPH_ID_SNC = 0, + BSR_PERIPH_ID_SPI1 = 1, + BSR_PERIPH_ID_SPI2 = 2, + BSR_PERIPH_ID_UART1 = 3, + BSR_PERIPH_ID_UART2 = 4, + BSR_PERIPH_ID_UART3 = 5, + BSR_PERIPH_ID_I2C1 = 6, + BSR_PERIPH_ID_I2C2 = 7, + BSR_PERIPH_ID_MOTOR = 8, + BSR_PERIPH_ID_GPADC = 9, + BSR_PERIPH_ID_SDADC = 10, + BSR_PERIPH_ID_MAX = 16, +} HW_SYS_BSR_PERIPH_ID; + +/** + * \brief Register configuration + * + */ +typedef struct +{ + __IO uint32_t * addr; //!< Register address + uint32_t value; //!< Register value +} hw_sys_reg_config_t; + +/* + * Export hw_sys_sw_bsr so that other masters have access to its address. + */ +extern __RETAINED uint32_t hw_sys_sw_bsr[BSR_PERIPH_ID_MAX]; + + #endif /* DA1469X */ + +__STATIC_INLINE void hw_sys_set_memory_remapping (HW_SYS_REMAP_ADDRESS_0 value) +{ + GLOBAL_INT_DISABLE(); + REG_SETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0, value); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Enable Cache retainability. + * + */ +__STATIC_INLINE void hw_sys_set_cache_retained (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE); + GLOBAL_INT_RESTORE(); +} + + #if (DEVICE_FAMILY == DA1468X) + +/** + * \brief Enable ECC microcode RAM retainment. + * + */ +__STATIC_INLINE void hw_sys_set_eccram_retained (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM); + GLOBAL_INT_RESTORE(); +} + + #endif /* DEVICE_FAMILY */ + +/** + * \brief Setup the Retention Memory configuration. + * + */ +__STATIC_INLINE void hw_sys_setup_retmem (void) +{ + GLOBAL_INT_DISABLE(); + + #if (DEVICE_FAMILY == DA1468X) + REG_SETF(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM, dg_configMEM_RETENTION_MODE); + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + CRG_TOP->RAM_PWR_CTRL_REG = dg_configMEM_RETENTION_MODE; + #endif /* DEVICE_FAMILY */ + + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Disable memory retention. + * + */ +__STATIC_INLINE void hw_sys_no_retmem (void) +{ + GLOBAL_INT_DISABLE(); + #if (DEVICE_FAMILY == DA1468X) + CRG_TOP->PMU_CTRL_REG &= ~(REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM) | + REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE) | + REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM)); + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE); + CRG_TOP->RAM_PWR_CTRL_REG = 0x5555; + #endif /* DEVICE_FAMILY */ + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Prepare RESET type tracking. + */ +__STATIC_FORCEINLINE void hw_sys_track_reset_type (void) +{ + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) || ((DEVICE_FAMILY == DA1468X) && \ + (DEVICE_REVISION == DEVICE_REV_B)) + CRG_TOP->RESET_STAT_REG = 0; + #endif +} + +/** + * \brief Enable the clock-less sleep mode. + * + */ +__STATIC_INLINE void hw_sys_enable_clockless (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_DEEPSLP, DEEP_SLEEP_CTRL_REG, CLKLESS_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Disable the clock-less sleep mode. + * + */ +__STATIC_INLINE void hw_sys_disable_clockless (void) +{ + GLOBAL_INT_DISABLE(); + REG_CLR_BIT(CRG_DEEPSLP, DEEP_SLEEP_CTRL_REG, CLKLESS_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Activate the "Reset on wake-up" functionality. + * + */ +__STATIC_INLINE void hw_sys_enable_reset_on_wup (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RESET_ON_WAKEUP); + GLOBAL_INT_RESTORE(); +} + + #if (DEVICE_FAMILY == DA1468X) + +/** + * \brief Set (part of) the preferred settings. + * + */ +void hw_sys_set_preferred_values(void); + + #elif ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + +/** + * \brief Set the preferred settings of a power domain. + * + * \param [in] pd power domain + */ +void hw_sys_set_preferred_values(HW_PD pd); + + #endif + +/** + * \brief Set the GPIO used for the SW cursor to High-Z. + * + */ +void hw_sys_setup_sw_cursor(void); + +/** + * \brief Triggers the GPIO used for the SW cursor. + * + */ +void hw_sys_trigger_sw_cursor(void); + +/** + * \brief Enable the debugger. + * + */ +__STATIC_FORCEINLINE void hw_sys_enable_debugger (void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Disable the debugger. + * + */ +__STATIC_FORCEINLINE void hw_sys_disable_debugger (void) +{ + GLOBAL_INT_DISABLE(); + REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); + GLOBAL_INT_RESTORE(); +} + +/** + * \brief Check if the debugger is attached. + * + * \return true, if the debugger is attached, else false. + * + */ +__STATIC_FORCEINLINE bool hw_sys_is_debugger_attached (void) +{ + return REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE) != 0; +} + +/** + * \brief Trigger a GPIO when ASSERT_WARNING() or ASSERT_ERROR() hits. + * + */ +__RETAINED_CODE void hw_sys_assert_trigger_gpio(void); + + #if ((DEVICE_FAMILY == DA1469X) || (DEVICE_FAMILY == DA1487X)) + +/** + * \brief Try to lock a BSR entry + * + * \param [in] sw_bsr_master_id The SW BSR ID of the relevant master + * \param [in] pos The position of the entry in BSR. Valid positions are provided in HW_BSR_POS. + * + * \return true if the BSR entry has been acquired, else false. + * + */ +bool hw_sys_hw_bsr_try_lock(HW_BSR_MASTER_ID hw_bsr_master_id, HW_BSR_POS pos); + +/** + * \brief Unlock a BSR entry + * + * \param [in] sw_bsr_master_id The SW BSR ID of the relevant master + * \param [in] pos The position of the entry in BSR. Valid positions are provided in HW_BSR_POS. + * + */ +void hw_sys_hw_bsr_unlock(HW_BSR_MASTER_ID hw_bsr_master_id, HW_BSR_POS pos); + +/** + * \brief Initializes the software busy status register. + */ +void hw_sys_sw_bsr_init(void); + +/** + * \brief Tries to acquire exclusive access to a specific peripheral when + * it is also used by other masters (SNC or CMAC). + * + * \param [in] sw_bsr_master_id The SW BSR ID of the relevant master + * \param [in] periph_id The peripheral id for which exclusive access must be granted. + * Valid range is (0 - BSR_PERIPH_ID_MAX). Check HW_SYS_BSR_PERIPH_ID. + * + * \return true if peripheral exclusive access has been acquired, else false. + */ +bool hw_sys_sw_bsr_try_acquire(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id); + +/** + * \brief Checks if exclusive access to a specific peripheral has been acquired + * from a given master. + * + * \param [in] sw_bsr_master_id The SW BSR ID of the relevant master + * \param [in] periph_id The peripheral id for which exclusive access will be checked. + * Valid range is (0 - BSR_PERIPH_ID_MAX). Check HW_SYS_BSR_PERIPH_ID. + * \return true if peripheral exclusive access has been acquired from the specific master, else false. + */ +bool hw_sys_sw_bsr_acquired(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id); + +/** + * \brief Releases the exclusive access from a specific peripheral so it + * it can be also used by other masters (SNC or CMAC). + * + * \param [in] sw_bsr_master_id The SW BSR ID of the relevant master + * \param [in] periph_id The peripheral id for which exclusive access must be released. + * Valid range is (0 - BSR_PERIPH_ID_MAX). Check HW_SYS_BSR_PERIPH_ID. + */ +void hw_sys_sw_bsr_release(SW_BSR_MASTER_ID sw_bsr_master_id, uint32_t periph_id); + +/** + * \brief Enables the COM power domain. + * + */ +void hw_sys_pd_com_enable(void); + +/** + * \brief Disables the COM power domain. If it has not + * been enabled by any other modules, it will be disabled. + */ +void hw_sys_pd_com_disable(void); + +/** + * \brief Enables the PERIPH power domain. + * + */ +void hw_sys_pd_periph_enable(void); + +/** + * \brief Disables the PERIPH power domain. If it has not + * been enabled by any other modules, it will be disabled. + */ +void hw_sys_pd_periph_disable(void); + +/** + * \brief Add register configuration entries in the system register configuration table + * + * \param [in] config pointer to the structure containing the register configuration + * \param [in] num_of_entries the number of entries in the register configuration structure + * + * \return the index of the first entry in the configuration table + */ +uint32_t hw_sys_reg_add_config(hw_sys_reg_config_t * config, uint32_t num_of_entries); + +/** + * \brief Get a register configuration entry + * + * \param [in] index the index of the entry in the register configuration table + * + * \return a pointer to the register configuration entry + */ +hw_sys_reg_config_t * hw_sys_reg_get_config(uint32_t index); + +/** + * \brief Modify a register configuration entry + * + * \param [in] index the index of the entry in the register configuration table + * \param [in] addr the new register address + * \param [in] value the new register value + */ +void hw_sys_reg_modify_config(uint32_t index, __IO uint32_t * addr, uint32_t value); + +/** + * \brief Get the number of entries in the system register configuration table + * + * \return a pointer to the number of entries + */ +uint32_t * hw_sys_reg_get_num_of_config_entries(void); + +/** + * \brief Apply system register configuration + * + * Configure non-retained system registers using the entries in the system register + * configuration table. + */ +__RETAINED_CODE void hw_sys_reg_apply_config(void); + +/** + * \brief Checks whether there are register entries in CS for the following registers + * - CLK_FREQ_TRIM_REG + * - XTAL32M_CTRL0_REG + * If any of the above is missing, the function applies the default values + * for specific fields + * - CLK_FREQ_TRIM_REG: XTAL32M_TRIM + * - XTAL32M_CTRL0_REG: XTAL32M_CXCOMP_ENABLE + */ +void hw_sys_apply_default_values(void); + + #if !DEVICE_FPGA + +/** + * \brief Calculates the PLL_MIN_CURRENT value needed for tuning the PLL lock time + * + * \note This function has to be called only once during startup. + */ +void hw_sys_pll_calculate_min_current(void); + +/** + * \brief Sets the PLL_MIN_CURRENT value needed for tuning the PLL lock time + * + * \note This function should be called every time the timers power domain powers off and on. + */ +void hw_sys_pll_set_min_current(void); + + #endif /* !DEVICE_FPGA */ + #endif /* DA1469X */ + + #endif /* dg_configUSE_HW_SYS */ +#endif /* DEVICE_FAMILY */ +#endif /* HW_SYS_H_ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/iface_defs.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/iface_defs.h new file mode 100644 index 000000000000..4c94bdde495a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/iface_defs.h @@ -0,0 +1,167 @@ +/** + **************************************************************************************** + * + * @file iface_defs.h + * + * @brief Featrue define + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __IFACE_DEFS_H__ +#define __IFACE_DEFS_H__ + +/* + * Interface definitions + */ + +/* NVRAM KEYWORD START */ + +#define NETMODE "NETMODE" +#define NETMODE_WIFI_PROFILE "netmode" + +#define WIFI_PROFILE_DNSSVR_0 "dns_0" +#define WIFI_PROFILE_DNSSVR_1 "dns_1" +#define WIFI_PROFILE_DNSSVR_2ND_0 "dns_2nd_0" +#define WIFI_PROFILE_DNSSVR_2ND_1 "dns_2nd_1" +#define STATIC_IP_ADDRESS "ipaddress" +#define STATIC_IP_NETMASK "subnetmask" +#define STATIC_IP_GATEWAY "gateway" +#define STATIC_IPV6_ADDRESS "IPV6ADDR" + +/* DHCP Server */ +#define DHCP_SERVER_START_IP "1:DHCPD_S_IP" +#define DHCP_SERVER_END_IP "1:DHCPD_E_IP" +#define DHCP_SERVER_LEASE_TIME "1:DHCPD_TIME" +#define DHCP_SERVER_DNS "1:DHCPD_DNS" +#define DHCP_SERVER_RESPONSE_DELAY "1:DHCPD_RESP_DELAY" + +#define DHCPV6_SERVER_START_IP "DHCPV6D_S_IP" +#define DHCPV6_SERVER_END_IP "DHCPV6D_E_IP" +#define DHCPV6_SERVER_DNS "DHCPV6D_DNS" +#define DHCPV6_SERVER_LEASE_TIME "DHCPV6D_TIME" + +#define ENV_SYS_MODE "SYSMODE" +#define ENV_SWITCH_SYSMODE "SWITCH_SYSMODE" +#define ENV_KEY_TEMP_STATIC_IP "0:TEMP_STATIC_IP" // Temporarily use a static IPaddress. + +/* NVRAM KEYWORD END */ + +/* NETWORK Define */ +#define NETMODE_DHCPCLIENT "dhcp" +#define IPADDR_LEN 16 +#define IP6ADDR_LEN 40 +#define DHCPCLIENT 1 +#define STATIC_IP 2 + +#define WLAN0_IFACE 0 +#define WLAN1_IFACE 1 +#define ETH0_IFACE 2 +#define NONE_IFACE 9 + +#define IFACE_UP 1 +#define IFACE_DOWN 0 + +#define GET_MACADDR 0 +#define GET_IPADDR 1 +#define GET_SUBNET 2 +#define GET_GATEWAY 3 +#define GET_MTU 4 +#define GET_DNS 5 +#define GET_DNS_2ND 6 +#define GET_IPV6 7 + +/* #################################################### */ + +enum dhcp_client_state +{ + DHCP_CLIENT_CREATE, + DHCP_CLIENT_INFO, + DHCP_CLIENT_STOP, + DHCP_CLIENT_START, + DHCP_CLIENT_FORCING_RENEW, + DHCP_CLIENT_RELEASE, + DHCP_CLIENT_STATUS /* add by sj.lee 21060721 */ +}; + +enum dhcp_server_state +{ + DHCP_SERVER_STATE_STATUS, + DHCP_SERVER_STATE_START, + DHCP_SERVER_STATE_STOP, + DHCP_SERVER_STATE_RANGE, + DHCP_SERVER_STATE_LEASE_TIME, + DHCP_SERVER_STATE_LEASE_TABLE, + DHCP_SERVER_STATE_DNS, + DHCP_SERVER_STATE_RESPONSE_DELAY, + DHCP_SERVER_STATE_DEBUG, + DHCP_SERVER_STATE_HELP, + DHCP_SERVER_STATE_STATUS_AT /* add by sj.lee for AT_CMD */ +}; + +enum network_state +{ + P2P_NET_GO, + P2P_NET_CLIENT, + P2P_NET_DEVICE, + INF_NET_STATION +}; + +/* DEFALUT VALUE */ +/* HTTP Server */ +#define DEFAULT_HTTP_SERVER_PORT 80 + +#define DEFAULT_IPADDR_WLAN0 "172.16.0.100" +#define DEFAULT_SUBNET_WLAN0 "255.255.255.0" +#define DEFAULT_GATEWAY_WLAN0 "172.16.0.1" +#define DEFAULT_DNS_WLAN0 "8.8.8.8" /* Google DNS */ +#define DEFAULT_DNS_2ND "208.67.222.222" /* OpenDNS */ + +#define DEFAULT_IPADDR_WLAN1 "10.0.0.1" +#define DEFAULT_SUBNET_WLAN1 "255.255.255.0" +#define DEFAULT_GATEWAY_WLAN1 "10.0.0.1" +#define DEFAULT_DNS_WLAN1 "8.8.8.8" /* Google DNS */ + +#define DEFAULT_NETMODE_WLAN0 DHCPCLIENT +#define DEFAULT_NETMODE_WLAN1 STATIC_IP + +/* DHCP Server */ +#define MAX_DHCP_LEASE_COUNT 10 +#define DEFAULT_DHCP_LEASE_COUNT 10 +#define MAX_DHCP_SERVER_LEASE_TIME 3600 * 24 +#define MIN_DHCP_SERVER_LEASE_TIME 60 +#define DEFAULT_DHCP_SERVER_LEASE_TIME 1800 + +#define P2P_GO_IP_ADDR "192.168.20.1" +#define P2P_GO_NETMASK "255.255.255.0" +#define P2P_GO_IP_DHCP_START "192.168.20.2" +#define P2P_GO_IP_DHCP_END "192.168.20.11" +#define P2P_GO_DNS_IP "8.8.8.8" + +#define IPADDR_ANY_STR "0.0.0.0" + +#endif /* __IFACE_DEFS_H__ */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/interrupts.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/interrupts.h new file mode 100644 index 000000000000..e638f0290549 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/interrupts.h @@ -0,0 +1,154 @@ +/** + * \addtogroup PLA_BSP_SYSTEM + * \{ + * \addtogroup BSP_INTERRUPTS Interrupts + * + * \brief Interrupt priority configuration + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file ra6w1/interrupts.h + * + * @brief Interrupt priority configuration + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef INTERRUPTS_H_ + #define INTERRUPTS_H_ + + #include + + #ifdef __cplusplus +extern "C" { + #endif + +/** + * \brief Setup interrupt priorities + * + * When CPU is reset all interrupts have some priority setup. + * Reset -3 + * NMI -2 + * HardFault -1 + * All other interrupts have configurable priority that is set to 0. + * If some interrupts should have priority other then default, this function should be called. + * Argument \p prios can specify only those interrupts that need to have value other than default. + * For memory efficiency table with priorities for each interrupt consist of interrupt priority + * tag PRIORITY_x followed by interrupts that should have this priority, interrupts names are from + * enum IRQn_Type. + * + * \note If interrupt priorities do not need to be changed dynamically at runtime, best way to + * specify static configuration is to create table named __dialog_interrupt_priorities that will + * be used automatically at startup. + * + * Most convenient way to prepare such table is to use macros like in example below: + * + * \code{.c} + * INTERRUPT_PRIORITY_CONFIG_START(__dialog_interrupt_priorities) + * PRIORITY_0, // Start interrupts with priority 0 (highest) + * SVCall_IRQn, + * PendSV_IRQn, + * SysTick_IRQn, + * PRIORITY_1, // Start interrupts with priority 1 + * BLE_WAKEUP_LP_IRQn, + * BLE_GEN_IRQn, + * FTDF_WAKEUP_IRQn, + * FTDF_GEN_IRQn, + * PRIORITY_2, + * SRC_IN_IRQn, + * SRC_OUT_IRQn, + * PRIORITY_3, + * UART_IRQn, + * UART2_IRQn, + * INTERRUPT_PRIORITY_CONFIG_END + * \endcode + * + * Table __dialog_interrupt_priorities can now be used to call this function. + * Table can specify all interrupts or only those that need to be changed. + * + * \param [in] prios table with interrupts and priorities to setup + * + */ +void set_interrupt_priorities(const int8_t prios[]); + +/** + * \brief Check whether running in interrupt context. + * + * \return true if the CPU is serving an interrupt. + */ +__STATIC_INLINE bool in_interrupt (void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; +} + +/** + * \brief Default interrupt priorities table. + * + */ +extern const int8_t __dialog_interrupt_priorities[]; + + #define LAST_IRQn (96) // WIFI_RC_IRQn + +/* + * Following macros allow easy way to build table with interrupt priorities. + * See example in set_interrupt_priorities function description. + */ + +/* UNCRUSTIFY-OFF */ +#define INTERRUPT_PRIORITY_CONFIG_START(name) const int8_t name[] = { +/* UNCRUSTIFY-ON */ + #define PRIORITY_0 (LAST_IRQn + 1) + #define PRIORITY_1 (LAST_IRQn + 2) + #define PRIORITY_2 (LAST_IRQn + 3) + #define PRIORITY_3 (LAST_IRQn + 4) + #define PRIORITY_4 (LAST_IRQn + 5) + #define PRIORITY_5 (LAST_IRQn + 6) + #define PRIORITY_6 (LAST_IRQn + 7) + #define PRIORITY_7 (LAST_IRQn + 8) + #define PRIORITY_8 (LAST_IRQn + 9) + #define PRIORITY_9 (LAST_IRQn + 10) + #define PRIORITY_10 (LAST_IRQn + 11) + #define PRIORITY_11 (LAST_IRQn + 12) + #define PRIORITY_12 (LAST_IRQn + 13) + #define PRIORITY_13 (LAST_IRQn + 14) + #define PRIORITY_14 (LAST_IRQn + 15) + #define PRIORITY_15 (LAST_IRQn + 16) + #define PRIORITY_TABLE_END (LAST_IRQn + 17) + #define INTERRUPT_PRIORITY_CONFIG_END PRIORITY_TABLE_END}; + + #ifdef __cplusplus +} + #endif + +#endif /* INTERRUPTS_H_ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/osal/osal.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/osal/osal.h new file mode 100644 index 000000000000..682d2f8cd62c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/osal/osal.h @@ -0,0 +1,1339 @@ +/** + * \addtogroup MID_RTO_OSAL + * + * \brief OS Abstraction Layer + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file osal.h + * + * @brief OS abstraction layer API + * + * Copyright (c) 2023-2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef OSAL_H_ +#define OSAL_H_ + +#include "FreeRTOS.h" + +#if defined(OS_FREERTOS) + + #include + #include + #include + #include + #ifdef RM_STDIO_W + #include "rm_stdio_w_cfg.h" + #endif + +/** + * \brief Check whether running in interrupt context. + * + * \return true if the CPU is serving an interrupt. + */ +__STATIC_INLINE bool in_interrupt (void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; +} + + #define OS_STACK_WORD_SIZE (sizeof(StackType_t)) + + #define OS_TASK TaskHandle_t + #define OS_TASK_STATUS TaskStatus_t + #define OS_TASK_CREATE_SUCCESS pdPASS + #define OS_TASK_NOTIFY_SUCCESS pdPASS + #define OS_TASK_NOTIFY_FAIL pdFALSE + #define OS_TASK_NOTIFY_NO_WAIT 0 + #define OS_TASK_NOTIFY_FOREVER portMAX_DELAY + #define OS_TASK_NOTIFY_ALL_BITS 0xFFFFFFFF + + #ifndef OS_TASK_PRIORITY_LOWEST + #define OS_TASK_PRIORITY_LOWEST tskIDLE_PRIORITY + #endif // OS_TASK_PRIORITY_LOWEST + #define OS_TASK_PRIORITY_NORMAL tskIDLE_PRIORITY + 1 + #define OS_TASK_PRIORITY_NORMAL_MAX (OS_TASK_PRIORITY_NORMAL + 9) // 10 + #ifndef OS_TASK_PRIORITY_HIGHEST + #define OS_TASK_PRIORITY_HIGHEST configMAX_PRIORITIES - 1 + #endif // OS_TASK_PRIORITY_HIGHEST + + #define OS_MUTEX SemaphoreHandle_t + #define OS_MUTEX_TAKEN pdTRUE + #define OS_MUTEX_NOT_TAKEN pdFALSE + #define OS_MUTEX_CREATE_SUCCESS 1 + #define OS_MUTEX_CREATE_FAILED 0 + #define OS_MUTEX_NO_WAIT 0 + #define OS_MUTEX_FOREVER portMAX_DELAY + + #define OS_EVENT SemaphoreHandle_t + #define OS_EVENT_CREATE_SUCCESS 1 + #define OS_EVENT_CREATE_FAILED 0 + #define OS_EVENT_SIGNALED pdTRUE + #define OS_EVENT_NOT_SIGNALED pdFALSE + #define OS_EVENT_NO_WAIT 0 + #define OS_EVENT_FOREVER portMAX_DELAY + + #define OS_EVENT_GROUP EventGroupHandle_t + #define OS_EVENT_GROUP_OK pdTRUE + #define OS_EVENT_GROUP_FAIL pdFALSE + #define OS_EVENT_GROUP_FOREVER portMAX_DELAY + + #define OS_QUEUE QueueHandle_t + #define OS_QUEUE_FULL errQUEUE_FULL + #define OS_QUEUE_EMPTY pdFALSE + #define OS_QUEUE_OK pdTRUE + #define OS_QUEUE_NO_WAIT 0 + #define OS_QUEUE_FOREVER portMAX_DELAY + + #define OS_TIMER TimerHandle_t + #define OS_TIMER_SUCCESS pdPASS + #define OS_TIMER_FAIL pdFAIL + #define OS_TIMER_FOREVER portMAX_DELAY + + #define OS_BASE_TYPE BaseType_t + #define OS_UBASE_TYPE UBaseType_t + + #define OS_OK pdPASS + #define OS_FAIL pdFAIL + + #define OS_TICK_TIME TickType_t + #define OS_PERIOD_MS portTICK_PERIOD_MS + + #define OS_ASSERT configASSERT + +/** + * \brief OS Notification action + */ +typedef enum +{ + OS_NOTIFY_NO_ACTION = eNoAction, /**< subject task receives event, but its notification value is not updated */ + OS_NOTIFY_SET_BITS = eSetBits, /**< notification value of subject task will be bitwise ORed with task value */ + OS_NOTIFY_INCREMENT = eIncrement, /**< notification value of subject task will be incremented by one */ + OS_NOTIFY_VAL_WITH_OVERWRITE = eSetValueWithOverwrite, /**< notification value of subject task is unconditionally set to task value */ + OS_NOTIFY_VAL_WITHOUT_OVERWRITE = eSetValueWithoutOverwrite, /**< if subject task has a notification pending then notification value + * will be set to task value otherwise task value is not updated */ +} OS_NOTIFY_ACTION; + +/** + * \brief OS Task state + */ +typedef enum +{ + OS_TASK_RUNNING = eRunning, /**< Task is in running state, a task is querying the state of itself */ + OS_TASK_READY = eReady, /**< Task is in a ready state */ + OS_TASK_BLOCKED = eBlocked, /**< Task is in blocked state */ + OS_TASK_SUSPENDED = eSuspended, /**< Task is in the suspended state, or is in the blocked state with an infinite time out */ + OS_TASK_DELETED = eDeleted, /**< Task is deleted, but its TCB has not yet been freed */ +} OS_TASK_STATE; + +/** + * \brief Converts a time in milliseconds to a time in ticks + * + * \param [in] time_in_ms time in milliseconds + * + * \return time in ticks + * + */ + #define OS_TIME_TO_TICKS(time_in_ms) portCONVERT_MS_2_TICKS(time_in_ms) + +/** + * \brief Return current OS task handle + * + * \return current task handle of type OS_TASK + * + */ + #define OS_GET_CURRENT_TASK() xTaskGetCurrentTaskHandle() + +/** + * \brief Create OS task + * + * Function creates OS task. Task is added to ready list. + * + * \param [in] name task name + * \param [in] task_func starting point of task + * \param [in] arg parameter past to \p task_func on task start + * \param [in] stack_size stack size allocated for task in bytes + * \param [in] priority number specifying task priority + * \param [in,out] task OS specific task handle + * + * \return OS_TASK_CREATE_SUCCESS if task was created successfully + * + */ + #if (dg_configSYSTEMVIEW == 0) + #define OS_TASK_CREATE(name, task_func, arg, stack_size, priority, task) \ + xTaskCreate((task_func), (name), (((stack_size) - 1) / sizeof(StackType_t) + 1), (arg), (priority), &(task)) + #else + #define OS_TASK_CREATE(name, task_func, arg, stack_size, priority, task) \ + xTaskCreate((task_func), \ + (name), \ + (((stack_size + dg_configSYSTEMVIEW_STACK_OVERHEAD) - 1) / sizeof(StackType_t) + 1), \ + (arg), \ + (priority), \ + &(task)) + #endif /* (dg_configSYSTEMVIEW == 1) */ + +/** + * \brief Delete OS task + * + * Function deletes OS task. + * + * \param [in,out] task OS specific task handle + * + */ + #define OS_TASK_DELETE(task) vTaskDelete(task) + +/** + * \brief Get the priority of an OS task + * + * Function returns the priority of an OS task. + * + * \param [in] task OS specific task handle. if NULL, the running task is assummed. + * + * \return the priority of the task (OS_UBASE_TYPE) + * + */ + #define OS_TASK_PRIORITY_GET(task) uxTaskPriorityGet(task) + +/** + * \brief Set the priority of an OS task + * + * Function sets the priority of an OS task. + * + * \param [in] task OS specific task handle + * \param [in] prio OS new priority + * + */ + #define OS_TASK_PRIORITY_SET(task, prio) vTaskPrioritySet(task, prio) + +/** + * \brief The running OS task yields control to the scheduler + * + * Function requests a context switch to another task. + * + */ + #define OS_TASK_YIELD() portYIELD() + +/** + * \brief Send an event directly to task + * + * Must not be called from ISR! + * + * \param [in] task id of task to notify + * \param [in] value used to update the notification value of the subject \p task + * \param [in] action action that performs when notify is occurred + * + * \return OS_TASK_NOTIFY_FAIL if \p action is set as OS_NOTIFY_VAL_WITHOUT_OVERWRITE and \p task + * already had a notification pending, OS_TASK_NOTIFY_SUCCESS otherwise + * + */ + #define OS_TASK_NOTIFY(task, value, action) xTaskNotify((task), (value), (action)) + +/** + * \brief Notify OS task sending an event and return previous notification value + * + * Must not be called from ISR! + * + * \param [in] task id of task to notify + * \param [in] value used to update the notification value of the subject \p task + * \param [in] action action that performs when notify is occurred + * \param [out] prev_value pointer to previous notification value - optional - can be set to NULL + * + * \return OS_TASK_NOTIFY_FAIL if \p action is set as OS_NOTIFY_VAL_WITHOUT_OVERWRITE and \p task + * already had a notification pending, OS_TASK_NOTIFY_SUCCESS otherwise + * + */ + #define OS_TASK_NOTIFY_AND_QUERY(task, value, action, prev_value) xTaskNotifyAndQuery((task), (value), (action), \ + (prev_value)) + +/** + * \brief Send an event and unblock OS task with updating notification value + * + * A version of OS_TASK_NOTIFY that can be called from ISR. + * + * \param [in] task id of task to notify + * \param [in] value used to update the notification value of the subject \p task + * \param [in] action action that performs when notify is occurred + * + * \return OS_TASK_NOTIFY_FAIL if \p action is set as OS_NOTIFY_VAL_WITHOUT_OVERWRITE and \p task + * already had a notification pending, OS_TASK_NOTIFY_SUCCESS otherwise + * + */ + #define OS_TASK_NOTIFY_FROM_ISR(task, value, action) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTaskNotifyFromISR(task, value, action, &need_switch); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Notify task and receive OS task notification value + * + * Must not called from ISR! Use OS_TASK_NOTIFY_GIVE_FROM_ISR instead. + * + * \param [in] task id of task to notify + * + * \return OS_TASK_NOTIFY_GIVE calls OS_TASK_NOTIFY with action set to OS_NOTIFY_INCREMENT resulting + * in all calls returning OS_TASK_NOTIFY_SUCCESS + * + */ + #define OS_TASK_NOTIFY_GIVE(task) xTaskNotifyGive(task) + +/** + * \brief Notify task from ISR + * + * Send notification from interrupt service routine (ISR) to \p task that can unblock the receiving + * task and optionally update the receiving task's notification value. + * This function is safe to call from ISR. + * + * \param [in] task id of task to notify + * + */ + #define OS_TASK_NOTIFY_GIVE_FROM_ISR(task) \ + ({ \ + BaseType_t need_switch; \ + vTaskNotifyGiveFromISR(task, &need_switch); \ + portEND_SWITCHING_ISR(need_switch); \ + }) + +/** + * \brief Clear to zero or decrement task notification value on exit + * + * \param [in] clear_on_exit = pdFASLE: RTOS task's notification value is decremented before + * OS_TASK_NOTIFY_TAKE() exits, + * pdTRUE: the RTOS task's notification value is reset to 0 before + * OS_TASK_NOTIFY_TAKE() exits. + * \param [in] time_to_wait maximum time to wait in the blocked state for a notification to be + * received if a notification is not already pending when + * OS_TASK_NOTIFY_TAKE() is called + * + * \return the value of the task's notification value before it is decremented or cleared + * + */ + #define OS_TASK_NOTIFY_TAKE(clear_on_exit, time_to_wait) ulTaskNotifyTake((clear_on_exit), (time_to_wait)) + +/** + * \brief Wait for the calling task to receive a notification + * + * \param [in] entry_bits any bits set in entry_bits will be cleared in calling notification value + * before enters to OS_TASK_NOTIFY_WAIT + * \param [in] exit_bits any bits set in exit_bits will be cleared in calling notification value + * before OS_TASK_NOTIFY_WAIT function exits if a notification was received + * \param [out] value pointer to task's notification value, if not required can be set to NULL + * \param [in] ticks_to_wait maximum time to wait in the blocked state for a notification to be + * received if a notification is not already pending when + * OS_TASK_NOTIFY_WAIT is called + * + * \return OS_TASK_NOTIFY_SUCCESS if notification was received or was already pending when + * OS_TASK_NOTIFY_WAIT was called + * OS_TASK_NOTIFY_FAIL if the call OS_TASK_NOTIFY_WAIT timed out before notification was + * received + * + */ + #define OS_TASK_NOTIFY_WAIT(entry_bits, exit_bits, value, ticks_to_wait) \ + xTaskNotifyWait((entry_bits), (exit_bits), (value), (ticks_to_wait)) + +/** + * \brief Resume task + * + * Make \p task ready to run. + * + * \param [in] task id of task to resume + * + */ + #define OS_TASK_RESUME(task) vTaskResume(task) + +/** + * \brief Resume task + * + * Make \p task ready to run. This function is safe to call from ISR. + * + * \param [in] task id of task to resume + * + */ + #define OS_TASK_RESUME_FROM_ISR(task) xTaskResumeFromISR(task) + +/** + * \brief Suspend task + * + * Remove \p task from execution queue. Task will not be run + * until OS_TASK_RESUME or OS_TASK_RESUME_FROM_ISR is called. + * + * \param [in] task id of task to suspend + * + */ + #define OS_TASK_SUSPEND(task) vTaskSuspend(task) + +/** + * \brief Suspend task + * + * Remove \p task from execution queue. Task will not be run + * until OS_TASK_RESUME or OS_TASK_RESUME_FROM_ISR is called. + * This function is safe to call from ISR. + * + * \param [in] task id of task to suspend + * + */ + #define OS_TASK_SUSPEND_FROM_ISR(task) vTaskSuspendFromISR(task) + +/** + * \brief Create OS mutex + * + * Function creates OS mutex. + * + * \param [in,out] mutex + * + * \return OS_MUTEX_CREATE_SUCCESS when mutex was created successfully, OS_MUTEX_CREATE_FAILED + * otherwise + */ + #define OS_MUTEX_CREATE(mutex) \ + ({ \ + (mutex) = xSemaphoreCreateRecursiveMutex(); \ + mutex != NULL ? OS_MUTEX_CREATE_SUCCESS : OS_MUTEX_CREATE_FAILED; \ + }) + +/** + * \brief Delete OS mutex + * + * Function deletes OS mutex. + * + * \param [in] mutex + * + */ + #define OS_MUTEX_DELETE(mutex) vSemaphoreDelete(mutex) + +/** + * \brief Relase mutex + * + * Decrease mutex count, when numer of calls to OS_MUTEX_GET equals number of calls to + * OS_MUTEX_PUT, mutex can be acquired by other task. + * + * \param [in] mutex id of mutex to realse + * + */ + #define OS_MUTEX_PUT(mutex) xSemaphoreGiveRecursive(mutex) + +/** + * \brief Acquire mutex + * + * Access to shared resource can be guarded by mutex. When task wants to get access + * to this resource call OS_MUTEX_GET. If mutex was not taken by any task yet it, call + * will succeed and mutex will be assigned to calling task. Next call to already acquired + * mutex from same task will succeed. If mutex is already taken by other task calling + * task will wait for specified time before failing. + * For non-blocking acquire \p timeout can be OS_MUTEX_NO_WAIT, for infinite wait till + * mutex is released OS_MUTEX_FOREVER should be used. + * + * \param [in] mutex id of mutex to acquire + * \param [in] timeout number of ticks that to acquire mutex + * + */ + #define OS_MUTEX_GET(mutex, timeout) xSemaphoreTakeRecursive((mutex), (timeout)) + +/** + * \brief Create OS event + * + * Function creates OS event that can be used to synchronize. + * + * \param [in,out] event + * + */ + #define OS_EVENT_CREATE(event) do {(event) = xSemaphoreCreateBinary();} while (0) + +/** + * \brief Delete OS event + * + * Function destroys OS event. + * + * \param [in] event item to delete + * + */ + #define OS_EVENT_DELETE(event) vSemaphoreDelete(event) + +/** + * \brief Set event in signaled state + * + * Set event in signaled stated so OS_EVENT_WAIT will release waiting task if any. + * Event will remain in signaled stated till call to OS_EVENT_WAIT releases one task. + * This function should not be called from ISR. + * + * \param [in] event + * + */ + #define OS_EVENT_SIGNAL(event) xSemaphoreGive(event) + +/** + * \brief Set event in signaled state + * + * Set event in signaled stated so OS_EVENT_WAIT will release waiting task if any. + * Event will remain in signaled stated till call to OS_EVENT_WAIT releases one task. + * This function is safe to call from ISR. + * + * \param [in] event + * + */ + #define OS_EVENT_SIGNAL_FROM_ISR(event) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xSemaphoreGiveFromISR(event, &need_switch); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Wait for event + * + * This function wait for \p event to be in signaled stated. + * If event was already in signaled state or become signaled in specified time + * function will return OS_EVENT_SIGNALED. + * To check if event is already signaled use OS_EVENT_NO_WAIT as timeout. + * To wait till event is signaled use OS_EVENT_FOREVERE. + * This function can't be used in ISR. + * + * \param [in] event if of event to wait on + * \param [in] timeout number of ticks to wait + * + * \return OS_EVENT_SIGNALED if event was signaled other value if not + * + */ + #define OS_EVENT_WAIT(event, timeout) xSemaphoreTake((event), (timeout)) + +/** + * \brief Check if event is signaled without waiting + * + * This function will return immediately with OS_EVENT_SIGNALED if event + * was in signaled state already. In case the event is signaled, its state + * changes to not signaled after calling this function. + * + * \param [in] event if of event to wait on + * + * \return OS_EVENT_SIGNALED if event was signaled other value if not + * + */ + #define OS_EVENT_CHECK(event) xSemaphoreTake((event), OS_EVENT_NO_WAIT) + + #define OS_EVENT_YIELD(higherPriorityTaskWoken) portYIELD_FROM_ISR(higherPriorityTaskWoken) + +/** + * \brief Create OS event group + * + * Function creates OS event group + * + * \return event group handle if successful, otherwise NULL + * + */ + #define OS_EVENT_GROUP_CREATE() xEventGroupCreate() + +/** + * \brief Event group wait bits + * + * Function reads bits within event group optionally entering the Blocked state (with a timeout) + * to wait for a bit or group of bits to become set. + * + * \param [in] event_group the event group in which the bits are being tested + * \param [in] bits_to_wait a bitwise value to test inside the event group + * \param [in] clear_on_exit = OS_OK: any bits set in the value passed as the bits_to_wait + * parameter will be cleared in the event group before + * xEventGroupWaitBits returns + * OS_FAIL: bits in the event group are not altered when the call + * to xEventGroupWaitBits() returns + * \param [in] wait_for_all = OS_OK: xEventGroupWaitBits() will return when either *all* bits + * set in the value passed as the bits_to_wait parameter are set in + * the event group + * OS_FAIL: xEventGroupWaitBits() will return when *any* of the bits set + * in the value passed as the bits_to_wait parameter are set in the event + * group + * \param [in] timeout maximum amount of time to wait for one/all of the bits specified + * by bits_to_wait to become set + * + * \return the value of the event group at the time either the event bits being waited for + * became set, or the timeout expired + * + */ + #define OS_EVENT_GROUP_WAIT_BITS(event_group, bits_to_wait, clear_on_exit, wait_for_all, timeout) \ + xEventGroupWaitBits((event_group), (bits_to_wait), (clear_on_exit), (wait_for_all), (timeout)) + +/** + * \brief Event group set bits + * + * Set bits (flags) within an event group + * + * \param [in] event_group the event group in which the bits are to be set + * \param [in] bits_to_set a bitwise value that indicates the bit or bits to set in the event group + * + * \return the value of the event group at the time the call to xEventGroupSetBits() returns + * + */ + #define OS_EVENT_GROUP_SET_BITS(event_group, bits_to_set) xEventGroupSetBits((event_group), (bits_to_set)) + +/** + * \brief Set event group bits from ISR + * + * Set bits (flags) within an RTOS event group that can be called from an ISR. + * + * \param [in] event_group the event group in which the bits are to be set + * \param [in] bits_to_set a bitwise value that indicates the bit or bits to set in the event group + * + * \return if the message was sent to the RTOS daemon task then OS_OK is returned, + * otherwise OS_FAIL is returned + * + */ + #define OS_EVENT_GROUP_SET_BITS_FROM_ISR(event_group, bits_to_set) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xEventGroupSetBitsFromISR((event_group), (bits_to_set), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Clear event group bits + * + * Function clear bits (flags) within an event group. + * + * \param [in] event_group the event group in which the bits are to be cleared + * \param [in] bits_to_clear a bitwise value that indicates the bit or bits to clear + * in the event group + * + * \return value of the event group before the specified bits were cleared + * + */ + #define OS_EVENT_GROUP_CLEAR_BITS(event_group, bits_to_clear) xEventGroupClearBits((event_group), (bits_to_clear)) + +/** + * \brief Clear event group bits from an interrupt + * + * Function clear bits (flags) within an event group from an interrupt. + * + * \param [in] event_group the event group in which the bits are to be cleared + * \param [in] bits_to_clear a bitwise value that indicates the bit or bits to clear + * in the event group + * + * \return value of the event group before the specified bits were cleared + * + */ + #define OS_EVENT_GROUP_CLEAR_BITS_FROM_ISR(event_group, bits_to_clear) \ + xEventGroupClearBitsFromISR((event_group), (bits_to_clear)) + +/** + * \brief Get event group bits + * + * Function returns the current value of the event bits (event flags) in an event group. + * + * \param [in] event_group the event group being queried + * + * \return value of the event bits in the event group at the time + * OS_EVENT_GROUP_GET_BITS() was called + * + */ + #define OS_EVENT_GROUP_GET_BITS(event_group) xEventGroupGetBits(event_group) + +/** + * \brief Get event group bits from an interrupt + * + * Function returns the current value of the event bits (event flags) in an event group from an + * interrupt + * + * \param [in] event_group the event group being queried + * + * \return value of the event bits in the event group at the time OS_EVENT_GROUP_GET_BITS_FROM_ISR() + * was called + * + */ + #define OS_EVENT_GROUP_GET_BITS_FROM_ISR(event_group) xEventGroupGetBitsFromISR(event_group) + +/** + * \brief Synchronize event group bits + * + * Atomically set bits (flags) within an event group, then wait for a combination of bits to be + * set within the same event group. + * + * \param [in] event_group event group in which the bits are being set and tested + * \param [in] bits_to_set bit or bits to set in the event group before determining if all + * the bits specified by the bits_to_wait parameter are set + * \param [in] bits_to_wait a bitwise value that indicates the bit or bits to test inside + * the event group + * \param [in] timeout maximum amount of time (specified in 'ticks') to wait for all the bits + * specified by the bits_to_wait parameter value to become set + * + * \return value of the event group at the time either the bits being waited for became set, + * or the block time expired + * + */ + #define OS_EVENT_GROUP_SYNC(event_group, bits_to_set, bits_to_wait, timeout) \ + xEventGroupSync((event_group), (bits_to_set), (bits_to_wait), (timeout)) + +/** + * \brief Delete event group + * + * Function deletes an event group. + * + * \param [in] event_group the event group being deleted. + * + */ + #define OS_EVENT_GROUP_DELETE(event_group) vEventGroupDelete(event_group) + +/** + * \brief Create OS queue + * + * Function creates OS queue that can contain \p max_items of specified size. + * + * \param [in,out] queue queue to initialize + * \param [in] item_size queue element size + * \param [in] max_items max number of items that queue can store + * + */ + #define OS_QUEUE_CREATE(queue, item_size, max_items) \ + do {(queue) = xQueueCreate((max_items), (item_size));} while (0) + +/** + * \brief Deletes OS queue + * + * Function deletes OS. + * + * \param [in] queue queue to delete + * + */ + #define OS_QUEUE_DELETE(queue) vQueueDelete(queue) + +/** + * \brief Put element in queue + * + * Function adds element into queue if there is enough room for it. + * If there is no room in queue for \p timeout ticks element is not + * put in queue and error is returned. + * + * \param [in] queue id of queue to put item to + * \param [in] item pointer to element to enqueue + * \param [in] timeout max time in ticks to wait for space in queue + * + * \return OS_QUEUE_FULL if there was no place in queue + * OS_QUEUE_OK if message was put in queue + * + */ + #define OS_QUEUE_PUT(queue, item, timeout) xQueueSendToBack((queue), (item), (timeout)) + +/** + * \brief Put element in queue + * + * Function adds element into queue if there is enough room for it. + * If there is no room in queue error is returned immediately. + * + * This is safe to call from ISR. + * + * \param [in] queue id of queue to put item to + * \param [in] item pointer to element to enqueue + * + * \return OS_QUEUE_FULL if there was no place in queue + * OS_QUEUE_OK if message was put in queue + * + */ + #define OS_QUEUE_PUT_FROM_ISR(queue, item) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xQueueSendToBackFromISR((queue), (item), &need_switch); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Get element from queue + * + * Function adds element into queue if there is enough room for it. + * If there is nothing in queue for \p timeout ticks error is returned. + * Use OS_QUEUE_NO_WAIT for \p timeout to get message without waiting. + * Use OS_QUEUE_FOREVER to wait till message arrives. + * + * \param [in] queue id of queue to get item from + * \param [out] item pointer to buffer that will receive element from queue + * \param [in] timeout max time in ticks to wait for element in queue + * + * \return OS_QUEUE_EMPTY if there was nothing in queue + * OS_QUEUE_OK if message was get from queue + * + */ + #define OS_QUEUE_GET(queue, item, timeout) xQueueReceive((queue), (item), (timeout)) + +/** + * \brief Peek element on queue + * + * Function gets element from queue without removing it. + * If there is nothing in queue for \p timeout ticks error is returned. + * Use OS_QUEUE_NO_WAIT for \p timeout to get message without waiting. + * Use OS_QUEUE_FOREVER to wait till message arrives. + * + * \param [in] queue id of queue to peek item from + * \param [out] item pointer to buffer that will receive element from queue + * \param [in] timeout max time in ticks to wait for element in queue + * + * \return OS_QUEUE_EMPTY if there was nothing in queue + * OS_QUEUE_OK if message was get from queue + * + */ + #define OS_QUEUE_PEEK(queue, item, timeout) xQueuePeek((queue), (item), (timeout)) + +/** + * \brief Get the number of messages stored in the queue + * + * \param [in] queue id of the queue to check. + */ + #define OS_QUEUE_MESSAGES_WAITING(queue) uxQueueMessagesWaiting((queue)) + +/** + * \brief Create software timer + * + * Function creates software timer with given timeout + * + * \param [in] name timer name + * \param [in] period timer period in ticks + * \param [in] reload indicates if callback will be called once or multiple times + * \param [in] timer_id identifier which can be used to identify timer in callback function + * \param [in] callback callback called when timer expires + * + * \return OS_TIMER if timer created successfully, otherwise null + */ + #define OS_TIMER_CREATE(name, period, reload, timer_id, callback) \ + xTimerCreate((name), (period), ((reload) ? pdTRUE : pdFALSE), ((void *) (timer_id)), (callback)) + +/** + * \brief Get timer ID + * + * Function returns timer_id assigned in OS_TIMER_CREATE + * + * \param [in] timer timer handle + * + * \return timer id + */ + #define OS_TIMER_GET_TIMER_ID(timer) pvTimerGetTimerID(timer) + +/** + * \brief Check if timer is active + * + * Function checks timer status + * + * \param [in] timer timer handle + * + * \return true if timer is active, otherwise false + */ + #define OS_TIMER_IS_ACTIVE(timer) xTimerIsTimerActive(timer) + +/** + * \brief Start timer + * + * Function starts timer + * + * \param [in] timer timer handle returned in OS_TIMER_CREATE + * \param [in] timeout max time in ticks to wait until command is sent + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * or OS_TIMER_FAIL if timeout occur + */ + #define OS_TIMER_START(timer, timeout) xTimerStart((timer), (timeout)) + +/** + * \brief Stop timer + * + * Function stops timer + * + * \param [in] timer timer handle returned in OS_TIMER_CREATE + * \param [in] timeout max time in ticks to wait until command is sent + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * or OS_TIMER_FAIL if timeout occur + */ + #define OS_TIMER_STOP(timer, timeout) xTimerStop((timer), (timeout)) + +/** + * \brief Change timer's period + * + * Functions updates timer's period + * + * \param [in] timer timer handle + * \param [in] period new timer's period + * \param [in] timeout max time in ticks to wait until command is sent + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * or OS_TIMER_FAIL if timeout occur + */ + #define OS_TIMER_CHANGE_PERIOD(timer, period, timeout) \ + xTimerChangePeriod((timer), (period), (timeout)) + +/** + * \brief Delete timer + * + * Function deletes previously created timer + * + * \param [in] timer timer handle + * \param [in] timeout max time in ticks to wait until command is sent + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * or OS_TIMER_FAIL if timeout occur + */ + #define OS_TIMER_DELETE(timer, timeout) xTimerDelete((timer), (timeout)) + +/** + * \brief Reset timer + * + * Function restarts previously created timer + * + * \param [in] timer timer handle + * \param [in] timeout max time in ticks to wait until command is sent + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * or OS_TIMER_FAIL if timeout occur + */ + #define OS_TIMER_RESET(timer, timeout) xTimerReset((timer), (timeout)) + +/** + * \brief Start timer from ISR + * + * Version of OS_TIMER_START that can be called from an interrupt service + * routine + * + * \param [in] timer timer handle + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * otherwise OS_TIMER_FAIL + * + * \sa OS_TIMER_START() + */ + #define OS_TIMER_START_FROM_ISR(timer) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTimerStartFromISR((timer), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Stop timer from ISR + * + * Version of OS_TIMER_STOP that can be called from an interrupt service + * routine + * + * \param [in] timer timer handle + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * otherwise OS_TIMER_FAIL + * + * \sa OS_TIMER_STOP() + */ + #define OS_TIMER_STOP_FROM_ISR(timer) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTimerStopFromISR((timer), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Reset timer from ISR + * + * Version of OS_TIMER_RESET that can be called from an interrupt service + * routine + * + * \param [in] timer timer handle + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * otherwise OS_TIMER_FAIL + * + * \sa OS_TIMER_RESET() + */ + #define OS_TIMER_RESET_FROM_ISR(timer) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTimerResetFromISR((timer), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Change timer period from ISR + * + * Version of OS_TIMER_CHANGE_PERIOD that can be called from an interrupt service + * routine + * + * \param [in] timer timer handle + * \param [in] period new timer period + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * otherwise OS_TIMER_FAIL + * + * \sa OS_TIMER_CHANGE_PERIOD + */ + #define OS_TIMER_CHANGE_PERIOD_FROM_ISR(timer, period) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTimerChangePeriodFromISR((timer), (period), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Reset timer from ISR + * + * Version of OS_TIMER_RESET that can be called from an interrupt service + * routine + * + * \param [in] timer timer handle + * + * \return OS_TIMER_SUCCESS if command has been sent successfully, + * otherwise OS_TIMER_FAIL + * + * \sa OS_TIMER_RESET() + */ + #define OS_TIMER_RESET_FROM_ISR(timer) \ + ({ \ + BaseType_t need_switch, ret; \ + ret = xTimerResetFromISR((timer), &(need_switch)); \ + portEND_SWITCHING_ISR(need_switch); \ + ret; \ + }) + +/** + * \brief Delay execution of task for specified time + * + * This function delays in OS specific way execution of current task. + * + * \param [in] ticks number of ticks to wait + * + */ + #define OS_DELAY(ticks) vTaskDelay(ticks) + +/** + * \brief Get current tick count + * + * \return current tick count + * + */ + #define OS_GET_TICK_COUNT() xTaskGetTickCount() + +/** + * \brief Convert from OS ticks to ms + * + * \param [in] ticks tick count to convert + * + * \return value in ms + * + */ + #define OS_TICKS_2_MS(ticks) portCONVERT_TICKS_2_MS(ticks) + +/** + * \brief Convert from ms to OS ticks + * + * \param [in] ms milliseconds to convert + * + * \return value in OS ticks + * + */ + #define OS_MS_2_TICKS(ms) portCONVERT_MS_2_TICKS(ms) + +/** + * \brief Delay execution of task for specified time + * + * This function delays in OS specific way execution of current task. + * + * \param [in] ms number of ms to wait + * + */ + #define OS_DELAY_MS(ms) OS_DELAY(OS_MS_2_TICKS(ms)) + +/** + * \brief Enter critical section from non-ISR context + * + * This allows to enter critical section from non-ISR context. + * Implementation will disable interrupts with nesting counter. + * This function can be called several times by task but requires same + * number of OS_LEAVE_CRITICAL_SECTION calls to allow task switching and interrupts + * again. + * + * \sa OS_LEAVE_CRITICAL_SECTION + * + */ + #define OS_ENTER_CRITICAL_SECTION() \ + do { \ + OS_ASSERT(!in_interrupt()); \ + portENTER_CRITICAL(); \ + } while (0) + +/** + * \brief Enter critical section from ISR context + * + * This function allows to enter critical section from ISR context. + * It can be called several times from within ISR context but requires same + * number of OS_LEAVE_CRITICAL_SECTION calls to restore interrupt status. + * + * \sa OS_LEAVE_CRITICAL_SECTION_FROM_ISR + * + */ + #define OS_ENTER_CRITICAL_SECTION_FROM_ISR(critical_section_status) \ + do { \ + OS_ASSERT(in_interrupt()); \ + critical_section_status = portSET_INTERRUPT_MASK_FROM_ISR(); \ + } while (0) + +/** + * \brief Leave critical section from non-ISR context. + * + * Function restores interrupts and task switching. + * Number of calls to this function must match number of calls to OS_ENTER_CRITICAL_SECTION. + * + * \sa OS_ENTER_CRITICAL_SECTION + * + */ + #define OS_LEAVE_CRITICAL_SECTION() \ + do { \ + OS_ASSERT(!in_interrupt()); \ + portEXIT_CRITICAL(); \ + } while (0) + +/** + * \brief Leave critical section from ISR context + * + * Function restores interrupts from ISR context. + * Number of calls to this function must match number of calls to OS_ENTER_CRITICAL_SECTION_FROM_ISR. + * + * \sa OS_ENTER_CRITICAL_SECTION_FROM_ISR + * + */ + #define OS_LEAVE_CRITICAL_SECTION_FROM_ISR(critical_section_status) \ + do { \ + OS_ASSERT(in_interrupt()); \ + portCLEAR_INTERRUPT_MASK_FROM_ISR(critical_section_status); \ + } while (0) + +/** + * \brief Name for OS memory allocation function + * + * \sa OS_MALLOC + * + */ + #define OS_MALLOC_FUNC pvPortMalloc + +/** + * \brief Name for non-retain memory allocation function + * + * \sa OS_MALLOC_FUNC + * + */ + #define OS_MALLOC_NORET_FUNC pvPortMalloc + +/** + * \brief Allocate memory from OS provided heap + * + * \sa OS_FREE + * + */ + #define OS_MALLOC(size) OS_MALLOC_FUNC(size) + +/** + * \brief Allocate memory from non-retain heap + * + * \sa OS_FREE + * + */ + #define OS_MALLOC_NORET(size) OS_MALLOC_NORET_FUNC(size) + +/** + * \brief Name for OS free memory function + * + * \sa OS_FREE + * + */ + #define OS_FREE_FUNC vPortFree + +/** + * \brief Name for non-retain memory free function + * + * \sa OS_FREE_NORET + * \sa OS_MALLOC_NORET + * + */ + #define OS_FREE_NORET_FUNC vPortFree + +/** + * \brief Free memory allocated by OS_MALLOC() + * + * \sa OS_MALLOC + * + */ + #define OS_FREE(addr) OS_FREE_FUNC(addr) + +/** + * \brief Free memory allocated by OS_MALLOC_NORET() + * + * \sa OS_MALLOC_NORET + * + */ + #define OS_FREE_NORET(addr) OS_FREE_NORET_FUNC(addr) + + #if (configUSE_TRACE_FACILITY == 1) + +/** + * \brief Get task status + * + * Function gets the status of a task + * + * \param [in] task_status where the status of the task is stored + * \param [in] status_size the size of the above container + * + * \return the number of the monitored tasks + * + */ + #define OS_GET_TASKS_STATUS(task_status, status_size) uxTaskGetSystemState(task_status, status_size, NULL) + #else + #define OS_GET_TASKS_STATUS(task_status, status_size) + #endif + + #if (INCLUDE_uxTaskGetStackHighWaterMark == 1) + +/** + * \brief Get task status + * + * Function gets the status of a task + * + * \param [in] task_id the task id of the tracked task + * + * \return high water mark of the stack in bytes + * + */ + #define OS_GET_STACK_WATERMARK(task_id) uxTaskGetStackHighWaterMark(task_id) + #else + #define OS_GET_STACK_WATERMARK(task_id) + #endif + +/** + * \brief Get heap min water mark size + * + * Function gets heap min water mark size + * + * + * \return The heap min water mark size in bytes + * + */ + #define OS_GET_HEAP_WATERMARK() xPortGetMinimumEverFreeHeapSize() + +/** + * \brief Get current free heap size + * + * Function gets heap current available size + * + * + * \return Current free heap size in bytes + * + */ + #define OS_GET_FREE_HEAP_SIZE() xPortGetFreeHeapSize() + +/** + * \brief Get current number OS tasks + * + * Function gets current number OS tasks + * + * + * \return the current number of OS tasks + * + */ + #define OS_GET_TASKS_NUMBER() uxTaskGetNumberOfTasks() + + #if (INCLUDE_pcTaskGetTaskName == 1) + +/** + * \brief Get task name + * + * Function gets task name + * + * \param [in] task_id the task id of the monitored task + * + * \return a string pointer, points to the name of task + * + */ + #define OS_GET_TASK_NAME(task_id) pcTaskGetTaskName(task_id) + #else + #define OS_GET_TASK_NAME(task_id) + #endif + + #if (INCLUDE_eTaskGetState == 1) + +/** + * \brief Get task state + * + * Function gets task state + * + * \param [in] task_id the task id of the monitored task + * + * \return the task state in OS_TASK_STATE + * + */ + #define OS_GET_TASK_STATE(task_id) eTaskGetState(task_id) + #else + #define OS_GET_TASK_STATE(task_id) + #endif + + #if (INCLUDE_uxTaskPriorityGet == 1) + +/** + * \brief Get task priority + * + * Function gets task priority + * + * \param [in] task_id the task id of the monitored task + * + * \return the task priority + * + */ + #define OS_GET_TASK_PRIOTITY(task_id) uxTaskPriorityGet(task_id) + #else + #define OS_GET_TASK_PRIOTITY(task_id) + #endif + +#endif /*defined(OS_FREERTOS)*/ + +#if defined OS_BAREMETAL + #include + +/* + * Basic set of macros that can be used in non OS environment. + */ + #define PRIVILEGED_DATA + #define OS_MALLOC malloc + #define OS_FREE free + #ifndef RELEASE_BUILD + #define OS_ASSERT(a) do {if (!(a)) {__BKPT(0);}} while (0) + #else + #define OS_ASSERT(a) ((void) (a)) + #endif + +#endif + +#endif /* OSAL_H_ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/ra6w1_platform_nvparam.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/ra6w1_platform_nvparam.h new file mode 100644 index 000000000000..738c4c1dc612 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/ra6w1_platform_nvparam.h @@ -0,0 +1,2102 @@ +/** + * \addtogroup MID_SYS_ADAPTERS + * \{ + * \addtogroup ADAPTER_CONFIGURATION + * \{ + */ + +/** + **************************************************************************************** + * + * @file ra6w1_platform_nvparam.h + * + * @brief Configuration of non-volatile parameters on platform + * + * Copyright (c) 2024 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef PLATFORM_NVPARAM_H_ + +// Do NOT modify this Definition Directive !! +#define PLATFORM_NVPARAM_H_ + +#undef CONFIG_UNUSED + +#include "ad_nvparam_defs.h" +#include "common_def.h" + +#if (dg_configNVPARAM_ADAPTERv2 == 1) + +/* + * Parameters length need to include 2 extra bytes for parameter header. + * Variable-length parameters length need to include 4 extra bytes for parameter header and length. + */ + #define NVPARAM_HEAD_SIZE 2 + #define STR_END 1 + #define PARAM_STR_EXTRA (NVPARAM_HEAD_SIZE + STR_END) + #define PARAM_IPADDR_LEN (16 + PARAM_STR_EXTRA) + #define PARAM_IP6ADDR_LEN (40 + PARAM_STR_EXTRA) + #define UINT32_LEN 4 + #define INT32_LEN 4 + #define UINT16_LEN 2 + #define UINT8_LEN 1 + + #define STR_INT32_LEN (11 + PARAM_STR_EXTRA) + #define STR_INT16_LEN (7 + PARAM_STR_EXTRA) + #define STR_INT8_LEN (4 + PARAM_STR_EXTRA) + + #define NPRO_0 "N0_" + #define NPRO_1 "N1_" + +/// List of NVEE lengths + +// bootcfg +//= ============================================================================= + #define NVEE_LEN_BOOT_CHIP 9 + PARAM_STR_EXTRA + #define NVEE_LEN_BOOT_PLATFORM 13 + PARAM_STR_EXTRA + #define NVEE_LEN_BOOT_CLK_CPU UINT32_LEN + #define NVEE_LEN_BOOT_CLK_BUS UINT32_LEN + #define NVEE_LEN_BOOT_BAUD UINT32_LEN + #define NVEE_LEN_BOOT_BIT UINT32_LEN + #define NVEE_LEN_BOOT_STOP UINT8_LEN + +// devcfg +//= ============================================================================= + + #define NVEE_LEN_WLANMAC (12 + PARAM_STR_EXTRA) + #define NVEE_LEN_ATCMD_UART_BAUDRATE (UINT32_LEN) + #define NVEE_LEN_ATCMD_UART_BITS (UINT32_LEN) + #define NVEE_LEN_ATCMD_UART_PARITY (UINT32_LEN) + #define NVEE_LEN_ATCMD_UART_STOPBIT (UINT32_LEN) + #define NVEE_LEN_ATCMD_UART_FLOWCTRL (UINT32_LEN) + +// wificfg +//= ============================================================================= + +// Supplicant Global Config + #define NVEE_LEN_uuid (40 + PARAM_STR_EXTRA) + #define NVEE_LEN_auto_uuid STR_INT32_LEN + +/** + * device_name - Device Name (WPS) + * User-friendly description of device; up to 32 octets encoded in + * UTF-8 + */ + #define NVEE_LEN_device_name (32 + PARAM_STR_EXTRA) + +/** + * manufacturer - Manufacturer (WPS) + * The manufacturer of the device (up to 64 ASCII characters) + */ + #define NVEE_LEN_manufacturer 64 + +/** + * model_name - Model Name (WPS) + * Model of the device (up to 32 ASCII characters) + */ + #define NVEE_LEN_model_name (32 + PARAM_STR_EXTRA) + +/** + * model_number - Model Number (WPS) + * Additional device description (up to 32 ASCII characters) + */ + #define NVEE_LEN_model_number (32 + PARAM_STR_EXTRA) + +/** + * serial_number - Serial Number (WPS) + * Serial number of the device (up to 32 characters) + */ + #define NVEE_LEN_serial_number (32 + PARAM_STR_EXTRA) + +/** + * device_type - Primary Device Type (WPS) + */ + #define NVEE_LEN_device_type (21 + PARAM_STR_EXTRA) /* WPS_DEV_TYPE_BUFSIZE */ + +/** + * config_methods - Config Methods + * + * This is a space-separated list of supported WPS configuration + * methods. For example + #define "label virtual_display virtual_push_button + * keypad". + * Available methods: usba ethernet label display ext_nfc_token + * int_nfc_token nfc_interface push_button keypad + * virtual_display physical_display + * virtual_push_button physical_push_button. + */ + #define NVEE_LEN_config_methods (256 + PARAM_STR_EXTRA) + #define NVEE_LEN_p2p_ssid_postfix (23 + PARAM_STR_EXTRA) // SSID_MAX_LEN-(DIRECT-xx) = 32-9 = 23 + #define NVEE_LEN_p2p_group_idle STR_INT32_LEN + #define NVEE_LEN_p2p_listen_channel STR_INT32_LEN + #define NVEE_LEN_p2p_oper_channel STR_INT32_LEN + #define NVEE_LEN_p2p_find_timeout STR_INT32_LEN + #define NVEE_LEN_p2p_go_intent STR_INT32_LEN + #define NVEE_LEN_wmm_enabled STR_INT32_LEN + #define NVEE_LEN_wmm_ps_enabled STR_INT32_LEN + #define NVEE_LEN_ap_max_inactivity STR_INT32_LEN + #define NVEE_LEN_ap_send_ka STR_INT32_LEN + #define NVEE_LEN_bss_max_count STR_INT32_LEN + #define NVEE_LEN_bss_expiration_age STR_INT32_LEN + #define NVEE_LEN_bss_expiration_scan_count STR_INT32_LEN + #define NVEE_LEN_filter_ssids STR_INT32_LEN + #define NVEE_LEN_filter_rssi STR_INT32_LEN + #define NVEE_LEN_max_num_sta STR_INT32_LEN + #define NVEE_LEN_ap_isolate STR_INT32_LEN + #define NVEE_LEN_disassoc_low_ack STR_INT32_LEN + #define NVEE_LEN_hs20 STR_INT32_LEN + #define NVEE_LEN_interworking STR_INT32_LEN + #define NVEE_LEN_hessid (6 + PARAM_STR_EXTRA) // ETH_ALEN 6 /* Octets in one ethernet addr */ + #define NVEE_LEN_access_network_type STR_INT32_LEN + #define NVEE_LEN_go_interworking STR_INT32_LEN + #define NVEE_LEN_go_access_network_type STR_INT32_LEN + #define NVEE_LEN_go_internet STR_INT32_LEN + #define NVEE_LEN_go_venue_group STR_INT32_LEN + #define NVEE_LEN_go_venue_type STR_INT32_LEN + #define NVEE_LEN_pbc_in_m1 STR_INT32_LEN + #define NVEE_LEN_wps_nfc_dev_pw_id STR_INT32_LEN + #define NVEE_LEN_ext_password_backend (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_p2p_go_max_inactivity STR_INT32_LEN + #define NVEE_LEN_auto_interworking STR_INT32_LEN + #define NVEE_LEN_okc STR_INT32_LEN + #define NVEE_LEN_pmf STR_INT32_LEN + #define NVEE_LEN_dtim_period STR_INT32_LEN + #define NVEE_LEN_beacon_int STR_INT32_LEN + #define NVEE_LEN_sae_groups (18 + PARAM_STR_EXTRA) // 3*MAX_SAE_GROUPS + #define NVEE_LEN_ignore_old_scan_res STR_INT32_LEN + #define NVEE_LEN_scan_cur_freq STR_INT32_LEN + #define NVEE_LEN_sched_scan_interval STR_INT32_LEN + #define NVEE_LEN_sched_scan_start_delay STR_INT32_LEN + #define NVEE_LEN_external_sim STR_INT32_LEN + #define NVEE_LEN_tdls_external_control STR_INT32_LEN + +/** + * wowlan_triggers - Wake-on-WLAN triggers + * + * If set, these wowlan triggers will be configured. + */ + #define NVEE_LEN_wowlan_triggers (32 + PARAM_STR_EXTRA) + +/** + * bgscan - Background scan and roaming parameters or %NULL if none + * + * This is an optional set of parameters for background scanning and + * roaming within a network (ESS). For more detailed information see + * ssid block documentation. + * + * The variable defines default bgscan behavior for all BSS station + * networks except for those which have their own bgscan configuration. + */ + #define NVEE_LEN_bgscan (32 + PARAM_STR_EXTRA) + +/** + * autoscan - Automatic scan parameters or %NULL if none + * + * This is an optional set of parameters for automatic scanning + * within an interface in following format: + * : + */ + #define NVEE_LEN_autoscan (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_p2p_search_delay STR_INT32_LEN + #define NVEE_LEN_mac_addr (6 + PARAM_STR_EXTRA) + #define NVEE_LEN_rand_addr_lifetime STR_INT32_LEN + #define NVEE_LEN_preassoc_mac_addr STR_INT32_LEN + #define NVEE_LEN_key_mgmt_offload STR_INT32_LEN + #define NVEE_LEN_user_mpm STR_INT32_LEN + #define NVEE_LEN_max_peer_links STR_INT32_LEN + #define NVEE_LEN_cert_in_cb STR_INT32_LEN + #define NVEE_LEN_mesh_max_inactivity STR_INT32_LEN + #define NVEE_LEN_dot11RSNASAERetransPeriod STR_INT32_LEN + #define NVEE_LEN_reassoc_same_bss_optim STR_INT32_LEN + #define NVEE_LEN_wps_priority STR_INT32_LEN + #define NVEE_LEN_wpa_rsc_relaxation STR_INT32_LEN + +/** + * sched_scan_plans - Scan plans for scheduled scan + * + * Each scan plan specifies the interval between scans and the number of + * iterations. The last scan plan only specifies the scan interval and + * will be run infinitely. + * + * format: ... + */ + #define NVEE_LEN_sched_scan_plans (32 + PARAM_STR_EXTRA) + +/** + * non_pref_chan - Non-preferred channels list + #define separated by spaces. + * + * format: op_class:chan:preference:reason<:detail> + * Detail is optional. + */ + #define NVEE_LEN_non_pref_chan (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_mbo_cell_capa STR_INT32_LEN + #define NVEE_LEN_disassoc_imminent_rssi_threshold STR_INT32_LEN + #define NVEE_LEN_oce STR_INT32_LEN + #define NVEE_LEN_gas_address3 STR_INT32_LEN + #define NVEE_LEN_ftm_responder STR_INT32_LEN + #define NVEE_LEN_ftm_initiator STR_INT32_LEN + +/** + * osu_dir - OSU provider information directory + * + * If set + #define allow FETCH_OSU control interface command to be used to fetch + * OSU provider information into all APs and store the results in this + * directory. + */ + #define NVEE_LEN_osu_dir STR_INT32_LEN + #define NVEE_LEN_fst_group_id (16 + PARAM_STR_EXTRA) // FST_MAX_GROUP_ID_LEN (IFNAMSIZ) + #define NVEE_LEN_fst_priority STR_INT32_LEN + #define NVEE_LEN_fst_llt STR_INT32_LEN + #define NVEE_LEN_gas_rand_addr_lifetime STR_INT32_LEN + #define NVEE_LEN_gas_rand_mac_addr STR_INT32_LEN + #define NVEE_LEN_dpp_config_processing STR_INT32_LEN + #define NVEE_LEN_STA_roam STR_INT32_LEN + #define NVEE_LEN_STA_roam_thold STR_INT32_LEN + #define NVEE_LEN_greenfield STR_INT32_LEN + #define NVEE_LEN_ht_protection STR_INT32_LEN + #define NVEE_LEN_rts_threshold STR_INT32_LEN + #define NVEE_LEN_acl_cmd STR_INT32_LEN + #define NVEE_LEN_country_code (3 + PARAM_STR_EXTRA) + #define NVEE_LEN_tls_ver STR_INT32_LEN + #define NVEE_LEN_rootca_chk STR_INT32_LEN + #define NVEE_LEN_peap_ver STR_INT32_LEN + #define NVEE_LEN_supp_log_mask STR_INT32_LEN + #define NVEE_LEN_supp_wpa_log_mask STR_INT32_LEN + #define NVEE_LEN_setband STR_INT32_LEN + #define NVEE_LEN_p2p_ps STR_INT32_LEN + #define NVEE_LEN_TEMP_PIN STR_INT32_LEN + #define NVEE_LEN_fast_reauth STR_INT32_LEN + #define NVEE_LEN_fast_pac (512 + PARAM_STR_EXTRA) + #define NVEE_LEN_fast_pac_len STR_INT32_LEN + +// ============================================================================= +// Supplicant Network Profile 0 +// ============================================================================= + #define NVEE_LEN_N0_profile STR_INT32_LEN + #define NVEE_LEN_N0_ssid (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_scan_ssid STR_INT32_LEN + #define NVEE_LEN_N0_bssid (17 + PARAM_STR_EXTRA) // MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" + #define NVEE_LEN_N0_bssid_hint STR_INT32_LEN + #define NVEE_LEN_N0_bssid_blacklist STR_INT32_LEN + #define NVEE_LEN_N0_bssid_whitelist STR_INT32_LEN + #define NVEE_LEN_N0_psk (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_psk_raw (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_mem_only_psk STR_INT32_LEN + +/** + * sae_password - SAE password + * + * This parameter can be used to set a password for SAE. By default, the + * passphrase value is used if this separate parameter is not used, but + * passphrase follows the WPA-PSK constraints (8..63 characters) even + * though SAE passwords do not have such constraints. + */ + #define NVEE_LEN_N0_sae_password (128 + 2 + PARAM_STR_EXTRA) + +/** + * sae_password_id - SAE password identifier + * + * This parameter can be used to identify a specific SAE password. If + * not included, the default SAE password is used instead. + */ + #define NVEE_LEN_N0_sae_password_id (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_proto (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_key_mgmt (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_bg_scan_period STR_INT32_LEN + #define NVEE_LEN_N0_pairwise (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher +// wpa_config_write_cipher + #define NVEE_LEN_N0_group (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher + #define NVEE_LEN_N0_group_mgmt (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher +// wpa_config_write_cipher + #define NVEE_LEN_N0_auth_alg (30 + PARAM_STR_EXTRA) + +/** + * bgscan - Background scan and roaming parameters or %NULL if none + * + * This is an optional set of parameters for background scanning and + * roaming within a network (ESS) in following format: + * : + */ + #define NVEE_LEN_N0_bgscan (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_autoscan (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + +/** + * scan_freq - Array of frequencies to scan or %NULL for all + * + * This is an optional zero-terminated array of frequencies in + * megahertz (MHz) to include in scan requests when searching for this + * network. This can be used to speed up scanning when the network is + * known to not use all possible channels. + */ + #define NVEE_LEN_N0_scan_freq (640 + PARAM_STR_EXTRA) // Unknown Size (expected size: channel count * 5, 2Ghz + 5Ghz) // 56 EA : 56(CH)*10(int)+56(space)+24(Margin) + #define NVEE_LEN_N0_freq_list (640 + PARAM_STR_EXTRA) // Unknown Size (expected size: channel count * 5, 2Ghz + 5Ghz) // 56 EA : 56(CH)*10(int)+56(space)+24(Margin) + #define NVEE_LEN_N0_eap (100 + PARAM_STR_EXTRA) // wpa_config_write_eap + #define NVEE_LEN_N0_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_anonymous_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + + #define NVEE_LEN_N0_imsi_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_password (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_phase1 (20 + PARAM_STR_EXTRA) // Unknown Size (expected size: aboud: 20) + #define NVEE_LEN_N0_phase2 (20 + PARAM_STR_EXTRA) // Unknown Size (expected size: aboud: 20) + #define NVEE_LEN_N0_eapol_flags STR_INT32_LEN + #define NVEE_LEN_N0_wep_key0 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N0_wep_key1 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N0_wep_key2 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N0_wep_key3 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N0_priority STR_INT32_LEN + #define NVEE_LEN_N0_eap_workaround STR_INT32_LEN + #define NVEE_LEN_N0_pac_file (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_fragment_size STR_INT32_LEN + #define NVEE_LEN_N0_ocsp STR_INT32_LEN + #define NVEE_LEN_N0_sim_num STR_INT32_LEN + #define NVEE_LEN_N0_mode STR_INT32_LEN + #define NVEE_LEN_N0_no_auto_peer STR_INT32_LEN + #define NVEE_LEN_N0_frequency STR_INT32_LEN + #define NVEE_LEN_N0_fixed_freq STR_INT32_LEN + #define NVEE_LEN_N0_acs STR_INT32_LEN + #define NVEE_LEN_N0_proactive_key_caching STR_INT32_LEN + #define NVEE_LEN_N0_disabled STR_INT32_LEN + #define NVEE_LEN_N0_pbss STR_INT32_LEN + #define NVEE_LEN_N0_wps_disabled STR_INT32_LEN + #define NVEE_LEN_N0_fils_dh_group STR_INT32_LEN + #define NVEE_LEN_N0_ieee80211w STR_INT32_LEN + #define NVEE_LEN_N0_id_str (256 + PARAM_STR_EXTRA) + #define NVEE_LEN_N0_ignore_broadcast_ssid STR_INT32_LEN + #define NVEE_LEN_N0_dtim_period STR_INT32_LEN + #define NVEE_LEN_N0_beacon_int STR_INT32_LEN + #define NVEE_LEN_N0_isolate STR_INT32_LEN + #define NVEE_LEN_N0_ap_max_inactivity STR_INT32_LEN + #define NVEE_LEN_N0_ap_power (8 + PARAM_STR_EXTRA) // auto, ... + #define NVEE_LEN_N0_update_identifier STR_INT32_LEN + #define NVEE_LEN_N0_roaming_consortium_selection (15 + PARAM_STR_EXTRA) // MAX_ROAMING_CONS_OI_LEN + +/** + * mac_addr - MAC address policy + * + * 0 = use permanent MAC address + * 1 = use random MAC address for each ESS connection + * 2 = like 1, but maintain OUI (with local admin bit set) + * + * Internally, special value -1 is used to indicate that the parameter + * was not specified in the configuration (i.e., default behavior is + * followed). + */ + #define NVEE_LEN_N0_mac_addr STR_INT32_LEN + #define NVEE_LEN_N0_mesh_basic_rates (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_dot11MeshMaxRetries STR_INT32_LEN + #define NVEE_LEN_N0_dot11MeshRetryTimeout STR_INT32_LEN + #define NVEE_LEN_N0_dot11MeshConfirmTimeout STR_INT32_LEN + #define NVEE_LEN_N0_dot11MeshHoldingTimeout STR_INT32_LEN + #define NVEE_LEN_N0_mesh_rssi_threshold STR_INT32_LEN // -255 ~1 + #define NVEE_LEN_N0_wpa_ptk_rekey STR_INT32_LEN + #define NVEE_LEN_N0_wpa_deny_ptk0_rekey STR_INT32_LEN + #define NVEE_LEN_N0_group_rekey STR_INT32_LEN + #define NVEE_LEN_N0_dpp_connector (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_dpp_netaccesskey (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_dpp_netaccesskey_expiry STR_INT32_LEN + #define NVEE_LEN_N0_dpp_csign (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_owe_group STR_INT32_LEN + #define NVEE_LEN_N0_owe_only STR_INT32_LEN + #define NVEE_LEN_N0_owe_ptk_workaround STR_INT32_LEN + #define NVEE_LEN_N0_multi_ap_backhaul_sta STR_INT32_LEN + #define NVEE_LEN_N0_ft_eap_pmksa_caching STR_INT32_LEN + #define NVEE_LEN_N0_beacon_prot STR_INT32_LEN + #define NVEE_LEN_N0_transition_disable STR_INT32_LEN + #define NVEE_LEN_N0_sae_pk STR_INT32_LEN + #define NVEE_LEN_N0_wifi_mode STR_INT32_LEN + +/** + * mixed_cell - Whether mixed cells are allowed + * + * This option can be used to configure whether so called mixed cells, + * i.e., networks that use both plaintext and encryption in the same + * SSID, are allowed. This is disabled (0) by default. Enable by + * setting this to 1. + */ + #define NVEE_LEN_N0_mixed_cell STR_INT32_LEN + #define NVEE_LEN_N0_ht STR_INT32_LEN + #define NVEE_LEN_N0_ht40 STR_INT32_LEN + #define NVEE_LEN_N0_disable_ht STR_INT32_LEN + #define NVEE_LEN_N0_disable_ht40 STR_INT32_LEN + #define NVEE_LEN_N0_disable_sgi STR_INT32_LEN + #define NVEE_LEN_N0_disable_ldpc STR_INT32_LEN + #define NVEE_LEN_N0_ht40_intolerant STR_INT32_LEN + #define NVEE_LEN_N0_tx_stbc STR_INT32_LEN + #define NVEE_LEN_N0_rx_stbc STR_INT32_LEN + #define NVEE_LEN_N0_disable_max_amsdu STR_INT32_LEN + #define NVEE_LEN_N0_ampdu_factor STR_INT32_LEN + #define NVEE_LEN_N0_ampdu_density STR_INT32_LEN + #define NVEE_LEN_N0_ht_mcs (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_max_oper_chwidth STR_INT32_LEN + #define NVEE_LEN_N0_vht_center_freq1 STR_INT32_LEN + #define NVEE_LEN_N0_vht_center_freq2 STR_INT32_LEN + #define NVEE_LEN_N0_vht STR_INT32_LEN + #define NVEE_LEN_N0_disable_vht STR_INT32_LEN + #define NVEE_LEN_N0_vht_capa STR_INT32_LEN + #define NVEE_LEN_N0_vht_capa_mask STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_1 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_2 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_3 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_4 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_5 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_6 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_7 STR_INT32_LEN + #define NVEE_LEN_N0_vht_rx_mcs_nss_8 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_1 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_2 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_3 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_4 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_5 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_6 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_7 STR_INT32_LEN + #define NVEE_LEN_N0_vht_tx_mcs_nss_8 STR_INT32_LEN + #define NVEE_LEN_N0_ca_cert STR_INT32_LEN + #define NVEE_LEN_N0_ca_path STR_INT32_LEN + #define NVEE_LEN_N0_client_cert STR_INT32_LEN + #define NVEE_LEN_N0_private_key STR_INT32_LEN + #define NVEE_LEN_N0_private_key_passwd STR_INT32_LEN + #define NVEE_LEN_N0_dh_file STR_INT32_LEN + #define NVEE_LEN_N0_subject_match STR_INT32_LEN + #define NVEE_LEN_N0_altsubject_match STR_INT32_LEN + #define NVEE_LEN_N0_domain_suffix_match STR_INT32_LEN + #define NVEE_LEN_N0_domain_match STR_INT32_LEN + #define NVEE_LEN_N0_ca_cert2 STR_INT32_LEN + #define NVEE_LEN_N0_ca_path2 STR_INT32_LEN + #define NVEE_LEN_N0_client_cert2 STR_INT32_LEN + #define NVEE_LEN_N0_private_key2 STR_INT32_LEN + #define NVEE_LEN_N0_private_key2_passwd STR_INT32_LEN + #define NVEE_LEN_N0_dh_file2 STR_INT32_LEN + #define NVEE_LEN_N0_subject_match2 STR_INT32_LEN + #define NVEE_LEN_N0_altsubject_match2 STR_INT32_LEN + #define NVEE_LEN_N0_domain_suffix_match2 STR_INT32_LEN + #define NVEE_LEN_N0_domain_match2 STR_INT32_LEN + #define NVEE_LEN_N0_pcsc (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N0_pin STR_INT32_LEN + #define NVEE_LEN_N0_engine_id STR_INT32_LEN + #define NVEE_LEN_N0_key_id STR_INT32_LEN + #define NVEE_LEN_N0_cert_id STR_INT32_LEN + #define NVEE_LEN_N0_ca_cert_id STR_INT32_LEN + #define NVEE_LEN_N0_key2_id STR_INT32_LEN + #define NVEE_LEN_N0_pin2 STR_INT32_LEN + #define NVEE_LEN_N0_engine2_id STR_INT32_LEN + #define NVEE_LEN_N0_cert2_id STR_INT32_LEN + #define NVEE_LEN_N0_ca_cert2_id STR_INT32_LEN + #define NVEE_LEN_N0_engine STR_INT32_LEN + #define NVEE_LEN_N0_engine2 STR_INT32_LEN + #define NVEE_LEN_N0_openssl_ciphers STR_INT32_LEN + #define NVEE_LEN_N0_erp STR_INT32_LEN + #define NVEE_LEN_N0_erp STR_INT32_LEN + #define NVEE_LEN_N0_FST_CONNECT STR_INT32_LEN + #define NVEE_LEN_N0_ASSOC_CH STR_INT32_LEN + #if 0 // def CONFIG_MACSEC + #define NVEE_LEN_N0_macsec_policy STR_INT32_LEN + #define NVEE_LEN_N0_macsec_integ_only STR_INT32_LEN + #define NVEE_LEN_N0_macsec_port STR_INT32_LEN + #define NVEE_LEN_N0_mka_priority STR_INT32_LEN + #endif /* CONFIG_MACSEC */ + +// ============================================================================= + +// ============================================================================= +// Supplicant Network Profile 1 +// ============================================================================= + #define NVEE_LEN_N1_profile STR_INT32_LEN + #define NVEE_LEN_N1_ssid (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_scan_ssid STR_INT32_LEN + #define NVEE_LEN_N1_bssid (17 + PARAM_STR_EXTRA) // MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" + #define NVEE_LEN_N1_bssid_hint STR_INT32_LEN + #define NVEE_LEN_N1_bssid_blacklist STR_INT32_LEN + #define NVEE_LEN_N1_bssid_whitelist STR_INT32_LEN + #define NVEE_LEN_N1_psk (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_mem_only_psk STR_INT32_LEN + +/** + * sae_password - SAE password + * + * This parameter can be used to set a password for SAE. By default, the + * passphrase value is used if this separate parameter is not used, but + * passphrase follows the WPA-PSK constraints (8..63 characters) even + * though SAE passwords do not have such constraints. + */ + #define NVEE_LEN_N1_sae_password (128 + 2 + PARAM_STR_EXTRA) + +/** + * sae_password_id - SAE password identifier + * + * This parameter can be used to identify a specific SAE password. If + * not included, the default SAE password is used instead. + */ + #define NVEE_LEN_N1_sae_password_id (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_proto (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_key_mgmt (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_bg_scan_period STR_INT32_LEN + #define NVEE_LEN_N1_pairwise (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher +// wpa_config_write_cipher + #define NVEE_LEN_N1_group (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher +// wpa_config_write_cipher + #define NVEE_LEN_N1_group_mgmt (50 + PARAM_STR_EXTRA) // wpa_config_write_cipher + #define NVEE_LEN_N1_auth_alg (30 + PARAM_STR_EXTRA) + +/** + * bgscan - Background scan and roaming parameters or %NULL if none + * + * This is an optional set of parameters for background scanning and + * roaming within a network (ESS) in following format: + * : + */ + #define NVEE_LEN_N1_bgscan (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_autoscan (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + +/** + * scan_freq - Array of frequencies to scan or %NULL for all + * + * This is an optional zero-terminated array of frequencies in + * megahertz (MHz) to include in scan requests when searching for this + * network. This can be used to speed up scanning when the network is + * known to not use all possible channels. + */ + #define NVEE_LEN_N1_scan_freq (640 + PARAM_STR_EXTRA) // Unknown Size (expected size: channel count * 5, 2Ghz + 5Ghz) // 56 EA : 56(CH)*10(int)+56(space)+24(Margin) + #define NVEE_LEN_N1_freq_list (640 + PARAM_STR_EXTRA) // Unknown Size (expected size: channel count * 5, 2Ghz + 5Ghz) // 56 EA : 56(CH)*10(int)+56(space)+24(Margin) + #define NVEE_LEN_N1_eap (100 + PARAM_STR_EXTRA) // wpa_config_write_eap + #define NVEE_LEN_N1_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_anonymous_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_imsi_identity (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_password (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_phase1 (20 + PARAM_STR_EXTRA) // Unknown Size (expected size: aboud: 20) + #define NVEE_LEN_N1_phase2 (20 + PARAM_STR_EXTRA) // Unknown Size (expected size: aboud: 20) + #define NVEE_LEN_N1_eapol_flags STR_INT32_LEN + #define NVEE_LEN_N1_wep_key0 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N1_wep_key1 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N1_wep_key2 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N1_wep_key3 (26 + PARAM_STR_EXTRA) // MAX_WEP_KEY_LEN + #define NVEE_LEN_N1_wep_tx_keyidx STR_INT32_LEN + #define NVEE_LEN_N1_priority STR_INT32_LEN + #define NVEE_LEN_N1_eap_workaround STR_INT32_LEN + #define NVEE_LEN_N1_pac_file (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_fragment_size STR_INT32_LEN + #define NVEE_LEN_N1_ocsp STR_INT32_LEN + #define NVEE_LEN_N1_sim_num STR_INT32_LEN + #define NVEE_LEN_N1_mode STR_INT32_LEN + #define NVEE_LEN_N1_no_auto_peer STR_INT32_LEN + #define NVEE_LEN_N1_frequency STR_INT32_LEN + #define NVEE_LEN_N1_fixed_freq STR_INT32_LEN + #define NVEE_LEN_N1_acs STR_INT32_LEN + #define NVEE_LEN_N1_proactive_key_caching STR_INT32_LEN + #define NVEE_LEN_N1_disabled STR_INT32_LEN + #define NVEE_LEN_N1_pbss STR_INT32_LEN + #define NVEE_LEN_N1_wps_disabled STR_INT32_LEN + #define NVEE_LEN_N1_fils_dh_group STR_INT32_LEN + #define NVEE_LEN_N1_ieee80211w STR_INT32_LEN + #define NVEE_LEN_N1_id_str (256 + PARAM_STR_EXTRA) + #define NVEE_LEN_N1_ignore_broadcast_ssid STR_INT32_LEN + #define NVEE_LEN_N1_dtim_period STR_INT32_LEN + #define NVEE_LEN_N1_beacon_int STR_INT32_LEN + #define NVEE_LEN_N1_isolate STR_INT32_LEN + #define NVEE_LEN_N1_ap_max_inactivity STR_INT32_LEN + #define NVEE_LEN_N1_ap_power (8 + PARAM_STR_EXTRA) // auto, ... + #define NVEE_LEN_N1_update_identifier STR_INT32_LEN + #define NVEE_LEN_N1_roaming_consortium_selection (15 + PARAM_STR_EXTRA) // MAX_ROAMING_CONS_OI_LEN + +/** + * mac_addr - MAC address policy + * + * 0 = use permanent MAC address + * 1 = use random MAC address for each ESS connection + * 2 = like 1, but maintain OUI (with local admin bit set) + * + * Internally, special value -1 is used to indicate that the parameter + * was not specified in the configuration (i.e., default behavior is + * followed). + */ + #define NVEE_LEN_N1_mac_addr STR_INT32_LEN + #define NVEE_LEN_N1_mesh_basic_rates (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_dot11MeshMaxRetries STR_INT32_LEN + #define NVEE_LEN_N1_dot11MeshRetryTimeout STR_INT32_LEN + #define NVEE_LEN_N1_dot11MeshConfirmTimeout STR_INT32_LEN + #define NVEE_LEN_N1_dot11MeshHoldingTimeout STR_INT32_LEN + #define NVEE_LEN_N1_mesh_rssi_threshold STR_INT32_LEN // -255 ~1 + #define NVEE_LEN_N1_wpa_ptk_rekey STR_INT32_LEN + #define NVEE_LEN_N1_wpa_deny_ptk0_rekey STR_INT32_LEN + #define NVEE_LEN_N1_group_rekey STR_INT32_LEN + #define NVEE_LEN_N1_dpp_connector (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_dpp_netaccesskey (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_dpp_netaccesskey_expiry STR_INT32_LEN + #define NVEE_LEN_N1_dpp_csign (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_owe_group STR_INT32_LEN + #define NVEE_LEN_N1_owe_only STR_INT32_LEN + #define NVEE_LEN_N1_owe_ptk_workaround STR_INT32_LEN + #define NVEE_LEN_N1_multi_ap_backhaul_sta STR_INT32_LEN + #define NVEE_LEN_N1_ft_eap_pmksa_caching STR_INT32_LEN + #define NVEE_LEN_N1_beacon_prot STR_INT32_LEN + #define NVEE_LEN_N1_transition_disable STR_INT32_LEN + #define NVEE_LEN_N1_sae_pk STR_INT32_LEN + #define NVEE_LEN_N1_wifi_mode STR_INT32_LEN + +/** + * mixed_cell - Whether mixed cells are allowed + * + * This option can be used to configure whether so called mixed cells, + * i.e., networks that use both plaintext and encryption in the same + * SSID, are allowed. This is disabled (0) by default. Enable by + * setting this to 1. + */ + #define NVEE_LEN_N1_mixed_cell STR_INT32_LEN + #define NVEE_LEN_N1_ht STR_INT32_LEN + #define NVEE_LEN_N1_ht40 STR_INT32_LEN + #define NVEE_LEN_N1_disable_ht STR_INT32_LEN + #define NVEE_LEN_N1_disable_ht40 STR_INT32_LEN + #define NVEE_LEN_N1_disable_sgi STR_INT32_LEN + #define NVEE_LEN_N1_disable_ldpc STR_INT32_LEN + #define NVEE_LEN_N1_ht40_intolerant STR_INT32_LEN + #define NVEE_LEN_N1_tx_stbc STR_INT32_LEN + #define NVEE_LEN_N1_rx_stbc STR_INT32_LEN + #define NVEE_LEN_N1_disable_max_amsdu STR_INT32_LEN + #define NVEE_LEN_N1_ampdu_factor STR_INT32_LEN + #define NVEE_LEN_N1_ampdu_density STR_INT32_LEN + #define NVEE_LEN_N1_ht_mcs (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_max_oper_chwidth STR_INT32_LEN + #define NVEE_LEN_N1_vht_center_freq1 STR_INT32_LEN + #define NVEE_LEN_N1_vht_center_freq2 STR_INT32_LEN + #define NVEE_LEN_N1_vht STR_INT32_LEN + #define NVEE_LEN_N1_disable_vht STR_INT32_LEN + #define NVEE_LEN_N1_vht_capa STR_INT32_LEN + #define NVEE_LEN_N1_vht_capa_mask STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_1 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_2 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_3 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_4 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_5 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_6 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_7 STR_INT32_LEN + #define NVEE_LEN_N1_vht_rx_mcs_nss_8 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_1 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_2 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_3 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_4 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_5 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_6 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_7 STR_INT32_LEN + #define NVEE_LEN_N1_vht_tx_mcs_nss_8 STR_INT32_LEN + #define NVEE_LEN_N1_ca_cert STR_INT32_LEN + #define NVEE_LEN_N1_ca_path STR_INT32_LEN + #define NVEE_LEN_N1_client_cert STR_INT32_LEN + #define NVEE_LEN_N1_private_key STR_INT32_LEN + #define NVEE_LEN_N1_private_key_passwd STR_INT32_LEN + #define NVEE_LEN_N1_dh_file STR_INT32_LEN + #define NVEE_LEN_N1_subject_match STR_INT32_LEN + #define NVEE_LEN_N1_altsubject_match STR_INT32_LEN + #define NVEE_LEN_N1_domain_suffix_match STR_INT32_LEN + #define NVEE_LEN_N1_domain_match STR_INT32_LEN + #define NVEE_LEN_N1_ca_cert2 STR_INT32_LEN + #define NVEE_LEN_N1_ca_path2 STR_INT32_LEN + #define NVEE_LEN_N1_client_cert2 STR_INT32_LEN + #define NVEE_LEN_N1_private_key2 STR_INT32_LEN + #define NVEE_LEN_N1_private_key2_passwd STR_INT32_LEN + #define NVEE_LEN_N1_dh_file2 STR_INT32_LEN + #define NVEE_LEN_N1_subject_match2 STR_INT32_LEN + #define NVEE_LEN_N1_altsubject_match2 STR_INT32_LEN + #define NVEE_LEN_N1_domain_suffix_match2 STR_INT32_LEN + #define NVEE_LEN_N1_domain_match2 STR_INT32_LEN + #define NVEE_LEN_N1_pcsc (32 + PARAM_STR_EXTRA) // Unknown Size (expected size) + #define NVEE_LEN_N1_pin STR_INT32_LEN + #define NVEE_LEN_N1_engine_id STR_INT32_LEN + #define NVEE_LEN_N1_key_id STR_INT32_LEN + #define NVEE_LEN_N1_cert_id STR_INT32_LEN + #define NVEE_LEN_N1_ca_cert_id STR_INT32_LEN + #define NVEE_LEN_N1_key2_id STR_INT32_LEN + #define NVEE_LEN_N1_pin2 STR_INT32_LEN + #define NVEE_LEN_N1_engine2_id STR_INT32_LEN + #define NVEE_LEN_N1_cert2_id STR_INT32_LEN + #define NVEE_LEN_N1_ca_cert2_id STR_INT32_LEN + #define NVEE_LEN_N1_engine STR_INT32_LEN + #define NVEE_LEN_N1_engine2 STR_INT32_LEN + #define NVEE_LEN_N1_openssl_ciphers STR_INT32_LEN + #define NVEE_LEN_N1_erp STR_INT32_LEN + #if 0 // def CONFIG_MACSEC + #define NVEE_LEN_N1_macsec_policy STR_INT32_LEN + #define NVEE_LEN_N1_macsec_integ_only STR_INT32_LEN + #define NVEE_LEN_N1_macsec_port STR_INT32_LEN + #define NVEE_LEN_N1_mka_priority STR_INT32_LEN + #endif /* CONFIG_MACSEC */ + #define NVEE_LEN_sleep_mgmt_mode STR_INT32_LEN + #define NVEE_LEN_sleep_mgmt_ddps STR_INT32_LEN + #define NVEE_LEN_sleep_mgmt_ab_wf_conn_retry STR_INT32_LEN + #define NVEE_LEN_sleep_mgmt_abnorm_stop STR_INT32_LEN + #define NVEE_LEN_sleep_mgmt_ip_condition STR_INT32_LEN + #define NVEE_LEN_abn_chk_conn_wait_name STR_INT32_LEN + + #define NVEE_LEN_abn_chk_dhcp_rsp_wait_name STR_INT32_LEN + #define NVEE_LEN_abn_chk_arp_rsp_wait_name STR_INT32_LEN + #define NVEE_LEN_abn_chk_fail_wait_name STR_INT32_LEN + #define NVEE_LEN_abn_chk_conn_retry_cnt_name STR_INT32_LEN + +// syscfg +//= ============================================================================= + #define HOSTNAME_MAX_LEN 32 + #define DHCPC_HOSTNAME_MAX_LEN HOSTNAME_MAX_LEN + #define SNTP_SERVER_DOMAIN_MAX_LEN HOSTNAME_MAX_LEN + #define TAG_DBG_TXPWR_2G 28 + #define TAG_DBG_TXPWR_5G 56 + #define TAG_DBG_TXPWR_5G_FLG 28 + + #define NVEE_LEN_INITWLAN STR_INT32_LEN + #define NVEE_LEN_SYSMODE STR_INT32_LEN + #define NVEE_LEN_SWITCH_SYSMODE STR_INT32_LEN + #define NVEE_LEN_0_MAC_SP (12 + PARAM_STR_EXTRA) + #define NVEE_LEN_0_NETMODE STR_INT32_LEN + #define NVEE_LEN_0_IP_Address PARAM_IPADDR_LEN + #define NVEE_LEN_0_NETMASK PARAM_IPADDR_LEN + #define NVEE_LEN_0_GATEWAY PARAM_IPADDR_LEN + #define NVEE_LEN_0_DNSSVR PARAM_IPADDR_LEN + #define NVEE_LEN_0_DNSSVR2 PARAM_IPADDR_LEN + #define NVEE_LEN_0_TEMP_STATIC_IP STR_INT32_LEN + +//= =========== + + #define NVEE_LEN_1_NETMODE STR_INT32_LEN + #define NVEE_LEN_1_IP_Address PARAM_IPADDR_LEN + #define NVEE_LEN_1_NETMASK PARAM_IPADDR_LEN + #define NVEE_LEN_1_GATEWAY PARAM_IPADDR_LEN + #define NVEE_LEN_1_DNSSVR PARAM_IPADDR_LEN + #define NVEE_LEN_1_DNSSVR2 PARAM_IPADDR_LEN + +/* DHCP Server (IPv4) */ + #define NVEE_LEN_1_DHCP_SERVER_RUN STR_INT32_LEN + #define NVEE_LEN_1_DHCP_SERVER_START_IP PARAM_IPADDR_LEN + #define NVEE_LEN_1_DHCP_SERVER_END_IP PARAM_IPADDR_LEN + #define NVEE_LEN_1_DHCP_SERVER_LEASE_TIME STR_INT32_LEN + #define NVEE_LEN_1_DHCP_SERVER_DNS PARAM_IPADDR_LEN + +/* IPv6 */ + #define NVEE_LEN_1_IPV6_ADDRESS PARAM_IP6ADDR_LEN + +/* DHCP Server (IPv6) */ + #define NVEE_LEN_1_DHCPV6_SERVER_START_IP PARAM_IP6ADDR_LEN + #define NVEE_LEN_1_DHCPV6_SERVER_END_IP PARAM_IP6ADDR_LEN + #define NVEE_LEN_1_DHCPV6_SERVER_DNS PARAM_IP6ADDR_LEN + #define NVEE_LEN_1_DHCPV6_SERVER_LEASE_TIME STR_INT32_LEN + +/* Timezone */ + #define NVEE_LEN_TIMEZONE STR_INT32_LEN + +/* DHCP Client hostname */ + #define NVEE_LEN_DHCPC_HOSTNAME (DHCPC_HOSTNAME_MAX_LEN + PARAM_STR_EXTRA) + +/* SNTP Server */ + #define NVEE_LEN_SNTP_SERVER_DOMAIN (SNTP_SERVER_DOMAIN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_SNTP_SERVER1_DOMAIN (SNTP_SERVER_DOMAIN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_SNTP_SERVER2_DOMAIN (SNTP_SERVER_DOMAIN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_SNTP_SYNC_PERIOD STR_INT32_LEN + #define NVEE_LEN_SNTP_RUN_FLAG STR_INT32_LEN + #define NVEE_LEN_DBG_TXPWR_2G_OFDM (TAG_DBG_TXPWR_2G + PARAM_STR_EXTRA) + #define NVEE_LEN_DBG_TXPWR_2G_DSSS (TAG_DBG_TXPWR_2G + PARAM_STR_EXTRA) + #define NVEE_LEN_DBG_TXPWR_5G (TAG_DBG_TXPWR_5G + PARAM_STR_EXTRA) + #define NVEE_LEN_DBG_TXPWR_5G_FLG (TAG_DBG_TXPWR_5G_FLG + PARAM_STR_EXTRA) + +/* UART Config */ +/* UART2 */ + #define NVEE_LEN_UART2_BAUDRATE (STR_INT32_LEN) + #define NVEE_LEN_UART2_BITS (STR_INT32_LEN) + #define NVEE_LEN_UART2_PARITY (STR_INT32_LEN) + #define NVEE_LEN_UART2_STOPBIT (STR_INT32_LEN) + #define NVEE_LEN_UART2_FLOWCTRL (STR_INT32_LEN) + +/* UART3 */ + #define NVEE_LEN_UART3_BAUDRATE (STR_INT32_LEN) + #define NVEE_LEN_UART3_BITS (STR_INT32_LEN) + #define NVEE_LEN_UART3_PARITY (STR_INT32_LEN) + #define NVEE_LEN_UART3_STOPBIT (STR_INT32_LEN) + #define NVEE_LEN_UART3_FLOWCTRL (STR_INT32_LEN) + +// appcfg +//= ============================================================================= + #define MATT_CLIENT_ID_MAX_LEN 40 + #define MATT_TLS_ALPN_MAX_LEN 24 + #define MATT_TLS_SNI_MAX_LEN 64 + #define MATT_TLS_CSUIT_MAX_LEN 84 + + #define NVEE_LEN_MQTT_BROKER (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_QOS STR_INT32_LEN + #define NVEE_LEN_MQTT_SUB_TOPIC (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_TOPIC0 (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_TOPIC1 (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_TOPIC2 (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_TOPIC3 (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_TOPIC_NUM STR_INT32_LEN + #define NVEE_LEN_MQTT_PUB_TOPIC (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS STR_INT32_LEN + #define NVEE_LEN_MQTT_USERNAME (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_PASSWORD (160 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_WILL_TOPIC (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_WILL_MSG (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_SUB_CID (MATT_CLIENT_ID_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_PUB_CID (MATT_CLIENT_ID_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS_ALPN0 (MATT_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS_ALPN1 (MATT_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS_ALPN2 (MATT_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS_SNI (MATT_TLS_SNI_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_MQTT_TLS_CSUIT_NUM STR_INT32_LEN + #define NVEE_LEN_MQTT_TLS_CSUIT (MATT_TLS_CSUIT_MAX_LEN + PARAM_STR_EXTRA) + +/* HTTP Client */ + #define HTTPC_TLS_ALPN_MAX_NUM 3 + #define HTTPC_TLS_ALPN_MAX_LEN 24 + #define HTTPC_TLS_SNI_MAX_LEN 64 + + #define NVEE_LEN_HTTPC_TLS_ALPN0 (HTTPC_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_HTTPC_TLS_ALPN1 (HTTPC_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_HTTPC_TLS_ALPN2 (HTTPC_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_HTTPC_TLS_SNI (HTTPC_TLS_SNI_MAX_LEN + PARAM_STR_EXTRA) + +/* OTA update */ + #define OTA_TLS_ALPN_MAX_NUM 3 + #define OTA_TLS_ALPN_MAX_LEN 24 + #define OTA_TLS_SNI_MAX_LEN 64 + + #define NVEE_LEN_OTA_TLS_ALPN0 (OTA_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_OTA_TLS_ALPN1 (OTA_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_OTA_TLS_ALPN2 (OTA_TLS_ALPN_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_OTA_TLS_SNI (OTA_TLS_SNI_MAX_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_URL (256 + PARAM_STR_EXTRA) + +/* ATCMD: TCP Server, Client, and UDP Session */ + #define NW_TR_PIPADDR_LEN (46 + PARAM_STR_EXTRA) + #define NVEE_LEN_ATC_NW_TR_PIPADDR NW_TR_PIPADDR_LEN + +/* ATCMD: TLS Client */ + #define NW_TLSC_CA_CERT_NAME_LEN 32 + #define NW_TLSC_CERT_NAME_LEN 32 + #define NW_TLSC_HOST_NAME_LEN 64 + #define NW_TLSC_PEER_IPADDR_LEN 64 + #define NVEE_LEN_ATC_NW_TLSC_CA_CERT_NAME (NW_TLSC_CA_CERT_NAME_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_ATC_NW_TLSC_CERT_NAME (NW_TLSC_CERT_NAME_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_ATC_NW_TLSC_HOST_NAME (NW_TLSC_HOST_NAME_LEN + PARAM_STR_EXTRA) + #define NVEE_LEN_ATC_NW_TLSC_PIPADDR (NW_TLSC_PEER_IPADDR_LEN + PARAM_STR_EXTRA) + +/* BLE-COMBO : BLE Provisioning - provisioning status */ + #define NVEE_LEN_BLE_COMBO_PROVISIONED (STR_INT32_LEN) + #define NVEE_LEN_BLE_COMBO_PROV_SRV_IP (PARAM_IPADDR_LEN) + #define NVEE_LEN_BLE_COMBO_PROV_SRV_PORT (STR_INT32_LEN) + +/* BLE-COMBO : For Gas Leak sensor sample */ + #define NVEE_LEN_BLE_COMBO_SENSOR_STARTED (STR_INT32_LEN) + +/* BLE-COMBO : For Sensor gateway sample */ + #define NVEE_LEN_BLE_COMBO_SENSOR_GW_UDP_SVR_IP (PARAM_IPADDR_LEN) + #define NVEE_LEN_BLE_COMBO_SENSOR_GW_UDP_SVR_PORT (STR_INT32_LEN) + +/* BLE-COMBO : For TCPC DPM sample */ + #define NVEE_LEN_BLE_COMBO_TCPC_SVR_IP (PARAM_IPADDR_LEN) + #define NVEE_LEN_BLE_COMBO_TCPC_SVR_PORT (STR_INT32_LEN) + +/* BLE-COMBO : For OTA */ + #define OTA_HTTP_URL_LENGTH 256 + #define NVEE_LEN_BLE_COMBO_OTA_URI_RTOS (OTA_HTTP_URL_LENGTH) + #define NVEE_LEN_BLE_COMBO_OTA_URI_BLE (OTA_HTTP_URL_LENGTH) + #define NVEE_LEN_DPM_REG_NAME_TIMER (STR_INT32_LEN) + #define NVEE_LEN_DPM_MNG_UDPC_SVR_IP (PARAM_IPADDR_LEN) + #define NVEE_LEN_DPM_MNG_UDPC_SVR_PORT (STR_INT32_LEN) + +/* Apps WiFi Provisioning for Mobile App */ + #define NVEE_LEN_APP_APPTHINGNAME (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_SETSLEEPMODE STR_INT32_LEN + #define NVEE_LEN_APP_SLEEPMODERTCTIME STR_INT32_LEN + #define NVEE_LEN_APP_SETUSEDPM STR_INT32_LEN + +/* TCP Client application */ + #define NVEE_LEN_APP_TCPC_ACTIVE (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_PEER_IP_ADDR (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_TCPC_PEER_PORT (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_SEND_PERIOD (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_SEND_DATA_SIZE (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_AUTO_RESTART_AT_EXIT (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_KA_ENABLE (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_KA_IDLE_TIME (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_KA_INTVL_TIME (UINT32_LEN) + #define NVEE_LEN_APP_TCPC_KA_MAX_PROBES (UINT32_LEN) + +// blecfg + +/* BD address is saved in next format: aa:bb:cc:dd:ee:ff */ + #define NVEE_LEN_BLECFG_BD_ADDR (17 + PARAM_STR_EXTRA) + +// blesec + + #define NVEE_LEN_BLESEC_BOOT_DATA (48) + #define NVEE_LEN_BLESEC_BONDING_DATA (80 + 16) // BOND DATA + IV + + #define AWSIOT_CFG_THINGNAME "thingname" + #define AWSIOT_CFG_USE_FLEET_PROVISION "use_fp" + #define AWSIOT_CFG_FLEET_PROVISIONING_DEVICE_ID "fp_dev_id" + #define AWSIOT_CFG_FLEET_PROVISIONING_TEMPLATE_NAME "fp_tmpl_name" + #define AWSIOT_CFG_BROKER_URL "broker_url" + #define AWSIOT_CFG_BOARD_FEATURE "board_feature" + #define AWSIOT_CFG_LPORT "lport" + #define AWSIOT_CFG_PORT "port" + #define AWSIOT_CFG_STOPIC "stopic" + #define AWSIOT_CFG_PTOPIC "ptopic" + #define AWSIOT_CFG_DPM_SLEEP_MODE "sleepmode" + #define AWSIOT_CFG_USE_DPM "usedpm" + #define AWSIOT_CFG_RTC_TIME "rtc_time" + #define AWSIOT_CFG_DPM_KEEP_ALIVE_TIME "keepalive_time" + #define AWSIOT_CFG_USER_WAKE_UP_TIME "usr_wakeup_time" + #define AWSIOT_CFG_TIM_WAKE_UP_TIME "tim_wakeup_time" + #define AWSIOT_CFG_MCU_WAKEUP_PORT "mcu_wu_port" + #define AWSIOT_CFG_MCU_WAKEUP_PIN "mcu_wu_pin" + #define AWSIOT_CFG_SAVED_IP_ADDRESS "ipaddr" + #define AWSIOT_CFG_OTA_URL "ota_url" + #define AWSIOT_CFG_OTA_STATE "ota_state" + #define AWSIOT_CFG_OTA_RESULT "ota_result" + #define AWSIOT_CFG_OTA_FLAG "ota_flag" + #define AWSIOT_CFG_SLEEP_MODE2_RTC_TIME "sleep2rtc" + #define AWSIOT_CFG_FIRST_SNTP_TIME "sntp_time" + #define AWSIOT_CFG_SNTP_SUCCESS_FLAG "sntp_success" + #define AWSIOT_CFG_PING_CHECK "ping_check" + #define AWSIOT_CFG_DPM_AUTO "dpm_auto" + #define AWSIOT_CFG_THING_ATTIRIBUTE_0 "T_att0" + #define AWSIOT_CFG_THING_ATTIRIBUTE_1 "T_att1" + #define AWSIOT_CFG_THING_ATTIRIBUTE_2 "T_att2" + #define AWSIOT_CFG_THING_ATTIRIBUTE_3 "T_att3" + #define AWSIOT_CFG_THING_ATTIRIBUTE_4 "T_att4" + #define AWSIOT_CFG_THING_ATTIRIBUTE_5 "T_att5" + #define AWSIOT_CFG_THING_ATTIRIBUTE_6 "T_att6" + #define AWSIOT_CFG_THING_ATTIRIBUTE_7 "T_att7" + #define AWSIOT_CFG_THING_ATTIRIBUTE_8 "T_att8" + #define AWSIOT_CFG_THING_ATTIRIBUTE_9 "T_att9" + + #define NVEE_LEN_AWSIOT_CFG_THINGNAME (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_FLEET_PROVISIONING_DEVICE_ID (44 + PARAM_STR_EXTRA) + #define NVEE_LEN_AWSIOT_CFG_FLEET_PROV_TEMPLATE_NAME (64 + PARAM_STR_EXTRA) + + #define NVEE_LEN_BROKER_URL NVEE_LEN_URL + #define NVEE_LEN_BOARD_FEATURE 32 + #define NVEE_LEN_AWSIOT_CFG_OTA_URL NVEE_LEN_URL + #define NVEE_LEN_AWSIOT_CFG_SAVED_IP_ADDRESS PARAM_IPADDR_LEN + #define NVEE_LEN_FIRST_SNTP_TIME STR_INT32_LEN + #define NVEE_LEN_STOPIC (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_PTOPIC (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_MCU_WAKEUP_PORT 12 + #define NVEE_LEN_MCU_WAKEUP_PIN 12 + #define NVEE_LEN_THING_ATTRIBUTE 32 + #define MAX_THING_ATT 10 + + #define APP_NVRAM_CONFIG_DEV_PRIMARY_KEY "dev_prim_key" + #define APP_NVRAM_CONFIG_HOST_NAME "host_name" + #define APP_NVRAM_CONFIG_IOTHUB_CONN_STRING "iothub_conn_str" + #define APP_NVRAM_CONFIG_THINGNAME "thingname" + #define APP_NVRAM_DEVICE_CONNECTION_STRING "device_conn_str" + #define AZURE_NVRAM_CONFIG_CURRENT_OTA_VERSION "current_ota_ver" + #define AZURE_NVRAM_CONFIG_CURRENT_MCUOTA_VERSION "current_mcuota_ver" + #define AZURE_NVRAM_CONFIG_OTA_URL "ota_url" + #define AZURE_NVRAM_CONFIG_OTA_VERSION "ota_ver" + #define AZURE_NVRAM_CONFIG_MCUOTA_VERSION "mcuota_ver" + #define AZURE_NVRAM_CONFIG_PORT "az_port" + #define AZURE_NVRAM_CONFIG_OTA_FLAG "ota_flag" + #define AZURE_NVRAM_CONFIG_OTA_STATE "ota_state" + #define AZURE_NVRAM_CONFIG_OTA_RESULT "ota_result" + + #define NVEE_LEN_APP_NVRAM_CONFIG_DEV_PRIMARY_KEY (256 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_NVRAM_CONFIG_HOST_NAME (64 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_NVRAM_CONFIG_IOTHUB_CONN_STRING (512 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_NVRAM_CONFIG_THINGNAME (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_APP_NVRAM_DEVICE_CONNECTION_STRING (512 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_CURRENT_OTA_VERSION (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_CURRENT_MCUOTA_VERSION (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_URL (256 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_VERSION (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_MCUOTA_VERSION (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_AZURE_NVRAM_CONFIG_PORT STR_INT32_LEN + #define NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_FLAG STR_INT32_LEN + #define NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_STATE STR_INT32_LEN + #define NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_RESULT STR_INT32_LEN + + #define WIFI_PROFILE_COMPLETE "profile_complete" + #define WIFI_PROFILE_COUNTRY_CODE "country_code" + #define WIFI_PROFILE_SYS_MODE "sysmode" + #define WIFI_PROFILE_BAND "band" + #define WIFI_PROFILE_CHANNEL "channel" + #define WIFI_PROFILE_WIFI_MODE "wifi_mode" + #define WIFI_PROFILE_PMF "pmf" + #define WIFI_PROFILE_ENABLE_DPM "enable_dpm" + #define WIFI_PROFILE_DPM_DEBUG_RUNTIME_FLAG "dpm_debug_enable" + #define WIFI_PROFILE_DPM_DPM_KEEPALIVE_TIME "dpm_keepalive_time" + #define WIFI_PROFILE_DPM_USER_WAKEUP_TIME "dpm_user_wakeup_time" + #define WIFI_PROFILE_DPM_TIM_WAKEUP_COUNT "dpm_TIM_wakeup_count" + #define WIFI_PROFILE_DPM_BLE_HIBERNATE "dpm_ble_hibernate" + #define WIFI_PROFILE_SSID_0 "ssid_0" + #define WIFI_PROFILE_SSID_1 "ssid_1" + #define WIFI_PROFILE_HIDDEN_SSID "hidden_ssid" + #define WIFI_PROFILE_PMF_0 "pmf_0" + #define WIFI_PROFILE_PMF_1 "pmf_1" + #define WIFI_PROFILE_SECURITY_0 "security_0" + #define WIFI_PROFILE_SECURITY_1 "security_1" + #define WIFI_PROFILE_ENCKEY_0 "password_0" + #define WIFI_PROFILE_ENCKEY_1 "password_1" + #define WIFI_PROFILE_WEPKEY0_0 "wep_key" + #define WIFI_PROFILE_WEPINDEX_0 "wep_key_idx" + #define WIFI_PROFILE_WEPTYPE_0 "wep_key_type" + #define WIFI_PROFILE_SAE_GROUPS_0 "sae_groups_0" + #define WIFI_PROFILE_SAE_GROUPS_1 "sae_groups_1" + #define WIFI_PROFILE_EAP_AUTH_MODE "eap_auth_mode" + #define WIFI_PROFILE_EAP_PHASE2 "eap_phase2" + #define WIFI_PROFILE_EAP_ID "eap_id" + #define WIFI_PROFILE_EAP_PW "eap_pw" + #define WIFI_PROFILE_P2P_SSID_POSTFIX "p2p_ssid_postfix" + #define WIFI_PROFILE_P2P_GROUP_IDLE "p2p_group_idle" + #define WIFI_PROFILE_P2P_LISTEN_CH "p2p_listen_chan" + #define WIFI_PROFILE_P2P_FIND_TIMEOUT "p2p_find_timeout" + #define WIFI_PROFILE_P2P_GO_INTENT "p2p_go_intent" + #define WIFI_PROFILE_NETMODE_0 "netmode_0" + #define WIFI_PROFILE_NETMODE_1 "netmode_1" + #define WIFI_PROFILE_IPADDR_0 "ipaddress_0" + #define WIFI_PROFILE_IPADDR_1 "ipaddress_1" + #define WIFI_PROFILE_NETMASK_0 "subnetmask_0" + #define WIFI_PROFILE_NETMASK_1 "subnetmask_1" + #define WIFI_PROFILE_GATEWAY_0 "gateway_0" + #define WIFI_PROFILE_GATEWAY_1 "gateway_1" + #define WIFI_PROFILE_DNSSVR_0 "dns_0" + #define WIFI_PROFILE_DNSSVR_1 "dns_1" + #define WIFI_PROFILE_DNSSVR_2ND_0 "dns_2nd_0" + #define WIFI_PROFILE_DNSSVR_2ND_1 "dns_2nd_1" + #define WIFI_PROFILE_AP_MAX_INACTIVITY_1 "ap_max_inactivity_1" + #define WIFI_PROFILE_AP_WMM_PS_1 "ap_wmm_ps_1" + #define WIFI_PROFILE_AP_WMM_1 "ap_wmm_1" + #define WIFI_PROFILE_SCAN_CHAN_NUM "scan_channel_number" + #define WIFI_PROFILE_SCAN_CHAN_LIST "scan_channel_list" + #define WIFI_PROFILE_AP_ENC_MODE_1 "ap_enc_1" + + #define NVEE_LEN_WIFI_country_code (3 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_sysmode STR_INT32_LEN + #define NVEE_LEN_WIFI_band STR_INT32_LEN + #define NVEE_LEN_WIFI_channel STR_INT32_LEN + #define NVEE_LEN_WIFI_wifi_mode STR_INT32_LEN + #define NVEE_LEN_WIFI_pmf STR_INT32_LEN + #define NVEE_LEN_WIFI_enable_dpm STR_INT32_LEN + #define NVEE_LEN_WIFI_dpm_debug_runtime_flag STR_INT32_LEN + #define NVEE_LEN_WIFI_dpm_keepalive_time STR_INT32_LEN + #define NVEE_LEN_WIFI_dpm_user_wakeup_time STR_INT32_LEN + #define NVEE_LEN_WIFI_dpm_TIM_wakeup_count STR_INT32_LEN + #define NVEE_LEN_WIFI_dpm_ble_hibernate STR_INT32_LEN + #define NVEE_LEN_WIFI_ssid_0 (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_ssid_1 (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_hidden_ssid STR_INT8_LEN + #define NVEE_LEN_WIFI_password_0 (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_password_1 (32 * 2 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_security_0 STR_INT32_LEN + #define NVEE_LEN_WIFI_security_1 STR_INT32_LEN + #define NVEE_LEN_WIFI_wep_key (26 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_wep_key_idx STR_INT32_LEN + #define NVEE_LEN_WIFI_wep_key_type STR_INT32_LEN + #define NVEE_LEN_WIFI_eap_auth_mode STR_INT32_LEN + #define NVEE_LEN_WIFI_eap_phase2 STR_INT32_LEN + #define NVEE_LEN_WIFI_eap_id (32 + PARAM_STR_EXTRA) + #define NVEE_LEN_WIFI_eap_pw (32 + PARAM_STR_EXTRA) + #define NVEE_LEN__WIFI_p2p_ssid_postfix (23 + PARAM_STR_EXTRA) + #define NVEE_LEN__WIFI_p2p_group_idle STR_INT32_LEN + #define NVEE_LEN_WIFI_p2p_listen_chan STR_INT32_LEN + #define NVEE_LEN_WIFI_p2p_go_intent STR_INT32_LEN + #define NVEE_LEN_WIFI_p2p_find_timeout STR_INT32_LEN + #define NVEE_LEN_WIFI_netmode_0 STR_INT32_LEN + #define NVEE_LEN_WIFI_netmode_1 STR_INT32_LEN + #define NVEE_LEN_WIFI_ipaddress_0 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_ipaddress_1 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_subnetmask_0 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_subnetmask_1 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_gateway_0 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_gateway_1 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_dns_0 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_dns_1 PARAM_IPADDR_LEN + #define NVEE_LEN_WIFI_ap_max_inactivity_1 STR_INT32_LEN + #define NVEE_LEN_WIFI_profile_complete STR_INT32_LEN + #define NVEE_LEN_WIFI_chan_list (128 + PARAM_STR_EXTRA) + +//= ============================================================================= +// boocfg +//= ============================================================================= +NVPARAM_AREA(bootcfg, NVMS_GENERIC_PART) + +// TAG-NAME, MAX-LENGTH +NVPARAM_VARPARAM("chip", NVEE_LEN_BOOT_CHIP) +NVPARAM_VARPARAM("platform", NVEE_LEN_BOOT_PLATFORM) +NVPARAM_PARAM("clk.cpu", NVEE_LEN_BOOT_CLK_CPU) +NVPARAM_PARAM("clk.bus", NVEE_LEN_BOOT_CLK_BUS) +NVPARAM_PARAM("con.baud", NVEE_LEN_BOOT_BAUD) +NVPARAM_PARAM("con.bit", NVEE_LEN_BOOT_BIT) +NVPARAM_PARAM("con.stop", NVEE_LEN_BOOT_STOP) +NVPARAM_AREA_END() + +//= ============================================================================= +// devcfg +//= ============================================================================= +NVPARAM_AREA(devcfg, NVMS_GENERIC_PART) + +// TAG-NAME, MAX-LENGTH +NVPARAM_VARPARAM("WLANMAC", NVEE_LEN_WLANMAC) +NVPARAM_PARAM("ATCMD_UART_BAUDRATE", NVEE_LEN_ATCMD_UART_BAUDRATE) +NVPARAM_PARAM("ATCMD_UART_BITS", NVEE_LEN_ATCMD_UART_BITS) +NVPARAM_PARAM("ATCMD_UART_PARITY", NVEE_LEN_ATCMD_UART_PARITY) +NVPARAM_PARAM("ATCMD_UART_STOPBIT", NVEE_LEN_ATCMD_UART_STOPBIT) +NVPARAM_PARAM("ATCMD_UART_FLOWCTRL", NVEE_LEN_ATCMD_UART_FLOWCTRL) +NVPARAM_AREA_END() + +//= ============================================================================= +// wificfg +//= ============================================================================= +NVPARAM_AREA(wificfg, NVMS_GENERIC_PART) + +// TAG-NAME, MAX-LENGTH +//= ============================================================================ + +/* wpa_config_global */ + +//= ============================================================================ +NVPARAM_VARPARAM("uuid", NVEE_LEN_uuid) +NVPARAM_VARPARAM("auto_uuid", NVEE_LEN_auto_uuid) +NVPARAM_VARPARAM("device_name", NVEE_LEN_device_name) +NVPARAM_VARPARAM("manufacturer", NVEE_LEN_manufacturer) +NVPARAM_VARPARAM("model_name", NVEE_LEN_model_name) +NVPARAM_VARPARAM("model_number", NVEE_LEN_model_number) +NVPARAM_VARPARAM("serial_number", NVEE_LEN_serial_number) +NVPARAM_VARPARAM("device_type", NVEE_LEN_device_type) /* WPS_DEV_TYPE_LEN */ +NVPARAM_VARPARAM("config_methods", NVEE_LEN_config_methods) +NVPARAM_VARPARAM("p2p_ssid_postfix", NVEE_LEN_p2p_ssid_postfix) +NVPARAM_VARPARAM("p2p_group_idle", NVEE_LEN_p2p_group_idle) +NVPARAM_PARAM("p2p_listen_channel", INT32_LEN) +NVPARAM_PARAM("p2p_oper_channel", INT32_LEN) +NVPARAM_PARAM("p2p_find_timeout", INT32_LEN) +NVPARAM_PARAM("p2p_go_intent", INT32_LEN) +NVPARAM_PARAM("wmm_enabled", INT32_LEN) +NVPARAM_PARAM("wmm_ps_enabled", INT32_LEN) +NVPARAM_VARPARAM("ap_max_inactivity", NVEE_LEN_ap_max_inactivity) +NVPARAM_VARPARAM("ap_send_ka", NVEE_LEN_ap_send_ka) +NVPARAM_VARPARAM("bss_max_count", NVEE_LEN_bss_max_count) +NVPARAM_VARPARAM("bss_expiration_age", NVEE_LEN_bss_expiration_age) +NVPARAM_VARPARAM("bss_expiration_scan_count", NVEE_LEN_bss_expiration_scan_count) +NVPARAM_VARPARAM("filter_ssids", NVEE_LEN_filter_ssids) +NVPARAM_VARPARAM("filter_rssi", NVEE_LEN_filter_rssi) +NVPARAM_VARPARAM("max_num_sta", NVEE_LEN_max_num_sta) +NVPARAM_VARPARAM("ap_isolate", NVEE_LEN_ap_isolate) +NVPARAM_VARPARAM("disassoc_low_ack", NVEE_LEN_disassoc_low_ack) +NVPARAM_VARPARAM("hs20", NVEE_LEN_hs20) +NVPARAM_VARPARAM("interworking", NVEE_LEN_interworking) +NVPARAM_VARPARAM("hessid", NVEE_LEN_hessid) +NVPARAM_VARPARAM("access_network_type", NVEE_LEN_access_network_type) +NVPARAM_VARPARAM("go_interworking", NVEE_LEN_go_interworking) +NVPARAM_VARPARAM("go_access_network_type", NVEE_LEN_go_access_network_type) +NVPARAM_VARPARAM("go_internet", NVEE_LEN_go_internet) +NVPARAM_VARPARAM("go_venue_group", NVEE_LEN_go_venue_group) +NVPARAM_VARPARAM("go_venue_type", NVEE_LEN_go_venue_type) +NVPARAM_VARPARAM("pbc_in_m1", NVEE_LEN_pbc_in_m1) +NVPARAM_VARPARAM("wps_nfc_dev_pw_id", NVEE_LEN_wps_nfc_dev_pw_id) +NVPARAM_VARPARAM("ext_password_backend", NVEE_LEN_ext_password_backend) +NVPARAM_VARPARAM("p2p_go_max_inactivity", NVEE_LEN_p2p_go_max_inactivity) +NVPARAM_VARPARAM("auto_interworking", NVEE_LEN_auto_interworking) +NVPARAM_VARPARAM("okc", NVEE_LEN_okc) +NVPARAM_VARPARAM("pmf", NVEE_LEN_pmf) +NVPARAM_VARPARAM("dtim_period", NVEE_LEN_dtim_period) +NVPARAM_VARPARAM("beacon_int", NVEE_LEN_beacon_int) +NVPARAM_VARPARAM("sae_groups", NVEE_LEN_sae_groups) +NVPARAM_VARPARAM("ignore_old_scan_res", NVEE_LEN_ignore_old_scan_res) +NVPARAM_VARPARAM("scan_cur_freq", NVEE_LEN_scan_cur_freq) +NVPARAM_VARPARAM("sched_scan_interval", NVEE_LEN_sched_scan_interval) +NVPARAM_VARPARAM("sched_scan_start_delay", NVEE_LEN_sched_scan_start_delay) +NVPARAM_VARPARAM("external_sim", NVEE_LEN_external_sim) +NVPARAM_VARPARAM("tdls_external_control", NVEE_LEN_tdls_external_control) +NVPARAM_VARPARAM("wowlan_triggers", NVEE_LEN_wowlan_triggers) +NVPARAM_VARPARAM("bgscan", NVEE_LEN_bgscan) +NVPARAM_VARPARAM("autoscan", NVEE_LEN_autoscan) +NVPARAM_VARPARAM("p2p_search_delay", NVEE_LEN_p2p_search_delay) +NVPARAM_VARPARAM("mac_addr", NVEE_LEN_mac_addr) +NVPARAM_VARPARAM("rand_addr_lifetime", NVEE_LEN_rand_addr_lifetime) +NVPARAM_VARPARAM("preassoc_mac_addr", NVEE_LEN_preassoc_mac_addr) +NVPARAM_VARPARAM("key_mgmt_offload", NVEE_LEN_key_mgmt_offload) +NVPARAM_VARPARAM("user_mpm", NVEE_LEN_user_mpm) +NVPARAM_VARPARAM("max_peer_links", NVEE_LEN_max_peer_links) +NVPARAM_VARPARAM("cert_in_cb", NVEE_LEN_cert_in_cb) +NVPARAM_VARPARAM("mesh_max_inactivity", NVEE_LEN_mesh_max_inactivity) +NVPARAM_VARPARAM("dot11RSNASAERetransPeriod", NVEE_LEN_dot11RSNASAERetransPeriod) + +NVPARAM_VARPARAM("reassoc_same_bss_optim", NVEE_LEN_reassoc_same_bss_optim) +NVPARAM_VARPARAM("wps_priority", NVEE_LEN_wps_priority) +NVPARAM_VARPARAM("wpa_rsc_relaxation", NVEE_LEN_wpa_rsc_relaxation) + +NVPARAM_VARPARAM("sched_scan_plans", NVEE_LEN_sched_scan_plans) + +NVPARAM_VARPARAM("non_pref_chan", NVEE_LEN_non_pref_chan) +NVPARAM_VARPARAM("mbo_cell_capa", NVEE_LEN_mbo_cell_capa) +NVPARAM_VARPARAM("disassoc_imminent_rssi_threshold", NVEE_LEN_disassoc_imminent_rssi_threshold) +NVPARAM_VARPARAM("oce", NVEE_LEN_oce) + +NVPARAM_VARPARAM("gas_address3", NVEE_LEN_gas_address3) +NVPARAM_VARPARAM("ftm_responder", NVEE_LEN_ftm_responder) +NVPARAM_VARPARAM("ftm_initiator", NVEE_LEN_ftm_initiator) +NVPARAM_VARPARAM("osu_dir", NVEE_LEN_osu_dir) +NVPARAM_VARPARAM("fst_group_id", NVEE_LEN_fst_group_id) +NVPARAM_VARPARAM("fst_priority", NVEE_LEN_fst_priority) +NVPARAM_VARPARAM("fst_llt", NVEE_LEN_fst_llt) +NVPARAM_VARPARAM("gas_rand_addr_lifetime", NVEE_LEN_gas_rand_addr_lifetime) +NVPARAM_VARPARAM("gas_rand_mac_addr", NVEE_LEN_gas_rand_mac_addr) +NVPARAM_VARPARAM("dpp_config_processing", NVEE_LEN_dpp_config_processing) +NVPARAM_PARAM("STA_roam", INT32_LEN) +NVPARAM_PARAM("STA_roam_thold", INT32_LEN) +NVPARAM_VARPARAM("greenfield", NVEE_LEN_greenfield) +NVPARAM_VARPARAM("ht_protection", NVEE_LEN_ht_protection) +NVPARAM_PARAM("rts_threshold", INT32_LEN) + +NVPARAM_VARPARAM("acl_cmd", NVEE_LEN_acl_cmd) +NVPARAM_VARPARAM("country_code", NVEE_LEN_country_code) +NVPARAM_VARPARAM("tls_ver", NVEE_LEN_tls_ver) +NVPARAM_PARAM("rootca_chk", INT32_LEN) +NVPARAM_PARAM("peap_ver", INT32_LEN) +NVPARAM_VARPARAM("supp_log_mask", NVEE_LEN_supp_log_mask) +NVPARAM_VARPARAM("supp_wpa_log_mask", NVEE_LEN_supp_wpa_log_mask) +NVPARAM_VARPARAM("setband", NVEE_LEN_setband) +NVPARAM_VARPARAM("p2p_ps", NVEE_LEN_p2p_ps) +NVPARAM_VARPARAM("TEMP_PIN", NVEE_LEN_TEMP_PIN) +NVPARAM_VARPARAM("fast_reauth", NVEE_LEN_fast_reauth) +NVPARAM_VARPARAM("fast_pac", NVEE_LEN_fast_pac) +NVPARAM_VARPARAM("fast_pac_len", NVEE_LEN_fast_pac_len) + +// Supplicant Network Profiles (N0_ ~ N1_ : STA, SOFTAP, P2P, MESH) +//= ============================================================================ +// Supplicant Network Profiles (N0_ : STA) +//= ============================================================================ +NVPARAM_PARAM(NPRO_0 "Profile", INT32_LEN) +NVPARAM_VARPARAM(NPRO_0 "ssid", NVEE_LEN_N0_ssid) +NVPARAM_PARAM(NPRO_0 "scan_ssid", INT32_LEN) +NVPARAM_VARPARAM(NPRO_0 "bssid", NVEE_LEN_N0_bssid) +NVPARAM_VARPARAM(NPRO_0 "bssid_hint", NVEE_LEN_N0_bssid_hint) +NVPARAM_VARPARAM(NPRO_0 "bssid_blacklist", NVEE_LEN_N0_bssid_blacklist) +NVPARAM_VARPARAM(NPRO_0 "bssid_whitelist", NVEE_LEN_N0_bssid_whitelist) +NVPARAM_VARPARAM(NPRO_0 "psk", NVEE_LEN_N0_psk) +NVPARAM_VARPARAM(NPRO_0 "PSK_RAW_KEY", NVEE_LEN_N0_psk_raw) + +NVPARAM_VARPARAM(NPRO_0 "mem_only_psk", NVEE_LEN_N0_mem_only_psk) +NVPARAM_VARPARAM(NPRO_0 "sae_password", NVEE_LEN_N0_sae_password) +NVPARAM_VARPARAM(NPRO_0 "sae_password_id", NVEE_LEN_N0_sae_password_id) +NVPARAM_VARPARAM(NPRO_0 "proto", NVEE_LEN_N0_proto) +NVPARAM_VARPARAM(NPRO_0 "key_mgmt", NVEE_LEN_N0_key_mgmt) +NVPARAM_VARPARAM(NPRO_0 "bg_scan_period", NVEE_LEN_N0_bg_scan_period) +NVPARAM_VARPARAM(NPRO_0 "pairwise", NVEE_LEN_N0_pairwise) +NVPARAM_VARPARAM(NPRO_0 "group", NVEE_LEN_N0_group) +NVPARAM_VARPARAM(NPRO_0 "group_mgmt", NVEE_LEN_N0_group_mgmt) +NVPARAM_VARPARAM(NPRO_0 "auth_alg", NVEE_LEN_N0_auth_alg) +NVPARAM_VARPARAM(NPRO_0 "bgscan", NVEE_LEN_N0_bgscan) +NVPARAM_VARPARAM(NPRO_0 "autoscan", NVEE_LEN_N0_autoscan) +NVPARAM_VARPARAM(NPRO_0 "scan_freq", NVEE_LEN_N0_scan_freq) +NVPARAM_VARPARAM(NPRO_0 "freq_list", NVEE_LEN_N0_freq_list) + +NVPARAM_VARPARAM(NPRO_0 "eap", NVEE_LEN_N0_eap) +NVPARAM_VARPARAM(NPRO_0 "identity", NVEE_LEN_N0_identity) +NVPARAM_VARPARAM(NPRO_0 "anonymous_identity", NVEE_LEN_N0_anonymous_identity) +NVPARAM_VARPARAM(NPRO_0 "imsi_identity", NVEE_LEN_N0_imsi_identity) +NVPARAM_VARPARAM(NPRO_0 "password", NVEE_LEN_N0_password) +NVPARAM_VARPARAM(NPRO_0 "phase1", NVEE_LEN_N0_phase1) +NVPARAM_VARPARAM(NPRO_0 "phase2", NVEE_LEN_N0_phase2) +NVPARAM_VARPARAM(NPRO_0 "eapol_flags", NVEE_LEN_N0_eapol_flags) +NVPARAM_VARPARAM(NPRO_0 "wep_key0", NVEE_LEN_N0_wep_key0) +NVPARAM_VARPARAM(NPRO_0 "wep_key1", NVEE_LEN_N0_wep_key1) +NVPARAM_VARPARAM(NPRO_0 "wep_key2", NVEE_LEN_N0_wep_key2) +NVPARAM_VARPARAM(NPRO_0 "wep_key3", NVEE_LEN_N0_wep_key3) +NVPARAM_PARAM(NPRO_0 "wep_tx_keyidx", INT32_LEN) +NVPARAM_VARPARAM(NPRO_0 "priority", NVEE_LEN_N0_priority) +NVPARAM_VARPARAM(NPRO_0 "eap_workaround", NVEE_LEN_N0_eap_workaround) +NVPARAM_VARPARAM(NPRO_0 "pac_file", NVEE_LEN_N0_pac_file) +NVPARAM_VARPARAM(NPRO_0 "fragment_size", NVEE_LEN_N0_fragment_size) +NVPARAM_VARPARAM(NPRO_0 "ocsp", NVEE_LEN_N0_ocsp) +NVPARAM_VARPARAM(NPRO_0 "sim_num", NVEE_LEN_N0_sim_num) +NVPARAM_VARPARAM(NPRO_0 "mode", NVEE_LEN_N0_mode) +NVPARAM_VARPARAM(NPRO_0 "no_auto_peer", NVEE_LEN_N0_no_auto_peer) +NVPARAM_VARPARAM(NPRO_0 "frequency", NVEE_LEN_N0_frequency) +NVPARAM_VARPARAM(NPRO_0 "fixed_freq", NVEE_LEN_N0_fixed_freq) +NVPARAM_VARPARAM(NPRO_0 "acs", NVEE_LEN_N0_acs) +NVPARAM_VARPARAM(NPRO_0 "proactive_key_caching", NVEE_LEN_N0_proactive_key_caching) +NVPARAM_PARAM(NPRO_0 "disabled", INT32_LEN) +NVPARAM_VARPARAM(NPRO_0 "pbss", NVEE_LEN_N0_pbss) +NVPARAM_VARPARAM(NPRO_0 "wps_disabled", NVEE_LEN_N0_wps_disabled) +NVPARAM_VARPARAM(NPRO_0 "fils_dh_group", NVEE_LEN_N0_fils_dh_group) +NVPARAM_VARPARAM(NPRO_0 "ieee80211w", NVEE_LEN_N0_ieee80211w) +NVPARAM_VARPARAM(NPRO_0 "id_str", NVEE_LEN_N0_id_str) +NVPARAM_VARPARAM(NPRO_0 "ignore_broadcast_ssid", NVEE_LEN_N0_ignore_broadcast_ssid) +NVPARAM_VARPARAM(NPRO_0 "dtim_period", NVEE_LEN_N0_dtim_period) +NVPARAM_VARPARAM(NPRO_0 "beacon_int", NVEE_LEN_N0_beacon_int) +NVPARAM_VARPARAM(NPRO_0 "isolate", NVEE_LEN_N0_isolate) +NVPARAM_VARPARAM(NPRO_0 "ap_max_inactivity", NVEE_LEN_N0_ap_max_inactivity) +NVPARAM_VARPARAM(NPRO_0 "ap_power", NVEE_LEN_N0_ap_power) // auto, ... +NVPARAM_VARPARAM(NPRO_0 "update_identifier", NVEE_LEN_N0_update_identifier) +NVPARAM_VARPARAM(NPRO_0 "roaming_consortium_selection", NVEE_LEN_N0_roaming_consortium_selection) // MAX_ROAMING_CONS_OI_LEN +NVPARAM_VARPARAM(NPRO_0 "mac_addr", NVEE_LEN_N0_mac_addr) +NVPARAM_VARPARAM(NPRO_0 "mesh_basic_rates", NVEE_LEN_N0_mesh_basic_rates) +NVPARAM_VARPARAM(NPRO_0 "dot11MeshMaxRetries", NVEE_LEN_N0_dot11MeshMaxRetries) +NVPARAM_VARPARAM(NPRO_0 "dot11MeshRetryTimeout", NVEE_LEN_N0_dot11MeshRetryTimeout) +NVPARAM_VARPARAM(NPRO_0 "dot11MeshConfirmTimeout", NVEE_LEN_N0_dot11MeshConfirmTimeout) +NVPARAM_VARPARAM(NPRO_0 "dot11MeshHoldingTimeout", NVEE_LEN_N0_dot11MeshHoldingTimeout) +NVPARAM_VARPARAM(NPRO_0 "mesh_rssi_threshold", NVEE_LEN_N0_mesh_rssi_threshold) +NVPARAM_VARPARAM(NPRO_0 "wpa_ptk_rekey", NVEE_LEN_N0_wpa_ptk_rekey) +NVPARAM_VARPARAM(NPRO_0 "wpa_deny_ptk0_rekey", NVEE_LEN_N0_wpa_deny_ptk0_rekey) +NVPARAM_VARPARAM(NPRO_0 "group_rekey", NVEE_LEN_N0_group_rekey) +NVPARAM_VARPARAM(NPRO_0 "dpp_connector", NVEE_LEN_N0_dpp_connector) +NVPARAM_VARPARAM(NPRO_0 "dpp_netaccesskey", NVEE_LEN_N0_dpp_netaccesskey) +NVPARAM_VARPARAM(NPRO_0 "dpp_netaccesskey_expiry", NVEE_LEN_N0_dpp_netaccesskey_expiry) +NVPARAM_VARPARAM(NPRO_0 "dpp_csign", NVEE_LEN_N0_dpp_csign) +NVPARAM_VARPARAM(NPRO_0 "owe_group", NVEE_LEN_N0_owe_group) +NVPARAM_VARPARAM(NPRO_0 "owe_only", NVEE_LEN_N0_owe_only) +NVPARAM_VARPARAM(NPRO_0 "owe_ptk_workaround", NVEE_LEN_N0_owe_ptk_workaround) + +NVPARAM_VARPARAM(NPRO_0 "multi_ap_backhaul_sta", NVEE_LEN_N0_multi_ap_backhaul_sta) +NVPARAM_VARPARAM(NPRO_0 "ft_eap_pmksa_caching", NVEE_LEN_N0_ft_eap_pmksa_caching) +NVPARAM_VARPARAM(NPRO_0 "beacon_prot", NVEE_LEN_N0_beacon_prot) +NVPARAM_VARPARAM(NPRO_0 "transition_disable", NVEE_LEN_N0_transition_disable) +NVPARAM_VARPARAM(NPRO_0 "sae_pk", NVEE_LEN_N0_sae_pk) +NVPARAM_VARPARAM(NPRO_0 "wifi_mode", NVEE_LEN_N0_wifi_mode) +NVPARAM_VARPARAM(NPRO_0 "mixed_cell", NVEE_LEN_N0_mixed_cell) +NVPARAM_VARPARAM(NPRO_0 "ht", NVEE_LEN_N0_ht) +NVPARAM_VARPARAM(NPRO_0 "ht40", NVEE_LEN_N0_ht40) +NVPARAM_VARPARAM(NPRO_0 "disable_ht", NVEE_LEN_N0_disable_ht) +NVPARAM_VARPARAM(NPRO_0 "disable_ht40", NVEE_LEN_N0_disable_ht40) +NVPARAM_VARPARAM(NPRO_0 "disable_sgi", NVEE_LEN_N0_disable_sgi) +NVPARAM_VARPARAM(NPRO_0 "disable_ldpc", NVEE_LEN_N0_disable_ldpc) +NVPARAM_VARPARAM(NPRO_0 "ht40_intolerant", NVEE_LEN_N0_ht40_intolerant) +NVPARAM_VARPARAM(NPRO_0 "tx_stbc", NVEE_LEN_N0_tx_stbc) +NVPARAM_VARPARAM(NPRO_0 "rx_stbc", NVEE_LEN_N0_rx_stbc) +NVPARAM_VARPARAM(NPRO_0 "disable_max_amsdu", NVEE_LEN_N0_disable_max_amsdu) +NVPARAM_VARPARAM(NPRO_0 "ampdu_factor", NVEE_LEN_N0_ampdu_factor) +NVPARAM_VARPARAM(NPRO_0 "ampdu_density", NVEE_LEN_N0_ampdu_density) +NVPARAM_VARPARAM(NPRO_0 "ht_mcs", NVEE_LEN_N0_ht_mcs) + +NVPARAM_VARPARAM(NPRO_0 "max_oper_chwidth", NVEE_LEN_N0_max_oper_chwidth) +NVPARAM_VARPARAM(NPRO_0 "vht_center_freq1", NVEE_LEN_N0_vht_center_freq1) +NVPARAM_VARPARAM(NPRO_0 "vht_center_freq2", NVEE_LEN_N0_vht_center_freq2) + +NVPARAM_VARPARAM(NPRO_0 "vht", NVEE_LEN_N0_vht) +NVPARAM_VARPARAM(NPRO_0 "disable_vht", NVEE_LEN_N0_disable_vht) +NVPARAM_VARPARAM(NPRO_0 "vht_capa", NVEE_LEN_N0_vht_capa) +NVPARAM_VARPARAM(NPRO_0 "vht_capa_mask", NVEE_LEN_N0_vht_capa_mask) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_1", NVEE_LEN_N0_vht_rx_mcs_nss_1) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_2", NVEE_LEN_N0_vht_rx_mcs_nss_2) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_3", NVEE_LEN_N0_vht_rx_mcs_nss_3) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_4", NVEE_LEN_N0_vht_rx_mcs_nss_4) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_5", NVEE_LEN_N0_vht_rx_mcs_nss_5) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_6", NVEE_LEN_N0_vht_rx_mcs_nss_6) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_7", NVEE_LEN_N0_vht_rx_mcs_nss_7) +NVPARAM_VARPARAM(NPRO_0 "vht_rx_mcs_nss_8", NVEE_LEN_N0_vht_rx_mcs_nss_8) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_1", NVEE_LEN_N0_vht_tx_mcs_nss_1) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_2", NVEE_LEN_N0_vht_tx_mcs_nss_2) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_3", NVEE_LEN_N0_vht_tx_mcs_nss_3) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_4", NVEE_LEN_N0_vht_tx_mcs_nss_4) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_5", NVEE_LEN_N0_vht_tx_mcs_nss_5) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_6", NVEE_LEN_N0_vht_tx_mcs_nss_6) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_7", NVEE_LEN_N0_vht_tx_mcs_nss_7) +NVPARAM_VARPARAM(NPRO_0 "vht_tx_mcs_nss_8", NVEE_LEN_N0_vht_tx_mcs_nss_8) + +NVPARAM_VARPARAM(NPRO_0 "ca_cert", NVEE_LEN_N0_ca_cert) +NVPARAM_VARPARAM(NPRO_0 "ca_path", NVEE_LEN_N0_ca_path) +NVPARAM_VARPARAM(NPRO_0 "client_cert", NVEE_LEN_N0_client_cert) +NVPARAM_VARPARAM(NPRO_0 "private_key", NVEE_LEN_N0_private_key) +NVPARAM_VARPARAM(NPRO_0 "private_key_passwd", NVEE_LEN_N0_private_key_passwd) + +NVPARAM_VARPARAM(NPRO_0 "dh_file", NVEE_LEN_N0_dh_file) +NVPARAM_VARPARAM(NPRO_0 "subject_match", NVEE_LEN_N0_subject_match) +NVPARAM_VARPARAM(NPRO_0 "altsubject_match", NVEE_LEN_N0_altsubject_match) +NVPARAM_VARPARAM(NPRO_0 "domain_suffix_match", NVEE_LEN_N0_domain_suffix_match) +NVPARAM_VARPARAM(NPRO_0 "domain_match", NVEE_LEN_N0_domain_match) +NVPARAM_VARPARAM(NPRO_0 "ca_cert2", NVEE_LEN_N0_ca_cert2) +NVPARAM_VARPARAM(NPRO_0 "ca_path2", NVEE_LEN_N0_ca_path2) +NVPARAM_VARPARAM(NPRO_0 "client_cert2", NVEE_LEN_N0_client_cert2) +NVPARAM_VARPARAM(NPRO_0 "private_key2", NVEE_LEN_N0_private_key2) +NVPARAM_VARPARAM(NPRO_0 "private_key2_passwd", NVEE_LEN_N0_private_key2_passwd) +NVPARAM_VARPARAM(NPRO_0 "dh_file2", NVEE_LEN_N0_dh_file2) +NVPARAM_VARPARAM(NPRO_0 "subject_match2", NVEE_LEN_N0_subject_match2) +NVPARAM_VARPARAM(NPRO_0 "altsubject_match2", NVEE_LEN_N0_altsubject_match2) +NVPARAM_VARPARAM(NPRO_0 "domain_suffix_match2", NVEE_LEN_N0_domain_suffix_match2) +NVPARAM_VARPARAM(NPRO_0 "domain_match2", NVEE_LEN_N0_domain_match2) + +NVPARAM_VARPARAM(NPRO_0 "pcsc", NVEE_LEN_N0_pcsc) +NVPARAM_VARPARAM(NPRO_0 "pin", NVEE_LEN_N0_pin) +NVPARAM_VARPARAM(NPRO_0 "engine_id", NVEE_LEN_N0_engine_id) +NVPARAM_VARPARAM(NPRO_0 "key_id", NVEE_LEN_N0_key_id) +NVPARAM_VARPARAM(NPRO_0 "cert_id", NVEE_LEN_N0_cert_id) +NVPARAM_VARPARAM(NPRO_0 "ca_cert_id", NVEE_LEN_N0_ca_cert_id) +NVPARAM_VARPARAM(NPRO_0 "key2_id", NVEE_LEN_N0_key2_id) +NVPARAM_VARPARAM(NPRO_0 "pin2", NVEE_LEN_N0_pin2) +NVPARAM_VARPARAM(NPRO_0 "engine2_id", NVEE_LEN_N0_engine2_id) +NVPARAM_VARPARAM(NPRO_0 "cert2_id", NVEE_LEN_N0_cert2_id) +NVPARAM_VARPARAM(NPRO_0 "ca_cert2_id", NVEE_LEN_N0_ca_cert2_id) +NVPARAM_VARPARAM(NPRO_0 "engine", NVEE_LEN_N0_engine) +NVPARAM_VARPARAM(NPRO_0 "engine2", NVEE_LEN_N0_engine2) + +NVPARAM_VARPARAM(NPRO_0 "openssl_ciphers", NVEE_LEN_N0_openssl_ciphers) +NVPARAM_VARPARAM(NPRO_0 "erp", NVEE_LEN_N0_erp) +NVPARAM_PARAM(NPRO_0 "FST_CONNECT", INT32_LEN) +NVPARAM_VARPARAM(NPRO_0 "ASSOC_CH", NVEE_LEN_N0_ASSOC_CH) + + #ifdef CONFIG_MACSEC +NVPARAM_VARPARAM(NPRO_0 "macsec_policy", NVEE_LEN_N0_macsec_policy) +NVPARAM_VARPARAM(NPRO_0 "macsec_integ_only", NVEE_LEN_N0_macsec_integ_only) +NVPARAM_VARPARAM(NPRO_0 "macsec_port", NVEE_LEN_N0_macsec_port) +NVPARAM_VARPARAM(NPRO_0 "mka_priority", NVEE_LEN_N0_mka_priority) + #endif /* CONFIG_MACSEC */ + +//= ============================================================================ +// Supplicant Network Profiles (N1_ : SOFTAP, P2P, MESH) +//= ============================================================================ +NVPARAM_PARAM(NPRO_1 "Profile", INT32_LEN) +NVPARAM_VARPARAM(NPRO_1 "ssid", NVEE_LEN_N1_ssid) +NVPARAM_VARPARAM(NPRO_1 "scan_ssid", NVEE_LEN_N1_scan_ssid) +NVPARAM_VARPARAM(NPRO_1 "bssid", NVEE_LEN_N1_bssid) +NVPARAM_VARPARAM(NPRO_1 "bssid_hint", NVEE_LEN_N1_bssid_hint) +NVPARAM_VARPARAM(NPRO_1 "bssid_blacklist", NVEE_LEN_N1_bssid_blacklist) +NVPARAM_VARPARAM(NPRO_1 "bssid_whitelist", NVEE_LEN_N1_bssid_whitelist) +NVPARAM_VARPARAM(NPRO_1 "psk", NVEE_LEN_N1_psk) +NVPARAM_VARPARAM(NPRO_1 "mem_only_psk", NVEE_LEN_N1_mem_only_psk) +NVPARAM_VARPARAM(NPRO_1 "sae_password", NVEE_LEN_N1_sae_password) +NVPARAM_VARPARAM(NPRO_1 "sae_password_id", NVEE_LEN_N1_sae_password_id) +NVPARAM_VARPARAM(NPRO_1 "proto", NVEE_LEN_N1_proto) +NVPARAM_VARPARAM(NPRO_1 "key_mgmt", NVEE_LEN_N1_key_mgmt) +NVPARAM_VARPARAM(NPRO_1 "bg_scan_period", NVEE_LEN_N1_bg_scan_period) +NVPARAM_VARPARAM(NPRO_1 "pairwise", NVEE_LEN_N1_pairwise) +NVPARAM_VARPARAM(NPRO_1 "group", NVEE_LEN_N1_group) +NVPARAM_VARPARAM(NPRO_1 "group_mgmt", NVEE_LEN_N1_group_mgmt) +NVPARAM_VARPARAM(NPRO_1 "auth_alg", NVEE_LEN_N1_auth_alg) +NVPARAM_VARPARAM(NPRO_1 "bgscan", NVEE_LEN_N1_bgscan) +NVPARAM_VARPARAM(NPRO_1 "autoscan", NVEE_LEN_N1_autoscan) +NVPARAM_VARPARAM(NPRO_1 "scan_freq", NVEE_LEN_N1_scan_freq) +NVPARAM_VARPARAM(NPRO_1 "freq_list", NVEE_LEN_N1_freq_list) + +NVPARAM_VARPARAM(NPRO_1 "eap", NVEE_LEN_N1_eap) +NVPARAM_VARPARAM(NPRO_1 "identity", NVEE_LEN_N1_identity) +NVPARAM_VARPARAM(NPRO_1 "anonymous_identity", NVEE_LEN_N1_anonymous_identity) +NVPARAM_VARPARAM(NPRO_1 "imsi_identity", NVEE_LEN_N1_imsi_identity) +NVPARAM_VARPARAM(NPRO_1 "password", NVEE_LEN_N1_password) +NVPARAM_VARPARAM(NPRO_1 "phase1", NVEE_LEN_N1_phase1) +NVPARAM_VARPARAM(NPRO_1 "phase2", NVEE_LEN_N1_phase2) +NVPARAM_VARPARAM(NPRO_1 "eapol_flags", NVEE_LEN_N1_eapol_flags) +NVPARAM_VARPARAM(NPRO_1 "wep_key0", NVEE_LEN_N1_wep_key0) +NVPARAM_VARPARAM(NPRO_1 "wep_key1", NVEE_LEN_N1_wep_key1) +NVPARAM_VARPARAM(NPRO_1 "wep_key2", NVEE_LEN_N1_wep_key2) +NVPARAM_VARPARAM(NPRO_1 "wep_key3", NVEE_LEN_N1_wep_key3) +NVPARAM_VARPARAM(NPRO_1 "wep_tx_keyidx", NVEE_LEN_N1_wep_tx_keyidx) +NVPARAM_VARPARAM(NPRO_1 "priority", NVEE_LEN_N1_priority) +NVPARAM_VARPARAM(NPRO_1 "eap_workaround", NVEE_LEN_N1_eap_workaround) +NVPARAM_VARPARAM(NPRO_1 "pac_file", NVEE_LEN_N1_pac_file) +NVPARAM_VARPARAM(NPRO_1 "fragment_size", NVEE_LEN_N1_fragment_size) +NVPARAM_VARPARAM(NPRO_1 "ocsp", NVEE_LEN_N1_ocsp) +NVPARAM_VARPARAM(NPRO_1 "sim_num", NVEE_LEN_N1_sim_num) +NVPARAM_PARAM(NPRO_1 "mode", INT32_LEN) +NVPARAM_VARPARAM(NPRO_1 "no_auto_peer", NVEE_LEN_N1_no_auto_peer) +NVPARAM_PARAM(NPRO_1 "frequency", INT32_LEN) +NVPARAM_VARPARAM(NPRO_1 "fixed_freq", NVEE_LEN_N1_fixed_freq) +NVPARAM_VARPARAM(NPRO_1 "acs", NVEE_LEN_N1_acs) +NVPARAM_VARPARAM(NPRO_1 "proactive_key_caching", NVEE_LEN_N1_proactive_key_caching) +NVPARAM_VARPARAM(NPRO_1 "disabled", NVEE_LEN_N1_disabled) +NVPARAM_VARPARAM(NPRO_1 "pbss", NVEE_LEN_N1_pbss) +NVPARAM_VARPARAM(NPRO_1 "wps_disabled", NVEE_LEN_N1_wps_disabled) +NVPARAM_VARPARAM(NPRO_1 "fils_dh_group", NVEE_LEN_N1_fils_dh_group) +NVPARAM_VARPARAM(NPRO_1 "ieee80211w", NVEE_LEN_N1_ieee80211w) +NVPARAM_VARPARAM(NPRO_1 "id_str", NVEE_LEN_N1_id_str) +NVPARAM_VARPARAM(NPRO_1 "ignore_broadcast_ssid", NVEE_LEN_N1_ignore_broadcast_ssid) +NVPARAM_VARPARAM(NPRO_1 "dtim_period", NVEE_LEN_N1_dtim_period) +NVPARAM_PARAM(NPRO_1 "beacon_int", INT32_LEN) +NVPARAM_VARPARAM(NPRO_1 "isolate", NVEE_LEN_N1_isolate) +NVPARAM_PARAM(NPRO_1 "ap_max_inactivity", INT32_LEN) +NVPARAM_VARPARAM(NPRO_1 "ap_power", NVEE_LEN_N1_ap_power) // auto, ... +NVPARAM_VARPARAM(NPRO_1 "update_identifier", NVEE_LEN_N1_update_identifier) +NVPARAM_VARPARAM(NPRO_1 "roaming_consortium_selection", NVEE_LEN_N1_roaming_consortium_selection) // MAX_ROAMING_CONS_OI_LEN +NVPARAM_VARPARAM(NPRO_1 "mac_addr", NVEE_LEN_N1_mac_addr) +NVPARAM_VARPARAM(NPRO_1 "mesh_basic_rates", NVEE_LEN_N1_mesh_basic_rates) +NVPARAM_VARPARAM(NPRO_1 "dot11MeshMaxRetries", NVEE_LEN_N1_dot11MeshMaxRetries) +NVPARAM_VARPARAM(NPRO_1 "dot11MeshRetryTimeout", NVEE_LEN_N1_dot11MeshRetryTimeout) +NVPARAM_VARPARAM(NPRO_1 "dot11MeshConfirmTimeout", NVEE_LEN_N1_dot11MeshConfirmTimeout) +NVPARAM_VARPARAM(NPRO_1 "dot11MeshHoldingTimeout", NVEE_LEN_N1_dot11MeshHoldingTimeout) +NVPARAM_VARPARAM(NPRO_1 "mesh_rssi_threshold", NVEE_LEN_N1_mesh_rssi_threshold) +NVPARAM_VARPARAM(NPRO_1 "wpa_ptk_rekey", NVEE_LEN_N1_wpa_ptk_rekey) +NVPARAM_VARPARAM(NPRO_1 "wpa_deny_ptk0_rekey", NVEE_LEN_N1_wpa_deny_ptk0_rekey) + +NVPARAM_VARPARAM(NPRO_1 "group_rekey", NVEE_LEN_N1_group_rekey) +NVPARAM_VARPARAM(NPRO_1 "dpp_connector", NVEE_LEN_N1_dpp_connector) +NVPARAM_VARPARAM(NPRO_1 "dpp_netaccesskey", NVEE_LEN_N1_dpp_netaccesskey) +NVPARAM_VARPARAM(NPRO_1 "dpp_netaccesskey_expiry", NVEE_LEN_N1_dpp_netaccesskey_expiry) +NVPARAM_VARPARAM(NPRO_1 "dpp_csign", NVEE_LEN_N1_dpp_csign) +NVPARAM_VARPARAM(NPRO_1 "owe_group", NVEE_LEN_N1_owe_group) +NVPARAM_VARPARAM(NPRO_1 "owe_only", NVEE_LEN_N1_owe_only) +NVPARAM_VARPARAM(NPRO_1 "owe_ptk_workaround", NVEE_LEN_N1_owe_ptk_workaround) +NVPARAM_VARPARAM(NPRO_1 "multi_ap_backhaul_sta", NVEE_LEN_N1_multi_ap_backhaul_sta) +NVPARAM_VARPARAM(NPRO_1 "ft_eap_pmksa_caching", NVEE_LEN_N1_ft_eap_pmksa_caching) +NVPARAM_VARPARAM(NPRO_1 "beacon_prot", NVEE_LEN_N1_beacon_prot) +NVPARAM_VARPARAM(NPRO_1 "transition_disable", NVEE_LEN_N1_transition_disable) +NVPARAM_VARPARAM(NPRO_1 "sae_pk", NVEE_LEN_N1_sae_pk) +NVPARAM_VARPARAM(NPRO_1 "wifi_mode", NVEE_LEN_N1_wifi_mode) +NVPARAM_VARPARAM(NPRO_1 "mixed_cell", NVEE_LEN_N1_mixed_cell) +NVPARAM_VARPARAM(NPRO_1 "ht", NVEE_LEN_N1_ht) +NVPARAM_VARPARAM(NPRO_1 "ht40", NVEE_LEN_N1_ht40) +NVPARAM_VARPARAM(NPRO_1 "disable_ht", NVEE_LEN_N1_disable_ht) +NVPARAM_VARPARAM(NPRO_1 "disable_ht40", NVEE_LEN_N1_disable_ht40) +NVPARAM_VARPARAM(NPRO_1 "disable_sgi", NVEE_LEN_N1_disable_sgi) +NVPARAM_VARPARAM(NPRO_1 "disable_ldpc", NVEE_LEN_N1_disable_ldpc) +NVPARAM_VARPARAM(NPRO_1 "ht40_intolerant", NVEE_LEN_N1_ht40_intolerant) +NVPARAM_VARPARAM(NPRO_1 "tx_stbc", NVEE_LEN_N1_tx_stbc) +NVPARAM_VARPARAM(NPRO_1 "rx_stbc", NVEE_LEN_N1_rx_stbc) +NVPARAM_VARPARAM(NPRO_1 "disable_max_amsdu", NVEE_LEN_N1_disable_max_amsdu) +NVPARAM_VARPARAM(NPRO_1 "ampdu_factor", NVEE_LEN_N1_ampdu_factor) +NVPARAM_VARPARAM(NPRO_1 "ampdu_density", NVEE_LEN_N1_ampdu_density) +NVPARAM_VARPARAM(NPRO_1 "ht_mcs", NVEE_LEN_N1_ht_mcs) + +NVPARAM_VARPARAM(NPRO_1 "max_oper_chwidth", NVEE_LEN_N1_max_oper_chwidth) +NVPARAM_VARPARAM(NPRO_1 "vht_center_freq1", NVEE_LEN_N1_vht_center_freq1) +NVPARAM_VARPARAM(NPRO_1 "vht_center_freq2", NVEE_LEN_N1_vht_center_freq2) + +NVPARAM_VARPARAM(NPRO_1 "vht", NVEE_LEN_N1_vht) +NVPARAM_VARPARAM(NPRO_1 "disable_vht", NVEE_LEN_N1_disable_vht) +NVPARAM_VARPARAM(NPRO_1 "vht_capa", NVEE_LEN_N1_vht_capa) +NVPARAM_VARPARAM(NPRO_1 "vht_capa_mask", NVEE_LEN_N1_vht_capa_mask) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_1", NVEE_LEN_N1_vht_rx_mcs_nss_1) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_2", NVEE_LEN_N1_vht_rx_mcs_nss_2) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_3", NVEE_LEN_N1_vht_rx_mcs_nss_3) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_4", NVEE_LEN_N1_vht_rx_mcs_nss_4) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_5", NVEE_LEN_N1_vht_rx_mcs_nss_5) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_6", NVEE_LEN_N1_vht_rx_mcs_nss_6) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_7", NVEE_LEN_N1_vht_rx_mcs_nss_7) +NVPARAM_VARPARAM(NPRO_1 "vht_rx_mcs_nss_8", NVEE_LEN_N1_vht_rx_mcs_nss_8) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_1", NVEE_LEN_N1_vht_tx_mcs_nss_1) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_2", NVEE_LEN_N1_vht_tx_mcs_nss_2) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_3", NVEE_LEN_N1_vht_tx_mcs_nss_3) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_4", NVEE_LEN_N1_vht_tx_mcs_nss_4) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_5", NVEE_LEN_N1_vht_tx_mcs_nss_5) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_6", NVEE_LEN_N1_vht_tx_mcs_nss_6) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_7", NVEE_LEN_N1_vht_tx_mcs_nss_7) +NVPARAM_VARPARAM(NPRO_1 "vht_tx_mcs_nss_8", NVEE_LEN_N1_vht_tx_mcs_nss_8) + +NVPARAM_VARPARAM(NPRO_1 "ca_cert", NVEE_LEN_N1_ca_cert) +NVPARAM_VARPARAM(NPRO_1 "ca_path", NVEE_LEN_N1_ca_path) +NVPARAM_VARPARAM(NPRO_1 "client_cert", NVEE_LEN_N1_client_cert) +NVPARAM_VARPARAM(NPRO_1 "private_key", NVEE_LEN_N1_private_key) +NVPARAM_VARPARAM(NPRO_1 "private_key_passwd", NVEE_LEN_N1_private_key_passwd) + +NVPARAM_VARPARAM(NPRO_1 "dh_file", NVEE_LEN_N1_dh_file) +NVPARAM_VARPARAM(NPRO_1 "subject_match", NVEE_LEN_N1_subject_match) +NVPARAM_VARPARAM(NPRO_1 "altsubject_match", NVEE_LEN_N1_altsubject_match) +NVPARAM_VARPARAM(NPRO_1 "domain_suffix_match", NVEE_LEN_N1_domain_suffix_match) +NVPARAM_VARPARAM(NPRO_1 "domain_match", NVEE_LEN_N1_domain_match) +NVPARAM_VARPARAM(NPRO_1 "ca_cert2", NVEE_LEN_N1_ca_cert2) +NVPARAM_VARPARAM(NPRO_1 "ca_path2", NVEE_LEN_N1_ca_path2) +NVPARAM_VARPARAM(NPRO_1 "client_cert2", NVEE_LEN_N1_client_cert2) +NVPARAM_VARPARAM(NPRO_1 "private_key2", NVEE_LEN_N1_private_key2) +NVPARAM_VARPARAM(NPRO_1 "private_key2_passwd", NVEE_LEN_N1_private_key2_passwd) +NVPARAM_VARPARAM(NPRO_1 "dh_file2", NVEE_LEN_N1_dh_file2) +NVPARAM_VARPARAM(NPRO_1 "subject_match2", NVEE_LEN_N1_subject_match2) +NVPARAM_VARPARAM(NPRO_1 "altsubject_match2", NVEE_LEN_N1_altsubject_match2) +NVPARAM_VARPARAM(NPRO_1 "domain_suffix_match2", NVEE_LEN_N1_domain_suffix_match2) +NVPARAM_VARPARAM(NPRO_1 "domain_match2", NVEE_LEN_N1_domain_match2) + +NVPARAM_VARPARAM(NPRO_1 "pcsc", NVEE_LEN_N1_pcsc) +NVPARAM_VARPARAM(NPRO_1 "pin", NVEE_LEN_N1_pin) +NVPARAM_VARPARAM(NPRO_1 "engine_id", NVEE_LEN_N1_engine_id) +NVPARAM_VARPARAM(NPRO_1 "key_id", NVEE_LEN_N1_key_id) +NVPARAM_VARPARAM(NPRO_1 "cert_id", NVEE_LEN_N1_cert_id) +NVPARAM_VARPARAM(NPRO_1 "ca_cert_id", NVEE_LEN_N1_ca_cert_id) +NVPARAM_VARPARAM(NPRO_1 "key2_id", NVEE_LEN_N1_key2_id) +NVPARAM_VARPARAM(NPRO_1 "pin2", NVEE_LEN_N1_pin2) +NVPARAM_VARPARAM(NPRO_1 "engine2_id", NVEE_LEN_N1_engine2_id) +NVPARAM_VARPARAM(NPRO_1 "cert2_id", NVEE_LEN_N1_cert2_id) +NVPARAM_VARPARAM(NPRO_1 "ca_cert2_id", NVEE_LEN_N1_ca_cert2_id) +NVPARAM_VARPARAM(NPRO_1 "engine", NVEE_LEN_N1_engine) +NVPARAM_VARPARAM(NPRO_1 "engine2", NVEE_LEN_N1_engine2) + +NVPARAM_VARPARAM(NPRO_1 "openssl_ciphers", NVEE_LEN_N1_openssl_ciphers) +NVPARAM_VARPARAM(NPRO_1 "erp", NVEE_LEN_N1_erp) + + #ifdef CONFIG_MACSEC +NVPARAM_VARPARAM(NPRO_1 "macsec_policy", NVEE_LEN_N1_macsec_policy) +NVPARAM_VARPARAM(NPRO_1 "macsec_integ_only", NVEE_LEN_N1_macsec_integ_only) +NVPARAM_VARPARAM(NPRO_1 "macsec_port", NVEE_LEN_N1_macsec_port) +NVPARAM_VARPARAM(NPRO_1 "mka_priority", NVEE_LEN_N1_mka_priority) + #endif /* CONFIG_MACSEC */ + +//= ============================================================================ +// Sleep Management(DPM) Profiles +//= ============================================================================ +NVPARAM_PARAM(NVR_KEY_DPM_MODE, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_KEEPALIVE_TIME, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_USER_WAKEUP_TIME, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_TIM_WAKEUP_TIME, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_AB_WF_CONN_RETRY, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_ABNORM_STOP, INT32_LEN) +NVPARAM_PARAM(NVR_KEY_DPM_IP_CONDITION, INT32_LEN) + +NVPARAM_PARAM(WIFI_CONN_WAIT_NAME, INT32_LEN) +NVPARAM_PARAM(DHCP_RSP_WAIT_NAME, INT32_LEN) +NVPARAM_PARAM(ARP_RSP_WAIT_NAME, INT32_LEN) +NVPARAM_PARAM(UNKNOWN_DPM_FAIL_WAIT_NAME, INT32_LEN) + +//= ============================================================================ +// TWT (Target Wake Time) Profiles +//= ============================================================================ +NVPARAM_PARAM("twt_auto_setup", UINT32_LEN) +NVPARAM_PARAM("twt_wake_int_mantissa", INT32_LEN) +NVPARAM_PARAM("twt_wake_int_exponent", INT32_LEN) +NVPARAM_PARAM("twt_wake_dur", UINT32_LEN) +NVPARAM_PARAM("twt_unannounced", UINT32_LEN) +NVPARAM_PARAM("twt_trigger_enable", UINT32_LEN) +NVPARAM_PARAM("twt_neg_type", UINT32_LEN) +NVPARAM_PARAM("twt_wake_dur_unit", UINT32_LEN) +NVPARAM_AREA_END() + +// syscfg +//= ============================================================================ +// syscfg : Network interface, etc +//= ============================================================================ +NVPARAM_AREA(syscfg, NVMS_GENERIC_PART) // supplicant about 6332+a +// TAG-NAME, MAX-LENGTH +NVPARAM_PARAM("INITWLAN", INT32_LEN) +NVPARAM_PARAM("SYSMODE", INT32_LEN) +NVPARAM_PARAM("SWITCH_SYSMODE", INT32_LEN) +NVPARAM_VARPARAM("0:MAC_SP", NVEE_LEN_0_MAC_SP) +NVPARAM_PARAM("0:NETMODE", INT32_LEN) +NVPARAM_VARPARAM("0:IP_Address", NVEE_LEN_0_IP_Address) +NVPARAM_VARPARAM("0:NETMASK", NVEE_LEN_0_NETMASK) +NVPARAM_VARPARAM("0:GATEWAY", NVEE_LEN_0_GATEWAY) +NVPARAM_VARPARAM("0:DNSSVR", NVEE_LEN_0_DNSSVR) +NVPARAM_VARPARAM("0:DNSSVR2", NVEE_LEN_0_DNSSVR2) +NVPARAM_PARAM("0:TEMP_STATIC_IP", INT32_LEN) + +NVPARAM_PARAM("1:NETMODE", INT32_LEN) +NVPARAM_VARPARAM("1:IP_Address", NVEE_LEN_1_IP_Address) +NVPARAM_VARPARAM("1:NETMASK", NVEE_LEN_1_NETMASK) +NVPARAM_VARPARAM("1:GATEWAY", NVEE_LEN_1_GATEWAY) +NVPARAM_VARPARAM("1:DNSSVR", NVEE_LEN_1_DNSSVR) +NVPARAM_VARPARAM("1:DNSSVR2", NVEE_LEN_1_DNSSVR2) + +/* DHCP Server */ +NVPARAM_PARAM("USEDHCPD", INT32_LEN) +NVPARAM_VARPARAM("1:DHCPD_S_IP", NVEE_LEN_1_DHCP_SERVER_START_IP) +NVPARAM_VARPARAM("1:DHCPD_E_IP", NVEE_LEN_1_DHCP_SERVER_END_IP) +NVPARAM_PARAM("1:DHCPD_TIME", INT32_LEN) +NVPARAM_VARPARAM("1:DHCPD_DNS", NVEE_LEN_1_DHCP_SERVER_DNS) + +NVPARAM_VARPARAM("1:DHCPV6D_S_IP", NVEE_LEN_1_DHCPV6_SERVER_START_IP) +NVPARAM_VARPARAM("1:DHCPV6D_E_IP", NVEE_LEN_1_DHCPV6_SERVER_END_IP) +NVPARAM_VARPARAM("1:DHCPV6D_DNS", NVEE_LEN_1_DHCPV6_SERVER_DNS) +NVPARAM_PARAM("1:DHCPV6D_TIME", INT32_LEN) + +/* DHCP Client hostname */ +NVPARAM_VARPARAM("DHCPC_HOSTNAME", NVEE_LEN_DHCPC_HOSTNAME) + +/* Timezone */ +NVPARAM_PARAM("TZONE", INT32_LEN) + +/* SNTP Server */ +NVPARAM_VARPARAM("SNTP_SVR", NVEE_LEN_SNTP_SERVER_DOMAIN) +NVPARAM_VARPARAM("SNTP_SVR_1", NVEE_LEN_SNTP_SERVER1_DOMAIN) +NVPARAM_VARPARAM("SNTP_SVR_2", NVEE_LEN_SNTP_SERVER2_DOMAIN) +NVPARAM_PARAM("SNTP_PERIOD", INT32_LEN) +NVPARAM_PARAM("SNTP_RUN_FLAG", INT32_LEN) + +/* UART Config */ +NVPARAM_PARAM("UART2_BAUDRATE", INT32_LEN) +NVPARAM_PARAM("UART2_BITS", INT32_LEN) +NVPARAM_PARAM("UART2_PARITY", INT32_LEN) +NVPARAM_PARAM("UART2_STOPBIT", INT32_LEN) +NVPARAM_PARAM("UART2_FLOWCTRL", INT32_LEN) + +NVPARAM_PARAM("UART3_BAUDRATE", INT32_LEN) +NVPARAM_PARAM("UART3_BITS", INT32_LEN) +NVPARAM_PARAM("UART3_PARITY", INT32_LEN) +NVPARAM_PARAM("UART3_STOPBIT", INT32_LEN) +NVPARAM_VARPARAM("UART3_FLOWCTRL", NVEE_LEN_UART3_FLOWCTRL) +NVPARAM_AREA_END() + +//= ============================================================================ +// Applicantion +//= ============================================================================ +NVPARAM_AREA(appcfg, NVMS_GENERIC_PART) + +// TAG-NAME, MAX-LENGTH +NVPARAM_PARAM("MQTT_TLS_NO_TIME_CHK", INT32_LEN) +NVPARAM_VARPARAM("MQTT_BROKER", NVEE_LEN_MQTT_BROKER) +NVPARAM_PARAM("MQTT_PORT", INT32_LEN) +NVPARAM_PARAM("MQTT_QOS", INT32_LEN) +NVPARAM_VARPARAM("MQTT_SUB_TOPIC", NVEE_LEN_MQTT_SUB_TOPIC) +NVPARAM_VARPARAM("MQTT_SUB_TOPIC0", NVEE_LEN_MQTT_SUB_TOPIC0) +NVPARAM_VARPARAM("MQTT_SUB_TOPIC1", NVEE_LEN_MQTT_SUB_TOPIC1) +NVPARAM_VARPARAM("MQTT_SUB_TOPIC2", NVEE_LEN_MQTT_SUB_TOPIC2) +NVPARAM_VARPARAM("MQTT_SUB_TOPIC3", NVEE_LEN_MQTT_SUB_TOPIC3) +NVPARAM_PARAM("MQTT_SUB_TOPIC_NUM", INT32_LEN) +NVPARAM_VARPARAM("MQTT_PUB_TOPIC", NVEE_LEN_MQTT_PUB_TOPIC) +NVPARAM_PARAM("MQTT_TLS", INT32_LEN) +NVPARAM_PARAM("MQTT_PING_PERIOD", INT32_LEN) +NVPARAM_PARAM("MQTT_AUTO", INT32_LEN) +NVPARAM_VARPARAM("MQTT_USERNAME", NVEE_LEN_MQTT_USERNAME) +NVPARAM_VARPARAM("MQTT_PASSWORD", NVEE_LEN_MQTT_PASSWORD) +NVPARAM_VARPARAM("MQTT_WILL_TOPIC", NVEE_LEN_MQTT_WILL_TOPIC) +NVPARAM_VARPARAM("MQTT_WILL_MSG", NVEE_LEN_MQTT_WILL_MSG) +NVPARAM_PARAM("MQTT_WILL_QOS", INT32_LEN) +NVPARAM_PARAM("MQTT_CLEAN_SESSION", INT32_LEN) +NVPARAM_PARAM("MQTT_VER311", INT32_LEN) +NVPARAM_VARPARAM("MQTT_SUB_CID", NVEE_LEN_MQTT_SUB_CID) +NVPARAM_VARPARAM("MQTT_PUB_CID", NVEE_LEN_MQTT_PUB_CID) +NVPARAM_PARAM("MQTT_TLS_ALPN_NUM", INT32_LEN) +NVPARAM_VARPARAM("MQTT_TLS_ALPN0", NVEE_LEN_MQTT_TLS_ALPN0) +NVPARAM_VARPARAM("MQTT_TLS_ALPN1", NVEE_LEN_MQTT_TLS_ALPN1) +NVPARAM_VARPARAM("MQTT_TLS_ALPN2", NVEE_LEN_MQTT_TLS_ALPN2) +NVPARAM_VARPARAM("MQTT_TLS_SNI", NVEE_LEN_MQTT_TLS_SNI) +NVPARAM_PARAM("MQTT_TLS_CSUIT_NUM", INT32_LEN) +NVPARAM_VARPARAM("MQTT_TLS_CSUIT", NVEE_LEN_MQTT_TLS_CSUIT) +NVPARAM_PARAM("MQTT_TLS_INCOMING", INT32_LEN) +NVPARAM_PARAM("MQTT_TLS_OUTGOING", INT32_LEN) +NVPARAM_PARAM("MQTT_TLS_AUTHMODE", INT32_LEN) +NVPARAM_PARAM("MQTT_TLS_VER", INT32_LEN) +NVPARAM_PARAM("MQTT_AT_MSG_FMT_VER", INT32_LEN) + +/* HTTP Client */ +NVPARAM_PARAM("HTTPC_TLS_VER", INT32_LEN) +NVPARAM_PARAM("HTTPC_TLS_AUTHMODE", INT32_LEN) +NVPARAM_PARAM("HTTPC_TLS_ALPN_NUM", INT32_LEN) +NVPARAM_VARPARAM("HTTPC_TLS_ALPN0", NVEE_LEN_HTTPC_TLS_ALPN0) +NVPARAM_VARPARAM("HTTPC_TLS_ALPN1", NVEE_LEN_HTTPC_TLS_ALPN1) +NVPARAM_VARPARAM("HTTPC_TLS_ALPN2", NVEE_LEN_HTTPC_TLS_ALPN2) +NVPARAM_VARPARAM("HTTPC_TLS_SNI", NVEE_LEN_HTTPC_TLS_SNI) + +/* HTTP Server */ +NVPARAM_PARAM("HTTPS_ENABLE", INT32_LEN) + +/* OTA update */ +NVPARAM_PARAM("OTA_TLS_VER", INT32_LEN) +NVPARAM_PARAM("OTA_TLS_AUTHMODE", INT32_LEN) +NVPARAM_PARAM("OTA_TLS_ALPN_NUM", INT32_LEN) +NVPARAM_VARPARAM("OTA_TLS_ALPN0", NVEE_LEN_OTA_TLS_ALPN0) +NVPARAM_VARPARAM("OTA_TLS_ALPN1", NVEE_LEN_OTA_TLS_ALPN1) +NVPARAM_VARPARAM("OTA_TLS_ALPN2", NVEE_LEN_OTA_TLS_ALPN2) +NVPARAM_VARPARAM("OTA_TLS_SNI", NVEE_LEN_OTA_TLS_SNI) +NVPARAM_PARAM("OTA_PROG_RTOS", INT32_LEN) +NVPARAM_PARAM("OTA_MODE", INT32_LEN) +NVPARAM_PARAM("OTA_EXPIRE", INT32_LEN) +NVPARAM_VARPARAM("OTA_URL", NVEE_LEN_URL) + +/* BLE-COMBO : BLE Provisioning - provisioning status */ +NVPARAM_VARPARAM("provisioned", NVEE_LEN_BLE_COMBO_PROVISIONED) +NVPARAM_VARPARAM("SERVER_IP", NVEE_LEN_BLE_COMBO_PROV_SRV_IP) +NVPARAM_VARPARAM("SERVER_PORT", NVEE_LEN_BLE_COMBO_PROV_SRV_PORT) + +/* BLE-COMBO : For Gas leak sample */ +NVPARAM_VARPARAM("sensor_started", NVEE_LEN_BLE_COMBO_SENSOR_STARTED) + +/* BLE-COMBO : For Sensor gateway sample */ +NVPARAM_VARPARAM("UDP_SERVER_IP", NVEE_LEN_BLE_COMBO_SENSOR_GW_UDP_SVR_IP) +NVPARAM_VARPARAM("UDP_SERVER_PORT", NVEE_LEN_BLE_COMBO_SENSOR_GW_UDP_SVR_PORT) + +/* BLE-COMBO : For TCPC DPM sample */ +NVPARAM_VARPARAM("TCPC_SERVER_IP", NVEE_LEN_BLE_COMBO_TCPC_SVR_IP) +NVPARAM_VARPARAM("TCPC_SERVER_PORT", NVEE_LEN_BLE_COMBO_TCPC_SVR_PORT) + +/* BLE-COMBO : For OTA */ +NVPARAM_VARPARAM("URI_RTOS", NVEE_LEN_BLE_COMBO_OTA_URI_RTOS) +NVPARAM_VARPARAM("URI_BLE", NVEE_LEN_BLE_COMBO_OTA_URI_BLE) + +/* ATCMD: TCP Server, Client, and UDP */ +NVPARAM_PARAM("0:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("2:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("3:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("4:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("5:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("6:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("7:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("8:ATC_NW_TR_CID", INT32_LEN) +NVPARAM_PARAM("9:ATC_NW_TR_CID", INT32_LEN) + +NVPARAM_PARAM("0:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("2:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("3:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("4:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("5:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("6:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("7:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("8:ATC_NW_TR_LPORT", INT32_LEN) +NVPARAM_PARAM("9:ATC_NW_TR_LPORT", INT32_LEN) + +NVPARAM_PARAM("0:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("2:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("3:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("4:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("5:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("6:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("7:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("8:ATC_NW_TR_PPORT", INT32_LEN) +NVPARAM_PARAM("9:ATC_NW_TR_PPORT", INT32_LEN) + +NVPARAM_PARAM("0:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("2:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("3:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("4:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("5:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("6:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("7:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("8:ATC_NW_TR_MAX_PEER", INT32_LEN) +NVPARAM_PARAM("9:ATC_NW_TR_MAX_PEER", INT32_LEN) + +NVPARAM_VARPARAM("0:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("1:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("2:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("3:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("4:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("5:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("6:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("7:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("8:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) +NVPARAM_VARPARAM("9:ATC_NW_TR_PIPADDR", NVEE_LEN_ATC_NW_TR_PIPADDR) + +NVPARAM_PARAM("0:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("2:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("3:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("4:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("5:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("6:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("7:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("8:ATC_NW_TR_IP_TYPE", INT32_LEN) +NVPARAM_PARAM("9:ATC_NW_TR_IP_TYPE", INT32_LEN) + +/* ATCMD: TLS Client */ +NVPARAM_PARAM("0:ATC_NW_TLS_CID", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLS_CID", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLS_ROLE", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLS_ROLE", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLS_PROFILE", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLS_PROFILE", INT32_LEN) +NVPARAM_VARPARAM("0:ATC_NW_TLSC_CA_NAME", NVEE_LEN_ATC_NW_TLSC_CA_CERT_NAME) +NVPARAM_VARPARAM("1:ATC_NW_TLSC_CA_NAME", NVEE_LEN_ATC_NW_TLSC_CA_CERT_NAME) +NVPARAM_VARPARAM("0:ATC_NW_TLSC_CERT_NAME", NVEE_LEN_ATC_NW_TLSC_CERT_NAME) +NVPARAM_VARPARAM("1:ATC_NW_TLSC_CERT_NAME", NVEE_LEN_ATC_NW_TLSC_CERT_NAME) +NVPARAM_VARPARAM("0:ATC_NW_TLSC_HOST_NAME", NVEE_LEN_ATC_NW_TLSC_HOST_NAME) +NVPARAM_VARPARAM("1:ATC_NW_TLSC_HOST_NAME", NVEE_LEN_ATC_NW_TLSC_HOST_NAME) +NVPARAM_PARAM("0:ATC_NW_TLSC_AUTH_MODE", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLSC_AUTH_MODE", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLSC_INCOMING", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLSC_INCOMING", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLSC_OUTGOING", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLSC_OUTGOING", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLSC_LPORT", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLSC_LPORT", INT32_LEN) +NVPARAM_PARAM("0:ATC_NW_TLSC_PPORT", INT32_LEN) +NVPARAM_PARAM("1:ATC_NW_TLSC_PPORT", INT32_LEN) +NVPARAM_VARPARAM("0:ATC_NW_TLSC_PIPADDR", NVEE_LEN_ATC_NW_TLSC_PIPADDR) +NVPARAM_VARPARAM("1:ATC_NW_TLSC_PIPADDR", NVEE_LEN_ATC_NW_TLSC_PIPADDR) + +// Apps WiFi Provisioning for Mobile App. +NVPARAM_VARPARAM("APP_THINGNAME", NVEE_LEN_APP_APPTHINGNAME) + +NVPARAM_PARAM("setsleepMode", INT32_LEN) +NVPARAM_PARAM("sleepmodertctime", INT32_LEN) + +/* AWS IoT Application */ +NVPARAM_VARPARAM(AWSIOT_CFG_THINGNAME, NVEE_LEN_AWSIOT_CFG_THINGNAME) +NVPARAM_VARPARAM(AWSIOT_CFG_FLEET_PROVISIONING_DEVICE_ID, NVEE_LEN_FLEET_PROVISIONING_DEVICE_ID) +NVPARAM_VARPARAM(AWSIOT_CFG_FLEET_PROVISIONING_TEMPLATE_NAME, NVEE_LEN_AWSIOT_CFG_FLEET_PROV_TEMPLATE_NAME) +NVPARAM_VARPARAM(AWSIOT_CFG_SAVED_IP_ADDRESS, NVEE_LEN_AWSIOT_CFG_SAVED_IP_ADDRESS) +NVPARAM_VARPARAM(AWSIOT_CFG_OTA_URL, NVEE_LEN_AWSIOT_CFG_OTA_URL) +NVPARAM_PARAM(AWSIOT_CFG_OTA_STATE, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_OTA_RESULT, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_OTA_FLAG, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_SLEEP_MODE2_RTC_TIME, INT32_LEN) +NVPARAM_VARPARAM(AWSIOT_CFG_FIRST_SNTP_TIME, NVEE_LEN_FIRST_SNTP_TIME) +NVPARAM_PARAM(AWSIOT_CFG_SNTP_SUCCESS_FLAG, UINT8_LEN) +NVPARAM_PARAM(AWSIOT_CFG_USE_FLEET_PROVISION, UINT8_LEN) +NVPARAM_VARPARAM(AWSIOT_CFG_BROKER_URL, NVEE_LEN_BROKER_URL) +NVPARAM_VARPARAM(AWSIOT_CFG_BOARD_FEATURE, NVEE_LEN_BOARD_FEATURE) +NVPARAM_PARAM(AWSIOT_CFG_LPORT, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_PORT, INT32_LEN) +NVPARAM_VARPARAM(AWSIOT_CFG_STOPIC, NVEE_LEN_STOPIC) +NVPARAM_VARPARAM(AWSIOT_CFG_PTOPIC, NVEE_LEN_PTOPIC) +NVPARAM_PARAM(AWSIOT_CFG_DPM_SLEEP_MODE, UINT8_LEN) +NVPARAM_PARAM(AWSIOT_CFG_USE_DPM, UINT8_LEN) +NVPARAM_PARAM(AWSIOT_CFG_RTC_TIME, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_DPM_KEEP_ALIVE_TIME, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_USER_WAKE_UP_TIME, INT32_LEN) +NVPARAM_PARAM(AWSIOT_CFG_TIM_WAKE_UP_TIME, INT32_LEN) +NVPARAM_VARPARAM(AWSIOT_CFG_MCU_WAKEUP_PORT, NVEE_LEN_MCU_WAKEUP_PORT) +NVPARAM_VARPARAM(AWSIOT_CFG_MCU_WAKEUP_PIN, NVEE_LEN_MCU_WAKEUP_PIN) +NVPARAM_PARAM(AWSIOT_CFG_PING_CHECK, UINT8_LEN) +NVPARAM_PARAM(AWSIOT_CFG_DPM_AUTO, UINT8_LEN) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_0, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_1, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_2, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_3, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_4, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_5, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_6, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_7, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_8, NVEE_LEN_THING_ATTRIBUTE) +NVPARAM_VARPARAM(AWSIOT_CFG_THING_ATTIRIBUTE_9, NVEE_LEN_THING_ATTRIBUTE) + +/* Azure IOT Application */ +NVPARAM_VARPARAM(APP_NVRAM_CONFIG_DEV_PRIMARY_KEY, NVEE_LEN_APP_NVRAM_CONFIG_DEV_PRIMARY_KEY) +NVPARAM_VARPARAM(APP_NVRAM_CONFIG_HOST_NAME, NVEE_LEN_APP_NVRAM_CONFIG_HOST_NAME) +NVPARAM_VARPARAM(APP_NVRAM_CONFIG_IOTHUB_CONN_STRING, NVEE_LEN_APP_NVRAM_CONFIG_IOTHUB_CONN_STRING) +NVPARAM_VARPARAM(APP_NVRAM_CONFIG_THINGNAME, NVEE_LEN_APP_NVRAM_CONFIG_THINGNAME) +NVPARAM_VARPARAM(APP_NVRAM_DEVICE_CONNECTION_STRING, NVEE_LEN_APP_NVRAM_DEVICE_CONNECTION_STRING) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_CURRENT_OTA_VERSION, NVEE_LEN_AZURE_NVRAM_CONFIG_CURRENT_OTA_VERSION) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_CURRENT_MCUOTA_VERSION, NVEE_LEN_AZURE_NVRAM_CONFIG_CURRENT_MCUOTA_VERSION) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_OTA_URL, NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_URL) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_OTA_VERSION, NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_VERSION) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_MCUOTA_VERSION, NVEE_LEN_AZURE_NVRAM_CONFIG_MCUOTA_VERSION) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_PORT, NVEE_LEN_AZURE_NVRAM_CONFIG_PORT) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_OTA_FLAG, NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_FLAG) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_OTA_STATE, NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_STATE) +NVPARAM_VARPARAM(AZURE_NVRAM_CONFIG_OTA_RESULT, NVEE_LEN_AZURE_NVRAM_CONFIG_OTA_RESULT) + +/* TCP Client application */ +NVPARAM_PARAM("TCPC_ACTIVE", NVEE_LEN_APP_TCPC_ACTIVE) +NVPARAM_VARPARAM("TCPC_PEER_IP_ADDR", NVEE_LEN_APP_TCPC_PEER_IP_ADDR) +NVPARAM_PARAM("TCPC_PEER_PORT", NVEE_LEN_APP_TCPC_PEER_PORT) +NVPARAM_PARAM("TCPC_SEND_PERIOD", NVEE_LEN_APP_TCPC_SEND_PERIOD) +NVPARAM_PARAM("TCPC_SEND_DATA_SIZE", NVEE_LEN_APP_TCPC_SEND_DATA_SIZE) +NVPARAM_PARAM("TCPC_AUTO_REST_EXIT", NVEE_LEN_APP_TCPC_AUTO_RESTART_AT_EXIT) +NVPARAM_PARAM("TCPC_KA_ENABLE", NVEE_LEN_APP_TCPC_KA_ENABLE) +NVPARAM_PARAM("TCPC_KA_IDLE_TIME", NVEE_LEN_APP_TCPC_KA_IDLE_TIME) +NVPARAM_PARAM("TCPC_KA_INTVL_TIME", NVEE_LEN_APP_TCPC_KA_INTVL_TIME) +NVPARAM_PARAM("TCPC_KA_MAX_PROBES", NVEE_LEN_APP_TCPC_KA_MAX_PROBES) + +/* ATCMD: Wake up source status */ +NVPARAM_PARAM("GPIO_WAKEUP_SOURCE_PIN", INT32_LEN) +NVPARAM_PARAM("GPIO_WAKEUP_SOURCE_EDGE_TYPE", INT32_LEN) +NVPARAM_AREA_END() + +//= ============================================================================= +// blecfg - for development BLE commands +//= ============================================================================= +NVPARAM_AREA(blecfg, NVMS_GENERIC_PART) + +/* Public BD address */ +NVPARAM_VARPARAM("PUBLIC_BD_ADDR", NVEE_LEN_BLECFG_BD_ADDR) + +NVPARAM_AREA_END() + +//= ============================================================================= +// blesec - for BLE Security +//= ============================================================================= + +NVPARAM_AREA(blesec, NVMS_GENERIC_PART) + +/* Public BD address */ +NVPARAM_PARAM("BOOT_DATA", NVEE_LEN_BLESEC_BOOT_DATA) +NVPARAM_PARAM("BONDING_DATA1", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA2", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA3", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA4", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA5", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA6", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_PARAM("BONDING_DATA7", NVEE_LEN_BLESEC_BONDING_DATA) + +// NVPARAM_PARAM("BDADDR2", NVEE_LEN_BLESEC_BONDING_DATA) +NVPARAM_AREA_END() + +//= ============================================================================= +// testcfg - for development test commands +//= ============================================================================= +NVPARAM_AREA(testcfg, NVMS_GENERIC_PART) + +// TAG-NAME, MAX-LENGTH + +/* Tx Power debug */ +NVPARAM_VARPARAM("DBG_TXPWR_L_2GO", NVEE_LEN_DBG_TXPWR_2G_OFDM) +NVPARAM_VARPARAM("DBG_TXPWR_L_2GD", NVEE_LEN_DBG_TXPWR_2G_DSSS) +NVPARAM_VARPARAM("DBG_TXPWR_L_5GP", NVEE_LEN_DBG_TXPWR_5G) +NVPARAM_VARPARAM("DBG_TXPWR_L_5GF", NVEE_LEN_DBG_TXPWR_5G_FLG) + +NVPARAM_PARAM("ldpc", INT32_LEN) +NVPARAM_PARAM("stbc", INT32_LEN) + +NVPARAM_VARPARAM("sku_id", STR_INT32_LEN) +NVPARAM_AREA_END() + +NVPARAM_AREA(wifiprofile, NVMS_GENERIC_PART) +NVPARAM_VARPARAM(WIFI_PROFILE_COUNTRY_CODE, NVEE_LEN_WIFI_country_code) +NVPARAM_PARAM(WIFI_PROFILE_SYS_MODE, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_BAND, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_CHANNEL, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_WIFI_MODE, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_PMF, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_ENABLE_DPM, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_DPM_DEBUG_RUNTIME_FLAG, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_DPM_DPM_KEEPALIVE_TIME, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_DPM_USER_WAKEUP_TIME, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_DPM_TIM_WAKEUP_COUNT, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_DPM_BLE_HIBERNATE, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_SSID_0, NVEE_LEN_WIFI_ssid_0) +NVPARAM_VARPARAM(WIFI_PROFILE_SSID_1, NVEE_LEN_WIFI_ssid_1) +NVPARAM_PARAM(WIFI_PROFILE_HIDDEN_SSID, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_PMF_0, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_PMF_1, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_SECURITY_0, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_SECURITY_1, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_ENCKEY_0, NVEE_LEN_WIFI_password_0) +NVPARAM_VARPARAM(WIFI_PROFILE_ENCKEY_1, NVEE_LEN_WIFI_password_1) +NVPARAM_VARPARAM(WIFI_PROFILE_SAE_GROUPS_0, NVEE_LEN_sae_groups) +NVPARAM_VARPARAM(WIFI_PROFILE_SAE_GROUPS_1, NVEE_LEN_sae_groups) +NVPARAM_VARPARAM(WIFI_PROFILE_WEPKEY0_0, NVEE_LEN_WIFI_wep_key) +NVPARAM_PARAM(WIFI_PROFILE_WEPINDEX_0, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_WEPTYPE_0, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_EAP_AUTH_MODE, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_EAP_PHASE2, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_EAP_ID, NVEE_LEN_WIFI_eap_id) +NVPARAM_VARPARAM(WIFI_PROFILE_EAP_PW, NVEE_LEN_WIFI_eap_pw) +NVPARAM_PARAM(WIFI_PROFILE_P2P_SSID_POSTFIX, NVEE_LEN__WIFI_p2p_ssid_postfix) +NVPARAM_PARAM(WIFI_PROFILE_P2P_GROUP_IDLE, NVEE_LEN__WIFI_p2p_group_idle) +NVPARAM_PARAM(WIFI_PROFILE_P2P_LISTEN_CH, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_P2P_GO_INTENT, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_P2P_FIND_TIMEOUT, NVEE_LEN_WIFI_p2p_find_timeout) +NVPARAM_PARAM(WIFI_PROFILE_NETMODE_0, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_NETMODE_1, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_IPADDR_0, NVEE_LEN_WIFI_ipaddress_0) +NVPARAM_VARPARAM(WIFI_PROFILE_IPADDR_1, NVEE_LEN_WIFI_ipaddress_1) +NVPARAM_VARPARAM(WIFI_PROFILE_NETMASK_0, NVEE_LEN_WIFI_subnetmask_0) +NVPARAM_VARPARAM(WIFI_PROFILE_NETMASK_1, NVEE_LEN_WIFI_subnetmask_1) +NVPARAM_VARPARAM(WIFI_PROFILE_GATEWAY_0, NVEE_LEN_WIFI_gateway_0) +NVPARAM_VARPARAM(WIFI_PROFILE_GATEWAY_1, NVEE_LEN_WIFI_gateway_1) +NVPARAM_VARPARAM(WIFI_PROFILE_DNSSVR_0, NVEE_LEN_WIFI_dns_0) +NVPARAM_VARPARAM(WIFI_PROFILE_DNSSVR_1, NVEE_LEN_WIFI_dns_1) +NVPARAM_PARAM(WIFI_PROFILE_COMPLETE, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_DNSSVR_2ND_0, PARAM_IPADDR_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_DNSSVR_2ND_1, PARAM_IPADDR_LEN) +NVPARAM_PARAM(WIFI_PROFILE_AP_MAX_INACTIVITY_1, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_AP_WMM_PS_1, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_AP_WMM_1, INT32_LEN) +NVPARAM_PARAM(WIFI_PROFILE_SCAN_CHAN_NUM, INT32_LEN) +NVPARAM_VARPARAM(WIFI_PROFILE_SCAN_CHAN_LIST, NVEE_LEN_WIFI_chan_list) +NVPARAM_PARAM(WIFI_PROFILE_AP_ENC_MODE_1, INT32_LEN) +NVPARAM_AREA_END() +#endif // (dg_configNVPARAM_ADAPTERv2 == 1) + +#endif /* PLATFORM_NVPARAM_H_ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sdk_defs.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sdk_defs.h new file mode 100644 index 000000000000..88cdafb6d3c6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sdk_defs.h @@ -0,0 +1,997 @@ +/** + * \addtogroup PLA_BSP_SYSTEM + * \{ + * \addtogroup BSP_DEFINITIONS SDK Platform Definitions + * + * \brief Platform definitions + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file sdk_defs.h + * + * @brief Central include header file with platform definitions. + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __SDK_DEFS_H__ + #define __SDK_DEFS_H__ + + #if !dg_configPTIM_APP + #include "bsp_api.h" + #include "config/bsp_definitions.h" + #include "config/bsp_sflash_map_ra6w1.h" + #include "config/bsp_defaults.h" + #endif + #include + #include + #include + + #ifdef __cplusplus +extern "C" { + #endif + + #ifdef __GNUC__ + #define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) + +/* assert gcc version is at least 4.9.3 */ + #if GCC_VERSION < 40903 + #error "Please use gcc version 4.9.3 or newer!" + #endif + #endif + + #include "bsp_api.h" + + #ifndef BSP_DEVICE_REVISION + #error "BSP_DEVICE_REVISION is not defined" + #endif + #ifndef DEVICE_REV_A + #error "DEVICE_REV_A is not defined" + #endif + #ifndef DEVICE_REV_B + #error "DEVICE_REV_B is not defined" + #endif + + #include "R7SA6W1CE.h" + + #if (DEVICE_FAMILY != DA1640X) + #error "Unknown device type -- check the value of dg_configDEVICE" + #endif /* DEVICE_FAMILY */ + +/************************ + * Memory map + ************************/ + +/** + * \brief Remapped device base address. + */ + #if (DEVICE_FAMILY == DA1640X) + #define MEMORY_REMAPPED_BASE 0x00000000UL + #define MEMORY_REMAPPED_END 0x08000000UL + #endif /* DEVICE_FAMILY */ + +/** + * \brief Remapped device memory size. + */ + #define MEMORY_REMAPPED_SIZE (MEMORY_REMAPPED_END - MEMORY_REMAPPED_BASE) + +/** + * \brief ROM base address. + */ + #if (DEVICE_FAMILY == DA1640X) + #define MEMORY_ROM_BASE 0xF020000UL + #define MEMORY_ROM_END (MEMORY_ROM_BASE + 0x40000UL) + #endif /* DEVICE_FAMILY */ + +/** + * \brief ROM memory size. + */ + #define MEMORY_ROM_SIZE (MEMORY_ROM_END - MEMORY_ROM_BASE) + +/** + * \brief OTP memory base address. + */ + #if (DEVICE_FAMILY == DA1640X) + #define MEMORY_OTP_BASE 0x400F2000UL + #define MEMORY_OTP_END 0x400F2800UL + #endif /* DEVICE_FAMILY */ + +/** + * \brief OTP memory size. + */ + #define MEMORY_OTP_SIZE (MEMORY_OTP_END - MEMORY_OTP_BASE) + +/** + * \brief SYSTEM RAM base address. + */ + #if (DEVICE_FAMILY == DA1640X) + #define MEMORY_SYSRAM_BASE 0x20000000UL + #define MEMORY_SYSRAM_END (MEMORY_SYSRAM_BASE + 0xc0000UL) + #endif /* DEVICE_FAMILY */ + +/** + * \brief SYSTEM RAM size. + */ + #define MEMORY_SYSRAM_SIZE (MEMORY_SYSRAM_END - MEMORY_SYSRAM_BASE) + +/** + * \brief CACHE RAM base address. + */ + #if (DEVICE_FAMILY == DA1640X) + #define MEMORY_CACHERAM_BASE 0x18A00000UL + #define MEMORY_CACHERAM_END 0x18A10000UL + #endif /* DEVICE_FAMILY */ + +/** + * \brief CACHE RAM size. + */ + #define MEMORY_CACHERAM_SIZE (MEMORY_CACHERAM_END - MEMORY_CACHERAM_BASE) + +/** + * \brief QSPI Flash base address. + */ + #if (DEVICE_FAMILY == DA1640X) + +/* + * OQSPI AHB-C(ode) bus (cached). Accesses through this bus + * are restricted according to CACHE_FLASH_REG. + */ + #define MEMORY_OQSPIC_BASE (0x0A000000) // before (0x19000000UL) + #define MEMORY_OQSPIC_END (0x0DFFFFFF) // before (0x1D000000UL) + + #define MEMORY_OQSPIC_SIZE (MEMORY_OQSPIC_END - MEMORY_OQSPIC_BASE) + +/* + * OQSPI AHB-S(ystem) bus (Not cached). Accesses through this bus + * are not affected by CACHE_FLASH_REG. + */ + #define MEMORY_OQSPIC_S_BASE (0x2A000000) // before (0x3A000000UL) + #define MEMORY_OQSPIC_S_END (0x2DFFFFFF) // before (0x3E000000UL) + +/* + * QSPI AHB-C(ode) bus (cached). Accesses through this bus + * are restricted according to CACHE_FLASH_REG. + */ + #define MEMORY_QSPIF_BASE (0x24000000UL) + #define MEMORY_QSPIF_END (MEMORY_QSPIF_BASE + 0x4000000UL) + +/* + * QSPI Data + */ + #define MEMORY_QSPID_BASE (0x24000000UL) + #define MEMORY_QSPID_END (0x28000000UL) + #define MEMORY_QSPID_SIZE (MEMORY_QSPID_END - MEMORY_QSPID_BASE) + +/* + * DCACHE controller + */ + #define MEMORY_DCACHE_BASE (0x21014000UL) + #define MEMORY_DCACHE_SIZE (0x2000UL) + #define MEMORY_DCACHE_END (MEMORY_DCACHE_BASE + MEMORY_DCACHE_SIZE) + + #endif /* DEVICE_FAMILY */ + +/** + * \brief QSPI Flash memory size. + */ + #define MEMORY_QSPIF_SIZE (MEMORY_QSPIF_END - MEMORY_QSPIF_BASE) + +/** + * \brief The Sector Size of the OQSPI and QSPI flash memories + */ + #define FLASH_SECTOR_SIZE (0x1000) + +/** + * \brief The base address for accessing the Flash memory connected to OQSPI + * + * The base address is used in oqspi_automode. Automode is using a single zero-based address region + * for accessing the Flash devices connected to OQSPI and QSPI controllers (OQSPIC and QSPIC). + * The defined address sub-regions are: + * Address region 1: starting at OQSPI_MEM1_VIRTUAL_BASE_ADDR + * When Flash address is in region 1 then the device connected to OQSPIC is accessed. + * The maximum region size handled by each QSPI controller in automode is 128MBytes. + * The default value of each region size is 0x8000000, allowing 128MBytes region + * for each controller. + */ + #ifndef OQSPI_MEM1_VIRTUAL_BASE_ADDR + #define OQSPI_MEM1_VIRTUAL_BASE_ADDR (0x00000000) + #endif + +/** + * \brief Address is in OQSPI_MEM1 virtual memory region + */ + #define IS_OQSPI_MEM1_VIRTUAL_ADDRESS(_a) WITHIN_RANGE((_a), OQSPI_MEM1_VIRTUAL_BASE_ADDR, \ + (OQSPI_MEM1_VIRTUAL_BASE_ADDR + MEMORY_OQSPIC_SIZE)) + +/** + * \brief The base address for accessing the Flash memory connected to QSPIC + * + * The base address is used in qspi_automode. + */ + #ifndef QSPI_MEM1_VIRTUAL_BASE_ADDR + #define QSPI_MEM1_VIRTUAL_BASE_ADDR (OQSPI_MEM1_VIRTUAL_BASE_ADDR + MEMORY_OQSPIC_SIZE) + #endif + +/** + * \brief OTP User Data Encryption Keys memory base address + */ + #define WITHIN_RANGE(_a, _s, _e) (((uint32_t) (_a) >= (uint32_t) (_s)) && ((uint32_t) (_a) < (uint32_t) (_e))) + +/** + * \brief Address is in the remapped memory region + */ + #define IS_REMAPPED_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_REMAPPED_BASE, MEMORY_REMAPPED_END) + +/** + * \brief Address is in the ROM region + */ + #define IS_ROM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_ROM_BASE, MEMORY_ROM_END) + +/** + * \brief Address is in the SYSTEM RAM region + */ + #define IS_SYSRAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_SYSRAM_BASE, MEMORY_SYSRAM_END) + +/** + * \brief Address is in the CACHE RAM region + */ + #define IS_CACHERAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_CACHERAM_BASE, MEMORY_CACHERAM_END) + +/** + * \brief Address is in the QSPI Flash memory region + */ + #define IS_QSPIF_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OQSPIC_BASE, MEMORY_OQSPIC_S_END) + + #if (DEVICE_FAMILY == DA1640X) + +/** + * \brief Address is in the QSPI AHB-S(ystem) memory region + */ + #define IS_QSPIF_S_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIF_BASE, MEMORY_QSPIF_END) + #endif /* DEVICE_FAMILY */ + + #if (DEVICE_FAMILY == DA1640X) + +/** + * \brief Address is in the OQSPI Flash memory region + */ + #define IS_OQSPIC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OQSPIC_BASE, MEMORY_OQSPIC_END) + +/** + * \brief Address is in the OQSPI AHB-S(ystem) memory region + */ + #define IS_OQSPIC_S_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OQSPIC_S_BASE, MEMORY_OQSPIC_S_END) + + #endif /* DEVICE_FAMILY */ + +/** + * \brief Zero-initialized data retained memory attribute + */ + +// TIN_HACK_WIFI + #define __RETAINED + #define __RETAINED_1 + +/** + * \brief Initialized data retained memory attribute + */ + #define __RETAINED_RW __attribute__((section("retention_mem_init"))) + +/** + * \brief Uninitialized data retained memory attribute. Used for variables that should + * not be initialized during startup. + */ + #define __RETAINED_UNINIT __attribute__((section("retention_mem_uninit"))) + +/** + * \brief Constant data retained memory attribute + */ + #define __RETAINED_CONST_INIT __attribute__((section("retention_mem_const"))) + +/** + * \brief Text retained memory attribute + */ + #if ((dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) && (dg_configEXEC_MODE == MODE_IS_CACHED)) + #define __RETAINED_CODE __attribute__((section(".ram_code_from_flash"))) __attribute__((noinline)) \ + __attribute__((optimize("no-tree-switch-conversion"))) + #define __MTB_CODE __attribute__((section("mtb_text_retained"))) __attribute__((noinline)) __attribute__(( \ + optimize( \ + "no-tree-switch-conversion"))) + #else + #define __RETAINED_CODE + #define __MTB_CODE __attribute__((section("mtb_text_retained"))) + #endif + +/** + * \brief Attribute to silence warnings about unused parameters/variables/function + */ + #define __UNUSED __attribute__((unused)) + +/** + * \brief Attribute to tell the compiler to consider a symbol as externally visible (for LTO) + */ + #define __LTO_EXT __attribute__((externally_visible)) + + #if dg_configUSE_HW_SYS + +// Forward declaration +__RETAINED_CODE void hw_sys_assert_trigger_gpio(void); + + #else + #define hw_sys_assert_trigger_gpio() + #endif + +/** + * \brief Assert as warning macro + * + * \note Active only while in development mode + */ + #if (DEVICE_FAMILY == DA1640X) + #define ASSERT_WARNING(a) \ + { \ + if (!(a)) { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + printf(" >> ASSERT_WARNING %s:%d \n", __func__, __LINE__);} \ + } \ + } + +/** + * \brief Assert as error macro + * + */ + #define ASSERT_ERROR(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + printf(" >> ASSERT_ERROR %s:%d \n", __func__, __LINE__); \ + } \ + } \ + else { \ + if (!(a)) { \ + __ASM volatile ("cpsid i" : : : "memory"); \ + __BKPT(2); \ + } \ + } \ + } + +/** + * \brief Assert as warning macro when the system is still uninitialized + * + * \note Active only while in development mode. The SW cursor is not activated. + */ + #define ASSERT_WARNING_UNINIT(a) \ + { \ + if (!(a)) { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + printf(" >> ASSERT_WARNING_UNINIT %s:%d \n", __func__, __LINE__);} \ + } \ + } + +/** + * \brief Assert as error macro when the system is still uninitialized + * + * \note The SW cursor is not activated. + */ + #define ASSERT_ERROR_UNINIT(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + printf(" >> ASSERT_ERROR_UNINIT %s:%d \n", __func__, __LINE__); \ + } \ + } \ + else { \ + if (!(a)) { \ + __disable_irq(); \ + __BKPT(2); \ + } \ + } \ + } + #endif /* DEVICE_FAMILY */ + +/** + * \brief Macro to disable all interrupts + * + * This macro must always be used with GLOBAL_INT_RESTORE(). E.g. + * + * \code{.c} + * GLOBAL_INT_DISABLE(); + * ... code to be executed with interrupts disabled ... + * GLOBAL_INT_RESTORE(); + * \endcode + * + * \sa GLOBAL_INT_RESTORE + */ + #define GLOBAL_INT_DISABLE() \ + do { \ + unsigned int __l_irq_rest; \ + __ASM volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (__l_irq_rest) \ + : \ + : "r1" \ + ); \ + /*DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION);*/ + +/** + * \brief Macro to restore all interrupts + * + * This macro must always be used after GLOBAL_INT_DISABLE(). E.g. + * + * \code{.c} + * GLOBAL_INT_DISABLE(); + * ... code to be executed with interrupts disabled ... + * GLOBAL_INT_RESTORE(); + * \endcode + * + * \sa GLOBAL_INT_DISABLE + */ + #define GLOBAL_INT_RESTORE() \ + if (__l_irq_rest == 0) { \ + /*DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION);*/ \ + } \ + __ASM volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (__l_irq_rest) \ + : \ + ); \ +} \ + while (0) + + #define containingoffset(address, type, field) ((type *) ((uint8 *) (address) - (size_t) (&((type *) 0)->field))) + +/** + * \brief Macro the minimum of two values + * + * \param[in] a First value + * \param[in] b Second value + */ + #ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) + #endif + +/** + * \brief Macro the maximum of two values + * + * \param[in] a First value + * \param[in] b Second value + */ + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/** + * \brief Macro to swap the bytes of a 16-bit variable + * + * \param[in] a The 16-bit variable + */ + #if defined(__GNUC__) + #define SWAP16(a) __builtin_bswap16(a) + #else + #define SWAP16(a) ((a << 8) | (a >> 8)) + #endif + +/** + * \brief Macro to swap the bytes of a 32-bit variable + * + * \param[in] a The 32-bit variable + */ + #if defined(__GNUC__) + #define SWAP32(a) __builtin_bswap32(a) + #else + #define SWAP32(a) ((a >> 24 & 0xff) | (a >> 8 & 0xff00) | (a << 8 & 0xff0000) | \ + (a << 24 & 0xff000000)) + #endif + + #if defined(__GNUC__) + #define DEPRECATED __attribute__((deprecated)) + #else + #pragma message "Deprecated macro must be implemented for this compiler" + #define DEPRECATED + #endif + + #if defined(__GNUC__) + #define DEPRECATED_MSG(msg) __attribute__((deprecated(msg))) + #else + #pragma message "Deprecated macro must be implemented for this compiler" + #define DEPRECATED_MSG(msg) + #endif + +/* The following exist in ROM code */ +void __aeabi_memcpy(void * dest, const void * src, size_t n); +void __aeabi_memmove(void * dest, const void * src, size_t n); +void __aeabi_memset(void * dest, size_t n, int c); + +/** + * \brief Optimized memcpy + */ + #define OPT_MEMCPY __aeabi_memcpy + +/** + * \brief Optimized memmove + */ + #define OPT_MEMMOVE __aeabi_memmove + +/** + * \brief Optimized memset + */ + #define OPT_MEMSET(s, c, n) __aeabi_memset(s, n, c) + +/** + * \brief Access register field mask. + * + * Returns a register field mask (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->SYS_STAT_REG; + * + * if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) { + * ... + * \endcode + */ + #define REG_MSK(base, reg, field) \ + (base ## _ ## reg ## _ ## field ## _Msk) + +/** + * \brief Access register field position. + * + * Returns a register field position (aimed to be used with local variables). + */ + #define REG_POS(base, reg, field) \ + (base ## _ ## reg ## _ ## field ## _Pos) + +/** + * \brief Access register field value. + * + * Returns a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * int counter; + * tmp = CRG_TOP->TRIM_CTRL_REG; + * counter = REG_GET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); + * ... + * \endcode + */ + #define REG_GET_FIELD(base, reg, field, var) \ + ((var & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Set register field value. + * + * Sets a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->TRIM_CTRL_REG; + * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10); + * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2); + * CRG_TOP->TRIM_CTRL_REG = tmp; + * ... + * \endcode + */ + #define REG_SET_FIELD(base, reg, field, var, val) \ + var = ((var & ~((base ## _ ## reg ## _ ## field ## _Msk))) | \ + (((val) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Set memory field value. + * + * Sets a memory field value using a mask (aimed to be used with local variables). + * e.g. + * \code + * uint32_t tmp = *(volatile uint32_t *)0x50000000; + * + * RAW_SET_FIELD(tmp, 0x1UL, 1); + * ... + * \endcode + */ + #define RAW_SET_FIELD(mem, mask, val) \ + mem = ((mem & ~((mask))) | (((val) << (__builtin_ctz(mask))) & (mask))) + +/** + * \brief Clear register field value. + * + * Clears a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->TRIM_CTRL_REG; + * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); + * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp); + * CRG_TOP->TRIM_CTRL_REG = tmp; + * ... + * \endcode + */ + #define REG_CLR_FIELD(base, reg, field, var) \ + var &= ~(base ## _ ## reg ## _ ## field ## _Msk) + +/** + * \brief Get the address of a register value by index (provided a register interval) + * + * \note The register interval should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by + * the interval value (in bytes) to find the actual offset of the register. + * + * Returns a register address value by index + */ + #define REG_GET_ADDR_INDEXED(base, reg, interval, index) \ + ((&base->reg) + (((intptr_t) index) * ((interval) / sizeof(base->reg)))) + +/** + * \brief Return the value of a register field by index (provided a register interval). + * + * e.g. + * \code + * uint16_t val; + * uint16_t index = 2 + * + * val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index) + * + * ... + * \endcode + * + * \note The register interval should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by + * the interval value (in bytes) to find the actual offset of the register. + * + */ + #define REG_GETF_INDEXED(base, reg, field, interval, index) \ + (((*REG_GET_ADDR_INDEXED(base, reg, interval, index)) & \ + (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Return the value of a register field. + * + * e.g. + * \code + * uint32_t val; + * + * val = REG_GETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N); + * ... + * \endcode + */ + #define REG_GETF(base, reg, field) \ + (((base->reg) & (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Return the value of a memory field using a mask. + * + * e.g. + * \code + * uint32_t val; + * + * val = RAW_GETF(0x50000000, 0x1UL); + * ... + * \endcode + */ + #define RAW_GETF(addr, mask) \ + ((*(volatile uint32_t *) (addr) & (mask)) >> (__builtin_ctz(mask))) + +/** + * \brief Set the value of a register field. + * + * e.g. + * \code + * + * REG_SETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, new_value); + * ... + * \endcode + */ + #define REG_SETF(base, reg, field, new_val) \ + base->reg = ((base->reg & ~(base ## _ ## reg ## _ ## field ## _Msk)) | \ + ((base ## _ ## reg ## _ ## field ## _Msk) &((new_val) << (base ## _ ## reg ## _ ## field ## _Pos)))) + +/** + * \brief Set the value of a memory field. + * + * e.g. + * \code + * + * RAW_SETF(0x50000000, 0x1UL, 1); + * ... + * \endcode + */ + #define RAW_SETF(addr, mask, val) \ + (*(volatile uint32_t *) (addr)) = ((*(volatile uint32_t *) (addr) & ~(mask)) | \ + ((mask) & ((val) << __builtin_ctz(mask)))) + +/** + * \brief Set a bit of a register. + * + * e.g. + * \code + * + * REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + * ... + * \endcode + */ + #define REG_SET_BIT(base, reg, field) \ + do { \ + base->reg |= (1 << (base ## _ ## reg ## _ ## field ## _Pos)); \ + } while (0) + +/** + * \brief Clear a bit of a register. + * + * e.g. + * \code + * + * REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + * ... + * \endcode + */ + #define REG_CLR_BIT(base, reg, field) \ + do { \ + base->reg &= ~(base ## _ ## reg ## _ ## field ## _Msk); \ + } while (0) + +/** + * \brief Sets register bits, indicated by the mask, to a value. + * + * e.g. + * \code + * REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); + * \endcode + */ + #define REG_SET_MASKED(base, reg, mask, value) \ + do { \ + base->reg = (base->reg & ~(mask)) | ((value) & (mask)); \ + } while (0) + +/** + * \brief Sets memory bits, indicated by the mask, to a value. + * + * e.g. + * \code + * RAW_SET_MASKED(0x50000000, 0xFF00, 0x1818); + * \endcode + */ + #define RAW_SET_MASKED(addr, mask, value) \ + do { \ + (*(volatile uint32_t *) (addr)) = ((*(volatile uint32_t *) (addr)) & ~(mask)) | ((value) & (mask)); \ + } while (0) + +/** + * \brief Sets 16-bit wide register bits, indicated by the field, to a value v. + */ + #define BITS16(base, reg, field, v) \ + ((uint16) (((uint16) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Sets 32-bit wide register bits, indicated by the field, to a value v. + */ + #define BITS32(base, reg, field, v) \ + ((uint32) (((uint32) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Reads 16-bit wide register bits, indicated by the field, to a variable v. + */ + #define GETBITS16(base, reg, v, field) \ + ((uint16) (((uint16) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Reads 32-bit wide register bits, indicated by the field, to a variable v. + */ + #define GETBITS32(base, reg, v, field) \ + ((uint32) (((uint32) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Macro to enable the debugger + * + */ + #define ENABLE_DEBUGGER \ + do { \ + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ + } while (0) + +/** + * \brief Macro to disable the debugger + * + */ + #define DISABLE_DEBUGGER \ + do { \ + REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ + } while (0) + +extern void pll_off(void); + +/** + * \brief Macro to cause a software reset + * + */ + #define SWRESET \ + do { \ + REG_SETF(CRG_TOP, PMU_CTRL_REG, PHY_SLEEP, 1); \ + REG_SETF(CRG_TOP, PMU_CTRL_REG, MAC_SLEEP, 1); \ + pll_off(); \ + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, SW_RESET); \ + } while (0) + +/** + * \brief Macro to cause a POR reset. it reset the DCORE + * + */ + #define PORRESET \ + do { \ + if (bsp_is_chip_revision_a()) \ + { \ + RTC->LDO_ENABLE_REG_b.LDO_EN_BOOST_PWR_OFF = 1; \ + } \ + RTC->DCDC_CNTL_OFF_REG = 0; \ + RTC->DCDC_CNTL_OFF_REG = 0x03; \ + } while (0) + + #define BIT0 0x00000001 + #define BIT1 0x00000002 + #define BIT2 0x00000004 + #define BIT3 0x00000008 + #define BIT4 0x00000010 + #define BIT5 0x00000020 + #define BIT6 0x00000040 + #define BIT7 0x00000080 + + #define BIT8 0x00000100 + #define BIT9 0x00000200 + #define BIT10 0x00000400 + #define BIT11 0x00000800 + #define BIT12 0x00001000 + #define BIT13 0x00002000 + #define BIT14 0x00004000 + #define BIT15 0x00008000 + + #define BIT16 0x00010000 + #define BIT17 0x00020000 + #define BIT18 0x00040000 + #define BIT19 0x00080000 + #define BIT20 0x00100000 + #define BIT21 0x00200000 + #define BIT22 0x00400000 + #define BIT23 0x00800000 + + #define BIT24 0x01000000 + #define BIT25 0x02000000 + #define BIT26 0x04000000 + #define BIT27 0x08000000 + #define BIT28 0x10000000 + #define BIT29 0x20000000 + #define BIT30 0x40000000 + #define BIT31 0x80000000 + +typedef unsigned char uint8; // 8 bits +typedef char int8; // 8 bits +typedef unsigned short uint16; // 16 bits +typedef short int16; // 16 bits +typedef unsigned long uint32; // 32 bits +typedef long int32; // 32 bits +typedef unsigned long long uint64; // 64 bits +typedef long long int64; // 64 bits + +/* See also "Data Types" on pag. 21 of the (Doulos) Cortex-M0 / SoC 1.0 training documentation. */ +typedef unsigned char BYTE; // 8 bits = Byte +typedef unsigned short HWORD; // 16 bits = Halfword +typedef unsigned long WORD; // 32 bits = Word +typedef long long DWORD; // 64 bits = Doubleword + +//////////////////////////////////////////////////////////////////// + +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef signed short SHORT; +typedef unsigned short USHORT; +typedef signed int INT; +typedef unsigned int UINT; +typedef signed long LONG; +typedef unsigned long ULONG; + +typedef void VOID; + +typedef char INT8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef int INT32; +typedef unsigned int UINT32; +typedef long long INT64; +typedef unsigned long long UINT64; + +typedef void * HANDLE; + +typedef unsigned int OPTION; +typedef unsigned long UNSIGNED; +typedef long SIGNED; + +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef signed char s8; +typedef signed int s32; + +/****************************************************************************** + * + * Macro + * + ******************************************************************************/ + + #ifndef NX_PORT_H + #define TRUE (1) + #define FALSE (0) + #else + #define TRUE pdTRUE + #define FALSE pdFALSE + #endif + + #define MBYTE (1024UL * 1024UL) + #define KBYTE (1024UL) + + #define MHz (1000UL * 1000UL) + #define KHz (1000UL) + + #ifndef RA6W1_UNUSED_ARG + #define RA6W1_UNUSED_ARG(x) (void) x + #endif // RA6W1_UNUSED_ARG + +/****************************************************************************** + * + * Callback + * + ******************************************************************************/ + +typedef VOID (* USR_CALLBACK)(VOID *); + +//////////////////////////////////////////////////////////////////// + + #if dg_configAUTOTEST_ENABLE + #define autotest_printf(fmt, arg ...) printf(fmt, ## arg); + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* __SDK_DEFS_H__ */ + +/** + * \} + * \} + */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sys_feature.h b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sys_feature.h new file mode 100644 index 000000000000..bae9a69b2458 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/bsp_w/mcu/ra6w1/sys_feature.h @@ -0,0 +1,178 @@ +/** + **************************************************************************************** + * + * @file sys_feature.h + * + * @brief Definition for System features + * + * Copyright (c) 2023 Renesas Electronics. All rights reserved. + * + * This software ("Software") is owned by Renesas Electronics. + * + * By using this Software you agree that Renesas Electronics retains all + * intellectual property and proprietary rights in and to this Software and any + * use, reproduction, disclosure or distribution of the Software without express + * written permission or a license agreement from Renesas Electronics is + * strictly prohibited. This Software is solely for use on or in conjunction + * with Renesas Electronics products. + * + * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE + * SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. EXCEPT AS OTHERWISE + * PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL + * RENESAS ELECTRONICS BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THE SOFTWARE. + * + **************************************************************************************** + */ + +#ifndef __SYS_FEATURE_H__ +#define __SYS_FEATURE_H__ + +#define COUNTRY_CODE_DEFAULT "KR" +#define CHANNEL_AUTO 0 +#define CHANNEL_DEFAULT CHANNEL_AUTO +#define REPLY_FAIL "FAIL" + +/* WiFi Direct */ +#define WIFI_DIR_LISTEN_CH_DFLT CHANNEL_AUTO +#define WIFI_DIR_OPERATION_CH_DFLT CHANNEL_AUTO +#define WIFI_DIR_GO_INTENT_DFLT 3 + +enum E_AUTH_MODE +{ + E_AUTH_MODE_NONE = 1, + E_AUTH_MODE_WEP, + E_AUTH_MODE_WPA, + E_AUTH_MODE_RSN, + E_AUTH_MODE_WPA_RSN, +#ifdef __SUPPORT_WPA3_SAE__ + E_AUTH_MODE_SAE, + E_AUTH_MODE_RSN_SAE, +#endif /* __SUPPORT_WPA3_SAE__ */ +#ifdef __SUPPORT_WPA3_OWE__ + E_AUTH_MODE_OWE, +#endif /* __SUPPORT_WPA3_OWE__ */ +#ifdef __SUPPORT_WPA_ENTERPRISE__ + E_AUTH_MODE_ENT, + #ifdef __SUPPORT_WPA3_ENTERPRISE__ + E_AUTH_MODE_WPA2_WPA3_ENT, + E_AUTH_MODE_WPA3_ENT, + #ifdef __SUPPORT_WPA3_ENTERPRISE_192B__ + E_AUTH_MODE_WPA3_ENT_192B, + #endif // __SUPPORT_WPA3_ENTERPRISE_192B__ + #endif // __SUPPORT_WPA3_ENTERPRISE__ +#endif // __SUPPORT_WPA_ENTERPRISE__ + E_AUTH_MODE_MAX +}; + +#ifdef __SUPPORT_WPA_ENTERPRISE__ +enum E_EAP_AUTH_MODE +{ + E_EAP_AUTH_MODE_NONE = 0, + E_EAP_AUTH_MODE_PEAP_TTLS_FAST, + E_EAP_AUTH_MODE_PEAP, + E_EAP_AUTH_MODE_TTLS, + E_EAP_AUTH_MODE_FAST, + E_EAP_AUTH_MODE_TLS, + E_EAP_AUTH_MODE_MAX +}; + +enum E_EAP_PHASE2_MODE +{ + E_EAP_PHASE2_MODE_NONE, + E_EAP_PHASE2_MODE_MSCHAPV2_N_GTC, + E_EAP_PHASE2_MODE_MSCHAPV2, + E_EAP_PHASE2_MODE_GTC, + E_EAP_PHASE2_MODE_TLS, + E_EAP_PHASE2_MODE_MAX +}; + +#endif // __SUPPORT_WPA_ENTERPRISE__ + +enum E_ENCRYP_MODE +{ + E_ENCRYP_MODE_TKIP = 1, + E_ENCRYP_MODE_CCMP, + E_ENCRYP_MODE_TKIP_CCMP +#ifdef __SUPPORT_WPA3_ENTERPRISE_192B__ + , + E_ENCRYP_MODE_GCMP_256 +#endif // __SUPPORT_WPA3_ENTERPRISE_192B__ +}; + +enum E_WEP_KEY_TYPE +{ + WEP_KEY_TYPE_ASCII = 1, + WEP_KEY_TYPE_HEXA +}; + +enum E_WEP_KEY_IDX +{ + E_WEP_KEY_IDX_1 = 1, + E_WEP_KEY_IDX_2, + E_WEP_KEY_IDX_3, + E_WEP_KEY_IDX_4, +}; + +enum E_WEP_KEY_BIT +{ + WEP_KEY_64BIT = 1, + WEP_KEY_128BIT +}; + +/* NET MODE */ +enum E_NETMODE +{ + E_NETMODE_DYNAMIC_IP = 1, + E_NETMODE_STATIC_IP +}; + +/* PSK_KEY_TYPE */ +enum E_PSK_KEY_TYPE +{ + E_PSK_KEY_ASCII = 1, + E_PSK_KEY_HEXA +}; + +/* SNTP Client */ +enum E_SNTP_CLIENT +{ + E_SNTP_CLIENT_STOP = 1, + E_SNTP_CLIENT_START +}; + +enum E_CFG_ENABLE +{ + E_DISABLE, + E_ENABLE +}; + +/* For Console Password ************************************/ + +#define NVR_KEY_PASSWORD "PASSWORD" +#define NVR_KEY_PASSWORD_SVC "PASSWORD_SVC" + +/*** !!! Notice !!! ******/ +/* Customer can change default Password ... */ +#define DEFAULT_PASSWORD "rrq61000" +#define PW_TIMEOUT 12000 /* tick : 2 min */ +#define DFLT_PASSWORD_SVC 1 + +/***********************************************************/ + +/* External global functions */ +extern void reboot_func(unsigned int flag); + +#if CFG_PMGR +extern int RM_PMGR_W_dpm_is_wakeup(void); + +#endif /* CFG_PMGR */ + +#endif /* __SYS_FEATURE_H__ */ + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_adc_w/r_adc_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_adc_w/r_adc_w.c new file mode 100644 index 000000000000..65ef9a62a006 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_adc_w/r_adc_w.c @@ -0,0 +1,1171 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "r_adc_w_cfg.h" +#include "r_adc_w.h" +#include "../bsp/mcu/ra6w1/config/bsp_device_definitions.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ADC_W_OPEN (0x41444342) /* ADC_W in ascii */ +#define AUX_ADC_INITIAL_VALUE (0x1582) +#define ADC_W_12BIT_MASK (0xFFFU) +#define ADC_W_5BIT_MASK (0x1FU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if ADC_W_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_adc_w_scan_cfg_check(adc_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_adc_w_open_cfg_check(adc_cfg_t const * const p_cfg); +static fsp_err_t r_adc_w_SensorWakeup_cfg_check(adc_w_instance_ctrl_t * const p_ctrl); + +#endif + +#if ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE +void adc_w_scan_end_isr(void); + +#endif + +static void r_adc_w_ldo_enable(adc_channel_t channel); + +/*********************************************************************************************************************** + * Interrupt Service Routines + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* ADC_W Implementation of ADC. */ +const adc_api_t g_adc_on_adc_w = +{ + .open = R_ADC_W_Open, + .scanCfg = R_ADC_W_ScanCfg, + .infoGet = R_ADC_W_InfoGet, + .scanStart = R_ADC_W_ScanStart, + .scanGroupStart = R_ADC_W_ScanGroupStart, + .scanStop = R_ADC_W_ScanStop, + .scanStatusGet = R_ADC_W_StatusGet, + .read = R_ADC_W_Read, + .read32 = R_ADC_W_Read32, + .close = R_ADC_W_Close, + .calibrate = R_ADC_W_Calibrate, + .offsetSet = R_ADC_W_OffsetSet, + .callbackSet = R_ADC_W_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup ADC_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the ADC_W peripheral. + * If interrupt is enabled, the function registers a callback function for notifying the user when ADC + * interrupt event occurrs. + * Implements @ref adc_api_t::open. + * + * @retval FSP_SUCCESS Module is ready for use. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_ALREADY_OPEN The instance control structure has already been opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED A callback is provided, but the interrupt is not enabled. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + + /* Verify the configuration parameters are valid */ + fsp_err_t err = r_adc_w_open_cfg_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify this unit has not already been initialized */ + FSP_ERROR_RETURN(ADC_W_OPEN != p_instance_ctrl->opened, FSP_ERR_ALREADY_OPEN); + + /* If a callback is used, then make sure an interrupt is enabled */ + if (NULL != p_cfg->p_callback) + { + FSP_ERROR_RETURN(p_cfg->scan_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + /* Mark driver as opened by initializing it to "ADC_W" in its ASCII equivalent for this unit. */ + p_instance_ctrl->opened = ADC_W_OPEN; +#endif + + /* Save configurations. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + adc_w_extended_cfg_t * p_ext = (adc_w_extended_cfg_t *) p_cfg->p_extend; + uint16_t div = p_ext->conversion_clockdiv; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* The default resolution is 12 bit */ + RTC->XADC12_CNTL_REG = AUX_ADC_INITIAL_VALUE; + + if (ADC_RESOLUTION_12_BIT == p_instance_ctrl->p_cfg->resolution) + { + RTC->XADC12_CNTL_REG_b.AUXADC12_BITNUM = 0x0; + } + else if (ADC_RESOLUTION_10_BIT == p_instance_ctrl->p_cfg->resolution) + { + RTC->XADC12_CNTL_REG_b.AUXADC12_BITNUM = 0x1; + } + else if (ADC_RESOLUTION_7_BIT == p_instance_ctrl->p_cfg->resolution) + { + RTC->XADC12_CNTL_REG_b.AUXADC12_BITNUM = 0x2; + } + else if (ADC_RESOLUTION_4_BIT == p_instance_ctrl->p_cfg->resolution) + { + RTC->XADC12_CNTL_REG_b.AUXADC12_BITNUM = 0x3; + } + else + { + ; + } + + CRG_TOP->CLK_AMBA_REG_b.PERI_CLK_ENABLE = 1; + + /* PLL divider enable for Aux 15Mhz */ + CRG_TOP->CLK_CTRL_REG_b.PLL_AUX_ENABLE = 0; + CRG_TOP->CLK_AMBA_REG_b.AUX_CLK_ENABLE = 0; + + CRG_PER->RESET_CLK_COM_REG_b.AUXADC_ENABLE = 1; + + CRG_TOP->AUX_CLK_DIV_REG = (uint32_t) (div - 1); + + /* PLL divider enable for Aux 15Mhz */ + CRG_TOP->CLK_CTRL_REG_b.PLL_AUX_ENABLE = 1; + CRG_TOP->CLK_AMBA_REG_b.AUX_CLK_ENABLE = 1; + CRG_PER->SET_CLK_COM_REG_b.AUXADC_ENABLE = 1; + + FSP_CRITICAL_SECTION_EXIT; + + AUXADC->XADC12B_CTRL_REG_b.ADC12B_RESET = 0; + AUXADC->XADC12B_CTRL_REG_b.ADC12B_PWRDOEN = 0; + AUXADC->XADC12B_CTRL_REG_b.ADC12B_DATA_FORMAT = 1; + + AUXADC->XADC12B_DMA_EN_REG = 0; + AUXADC->XADC12B_INT_THR_OVER_REG = 0xffff; + AUXADC->XADC12B_INT_THR_UNDER_REG = 0x0; + AUXADC->XADC12B_INT_THR_DIFF_REG = 0xfff0; + AUXADC->XADC12B_THR_INTR_MASK_REG = 0; + AUXADC->XADC12B_FIFO_INTR_MASK_REG = 0; + + /* For each channel */ + uint32_t scan_mask = 0U; + for (uint32_t i = 0U; i < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; i++) + { + if (NULL != p_ext->p_channel_cfgs[i]) + { + /* Enable conversion for the channel. */ + scan_mask |= (1U << i); + } + } + + p_instance_ctrl->scan_mask = 0; + p_instance_ctrl->scan_cfg_mask = scan_mask; + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the enabled channels of the ADC. Channel specific settings are set in this function. Pass a pointer to + * @ref adc_w_scan_cfg_t to p_extend. + * Implements @ref adc_api_t::scanCfg. + * + * @retval FSP_SUCCESS Channel specific settings applied. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_scan_cfg) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + adc_w_scan_cfg_t const * p_channel_scan_cfg = (adc_w_scan_cfg_t const *) p_scan_cfg; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_channel_scan_cfg); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + fsp_err_t err = r_adc_w_scan_cfg_check(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify all channels to enable are configured. */ + FSP_ASSERT(p_instance_ctrl->scan_cfg_mask == (p_channel_scan_cfg->scan_mask | p_instance_ctrl->scan_cfg_mask)); +#endif + + adc_w_extended_cfg_t * p_ext = (adc_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint16_t div = p_ext->conversion_clockdiv; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* PLL divider enable for Aux 15Mhz */ + CRG_TOP->CLK_CTRL_REG_b.PLL_AUX_ENABLE = 0; + CRG_TOP->CLK_AMBA_REG_b.AUX_CLK_ENABLE = 0; + + CRG_PER->RESET_CLK_COM_REG_b.AUXADC_ENABLE = 1; + + CRG_TOP->AUX_CLK_DIV_REG = (uint32_t) (div - 1); + + /* PLL divider enable for Aux 15Mhz */ + CRG_TOP->CLK_CTRL_REG_b.PLL_AUX_ENABLE = 1; + CRG_TOP->CLK_AMBA_REG_b.AUX_CLK_ENABLE = 1; + CRG_PER->SET_CLK_COM_REG_b.AUXADC_ENABLE = 1; + + FSP_CRITICAL_SECTION_EXIT; + + uint32_t enabled_ch_mask = p_channel_scan_cfg->scan_mask; + +#if ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE + + /* This feature is not available. */ + AUXADC->XADC12B_INT_THR_DIFF_REG = 0; + + for (uint8_t channel = ADC_CHANNEL_0; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (enabled_ch_mask & (1U << channel)) + { + if (p_ext->p_channel_cfgs[channel]->interrupt_mode_thd) + { + AUXADC->XADC12B_THR_INTR_MASK_REG |= (p_ext->p_channel_cfgs[channel]->interrupt_mode_thd << channel); + + if (ADC_W_INTERRUPT_THD_OVER == p_ext->p_channel_cfgs[channel]->interrupt_mode_thd) + { + AUXADC->XADC12B_INT_THR_OVER_REG = p_ext->upper_bound_limit; + } + else if (ADC_W_INTERRUPT_THD_UNDER == p_ext->p_channel_cfgs[channel]->interrupt_mode_thd) + { + AUXADC->XADC12B_INT_THR_UNDER_REG = p_ext->lower_bound_limit; + } + else + { + ; + } + } + else + { + AUXADC->XADC12B_THR_INTR_MASK_REG &= + (uint32_t) ~(p_ext->p_channel_cfgs[channel]->interrupt_mode_thd << channel); + } + + if (p_ext->p_channel_cfgs[channel]->interrupt_mode_fifo) + { + AUXADC->XADC12B_FIFO_INTR_MASK_REG |= (p_ext->p_channel_cfgs[channel]->interrupt_mode_fifo << channel); + } + else + { + AUXADC->XADC12B_FIFO_INTR_MASK_REG &= + (uint32_t) ~(p_ext->p_channel_cfgs[channel]->interrupt_mode_fifo << channel); + } + } + } + + AUXADC->XADC12B_THR_INTR_CLR_REG = 0xfff; + + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->scan_end_irq, p_instance_ctrl->p_cfg->scan_end_ipl, p_instance_ctrl); +#endif + + uint8_t used_channel_num = 0; + + for (uint8_t channel = ADC_CHANNEL_0; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (enabled_ch_mask & (1U << channel)) + { + used_channel_num++; + + r_adc_w_ldo_enable(channel); + + if (ADC_W_DMA_ENABLED == p_ext->p_channel_cfgs[channel]->dma_en) + { + AUXADC->XADC12B_DMA_EN_REG |= 1 << channel; + } + else + { + AUXADC->XADC12B_DMA_EN_REG &= (uint32_t) ~(1 << channel); + } + } + } + + /* When using multiple channels at the same time, the ADC sample data can be stored correctly in the FIFO + * with latency of at least 4-cycles after the channel change. */ + if (1 == used_channel_num) + { + AUXADC->XADC12B_ST_SAMPLE_REG_b.XADC12B_SP_INTERVAL = 0; + } + else + { + AUXADC->XADC12B_ST_SAMPLE_REG_b.XADC12B_SP_INTERVAL = 4; + } + + /* Update the enabled channels. */ + p_instance_ctrl->scan_mask = p_channel_scan_cfg->scan_mask; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + + /* Mark driver as initialized */ + p_instance_ctrl->initialized = ADC_W_OPEN; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback. + * Implements adc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_CallbackSet (adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void * const p_context, + adc_callback_args_t * const p_callback_memory) +{ + adc_w_instance_ctrl_t * p_ctrl = (adc_w_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_callback_memory); + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_callback); + FSP_ERROR_RETURN(ADC_W_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function starts the software triggered scan. + * + * @pre Call R_ADC_W_ScanCfg after R_ADC_W_Open before starting a scan. + * @retval FSP_SUCCESS Scan started. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + * @retval FSP_ERR_NOT_INITIALIZED ADC_W is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_ScanStart (adc_ctrl_t * p_ctrl) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + AUXADC->SWITCHING_MODE_REG = AUXADC->SWITCHING_MODE_REG & (uint32_t) 0xff; + + for (uint8_t channel = ADC_CHANNEL_0; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (p_instance_ctrl->scan_mask & (1U << channel)) + { + AUXADC->SWITCHING_MODE_REG = AUXADC->SWITCHING_MODE_REG & (uint32_t) ~((1 << channel)); + AUXADC->SWITCHING_MODE_REG = AUXADC->SWITCHING_MODE_REG | (uint32_t) ((1 << (channel + 4))); + } + } + + AUXADC->SWITCHING_MODE_REG = AUXADC->SWITCHING_MODE_REG | (uint32_t) (0x100); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::scanGroupStart is not supported on the ADC_W. Use scanStart instead. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_ScanGroupStart (adc_ctrl_t * p_ctrl, adc_group_mask_t group_id) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(group_id); + + /* Return the unsupported error. */ + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Immediately stops converters. + * This function will abort conversions. + * + * @retval FSP_SUCCESS Scan stopped. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_ScanStop (adc_ctrl_t * p_ctrl) +{ + /* Perform parameter checking */ +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + AUXADC->SWITCHING_MODE_REG = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the status of any scan process that was started. + * + * + * @retval FSP_SUCCESS Module status stored in the provided pointer p_status. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_StatusGet (adc_ctrl_t * p_ctrl, adc_status_t * p_status) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + uint32_t status; + + status = AUXADC->SWITCHING_MODE_REG & 0xF0; + p_status->state = (status ? ADC_STATE_SCAN_IN_PROGRESS : ADC_STATE_IDLE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads conversion results from a channel register. + * + * + * @retval FSP_SUCCESS Data read into provided p_data. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + FSP_ERROR_RETURN(((ADC_CHANNEL_0 <= reg_id) && (reg_id <= ADC_CHANNEL_3)), FSP_ERR_ASSERTION); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + switch (reg_id) + { + case ADC_CHANNEL_0: + { + *p_data = AUXADC->FIFO0_DATA_CURR_REG_b.FIFO0_CURR_DATA; + break; + } + + case ADC_CHANNEL_1: + { + *p_data = AUXADC->FIFO1_DATA_CURR_REG_b.FIFO1_CURR_DATA; + break; + } + + case ADC_CHANNEL_2: + { + *p_data = AUXADC->FIFO2_DATA_CURR_REG_b.FIFO2_CURR_DATA; + break; + } + + case ADC_CHANNEL_3: + { + *p_data = AUXADC->FIFO3_DATA_CURR_REG_b.FIFO3_CURR_DATA; + break; + } + + default: + { + break; + } + } + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads conversion results from a channel register into a 32-bit result. + * + * + * @retval FSP_SUCCESS Data read into provided p_data. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + * @retval FSP_ERR_NOT_INITIALIZED ADC_W is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data) +{ + uint16_t result = 0U; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_data); +#endif + + fsp_err_t err = R_ADC_W_Read(p_ctrl, reg_id, &result); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + *p_data = result; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns the address of the lowest number configured channel, determine the size of data that must be read. + * + * @retval FSP_SUCCESS Information stored in p_adc_info. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + * @retval FSP_ERR_NOT_INITIALIZED ADC_W is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_adc_info); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Retrieve the scan mask of active channels from the control block */ + uint32_t scan_mask = p_instance_ctrl->scan_mask; + + if (0U == scan_mask) + { + p_adc_info->length = 0U; + p_adc_info->p_address = NULL; + } + else + { + /* Determine the lowest channel that is configured. */ + uint32_t temp_mask = 0U; + int32_t lowest_channel = -1; + while (0U == temp_mask) + { + lowest_channel++; + temp_mask = (uint32_t) (scan_mask & (1U << lowest_channel)); + } + + /* Determine the size of data that must be read to read all the channels. */ + uint32_t enabled_channel_num = 0; + for (uint32_t temp_channel = 0; temp_channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; temp_channel++) + { + if (scan_mask & (1U << temp_channel)) + { + enabled_channel_num++; + } + } + + p_adc_info->length = enabled_channel_num; + p_adc_info->p_address = (uint32_t *) (ADC_CH0_DMAC_SRC_ADDR + lowest_channel); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function ends any scan or select mode in progress, disables interrupts, and removes power to the A/D peripheral. + * + * @retval FSP_SUCCESS Module closed. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Close (adc_ctrl_t * p_ctrl) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Mark driver as closed */ + p_instance_ctrl->opened = 0U; + p_instance_ctrl->initialized = 0U; +#endif +#if ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE + + /* Disable interrupts. */ + if (p_instance_ctrl->p_cfg->scan_end_irq > 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->scan_end_irq); + } +#endif +#if !ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE && !ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + AUXADC->XADC12B_INT_THR_OVER_REG = 0xffff; + AUXADC->XADC12B_INT_THR_UNDER_REG = 0x0; + AUXADC->XADC12B_INT_THR_DIFF_REG = 0xfff0; + + AUXADC->XADC12B_THR_INTR_MASK_REG = 0; + AUXADC->XADC12B_FIFO_INTR_MASK_REG = 0; + + if (p_instance_ctrl->p_callback) + { + p_instance_ctrl->p_callback = NULL; + } + + AUXADC->SWITCHING_MODE_REG = 0; + + AUXADC->XADC12B_DMA_EN_REG = 0; + + AUXADC->XADC12B_CTRL_REG_b.ADC12B_RESET = 1; + AUXADC->XADC12B_CTRL_REG_b.ADC12B_PWRDOEN = 1; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO0 = 0; + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO1 = 0; + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO2 = 0; + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO3 = 0; + + CRG_TOP->CLK_AMBA_REG_b.AUX_CLK_ENABLE = 0; + + RTC->XADC12_THR01_REG = 0; + RTC->XADC12_THR23_REG = 0; + + RTC->XADC12_TIMER_SET_REG_b.X12_CLK_TMR_CNT_SRC = 0; + RTC->XADC12_TIMER_SET_REG_b.AX12B_TIMER_VAL = 0xf; + RTC->XADC12_TIMER_SET_REG_b.ASWCH_CTRL = 0; + + RTC->XADC12_SP_NUM_REG_b.ADC_SMLP_NUM_AVR = 0; + + /* Disable sensor detection */ + RTC->XADC12_TIMER_SET_REG_b.SENSOR_DETECT_ACT = 0; + + /* Disable CLOCK for adc sensor and pulse cnt functions */ + RTC->ENABLE_CTRL_REG_b.REAL_CNT_LOAD = 0; + + FSP_CRITICAL_SECTION_EXIT; + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::calibrate is not supported on the ADC_W. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_Calibrate (adc_ctrl_t * const p_ctrl, void const * p_extend) +{ + FSP_PARAMETER_NOT_USED(p_extend); + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_ERROR_LOG(FSP_ERR_UNSUPPORTED); + + /* Return the unsupported error. */ + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::offsetSet is not supported on the ADC_W. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(reg_id); + FSP_PARAMETER_NOT_USED(offset); + FSP_ERROR_LOG(FSP_ERR_UNSUPPORTED); + + /* Return the unsupported error. */ + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Prepare ADC_W to enter sensor wakeup mode. + * This function must be called before entering sleep mode. + * + * @param[in] p_ctrl Pointer to the ADC control block + * + * @retval FSP_SUCCESS ADC is configured to request sensor wakeup mode. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN ADC_W is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_SensorWakeupcfg (adc_ctrl_t * const p_ctrl) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Verify that the ADC instance is in the correct mode for requesting sensor wakeup mode. */ + fsp_err_t err = r_adc_w_SensorWakeup_cfg_check(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + R_BSP_SoftwareDelay(120, BSP_DELAY_UNITS_MICROSECONDS); +#endif + + adc_w_extended_cfg_t * p_ext = (adc_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint8_t aswch_reg = 0; + + for (uint8_t channel = 0U; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (NULL != p_ext->p_channel_cfgs[channel]) + { + if (ADC_W_SENSOR_WAKEUP_ENABLED == p_ext->p_channel_cfgs[channel]->sensorwakeup_en) + { + aswch_reg |= (1 << 4); + aswch_reg = aswch_reg & ((uint8_t) ~(1 << (channel))); + aswch_reg = aswch_reg | ((uint8_t) (1 << (channel))); + + RTC->XADC12_TIMER_SET_REG_b.ASWCH_CTRL = ADC_W_5BIT_MASK & aswch_reg; + + switch (channel) + { + case ADC_CHANNEL_0: + { + RTC->XADC12_THR01_REG_b.XADC12_THR_LEVEL0_CH0 = ADC_W_12BIT_MASK & + p_ext->p_channel_cfgs[channel]->thd_value; + RTC->XADC12_THR01_REG_b.XADC12_THR_CONFIG_CH0 = p_ext->p_channel_cfgs[channel]->threshold_mode; + r_adc_w_ldo_enable(ADC_CHANNEL_0); + break; + } + + case ADC_CHANNEL_1: + { + RTC->XADC12_THR01_REG_b.XADC12_THR_LEVEL1_CH2 = ADC_W_12BIT_MASK & + p_ext->p_channel_cfgs[channel]->thd_value; + RTC->XADC12_THR01_REG_b.XADC12_THR_CONFIG_CH1 = p_ext->p_channel_cfgs[channel]->threshold_mode; + r_adc_w_ldo_enable(ADC_CHANNEL_1); + break; + } + + case ADC_CHANNEL_2: + { + RTC->XADC12_THR23_REG_b.XADC12_THR_LEVEL2_CH2 = ADC_W_12BIT_MASK & + p_ext->p_channel_cfgs[channel]->thd_value; + RTC->XADC12_THR23_REG_b.XADC12_THR_CONFIG_CH2 = p_ext->p_channel_cfgs[channel]->threshold_mode; + r_adc_w_ldo_enable(ADC_CHANNEL_2); + break; + } + + case ADC_CHANNEL_3: + { + RTC->XADC12_THR23_REG_b.XADC12_THR_LEVEL3_CH3 = ADC_W_12BIT_MASK & + p_ext->p_channel_cfgs[channel]->thd_value; + RTC->XADC12_THR23_REG_b.XADC12_THR_CONFIG_CH3 = p_ext->p_channel_cfgs[channel]->threshold_mode; + r_adc_w_ldo_enable(ADC_CHANNEL_3); + break; + } + + default: + { + break; + } + } + } + } + } + + /* Setting the AD conversion period */ + RTC->XADC12_TIMER_SET_REG_b.X12_CLK_TMR_CNT_SRC = p_ext->timer_count_clock_source; + RTC->XADC12_TIMER_SET_REG_b.AX12B_TIMER_VAL = 0xFU & p_ext->timer_value; + + RTC->XADC12_SP_NUM_REG_b.ADC_SMLP_NUM_AVR = p_ext->sample_average; + + /* Sensor detect activate */ + RTC->XADC12_TIMER_SET_REG_b.SENSOR_DETECT_ACT = 1; + + /* CLOCK enable for adc sensor and pulse cnt functions */ + RTC->ENABLE_CTRL_REG_b.REAL_CNT_LOAD = 1; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads conversion results from FIFO for the given channel. + * When reading multiple data from the FIFO, call this function repeatedly. + * + * @retval FSP_SUCCESS Data read into provided p_data. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_W_FifoRead (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data) +{ +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_W_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + FSP_ERROR_RETURN(((ADC_CHANNEL_0 <= reg_id) && (reg_id <= ADC_CHANNEL_3)), FSP_ERR_ASSERTION); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + switch (reg_id) + { + case ADC_CHANNEL_0: + { + *p_data = AUXADC->FIFO0_DMA_DATA_REG_b.FIFO0_DMA_DATA; + break; + } + + case ADC_CHANNEL_1: + { + *p_data = AUXADC->FIFO1_DMA_DATA_REG_b.FIFO1_DMA_DATA; + break; + } + + case ADC_CHANNEL_2: + { + *p_data = AUXADC->FIFO2_DMA_DATA_REG_b.FIFO2_DMA_DATA; + break; + } + + case ADC_CHANNEL_3: + { + *p_data = AUXADC->FIFO3_DMA_DATA_REG_b.FIFO3_DMA_DATA; + break; + } + + default: + { + break; + } + } + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ADC_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if ADC_W_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validate the configuration when ADC_W channel is configured + * + * @param[in] p_ctrl Pointer to instance control block + * + * @retval FSP_SUCCESS No configuration errors detected. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_w_scan_cfg_check (adc_w_instance_ctrl_t * const p_ctrl) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = p_ctrl; + adc_w_extended_cfg_t * p_extend = (adc_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + #if ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE + FSP_ERROR_RETURN(((0x0U <= p_extend->upper_bound_limit) && (p_extend->upper_bound_limit <= 0xFFFFU)), + FSP_ERR_ASSERTION); + FSP_ERROR_RETURN(((0x0U <= p_extend->lower_bound_limit) && (p_extend->lower_bound_limit <= 0xFFFFU)), + FSP_ERR_ASSERTION); + + /* Currently ADC_W_INTERRUPT_FIFO_FULL is not supported. */ + for (uint8_t channel = ADC_CHANNEL_0; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (NULL != p_extend->p_channel_cfgs[channel]) + { + FSP_ERROR_RETURN(((ADC_W_INTERRUPT_FIFO_NONE == p_extend->p_channel_cfgs[channel]->interrupt_mode_fifo) || + (ADC_W_INTERRUPT_FIFO_HALF == p_extend->p_channel_cfgs[channel]->interrupt_mode_fifo)), + FSP_ERR_ASSERTION); + } + } + #endif + + /* Get the frequency of the clock supplying the ADC */ + uint32_t clock_frequency_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_AUX_ADC); + + if (clock_frequency_hz == 40000000) + { + FSP_ERROR_RETURN(((3 <= p_extend->conversion_clockdiv) && (p_extend->conversion_clockdiv <= 1024)), + FSP_ERR_ASSERTION); + } + else + { + FSP_ERROR_RETURN(((1 <= p_extend->conversion_clockdiv) && (p_extend->conversion_clockdiv <= 1024)), + FSP_ERR_ASSERTION); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validates the configuration arguments for illegal combinations or options. + * + * @param[in] p_cfg Pointer to configuration structure. + * + * @retval FSP_SUCCESS No configuration errors detected. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_w_open_cfg_check (adc_cfg_t const * const p_cfg) +{ + /* Check if p_cfg is NULL. */ + FSP_ASSERT(NULL != p_cfg); + + adc_w_extended_cfg_t const * p_extend = (adc_w_extended_cfg_t const *) p_cfg->p_extend; + + /* Get the frequency of the clock supplying the ADC */ + uint32_t clock_frequency_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_AUX_ADC); + + if (clock_frequency_hz == 40000000) + { + FSP_ERROR_RETURN(((3 <= p_extend->conversion_clockdiv) && (p_extend->conversion_clockdiv <= 1024)), + FSP_ERR_ASSERTION); + } + else + { + FSP_ERROR_RETURN(((1 <= p_extend->conversion_clockdiv) && (p_extend->conversion_clockdiv <= 1024)), + FSP_ERR_ASSERTION); + } + + FSP_ERROR_RETURN(((ADC_RESOLUTION_12_BIT <= p_cfg->resolution) && (p_cfg->resolution <= ADC_RESOLUTION_4_BIT)), + FSP_ERR_ASSERTION); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validates the configuration arguments for illegal combinations or options. + * + * @param[in] p_ctrl Pointer to instance control block + * + * @retval FSP_SUCCESS No configuration errors detected. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_w_SensorWakeup_cfg_check (adc_w_instance_ctrl_t * const p_ctrl) +{ + adc_w_instance_ctrl_t * p_instance_ctrl = p_ctrl; + adc_w_extended_cfg_t * p_ext = (adc_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + for (uint32_t channel = 0U; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (NULL != p_ext->p_channel_cfgs[channel]) + { + if (ADC_W_SENSOR_WAKEUP_ENABLED == p_ext->p_channel_cfgs[channel]->sensorwakeup_en) + { + FSP_ERROR_RETURN((p_ext->p_channel_cfgs[channel]->thd_value <= 0xFFFU), FSP_ERR_ASSERTION); + } + } + } + + FSP_ERROR_RETURN(((1 <= p_ext->timer_value) && (p_ext->timer_value <= 0xF)), FSP_ERR_ASSERTION); + + return FSP_SUCCESS; +} + +#endif + +#if ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * This function implements the interrupt handler for trigger scan complete. + **********************************************************************************************************************/ +void adc_w_scan_end_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + adc_w_instance_ctrl_t * p_instance_ctrl = (adc_w_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); + + uint32_t interrupt_flag = AUXADC->XADC12B_INTR_STATUS_REG; + + /* Clear the interrupt status */ + AUXADC->XADC12B_THR_INTR_CLR_REG = (interrupt_flag >> 8); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { + adc_callback_args_t args; + uint32_t interrupt_ch_flag = + ((ADC_W_INTERRUPT_THD_OVER | ADC_W_INTERRUPT_THD_UNDER | ADC_W_INTERRUPT_THD_DIFF) << 8) | + ADC_W_INTERRUPT_FIFO_HALF | ADC_W_INTERRUPT_FIFO_FULL; + + /* Store the unit number into the callback argument */ + args.unit = p_instance_ctrl->p_cfg->unit; + + /* Populate the context field. */ + args.p_context = p_instance_ctrl->p_context; + + /* Not used */ + args.channel_mask = 0; + args.group_mask = 0; + + for (uint8_t channel = ADC_CHANNEL_0; channel < BSP_FEATURE_ADC_W_MAX_NUM_CHANNELS; channel++) + { + if (interrupt_flag & (interrupt_ch_flag << channel)) + { + /* Return the channel */ + args.channel = channel; + + /* fifo_half and thd_over/under interrupts can occur simultaneously */ + if (interrupt_flag & (ADC_W_INTERRUPT_FIFO_HALF << channel)) + { + args.event = ADC_EVENT_FIFO_READ_REQUEST; + + /* Call the callback. */ + p_instance_ctrl->p_callback(&args); + } + + if (interrupt_flag & ((ADC_W_INTERRUPT_THD_OVER << 8) << channel)) + { + args.event = ADC_EVENT_THD_OVER; + + /* Call the callback. */ + p_instance_ctrl->p_callback(&args); + } + else if (interrupt_flag & ((ADC_W_INTERRUPT_THD_UNDER << 8) << channel)) + { + args.event = ADC_EVENT_THD_UNDER; + + /* Call the callback. */ + p_instance_ctrl->p_callback(&args); + } + else + { + ; + } + } + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +static void r_adc_w_ldo_enable (adc_channel_t channel) +{ + FSP_CRITICAL_SECTION_DEFINE; + + if (bsp_is_chip_revision_a()) + { + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case ADC_CHANNEL_0: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO3 = 1; + break; + } + + case ADC_CHANNEL_1: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO0 = 1; + break; + } + + case ADC_CHANNEL_2: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO1 = 1; + break; + } + + case ADC_CHANNEL_3: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO2 = 1; + break; + } + + default: + { + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; + } + else /* revision B or later */ + { + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case ADC_CHANNEL_0: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO0 = 1; + break; + } + + case ADC_CHANNEL_1: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO1 = 1; + break; + } + + case ADC_CHANNEL_2: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO2 = 1; + break; + } + + case ADC_CHANNEL_3: + { + RTC->LDO_ENABLE2_REG_b.EN_TST_GPIO3 = 1; + break; + } + + default: + { + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; + } +} + +/* End of file R_ADC_W. */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ext_irq_w/r_ext_irq_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ext_irq_w/r_ext_irq_w.c new file mode 100644 index 000000000000..aea9de4a0541 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ext_irq_w/r_ext_irq_w.c @@ -0,0 +1,430 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ext_irq_w.h" +#include "r_ext_irq_w_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "EXT_IRQ" in ASCII, used to determine if channel is open. */ +#define EXT_IRQ_W_OPEN (0x00494355U) + +#define EXT_IRQ_W_IRQMD_OFFSET (0) + +#define EXT_IRQ_W_PORT0_PINBIT_MASK (0x3FFF) +#define EXT_IRQ_W_PORT1_PINBIT_MASK (0xFFFF) + +#define EXT_IRQ_W_WKUP_PINBIT_MASK (0x7FF) + +#define EXT_IRQ_W_MAX_CHANNEL (30) +#define EXT_IRQ_W_MAX_IO_PORT (BSP_IO_PORT_MAX - 1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ext_irq_w_prv_ns_callback)(external_irq_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ext_irq_w_prv_ns_callback)(external_irq_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void r_ext_irq_w_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +static uint32_t gs_enabled_pin_bit[EXT_IRQ_W_MAX_IO_PORT] = {0, 0, }; + +static ext_irq_w_instance_ctrl_t * volatile gp_ext_irq_w_ctrls[EXT_IRQ_W_MAX_CHANNEL]; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* EXT_IRQ implementation of External IRQ API. */ +const external_irq_api_t g_external_irq_on_ext_irq_w = +{ + .open = R_EXT_IRQ_W_ExternalIrqOpen, + .enable = R_EXT_IRQ_W_ExternalIrqEnable, + .disable = R_EXT_IRQ_W_ExternalIrqDisable, + .callbackSet = R_EXT_IRQ_W_ExternalIrqCallbackSet, + .close = R_EXT_IRQ_W_ExternalIrqClose, +}; + +/*******************************************************************************************************************//** + * @addtogroup EXT_IRQ_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure an IRQ input pin for use with the external interrupt interface. Implements @ref external_irq_api_t::open. + * + * The Open function is responsible for preparing an external IRQ pin for operation. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION One of the following is invalid: + * - p_ctrl or p_cfg is NULL + * @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. No configurations were changed. + * Call the associated Close function to reconfigure the channel. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in + * r_bsp_cfg.h. + * @retval FSP_ERR_INVALID_ARGUMENT p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to + * use callback function. + * @retval FSP_ERR_UNSUPPORTED An input argument is not supported by selected mode. + * + * @note This function is reentrant for different channels. It is not reentrant for the same channel. + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg) +{ + ext_irq_w_instance_ctrl_t * p_ctrl = (ext_irq_w_instance_ctrl_t *) p_api_ctrl; + +#if EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); +#endif + + FSP_ERROR_RETURN(EXT_IRQ_W_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Verify the configuration trigger source is correct */ + FSP_ERROR_RETURN((EXTERNAL_IRQ_TRIG_FALLING == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_RISING == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_LEVEL_LOW == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_LEVEL_HIGH == p_cfg->trigger), + FSP_ERR_UNSUPPORTED); + + FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Callback must be used with a valid interrupt priority otherwise it will never be called. */ + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + } + + /* Channel must be free */ + FSP_ERROR_RETURN(gp_ext_irq_w_ctrls[p_cfg->channel] == NULL, FSP_ERR_INVALID_CHANNEL); + + p_ctrl->irq_pin = ((ext_irq_w_extended_cfg_t *) p_cfg->p_extend)->irq_pin; + + uint8_t port = (uint8_t) ((p_ctrl->irq_pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET); + uint8_t pin = (uint8_t) (p_ctrl->irq_pin & BSP_IO_PIN_BITS); + uint32_t pin_bit = 0; + + pin_bit = 1 << pin; + + if ((BSP_IO_PORT_00 == port) && (0 != (EXT_IRQ_W_PORT0_PINBIT_MASK & pin_bit))) + { + p_ctrl->irq = GPIO_P0_IRQn; + } + else if ((BSP_IO_PORT_01 == port) && (0 != (EXT_IRQ_W_PORT1_PINBIT_MASK & pin_bit))) + { + p_ctrl->irq = GPIO_P1_IRQn; + } + else + { + FSP_RETURN(FSP_ERR_UNSUPPORTED); + } + + /* Initialize control block. */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->channel = p_cfg->channel; + + switch (p_cfg->trigger) + { + case EXTERNAL_IRQ_TRIG_FALLING: + { + BSP_IO_PXX_POL_REG(port) = BSP_IO_PXX_POL_REG(port) | pin_bit; /* give an event if that input goes low */ + BSP_IO_PXX_SEL1_REG(port) = BSP_IO_PXX_SEL1_REG(port) | pin_bit; /* Edge sensitive */ + break; + } + + case EXTERNAL_IRQ_TRIG_RISING: + { + BSP_IO_PXX_POL_REG(port) = BSP_IO_PXX_POL_REG(port) & ~pin_bit; /* give an event if that input goes high */ + BSP_IO_PXX_SEL1_REG(port) = BSP_IO_PXX_SEL1_REG(port) | pin_bit; /* Edge sensitive */ + break; + } + + case EXTERNAL_IRQ_TRIG_LEVEL_LOW: + { + BSP_IO_PXX_POL_REG(port) = BSP_IO_PXX_POL_REG(port) | pin_bit; /* give an event if that input goes low */ + BSP_IO_PXX_SEL1_REG(port) = BSP_IO_PXX_SEL1_REG(port) & ~pin_bit; /* Level sensitive */ + break; + } + + case EXTERNAL_IRQ_TRIG_LEVEL_HIGH: + { + BSP_IO_PXX_POL_REG(port) = BSP_IO_PXX_POL_REG(port) & ~pin_bit; /* give an event if that input goes high */ + BSP_IO_PXX_SEL1_REG(port) = BSP_IO_PXX_SEL1_REG(port) & ~pin_bit; /* Level sensitive */ + break; + } + + default: + { + ; /* do nothing */ + } + } + + R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl); + + gp_ext_irq_w_ctrls[p_ctrl->channel] = p_ctrl; + + /* Mark the control block as open */ + p_ctrl->open = EXT_IRQ_W_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable. + * + * @retval FSP_SUCCESS Interrupt Enabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl) +{ + ext_irq_w_instance_ctrl_t * p_ctrl = (ext_irq_w_instance_ctrl_t *) p_api_ctrl; + +#if EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); +#endif + + FSP_ERROR_RETURN(EXT_IRQ_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + uint8_t port = (uint8_t) ((p_ctrl->irq_pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET); + uint8_t pin = (uint8_t) (p_ctrl->irq_pin & BSP_IO_PIN_BITS); + uint32_t pin_bit = 0; + + pin_bit = 1 << pin; + + if (pin_bit == (BSP_IO_PXX_INT_STS_REG(port) & pin_bit)) + { + BSP_IO_PXX_INT_CLR_REG(port) = pin_bit; + } + + BSP_IO_PXX_SEL_REG(port) = BSP_IO_PXX_SEL_REG(port) | pin_bit; + + /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */ + if (0 == gs_enabled_pin_bit[port]) + { + R_BSP_IrqEnable(p_ctrl->irq); + } + + gs_enabled_pin_bit[port] = gs_enabled_pin_bit[port] | pin_bit; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable. + * + * @retval FSP_SUCCESS Interrupt disabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) +{ + ext_irq_w_instance_ctrl_t * p_ctrl = (ext_irq_w_instance_ctrl_t *) p_api_ctrl; + +#if EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); +#endif + + FSP_ERROR_RETURN(EXT_IRQ_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + uint8_t port = (uint8_t) ((p_ctrl->irq_pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET); + uint8_t pin = (uint8_t) (p_ctrl->irq_pin & BSP_IO_PIN_BITS); + uint32_t pin_bit = 0; + + pin_bit = 1 << pin; + + BSP_IO_PXX_SEL_REG(port) = BSP_IO_PXX_SEL_REG(port) & ~pin_bit; + + if (pin_bit == (BSP_IO_PXX_INT_STS_REG(port) & pin_bit)) + { + BSP_IO_PXX_INT_CLR_REG(port) = pin_bit; + } + + gs_enabled_pin_bit[port] = gs_enabled_pin_bit[port] & ~pin_bit; + + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + if (0 == gs_enabled_pin_bit[port]) + { + R_BSP_IrqDisable(p_ctrl->irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements external_irq_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)( + external_irq_callback_args_t *), + void * const p_context, + external_irq_callback_args_t * const p_callback_memory) +{ + ext_irq_w_instance_ctrl_t * p_ctrl = p_api_ctrl; + + FSP_PARAMETER_NOT_USED(p_callback_memory); + +#if EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_callback); +#endif + + FSP_ERROR_RETURN(EXT_IRQ_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close the external interrupt channel. Implements @ref external_irq_api_t::close. + * + * @retval FSP_SUCCESS Successfully closed. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_EXT_IRQ_W_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl) +{ + ext_irq_w_instance_ctrl_t * p_ctrl = (ext_irq_w_instance_ctrl_t *) p_api_ctrl; + +#if EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); +#endif + + FSP_ERROR_RETURN(EXT_IRQ_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + uint8_t port = (uint8_t) ((p_ctrl->irq_pin & BSP_IO_PORT_BITS) >> BSP_IO_PORT_OFFSET); + uint8_t pin = (uint8_t) (p_ctrl->irq_pin & BSP_IO_PIN_BITS); + uint32_t pin_bit = 0; + + pin_bit = 1 << pin; + + gs_enabled_pin_bit[port] = gs_enabled_pin_bit[port] & ~pin_bit; + BSP_IO_PXX_SEL_REG(port) = BSP_IO_PXX_SEL_REG(port) & ~pin_bit; + + /* Cleanup. Disable interrupt */ + if (0 == gs_enabled_pin_bit[port]) + { + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + R_BSP_IrqDisable(p_ctrl->irq); + R_FSP_IsrContextSet(p_ctrl->irq, NULL); + } + + p_ctrl->open = 0U; + + gp_ext_irq_w_ctrls[p_ctrl->channel] = NULL; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup EXT_IRQ_W) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * EXT_IRQ External Interrupt ISR. + **********************************************************************************************************************/ +void r_ext_irq_w_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint8_t port = 0; + uint32_t status_reg = 0; + uint8_t pin = 0; + uint32_t pin_bit = 0; + + if (GPIO_P0_IRQn == irq) + { + port = BSP_IO_PORT_00; + } + else if (GPIO_P1_IRQn == irq) + { + port = BSP_IO_PORT_01; + } + else + { + return; + } + + status_reg = BSP_IO_PXX_INT_STS_REG(port); + + if (0 == status_reg) + { + /* Status is empty, but maybe this is wakeup from GPIO context */ + bsp_io_wakeup_pin_t wakeup_pin = R_BSP_WakeupSourcePinGet(); + + if (wakeup_pin != 0) + { + /* Fake status based on the wakeup GPIO */ + status_reg = (1 << (bsp_prv_wakeup_pin_to_port_pin(wakeup_pin) & BSP_IO_PIN_BITS)); + } + else + { + return; + } + } + + for (pin = 0; 0 != status_reg; pin++) + { + status_reg >>= 1; + } + + pin_bit = (uint32_t) (1 << (pin - 1)); + + BSP_IO_PXX_INT_CLR_REG(port) = pin_bit; + + uint32_t irq_pin = (uint32_t) (port << BSP_IO_PORT_OFFSET) | (uint32_t) (pin - 1); + + if (pin_bit == (gs_enabled_pin_bit[port] & pin_bit)) + { + for (uint8_t channel = 0; channel < EXT_IRQ_W_MAX_CHANNEL; channel++) + { + if ((NULL != gp_ext_irq_w_ctrls[channel]) && (irq_pin == gp_ext_irq_w_ctrls[channel]->irq_pin) && + (NULL != gp_ext_irq_w_ctrls[channel]->p_callback)) + { + /* Set data to identify callback to user, then call user callback. */ + external_irq_callback_args_t args; + + args.channel = gp_ext_irq_w_ctrls[channel]->channel; + args.p_context = gp_ext_irq_w_ctrls[channel]->p_context; + gp_ext_irq_w_ctrls[channel]->p_callback(&args); + + break; + } + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_gpio_w/r_gpio_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_gpio_w/r_gpio_w.c new file mode 100644 index 000000000000..47bb0e538a53 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_gpio_w/r_gpio_w.c @@ -0,0 +1,812 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_gpio_w.h" +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + #include "rm_pmgr_w_instance.h" + #endif +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + #define GPIO_PD BSP_PD_COM +#elif BSP_MCU_GROUP_RA6W3 + #define GPIO_PD BSP_PD_SYS +#endif + +/* "PORT" in ASCII, used to determine if the module is open */ +#define GPIO_W_OPEN (0x504F5254U) +#define GPIO_W_CLOSED (0x00000000U) +#if !defined(BSP_MCU_GROUP_RA6W1) + #define GPIO_W_CLK_SEL_REG_FUNC_MASK (0xF) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_gpio_w_pins_config(gpio_w_instance_ctrl_t * p_ctrl, const ioport_cfg_t * p_cfg); +static void r_gpio_w_pin_config(gpio_w_instance_ctrl_t * p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + +#if defined(BSP_MCU_GROUP_RA6W1) +bool r_gpio_w_retained_io_set(bsp_io_port_pin_t pin); + + #if CFG_PMGR +static fsp_err_t r_gpio_w_enter_sleep(ioport_ctrl_t * p_ctrl); +static fsp_err_t r_gpio_w_wakeup(ioport_ctrl_t * p_ctrl); +static void r_gpio_w_pmgr_callback(pmgr_callback_args_t * p_args); +static fsp_err_t r_gpio_w_subscribe_for_pmgr_notifications(ioport_ctrl_t * const p_ctrl); +static fsp_err_t r_gpio_w_unsubscribe_from_pmgr_notifications(void); + + #endif +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* GPIO_W Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_gpio_w = +{ + .open = R_GPIO_W_Open, + .close = R_GPIO_W_Close, + .pinsCfg = R_GPIO_W_PinsCfg, + .pinCfg = R_GPIO_W_PinCfg, + .pinEventInputRead = R_GPIO_W_PinEventInputRead, + .pinEventOutputWrite = R_GPIO_W_PinEventOutputWrite, + .pinRead = R_GPIO_W_PinRead, + .pinWrite = R_GPIO_W_PinWrite, + .portDirectionSet = R_GPIO_W_PortDirectionSet, + .portEventInputRead = R_GPIO_W_PortEventInputRead, + .portEventOutputWrite = R_GPIO_W_PortEventOutputWrite, + .portRead = R_GPIO_W_PortRead, + .portWrite = R_GPIO_W_PortWrite, +}; + +#if CFG_PMGR +static pmgr_instance_info_t g_r_gpio_w_pmgr_info = +{ + .power_mode = PMGR_LLD_POWER_MODE_SLEEP4, + .wake_source = PMGR_WAKE_SOURCE_NONE, +}; + +static pmgr_callback_args_t g_r_gpio_w_pmgr_args = +{ + .constraints = PMGR_CONSTRAINT_NONE, + .event = PMGR_EVENT_NOT_SET, + .p_context = NULL, + .p_instance_info = &g_r_gpio_w_pmgr_info, +}; + +static pmgr_w_notifier_extend_t g_r_gpio_w_pmgr_notifier_extend = +{ + .order = PMGR_W_NOTIFIER_ORDER_HIGHEST, +}; + +static uint32_t gpio_w_sel[BSP_FEATURE_IO_PORT_COUNT]; +static uint32_t gpio_w_sel1[BSP_FEATURE_IO_PORT_COUNT]; +static uint32_t gpio_w_pol[BSP_FEATURE_IO_PORT_COUNT]; +#endif // #if CFG_PMGR + +/*******************************************************************************************************************//** + * @addtogroup GPIO_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to MODE, Set port pins and Reset port pins register(s) + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; +#if defined(BSP_MCU_GROUP_RA6W1) + #if CFG_PMGR + bool is_sleep3_wakeup; + #endif +#endif + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data || 0 == p_cfg->number_of_pins); + FSP_ERROR_RETURN(GPIO_W_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + #if !BSP_MCU_GROUP_RA6W1 && !BSP_MCU_GROUP_RA6B2 // TIN-TODO + FSP_ERROR_RETURN(bsp_pd_is_up_check(GPIO_PD), FSP_ERR_INVALID_HW_CONDITION); + #endif +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = GPIO_W_OPEN; + + /* Init P0 reg addresses. The regs for other ports are right after P0's regs. */ + p_instance_ctrl->p_reg_p0_data = &GPIO->P0_DATA_REG; + p_instance_ctrl->p_reg_p0_set_data = &GPIO->P0_SET_DATA_REG; + p_instance_ctrl->p_reg_p0_reset_data = &GPIO->P0_RESET_DATA_REG; + p_instance_ctrl->p_reg_p0_00_mode = &GPIO->P0_00_MODE_REG; + +#if defined(BSP_MCU_GROUP_RA6W1) + #if CFG_PMGR + r_gpio_w_subscribe_for_pmgr_notifications(p_ctrl); + is_sleep3_wakeup = RM_PMGR_W_IsSleep3Wakeup(); + + if (is_sleep3_wakeup) + { + R_BSP_RetainedIoRecovery(false); + } + else + #endif + + { + R_BSP_RetainedIoClear(); + r_gpio_w_pins_config(p_instance_ctrl, p_cfg); + } + +#else + r_gpio_w_pins_config(p_instance_ctrl, p_cfg); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets GPIO_W registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The GPIO_W was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_Close (ioport_ctrl_t * const p_ctrl) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; +#if defined(BSP_MCU_GROUP_RA6W1) + #if CFG_PMGR + r_gpio_w_unsubscribe_from_pmgr_notifications(); + #endif +#endif +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = GPIO_W_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into pin MODE,Set port pins and Reset port pins registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of MODE, Set port pins and Reset port pins registers with the supplied values. This data can be generated + * by the Pins tab of the RAFW Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to MODE,Set port pins and Reset port pins register(s) + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#endif + + r_gpio_w_pins_config(p_instance_ctrl, p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + R_BSP_PinAccessEnable(); + + r_gpio_w_pin_config(p_instance_ctrl, pin, cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_port_value = (ioport_size_t) *(p_instance_ctrl->p_reg_p0_data + port); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different ports. This function makes use of the Set port pins and Reset port pins registers to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#endif + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + *(p_instance_ctrl->p_reg_p0_set_data + port) = value & mask; + *(p_instance_ctrl->p_reg_p0_reset_data + port) = (ioport_size_t) (~value) & mask; + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opene + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different pins. This function makes use of the Set port pins and Reset port pins registers to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#elif defined(BSP_MCU_GROUP_RA6W1) + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + +#if !defined(BSP_MCU_GROUP_RA6W1) + bsp_io_port_t port = (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) pin) >> BSP_IO_PORT_OFFSET); + + uint32_t gpio_id = BSP_IO_PIN_BITS & (uint16_t) pin; + + if (BSP_IO_LEVEL_HIGH == level) + { + *(p_instance_ctrl->p_reg_p0_set_data + port) = 1 << gpio_id; + } + else + { + *(p_instance_ctrl->p_reg_p0_reset_data + port) = 1 << gpio_id; + } + +#else + R_BSP_PinWrite(pin, level); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + gpio_w_instance_ctrl_t * p_instance_ctrl = (gpio_w_instance_ctrl_t *) p_ctrl; + +#if (1 == GPIO_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPIO_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#endif + + volatile uint32_t * mode_reg; + uint16_t port_gpio_count; + + if (BSP_IO_PORT_00 == port) + { + port_gpio_count = BSP_FEATURE_IO_PORT0_GPIO_COUNT; + mode_reg = p_instance_ctrl->p_reg_p0_00_mode; + } + else if (BSP_IO_PORT_01 == port) + { + port_gpio_count = BSP_FEATURE_IO_PORT1_GPIO_COUNT; + mode_reg = p_instance_ctrl->p_reg_p0_00_mode + BSP_FEATURE_IO_PORT0_GPIO_COUNT; + } + else /* Port 2 */ + { + port_gpio_count = BSP_FEATURE_IO_PORT2_GPIO_COUNT; + mode_reg = p_instance_ctrl->p_reg_p0_00_mode + BSP_FEATURE_IO_PORT0_GPIO_COUNT + + BSP_FEATURE_IO_PORT1_GPIO_COUNT; + } + + for (uint16_t gpio = 0U; gpio < port_gpio_count; gpio++, mode_reg++) + { + if (mask & (1U << gpio)) + { + if (0 != ((direction_values >> gpio) & 1)) + { + *mode_reg = ((*mode_reg) & ~GPIO_P0_00_MODE_REG_PUPD_Msk) | GPIO_W_CFG_PORT_DIRECTION_OUTPUT; + } + else + { + *mode_reg = ((*mode_reg) & ~GPIO_P0_00_MODE_REG_PUPD_Msk) | GPIO_W_CFG_PORT_DIRECTION_INPUT; + } + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(p_event_data); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant. + * + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(p_pin_event); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(event_data); + FSP_PARAMETER_NOT_USED(mask_value); + + return FSP_ERR_UNSUPPORTED; +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_GPIO_W_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(pin_value); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup GPIO_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures gpios with cfg setting. It calls r_gpio_w_pin_config internally repeatedly + * to have required gpios configured one by one + * + * @param[in] p_ctrl Instance ctrl + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +static void r_gpio_w_pins_config (gpio_w_instance_ctrl_t * p_ctrl, const ioport_cfg_t * p_cfg) +{ + uint16_t pin_count; +#if !defined(BSP_MCU_GROUP_RA6W1) + const gpio_w_extended_cfg_t * gpio_w_extend_struct = p_cfg->p_extend; + + if (NULL != gpio_w_extend_struct) + { + #if defined GPIO_P2_1P8_MODE_REG_P2_00_1P8_MODE_Msk + GPIO->P2_1P8_MODE_REG = gpio_w_extend_struct->power.p2_pwr; + #elif !BSP_MCU_GROUP_RA6W1 // TIN-TODO + GPIO->P1_PADPWR_CTRL_REG = gpio_w_extend_struct->power.p1_pwr; + #endif + + #if BSP_FEATURE_IO_HAS_WEAK_CONFIG_PER_PORT + GPIO->P0_WEAK_CTRL_REG = gpio_w_extend_struct->weak_pad_power.p0_pwr; + GPIO->P1_WEAK_CTRL_REG = gpio_w_extend_struct->weak_pad_power.p1_pwr; + #if (0 != BSP_FEATURE_IO_PORT2_GPIO_COUNT) + GPIO->P2_WEAK_CTRL_REG = gpio_w_extend_struct->weak_pad_power.p2_pwr; + #endif + #elif !BSP_MCU_GROUP_RA6W1 // TIN-TODO + GPIO->PAD_WEAK_CTRL_REG = gpio_w_extend_struct->weak_pad_power.aggregate; + #endif + + uint32_t temp = GPIO->GPIO_CLK_SEL_REG & GPIO_W_CLK_SEL_REG_FUNC_MASK; + GPIO->GPIO_CLK_SEL_REG = gpio_w_extend_struct->fixed_pin_clk_out | temp; + + GPIO->GPIO_CLK_SEL_REG_b.FUNC_CLOCK_SEL = gpio_w_extend_struct->sel_pin_clk_out.clk_sel; + GPIO->GPIO_CLK_SEL_REG_b.FUNC_CLOCK_EN = gpio_w_extend_struct->sel_pin_clk_out.clk_en; + } +#endif + + for (pin_count = 0U; pin_count < p_cfg->number_of_pins; pin_count++) + { + r_gpio_w_pin_config(p_ctrl, p_cfg->p_pin_cfg_data[pin_count].pin, p_cfg->p_pin_cfg_data[pin_count].pin_cfg); + } +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's register + * + * @param[in] p_ctrl Instance ctrl + * @param[in] pin Pin to write Mux data for + * @param[in] cfg Value to be written + * + **********************************************************************************************************************/ +static void r_gpio_w_pin_config (gpio_w_instance_ctrl_t * p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if BSP_MCU_GROUP_RA6W1 + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + bsp_io_port_pin_t pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) pin); + bsp_io_port_t port_id = + (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) pin) >> BSP_IO_PORT_OFFSET); + bsp_io_level_t level = (bsp_io_level_t) ((cfg & GPIO_W_PRV_LEVEL_BITS) >> GPIO_W_PRV_LEVEL_OFFSET); +#if !defined(BSP_MCU_GROUP_RA6W1) + uint32_t mode = cfg & GPIO_W_MODE_REG_VALID_BITS_MSK; +#else + uint16_t mode = cfg & GPIO_W_PRV_MODE_BITS; +#endif +#if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + if (BSP_IO_PORT_01 == port_id) + { + PMU_ANA->POWER_CTRL_REG_b.EN_HSGND = 1; + FSP_HARDWARE_REGISTER_WAIT(PMU_ANA->ANA_STATUS_REG_b.HSGND_OK, 1U); + } +#endif +#if !defined(BSP_MCU_GROUP_RA6W1) + if (GPIO_W_PERIPHERAL_GPIO == (mode & GPIO_W_PRV_FUNC_BITS)) + { + if (BSP_IO_LEVEL_HIGH == level) + { + *(p_ctrl->p_reg_p0_set_data + port_id) = 1 << pin_id; + } + else + { + *(p_ctrl->p_reg_p0_reset_data + port_id) = 1 << pin_id; + } + } + + GPIO_W_PXX_MODE_REG(port_id, pin_id) = mode; +#else + if (GPIO_W_PERIPHERAL_GPIO == (mode & GPIO_W_PRV_FUNC_BITS)) + { + R_BSP_PinWrite(pin, level); + } + + if (GPIO_W_CFG_RETENTION == (cfg & GPIO_W_CFG_RETENTION)) + { + R_BSP_PinCfg(pin, mode); + R_BSP_RetainedIoSet(pin); + } + else + { + R_BSP_PinCfg(pin, mode); + } + + if (GPIO_W_CFG_IRQ_ENABLE == (cfg & GPIO_W_CFG_IRQ_ENABLE)) + { + BSP_IO_PXX_SEL_REG(port_id) |= (uint32_t) (0x01 << pin_id); + } + else + { + BSP_IO_PXX_SEL_REG(port_id) &= ~((uint32_t) (0x01 << pin_id)); + } +#endif +} + +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR +static fsp_err_t r_gpio_w_enter_sleep (ioport_ctrl_t * p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + fsp_err_t err = FSP_SUCCESS; + + for (uint8_t port = 0; port < BSP_FEATURE_IO_PORT_COUNT; port++) + { + /* Store GPIO IRQ settings */ + gpio_w_pol[port] = BSP_IO_PXX_POL_REG(port); + gpio_w_sel1[port] = BSP_IO_PXX_SEL1_REG(port); + gpio_w_sel[port] = BSP_IO_PXX_SEL_REG(port); + } + + R_BSP_RetainedIoExecute(); + + return err; +} + +static fsp_err_t r_gpio_w_wakeup (ioport_ctrl_t * p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + fsp_err_t err = FSP_SUCCESS; + bsp_io_wakeup_pin_t wakeup_pin; + + wakeup_pin = R_BSP_WakeupSourcePinGet(); + R_BSP_RetainedIoRecovery(false); + + for (uint8_t port = 0; port < BSP_FEATURE_IO_PORT_COUNT; port++) + { + /* Restore GPIO IRQ settings */ + BSP_IO_PXX_POL_REG(port) = gpio_w_pol[port]; // Restore polarity (High/Low) + BSP_IO_PXX_SEL1_REG(port) = gpio_w_sel1[port]; // Restore sensitivity (Level/Edge) + BSP_IO_PXX_SEL_REG(port) = gpio_w_sel[port]; // Restore mode (Enable/Disable) + } + + if (wakeup_pin != 0) + { + bsp_io_port_pin_t port_pin = bsp_prv_wakeup_pin_to_port_pin(wakeup_pin); + + if (port_pin != BSP_IO_PORT_FF_PIN_FF) + { + uint8_t port = (uint8_t) ((port_pin >> BSP_IO_PORT_OFFSET) & BSP_IO_PORT_BITS); + uint8_t pin = (uint8_t) (port_pin & BSP_IO_PIN_BITS); + + bool irq_enabled = !!(gpio_w_sel[port] & (1 << pin)); + bool edge_sensitive = !!(gpio_w_sel1[port] & (1 << pin)); + + if (irq_enabled && edge_sensitive) + { + bool irq_edge = !!(gpio_w_pol[port] & (1 << pin)); + bool wakeup_edge = !!(RTC->GPIO_WAKEUP0_REG_b.GPIO_WAKEUP_EDGE_INVERSION_SEL & wakeup_pin); + + if (irq_edge == wakeup_edge) + { + R_BSP_IrqSetPending(GPIO_P0_IRQn + port); + } + } + } + } + + return err; +} + +static void r_gpio_w_pmgr_callback (pmgr_callback_args_t * p_args) +{ + pmgr_instance_info_t * p_pmgr_info = (pmgr_instance_info_t *) p_args->p_instance_info; + + if (p_pmgr_info->power_mode == PMGR_LLD_POWER_MODE_SLEEP4) + { + if (p_args->event == PMGR_EVENT_ENTERING_SLEEP) + { + r_gpio_w_enter_sleep((ioport_ctrl_t *) p_args->p_context); + } + else if (p_args->event == PMGR_EVENT_EXITING_SLEEP) + { + r_gpio_w_wakeup((ioport_ctrl_t *) p_args->p_context); + } + } +} + +static fsp_err_t r_gpio_w_subscribe_for_pmgr_notifications (ioport_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + + g_r_gpio_w_pmgr_args.p_context = (void *) p_ctrl; + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(pmgr_ctrl != NULL); + + err = RM_PMGR_W_notifier_register(pmgr_ctrl, + r_gpio_w_pmgr_callback, + &g_r_gpio_w_pmgr_args, + &g_r_gpio_w_pmgr_notifier_extend); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + +static fsp_err_t r_gpio_w_unsubscribe_from_pmgr_notifications (void) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + FSP_ASSERT(pmgr_ctrl != NULL); + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(pmgr_ctrl != NULL); + + err = RM_PMGR_W_notifier_unregister(pmgr_ctrl, g_r_gpio_w_pmgr_notifier_extend.notifier_id); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + + #endif // #if CFG_PMGR +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_i2c_master_w/r_i2c_master_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_i2c_master_w/r_i2c_master_w.c new file mode 100644 index 000000000000..9c136b60c91a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_i2c_master_w/r_i2c_master_w.c @@ -0,0 +1,1876 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i2c_master_w.h" +#if I2C_MASTER_W_CFG_DTC_ENABLE + #include "r_dtc_w.h" +#elif I2C_MASTER_W_CFG_DMA_ENABLE + #if BSP_FEATURE_DMAC_W_B + #include "r_dmac_w_b.h" + #elif BSP_FEATURE_DMAC_W + #include "r_dmac_w.h" + #endif +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "I2CW" in ASCII, used to determine if channel is open. */ +#define I2C_MASTER_W_OPEN (0x49324357U) + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + #define I2C_MASTER_W_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + #define I2C_MASTER_W_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_2_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#endif + +#define I2C_ENABLE_LOOP_LIMIT (0x10) +#define I2C_ENABLE_STATUS_INTERVAL (0x200) + +#if defined(CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk) + #define RESET_CLK_COM_REG CRG_COM->RESET_CLK_COM_REG + #define SET_CLK_COM_REG CRG_COM->SET_CLK_COM_REG + #define RESET_CLK_COM_I2C_CLK_SEL CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk + #define SET_CLK_COM_I2C_CLK_SEL CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk + #define RESET_CLK_COM_I2C_ENABLE CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk + #define SET_CLK_COM_I2C_ENABLE CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk +#elif defined(CRG_PER_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk) + #define RESET_CLK_COM_REG CRG_PER->RESET_CLK_COM_REG + #define SET_CLK_COM_REG CRG_PER->SET_CLK_COM_REG + #define RESET_CLK_COM_I2C_CLK_SEL CRG_PER_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk + #define SET_CLK_COM_I2C_CLK_SEL CRG_PER_SET_CLK_COM_REG_I2C_CLK_SEL_Msk + #define RESET_CLK_COM_I2C_ENABLE CRG_PER_RESET_CLK_COM_REG_I2C_ENABLE_Msk + #define SET_CLK_COM_I2C_ENABLE CRG_PER_SET_CLK_COM_REG_I2C_ENABLE_Msk +#endif + +#if I2C_MASTER_W_CFG_DMA_ENABLE + #if BSP_FEATURE_DMAC_W_B + #define DMAC_EXTENDED_CONFIG dmac_w_b_extended_cfg_t + #define DMAC_BURST_MODE_NONE DMAC_W_B_BURST_MODE_DISABLED + #define DMAC_BURST_MODE_8X DMAC_W_B_BURST_MODE_8x + #define DMAC_BURST_MODE_4X DMAC_W_B_BURST_MODE_4x + #elif BSP_FEATURE_DMAC_W + #define DMAC_EXTENDED_CONFIG dmac_extended_cfg_t + #define DMAC_BURST_MODE_NONE DMAC_BURST_MODE_DISABLED + #define DMAC_BURST_MODE_8X DMAC_BURST_MODE_8x + #define DMAC_BURST_MODE_4X DMAC_BURST_MODE_4x + #endif +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Hardware errors and events that can occur on the I2C */ +typedef enum e_i2c_master_w_err +{ + I2C_MASTER_W_ERR_EVENT_NONE = 0, + I2C_MASTER_W_ERR_EVENT_TIMEOUT = 1, + I2C_MASTER_W_ERR_EVENT_ARBITRATION_LOSS = 2, + I2C_MASTER_W_ERR_EVENT_START = 4, + I2C_MASTER_W_ERR_EVENT_STOP = 8, + I2C_MASTER_W_ERR_EVENT_NACK = 16 +} i2c_master_w_err_t; + +/* I2C read/write enumeration */ +typedef enum e_i2c_master_w_transfer_dir +{ + I2C_MASTER_W_TRANSFER_DIR_WRITE = 0x0, + I2C_MASTER_W_TRANSFER_DIR_READ = 0x1 +} i2c_master_w_transfer_dir_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * i2c_master_w_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile i2c_master_w_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Internal helper functions */ +static fsp_err_t i2c_master_w_read_write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + i2c_master_w_transfer_dir_t direction); +static void i2c_master_w_isr_tx_handler(i2c_master_w_instance_ctrl_t * p_ctrl); +static void i2c_master_w_isr_rx_handler(i2c_master_w_instance_ctrl_t * p_ctrl, uint32_t event); +static void i2c_master_w_notify(i2c_master_w_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event); + +/* Functions that manipulate hardware */ +static fsp_err_t i2c_master_w_open_hw_master(i2c_master_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t i2c_master_w_disable(i2c_master_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t i2c_master_w_mode_address_set(i2c_master_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t i2c_master_w_set_target_address(i2c_master_w_instance_ctrl_t * const p_ctrl); +static void i2c_master_w_enable_clk(uint8_t channel, bool select_divn); +static void i2c_master_w_disable_clk(uint8_t channel); +static void i2c_master_w_abort_transfer(i2c_master_w_instance_ctrl_t * const p_ctrl); +static void i2c_master_w_configure_speed(i2c_master_w_instance_ctrl_t * const p_ctrl); +static void i2c_master_w_read_configure(i2c_master_w_instance_ctrl_t * const p_ctrl); +static void i2c_master_w_write_configure(i2c_master_w_instance_ctrl_t * const p_ctrl); + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) +static fsp_err_t i2c_master_w_transfer_open(i2c_master_cfg_t const * const p_cfg); +static fsp_err_t i2c_master_w_transfer_configure(transfer_instance_t const * p_transfer, + i2c_master_w_transfer_dir_t direction); + +#endif + +/* ISR function prototypes. */ +void i2c_master_w_gen_isr(void); + +#if !I2C_MASTER_W_CFG_GENERIC_ONLY +void i2c_master_w_rxi_isr(void); +void i2c_master_w_txi_isr(void); +void i2c_master_w_tei_isr(void); + +#endif + +#if (I2C_MASTER_W_CFG_DMA_ENABLE) +void i2c_master_w_rx_dmac_callback(i2c_master_w_instance_ctrl_t * const p_ctrl); +void i2c_master_w_tx_dmac_callback(i2c_master_w_instance_ctrl_t * const p_ctrl); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* I2C_W Implementation of I2C device master interface */ +i2c_master_api_t const g_i2c_master_on_i2c_w = +{ + .open = R_I2C_MASTER_W_Open, + .read = R_I2C_MASTER_W_Read, + .write = R_I2C_MASTER_W_Write, + .abort = R_I2C_MASTER_W_Abort, + .slaveAddressSet = R_I2C_MASTER_W_SlaveAddressSet, + .close = R_I2C_MASTER_W_Close, + .statusGet = R_I2C_MASTER_W_StatusGet, + .callbackSet = R_I2C_MASTER_W_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup I2C_MASTER_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the I2C device. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[in] p_cfg Pointer to I2C specific configuration structure. + * + * @retval FSP_SUCCESS I2C slave device opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_INVALID_HW_CONDITION I2C's power domain is not enabled. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. p_extend parameter is NULL. + * 3. Invalid IRQ number assigned. Please refer to the documentation + * of I2C_MASTER_W_CFG_GENERIC_ONLY + * 4. Invalid driver configuration. + * @retval FSP_ERR_TIMEOUT Device is stuck & cannot be disabled. To recover from such an + * issue you can: + * - reset the SCLK & SDA pins, + * - disable PD_COM, + * - perform a HW reset. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(p_extend->gen_irq >= (IRQn_Type) 0); + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + #endif + FSP_ERROR_RETURN(I2C_MASTER_W_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_I2C_VALID_CHANNEL_MASK & (1 << (p_cfg->channel + I2C_MASTER_W_CHANNEL_OFFSET)), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #if BSP_FEATURE_I2C_HAS_SEPARATE_PD + FSP_ERROR_RETURN(bsp_pd_is_up_check(BSP_FEATURE_I2C_HAS_SEPARATE_PD), FSP_ERR_INVALID_HW_CONDITION); + #endif +#endif + +#if I2C_MASTER_W_CFG_GENERIC_ONLY + FSP_ASSERT(I2C_MASTER_W_CFG_DTC_ENABLE == 0); +#endif + + fsp_err_t err = FSP_SUCCESS; + + p_ctrl->p_reg = (I2C_Type *) ((uint32_t) I2C + (p_cfg->channel * ((uint32_t) I2C2 - (uint32_t) I2C))); + + /* Record the pointer to the configuration structure for later use */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Open the hardware in master mode. Performs I2C initialization. */ + err = i2c_master_w_open_hw_master(p_ctrl); + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + + /* Open the I2C transfer interface if available. */ + err = i2c_master_w_transfer_open(p_cfg); + if (FSP_SUCCESS != err) + { + return err; + } +#endif + + p_ctrl->p_buff = NULL; + p_ctrl->total = 0U; + p_ctrl->nof_bytes = 0U; + p_ctrl->loaded = 0U; + p_ctrl->read = false; + p_ctrl->restart = false; + p_ctrl->restarted = false; + p_ctrl->open = I2C_MASTER_W_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Performs a read from the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_RX_COMPLETE in the callback. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[out] p_dest Pointer to the destination buffer. + * @param[in] bytes Number of bytes to be read. + * @param[in] restart Restart information about this transfer. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl, p_dest or bytes is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than the configured TX buffer size or more than + * UINT16_MAX(= 65535) while DTC/DMAC is used for data transfer. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control block. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::reset. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Read (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart) +{ +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ASSERT(0U != bytes); +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of i2c_master_w_read_write to 4. */ + ((i2c_master_w_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Read operation.*/ + err = i2c_master_w_read_write(p_api_ctrl, p_dest, bytes, I2C_MASTER_W_TRANSFER_DIR_READ); + + return err; +} + +/*******************************************************************************************************************//** + * Performs a write to the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_TX_COMPLETE in the callback. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[in] p_src Pointer to the source buffer. + * @param[in] bytes Number of bytes to be write. + * @param[in] restart Restart information about this transfer. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_src is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than the configured TX buffer size or more than + * UINT16_MAX(= 65535) while DTC/DMAC is used for data transfer. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control block. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::reset. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart) +{ +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of i2c_master_w_read_write to 4. */ + ((i2c_master_w_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Write operation.*/ + err = i2c_master_w_read_write(p_api_ctrl, p_src, bytes, I2C_MASTER_W_TRANSFER_DIR_WRITE); + + return err; +} + +/*******************************************************************************************************************//** + * Safely aborts any in-progress transfer and forces the I2C peripheral into ready state. + * + * @param[in] p_api_ctrl Pointer to control block. + * + * @retval FSP_SUCCESS Channel was reset successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control block. + * @retval FSP_ERR_TIMEOUT Device is stuck & cannot be disabled. To recover from such an issue you can: + * - reset the SCLK & SDA pins, + * - disable PD_COM, + * - perform a HW reset. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Abort (i2c_master_ctrl_t * const p_api_ctrl) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(I2C_MASTER_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable interrupts immediately. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = 0; +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + p_ctrl->p_reg->I2C_MASK_REG = 0; +#endif + + /* This helper function would do a full I2C reset + * followed by re-initializing the required peripheral registers. */ + err = i2c_master_w_open_hw_master(p_ctrl); + + /* Update the transfer descriptor to show no longer in-progress and an error */ + p_ctrl->nof_bytes = p_ctrl->total; + + /* Update the transfer descriptor to make sure interrupts no longer process */ + p_ctrl->loaded = p_ctrl->total; + p_ctrl->restart = false; + p_ctrl->restarted = false; + + return err; +} + +/*******************************************************************************************************************//** + * Sets address and addressing mode of the slave device. + * This function is used to set the device address and addressing mode of the slave + * without reconfiguring the entire bus. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[in] slave Denotes the slave device. + * @param[in] addr_mode Addressing mode (7 bit or 10 bit). + * + * @retval FSP_SUCCESS Address of the slave is set correctly. + * @retval FSP_ERR_ASSERTION Pointer to control structure is NULL. + * @retval FSP_ERR_IN_USE Another transfer was in-progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control + * block. + * @retval FSP_ERR_TIMEOUT Device is stuck & cannot be disabled. To recover from such an issue you can: + * - reset the SCLK & SDA pins, + * - disable PD_COM, + * - perform a HW reset. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(I2C_MASTER_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress. */ + FSP_ERROR_RETURN(((p_ctrl->loaded == p_ctrl->total) && (false == p_ctrl->restart)), FSP_ERR_IN_USE); +#endif + + /* Sets the address of the slave device. */ + p_ctrl->slave = slave; + err = i2c_master_w_set_target_address(p_ctrl); + + /* Sets the mode of addressing. */ + p_ctrl->addr_mode = addr_mode; + + /* Sets target addressing mode. */ + p_ctrl->p_reg->I2C_CON_REG_b.I2C_10BITADDR_MASTER = + ((I2C_MASTER_ADDR_MODE_10BIT == p_ctrl->p_cfg->addr_mode) ? 1 : 0); + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[in] p_callback Pointer to the callback. + * @param[in] p_context Pointer to context. + * @param[in] p_callback_memory Pointer to the callback memory. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(I2C_MASTER_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback. */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure. */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context. */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[out] p_status Pointer to the I2C status. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); +#endif + + p_status->open = (I2C_MASTER_W_OPEN == p_ctrl->open); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the I2C device. May power down I2C peripheral. + * This function will safely terminate any in-progress I2C transfers. + * + * @param[in] p_api_ctrl Pointer to control block. + * + * @retval FSP_SUCCESS Device closed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control block. + * @retval FSP_ERR_TIMEOUT Device is stuck & cannot be disabled. To recover from such an issue you can: + * - reset the SCLK & SDA pins, + * - disable PD_COM, + * - perform a HW reset. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + **********************************************************************************************************************/ +fsp_err_t R_I2C_MASTER_W_Close (i2c_master_ctrl_t * const p_api_ctrl) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(I2C_MASTER_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Update the transfer descriptor to show no longer in-progress and an error. */ + p_ctrl->nof_bytes = 0U; + + /* Update the transfer descriptor to make sure interrupts no longer process. */ + p_ctrl->loaded = p_ctrl->total; + p_ctrl->restart = false; + p_ctrl->restarted = false; + + FSP_CRITICAL_SECTION_DEFINE; + + FSP_CRITICAL_SECTION_ENTER; + + /* Abort any ongoing transaction. */ + i2c_master_w_abort_transfer(p_ctrl); + + /* Disable events for both GEN & dedicated TXE, RX & TXR interrupts. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = 0; +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + p_ctrl->p_reg->I2C_MASK_REG = 0; +#endif + + /* Disable I2C controller. */ + err = i2c_master_w_disable(p_ctrl); + + /* Disable I2C clock. */ + i2c_master_w_disable_clk(p_ctrl->p_cfg->channel); + + /* The device is now considered closed. */ + p_ctrl->open = 0U; + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + + /* Close the handles for the transfer interfaces. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + #if I2C_MASTER_W_CFG_DTC_ENABLE + R_BSP_IrqClearPending(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + #endif + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + #if I2C_MASTER_W_CFG_DTC_ENABLE + R_BSP_IrqClearPending(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + #endif + } +#endif + + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + R_BSP_IrqDisable(p_extend->gen_irq); + + FSP_CRITICAL_SECTION_EXIT; + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup I2C_MASTER_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Read or Write. + * + * @param[in] p_api_ctrl Pointer to control block. + * @param[in] p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction I2C direction Read or Write. + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than the configured TX buffer size or more than + * UINT16_MAX(= 65535) while DTC/DMAC is used for data transfer. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_I2C_MASTER_W_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_read_write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + i2c_master_w_transfer_dir_t direction) +{ + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) p_api_ctrl; + +#if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_buffer); + FSP_ERROR_RETURN((I2C_MASTER_W_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((i2c_master_w_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN((bytes <= I2C_MASTER_W_CFG_TRANSFER_API_TX_BUFFER_SIZE), FSP_ERR_INVALID_SIZE); + #endif +#endif + + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + + p_ctrl->read = (bool) direction; + + if (I2C_MASTER_W_TRANSFER_DIR_WRITE == p_ctrl->read) + { + i2c_master_w_write_configure(p_ctrl); + } + else + { + i2c_master_w_read_configure(p_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + * @param[in] event The event code to pass to the callback. + **********************************************************************************************************************/ +static void i2c_master_w_notify (i2c_master_w_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) +{ + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + + /* Stop any DTC assisted transfer for TX. */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (!p_ctrl->read) + { + if (NULL != p_transfer_tx) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + } + else + { + /* Stop any DTC assisted transfer for RX. */ + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } + + if (NULL != p_transfer_tx) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + } +#endif + + /* Disable all events for the Generic interrupt. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = 0; + + /* Disable all events for the dedicated interrupts. */ +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + p_ctrl->p_reg->I2C_MASK_REG = 0; +#endif +#if !I2C_MASTER_W_CFG_GENERIC_ONLY + R_BSP_IrqClearPending(p_ctrl->p_cfg->txi_irq); +#endif + + /* Now do the callback here. */ +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order + * to call the callback. */ + i2c_master_w_prv_ns_callback p_callback = (i2c_master_w_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in + * order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a master. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + * + * @retval FSP_SUCCESS Function executed successfully. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_open_hw_master (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + fsp_err_t err = FSP_SUCCESS; + + /* Enable I2C clock. */ + i2c_master_w_enable_clk(p_ctrl->p_cfg->channel, p_extend->select_divn); + + /* Abort any ongoing transaction. */ + i2c_master_w_abort_transfer(p_ctrl); + + /* Disable I2C controller. */ + err = i2c_master_w_disable(p_ctrl); + + /* Disable events for both GEN & dedicated TXE, RX & TXR interrupts. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = 0; +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + p_ctrl->p_reg->I2C_MASK_REG = 0; +#endif + + /* Configure master clock settings & communication speed. */ + i2c_master_w_configure_speed(p_ctrl); + + /* Set mode, addressing mode & target's address. */ + err = i2c_master_w_mode_address_set(p_ctrl); + + /* Enable the I2C Controller. */ + p_ctrl->p_reg->I2C_ENABLE_REG_b.I2C_EN = 1; + + /* Set valid interrupt contexts and user provided priority. Enable the interrupts at the NVIC. */ + R_BSP_IrqCfgEnable(p_extend->gen_irq, p_extend->gen_ipl, p_ctrl); +#if I2C_MASTER_W_CFG_DTC_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + /* If DTC is used, configure TX FIFO threshold to "completely empty". */ + p_ctrl->p_reg->I2C_TX_TL_REG = 0; + } + else +#endif + { + /* Configure TX FIFO threshold to at least 1 empty entry. */ + p_ctrl->p_reg->I2C_TX_TL_REG = I2C_MASTER_W_FIFO_DEPTH - 1; + } + + /* Configure RX FIFO threshold to at least one entry. */ + p_ctrl->p_reg->I2C_RX_TL_REG = 0; + +#if !I2C_MASTER_W_CFG_GENERIC_ONLY + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->ipl, p_ctrl); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Disables I2C. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_TIMEOUT Timeout error. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_disable (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + /* Disable I2C controller */ + p_ctrl->p_reg->I2C_ENABLE_REG_b.I2C_EN = 0; + + /* wait until controller is disabled. */ + uint32_t times = 0; + while (1 == p_ctrl->p_reg->I2C_ENABLE_STATUS_REG_b.IC_EN) + { + /* We shouldn't get stuck here, the I2C block should eventually be disabled. */ + FSP_ERROR_RETURN((times++ < I2C_ENABLE_LOOP_LIMIT), FSP_ERR_TIMEOUT); + R_BSP_SoftwareDelay(I2C_ENABLE_STATUS_INTERVAL, BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets I2C master mode, addressing mode & target's address. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + * + * @retval FSP_SUCCESS Function executed successfully. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_mode_address_set (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Set master mode. */ + uint32_t tmp = p_ctrl->p_reg->I2C_CON_REG; + FSP_REG_VAR_FIELD_SET(I2C, I2C_CON_REG, I2C_MASTER_MODE, tmp, 1); + FSP_REG_VAR_FIELD_SET(I2C, I2C_CON_REG, I2C_SLAVE_DISABLE, tmp, 1); + p_ctrl->p_reg->I2C_CON_REG = tmp; + + /* Set the Master HS Code ID. */ + if (0 == p_ctrl->p_cfg->channel) + { + p_ctrl->p_reg->I2C_HS_MADDR_REG_b.I2C_IC_HS_MAR = I2C_MASTER_W_I2C1_MADDR; + } + else if (1 == p_ctrl->p_cfg->channel) + { + p_ctrl->p_reg->I2C_HS_MADDR_REG_b.I2C_IC_HS_MAR = I2C_MASTER_W_I2C2_MADDR; + } + else + { + p_ctrl->p_reg->I2C_HS_MADDR_REG_b.I2C_IC_HS_MAR = I2C_MASTER_W_I2C3_MADDR; + } + + /* Set target's addressing mode. */ + p_ctrl->p_reg->I2C_CON_REG_b.I2C_10BITADDR_MASTER = + ((I2C_MASTER_ADDR_MODE_10BIT == p_ctrl->p_cfg->addr_mode) ? 1 : 0); + + /* Set target's address. */ + err = i2c_master_w_set_target_address(p_ctrl); + + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->I2C_STATUS_REG_b.MST_ACTIVITY, 0); + + return err; +} + +/*******************************************************************************************************************//** + * Sets target address. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + * + * @retval FSP_SUCCESS Function executed successfully. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_set_target_address (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Check if I2C is enabled. */ + if (p_ctrl->p_reg->I2C_ENABLE_STATUS_REG_b.IC_EN) + { + /* Check if master is busy. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->I2C_STATUS_REG_b.MST_ACTIVITY, 0); + + err = i2c_master_w_disable(p_ctrl); + + p_ctrl->p_reg->I2C_TAR_REG_b.IC_TAR = p_ctrl->slave & I2C_I2C_TAR_REG_IC_TAR_Msk; + + /* Enable I2C. */ + p_ctrl->p_reg->I2C_ENABLE_REG_b.I2C_EN = 1; + } + else + { + p_ctrl->p_reg->I2C_TAR_REG_b.IC_TAR = p_ctrl->slave & I2C_I2C_TAR_REG_IC_TAR_Msk; + } + + return err; +} + +/*******************************************************************************************************************//** + * Enables I2C clock. + * + * @param [in] channel I2C selected channel. + * @param [in] select_divn I2C selected DIVN. + **********************************************************************************************************************/ +static void i2c_master_w_enable_clk (uint8_t channel, bool select_divn) +{ + if (select_divn) + { + RESET_CLK_COM_REG = RESET_CLK_COM_I2C_CLK_SEL << (channel * 2); + SET_CLK_COM_REG = SET_CLK_COM_I2C_ENABLE << (channel * 2); + } + else + { + SET_CLK_COM_REG = (SET_CLK_COM_I2C_CLK_SEL << (channel * 2)) | + (SET_CLK_COM_I2C_ENABLE << (channel * 2)); + } +} + +/*******************************************************************************************************************//** + * Disables I2C clock. + * + * @param [in] channel I2C selected channel. + **********************************************************************************************************************/ +static void i2c_master_w_disable_clk (uint8_t channel) +{ + RESET_CLK_COM_REG = RESET_CLK_COM_I2C_ENABLE << (channel * 2); +} + +/*******************************************************************************************************************//** + * Abort I2C transfer. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + **********************************************************************************************************************/ +static void i2c_master_w_abort_transfer (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + if (p_ctrl->p_reg->I2C_CON_REG_b.I2C_MASTER_MODE) + { + p_ctrl->p_reg->I2C_ENABLE_REG_b.I2C_ABORT = 1; + } +} + +/*******************************************************************************************************************//** + * Configures I2C master clock settings & transaction speed. + * + * @param[in] p_ctrl Pointer to I2C specific control structure. + **********************************************************************************************************************/ +static void i2c_master_w_configure_speed (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + switch (p_ctrl->p_cfg->rate) + { + case I2C_MASTER_RATE_HIGHSPEED: + { + p_ctrl->p_reg->I2C_HS_SCL_HCNT_REG = p_extend->clock_settings.scl_hcnt; + p_ctrl->p_reg->I2C_HS_SCL_LCNT_REG = p_extend->clock_settings.scl_lcnt; + p_ctrl->p_reg->I2C_CON_REG_b.I2C_SPEED = 3; + break; + } + + case I2C_MASTER_RATE_FASTPLUS: + case I2C_MASTER_RATE_FAST: + { + p_ctrl->p_reg->I2C_FS_SCL_HCNT_REG = p_extend->clock_settings.scl_hcnt; + p_ctrl->p_reg->I2C_FS_SCL_LCNT_REG = p_extend->clock_settings.scl_lcnt; + p_ctrl->p_reg->I2C_CON_REG_b.I2C_SPEED = 2; + break; + } + + case I2C_MASTER_RATE_STANDARD: + default: + { + p_ctrl->p_reg->I2C_SS_SCL_HCNT_REG = p_extend->clock_settings.scl_hcnt; + p_ctrl->p_reg->I2C_SS_SCL_LCNT_REG = p_extend->clock_settings.scl_lcnt; + p_ctrl->p_reg->I2C_CON_REG_b.I2C_SPEED = 1; + break; + } + } +} + +/*******************************************************************************************************************//** + * Activates the required interrupt sources for read. + * + * It initiates an I2C read transmission. + * + * @param [in] p_ctrl Pointer to I2C specific control structure. + **********************************************************************************************************************/ +static void i2c_master_w_read_configure (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + uint16_t mask = I2C_MASTER_W_INT_TX_ABORT; + + /* Clear TX ABORT interrupt status. */ + p_ctrl->p_reg->I2C_CLR_TX_ABRT_REG; + + if (0 == p_ctrl->restart) + { + mask |= I2C_MASTER_W_INT_STOP_DETECTED; + + /* Clear STOP DETECTED interrupt status. */ + p_ctrl->p_reg->I2C_CLR_STOP_DET_REG; + } + + /* Initialize fields used during transfer. */ + p_ctrl->loaded = 0U; + p_ctrl->nof_bytes = 0U; + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_rx; + transfer_instance_t * p_transfer_tx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_tx; + + /* Enable RX transfer support if possible. */ + if ((NULL != p_transfer_rx) && (p_ctrl->total > 0U)) + { + uint32_t volatile const * p_i2c_master_w_rx_src_buf = &(p_ctrl->p_reg->I2C_DATA_CMD_REG); + + #if I2C_MASTER_W_CFG_DTC_ENABLE + p_transfer_rx->p_api->reset(p_transfer_rx->p_ctrl, (uint8_t *) (p_i2c_master_w_rx_src_buf), + (void *) (p_ctrl->p_buff), (uint16_t) (p_ctrl->total)); + #else + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + + /* RX operation will be handled by DMA. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + #endif + + /* Make sure I2C DMA is off so it's not unexpectedly triggered when channels are enabled. */ + p_ctrl->p_reg->I2C_DMA_CR_REG = 0; + + /* Configure RX DMA Channel and RX FIFO threshold level for I2C Master. */ + DMAC_EXTENDED_CONFIG * p_dmac_extend = (DMAC_EXTENDED_CONFIG *) p_transfer_rx->p_cfg->p_extend; + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + if ((0 == (p_ctrl->total % 8)) && p_extend->enable_dma_bursts_rx) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_8X; + p_ctrl->p_reg->I2C_DMA_RDLR_REG = 7; + } + else if ((0 == (p_ctrl->total % 4)) && p_extend->enable_dma_bursts_rx) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_4X; + p_ctrl->p_reg->I2C_DMA_RDLR_REG = 3; + } + else + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_NONE; + p_ctrl->p_reg->I2C_DMA_RDLR_REG = 0; + } + + p_transfer_rx->p_cfg->p_info->p_src = (uint8_t *) p_i2c_master_w_rx_src_buf; + p_transfer_rx->p_cfg->p_info->p_dest = (uint8_t *) p_ctrl->p_buff; + p_transfer_rx->p_cfg->p_info->length = (uint16_t) p_ctrl->total; + + p_transfer_rx->p_api->reconfigure(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg->p_info); + p_transfer_rx->p_api->enable(p_transfer_rx->p_ctrl); + + p_ctrl->p_reg->I2C_DMA_CR_REG_b.RDMAE = 1; + #endif + p_ctrl->nof_bytes = p_ctrl->total; + } + + #if I2C_MASTER_W_CFG_GENERIC_ONLY + else + { + mask |= I2C_MASTER_W_INT_RX_FULL; + } + #endif + + /* Enable TX transfer support if possible for the enqueueing of the READ commands. */ + if ((NULL != p_transfer_tx) && (p_ctrl->read) && (p_ctrl->total > 0U)) + { + bool add_stop; + bool add_restart; + + /* Pack commands with READ request, STOP/RESTART information. */ + while (p_ctrl->loaded < p_ctrl->total) + { + add_stop = (p_ctrl->loaded + 1 == p_ctrl->total) && (p_ctrl->restart == 0); + add_restart = ((p_ctrl->loaded == 0) && (p_ctrl->restarted == 1)); + + p_ctrl->p_transfer_api_tx_buff[p_ctrl->loaded] = I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk | + (add_stop ? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk : 0) | + (add_restart ? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk : 0); + + p_ctrl->loaded++; + } + + uint32_t volatile const * p_i2c_master_w_tx_dest_buf = &(p_ctrl->p_reg->I2C_DATA_CMD_REG); + + #if I2C_MASTER_W_CFG_DTC_ENABLE + p_transfer_tx->p_api->reset(p_transfer_tx->p_ctrl, (void *) (p_ctrl->p_transfer_api_tx_buff), + (uint16_t *) (p_i2c_master_w_tx_dest_buf), (uint16_t) (p_ctrl->total)); + #else + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + + /* TX operation will be handled by DMA. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + #endif + + /* Configure TX DMA Channel and TX FIFO threshold level for I2C. */ + DMAC_EXTENDED_CONFIG * p_dmac_extend = (DMAC_EXTENDED_CONFIG *) p_transfer_tx->p_cfg->p_extend; + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + if ((p_ctrl->total < 4) || !(p_extend->enable_dma_bursts_tx)) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_NONE; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = p_ctrl->total; + } + else if (p_ctrl->total < 8) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_4X; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = p_ctrl->total; + } + else + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_8X; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = I2C_MASTER_W_FIFO_DEPTH - 8; + } + + p_transfer_tx->p_cfg->p_info->p_src = (uint16_t *) p_ctrl->p_transfer_api_tx_buff; + p_transfer_tx->p_cfg->p_info->p_dest = (uint16_t *) p_i2c_master_w_tx_dest_buf; + p_transfer_tx->p_cfg->p_info->length = (uint16_t) p_ctrl->total; + + p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg->p_info); + p_transfer_tx->p_api->enable(p_transfer_tx->p_ctrl); + + p_ctrl->p_reg->I2C_DMA_CR_REG_b.TDMAE = 1; + #endif + } + + #if I2C_MASTER_W_CFG_GENERIC_ONLY + else + { + mask |= I2C_MASTER_W_INT_TX_EMPTY; + } + #endif +#elif I2C_MASTER_W_CFG_GENERIC_ONLY + mask |= (I2C_MASTER_W_INT_TX_EMPTY | I2C_MASTER_W_INT_RX_FULL); +#endif + + /* Enable the Generic interrupt events. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = mask; + +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + + /* Unmask dedicated TXE & RX events. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_RX_IRQ_MASK_Msk | I2C_I2C_MASK_REG_I2C_TXE_IRQ_MASK_Msk; +#endif +} + +/*******************************************************************************************************************//** + * Activates the required interrupt sources for write. + * + * It initiates an I2C write transmission. + * + * @param [in] p_ctrl Pointer to I2C specific control structure. + **********************************************************************************************************************/ +static void i2c_master_w_write_configure (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + uint16_t mask = I2C_MASTER_W_INT_TX_ABORT; + + /* Clear TX ABORT interrupt status. */ + p_ctrl->p_reg->I2C_CLR_TX_ABRT_REG; + + if (0 == p_ctrl->restart) + { + mask |= I2C_MASTER_W_INT_STOP_DETECTED; + + /* Clear STOP DETECTED interrupt status. */ + p_ctrl->p_reg->I2C_CLR_STOP_DET_REG; + } + + /* Initialize fields used during transfer. */ + p_ctrl->loaded = 0U; + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + transfer_instance_t * p_transfer_tx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_tx; + + /* Enable transfer support if possible */ + if ((NULL != p_transfer_tx) && (p_ctrl->total > 0U)) + { + bool add_stop; + bool add_restart; + + while (p_ctrl->loaded < p_ctrl->total) + { + add_stop = (p_ctrl->loaded + 1 == p_ctrl->total) && (p_ctrl->restart == 0); + add_restart = (p_ctrl->loaded == 0) && (p_ctrl->restarted == 1); + + /* Add STOP or RESTART to write request for last or first byte if user requires it. */ + p_ctrl->p_transfer_api_tx_buff[p_ctrl->loaded] = (p_ctrl->p_buff[p_ctrl->loaded] | + (add_stop ? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk : 0) | + (add_restart ? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk : 0)); + p_ctrl->loaded++; + } + + uint32_t volatile const * p_i2c_master_w_tx_dest_buf = &(p_ctrl->p_reg->I2C_DATA_CMD_REG); + + #if I2C_MASTER_W_CFG_DTC_ENABLE + p_transfer_tx->p_api->reset(p_transfer_tx->p_ctrl, (void *) (p_ctrl->p_transfer_api_tx_buff), + (uint16_t *) (p_i2c_master_w_tx_dest_buf), (uint16_t) (p_ctrl->total)); + #else + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + + /* TX operation will be handled by DMA. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + #endif + + /* Make sure I2C DMA is off so it's not unexpectedly triggered when channels are enabled. */ + p_ctrl->p_reg->I2C_DMA_CR_REG = 0; + i2c_master_w_extended_cfg_t * p_extend = (i2c_master_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Configure TX DMA Channel and TX FIFO threshold level for I3C. */ + DMAC_EXTENDED_CONFIG * p_dmac_extend = (DMAC_EXTENDED_CONFIG *) p_transfer_tx->p_cfg->p_extend; + + if ((p_ctrl->total < 4) || !(p_extend->enable_dma_bursts_tx)) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_NONE; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = p_ctrl->total; + } + else if (p_ctrl->total < 8) + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_4X; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = p_ctrl->total; + } + else + { + p_dmac_extend->burst_mode = DMAC_BURST_MODE_8X; + p_ctrl->p_reg->I2C_DMA_TDLR_REG = I2C_MASTER_W_FIFO_DEPTH - 8; + } + + p_transfer_tx->p_cfg->p_info->p_src = (uint16_t *) p_ctrl->p_transfer_api_tx_buff; + p_transfer_tx->p_cfg->p_info->p_dest = (uint16_t *) p_i2c_master_w_tx_dest_buf; + p_transfer_tx->p_cfg->p_info->length = (uint16_t) p_ctrl->total; + + p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg->p_info); + p_transfer_tx->p_api->enable(p_transfer_tx->p_ctrl); + + p_ctrl->p_reg->I2C_DMA_CR_REG = I2C_I2C_DMA_CR_REG_TDMAE_Msk; + #endif + } + + #if I2C_MASTER_W_CFG_GENERIC_ONLY + else + { + mask |= I2C_MASTER_W_INT_TX_EMPTY; + } + #endif +#elif I2C_MASTER_W_CFG_GENERIC_ONLY + mask |= I2C_MASTER_W_INT_TX_EMPTY; +#endif + +#if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + #if (BSP_FEATURE_I2C_VERSION == 1) + + /* Unmask dedicated TXE event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXE_IRQ_MASK_Msk; + #elif (BSP_FEATURE_I2C_VERSION == 2) + + /* Unmask dedicated TXE and TXR events. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXE_IRQ_MASK_Msk | I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; + #endif +#endif + + /* Enable the Generic interrupt events. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG = mask; +} + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + +/*******************************************************************************************************************//** + * Configures I2C related transfer drivers (if enabled). + * + * @param[in] p_cfg Pointer to I2C specific configuration structure. + * + * @retval FSP_SUCCESS Transfer interface initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance p_api, p_cfg or p_cfg->p_info are NULL. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_transfer_open (i2c_master_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_cfg->p_transfer_rx) + { + err = i2c_master_w_transfer_configure(p_cfg->p_transfer_rx, I2C_MASTER_W_TRANSFER_DIR_READ); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + err = i2c_master_w_transfer_configure(p_cfg->p_transfer_tx, I2C_MASTER_W_TRANSFER_DIR_WRITE); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures I2C related transfer. + * @param[in] p_transfer Pointer to transfer instance. + * @param[in] direction I2C direction Read or Write. + * + * @retval FSP_SUCCESS Transfer interface is configured with valid parameters. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance p_api, p_cfg or p_cfg->p_info are NULL. + **********************************************************************************************************************/ +static fsp_err_t i2c_master_w_transfer_configure (transfer_instance_t const * p_transfer, + i2c_master_w_transfer_dir_t direction) +{ + fsp_err_t err; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + #endif + transfer_info_t * p_cfg = p_transfer->p_cfg->p_info; + if (I2C_MASTER_W_TRANSFER_DIR_READ == direction) + { + p_cfg->transfer_settings_word = I2C_MASTER_W_DTC_RX_TRANSFER_SETTINGS; + } + else + { + p_cfg->transfer_settings_word = I2C_MASTER_W_DTC_TX_TRANSFER_SETTINGS; + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Performs an I2C read transmission. + * + * @param [in] p_ctrl Pointer to I2C specific control structure. + * @param [in] event Event from Interrupt Status Register. + * + **********************************************************************************************************************/ +static void i2c_master_w_isr_rx_handler (i2c_master_w_instance_ctrl_t * p_ctrl, uint32_t event) +{ +#if I2C_MASTER_W_CFG_GENERIC_ONLY + bool add_stop; + bool add_restart; + + /* Send CMDs to issue READ requests. */ + while ((p_ctrl->loaded < p_ctrl->total) && p_ctrl->p_reg->I2C_STATUS_REG_b.TFNF) + { + p_ctrl->loaded++; + + add_stop = ((p_ctrl->loaded == p_ctrl->total) && (p_ctrl->restart == 0)); + add_restart = ((p_ctrl->loaded == 1) && (p_ctrl->restarted == 1)); + + /* Add STOP or RESTART to read request for last or first byte. */ + p_ctrl->p_reg->I2C_DATA_CMD_REG = I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk | + (add_stop ? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk : 0) | + (add_restart ? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk : 0);; + } + + /* All command data have been send. */ + if ((event & I2C_MASTER_W_INT_TX_EMPTY) && (p_ctrl->loaded == p_ctrl->total)) + { + /* Mask TX Empty event both in Generic and dedicated TXE interrupts. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG_b.M_TX_EMPTY = 0; + #if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + p_ctrl->p_reg->I2C_MASK_REG_b.I2C_TXE_IRQ_MASK = 0; + #endif + } + +#else + FSP_PARAMETER_NOT_USED(event); +#endif + + /* Read data from RX FIFO. */ + while (p_ctrl->p_reg->I2C_RXFLR_REG_b.RXFLR && p_ctrl->nof_bytes < p_ctrl->total) + { + p_ctrl->p_buff[p_ctrl->nof_bytes] = p_ctrl->p_reg->I2C_DATA_CMD_REG_b.I2C_DAT; + p_ctrl->nof_bytes++; + } + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + if (NULL == p_ctrl->p_cfg->p_transfer_rx) + { +#endif + + /* All data have been read. */ + if (p_ctrl->nof_bytes == p_ctrl->total) + { + if (p_ctrl->restart) + { + p_ctrl->restart = false; + p_ctrl->restarted = true; + } + + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_RX_COMPLETE); + } + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) +} +#endif +} + +/*******************************************************************************************************************//** + * Performs an I2C write transmission. + * + * @param [in] p_ctrl Pointer to I2C specific control structure. + * + **********************************************************************************************************************/ +static void i2c_master_w_isr_tx_handler (i2c_master_w_instance_ctrl_t * p_ctrl) +{ + bool add_stop; + bool add_restart; + + while (p_ctrl->loaded < p_ctrl->total && p_ctrl->p_reg->I2C_STATUS_REG_b.TFNF) + { + add_stop = ((p_ctrl->loaded + 1 == p_ctrl->total) && (p_ctrl->restart == 0)); + add_restart = ((p_ctrl->loaded == 0) && (p_ctrl->restarted == 1)); + + /* Add STOP or RESTART to write request for last or first byte if user requires it. */ + p_ctrl->p_reg->I2C_DATA_CMD_REG = p_ctrl->p_buff[p_ctrl->loaded] | + (add_stop ? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk : 0) | + (add_restart ? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk : 0); + + p_ctrl->loaded++; + } + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + { +#endif + + /* Trigger reply when all data were written to TX FIFO. */ + if (p_ctrl->loaded == p_ctrl->total) + { +#if (BSP_FEATURE_I2C_HAS_DEDICATED_IRQS && (BSP_FEATURE_I2C_VERSION == 1)) + + /* Enable the dedicated Transmit End event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; +#endif + if (p_ctrl->restart) + { + p_ctrl->restart = false; + p_ctrl->restarted = true; +#if (I2C_MASTER_W_CFG_GENERIC_ONLY || (BSP_FEATURE_I2C_VERSION == 2)) + + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_TX_COMPLETE); +#endif + } + +#if I2C_MASTER_W_CFG_GENERIC_ONLY + else + { + /* Disable TX Empty Interrupt event. */ + p_ctrl->p_reg->I2C_INTR_MASK_REG_b.M_TX_EMPTY = 0; + } +#endif + } + +#if (I2C_MASTER_W_CFG_DTC_ENABLE) || (I2C_MASTER_W_CFG_DMA_ENABLE) +} +#endif +} + +/******************************************************************************************************************//** + * Generic I2C Event interrupt routine. + * + * This function implements the Generic ISR routine. + *********************************************************************************************************************/ +void i2c_master_w_gen_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); +#if BSP_FEATURE_BSP_HAS_ICU + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); +#endif + + uint32_t mask = p_ctrl->p_reg->I2C_INTR_STAT_REG; + + if (mask & I2C_MASTER_W_INT_TX_ABORT) + { + /* Notify anyone waiting that the transfer is Aborted due to error. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + + /* Mark the transaction as completed. */ + p_ctrl->loaded = p_ctrl->total; + + /* Clear abort. */ + p_ctrl->p_reg->I2C_CLR_TX_ABRT_REG; + +#if !I2C_MASTER_W_CFG_GENERIC_ONLY + R_BSP_IrqClearPending(p_ctrl->p_cfg->tei_irq); + p_ctrl->p_reg->I2C_MASK_REG = 0; +#endif + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; + + return; + } + + if (mask & I2C_MASTER_W_INT_STOP_DETECTED) + { +#if I2C_MASTER_W_CFG_GENERIC_ONLY + if (p_ctrl->loaded == p_ctrl->total) + { + /* Notify anyone waiting that the transfer is completed. */ + if (I2C_MASTER_W_TRANSFER_DIR_WRITE == p_ctrl->read) + { + #if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + + /* Enable the dedicated Transmit End event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; + #endif + + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_TX_COMPLETE); + } + else + { + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_RX_COMPLETE); + } + } + else + { + /* Notify anyone waiting that the transfer is Aborted due to error. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + + /* Mark the transaction as completed. */ + p_ctrl->loaded = p_ctrl->total; + } + +#else + if (I2C_MASTER_W_TRANSFER_DIR_WRITE == p_ctrl->read) + { + #if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + + /* Enable the dedicated Transmit End event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; + #endif + } + else + { + if (p_ctrl->loaded == p_ctrl->total) + { + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_RX_COMPLETE); + } + else + { + /* Notify anyone waiting that the transfer is Aborted due to error. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + + /* Mark the transaction as completed. */ + p_ctrl->loaded = p_ctrl->total; + } + } +#endif + + /* Reset restarted status */ + if (p_ctrl->restarted) + { + p_ctrl->restarted = false; + } + + /* Reset STOP_DETECTED interrupt state. */ + p_ctrl->p_reg->I2C_CLR_STOP_DET_REG; + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; + + return; + } + +#if I2C_MASTER_W_CFG_GENERIC_ONLY + + /* Call handler. */ + if (I2C_MASTER_W_TRANSFER_DIR_WRITE == p_ctrl->read) + { + i2c_master_w_isr_tx_handler(p_ctrl); + } + else + { + i2c_master_w_isr_rx_handler(p_ctrl, mask); + } +#endif + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; +} + +#if !I2C_MASTER_W_CFG_GENERIC_ONLY + +/******************************************************************************************************************//** + * I2C RX FIFO Full Event interrupt routine. + * + * This function implements the RXI ISR routine. + *********************************************************************************************************************/ +void i2c_master_w_rxi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + #if BSP_FEATURE_I2C_IRQ_TRIGGER_EDGE + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); + #endif + + #if I2C_MASTER_W_CFG_DTC_ENABLE + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_rx; + + /* Check if DTC is enabled. */ + if (NULL != p_transfer_rx) + { + p_ctrl->p_reg->I2C_MASK_REG = 0; + R_BSP_IrqClearPending(p_ctrl->p_cfg->rxi_irq); + + if (p_ctrl->restart) + { + p_ctrl->restart = false; + p_ctrl->restarted = true; + + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_RX_COMPLETE); + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; + + return; + } + #endif + + /* Call handler. */ + if (I2C_MASTER_W_TRANSFER_DIR_READ == p_ctrl->read) + { + i2c_master_w_isr_rx_handler(p_ctrl, I2C_MASTER_W_INT_RX_FULL); + } + + #if !BSP_FEATURE_I2C_IRQ_TRIGGER_EDGE + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; +} + +/******************************************************************************************************************//** + * I2C TX FIFO Empty Event interrupt routine. + * + * This function implements the TXI ISR routine. + *********************************************************************************************************************/ +void i2c_master_w_txi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + #if BSP_FEATURE_I2C_IRQ_TRIGGER_EDGE + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); + #endif + + #if I2C_MASTER_W_CFG_DTC_ENABLE + transfer_instance_t * p_transfer_tx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_tx; + + /* Check if DTC is enabled. */ + if (NULL != p_transfer_tx) + { + p_ctrl->p_reg->I2C_MASK_REG_b.I2C_TXE_IRQ_MASK = 0; + R_BSP_IrqClearPending(p_ctrl->p_cfg->txi_irq); + + if (!p_ctrl->read) + { + if (p_ctrl->restart) + { + p_ctrl->restart = false; + p_ctrl->restarted = true; + + /* Enable the dedicated Transmit End event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; + } + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; + + return; + } + #endif + + /* Call handler. */ + if (I2C_MASTER_W_TRANSFER_DIR_WRITE == p_ctrl->read) + { + i2c_master_w_isr_tx_handler(p_ctrl); + } + else + { + bool add_stop; + bool add_restart; + + /* Send CMDs to issue READ requests. */ + while ((p_ctrl->loaded < p_ctrl->total) && p_ctrl->p_reg->I2C_STATUS_REG_b.TFNF) + { + p_ctrl->loaded++; + add_stop = (p_ctrl->loaded == p_ctrl->total) && (p_ctrl->restart == 0); + add_restart = (p_ctrl->loaded == 1) && (p_ctrl->restarted == 1); + /* Add STOP or RESTART to read request for last or first byte. */ + p_ctrl->p_reg->I2C_DATA_CMD_REG = I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk | + (add_stop ? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk : 0) | + (add_restart ? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk : 0); + } + + /* All command data have been send. */ + if (p_ctrl->loaded == p_ctrl->total) + { + /* Mask the dedicated TXE interrupt. */ + p_ctrl->p_reg->I2C_MASK_REG_b.I2C_TXE_IRQ_MASK = 0; + } + } + + #if !BSP_FEATURE_I2C_IRQ_TRIGGER_EDGE + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; +} + +/******************************************************************************************************************//** + * I2C Transmission End Event interrupt routine. + * + * This function implements the TEI ISR routine. + *********************************************************************************************************************/ +void i2c_master_w_tei_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + i2c_master_w_instance_ctrl_t * p_ctrl = (i2c_master_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IR flag in the ICU. */ + R_BSP_IrqStatusClear(irq); + + if (p_ctrl->loaded == p_ctrl->total) + { + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_TX_COMPLETE); + } + else + { + /* Notify anyone waiting that the transfer is Aborted due to error. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + + /* Mark the transaction as completed. */ + p_ctrl->loaded = p_ctrl->total; + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (I2C_MASTER_W_CFG_DMA_ENABLE) + +/*******************************************************************************************************************//** + * Callback that must be called after a RX DMAC transfer completes with restart condition. + * + * @param[in] p_ctrl Pointer to I2C Master instance control block + **********************************************************************************************************************/ +void i2c_master_w_rx_dmac_callback (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + #endif + if (p_ctrl->restart) + { + p_ctrl->restart = false; + p_ctrl->restarted = true; + + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_RX_COMPLETE); + } +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes with restart condition. + * + * @param[in] p_ctrl Pointer to I2C Master instance control block + **********************************************************************************************************************/ +void i2c_master_w_tx_dmac_callback (i2c_master_w_instance_ctrl_t * const p_ctrl) +{ + #if !I2C_MASTER_W_CFG_GENERIC_ONLY + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + #endif + if (p_ctrl->restart) + { + if (p_ctrl->read) + { + #if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + + /* Mask the dedicated TXE interrupt. */ + p_ctrl->p_reg->I2C_MASK_REG_b.I2C_TXE_IRQ_MASK = 0; + #endif + } + else + { + p_ctrl->restart = false; + p_ctrl->restarted = true; + #if BSP_FEATURE_I2C_HAS_DEDICATED_IRQS + + /* Enable the dedicated Transmit End event. */ + p_ctrl->p_reg->I2C_MASK_REG = I2C_I2C_MASK_REG_I2C_TXR_IRQ_MASK_Msk; + #endif + + #if I2C_MASTER_W_CFG_GENERIC_ONLY + + /* Notify anyone waiting that the transfer is completed. */ + i2c_master_w_notify(p_ctrl, I2C_MASTER_EVENT_TX_COMPLETE); + #endif + } + } +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ospi_w/r_ospi_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ospi_w/r_ospi_w.c new file mode 100644 index 000000000000..5e852dcfaf56 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_ospi_w/r_ospi_w.c @@ -0,0 +1,1429 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ospi_w.h" + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM static void r_ospi_w_wait_while_busy(void); +BSP_PLACE_CODE_IN_RAM static void r_ospi_w_write_enable(void); +BSP_PLACE_CODE_IN_RAM void ospi_w_set_bus_mode(ospi_w_device_bus_mode bus_mode); +BSP_PLACE_CODE_IN_RAM void ospi_w_flash_sector_erase(uint8_t se_cmd, + ospi_w_device_addr_size mode, + uint32_t addr); +BSP_PLACE_CODE_IN_RAM static uint32_t r_ospi_w_flash_write_page(spi_flash_ctrl_t * const p_ctrl, + uint32_t addr, + const uint8_t * buf, + uint32_t size); +BSP_PLACE_CODE_IN_RAM static uint32_t r_ospi_w_flash_write_page_safe(spi_flash_ctrl_t * const p_ctrl, + uint32_t addr, + const uint8_t * buf, + uint32_t size); +BSP_PLACE_CODE_IN_RAM uint8_t r_ospi_flash_read_register(uint8_t cmd, + uint8_t mask, + ospi_w_device_bus_mode bus_mode); +BSP_PLACE_CODE_IN_RAM bool r_ospi_flash_is_busy(spi_flash_ctrl_t * const p_ctrl); +BSP_PLACE_CODE_IN_RAM void r_ospi_w_memcpy(void * dest, const void * src, size_t count); + +void r_ospi_w_flash_rd_buf(uint8_t * rd_buf, size_t rd_buf_size); +void r_ospi_w_flash_cfg_read(uint8_t rd_cmd, uint32_t address); +void r_ospi_w_reset(); + +spi_flash_api_t g_ospi_w_on_spi_flash = +{ + .open = R_OSPI_W_Open, + .directWrite = R_OSPI_W_DirectWrite, + .directRead = R_OSPI_W_DirectRead, + .directTransfer = R_OSPI_W_DirectTransfer, + .spiProtocolSet = R_OSPI_W_SpiProtocolSet, + .write = R_OSPI_W_Write, + .erase = R_OSPI_W_Erase, + .statusGet = R_OSPI_W_StatusGet, + .xipEnter = R_OSPI_W_XipEnter, + .xipExit = R_OSPI_W_XipExit, + .bankSet = R_OSPI_W_BankSet, + .autoCalibrate = R_OSPI_W_AutoCalibrate, + .close = R_OSPI_W_Close, +}; + +/*******************************************************************************************************************//** + * Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory. + * + * Implements @ref spi_flash_api_t::open. + * + * Example: + * @snippet r_ospi_w_example.c R_OSPI_W_Open + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl or p_cfg is NULL. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_ctrl. + * @retval FSP_ERR_INVALID_ARGUMENT Attempting to open the driver with an invalid SPI protocol for OctaRAM. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Open (spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + + // ospi_w_device_config_t * p_ospi_config; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); +#endif + + ospi_w_extended_cfg_t * p_cfg_extend = (ospi_w_extended_cfg_t *) p_cfg->p_extend; + FSP_CRITICAL_SECTION_DEFINE; + + /* Initialize control block. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->channel = p_cfg_extend->channel; + p_instance_ctrl->p_cmd_set = p_cfg_extend->p_xspi_command_set_list; + p_instance_ctrl->spi_protocol = p_cfg->spi_protocol; + + if (p_cfg_extend == NULL) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + if (p_cfg_extend->p_ospi_w_device_cfg != NULL) + { + r_ospi_w_device_init(p_cfg_extend->p_ospi_w_device_cfg); + } + + if (p_instance_ctrl->open == 0) + { + FSP_CRITICAL_SECTION_ENTER; + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_MANUAL); + if ((p_cfg_extend->p_read_instr_cfg != NULL) && (p_cfg_extend->p_read_instr_cfg->enable)) + { + r_ospi_w_device_read_instr_init(p_cfg_extend->p_read_instr_cfg); + + /* settings for automode erase */ + if (p_cfg_extend->p_read_instr_cfg->instr_mode == OSPI_W_DEVICE_INSTR_MODE_SEND_ONCE) + { + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_WRD = 0xffff; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_SZ = 3; // 4byte + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_TX_MD = OSPI_W_DEVICE_BUS_MODE_SINGLE; + OQSPIF->OQSPIF_BURSTBRK_REG_b.OSPIC_BRK_EN = 1; + } + } + + if ((p_cfg_extend->p_wrap_burst_instr_cfg != NULL) && (p_cfg_extend->p_wrap_burst_instr_cfg->enable)) + { + r_ospi_w_device_wrap_burst_instr_init(p_cfg_extend->p_wrap_burst_instr_cfg); + } + + if ((p_cfg_extend->p_erase_instr_cfg != NULL) && (p_cfg_extend->p_erase_instr_cfg->enable)) + { + r_ospi_w_device_erase_instr_init(p_cfg_extend->p_erase_instr_cfg); + } + + if ((p_cfg_extend->p_read_status_instr_cfg != NULL) && (p_cfg_extend->p_read_status_instr_cfg->enable)) + { + r_ospi_w_device_read_status_instr_init(p_cfg_extend->p_read_status_instr_cfg); + } + + if ((p_cfg_extend->p_write_enable_instr_cfg != NULL) && (p_cfg_extend->p_write_enable_instr_cfg->enable)) + { + r_ospi_w_device_write_enable_instr_init(p_cfg_extend->p_write_enable_instr_cfg); + } + + if ((p_cfg_extend->p_suspend_resume_instr_cfg != NULL) && (p_cfg_extend->p_suspend_resume_instr_cfg->enable)) + { + r_ospi_w_device_suspend_resume_instr_init(p_cfg_extend->p_suspend_resume_instr_cfg); + } + + CRG_TOP->SYS_CTRL_REG_b.CACHERAM_MUX = 0; + do + { + OQSPIF->OQSPIF_CTRLMODE_REG_b.OSPIC_AUTO_MD = 0; // switch off and on automode in order to trigger re-sending the read command. + OQSPIF->OQSPIF_CTRLMODE_REG_b.OSPIC_AUTO_MD = 1; + + if ((*(volatile uint32_t *) 0x0a000000 & 0x0000FFFF) == 0x00007050) + { + break; // if "Pp" was found, we assume the flash is ready to be used in automode. + } + } while (1); + + CRG_TOP->SYS_CTRL_REG_b.CACHERAM_MUX = 1; + FSP_CRITICAL_SECTION_EXIT; + } + + p_instance_ctrl->open++; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close the OSPI driver module. + * + * Implements @ref spi_flash_api_t::close. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Close (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + + if (p_instance_ctrl->open == 0) + { + return FSP_ERR_NOT_OPEN; + } + + p_instance_ctrl->open--; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes raw data directly to the OctaFlash. API not supported. Use R_OSPI_W_DirectTransfer + * + * Implements @ref spi_flash_api_t::directWrite. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectWrite (spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + FSP_PARAMETER_NOT_USED(read_after_write); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reads raw data directly from the OctaFlash. API not supported. Use R_OSPI_W_DirectTransfer. + * + * Implements @ref spi_flash_api_t::directRead. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectRead (spi_flash_ctrl_t * const p_ctrl, + uint8_t * const p_dest, + uint32_t const bytes) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Read/Write raw data directly with the OctaFlash. + * + * Implements @ref spi_flash_api_t::directTransfer. + * + * Example: + * @snippet r_ospi_w_example.c OSPI_W_Read_chip_ID + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT The parameters are wrong. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectTransfer (spi_flash_ctrl_t * const p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint8_t read_cmd = (uint8_t) p_transfer->command; + uint8_t pp_cmd = (uint8_t) p_transfer->command; + uint32_t addr = p_transfer->address; + uint8_t addr_len = p_transfer->address_length; + uint8_t * buf_rd = (uint8_t *) (&(p_transfer->data)); + uint8_t * buf = (uint8_t *) (&(p_transfer->data)); + uint32_t bytes = p_transfer->data_length; + uint32_t automode_backup = 0; + ospi_w_extended_cfg_t * p_extended = (ospi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + if (bytes > 8) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + if (direction == SPI_FLASH_DIRECT_TRANSFER_DIR_READ) + { + /* Check now in automode */ + if (r_ospi_w_device_get_access_mode() == OSPI_W_DEVICE_ACCESS_MODE_AUTO) + { + memcpy((void *) buf_rd, (void *) (addr | OSPI_W_AUTOMODE_BASE_ADD), bytes); + } + else + { + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8(read_cmd); + if (p_extended->p_ospi_w_device_cfg->automode_config.instruct_size == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8(~read_cmd); + } + + if (addr_len == SPI_FLASH_ADDRESS_BYTES_4) + { + r_ospi_w_device_write32(addr); + } + else if (addr_len == SPI_FLASH_ADDRESS_BYTES_3) + { + r_ospi_w_device_write8((uint8_t) (addr >> 16)); + r_ospi_w_device_write8((uint8_t) (addr >> 8)); + r_ospi_w_device_write8((uint8_t) (addr >> 0)); + } + else + { + /* special case such like READ ID */ + } + + if ((read_cmd == OSPI_FAST_READ3B_CMD) || (read_cmd == OSPI_FAST_READ4B_CMD)) + { + r_ospi_w_device_dummy8(); + } + + /* Send dummy cycle */ + if (p_transfer->dummy_cycles) + { + for (uint32_t dummy_cnt = 0; dummy_cnt < (p_transfer->dummy_cycles); dummy_cnt++) + { + r_ospi_w_device_dummy8(); + } + } + + for (uint32_t i = 0; i < bytes; ++i) + { + buf_rd[i] = r_ospi_w_device_read8(); + } + + r_ospi_w_device_cs_disable(); + } + } + else if (direction == SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE) + { + if (r_ospi_w_device_get_access_mode() == OSPI_W_DEVICE_ACCESS_MODE_AUTO) + { + /* turn off auto mode first */ + automode_backup = 1; + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_MANUAL); + } + + r_ospi_w_write_enable(); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8((uint8_t) pp_cmd); + if (addr_len == SPI_FLASH_ADDRESS_BYTES_4) + { + r_ospi_w_device_write32(addr); + } + else + { + r_ospi_w_device_write8((uint8_t) (addr >> 16)); + r_ospi_w_device_write8((uint8_t) (addr >> 8)); + r_ospi_w_device_write8((uint8_t) (addr >> 0)); + } + + for (uint32_t i = 0; i < bytes; ++i) + { + r_ospi_w_device_write8(buf[i]); + } + + r_ospi_w_device_cs_disable(); + + r_ospi_w_wait_while_busy(); + if (automode_backup) + { + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_AUTO); + } + } + else + { + return FSP_ERR_INVALID_DATA; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the SPI protocol. + * + * Implements @ref spi_flash_api_t::spiProtocolSet. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. Once the RA6W1/RA6W2 is running, it already be in automode by Booter. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_SpiProtocolSet (spi_flash_ctrl_t * const p_ctrl, + spi_flash_protocol_t spi_protocol) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(spi_protocol); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enters XIP (execute in place) mode. + * @note It need to enable the interrupt if it is disabled before. + * + * Implements @ref spi_flash_api_t::xipEnter. + * + * @retval FSP_SUCCESS XiP mode was entered successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_UNSUPPORTED XiP support is not enabled. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_XipEnter (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + + ospi_w_device_bus_mode bus_mode = OSPI_W_DEVICE_BUS_MODE_QUAD; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + switch (p_instance_ctrl->p_cmd_set->protocol) + { + case SPI_FLASH_PROTOCOL_1S_1S_1S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_SINGLE; + break; + } + + case SPI_FLASH_PROTOCOL_1S_4S_4S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_QUAD; + break; + } + + case SPI_FLASH_PROTOCOL_8D_8D_8D: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_OCTA; + break; + } + + default: + { + return FSP_ERR_INVALID_MODE; + break; + } + } + + ospi_w_set_bus_mode(bus_mode); + + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_AUTO); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Exits XIP (execute in place) mode. + * @note Once R_OSPI_W_XipExit called, it cannot excute the ISR code on the flash. + * So, it need to disable all interrupt right before this function. + * + * Implements @ref spi_flash_api_t::xipExit. + * + * @retval FSP_SUCCESS XiP mode was entered successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_UNSUPPORTED XiP support is not enabled. + * @retval FSP_ERR_INVALID_MODE Unsupport flash mode. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_XipExit (spi_flash_ctrl_t * const p_ctrl) +{ + uint8_t exit_continuous_seq_bytes = 4; + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + + ospi_w_extended_cfg_t * p_cfg_extend = (ospi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + /* Turn off auto mode to allow command entry mode */ + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_MANUAL); + + if (p_cfg_extend->p_read_instr_cfg->instr_mode == OSPI_W_DEVICE_INSTR_MODE_SEND_ONCE) + { + r_ospi_w_device_cs_enable(); + for (uint8_t i = 0; i < exit_continuous_seq_bytes; ++i) + { + r_ospi_w_device_write8(OSPI_EXIT_CONTINUOUS_MODE_CMD); + } + + r_ospi_w_device_cs_disable(); + } + + ospi_w_set_bus_mode(p_cfg_extend->p_read_instr_cfg->instr_bus_mode); + + return FSP_SUCCESS; +} + +BSP_PLACE_CODE_IN_RAM void r_ospi_w_memcpy (void * dest, const void * src, size_t count) +{ + char * tmp = dest; + const char * s = src; + + while (count--) + { + *tmp++ = *s++; + } +} + +/*******************************************************************************************************************//** + * Program a page of data to the flash. + * + * Implements @ref spi_flash_api_t::write. + * + * Example: + * @snippet r_ospi_w_example.c OSPI_W_Write + * * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_SIZE Insufficient space remaining in page or write length is not a multiple of CPU access size when not using the DMAC. + * @retval FSP_ERR_DEVICE_BUSY Another Write/Erase transaction is in progress. + * @retval FSP_ERR_WRITE_FAILED Write operation failed. + * @retval FSP_ERR_INVALID_ADDRESS Destination or source is not aligned to CPU access alignment when not using the DMAC. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Write (spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint32_t addr = (uint32_t) p_dest; + uint8_t buf[ON_STACK_BUFFER_SIZE]; + uint32_t size = byte_count; + uint32_t offset = 0; + uint32_t automode = 0; + + FSP_CRITICAL_SECTION_DEFINE; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + if (p_instance_ctrl->p_cfg->page_size_bytes > ON_STACK_BUFFER_SIZE) + { + return FSP_ERR_INVALID_SIZE; + } + + /* set address to physical address */ + addr &= 0xFFFFFF; + + FSP_CRITICAL_SECTION_ENTER; + if (r_ospi_w_device_get_access_mode() != OSPI_W_DEVICE_ACCESS_MODE_MANUAL) + { + // for convenience it call xip exit. + R_OSPI_W_XipExit(p_ctrl); + automode = 1; + } + + while (offset < size) + { + size_t chunk = sizeof(buf) > size - offset ? size - offset : sizeof(buf); + r_ospi_w_memcpy(buf, p_src + offset, chunk); + + size_t written = r_ospi_w_flash_write_page_safe(p_ctrl, addr + offset, buf, chunk); + offset += written; + } + + if (automode) + { + R_OSPI_W_XipEnter(p_ctrl); + } + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. + * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. + * If it was opened with auto-erase configuration, it could be called without XIP_Exit() function. + * Implements @ref spi_flash_api_t::erase. + * + * Example: + * @snippet r_ospi_w_example.c OSPI_W_Erase + * @snippet r_ospi_w_example.c OSPI_W_Erase_Auto + * + * @retval FSP_SUCCESS The command to erase the flash was executed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase + * size defined in spi_flash_cfg_t, or byte_count is set to 0. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + * @retval FSP_ERR_WRITE_FAILED Write operation failed. + * @retval FSP_ERR_INVALID_ARGUMENT The parameters are wrong. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Erase (spi_flash_ctrl_t * const p_ctrl, + uint8_t * const p_device_address, + uint32_t byte_count) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint8_t se_cmd = 0; + uint32_t addr = (uint32_t) p_device_address; + uint8_t addr_len = p_instance_ctrl->p_cfg->address_bytes; + ospi_w_device_addr_size mode; + uint32_t automode = 0; + + ospi_w_extended_cfg_t * p_cfg_extend = (ospi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + FSP_CRITICAL_SECTION_DEFINE; + + mode = (addr_len == SPI_FLASH_ADDRESS_BYTES_3) ? OSPI_W_DEVICE_ADDR_SIZE_24 : OSPI_W_DEVICE_ADDR_SIZE_32; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + if (p_instance_ctrl->p_cfg->erase_command_list_length == 0) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + /* set address to physical address */ + addr &= 0xFFFFFF; + + /* filter out unsupport erase byte_count */ + if (byte_count < p_instance_ctrl->p_cfg->p_erase_command_list[0].size) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + for (uint32_t index = 0; index < p_instance_ctrl->p_cfg->erase_command_list_length; index++) + { + /* If requested byte_count is supported by underlying flash, store the command. */ + if (byte_count == p_instance_ctrl->p_cfg->p_erase_command_list[index].size) + { + se_cmd = (uint8_t) p_instance_ctrl->p_cfg->p_erase_command_list[index].command; + break; + } + + if (byte_count > p_instance_ctrl->p_cfg->p_erase_command_list[0].size) + { + if ((byte_count % p_instance_ctrl->p_cfg->p_erase_command_list[0].size) == 0) + { + se_cmd = (uint8_t) p_instance_ctrl->p_cfg->p_erase_command_list[0].command; + } + } + } + +#if OSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U != se_cmd); +#endif + if (se_cmd == 0) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + /* Try auto mode erase first */ + if (r_ospi_w_device_get_access_mode() == OSPI_W_DEVICE_ACCESS_MODE_AUTO) + { + if ((p_cfg_extend != NULL) && (p_cfg_extend->p_erase_instr_cfg != NULL) && + (p_cfg_extend->p_erase_instr_cfg->enable == 1)) + { + uint32_t flash_offset; + flash_offset = addr; + + while (flash_offset < addr + byte_count) + { + r_ospi_w_device_erase_block(flash_offset); + while (r_ospi_w_device_get_erase_status() != OSPI_W_DEVICE_ERS_NO) + { + } + + flash_offset += OSPI_FLASH_SECTOR_LENGTH; + } + + return FSP_SUCCESS; + } + else /* it does not support automode erase */ + { + goto R_OSPI_W_ERASE_MANUAL; + } + } + else /* Already xip exit called. */ + { +R_OSPI_W_ERASE_MANUAL: + FSP_CRITICAL_SECTION_ENTER; + if (r_ospi_w_device_get_access_mode() != OSPI_W_DEVICE_ACCESS_MODE_MANUAL) + { + // for convenience it call xip exit. + R_OSPI_W_XipExit(p_ctrl); + automode = 1; + } + + if (se_cmd == p_instance_ctrl->p_cfg->p_erase_command_list[0].command) + { + if (byte_count > OSPI_FLASH_SECTOR_LENGTH) + { + uint32_t cnt = byte_count / OSPI_FLASH_SECTOR_LENGTH; + cnt = cnt + ((byte_count & 0xFFF) ? 1 : 0); + + for (uint32_t i = 0; i < cnt; i++) + { + ospi_w_flash_sector_erase(se_cmd, mode, addr + (i * OSPI_FLASH_SECTOR_LENGTH)); + } + } + else + { + ospi_w_flash_sector_erase(se_cmd, mode, addr); + } + } + else + { + ospi_w_flash_sector_erase(se_cmd, mode, addr); + } + + if (automode) + { + R_OSPI_W_XipEnter(p_ctrl); + } + + FSP_CRITICAL_SECTION_EXIT; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets the write or erase status of the flash. + * + * Implements @ref spi_flash_api_t::statusGet. + * + * @retval FSP_SUCCESS The write status is in p_status. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_StatusGet (spi_flash_ctrl_t * const p_ctrl, + spi_flash_status_t * const p_status) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint32_t automode = 0; + + if (!(p_instance_ctrl->open)) + { + return FSP_ERR_NOT_OPEN; + } + + if (r_ospi_w_device_get_access_mode() != OSPI_W_DEVICE_ACCESS_MODE_MANUAL) + { + // for convenience it call xip exit. + R_OSPI_W_XipExit(p_ctrl); + automode = 1; + } + + p_status->write_in_progress = r_ospi_flash_is_busy(p_ctrl); + + if (automode) + { + R_OSPI_W_XipEnter(p_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Selects the bank to access. Use ospi_w_bank_select_t as the bank value. + * + * Implements @ref spi_flash_api_t::bankSet. + * + * @retval FSP_ERR_UNSUPPORTED This function is unsupported. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_BankSet (spi_flash_ctrl_t * const p_ctrl, uint32_t bank) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(bank); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * AutoCalibrate the OSPI_W DS signal. + * + * Implements @ref spi_flash_api_t::autoCalibrate. + * + * @retval FSP_ERR_UNSUPPORTED Autocalibration support is not enabled. + **********************************************************************************************************************/ +BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_AutoCalibrate (spi_flash_ctrl_t * const p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_init (const ospi_w_device_config_t * cfg) +{ +#if ((dg_configCODE_LOCATION == NON_VOLATILE_IS_OCTA_FLASH) && (dg_configEXEC_MODE == MODE_IS_CACHED)) + FSP_ASSERT(REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) != 0 || + REG_GETF(CRG_TOP, SYS_CTRL_REG, CACHERAM_MUX) == 1) +#endif + + if (cfg) + { + r_ospi_w_device_set_div(cfg->clk_div); + r_ospi_w_device_clock_enable(); + r_ospi_w_device_set_clock_mode(cfg->clock_mode); + r_ospi_w_device_set_access_mode(cfg->access_mode); + r_ospi_w_device_set_bus_mode(cfg->bus_mode); + r_ospi_w_device_set_io2_direction(cfg->io2_dir); + r_ospi_w_device_set_io3_direction(cfg->io3_dir); + r_ospi_w_device_set_io4_7_direction(cfg->io4_7_dir); + + if (cfg->io2_dir == OSPI_W_DEVICE_IO_DIR_OUTPUT) + { + r_ospi_w_device_set_io2_value(cfg->io2_value); + } + + if (cfg->io3_dir == OSPI_W_DEVICE_IO_DIR_OUTPUT) + { + r_ospi_w_device_set_io3_value(cfg->io3_value); + } + + if (cfg->io4_7_dir == OSPI_W_DEVICE_IO_DIR_OUTPUT) + { + r_ospi_w_device_set_io4_7_value(cfg->io4_7_value); + } + + r_ospi_w_device_set_hready_mode(cfg->hready_mode); + r_ospi_w_device_set_read_sampling_edge(cfg->sampling_edge); + r_ospi_w_device_set_read_pipe(cfg->read_pipe); + r_ospi_w_device_set_read_pipe_clock_delay(cfg->read_pipe_delay); + r_ospi_w_device_set_address_size(cfg->address_size); + r_ospi_w_device_set_dummy_mode(cfg->dummy_mode); + + r_ospi_w_device_set_slew_rate(cfg->slew_rate); + r_ospi_w_device_set_drive_current(cfg->drive_current); + + r_ospi_w_device_set_dir_change_mode(cfg->manualmode_config.dir_change_mode); + r_ospi_w_device_set_mapped_addr_read_access_response(cfg->manualmode_config.mapped_addr_rd_acc_response); + + r_ospi_w_device_set_full_buffer_mode(cfg->automode_config.full_buffer_mode); + r_ospi_w_device_set_instruction_size(cfg->automode_config.instruct_size); + r_ospi_w_device_set_burst_len_limit(cfg->automode_config.burst_len_limit); + } +} + +static void r_ospi_w_device_flash_wr (uint8_t wr_data) +{ + *(volatile uint8_t *) &OQSPIF->OQSPIF_WRITEDATA_REG = wr_data; // QSPIC transmits 8 bits + while (REG_GETF(OQSPIF, OQSPIF_STATUS_REG, OSPIC_BUSY) == 1) + { + ; + } +} + +static uint8_t r_ospi_w_device_flash_rd (void) +{ + uint8_t rd_data; + __UNUSED volatile uint8_t dummy; + + dummy = *((volatile uint8_t *) &(OQSPIF->OQSPIF_READDATA_REG)); + + while (REG_GETF(OQSPIF, OQSPIF_STATUS_REG, OSPIC_BUSY) == 1) + { + ; + } + + rd_data = *((volatile uint8_t *) &(OQSPIF->OQSPIF_RECVDATA_REG)); + + return rd_data; +} + +void r_ospi_w_flash_rd_buf (uint8_t * rd_buf, size_t rd_buf_size) +{ + size_t i; + for (i = 0; i < rd_buf_size; i++) + { + rd_buf[i] = r_ospi_w_device_flash_rd(); + } +} + +void r_ospi_w_flash_cfg_read (uint8_t rd_cmd, uint32_t address) +{ + r_ospi_w_device_flash_wr((uint8_t) rd_cmd); /* Write Read Opcode */ + r_ospi_w_device_flash_wr((address >> 16) & 0xff); /* addr2 */ + r_ospi_w_device_flash_wr((address >> 8) & 0xff); /* addr1 */ + r_ospi_w_device_flash_wr(address & 0xff); /* addr0 */ +} + +void r_ospi_w_reset () +{ + volatile int i; + + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_AUTO_MD, 0); + + if (1) + { + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_SINGLE_Msk; + + // First cs toggle to wake up MX devices + r_ospi_w_device_cs_enable(); + for (i = 0; i < 800; i++) + { + __asm__ ("mov r0,r0"); + } + + r_ospi_w_device_cs_disable(); + for (i = 0; i < 800; i++) + { + __asm__ ("mov r0,r0"); + } + + // Wake up from the "Deep Power Down Mode" for other devices in single spi + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_EXIT_DPD_CMD); + r_ospi_w_device_cs_disable(); // Leave CSn asserted for the next steps ! + for (i = 0; i < 400; i++) // wait at least 30us to exit from the "Deep Power Down Mode" + { + __asm__ ("mov r0,r0"); + } + + // Wake up from the "Deep Power Down Mode" for other devices in QPI mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_QUAD_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_OEN, 0); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_OEN, 0); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_EXIT_DPD_CMD); + r_ospi_w_device_cs_disable(); // Leave CSn asserted for the next steps ! + for (i = 0; i < 400; i++) // wait at least 30us to exit from the "Deep Power Down Mode" + { + __asm__ ("mov r0,r0"); + } + + // Wake up from the "Deep Power Down Mode" for other devices in OCTA mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_OCTAL_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN, 0); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_EXIT_DPD_CMD); + r_ospi_w_device_cs_disable(); // Leave CSn asserted for the next steps ! + for (i = 0; i < 400; i++) // wait at least 30us to exit from the "Deep Power Down Mode" + { + __asm__ ("mov r0,r0"); + } + + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_EXIT_DPD_CMD); + r_ospi_w_device_flash_wr(OSPI_W_EXIT_DPD_CMD_INV); + r_ospi_w_device_cs_disable(); // Leave CSn asserted for the next steps ! + for (i = 0; i < 400; i++) // wait at least 30us to exit from the "Deep Power Down Mode" + { + __asm__ ("mov r0,r0"); + } + } + + // First make sure the device exits continuous read mode by sending 5 dummy bytes in Quad mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_QUAD_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_OEN, 0); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_OEN, 0); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN, 1); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_cs_disable(); + + // First make sure the device exits continuous read mode by sending 5 dummy bytes in OCTA mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_OCTAL_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN, 0); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_flash_wr(OSPI_W_DUMMY_CMD); + r_ospi_w_device_cs_disable(); + + // switch back to single mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_SINGLE_Msk; + OQSPIF->OQSPIF_CTRLMODE_REG = (OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CLK_MD_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RXD_NEG_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_OEN_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_OEN_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_OEN_Msk); + + // send reset in single SPI mode + r_ospi_w_device_cs_enable(); + + // Device reset in single mode + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); // MX25U, W25Q16DW Reset Enable (MX) + r_ospi_w_device_cs_toggle(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_CMD); // Reset Memory + r_ospi_w_device_cs_disable(); + for (i = 0; i < 400; i++) // MX Read, Write recover time > 20 us = 77us@10MHz, 39us@20MHz + { + __asm__ ("mov r0,r0"); + } + + // Device reset in QPI mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_QUAD_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO2_OEN, 0); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO3_OEN, 0); + + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); // MX25U, W25Q16DW Reset Enable (MX) + r_ospi_w_device_cs_toggle(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_CMD); // Reset Memory + r_ospi_w_device_cs_disable(); + for (i = 0; i < 400; i++) // MX Read, Write recover time > 20 us = 77us@10MHz, 39us@20MHz + { + __asm__ ("mov r0,r0"); + } + + // Device reset in OCTA mode double command mode + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_OCTAL_Msk; + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_IO_UH_OEN, 0); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); // MX25U, W25Q16DW Reset Enable (MX) + r_ospi_w_device_flash_wr(OSPI_W_RESET_CMD); // Reset Memory + r_ospi_w_device_cs_toggle(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_CMD); // Reset Memory + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); // MX25U, W25Q16DW Reset Enable (MX) + r_ospi_w_device_cs_disable(); + for (i = 0; i < 400; i++) // MX Read, Write recover time > 20 us = 77us@10MHz, 39us@20MHz + { + __asm__ ("mov r0,r0"); + } + + // Device reset in OCTA mode single command mode + r_ospi_w_device_cs_enable(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); + r_ospi_w_device_cs_toggle(); + r_ospi_w_device_flash_wr(OSPI_W_RESET_EN_CMD); + r_ospi_w_device_cs_disable(); + for (i = 0; i < 400; i++) // MX Read, Write recover time > 20 us = 77us@10MHz, 39us@20MHz + { + __asm__ ("mov r0,r0"); + } + + OQSPIF->OQSPIF_CTRLBUS_REG = OQSPIF_OQSPIF_CTRLBUS_REG_OSPIC_SET_SINGLE_Msk; + OQSPIF->OQSPIF_CTRLMODE_REG = (OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_CLK_MD_Msk | + + // OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RXD_NEG_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_RPIPE_EN_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_DAT_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO3_OEN_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO2_OEN_Msk | + OQSPIF_OQSPIF_CTRLMODE_REG_OSPIC_IO_UH_OEN_Msk); + +#ifdef FPGA_DEBUG + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_PCLK_MD, 7); + REG_SETF(OQSPIF, OQSPIF_CTRLMODE_REG, OSPIC_RPIPE_EN, 1); +#endif +} + +BSP_PLACE_CODE_IN_RAM void ospi_w_flash_sector_erase (uint8_t se_cmd, ospi_w_device_addr_size mode, uint32_t addr) +{ + r_ospi_w_wait_while_busy(); + + r_ospi_w_write_enable(); + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8((uint8_t) se_cmd); + if (r_ospi_w_device_get_instruction_size() == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8(~se_cmd); + } + + if (mode == OSPI_W_DEVICE_ADDR_SIZE_32) + { + r_ospi_w_device_write32(addr); + } + else + { + r_ospi_w_device_write8((uint8_t) (addr >> 16)); + r_ospi_w_device_write8((uint8_t) (addr >> 8)); + r_ospi_w_device_write8((uint8_t) (addr >> 0)); + } + + r_ospi_w_device_cs_disable(); + + r_ospi_w_wait_while_busy(); +} + +BSP_PLACE_CODE_IN_RAM static void r_ospi_w_write_enable (void) +{ + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8(OSPI_WRITE_ENABLE_CMD); + if (r_ospi_w_device_get_instruction_size() == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8((uint8_t) ~OSPI_WRITE_ENABLE_CMD); + } + + r_ospi_w_device_cs_disable(); +} + +BSP_PLACE_CODE_IN_RAM static void r_ospi_w_wait_while_busy (void) +{ + uint8_t dummy_cycle; + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8(SPI_READ_STATUS_REG_CMD); + if (r_ospi_w_device_get_instruction_size() == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8((uint8_t) ~SPI_READ_STATUS_REG_CMD); + } + + /* Send dummy bytes for octa flash */ + dummy_cycle = REG_GETF(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_NUM); + if (dummy_cycle > 0) + { + dummy_cycle += 1; + for (uint8_t dummy = 0; dummy < dummy_cycle; dummy++) + { + r_ospi_w_device_dummy8(); + } + } + + /* Busy bit in status register */ + while (r_ospi_w_device_read8() & 1) + { + ; + } + + r_ospi_w_device_cs_disable(); +} + +BSP_PLACE_CODE_IN_RAM void ospi_w_set_bus_mode (ospi_w_device_bus_mode bus_mode) +{ + switch (bus_mode) + { + case OSPI_W_DEVICE_BUS_MODE_SINGLE: + { + r_ospi_w_device_set_io2_direction(OSPI_W_DEVICE_IO_DIR_OUTPUT); + r_ospi_w_device_set_io2_value(OSPI_W_DEVICE_IO_VALUE_HIGH); + r_ospi_w_device_set_io3_direction(OSPI_W_DEVICE_IO_DIR_OUTPUT); + r_ospi_w_device_set_io3_value(OSPI_W_DEVICE_IO_VALUE_HIGH); + break; + } + + /* Octa mode needs one more settings from Quad mode. */ + case OSPI_W_DEVICE_BUS_MODE_OCTA: + { + r_ospi_w_device_set_io4_7_direction(OSPI_W_DEVICE_IO_DIR_AUTO_SEL); + [[fallthrough]]; /* Fall through */ + /* Dual and Quad mode uses same config. */ + } + + case OSPI_W_DEVICE_BUS_MODE_DUAL: + case OSPI_W_DEVICE_BUS_MODE_QUAD: + { + r_ospi_w_device_set_io2_direction(OSPI_W_DEVICE_IO_DIR_AUTO_SEL); + r_ospi_w_device_set_io3_direction(OSPI_W_DEVICE_IO_DIR_AUTO_SEL); + } + + default: + { + break; + } + } + + r_ospi_w_device_set_bus_mode(bus_mode); +} + +BSP_PLACE_CODE_IN_RAM static uint32_t r_ospi_w_flash_write_page_safe (spi_flash_ctrl_t * const p_ctrl, + uint32_t addr, + const uint8_t * buf, + uint32_t size) +{ + uint32_t written; + FSP_CRITICAL_SECTION_DEFINE; + + /* + * From now on OQSPI may not be available, turn off interrupts. + */ + FSP_CRITICAL_SECTION_ENTER; + + /* + * Write data into the page of the Flash. + */ + written = r_ospi_w_flash_write_page(p_ctrl, addr, buf, size); + + /* Wait for the Flash to process the command */ + while (r_ospi_flash_is_busy(p_ctrl)) + { + ; + } + + /* + * Let other code to be executed including OQSPI one. + */ + FSP_CRITICAL_SECTION_EXIT; + + return written; +} + +BSP_PLACE_CODE_IN_RAM static uint32_t r_ospi_w_flash_write_page (spi_flash_ctrl_t * const p_ctrl, + uint32_t addr, + const uint8_t * buf, + uint32_t size) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint8_t pp_cmd = p_instance_ctrl->p_cfg->page_program_command; + uint8_t addr_len = p_instance_ctrl->p_cfg->address_bytes; + const spi_flash_cfg_t * p_cfg = p_instance_ctrl->p_cfg; + ospi_w_extended_cfg_t * p_extended = (ospi_w_extended_cfg_t *) p_cfg->p_extend; + + ospi_w_device_bus_mode instr_bus_mode; + ospi_w_device_bus_mode bus_mode; + + uint32_t i = 0; + uint32_t odd = ((uint32_t) buf) & 3; + uint32_t size_aligned32; + uint32_t tmp; + + switch (p_instance_ctrl->p_cfg->spi_protocol) + { + case SPI_FLASH_PROTOCOL_1S_1S_1S: + { + instr_bus_mode = OSPI_W_DEVICE_BUS_MODE_SINGLE; + break; + } + + case SPI_FLASH_PROTOCOL_1S_4S_4S: + { + instr_bus_mode = OSPI_W_DEVICE_BUS_MODE_QUAD; + break; + } + + case SPI_FLASH_PROTOCOL_8D_8D_8D: + { + instr_bus_mode = OSPI_W_DEVICE_BUS_MODE_OCTA; + break; + } + + default: + { + return FSP_ERR_INVALID_MODE; + break; + } + } + + switch (p_instance_ctrl->p_cmd_set->protocol) + { + case SPI_FLASH_PROTOCOL_1S_1S_1S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_SINGLE; + break; + } + + case SPI_FLASH_PROTOCOL_1S_4S_4S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_QUAD; + break; + } + + case SPI_FLASH_PROTOCOL_8D_8D_8D: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_OCTA; + break; + } + + default: + { + return FSP_ERR_INVALID_MODE; + break; + } + } + + ospi_w_set_bus_mode(instr_bus_mode); + r_ospi_w_write_enable(); + + /* Make sure write will not cross page boundary */ + tmp = OSPI_FLASH_PAGE_SIZE - (addr & 0xFF); + if (size > tmp) + { + size = tmp; + } + + r_ospi_w_device_cs_enable(); + + r_ospi_w_device_write8(pp_cmd); + + if (p_extended->p_ospi_w_device_cfg->automode_config.instruct_size == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8(~pp_cmd); + } + + if ((pp_cmd == OSPI_W_QUAD_PAGEPR_CMD) || (pp_cmd == OSPI_W_QUAD_PAGEPR_CMD_2)) /* 4PP command */ + { + ospi_w_set_bus_mode(bus_mode); + } + + if (addr_len == SPI_FLASH_ADDRESS_BYTES_4) + { + r_ospi_w_device_write32(addr); + } + else + { + r_ospi_w_device_write8((uint8_t) ((addr >> 16) & 0xFF)); + r_ospi_w_device_write8((uint8_t) ((addr >> 8) & 0xFF)); + r_ospi_w_device_write8((uint8_t) (addr & 0xFF)); + } + + if (pp_cmd == OSPI_W_SINGLE_ADDR_QUAD_PAGEPR_CMD) /* 1-1-4 page program command */ + { + ospi_w_set_bus_mode(bus_mode); + } + + if (odd) + { + odd = 4 - odd; + for (i = 0; i < odd && i < size; ++i) + { + r_ospi_w_device_write8(buf[i]); + } + } + + size_aligned32 = ((size - i) & (uint32_t) ~0x3); + + if (size_aligned32) + { + fast_write_to_fifo32((uint32_t) (buf + i), (uint32_t) (buf + i + size_aligned32), + (uint32_t) &(OQSPIF->OQSPIF_WRITEDATA_REG)); + i += size_aligned32; + } + + for ( ; i < size; ++i) + { + r_ospi_w_device_write8(buf[i]); + } + + r_ospi_w_device_cs_disable(); + + ospi_w_set_bus_mode(instr_bus_mode); + + return i; +} + +BSP_PLACE_CODE_IN_RAM uint8_t r_ospi_flash_read_register (uint8_t cmd, uint8_t mask, ospi_w_device_bus_mode bus_mode) +{ + FSP_PARAMETER_NOT_USED(bus_mode); + volatile uint8_t reg_val; + uint8_t dummy_cycle; + + r_ospi_w_device_cs_enable(); + r_ospi_w_device_write8(cmd); + if (r_ospi_w_device_get_instruction_size() == OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES) + { + r_ospi_w_device_write8(~cmd); + } + + /* Send dummy bytes for octa flash */ + dummy_cycle = REG_GETF(OQSPIF, OQSPIF_STATUSCMD_REG, OSPIC_RSTAT_DMY_NUM); + if (dummy_cycle > 0) + { + dummy_cycle += 1; + for (uint8_t dummy = 0; dummy < dummy_cycle; dummy++) + { + r_ospi_w_device_write8(0); + } + } + + reg_val = r_ospi_w_device_read8(); + r_ospi_w_device_cs_disable(); + + return reg_val & mask; +} + +BSP_PLACE_CODE_IN_RAM bool r_ospi_flash_is_busy (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_w_instance_ctrl_t * p_instance_ctrl = (ospi_w_instance_ctrl_t *) p_ctrl; + uint8_t status_cmd = p_instance_ctrl->p_cfg->status_command; + uint8_t busy_mask = (0x01 << (p_instance_ctrl->p_cfg->write_status_bit)); + ospi_w_device_bus_mode bus_mode; + + switch (p_instance_ctrl->p_cfg->spi_protocol) + { + case SPI_FLASH_PROTOCOL_1S_1S_1S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_SINGLE; + break; + } + + case SPI_FLASH_PROTOCOL_1S_4S_4S: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_QUAD; + break; + } + + case SPI_FLASH_PROTOCOL_8D_8D_8D: + { + bus_mode = OSPI_W_DEVICE_BUS_MODE_OCTA; + break; + } + + default: + { + return FSP_ERR_INVALID_MODE; + break; + } + } + + uint8_t is_busy; + is_busy = r_ospi_flash_read_register(status_cmd, busy_mask, bus_mode); + + return is_busy ? true : false; +} + +BSP_PLACE_CODE_IN_RAM void r_ospi_w_device_erase_block (uint32_t addr) +{ + if (r_ospi_w_device_get_access_mode() != OSPI_W_DEVICE_ACCESS_MODE_AUTO) + { + r_ospi_w_device_set_access_mode(OSPI_W_DEVICE_ACCESS_MODE_AUTO); + } + + // Wait for previous erase to end + while (r_ospi_w_device_get_erase_status() != OSPI_W_DEVICE_ERS_NO) + { + } + + uint32_t block_sector = addr >> 12; + switch (r_ospi_w_device_get_address_size()) + { + case OSPI_W_DEVICE_ADDR_SIZE_24: + { + // FSP_ASSERT(addr <= 0x00FFFFFF); + // OQSPIF_ERASECTRL_REG bits 23-12 determine the block/sector address bits (23-12) + block_sector <<= 8; + break; + } + + case OSPI_W_DEVICE_ADDR_SIZE_32: + { + // FSP_ASSERT(addr < (MEMORY_OQSPIC_S_END - MEMORY_OQSPIC_S_BASE)); + // OQSPIF_ERASECTRL_REG bits 23-4 determine the block/sector address bits (31-12) + break; + } + + default: + { + // FSP_ASSERT(0); + break; + } + } + + r_ospi_w_device_set_erase_address(block_sector); + r_ospi_w_device_trigger_erase(); +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_qspi_w/r_qspi_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_qspi_w/r_qspi_w.c new file mode 100644 index 000000000000..2dd5e45fb159 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_qspi_w/r_qspi_w.c @@ -0,0 +1,2138 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "r_qspi_w.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define QSPI_W_PRV_OPEN (0x51535049U) // ASCII characters "QSPI" +#define QSPI_W_PRV_TIMEOUT_US (500000U) + +#if defined(BSP_MCU_GROUP_RA6W1) + #define QSPI_W_DEVICE_END_ADDRESS (0x28000000U) + #define QSPI_W_MEMORY_QSPID_SIZE (QSPI_W_DEVICE_END_ADDRESS - QSPI_W_DEVICE_START_ADDRESS) + #define QSPI_W_DCACHE_CACHEABLE_RESOLUTION (0x400U) + #define QSPI_W_DCACHE_CACHEABLE_LEN_MAX (QSPI_W_MEMORY_QSPID_SIZE / QSPI_W_DCACHE_CACHEABLE_RESOLUTION) + +/* Read pipe delay based on voltage level of power rail. */ + #define QSPI_W_READ_PIPE_DELAY (QSPI_W_READ_PIPE_DELAY_3) +#else + +/* Read pipe delay based on voltage level of power rail. */ + #define QSPI_W_READ_PIPE_DELAY (QSPI_W_READ_PIPE_DELAY_2) /* 0V9 */ +#endif + +/* Sector size. */ +#define QSPI_W_FLASH_SECTOR_SIZE (0x1000U) +#define QSPI_W_MAN_DIRCHG_MD_DEFAULT (1U) // The bus direction goes to input only after a dummy access (Manual Mode). + +/* Number of dummy bytes. */ +#define QSPI_W_DUMMY_BYTES_FORCED (3U) + +#define QSPI_W_FLASH_PAGE_SIZE (0XFFU) + +/* QSPI_W base register access macro. */ +#define QSPI_REG(channel) ((QSPIC_Type *) ((uint32_t) QSPIC - ((uint32_t) QSPIC) * (channel))) + +#if defined(QSPIC_QSPIC_STATUSCMDA_REG_QSPIC_BUSY_VAL_Msk) + #define QSPI_W_STATUSCMDA_REG QSPIC_STATUSCMDA_REG + #define QSPI_W_STATUSCMDA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((QSPIC_QSPIC_STATUSCMDA_REG_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (QSPIC_QSPIC_STATUSCMDA_REG_ ## field ## _Pos)) & \ + (QSPIC_QSPIC_STATUSCMDA_REG_ ## field ## _Msk))) +#elif defined(QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk) + #define QSPI_W_STATUSCMDA_REG QSPIC_STATUSCMD_REG + #define QSPI_W_STATUSCMDA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((QSPIC_QSPIC_STATUSCMD_REG_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (QSPIC_QSPIC_STATUSCMD_REG_ ## field ## _Pos)) & \ + (QSPIC_QSPIC_STATUSCMD_REG_ ## field ## _Msk))) +#endif + +#if defined(QSPIC_QSPIC_AWRITECMDA_REG_QSPIC_WR_INST_Msk) + #define QSPI_W_AWRITECMDA_REG QSPIC_AWRITECMDA_REG + #define QSPI_W_AWRITECMDA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((QSPIC_QSPIC_AWRITECMDA_REG_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (QSPIC_QSPIC_AWRITECMDA_REG_ ## field ## _Pos)) & \ + (QSPIC_QSPIC_AWRITECMDA_REG_ ## field ## _Msk))) +#elif defined(QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk) + #define QSPI_W_AWRITECMDA_REG QSPIC_AWRITECMD_REG + #define QSPI_W_AWRITECMDA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((QSPIC_QSPIC_AWRITECMD_REG_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (QSPIC_QSPIC_AWRITECMD_REG_ ## field ## _Pos)) & \ + (QSPIC_QSPIC_AWRITECMD_REG_ ## field ## _Msk))) +#endif + +#if defined(CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk) + #define QSPI_W_CLK_AMBA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((CRG_TOP_CLK_AMBA_REG_QSPI2_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (CRG_TOP_CLK_AMBA_REG_QSPI2_ ## field ## _Pos)) & \ + (CRG_TOP_CLK_AMBA_REG_QSPI2_ ## field ## _Msk))) +#elif defined(CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk) + #define QSPI_W_CLK_AMBA_REG_FIELD_SET(field, var, val) \ + var = (((unsigned) var & ~((CRG_TOP_CLK_AMBA_REG_QSPI_ ## field ## _Msk))) | \ + ((((unsigned) (val)) << (CRG_TOP_CLK_AMBA_REG_QSPI_ ## field ## _Pos)) & \ + (CRG_TOP_CLK_AMBA_REG_QSPI_ ## field ## _Msk))) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Index of bus mode. */ +typedef enum e_qspi_w_idx_bus_mode +{ + QSPI_W_IDX_INSTR_BUS_MODE, // Index of instruction bus mode. + QSPI_W_IDX_NON_INSTR_BUS_MODE, // Index of non-instruction bus mode (address/extra/dummy/data bus modes). +} qspi_w_idx_bus_mode_t; + +/* + * Union used in order to allow different size access when reading/writing to + * QSPIC_READDATA_REG, QSPIC_WRITEDATA_REG, QSPIC_DUMMYDATA_REG. + */ +typedef union u_qspi_w_data +{ + __IO uint32_t data32; + __IO uint16_t data16; + __IO uint8_t data8; +} qspi_w_data_t; + +/*********************************************************************************************************************** + * Private global variables and functions. + **********************************************************************************************************************/ + +__STATIC_FORCEINLINE void r_qspi_w_set_io(uint8_t channel, qspi_w_bus_mode_t bus_mode); +__STATIC_FORCEINLINE void r_qspi_w_write32(uint8_t channel, uint32_t data); +__STATIC_FORCEINLINE void r_qspi_w_write8(uint8_t channel, uint8_t data); +__STATIC_FORCEINLINE void r_qspi_w_read_status_instr_init(uint8_t channel, + const qspi_w_read_status_instr_cfg_t * p_read_status_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_write_enable_instr_init(uint8_t channel, + const qspi_w_write_enable_instr_cfg_t * p_wrt_enble_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_erase_instr_init(uint8_t channel, + const qspi_w_erase_instr_cfg_t * p_erase_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_suspend_resume_instr_init(uint8_t channel, + const qspi_w_suspend_resume_instr_cfg_t * p_sus_res_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_write_instr_init(uint8_t channel, + const qspi_w_write_instr_cfg_t * p_wrt_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_break_instr_init(uint8_t channel, + const qspi_w_break_instr_cfg_t * p_break_instr_cfg); +__STATIC_FORCEINLINE void r_qspi_w_memblen_init(uint8_t channel, const qspi_w_memblen_cfg_t * p_memblen_cfg); +__STATIC_FORCEINLINE qspi_w_ers_t r_qspi_w_get_erase_status(uint8_t channel); +__STATIC_FORCEINLINE uint8_t r_qspi_w_read8(uint8_t channel); +__STATIC_FORCEINLINE void r_qspi_w_fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest); +__STATIC_FORCEINLINE void r_qspi_w_enter_manual_access_mode(qspi_w_instance_ctrl_t * p_instance_ctrl); + +PLACE_IN_RAM_SECTION static void r_qspi_w_direct_write_sub(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +PLACE_IN_RAM_SECTION static void r_qspi_w_direct_read_sub(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t * const p_dest, + uint32_t const bytes); +PLACE_IN_RAM_SECTION static fsp_err_t r_qspi_w_xip(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t code, + bool enter_mode); +PLACE_IN_RAM_SECTION static void r_qspi_w_manual_access_bus_mode_set(uint8_t channel, qspi_w_bus_mode_t bus_mode); +PLACE_IN_RAM_SECTION static void r_qspi_w_enter_auto_access_mode(qspi_w_extended_cfg_t * p_inst_extend); +PLACE_IN_RAM_SECTION static uint32_t r_qspi_w_flash_write_page(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint32_t addr, + const uint8_t * p_buf, + uint32_t size); +PLACE_IN_RAM_SECTION static uint32_t r_qspi_w_get_chip_address(uint8_t * const p_addr); +PLACE_IN_RAM_SECTION static void r_qspi_w_erase_block(uint8_t channel, uint32_t addr); +PLACE_IN_RAM_SECTION static fsp_err_t r_qspi_w_erase_flash_sector(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint32_t addr); +PLACE_IN_RAM_SECTION static uint16_t r_qspi_w_get_erase_opcode(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint32_t byte_count); +PLACE_IN_RAM_SECTION static void r_qspi_w_erase_chip(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t erase_command); + +PLACE_IN_RAM_SECTION static void r_qspi_w_instructions_init(qspi_w_instance_ctrl_t * p_instance_ctrl); +PLACE_IN_RAM_SECTION static void r_qspi_w_controller_init(qspi_w_instance_ctrl_t * p_instance_ctrl); +PLACE_IN_RAM_SECTION static void r_qspi_w_get_bus_mode(spi_flash_protocol_t spi_protocol, + qspi_w_bus_mode_t * p_bus_mode); + +PLACE_IN_RAM_SECTION static bool r_qspi_w_flash_is_writable(qspi_w_instance_ctrl_t * p_instance_ctrl); +PLACE_IN_RAM_SECTION static void r_qspi_w_flash_cmd(uint8_t channel, const uint8_t opcode); +PLACE_IN_RAM_SECTION static void r_qspi_w_flash_write_enable(qspi_w_instance_ctrl_t * p_instance_ctrl); +PLACE_IN_RAM_SECTION static bool r_qspi_w_flash_is_busy(qspi_w_instance_ctrl_t * p_instance_ctrl); + +PLACE_IN_RAM_SECTION static void r_qspi_w_set_extra_byte(uint8_t channel, + uint8_t extra_byte, + qspi_w_read_instr_cfg_t const * p_qspi_cfg); +PLACE_IN_RAM_SECTION static void r_qspi_w_read_instr_init(uint8_t channel, + const qspi_w_read_instr_cfg_t * p_read_instr_cfg); +PLACE_IN_RAM_SECTION static void r_qspi_w_transact(qspi_w_extended_cfg_t * p_inst_extend, + const uint8_t * p_wbuf, + uint32_t wlen, + uint8_t * p_rbuf, + uint32_t rlen); +PLACE_IN_RAM_SECTION static uint8_t r_qspi_w_read_status_register(qspi_w_instance_ctrl_t * p_instance_ctrl); + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE +PLACE_IN_RAM_SECTION static fsp_err_t r_qspi_w_param_checking_dcom(qspi_w_instance_ctrl_t * p_instance_ctrl); +PLACE_IN_RAM_SECTION static fsp_err_t r_qspi_w_program_param_check(qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); + +#endif +#if defined(BSP_MCU_GROUP_RA6W1) +static void r_qspi_w_dcache_enable(void); +static void r_qspi_w_dcache_set_cacheable_base(void); +static fsp_err_t r_qspi_w_dcache_disable(void); +static fsp_err_t r_qspi_w_dcache_init(void); +static fsp_err_t r_qspi_w_dcache_set_cacheable_len(uint32_t len); + +#endif + +static qspi_w_bus_mode_t g_manual_access_bus_mode = QSPI_W_BUS_MODE_SINGLE; + +/*******************************************************************************************************************//** + * @addtogroup QSPI_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +const spi_flash_api_t g_spi_flash_on_qspi_w = +{ + .open = R_QSPI_W_Open, + .directWrite = R_QSPI_W_DirectWrite, + .directRead = R_QSPI_W_DirectRead, + .directTransfer = R_QSPI_W_DirectTransfer, + .spiProtocolSet = R_QSPI_W_SpiProtocolSet, + .write = R_QSPI_W_Write, + .erase = R_QSPI_W_Erase, + .statusGet = R_QSPI_W_StatusGet, + .xipEnter = R_QSPI_W_XipEnter, + .xipExit = R_QSPI_W_XipExit, + .bankSet = R_QSPI_W_BankSet, + .autoCalibrate = R_QSPI_W_AutoCalibrate, + .close = R_QSPI_W_Close, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Open the QSPI_W driver module. After the driver is open, the QSPI_W can be accessed like internal flash memory + * starting at address 0x16000000/0x36000000. + * + * QSPI_W is configured to operate in AUTO MODE after the driver is open. + * + * QSPI_W memory is expected to be in single SPI mode before calling open. + * + * Implements @ref spi_flash_api_t::open. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] p_cfg Configuration structure which contains all the user provided configurations. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION The pointer parameters are NULL. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_instance_ctrl. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + * @retval FSP_ERR_INVALID_HW_CONDITION Invalid power rail condition. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_Open (spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + qspi_w_extended_cfg_t * p_cfg_extend; + + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + p_cfg_extend = (qspi_w_extended_cfg_t *) p_cfg->p_extend; + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg_extend); + FSP_ERROR_RETURN(BSP_FEATURE_QSPI_MAX_CHANNEL > p_cfg_extend->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #if defined(BSP_MCU_GROUP_RA6B1) || defined(BSP_MCU_GROUP_RA6U1) + FSP_ERROR_RETURN(1 == PMU_ANA->POWER_CTRL_REG_b.V18EXT_ENABLE, FSP_ERR_INVALID_HW_CONDITION); + #endif +#endif + + p_instance_ctrl->p_cfg = p_cfg; + +#if defined(BSP_MCU_GROUP_RA6W1) + #if !QSPI_W_CFG_PARAM_CHECKING_ENABLE + qspi_w_extended_cfg_t * p_cfg_extend = (qspi_w_extended_cfg_t *) p_cfg->p_extend; + #endif + + /* Data cache setting. */ + if (QSPI_W_DCACHE_ENABLE == p_cfg_extend->qspi_dcache) + { + r_qspi_w_dcache_enable(); + FSP_ERROR_RETURN(FSP_SUCCESS == r_qspi_w_dcache_init(), FSP_ERR_TIMEOUT); + FSP_ERROR_RETURN(FSP_SUCCESS == + r_qspi_w_dcache_set_cacheable_len(QSPI_W_DCACHE_CACHEABLE_LEN_MAX), + FSP_ERR_TIMEOUT); + r_qspi_w_dcache_set_cacheable_base(); + } +#endif + r_qspi_w_controller_init(p_instance_ctrl); + + r_qspi_w_instructions_init(p_instance_ctrl); + + /* The memory size is read from the device if needed. */ + p_instance_ctrl->total_size_bytes = 0U; + + p_instance_ctrl->open = QSPI_W_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes raw data directly to the QSPI_W. + * + * @note Use R_QSPI_W_SpiProtocolSet before a direct write to set the bus mode in the appropriate manual mode. + * + * Implements @ref spi_flash_api_t::directWrite. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] p_src Pointer to the data to write. + * @param[in] bytes Number of bytes to write. + * @param[in] read_after_write Whether or not to close the SPI bus cycle. + * + * @retval FSP_SUCCESS Directly write raw data successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_DirectWrite (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_qspi_w_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(bytes > 0); +#endif + + /* Write data to QSPI_W. */ + r_qspi_w_direct_write_sub(p_instance_ctrl, p_src, bytes, read_after_write); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads raw data directly from the QSPI_W. This API can only be called after R_QSPI_W_DirectWrite with read_after_write + * set to true. + * + * Implements @ref spi_flash_api_t::directRead. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[out] p_dest Pointer to the destination buffer. + * @param[in] bytes Number of bytes to read. + * + * @retval FSP_SUCCESS Directly read raw data successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function must be called after R_QSPI_W_DirectWrite with read_after_write set + * to true. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_DirectRead (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(bytes > 0); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* This API can only be called after R_QSPI_W_DirectWrite with the read_after_write parameter set to true. The QSPI_W + * peripheral must already be in direct communications mode. */ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + FSP_ERROR_RETURN(0U == QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD, FSP_ERR_INVALID_MODE); +#endif + + /* Read data from QSPI_W. */ + r_qspi_w_direct_read_sub(p_instance_ctrl, p_dest, bytes); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read/Write raw data directly with the OctaFlash/OctaRAM device. Unsupported by QSPI_W. + * + * Implements @ref spi_flash_api_t::directTransfer. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] p_transfer Pointer to @ref spi_flash_direct_transfer_t. + * @param[in] direction Direct read or write direction. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI_W. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_DirectTransfer (spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_transfer); + FSP_PARAMETER_NOT_USED(direction); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enters XiP (execute in place) mode. + * + * @note XiP mode refers to random access read mode, also known as Fast Read Quad I/O (EBh), + * 4READ: 4 x I/O READ (EBh), etc. + * + * Implements @ref spi_flash_api_t::xipEnter. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * + * @retval FSP_SUCCESS The flash enters XiP mode successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_XipEnter (spi_flash_ctrl_t * p_ctrl) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + fsp_err_t err = + r_qspi_w_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_enter_command, true); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Exits XiP (execute in place) mode. + * + * Implements @ref spi_flash_api_t::xipExit. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * + * @retval FSP_SUCCESS The flash exits XiP mode successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_XipExit (spi_flash_ctrl_t * p_ctrl) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + fsp_err_t err = + r_qspi_w_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_exit_command, false); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Program a page of data to the flash. + * + * Implements @ref spi_flash_api_t::write. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] p_src Pointer to the source data. + * @param[out] p_dest Pointer to the destination. + * @param[in] byte_count Number of bytes to write. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_Write (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_qspi_w_program_param_check(p_instance_ctrl, p_src, p_dest, byte_count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + qspi_w_bus_mode_t busy_bus_mode = + p_inst_extend->p_qspi_flash_cfg->p_read_status_instr_cfg->opcode_bus_mode; + + /* Disable the interrupts as long as the QSPIC remains in manual access mode. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Wait until the flash memory is ready. */ + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + r_qspi_w_manual_access_bus_mode_set(channel, busy_bus_mode); + while (r_qspi_w_flash_is_busy(p_instance_ctrl)) + { + /* No messages to process */ + ; + } + + r_qspi_w_flash_write_page(p_instance_ctrl, r_qspi_w_get_chip_address(p_dest), p_src, byte_count); + + r_qspi_w_manual_access_bus_mode_set(channel, busy_bus_mode); + + r_qspi_w_enter_auto_access_mode(p_inst_extend); + + /* Re-enable the interrupts since the QSPIC switched back to auto access mode. */ + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. + * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. + * + * Implements @ref spi_flash_api_t::erase. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] p_device_address Pointer to the device address. + * @param[in] byte_count Number of bytes to be erased. + * + * @retval FSP_SUCCESS The command to erase the flash was executed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase + * size defined in spi_flash_cfg_t, or device is in XiP mode. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + * @retval FSP_ERR_TIMEOUT The erase operation timed out. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_qspi_w_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_device_address); +#endif + + uint8_t erase_command = (uint8_t) r_qspi_w_get_erase_opcode(p_instance_ctrl, byte_count); + + if (SPI_FLASH_ERASE_SIZE_CHIP_ERASE == byte_count) + { + /* MANUAL MODE chip erase. */ + r_qspi_w_erase_chip(p_instance_ctrl, erase_command); + } + else + { + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + /* AUTO MODE block erase. */ + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U != erase_command); +#endif + QSPI_REG(channel)->QSPIC_ERASECMDA_REG_b.QSPIC_ERS_INST = erase_command; + + return r_qspi_w_erase_flash_sector(p_instance_ctrl, r_qspi_w_get_chip_address(p_device_address)); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets the write or erase status of the flash. + * + * Implements @ref spi_flash_api_t::statusGet. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[out] p_status Pointer to the status @ref spi_flash_status_t. + * + * @retval FSP_SUCCESS The write status is in p_status. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_StatusGet (spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Do not enter direct communication mode from XiP mode. */ + FSP_ERROR_RETURN(false == p_instance_ctrl->xip_mode_is_enabled, FSP_ERR_INVALID_MODE); +#endif + + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + /* Read device status. */ + if (QSPI_W_ERS_NO != r_qspi_w_get_erase_status(channel)) + { + p_status->write_in_progress = true; + } + else + { + p_status->write_in_progress = !(r_qspi_w_flash_is_writable(p_instance_ctrl)); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Selects the bank to access. + * + * Implements @ref spi_flash_api_t::bankSet. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] bank The bank which need to access. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI_W. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_BankSet (spi_flash_ctrl_t * p_ctrl, uint32_t bank) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(bank); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sets the SPI protocol. + * + * @note Updates QSPI_W manual mode bus mode registers. + * + * Implements @ref spi_flash_api_t::spiProtocolSet. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * @param[in] spi_protocol The type of SPI Flash protocol. + * + * @retval FSP_SUCCESS SPI protocol registers updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid SPI protocol requested. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(spi_protocol != SPI_FLASH_PROTOCOL_SOPI && + spi_protocol != SPI_FLASH_PROTOCOL_DOPI && + spi_protocol != SPI_FLASH_PROTOCOL_8D_8D_8D, + FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Update the SPI protocol. */ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + qspi_w_bus_mode_t bus_mode[2] = {QSPI_W_BUS_MODE_SINGLE}; + + r_qspi_w_get_bus_mode(spi_protocol, bus_mode); + + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + + r_qspi_w_manual_access_bus_mode_set(channel, bus_mode[QSPI_W_IDX_INSTR_BUS_MODE]); + + r_qspi_w_enter_auto_access_mode(p_inst_extend); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Auto-calibrate the OctaRAM device using the preamble pattern. + * Implements @ref spi_flash_api_t::autoCalibrate. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI_W. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_AutoCalibrate (spi_flash_ctrl_t * p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Close the QSPI_W driver module. + * + * Implements @ref spi_flash_api_t::close. + * + * @param[in] p_ctrl Pointer to the instance control structure. + * + * @retval FSP_SUCCESS Close module successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_W_Close (spi_flash_ctrl_t * p_ctrl) +{ + qspi_w_instance_ctrl_t * p_instance_ctrl = (qspi_w_instance_ctrl_t *) p_ctrl; + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->open = 0U; + + /* Disable clock to the QSPI_W block. */ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + +#if defined(BSP_MCU_GROUP_RA6W1) + + /* Data cache disable setting */ + if (QSPI_W_DCACHE_ENABLE == p_inst_extend->qspi_dcache) + { + FSP_ERROR_RETURN(FSP_SUCCESS == r_qspi_w_dcache_set_cacheable_len(0), FSP_ERR_TIMEOUT); + FSP_ERROR_RETURN(FSP_SUCCESS == r_qspi_w_dcache_disable(), FSP_ERR_TIMEOUT); + } +#endif + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (0 == channel) + { +#if defined(CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk) + CRG_TOP->CLK_AMBA_REG_b.QSPI2_ENABLE = 0; +#else + CRG_TOP->CLK_AMBA_REG_b.QSPI_ENABLE = 0; +#endif + } + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup QSPI_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Set the direction and the level of QSPIC IOs based on the Bus Mode. + * + * @param[in] channel QSPI controller id. + * @param[in] bus_mode The QSPIC Bus Mode. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_set_io (uint8_t channel, qspi_w_bus_mode_t bus_mode) +{ + uint32_t ctrlmode_reg = QSPI_REG(channel)->QSPIC_CTRLMODE_REG; + + switch (bus_mode) + { + case QSPI_W_BUS_MODE_QUAD: + { + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, ctrlmode_reg, 0); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, ctrlmode_reg, 0); + break; + } + + default: + { + /* QSPI_BUS_MODE_SINGLE or QSPI_BUS_MODE_DUAL. */ + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, ctrlmode_reg, 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, ctrlmode_reg, 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, ctrlmode_reg, 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, ctrlmode_reg, 1); + break; + } + } + + QSPI_REG(channel)->QSPIC_CTRLMODE_REG = ctrlmode_reg; +} + +/*******************************************************************************************************************//** + * Generate 32 bits data transfer from the QSPIC to the external device (manual mode). + * + * @param[in] channel QSPI controller id. + * @param[in] data 32 bits value to be written on the device. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_write32 (uint8_t channel, uint32_t data) +{ + volatile qspi_w_data_t * p_tmp = (volatile qspi_w_data_t *) &(QSPI_REG(channel)->QSPIC_WRITEDATA_REG); + + p_tmp->data32 = FSP_SWAP32(data); +} + +/*******************************************************************************************************************//** + * Generate 8 bits data transfer from the QSPIC to the external device (manual mode). + * + * @param[in] channel QSPI controller id. + * @param[in] data 8 bits value to be written on the device. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_write8 (uint8_t channel, uint8_t data) +{ + volatile qspi_w_data_t * p_tmp = (volatile qspi_w_data_t *) &(QSPI_REG(channel)->QSPIC_WRITEDATA_REG); + + p_tmp->data8 = data; +} + +/*******************************************************************************************************************//** + * Initialize the read status register instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_read_status_instr_cfg Pointer to configuration structure of the read status register + * instruction. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_read_status_instr_init (uint8_t channel, + const qspi_w_read_status_instr_cfg_t * p_read_status_instr_cfg) +{ + if (p_read_status_instr_cfg) + { + uint32_t statuscmd_reg = QSPI_REG(channel)->QSPI_W_STATUSCMDA_REG; + + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_BUSY_VAL, statuscmd_reg, p_read_status_instr_cfg->busy_level); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_STSDLY_SEL, statuscmd_reg, p_read_status_instr_cfg->stsdly_sel); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_RESSTS_DLY, statuscmd_reg, p_read_status_instr_cfg->delay_cycles); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_BUSY_POS, statuscmd_reg, p_read_status_instr_cfg->busy_pos); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_RSTAT_RX_MD, statuscmd_reg, p_read_status_instr_cfg->receive_bus_mode); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_RSTAT_TX_MD, statuscmd_reg, p_read_status_instr_cfg->opcode_bus_mode); + QSPI_W_STATUSCMDA_REG_FIELD_SET(QSPIC_RSTAT_INST, statuscmd_reg, p_read_status_instr_cfg->opcode); + + QSPI_REG(channel)->QSPI_W_STATUSCMDA_REG = statuscmd_reg; + +#if defined(QSPIC_QSPIC_STATUSCMDB_REG_QSPIC_RSTAT_REQ_Msk) + statuscmd_reg = QSPI_REG(channel)->QSPIC_STATUSCMDB_REG; + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_REQ, + statuscmd_reg, + p_read_status_instr_cfg->rstat_req); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_SPLIT_EN, + statuscmd_reg, + p_read_status_instr_cfg->rstat_split_en); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_RDB_EN, + statuscmd_reg, + p_read_status_instr_cfg->rstat_rdb_en); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_DMY_EN, + statuscmd_reg, + p_read_status_instr_cfg->rstat_dmy_en); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_DMY_ZERO, + statuscmd_reg, + p_read_status_instr_cfg->dummy_value); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_DMY_TX_MD, + statuscmd_reg, + p_read_status_instr_cfg->dummy_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_STATUSCMDB_REG, + QSPIC_RSTAT_DMY_NUM, + statuscmd_reg, + p_read_status_instr_cfg->rstat_dmy_num); + + QSPI_REG(channel)->QSPIC_STATUSCMDB_REG = statuscmd_reg; +#endif + } +} + +/*******************************************************************************************************************//** + * Initialize the write enable instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_wrt_enble_instr_cfg Pointer to configuration structure of the write enable instruction. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_write_enable_instr_init (uint8_t channel, + const qspi_w_write_enable_instr_cfg_t * p_wrt_enble_instr_cfg) +{ + if (p_wrt_enble_instr_cfg) + { + QSPI_REG(channel)->QSPIC_ERASECMDA_REG_b.QSPIC_WEN_INST = p_wrt_enble_instr_cfg->opcode; + QSPI_REG(channel)->QSPIC_ERASECMDB_REG_b.QSPIC_WEN_TX_MD = p_wrt_enble_instr_cfg->opcode_bus_mode; + } +} + +/*******************************************************************************************************************//** + * Initialize the erase instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_erase_instr_cfg Pointer to configuration structure of the erase instruction. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_erase_instr_init (uint8_t channel, + const qspi_w_erase_instr_cfg_t * p_erase_instr_cfg) +{ + if (p_erase_instr_cfg) + { + QSPI_REG(channel)->QSPIC_ERASECMDA_REG_b.QSPIC_ERS_INST = p_erase_instr_cfg->opcode; + + uint32_t erasecmdb_reg = QSPI_REG(channel)->QSPIC_ERASECMDB_REG; + + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_ERS_TX_MD, + erasecmdb_reg, + p_erase_instr_cfg->opcode_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_EAD_TX_MD, + erasecmdb_reg, + p_erase_instr_cfg->addr_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_ERSRES_HLD, + erasecmdb_reg, + p_erase_instr_cfg->hclk_cycles); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_ERS_CS_HI, + erasecmdb_reg, + p_erase_instr_cfg->cs_idle_delay_cycles); + + QSPI_REG(channel)->QSPIC_ERASECMDB_REG = erasecmdb_reg; + } +} + +/*******************************************************************************************************************//** + * Initialize the program and erase suspend/resume instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_sus_res_instr_cfg Pointer to configuration structure of the program and erase suspend/resume + * instruction. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_suspend_resume_instr_init (uint8_t channel, + const qspi_w_suspend_resume_instr_cfg_t * p_sus_res_instr_cfg) +{ + if (p_sus_res_instr_cfg) + { + uint32_t erasecmda_reg = QSPI_REG(channel)->QSPIC_ERASECMDA_REG; + uint32_t erasecmdb_reg = QSPI_REG(channel)->QSPIC_ERASECMDB_REG; + + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDA_REG, + QSPIC_SUS_INST, + erasecmda_reg, + p_sus_res_instr_cfg->suspend_opcode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDA_REG, + QSPIC_RES_INST, + erasecmda_reg, + p_sus_res_instr_cfg->resume_opcode); + + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_SUS_TX_MD, + erasecmdb_reg, + p_sus_res_instr_cfg->suspend_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_RES_TX_MD, + erasecmdb_reg, + p_sus_res_instr_cfg->resume_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_ERASECMDB_REG, + QSPIC_RESSUS_DLY, + erasecmdb_reg, + p_sus_res_instr_cfg->res_sus_latency_clk_cycles); + + QSPI_REG(channel)->QSPIC_ERASECMDA_REG = erasecmda_reg; + QSPI_REG(channel)->QSPIC_ERASECMDB_REG = erasecmdb_reg; + +#if defined(QSPIC_QSPIC_ERASECMDC_REG_QSPIC_SUSSTS_DLY_Msk) + QSPIC->QSPIC_ERASECMDC_REG_b.QSPIC_SUSSTS_DLY = p_sus_res_instr_cfg->sussts_dly; +#endif + } +} + +/*******************************************************************************************************************//** + * Initialize the write instruction of the QSPIC in auto mode when device is PSRAM. + * + * @param[in] channel QSPI controller id. + * @param[in] p_wrt_instr_cfg Pointer to configuration structure of the write instruction (PSRAM, auto mode). + * + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_write_instr_init (uint8_t channel, const qspi_w_write_instr_cfg_t * p_wrt_instr_cfg) +{ +#if defined(QSPIC_QSPIC_AWRITECMDB_REG_QSPIC_WR_CS_HIGH_MIN_Msk) + uint32_t reg_val = QSPI_REG(channel)->QSPIC_AWRITECMDB_REG; + + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_AWRITECMDB_REG, QSPIC_SEND_WEN_REQ, reg_val, p_wrt_instr_cfg->send_wen_req); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_AWRITECMDB_REG, + QSPIC_WR_CS_HIGH_MIN, + reg_val, + p_wrt_instr_cfg->cs_hi_min_clk_cycles); + + QSPI_REG(channel)->QSPIC_AWRITECMDB_REG = reg_val; + + reg_val = QSPI_REG(channel)->QSPI_W_AWRITECMDA_REG; +#else + uint32_t reg_val = QSPI_REG(channel)->QSPI_W_AWRITECMDA_REG; +#endif + + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_INST, reg_val, p_wrt_instr_cfg->write_opcode); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_INST_TX_MD, reg_val, p_wrt_instr_cfg->opcode_bus_mode); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_ADR_TX_MD, reg_val, p_wrt_instr_cfg->addr_bus_mode); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_DAT_TX_MD, reg_val, p_wrt_instr_cfg->data_bus_mode); +#if !defined(BSP_MCU_GROUP_RA6W1) + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_INST_WB, reg_val, p_wrt_instr_cfg->write_opcode_wb); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_DMY_TX_MD, reg_val, p_wrt_instr_cfg->dummy_bus_mode); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_DMY_EN, reg_val, p_wrt_instr_cfg->dummy_en); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_DMY_NUM, reg_val, p_wrt_instr_cfg->dummy_bytes); + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_WDEX_EN, reg_val, p_wrt_instr_cfg->wdex_en); +#else + QSPI_W_AWRITECMDA_REG_FIELD_SET(QSPIC_WR_CS_HIGH_MIN, reg_val, p_wrt_instr_cfg->cs_hi_min_clk_cycles); +#endif + QSPI_REG(channel)->QSPI_W_AWRITECMDA_REG = reg_val; +} + +/*******************************************************************************************************************//** + * Initialize the burst break instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_break_instr_cfg Pointer to configuration structure of Burst break instruction. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_break_instr_init (uint8_t channel, + const qspi_w_break_instr_cfg_t * p_break_instr_cfg) +{ + QSPI_REG(channel)->QSPIC_BURSTBRK_REG = + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_SEC_HF_DS, p_break_instr_cfg->break_sec_hf) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_SZ, p_break_instr_cfg->break_sz) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_TX_MD, p_break_instr_cfg->break_tx_md) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_EN, p_break_instr_cfg->break_en) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_WRD, p_break_instr_cfg->break_opcode); +} + +/*******************************************************************************************************************//** + * Initialize the External memory burst of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_memblen_cfg Pointer to configuration structure of External memory burst. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_memblen_init (uint8_t channel, const qspi_w_memblen_cfg_t * p_memblen_cfg) +{ + QSPI_REG(channel)->QSPIC_MEMBLEN_REG = + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_MEMBLEN, p_memblen_cfg->memblen) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_T_CEM_EN, p_memblen_cfg->tcem_en) | +#if defined(BSP_MCU_GROUP_RA6W1) + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_T_CEM_CC, p_memblen_cfg->tcem_cc); +#else + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_T_CEM_CC, p_memblen_cfg->tcem_cc) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_RD_LIN_EN, p_memblen_cfg->rd_lin_en) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_KEEP_ACTIVE, p_memblen_cfg->keep_active) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_WCMD_HYBRID, p_memblen_cfg->wcmd_hybrid) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_DIELEN, p_memblen_cfg->dielen) | + FSP_REG_FIELD_SET_BITS32(QSPIC, QSPIC_MEMBLEN_REG, QSPIC_ACTIVE_THR, p_memblen_cfg->active_thr); +#endif +} + +/*******************************************************************************************************************//** + * Get erase status. + * + * @param[in] channel QSPI controller id. + * + * @retval QSPI_W_ERS_NO No erase + * @retval QSPI_W_ERS_PENDING Pending erase request. + * @retval QSPI_W_ERS_RUNNING Erase procedure is running. + * @retval QSPI_W_ERS_SUSPENDED Suspended erase procedure. + * @retval QSPI_W_ERS_FINISHING Finishing the erase procedure. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE qspi_w_ers_t r_qspi_w_get_erase_status (uint8_t channel) +{ + QSPI_REG(channel)->QSPIC_CHCKERASE_REG = 0; + + return (qspi_w_ers_t) (QSPI_REG(channel)->QSPIC_ERASECTRL_REG_b.QSPIC_ERS_STATE); +} + +/*******************************************************************************************************************//** + * Generate 8 bits data transfer from the external device to the QSPIC (manual mode). + * + * @param[in] channel QSPI controller id. + * + * @return uint8_t 8 bits value read from the bus. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE uint8_t r_qspi_w_read8 (uint8_t channel) +{ + volatile qspi_w_data_t * p_tmp = (volatile qspi_w_data_t *) &(QSPI_REG(channel)->QSPIC_READDATA_REG); + + return p_tmp->data8; +} + +/*******************************************************************************************************************//** + * Fast copy of a buffer to a FIFO. + * + * @details Implementation of a fast copy of the contents of a buffer to a FIFO in assembly. + * All addresses are word aligned. + * + * @param[in] start Pointer to the beginning of the buffer. + * @param[in] end Pointer to the end of the buffer. + * @param[out] dest Pointer to the FIFO. + * + * @warning No validity checks are made! It is the responsibility of the caller to make sure that + * sane values are passed to this function. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_fast_write_to_fifo32 (uint32_t start, uint32_t end, uint32_t dest) +{ + __asm volatile ("copy: \n" + " ldmia %[start]!, {r3} \n" + " str r3, [%[dest]] \n" + " cmp %[start], %[end] \n" + " blt copy \n" + : + : /* output */ + [start] "l" (start), [end] "r" (end), [dest] "l" (dest) : /* inputs (%0, %1, %2) */ + "r3"); /* registers that are destroyed. */ +} + +/*******************************************************************************************************************//** + * Enter Manual Access Mode. + * + * @note This function does not turn the QSPI Flash memory out of the XiP Mode of operation, if enabled. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + **********************************************************************************************************************/ +__STATIC_FORCEINLINE void r_qspi_w_enter_manual_access_mode (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + if (QSPI_W_ACCESS_MODE_AUTO == QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD) + { + QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD = QSPI_W_ACCESS_MODE_MANUAL; + } +} + +/*******************************************************************************************************************//** + * Writes raw data to QSPI_W. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] p_src Pointer to data to write. + * @param[in] bytes Number of bytes to write. + * @param[in] read_after_write Whether or not to close SPI bus cycle. + **********************************************************************************************************************/ +static void r_qspi_w_direct_write_sub (qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + /* Enter direct communication mode. */ + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; + + /* Write data to QSPI_W. */ + for (uint32_t i = 0; i < bytes; i++) + { + r_qspi_w_write8(channel, p_src[i]); + } + + if (!read_after_write) + { + /* Close the SPI bus cycle. */ + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; + + /* Return to ROM access mode. */ + r_qspi_w_enter_auto_access_mode(p_inst_extend); + } +} + +/*******************************************************************************************************************//** + * Reads raw data from QSPI_W. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[out] p_dest Pointer to store data. + * @param[in] bytes Number of bytes to read. + **********************************************************************************************************************/ +static void r_qspi_w_direct_read_sub (qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t * const p_dest, + uint32_t const bytes) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + /* Read data from QSPI_W. */ + for (uint32_t i = 0; i < bytes; i++) + { + p_dest[i] = r_qspi_w_read8(channel); + } + + /* Close the SPI bus cycle. */ + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; + + /* Return to ROM access mode. */ + r_qspi_w_enter_auto_access_mode(p_inst_extend); +} + +/*******************************************************************************************************************//** + * Enters or exits XiP (execute in place) mode. + * + * @note Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. + * This is a user task. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] code Code to place in M7-M0. + * @param[in] enter_mode True to enter, false to exit. + * + * @retval FSP_SUCCESS Enter/Exit XiP mode successfully. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_xip (qspi_w_instance_ctrl_t * p_instance_ctrl, uint8_t code, bool enter_mode) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + if (enter_mode) + { + QSPI_REG(channel)->QSPIC_BURSTCMDB_REG_b.QSPIC_INST_MD = QSPI_W_INSTR_MD_TX_ONLY_IN_FIRST_ACCESS; + r_qspi_w_set_extra_byte(channel, code, p_inst_extend->p_qspi_flash_cfg->p_read_instr_cfg); + } + else + { + QSPI_REG(channel)->QSPIC_BURSTCMDB_REG_b.QSPIC_INST_MD = QSPI_W_INSTR_MD_TX_AT_ANY_BURST_ACCESS; + + /* Exit XiP mode. */ + volatile uint8_t dummy = 0; + FSP_PARAMETER_NOT_USED(dummy); + + r_qspi_w_set_extra_byte(channel, code, p_inst_extend->p_qspi_flash_cfg->p_read_instr_cfg); + + /* Read from QSPI_W (preferably non-cached access) to send + * the XiP exit request (i.e. code - extra byte - mode bits). */ + dummy = *(volatile uint8_t *) QSPI_W_DEVICE_START_ADDRESS_DATA; + } + + p_instance_ctrl->xip_mode_is_enabled = enter_mode; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set QSPIC bus mode. + * + * @param[in] channel QSPI controller id. + * @param[in] bus_mode The QSPIC Bus Mode. + **********************************************************************************************************************/ +static void r_qspi_w_manual_access_bus_mode_set (uint8_t channel, qspi_w_bus_mode_t bus_mode) +{ + if (g_manual_access_bus_mode != bus_mode) + { + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = 1U << bus_mode; + r_qspi_w_set_io(channel, bus_mode); + g_manual_access_bus_mode = bus_mode; + } +} + +/*******************************************************************************************************************//** + * Set device to auto mode. + * + * @param[in] p_inst_extend Pointer to a driver extended handle. + **********************************************************************************************************************/ +static void r_qspi_w_enter_auto_access_mode (qspi_w_extended_cfg_t * p_inst_extend) +{ + uint8_t channel = p_inst_extend->channel; + + /* + * Before switching to Auto Access Mode set the direction of all QSPIC IOs so that they are + * selected by the controller. + */ + qspi_w_bus_mode_t bus_mode = p_inst_extend->p_qspi_flash_cfg->p_read_instr_cfg->data_bus_mode; + + r_qspi_w_set_io(channel, bus_mode); + QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD = QSPI_W_ACCESS_MODE_AUTO; +} + +/*******************************************************************************************************************//** + * Write data to flash memory. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] addr Zero based address of the flash memory, where the + * content of the p_buf is to be written. + * @param[in] p_buf Pointer to the source data. + * @param[in] size Number of bytes to write. + * + * @return Number of written bytes by the function call. + * + * @warning This function switches and leaves the QSPIC to manual access mode. Therefore, it must + * be called with disabled interrupts. It's up to the caller to switch the QSPIC back to + * auto access mode, in order to re-enable XiP. + * + * @warning The write operation will not exceed the page boundary. Thus, It's up to the caller to + * issue another call of the function, in order to write the remaining data to the next page. + **********************************************************************************************************************/ +static uint32_t r_qspi_w_flash_write_page (qspi_w_instance_ctrl_t * p_instance_ctrl, + uint32_t addr, + const uint8_t * p_buf, + uint32_t size) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + uint32_t written_bytes = 0; + uint32_t addr_unaligned_bytes = 0; + uint32_t bytes_aligned32 = 0; + uint32_t page_boundary; + uint8_t opcode = + p_inst_extend->p_qspi_flash_cfg->p_write_instr_cfg->write_opcode; + qspi_w_bus_mode_t write_enable_bus_mode = + p_inst_extend->p_qspi_flash_cfg->p_write_enable_instr_cfg->opcode_bus_mode; + qspi_w_bus_mode_t opcode_bus_mode = + p_inst_extend->p_qspi_flash_cfg->p_write_instr_cfg->opcode_bus_mode; + qspi_w_bus_mode_t addr_bus_mode = + p_inst_extend->p_qspi_flash_cfg->p_write_instr_cfg->addr_bus_mode; + qspi_w_bus_mode_t data_bus_mode = + p_inst_extend->p_qspi_flash_cfg->p_write_instr_cfg->data_bus_mode; + spi_flash_address_bytes_t addr_bytes = p_instance_ctrl->p_cfg->address_bytes; + + /* Reduce max write size, that can reduce interrupt latency time. */ + if (size > p_instance_ctrl->p_cfg->page_size_bytes) + { + size = p_instance_ctrl->p_cfg->page_size_bytes; + } + + /* Make sure write will not cross page boundary. */ + page_boundary = p_instance_ctrl->p_cfg->page_size_bytes - (addr & QSPI_W_FLASH_PAGE_SIZE); + if (size > page_boundary) + { + size = page_boundary; + } + + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + r_qspi_w_manual_access_bus_mode_set(channel, write_enable_bus_mode); + r_qspi_w_flash_write_enable(p_instance_ctrl); + + r_qspi_w_manual_access_bus_mode_set(channel, opcode_bus_mode); + + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; + r_qspi_w_write8(channel, opcode); + + r_qspi_w_manual_access_bus_mode_set(channel, addr_bus_mode); + + if (SPI_FLASH_ADDRESS_BYTES_4 == addr_bytes) + { + r_qspi_w_write32(channel, addr); + } + else + { + r_qspi_w_write8(channel, (uint8_t) ((addr >> 16U) & 0xFF)); + r_qspi_w_write8(channel, (uint8_t) ((addr >> 8U) & 0xFF)); + r_qspi_w_write8(channel, (uint8_t) (addr & 0xFF)); + } + + r_qspi_w_manual_access_bus_mode_set(channel, data_bus_mode); + + /* Write address-unaligned data byte-per-byte */ + addr_unaligned_bytes = 4 - (((uint32_t) p_buf) & 3); + for (written_bytes = 0; written_bytes < addr_unaligned_bytes && written_bytes < size; ++written_bytes) + { + r_qspi_w_write8(channel, p_buf[written_bytes]); + } + + /* Write size-aligned data word-per-word */ + bytes_aligned32 = ((size - written_bytes) & 0xFFFFFFFCUL); + if (bytes_aligned32) + { + r_qspi_w_fast_write_to_fifo32((uint32_t) (p_buf + written_bytes), + (uint32_t) (p_buf + written_bytes + bytes_aligned32), + (uint32_t) &((QSPI_REG(channel))->QSPIC_WRITEDATA_REG)); + written_bytes += bytes_aligned32; + } + + /* Write size-unaligned data byte-per-byte */ + for ( ; written_bytes < size; ++written_bytes) + { + r_qspi_w_write8(channel, p_buf[written_bytes]); + } + + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; + + return written_bytes; +} + +/*******************************************************************************************************************//** + * Return the zero-based chip address from the memory mapped address. + * + * @param[in] p_addr Pointer to memory mapped address. + * + * @return uint32_t Zero-based chip address. + **********************************************************************************************************************/ +static uint32_t r_qspi_w_get_chip_address (uint8_t * const p_addr) +{ + if ((uint32_t) p_addr >= QSPI_W_DEVICE_START_ADDRESS_DATA) + { + return (uint32_t) p_addr - QSPI_W_DEVICE_START_ADDRESS_DATA; + } + else + { + return (uint32_t) p_addr - QSPI_W_DEVICE_START_ADDRESS; + } +} + +/*******************************************************************************************************************//** + * Erase block/sector of flash memory. + * + * @note Before erasing the flash memory, it is mandatory to set up the erase instructions + * first by calling r_qspi_w_erase_instr_init(). + * + * @note Call r_qspi_w_get_erase_status() to check whether the erase operation has finished. + * + * @note Before switching the QSPI controller to manual mode check that + * r_qspi_w_get_erase_status() == QSPI_W_ERASE_STATUS_NO. + * + * @param[in] channel QSPI controller id. + * @param[in] addr Memory address of the block/sector to be erased. + **********************************************************************************************************************/ +static void r_qspi_w_erase_block (uint8_t channel, uint32_t addr) +{ + uint32_t block_sector = addr / QSPI_W_FLASH_SECTOR_SIZE; + + /* Wait for previous erase to end. */ + while (QSPI_W_ERS_NO != r_qspi_w_get_erase_status(channel)) + { + /* No messages to process. */ + ; + } + + if (QSPI_W_ACCESS_MODE_AUTO != QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD) + { + QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_AUTO_MD = QSPI_W_ACCESS_MODE_AUTO; + } + + /* + * In order to calculate the sector number and set the proper value for the QSPIC_ERS_ADDR + * field in the QSPIC_ERASECTRL_REG, the given address needs to be divided by the sector size. + * However, when using 24 bits addressing size, the sector number needs to be stored in the + * higher 12 bits of the field, as the remaining bits are disregarded. As a result, the sector + * number must be shifted left by 8 bits to account for this. + * + * QSPIC_ERASECTRL_REG[QSPIC_ERS_ADDR] + * ===================================================================== + * 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + * ===================================================================== + * 24 bits: v v v v v v v v v v v v x x x x x x x x + * 32 bits: v v v v v v v v v v v v v v v v v v v v + */ + if (0 == QSPI_REG(channel)->QSPIC_CTRLMODE_REG_b.QSPIC_USE_32BA) + { + block_sector <<= 8U; + } + + uint32_t erasectrl_reg = QSPI_REG(channel)->QSPIC_ERASECTRL_REG; + + /* Setup erase block page. */ + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_ERASECTRL_REG, QSPIC_ERS_ADDR, erasectrl_reg, block_sector); + + /* Trigger erase. */ + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_ERASECTRL_REG, QSPIC_ERASE_EN, erasectrl_reg, 1); + + QSPI_REG(channel)->QSPIC_ERASECTRL_REG = erasectrl_reg; +} + +/*******************************************************************************************************************//** + * Erase sector of flash memory. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] addr Memory address of the sector to be erased. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_erase_flash_sector (qspi_w_instance_ctrl_t * p_instance_ctrl, uint32_t addr) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + uint32_t timeout = QSPI_W_PRV_TIMEOUT_US; + + while (!r_qspi_w_flash_is_writable(p_instance_ctrl)) + { + /* No messages to process. */ + ; + } + + r_qspi_w_erase_block(channel, addr); + + /* Ensure erase block has started. QSPI_W_ERS_NO will occur later when erase will be finished. User has to monitor when erase is done. */ + while (QSPI_W_ERS_NO == r_qspi_w_get_erase_status(channel) && timeout) + { + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + timeout--; + } + + FSP_ERROR_RETURN(0U < timeout, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get erase instruction code. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] byte_count Number of bytes to be erased. + * + * @return uint16_t Erase instruction code. + **********************************************************************************************************************/ +static uint16_t r_qspi_w_get_erase_opcode (qspi_w_instance_ctrl_t * p_instance_ctrl, uint32_t byte_count) +{ + uint16_t erase_command = 0; + + for (uint32_t idx = 0; idx < p_instance_ctrl->p_cfg->erase_command_list_length; idx++) + { + /* If requested byte_count is supported by underlying flash, store the command. */ + if (byte_count == p_instance_ctrl->p_cfg->p_erase_command_list[idx].size) + { + erase_command = p_instance_ctrl->p_cfg->p_erase_command_list[idx].command; + break; + } + } + + return erase_command; +} + +/*******************************************************************************************************************//** + * Erase chip. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] erase_command Erase instruction code. + **********************************************************************************************************************/ +static void r_qspi_w_erase_chip (qspi_w_instance_ctrl_t * p_instance_ctrl, uint8_t erase_command) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + /* Disable the interrupts as long as the QSPIC remains in manual access mode. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + r_qspi_w_flash_write_enable(p_instance_ctrl); + r_qspi_w_flash_cmd(channel, erase_command); + while (r_qspi_w_flash_is_busy(p_instance_ctrl)) + { + /* No messages to process. */ + ; + } + + r_qspi_w_enter_auto_access_mode(p_inst_extend); + + /* Re-enable the interrupts since the QSPIC switched back to auto access mode. */ + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Initialize the QSPI controller instruction registers. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + **********************************************************************************************************************/ +static void r_qspi_w_instructions_init (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + r_qspi_w_read_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_read_instr_cfg); + r_qspi_w_break_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_break_instr_cfg); + r_qspi_w_memblen_init(channel, p_inst_extend->p_qspi_flash_cfg->p_memblen_cfg); + r_qspi_w_write_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_write_instr_cfg); + r_qspi_w_read_status_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_read_status_instr_cfg); + r_qspi_w_erase_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_erase_instr_cfg); + r_qspi_w_suspend_resume_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_suspend_resume_instr_cfg); + r_qspi_w_write_enable_instr_init(channel, p_inst_extend->p_qspi_flash_cfg->p_write_enable_instr_cfg); +#if BSP_FEATURE_QSPI_HAS_DDR_SUPPORT + if (p_inst_extend->p_qspi_flash_cfg->p_ctrl_ddr) + { + QSPI_REG(channel)->QSPIC_CTRLDDRA_REG = p_inst_extend->p_qspi_flash_cfg->p_ctrl_ddr->ctrl_ddra; + QSPI_REG(channel)->QSPIC_CTRLDDRB_REG = p_inst_extend->p_qspi_flash_cfg->p_ctrl_ddr->ctrl_ddrb; + } + + if (p_inst_extend->p_qspi_flash_cfg->p_extra_regs) + { + QSPI_REG(channel)->QSPIC_CTRLMR_REG = p_inst_extend->p_qspi_flash_cfg->p_extra_regs->ctrl_mr_reg; + QSPI_REG(channel)->QSPIC_DRST_CMD_REG = p_inst_extend->p_qspi_flash_cfg->p_extra_regs->drst_cmd_reg; + } +#endif +} + +/*******************************************************************************************************************//** + * Initialize the QSPI controller based on the QSPI_W flash driver. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + **********************************************************************************************************************/ +static void r_qspi_w_controller_init (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + uint32_t clkamba_reg = CRG_TOP->CLK_AMBA_REG; + +#if BSP_FEATURE_QSPI_HAS_DDR_SUPPORT + QSPI_W_CLK_AMBA_REG_FIELD_SET(SDR_DIV2, clkamba_reg, p_inst_extend->qspclk_div); + QSPI_W_CLK_AMBA_REG_FIELD_SET(SDR_MODE, clkamba_reg, p_inst_extend->qspi_mode); +#else + QSPI_W_CLK_AMBA_REG_FIELD_SET(DIV, clkamba_reg, p_inst_extend->qspclk_div); +#endif + QSPI_W_CLK_AMBA_REG_FIELD_SET(ENABLE, clkamba_reg, 1); + + CRG_TOP->CLK_AMBA_REG = clkamba_reg; + + /* CLK_AMBA_REG is in APB (PCLK might be slower than HCLK). */ + FSP_HARDWARE_REGISTER_WAIT(CRG_TOP->CLK_AMBA_REG, clkamba_reg); + + FSP_CRITICAL_SECTION_EXIT; + uint32_t ctrlmode_reg = QSPI_REG(channel)->QSPIC_CTRLMODE_REG; + uint32_t gp_reg = QSPI_REG(channel)->QSPIC_GP_REG; + + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_USE_32BA, ctrlmode_reg, + p_instance_ctrl->p_cfg->address_bytes); + + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_CTRLMODE_REG, + QSPIC_CLK_MD, + ctrlmode_reg, + p_inst_extend->p_qspi_flash_cfg->clk_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_RXD_NEG, ctrlmode_reg, QSPI_W_SAMPLING_EDGE_POS); + + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_RPIPE_EN, ctrlmode_reg, QSPI_W_READ_PIPE_ENABLE); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_PCLK_MD, ctrlmode_reg, QSPI_W_READ_PIPE_DELAY); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_HRDY_MD, ctrlmode_reg, QSPI_W_HREADY_MODE_WAIT); +#if !defined(BSP_MCU_GROUP_RA6W1) + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_MAN_DIRCHG_MD, ctrlmode_reg, 1); +#endif + + if (p_inst_extend->p_qspi_flash_cfg->is_ram) + { + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_SRAM_EN, ctrlmode_reg, 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_CS_MD, ctrlmode_reg, 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_CLK_FREE_EN, ctrlmode_reg, 1); + + QSPI_REG(channel)->QSPIC_CTRLMODE_REG = ctrlmode_reg; + + for (uint32_t i = 0; i < 10; i++) + { + __NOP(); + } + + QSPIC->QSPIC_CTRLMODE_REG_b.QSPIC_CLK_FREE_EN = 0; + } + else + { + QSPI_REG(channel)->QSPIC_CTRLMODE_REG = ctrlmode_reg; + } + + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, gp_reg, p_inst_extend->qspi_drive_current); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, gp_reg, p_inst_extend->qspi_slew_rate); + + QSPI_REG(channel)->QSPIC_GP_REG = gp_reg; + + r_qspi_w_enter_auto_access_mode(p_inst_extend); +} + +/*******************************************************************************************************************//** + * Based on the requested protocol, return the bus mode of the instruction (or opcode) and addr/extra/dummy/data bus. + * + * @note The protocol mode xS-xS-xS means that the bus (opcode, address and data) is in Single Data Rate. + * The protocol mode xD-xD-xD means that the bus (opcode, address and data) is in Double Data Rate. + * + * @param[in] spi_protocol Requested protocol. + * @param[out] p_bus_mode Pointer to store data. + **********************************************************************************************************************/ +static void r_qspi_w_get_bus_mode (spi_flash_protocol_t spi_protocol, qspi_w_bus_mode_t * p_bus_mode) +{ + switch (spi_protocol) + { + case SPI_FLASH_PROTOCOL_EXTENDED_SPI: // SPI_FLASH_PROTOCOL_1S_1S_1S is the same enum value. + { + p_bus_mode[QSPI_W_IDX_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_SINGLE; + p_bus_mode[QSPI_W_IDX_NON_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_SINGLE; + break; + } + + case SPI_FLASH_PROTOCOL_1S_2S_2S: + { + p_bus_mode[QSPI_W_IDX_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_SINGLE; + p_bus_mode[QSPI_W_IDX_NON_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_DUAL; + break; + } + + case SPI_FLASH_PROTOCOL_1S_4S_4S: + { + p_bus_mode[QSPI_W_IDX_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_SINGLE; + p_bus_mode[QSPI_W_IDX_NON_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_QUAD; + break; + } + + case SPI_FLASH_PROTOCOL_2S_2S_2S: + { + p_bus_mode[QSPI_W_IDX_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_DUAL; + p_bus_mode[QSPI_W_IDX_NON_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_DUAL; + break; + } + + /* The below protocols transmit both the instruction and non instruction bytes using QUAD bus mode */ + case SPI_FLASH_PROTOCOL_QPI: + case SPI_FLASH_PROTOCOL_4S_4S_4S: + case SPI_FLASH_PROTOCOL_4S_4D_4D: + { + p_bus_mode[QSPI_W_IDX_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_QUAD; + p_bus_mode[QSPI_W_IDX_NON_INSTR_BUS_MODE] = QSPI_W_BUS_MODE_QUAD; + break; + } + + default: + { + break; + } + } +} + +/*******************************************************************************************************************//** + * Check if the Flash can accept commands. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * + * @return bool True if the Flash is not busy else false. + **********************************************************************************************************************/ +static bool r_qspi_w_flash_is_writable (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + bool writable; + + /* Disable the interrupts as long as the QSPIC remains in manual access mode. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + r_qspi_w_enter_manual_access_mode(p_instance_ctrl); + + /* Check if flash is ready. */ + writable = !(r_qspi_w_flash_is_busy(p_instance_ctrl)); + + r_qspi_w_enter_auto_access_mode(p_inst_extend); + + /* Re-enable the interrupts since the QSPIC switched back to auto access mode. */ + FSP_CRITICAL_SECTION_EXIT; + + return writable; +} + +/*******************************************************************************************************************//** + * Send flash command. + * + * @param[in] channel QSPI controller id. + * @param[in] opcode Command code to be send to the flash device. + **********************************************************************************************************************/ +static void r_qspi_w_flash_cmd (uint8_t channel, const uint8_t opcode) +{ + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; + r_qspi_w_write8(channel, opcode); + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; +} + +/*******************************************************************************************************************//** + * Set WEL (Write Enable Latch) bit of the Status Register of the Flash. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * + * @details The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, + * Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers + * instruction. In the case of Write Status Register command, any status bits will be written + * as non-volatile bits. + * + * @note This function blocks until the Flash has processed the command and it will be repeated if, + * for any reason, the command was not successfully executed by the Flash. + **********************************************************************************************************************/ +static void r_qspi_w_flash_write_enable (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint8_t channel = p_inst_extend->channel; + + uint8_t status; + uint8_t opcode = p_inst_extend->p_qspi_flash_cfg->p_write_enable_instr_cfg->opcode; + + /* Wait till the Write enable bit in the flash device status register is set. */ + do + { + r_qspi_w_flash_cmd(channel, opcode); + + /* Wait till the WIP(Write in progress bit) in the flash device status register is cleared. */ + do + { + status = r_qspi_w_read_status_register(p_instance_ctrl); + } while (status & (1U << p_instance_ctrl->p_cfg->write_status_bit)); + } while (!(status & (1U << p_instance_ctrl->p_cfg->write_enable_bit))); +} + +/*******************************************************************************************************************//** + * Check if the device is busy. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * + * @return bool True if the BUSY bit is set else false. + * + * @warning This function checks the value of the BUSY bit in the Status Register 1 of the Flash. It + * is the responsibility of the caller to call the function in the right context. The + * function must be called with interrupts disabled. + **********************************************************************************************************************/ +static bool r_qspi_w_flash_is_busy (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + uint8_t status_reg = r_qspi_w_read_status_register(p_instance_ctrl); + bool status_wip = (status_reg >> p_instance_ctrl->p_cfg->write_status_bit) & 1; + + return status_wip; +} + +/*******************************************************************************************************************//** + * Set an extra byte to use with read instructions, used to enter/stay/exit XiP mode. + * + * @param[in] channel QSPI controller id. + * @param[in] extra_byte An extra byte transferred after the address asking memory to + * stay in XiP mode or wait for a normal instruction + * after CS goes inactive. + * @param[in] p_qspi_cfg Pointer to configuration structure of the read instruction. + **********************************************************************************************************************/ +static void r_qspi_w_set_extra_byte (uint8_t channel, uint8_t extra_byte, qspi_w_read_instr_cfg_t const * p_qspi_cfg) +{ + QSPI_REG(channel)->QSPIC_BURSTCMDA_REG = (QSPI_REG(channel)->QSPIC_BURSTCMDA_REG & + ~(FSP_REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE) | + FSP_REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD))) | + FSP_REG_FIELD_SET_BITS32(QSPIC, + QSPIC_BURSTCMDA_REG, + QSPIC_EXT_BYTE, + extra_byte) | + FSP_REG_FIELD_SET_BITS32(QSPIC, + QSPIC_BURSTCMDA_REG, + QSPIC_EXT_TX_MD, + p_qspi_cfg->extra_byte_bus_mode); + + QSPI_REG(channel)->QSPIC_BURSTCMDB_REG = (QSPI_REG(channel)->QSPIC_BURSTCMDB_REG & + ~(FSP_REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN) | + FSP_REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS))) | + FSP_REG_FIELD_SET_BITS32(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_EXT_BYTE_EN, + p_qspi_cfg->extra_byte_en) | + FSP_REG_FIELD_SET_BITS32(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_EXT_HF_DS, + p_qspi_cfg->extra_byte_half_cfg); +} + +/*******************************************************************************************************************//** + * Initialize the read instruction of the QSPIC. + * + * @param[in] channel QSPI controller id. + * @param[in] p_read_instr_cfg Pointer to configuration structure of the read instruction. + **********************************************************************************************************************/ +static void r_qspi_w_read_instr_init (uint8_t channel, const qspi_w_read_instr_cfg_t * p_read_instr_cfg) +{ + uint32_t burstcmda_reg = QSPI_REG(channel)->QSPIC_BURSTCMDA_REG; + uint32_t burstcmdb_reg = QSPI_REG(channel)->QSPIC_BURSTCMDB_REG; + + /* QSPIC_BURSTCMDA_REG. */ + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST, burstcmda_reg, p_read_instr_cfg->opcode); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_WB, burstcmda_reg, p_read_instr_cfg->opcode_wb); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE, burstcmda_reg, + p_read_instr_cfg->extra_byte_value); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_TX_MD, burstcmda_reg, + p_read_instr_cfg->opcode_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_ADR_TX_MD, burstcmda_reg, p_read_instr_cfg->addr_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_BURSTCMDA_REG, + QSPIC_EXT_TX_MD, + burstcmda_reg, + p_read_instr_cfg->extra_byte_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_DMY_TX_MD, burstcmda_reg, p_read_instr_cfg->dummy_bus_mode); + + /* QSPIC_BURSTCMDB_REG. */ + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DAT_RX_MD, burstcmdb_reg, p_read_instr_cfg->data_bus_mode); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN, burstcmdb_reg, + p_read_instr_cfg->extra_byte_en); + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_EXT_HF_DS, + burstcmdb_reg, + p_read_instr_cfg->extra_byte_half_cfg); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, burstcmdb_reg, p_read_instr_cfg->instr_md); +#if !defined(BSP_MCU_GROUP_RA6W1) + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_DMY_NUM, + burstcmdb_reg, + (0 == + p_read_instr_cfg->dummy_bytes) ? p_read_instr_cfg->dummy_bytes : p_read_instr_cfg->dummy_bytes - + 1); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_EN, burstcmdb_reg, p_read_instr_cfg->dummy_en); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_BLEN, burstcmdb_reg, p_read_instr_cfg->wrap_blen); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_WR_EN, burstcmdb_reg, p_read_instr_cfg->wrap_wr_en); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_RD_BEND_MD, burstcmdb_reg, p_read_instr_cfg->rd_bend_md); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_RD_RDB_EN, burstcmdb_reg, p_read_instr_cfg->rd_rdb_en); +#else + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_DMY_NUM, + burstcmdb_reg, + (4U <= p_read_instr_cfg->dummy_bytes) ? 3U : p_read_instr_cfg->dummy_bytes); +#endif + FSP_REG_VAR_FIELD_SET(QSPIC, + QSPIC_BURSTCMDB_REG, + QSPIC_CS_HIGH_MIN, + burstcmdb_reg, + p_read_instr_cfg->cs_high_min_cycles); + FSP_REG_VAR_FIELD_SET(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, burstcmdb_reg, p_read_instr_cfg->wrap_md); + + QSPI_REG(channel)->QSPIC_BURSTCMDA_REG = burstcmda_reg; + QSPI_REG(channel)->QSPIC_BURSTCMDB_REG = burstcmdb_reg; +} + +/*******************************************************************************************************************//** + * Write an arbitrary number of bytes to the Flash and then read an arbitrary number of bytes + * from the Flash in one transaction. + * + * @param[in] p_inst_extend Pointer to a driver extended handle. + * @param[in] p_wbuf Pointer to the beginning of the buffer that contains the data to be written. + * @param[in] wlen The number of bytes to be written. + * @param[out] p_rbuf Pointer to the beginning of the buffer that the read data are stored. + * @param[in] rlen The number of bytes to be read. + * + * @note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use + * faster access methods (i.e. transfer words instead of bytes whenever it is possible). + **********************************************************************************************************************/ +static void r_qspi_w_transact (qspi_w_extended_cfg_t * p_inst_extend, + const uint8_t * p_wbuf, + uint32_t wlen, + uint8_t * p_rbuf, + uint32_t rlen) +{ + uint8_t channel = p_inst_extend->channel; + + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; + + for (uint32_t i = 0; i < wlen; ++i) + { + r_qspi_w_write8(channel, p_wbuf[i]); + } + + for (uint32_t i = 0; i < rlen; ++i) + { + p_rbuf[i] = r_qspi_w_read8(channel); + } + + QSPI_REG(channel)->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; +} + +/*******************************************************************************************************************//** + * Read the Status Register of the Flash. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * + * @return uint8_t The value of the Status Register of the Flash. + **********************************************************************************************************************/ +static uint8_t r_qspi_w_read_status_register (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint8_t status; + uint8_t cmd[] = {p_instance_ctrl->p_cfg->status_command}; + + r_qspi_w_transact(p_inst_extend, cmd, 1, &status, 1); + + return status; +} + +#if QSPI_W_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Ensures that the parameters are valid and also that there is no write or erase operation inprogress. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_param_checking_dcom (qspi_w_instance_ctrl_t * p_instance_ctrl) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_W_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Do not enter direct communication mode from XiP mode. */ + qspi_w_extended_cfg_t * p_inst_extend = (qspi_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + FSP_ERROR_RETURN(false == p_instance_ctrl->xip_mode_is_enabled, FSP_ERR_INVALID_MODE); + + /* Verify device is not busy. */ + if (!p_inst_extend->p_qspi_flash_cfg->is_ram) + { + FSP_ERROR_RETURN(r_qspi_w_flash_is_writable(p_instance_ctrl), FSP_ERR_DEVICE_BUSY); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Parameter checking for R_QSPI_W_Write. + * + * @param[in] p_instance_ctrl Pointer to a driver handle. + * @param[in] p_src The source of the data to write to QSPI_W. + * @param[in] p_dest The address in QSPI_W to write to. + * @param[in] byte_count The number of bytes to write. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION p_instance_ctrl,p_src or p_dest is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XiP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_program_param_check (qspi_w_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + fsp_err_t err = r_qspi_w_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + + /* Check if byte_count is valid. */ + uint32_t page_size_bytes = p_instance_ctrl->p_cfg->page_size_bytes; + uint32_t bytes_left_in_page = page_size_bytes - ((uint32_t) p_dest % page_size_bytes); + FSP_ASSERT(byte_count > 0); + FSP_ASSERT(byte_count <= bytes_left_in_page); + + return FSP_SUCCESS; +} + +#endif + +#if defined(BSP_MCU_GROUP_RA6W1) + +/*******************************************************************************************************************//** + * Enables the dCache Controller. + **********************************************************************************************************************/ +static void r_qspi_w_dcache_enable (void) +{ + DCACHE->DCACHE_CTRL_REG_b.DCACHE_ENABLE = 1U; +} + +/*******************************************************************************************************************//** + * Disables the dCache Controller. + * + * @retval FSP_SUCCESS dCache disabling successfully. + * @retval FSP_ERR_TIMEOUT dCache disabling timeout. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_dcache_disable (void) +{ + uint32_t timeout = QSPI_W_PRV_TIMEOUT_US; + + if (1U == DCACHE->DCACHE_CTRL_REG_b.DCACHE_ENABLE) + { + DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSH = 1U; + + /* Wait until the write flushing process is complete. */ + while (1U != DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSHED) + { + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + timeout--; + FSP_ERROR_RETURN(0U < timeout, FSP_ERR_TIMEOUT); + } + + /* Clear the completion indication to be ready for the next invocation */ + DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSHED = 0U; + DCACHE->DCACHE_CTRL_REG_b.DCACHE_ENABLE = 0U; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initializes the dCache Controller. + * + * @retval FSP_SUCCESS dCache initializing successfully. + * @retval FSP_ERR_TIMEOUT dCache initializing timeout. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_dcache_init (void) +{ + uint32_t timeout = QSPI_W_PRV_TIMEOUT_US; + + /* initialization of cache. */ + DCACHE->DCACHE_CTRL_REG_b.DCACHE_INIT = 1U; + + while (1U != DCACHE->DCACHE_CTRL_REG_b.DCACHE_READY) + { + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + timeout--; + FSP_ERROR_RETURN(0U < timeout, FSP_ERR_TIMEOUT); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the target data memory cacheable area length and jointly the operational mode. + * + * @param[in] len The cacheable area length + * + * @retval FSP_SUCCESS Cachable length setting successfully. + * @retval FSP_ERR_TIMEOUT Cachable length setting timeout. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_w_dcache_set_cacheable_len (uint32_t len) +{ + uint32_t timeout = QSPI_W_PRV_TIMEOUT_US; + + /* set cacheable length process. */ + if ((0U < DCACHE->DCACHE_CTRL_REG_b.DCACHE_LEN) && (0U == len)) + { + DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSH = 1U; + + /* Wait until the write flushing process is complete. */ + while (1U != DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSHED) + { + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + timeout--; + FSP_ERROR_RETURN(0U < timeout, FSP_ERR_TIMEOUT); + } + + /* Clear the completion indication to be ready for the next invocation. */ + DCACHE->DCACHE_CTRL_REG_b.DCACHE_WFLUSHED = 0U; + } + + DCACHE->DCACHE_CTRL_REG_b.DCACHE_LEN = len & 0x3FFFFU; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the base address of the cacheable area for the target data memory. + **********************************************************************************************************************/ +static void r_qspi_w_dcache_set_cacheable_base (void) +{ + DCACHE->DCACHE_BASE_ADDR_REG_b.DCACHE_BASE_ADDR = 0U; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w.c new file mode 100644 index 000000000000..fbdbcc7adf8d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w.c @@ -0,0 +1,887 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rtc_w.h" +#include "r_rtc_w_helper.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Divisors and Multipliers */ +#define RTC_DIV_MUL_100 (100) +#define RTC_DIV_400 (400) + +#define RTC_FIRST_DAY_OF_A_MONTH (1) + +/* Month : valid range between 0 to 11.*/ +#define RTC_MONTHS_VALUE_MAX (11) +#define RTC_LAST_DAY_OF_LEAP_FEB_MONTH (29) + +/* Year : valid range between 0 to 1099.*/ +#define RTC_YEAR_VALUE_MIN (0) +#define RTC_YEAR_VALUE_MAX (1099) + +/* Seconds : valid range between 0 to 59.*/ +#define RTC_SECONDS_VALUE_MAX (59) + +/* Minute : valid range between 0 to 59. */ +#define RTC_MINUTES_VALUE_MAX (59) + +/* Hours : valid range between 0 to 23. */ +#define RTC_HOURS_VALUE_MAX (23) + +/* Macro definitions for February and March months */ +#define RTC_FEBRUARY_MONTH (1U) +#define RTC_MARCH_MONTH (2U) + +/* As per HW manual, value of Month is between 1 to 12. + * But as per C standards, tm_month is between 0 to 11.*/ +#define RTC_TIME_H_MONTH_WDAY_OFFSET (1) + +/* As per HW manual, value of Year is between 1900 to 2999. + * But as per C standards, tm_year is years since 1900.*/ +#define RTC_TIME_H_YEAR_OFFSET (1900) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + +static fsp_err_t r_rtc_time_and_date_validate(rtc_time_t * const p_time); +static fsp_err_t r_rtc_time_validate(rtc_time_t * const p_time); +static fsp_err_t r_rtc_date_validate(rtc_time_t * const p_time); +static fsp_err_t r_rtc_alarm_time_and_date_validate(rtc_alarm_time_t * const p_alarm); +static fsp_err_t r_rtc_alarm_time_validate(rtc_alarm_time_t * const p_alarm); +static fsp_err_t r_rtc_alarm_date_validate(rtc_alarm_time_t * const p_alarm); +static fsp_err_t r_rtc_month_and_year_validate(uint32_t year, uint32_t month); +static fsp_err_t r_rtc_monthday_validate(uint32_t day_of_month, uint32_t * num_days_month, uint32_t month, + uint32_t year); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +rtc_w_instance_ctrl_t * g_p_rtc_w_ctrl = NULL; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** RTC Implementation of Real Time Clock */ +const rtc_api_t g_rtc_on_rtc_w = +{ + .open = R_RTC_W_Open, + .close = R_RTC_W_Close, + .clockSourceSet = R_RTC_W_ClockSourceSet, + .calendarTimeGet = R_RTC_W_CalendarTimeGet, + .calendarTimeSet = R_RTC_W_CalendarTimeSet, + .calendarAlarmGet = R_RTC_W_CalendarAlarmGet, + .calendarAlarmSet = R_RTC_W_CalendarAlarmSet, + .periodicIrqRateSet = R_RTC_W_PeriodicIrqRateSet, + .infoGet = R_RTC_W_InfoGet, + .errorAdjustmentSet = R_RTC_W_ErrorAdjustmentSet, + .callbackSet = R_RTC_W_CallbackSet, + .timeCaptureSet = R_RTC_W_TimeCaptureSet, + .timeCaptureGet = R_RTC_W_TimeCaptureGet, +}; + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + +/* Number of days in each months start from January to December */ +static const uint8_t days_in_months[12] = {31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup RTC_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens and configures the RTC driver module. Implements @ref rtc_api_t::open. + * @note To start the RTC @ref R_RTC_W_CalendarTimeZoneSet and @ref R_RTC_W_CalendarTimeSet must be called at least once. + * R_RTC_W_Open should be called once globally. + * + * Example: + * @snippet r_rtc_w_example.c R_RTC_W_Open + * + * @retval FSP_SUCCESS Initialization was successful and RTC has started. + * @retval FSP_ERR_ASSERTION Invalid p_ctrl or p_cfg pointer. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_HW_CONDITION Invalid Low-Power clock selected. + *********************************`*************************************************************************************/ +fsp_err_t R_RTC_W_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + /* Parameter checking */ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(RTC_W_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + if (g_p_rtc_w_ctrl) + { + return FSP_ERR_ALREADY_OPEN; + } + + /* Save the module's configuration. */ + p_instance_ctrl->p_cfg = p_cfg; + rtc_extended_cfg_t const * p_extend = p_instance_ctrl->p_cfg->p_extend; + + /* init lock for shared Calendar time data */ + err = RTC_W_LOCK_INIT(p_instance_ctrl); + if (FSP_SUCCESS != err) + { + return err; + } + + /** Mark driver as open by initializing it to "RTC" in its ASCII equivalent. */ + p_instance_ctrl->open = RTC_W_OPEN; + + g_p_rtc_w_ctrl = p_instance_ctrl; + + FSP_PARAMETER_NOT_USED(p_extend); + + return err; +} + +/*******************************************************************************************************************//** + * Close the RTC driver. + * Implements @ref rtc_api_t::close + * + * @retval FSP_SUCCESS De-Initialization was successful and RTC driver closed. + * @retval FSP_ERR_ASSERTION Invalid p_ctrl. + * @retval FSP_ERR_NOT_OPEN Driver not open already for close. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_Close (rtc_ctrl_t * const p_ctrl) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + rtc_extended_cfg_t * p_extend = (rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + FSP_PARAMETER_NOT_USED(p_extend); + + if (g_p_rtc_w_ctrl) + { + p_instance_ctrl->p_cfg = NULL; + } + else + { + return FSP_ERR_NOT_OPEN; + } + + g_p_rtc_w_ctrl = NULL; + + p_instance_ctrl->open = 0U; + + RTC_W_LOCK_DEINIT(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the RTC clock source. Implements @ref rtc_api_t::clockSourceSet. + * + * @retval FSP_ERR_UNSUPPORTED Clock source is the LP clock and which is selected during System Init. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_ClockSourceSet (rtc_ctrl_t * const p_ctrl) +{ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Set the calendar time. + * + * Implements @ref rtc_api_t::calendarTimeSet. + * + * @retval FSP_SUCCESS Calendar time set operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarTimeSet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify the seconds, minutes, hours, year ,day of the week, day of the month, month and year are valid values */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_time_and_date_validate(p_time), FSP_ERR_INVALID_ARGUMENT); +#endif + + __time64_t corrtime, now; + RTC_W_LOCK_TAKE(p_instance_ctrl); + ra6w1_mktime64(p_time, &corrtime); /* convert local time struct tm to GMT time64 */ + ra6w1_time64(&corrtime, &now); /* set GMT time */ + RTC_W_LOCK_GIVE(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the calendar time. + * + * Implements @ref rtc_api_t::calendarTimeGet + * + * @retval FSP_SUCCESS Calendar time get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + __time64_t now; + + RTC_W_LOCK_TAKE(p_instance_ctrl); + ra6w1_time64(NULL, &now); + *p_time = *(struct tm *) ra6w1_localtime64(&now); + RTC_W_LOCK_GIVE(p_instance_ctrl); + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the calendar alarm time. + * + * Implements @ref rtc_api_t::calendarAlarmSet. + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarAlarmSet (rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_alarm); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify the seconds, minutes, hours, year ,day of the week, day of the month and month are valid values */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_alarm_time_and_date_validate(p_alarm), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(p_alarm); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Get the calendar alarm time. + * + * Implements @ref rtc_api_t::calendarAlarmGet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CalendarAlarmGet (rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm) +{ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_alarm); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_alarm); + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Set the periodic interrupt rate and enable periodic interrupt. Periodic interrupts refer to the recurring + * interrupts when a unit of time rolls over. + * + * Implements @ref rtc_api_t::periodicIrqRateSet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_PeriodicIrqRateSet (rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(rate); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Get RTC clock source and running status information and store it in provided pointer p_rtc_info + * + * Implements @ref rtc_api_t::infoGet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_InfoGet (rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info) +{ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_rtc_info); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_rtc_info); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * This function sets time error adjustment + * + * @retval FSP_ERR_UNSUPPORTED Time error adjustment functionality is not supported. + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_ErrorAdjustmentSet (rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg) +{ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != err_adj_cfg); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(err_adj_cfg); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * + * Implements rtc_api_t::callbackSet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_CallbackSet (rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void * const p_context, + rtc_callback_args_t * const p_callback_memory) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + +#if (RTC_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_callback); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Set time capture configuration for the provided channel. + * + * Implements @ref rtc_api_t::timeCaptureSet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_TimeCaptureSet (rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture) +{ +#if BSP_FEATURE_RTC_CAPTURE_CHANNELS + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if (RTC_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time_capture); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_RTC_CAPTURE_CHANNELS > p_time_capture->channel, FSP_ERR_INVALID_CHANNEL); +#endif + rtc_extended_cfg_t const * p_extend = p_instance_ctrl->p_cfg->p_extend; + + FSP_PARAMETER_NOT_USED(p_extend); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_time_capture); +#endif + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Get time capture value of the provided channel. + * + * Implements @ref rtc_api_t::timeCaptureGet + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_RTC_W_TimeCaptureGet (rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture) +{ +#if BSP_FEATURE_RTC_CAPTURE_CHANNELS +#if (RTC_W_CFG_PARAM_CHECKING_ENABLE) + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time_capture); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_RTC_CAPTURE_CHANNELS > p_time_capture->channel, FSP_ERR_INVALID_CHANNEL); +#endif +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_time_capture); +#endif + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t R_RTC_W_CalendarBootTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + __time64_t boottime; + RTC_W_LOCK_TAKE(p_instance_ctrl); + __boottime(&boottime); + *p_time = *(struct tm *) ra6w1_localtime64(&boottime); + RTC_W_LOCK_GIVE(p_instance_ctrl); + return FSP_SUCCESS; +} + +fsp_err_t R_RTC_W_CalendarTimeZoneSet (rtc_ctrl_t * const p_ctrl, long * p_timezone) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_timezone); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + RTC_W_LOCK_TAKE(p_instance_ctrl); + ra6w1_SetTzoff(*p_timezone); + RTC_W_LOCK_GIVE(p_instance_ctrl); + + return FSP_SUCCESS; +} + +fsp_err_t R_RTC_W_CalendarTimeZoneGet (rtc_ctrl_t * const p_ctrl, long * p_timezone) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_timezone); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + RTC_W_LOCK_TAKE(p_instance_ctrl); + *p_timezone = ra6w1_Tzoff(); + RTC_W_LOCK_GIVE(p_instance_ctrl); + + return FSP_SUCCESS; +} + +fsp_err_t R_RTC_W_CalendarGMTTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + __time64_t now; + RTC_W_LOCK_TAKE(p_instance_ctrl); + ra6w1_time64(NULL, &now); + *p_time = *(struct tm *) ra6w1_gmtime64(&now); + RTC_W_LOCK_GIVE(p_instance_ctrl); + + return FSP_SUCCESS; +} + +fsp_err_t R_RTC_W_CalendarTimePassed (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time, bool * p_comp) +{ + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ASSERT(NULL != p_comp); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + __time64_t now, diff; + + RTC_W_LOCK_TAKE(p_instance_ctrl); + ra6w1_time64(NULL, &now); /* current time */ + now += (__time64_t) ra6w1_Tzoff(); + ra6w1_mktime64(p_time, &diff); /* given time */ + RTC_W_LOCK_GIVE(p_instance_ctrl); + + if (now < diff) { + *p_comp = 0; + } else { + *p_comp = 1; + } + + return FSP_SUCCESS; +} + +fsp_err_t R_RTC_W_Time2Str (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time, char * const str_buff_ptr, + size_t maxsize, char const * format) +{ +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + rtc_w_instance_ctrl_t * p_instance_ctrl = (rtc_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time); + FSP_ASSERT(NULL != str_buff_ptr); + FSP_ASSERT(0 != maxsize); + FSP_ASSERT(NULL != format); + FSP_ERROR_RETURN(RTC_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + size_t p_size; + p_size = ra6w1_strftime(str_buff_ptr, maxsize, format, p_time); + + FSP_ASSERT(0 != p_size); + + return FSP_SUCCESS; +} + +rtc_ctrl_t * R_RTC_W_GetCtrl(void) +{ + return g_p_rtc_w_ctrl; +} + +/*******************************************************************************************************************//** + * @} (end addtpgroup RTC_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if RTC_W_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validate time and date fields of time parameter fields. + * Checking if seconds, minutes, hours are valid values by calling sub-function time validate. + * Checking if year, month, day of the week and day of a month are valid values by calling sub-function + * date validate. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_time_and_date_validate (rtc_time_t * const p_time) +{ + fsp_err_t err = FSP_SUCCESS; + err = r_rtc_time_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + err = r_rtc_date_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate time fields of time type parameter + * Checking for the seconds, minutes, hours values for valid specified range. + * Seconds 0 to 59. + * Minutes 0 to 59. + * Hours 0 to 23. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_time_validate (rtc_time_t * p_time) +{ + fsp_err_t err; + err = FSP_SUCCESS; + if ((p_time->tm_sec < 0) || (p_time->tm_sec > RTC_SECONDS_VALUE_MAX) || + (p_time->tm_min < 0) || (p_time->tm_min > RTC_MINUTES_VALUE_MAX) || + (p_time->tm_hour < 0) || (p_time->tm_hour > RTC_HOURS_VALUE_MAX)) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate date fields of time parameter and set day of a Week using Zeller's congruence. + * + * Day of week between 0 to 6. There's a mismatch between hardware configuration, + * as we have a value from 1 through 7 (in BCD) for Day of week register in the RTC. + * This difference will be taken care in the Set and Get functions. + * + * Day of month between 1 to 31. + * + * Month between 0 to 11 as per standard time.h. There's a mismatch between hardware configuration, + * as we have a value from 01 through 12 (in BCD) for Month Counter register in the RTC. + * This difference will be taken care in the Set and Get functions. + * + * As per HW manual, value of Year is between 1900 to 2999, the RTC has a 1099 year calendar from 1900 to 2999. + * But as per C standards, tm_year is years since 1900. + * A sample year set in an application would be like time.tm_year = 2019-1900; (to set year 2019) + * Since RTC API follows the Date and Time structure defined in C standard library , the valid value of year is + * between 0 and 1099, which will be internally converted to HW required value. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_date_validate (rtc_time_t * const p_time) +{ + uint32_t day_of_week; + uint32_t num_days_month; + uint32_t day_of_month; + uint32_t month; + uint32_t year; + uint32_t k_year; + uint32_t j_year; + + day_of_month = (uint32_t) p_time->tm_mday; + month = (uint32_t) p_time->tm_mon; + year = (uint32_t) p_time->tm_year; + + /* Checking the error condition for year and months values + * Here valid value of year is between 0 to 1099 and for month 0 to 11 */ + fsp_err_t err = FSP_SUCCESS; + err = r_rtc_month_and_year_validate(year, month); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + /*For particular valid month, number of days in a month is updated */ + num_days_month = days_in_months[month]; + + /* Checking for February month and Conditions for Leap year. + * Year needs to be translated from time.h format */ + year += RTC_TIME_H_YEAR_OFFSET; + err = r_rtc_monthday_validate(day_of_month, &num_days_month, month, year); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + /* Month parameter valid values are 0 to 11 for January to December. + * For Zeller's congruence formula below, adjust month to run from 3 to 14 for March to February */ + if (month < RTC_MARCH_MONTH) + { + month = (month + 12U); + + /* Adjust year if January or February*/ + --year; + } + + month = month + RTC_TIME_H_MONTH_WDAY_OFFSET; + + /*For the Gregorian calendar, Zeller's congruence formulas is + * h = ( q + [13(m+1)/5] + K + [K/4] + [J/4] + [5J])mod 7 (mod : modulo) + * h is the day of the week , q is the day of the month, + * m is the month (3 = March, 4 = April,..., 14 = February) + * K is the year of the century (year % 100), J is the zero-based century (⌊ year/100 ⌋) + * Day of week between 0 to 6 :- Saturday - Friday */ + k_year = year % RTC_DIV_MUL_100; + j_year = year / RTC_DIV_MUL_100; + day_of_week = day_of_month + ((13 * (month + 1)) / 5) + k_year + (k_year / 4) + (j_year / 4) + (5 * j_year); + day_of_week = day_of_week % 7; + + /* We want day of week between 0 to 6 :- Sunday to Saturday */ + /* d = (h + 6)mod 7 (mod : modulo) */ + p_time->tm_wday = (int16_t) (day_of_week + 6U) % 7U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate alarm time and date of alarm time type parameter + * Checking if the seconds, minutes, hours are valid values, based on alarm enable bits. + * Checking if year, month, day of the week and day of a month are valid values, based on alarm enable bits. + * If alarm enable bit is set for year, month, and day of a month for valid range, Week of the day is + * calculated and updated in alarm time. + * + * @param[in] p_alarm_time Pointer to rtc_alarm_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_time_and_date_validate (rtc_alarm_time_t * const p_alarm_time) +{ + fsp_err_t err = FSP_SUCCESS; + err = r_rtc_alarm_time_validate(p_alarm_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + err = r_rtc_alarm_date_validate(p_alarm_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate alarm time fields of Alarm time type parameter + * Checking if the seconds, minutes, hours value is in the valid specified range, based on alarm enable bits. + * Seconds 0 to 59. + * Minutes 0 to 59. + * Hours 0 to 23. + * + * @param[in] p_alarm_time Pointer to rtc_alarm_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_time_validate (rtc_alarm_time_t * const p_alarm_time) +{ + fsp_err_t err; + err = FSP_SUCCESS; + if (((p_alarm_time->sec_match) && + ((p_alarm_time->time.tm_sec < 0) || (p_alarm_time->time.tm_sec > RTC_SECONDS_VALUE_MAX))) || + ((p_alarm_time->min_match) && + ((p_alarm_time->time.tm_min < 0) || (p_alarm_time->time.tm_min > RTC_MINUTES_VALUE_MAX))) || + ((p_alarm_time->hour_match) && + ((p_alarm_time->time.tm_hour < 0) || (p_alarm_time->time.tm_hour > RTC_HOURS_VALUE_MAX)))) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate alarm month and day of month of time type parameter + * Checking if month and day of month value is in the valid specified range, based on alarm enable bits. + * Month : 0 to 11. + * Day of month : 1 to 28/29/30/31. + * + * @param[in] p_alarm Pointer to rtc_alarm_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_date_validate (rtc_alarm_time_t * const p_alarm) +{ + fsp_err_t err; + err = FSP_SUCCESS; + + uint32_t num_days_month; + uint32_t day_of_month; + uint32_t month; + uint32_t year; + + day_of_month = (uint32_t) p_alarm->time.tm_mday; + month = (uint32_t) p_alarm->time.tm_mon; + + /* Alarm on year time unit is not supported */ + year = (uint32_t) p_alarm->time.tm_year; + + err = r_rtc_month_and_year_validate(year, month); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + if (p_alarm->mday_match) + { + /*For particular valid month, number of days in a month is updated */ + num_days_month = days_in_months[month]; + + /* Checking for February month and Conditions for Leap year. + * Year needs to be translated from time.h format */ + year += RTC_TIME_H_YEAR_OFFSET; + err = r_rtc_monthday_validate(day_of_month, &num_days_month, month, year); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + } + + return err; +} + +/*******************************************************************************************************************//** + * Validates the year and month paremeters. + * + * @param[in] year Year parameter. + * @param[in] month Month parameter. + **********************************************************************************************************************/ +static fsp_err_t r_rtc_month_and_year_validate (uint32_t year, uint32_t month) +{ + if ((year < RTC_YEAR_VALUE_MIN) || (year > RTC_YEAR_VALUE_MAX) || + (month < 0) || (month > RTC_MONTHS_VALUE_MAX)) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validates the day of month paremeter and the number of total days in a month. + * + * @param[in] day_of_month Day of month parameter. + * @param[in] num_days_month Total number of days in the month parameter. + * @param[in] month Month parameter. + * @param[in] year Year parameter. + **********************************************************************************************************************/ +static fsp_err_t r_rtc_monthday_validate (uint32_t day_of_month, + uint32_t * num_days_month, + uint32_t month, + uint32_t year) +{ + /* Checking for February month and Conditions for Leap year : Every fourth year is a leap year, + * except for century-years (divisible by 100) which must be also divisible by 400. */ + if (RTC_FEBRUARY_MONTH == month) + { + if ((0 == (year % 4U)) && (((year % RTC_DIV_MUL_100) != 0) || (0 == (year % RTC_DIV_400)))) + { + *num_days_month = RTC_LAST_DAY_OF_LEAP_FEB_MONTH; + } + } + + /* Checking for day of a month values for valid range */ + if ((day_of_month < RTC_FIRST_DAY_OF_A_MONTH) || (day_of_month > *num_days_month)) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + return FSP_SUCCESS; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_helper.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_helper.c new file mode 100644 index 000000000000..7ff95ab8c00b --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_helper.c @@ -0,0 +1,350 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +#include "bsp_rtc.h" +#include "r_rtc_w.h" +#include "r_rtc_w_helper.h" + +#define RTC_OVERFLOW 0xFFFFFFFFFULL /* Real RTC Counter 36bit */ +#define RTC_OVERFLOW_STACK_SIZE 256 + +#define _INT_MAX ((int) (~0U >> 1)) +#define _INT_MIN (-_INT_MAX - 1) +#define WDAY 1 /* to get day of week right */ + +/* Bias between 1900 (struct tm) and 1970 time_t. */ +#define _TBIAS_DAYS (70 * 365L + 17) +#define _TBIAS (_TBIAS_DAYS * 86400LU) + +/* macros */ +#define MONTAB(year) ((year) & 03 || (year) == 0 ? mos : lmos) + +/* from retmem.h */ +#define CLK2US(clk) ((((unsigned long long) clk) * 15625ULL) >> 9ULL) +#define CLK2MS(clk) ((CLK2US(clk)) / 1000ULL) +#define CLK2SEC(clk) (((unsigned long long) clk) >> 15ULL) +#define US2CLK(us) ((((unsigned long long) us) << 9ULL) / 15625ULL) +#define SEC2CLK(clk) (((unsigned long long) clk) << 15ULL) + +/* static data */ +static const short lmos[] = {0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335}; +static const short mos[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; + +static struct tm _Ttotm_ts = {0}; + +static void set_systimeoffset_to_rtm (unsigned long long offset) +{ + RTM_TIME_PTR->systime_offset = offset; +} + +static unsigned long long get_rtc_oldtime_from_rtm (void) +{ + return (unsigned long long) (RTM_TIME_PTR->rtc_oldtime); +} + +static unsigned long long get_systimeoffset_from_rtm (void) +{ + return (unsigned long long) RTM_TIME_PTR->systime_offset; +} + +static void set_rtc_oldtime_to_rtm (unsigned long long time) +{ + RTM_TIME_PTR->rtc_oldtime = time; +} + +void ra6w1_SetTzoff (long offset) +{ + RTM_TIME_PTR->__timezone = offset; +} + +long ra6w1_Tzoff (void) +{ + return RTM_TIME_PTR->__timezone; +} + +static int ra6w1_Daysto64 (int year, int mon) +{ + /* year >= 1900: leapdays from 1900 up to (not including) year plus + * days to start of month. + * year < 1900: leapdays backwards from 1900 down to (including) + * year (negative) plus days to start of month from year. */ + int days; + int y, ly; + + if (year >= 0) + { + y = year - 1; + ly = y + 300; + } + else + { + y = year; + ly = y - 100; + } + + days = y / 4; + days -= y / 100; + days += ly / 400; + + return days + MONTAB(year)[mon]; +} + +#define __isleap(y) (!((y) % 4) && (((y) % 100) || !((y) % 400))) + +static struct tm * ra6w1_Ttotm64 (struct tm * t, __time64_t secsarg, int isdst) +{ + /* Convert scalar time to time structure */ + int year; + long days; + signed long long secs; + + secsarg += _TBIAS; /* Changed to (wraparound) time since 1 Jan 1900 */ + + if (t == 0) + { + t = &_Ttotm_ts; + memset(t, 0x00, sizeof(struct tm)); + } + + t->tm_isdst = isdst; + + /* Loop to correct for DST */ + for (secs = (signed long long) secsarg; ; secs = (signed long long) secsarg + 3600) + { + /* If secs are negative we want to get a negative year that we then add + * month, day, etc to */ + days = (long) (secs / 86400); + secs = secs % 86400; + + if (secs < 0) + { + days--; + secs += 86400; + } + + t->tm_wday = (days + WDAY) % 7; + + if (t->tm_wday < 0) + { + t->tm_wday += 7; + } + + /* Determine year */ + long i; + year = days / 365; + + while (1) + { + i = ra6w1_Daysto64(year, 0) + 365L * year; + + if (days < i) + { + --year; /* Correct guess and recheck */ + continue; + } + + if (days <= (i + 365)) + { + break; + } + + if ((days == (i + 366)) && __isleap(year + 1900)) + { + break; + } + + ++year; + } + + days -= i; + t->tm_year = year; + t->tm_yday = days; + + { + /* Determine month */ + int mon; + const short * pm = MONTAB(year); + + for (mon = 12; days < pm[--mon]; ) + { + ; + } + + t->tm_mon = mon; + t->tm_mday = days - pm[mon] + 1; + } + + t->tm_hour = (int) (secs / 3600); + secs %= 3600; + t->tm_min = (int) (secs / 60); + t->tm_sec = (int) (secs % 60); + + return t; /* Loop only if <0 => 1 */ + } + + return NULL; +} + +void ra6w1_mktime64 (struct tm * t, __time64_t * now) +{ + /* Convert local time structure to scalar time */ + long cdays, csecs; + int mon, year, ymon; + __time64_t secs; + + ymon = t->tm_mon / 12; + mon = t->tm_mon - ymon * 12; + + if (mon < 0) + { + mon += 12, --ymon; + } + + if (((ymon < 0) && (t->tm_year < _INT_MIN - ymon)) || ((0 < ymon) && (_INT_MAX - ymon < t->tm_year))) + { + *now = ((__time64_t) (-1)); + + return; + } + + year = t->tm_year + ymon; + + /* Note that this is correct even with a 32 bit double. */ + + /* Calculate number of days. */ + cdays = ra6w1_Daysto64(year, mon) - 1; + cdays += 365L * year; + cdays += t->tm_mday; + + /* Calculate number of seconds. */ + cdays += t->tm_hour / 24; + csecs = 3600L * (t->tm_hour % 24); + cdays += t->tm_min / (24 * 60); + csecs += 60L * (t->tm_min % (24 * 60)); + cdays += t->tm_sec / 86400L; + csecs += t->tm_sec % 86400L; + + /* Change from 1900 into 1970 representation. */ + cdays -= _TBIAS_DAYS; + + /* Add them together to get seconds since 1970. */ + secs = (__time64_t) cdays * 86400L + (__time64_t) csecs; + + ra6w1_Ttotm64(t, secs, t->tm_isdst); + + if (0 < t->tm_isdst) + { + secs -= 3600; + } + + *now = (secs - (__time64_t) ra6w1_Tzoff()); +} + +static void ra6w1_time64_msec (__time64_t * p, __time64_t * cur_msec) +{ + unsigned long long time_ms; + unsigned long long rtc; + + /* rtc is retained when SW reset, reset when POR */ + rtc = R_BSP_SystemRtcCountGet(); + + time_ms = CLK2MS(rtc); /* Elapsed time from Power On in msec */ + + if (p != NULL) + { + /* msec : (time value to set) - (Elapsed time from Power On) */ + set_systimeoffset_to_rtm((unsigned long long) ((*p) * 1000ULL - time_ms)); + } + else if ((get_rtc_oldtime_from_rtm() != 0) && (get_rtc_oldtime_from_rtm() > time_ms)) /* Check Overflow */ + { + unsigned long long offset; + + offset = CLK2MS(RTC_OVERFLOW + 1ULL); // Overflow time + + /* RTC overflow 36bit + old offset = Elapsed time from Power On */ + set_systimeoffset_to_rtm(offset + get_systimeoffset_from_rtm()); /* newoffset */ + } + + set_rtc_oldtime_to_rtm(time_ms); + + time_ms = time_ms + (unsigned long long) get_systimeoffset_from_rtm(); + *cur_msec = time_ms; /* msec */ +} + +static void ra6w1_time64_sec (__time64_t * p, __time64_t * cur_sec) +{ + __time64_t cur_msec; + + ra6w1_time64_msec(p, &cur_msec); + if ((long long) cur_msec < 0) + { + *cur_sec = (cur_msec / 1000LL); /* sec */ + } + else + { + *cur_sec = (cur_msec / 1000ULL); /* sec */ + } +} + +void ra6w1_time64 (__time64_t * p, __time64_t * now) +{ + ra6w1_time64_sec(p, now); +} + +struct tm * ra6w1_gmtime64 (const __time64_t * tod) +{ + /* Convert to Greenwich Mean Time (UTC) */ + return ra6w1_Ttotm64(0, *tod, -1); +} + +struct tm * ra6w1_localtime64 (const __time64_t * tod) +{ + /* Convert to local time structure */ + return ra6w1_Ttotm64(0, *tod + (__time64_t) ra6w1_Tzoff(), 0); +} + +void __boottime (__time64_t * boottime) +{ + __time64_t time = 0; + __time64_t uptime = 0; + + if (get_systimeoffset_from_rtm() == 0) + { + *boottime = 0; + } + else + { + ra6w1_time64(NULL, &time); + uptime = __uptime(); + *boottime = time - uptime; + } +} + +void rtc_w_lock_take (void) +{ + rtc_w_instance_ctrl_t * rtc_w_ctrl = (rtc_w_instance_ctrl_t *) R_RTC_W_GetCtrl(); + + if (rtc_w_ctrl) + { + RTC_W_LOCK_TAKE(rtc_w_ctrl); + } +} + +void rtc_w_lock_give (void) +{ + rtc_w_instance_ctrl_t * rtc_w_ctrl = (rtc_w_instance_ctrl_t *) R_RTC_W_GetCtrl(); + + if (rtc_w_ctrl) + { + RTC_W_LOCK_GIVE(rtc_w_ctrl); + } +} diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_strftime.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_strftime.c new file mode 100644 index 000000000000..212ab92731ec --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_strftime.c @@ -0,0 +1,573 @@ +/* + * SPDX-License-Identifier: BSD-4.3TAHOE + * + * Copyright (c) 1989 The Regents of the University of California. + * All rights reserved. + * + * Copyright (c) 2011 The FreeBSD Foundation + * + * Portions of this software were developed by David Chisnall + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include +#include +#include + + +static char * _add(const char *, char *, const char *); +#include "r_rtc_w.h" + +#include +#include + +#define TYPE_SIGNED(type) (!((type) 0 < (type) -1)) +#define TYPE_BIT(type) (sizeof (type) * 8) +#define INT64_STRLEN_MAX 22 +#define INT_STRLEN_MAXIMUM(type) ((TYPE_BIT(type) - TYPE_SIGNED(type)) * 302 / 1000 \ + + 1 + TYPE_SIGNED(type)) + +#define isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0)) +#define isleap_sum(a, b) isleap((a) % 400 + (b) % 400) + +#define HOURSPERDAY 24 +#define DAYSPERWEEK 7 +#define DAYSPERNYEAR 365 +#define DAYSPERLYEAR 366 +#define MONSPERYEAR 12 + +#define TM_YEAR_BASE 1900 + +#define IN_SOME 1 +#define IN_THIS 2 +#define IN_ALL 3 + +struct lc_time_T { + const char * mon[MONSPERYEAR]; + const char * month[MONSPERYEAR]; + const char * wday[DAYSPERWEEK]; + const char * weekday[DAYSPERWEEK]; + const char * X_fmt; + const char * x_fmt; + const char * c_fmt; + const char * am; + const char * pm; + const char * date_fmt; +}; +#ifdef LOCALE_HOME +#include "sys/stat.h" +static struct lc_time_T localebuf; +static struct lc_time_T * _loc(void); +#define Locale _loc() +#endif /* defined LOCALE_HOME */ +#ifndef LOCALE_HOME +#define Locale (&C_time_locale) +#endif /* !defined LOCALE_HOME */ +static const struct lc_time_T C_time_locale = { + { + "Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" + }, { + "January", "February", "March", "April", "May", "June", + "July", "August", "September", "October", "November", "December" + }, { + "Sun", "Mon", "Tue", "Wed", + "Thu", "Fri", "Sat" + }, { + "Sunday", "Monday", "Tuesday", "Wednesday", + "Thursday", "Friday", "Saturday" + }, + /* X_fmt */ + "%H:%M:%S", + /* + ** x_fmt + ** C99 requires this format. + ** Using just numbers (as here) makes Quakers happier; + ** it's also compatible with SVR4. + */ + "%m/%d/%y", + /* + ** c_fmt + ** C99 requires this format. + ** Previously this code used "%D %X", but we now conform to C99. + ** Note that + ** "%a %b %d %H:%M:%S %Y" + ** is used by Solaris 2.3. + */ + "%a %b %e %T %Y", + /* am */ + "AM", + /* pm */ + "PM", + /* date_fmt */ + "%a %b %e %H:%M:%S %Z %Y" +}; + +char * _fmt(const char * format, const struct tm * t, char * pt, + const char * ptlim, int * warnp); + +static void ulltoa(unsigned long long value, char * buf, int radix) +{ + char tmp[64 + 1]; /* Lowest radix is 2, so 64-bits plus a null */ + char * p1 = tmp, * p2; + static const char xlat[] = "0123456789abcdefghijklmnopqrstuvwxyz"; + + if (radix < 2 || radix > 36) { + return; + + } + + do { + *p1++ = xlat[value % (unsigned)radix]; + } while((value /= (unsigned)radix)); + + for(p2 = buf; p1 != tmp; *p2++ = *--p1) { + /* Nothing to do */ + } + + *p2 = '\0'; +} + +static char * _add(const char * str, char * pt, const char * ptlim) +{ + while (pt < ptlim && (*pt = *str++) != '\0') { + ++pt; + } + + return pt; +} + +static char * _conv(int n, const char * format, char * pt, const char * ptlim) +{ + char buf[INT_STRLEN_MAXIMUM(int) + 1]; + + sprintf(buf, format, n); + return _add(buf, pt, ptlim); +} + +/* +** POSIX and the C Standard are unclear or inconsistent about +** what %C and %y do if the year is negative or exceeds 9999. +** Use the convention that %C concatenated with %y yields the +** same output as %Y, and that %Y contains at least 4 bytes, +** with more only if necessary. +*/ + +static char * lltoa(long long value, char * buf, int radix) +{ + char * save = buf; + + if (radix == 10 && value < 0) { + *buf++ = '-'; + value = -value; + } + + ulltoa((unsigned long long)value, buf, radix); + + return buf ? save : 0; +} + +static char * _yconv(int a, int b, char convert_top, char convert_yy, char * pt, const char * ptlim) +{ + register int lead; + register int trail; + +#define DIVISOR 100 + trail = a % DIVISOR + b % DIVISOR; + lead = a / DIVISOR + b / DIVISOR + trail / DIVISOR; + trail %= DIVISOR; + + if (trail < 0 && lead > 0) { + trail += DIVISOR; + --lead; + } else if (lead < 0 && trail > 0) { + trail -= DIVISOR; + ++lead; + } + + if (convert_top) { + if (lead == 0 && trail < 0) { + pt = _add("-0", pt, ptlim); + } else { + pt = _conv(lead, "%02d", pt, ptlim); + } + } + + if (convert_yy) { + pt = _conv(((trail < 0) ? -trail : trail), "%02d", pt, ptlim); + } + + return pt; +} + +char * _fmt(const char * format, const struct tm * t, char * pt, + const char * ptlim, int * warnp) +{ + for ( ; *format; ++format) { + if (*format == '%') { +label: + + switch (*++format) + { + case '\0': + --format; + break; + + case 'A': + pt = _add((t->tm_wday < 0 || t->tm_wday >= DAYSPERWEEK) ? "?" : Locale->weekday[t->tm_wday], pt, ptlim); + + continue; + + case 'a': + pt = _add((t->tm_wday < 0 || t->tm_wday >= DAYSPERWEEK) ? "?" : Locale->wday[t->tm_wday], pt, ptlim); + continue; + + case 'B': + pt = _add((t->tm_mon < 0 || t->tm_mon >= MONSPERYEAR) ? "?" : Locale->month[t->tm_mon], pt, ptlim); + continue; + + case 'b': + case 'h': + pt = _add((t->tm_mon < 0 || t->tm_mon >= MONSPERYEAR) ? "?" : Locale->mon[t->tm_mon], pt, ptlim); + continue; + + case 'C': + /* + ** %C used to do a... + ** _fmt("%a %b %e %X %Y", t); + ** ...whereas now POSIX 1003.2 calls for + ** something completely different. + ** (ado, 1993-05-24) + */ + pt = _yconv(t->tm_year, TM_YEAR_BASE, + true, false, pt, ptlim); + continue; + + case 'c': + { + int warn2 = IN_SOME; + + pt = _fmt(Locale->c_fmt, t, pt, ptlim, &warn2); + + if (warn2 == IN_ALL) { + warn2 = IN_THIS; + } + + if (warn2 > *warnp) { + *warnp = warn2; + } + } + + continue; + + case 'D': + pt = _fmt("%m/%d/%y", t, pt, ptlim, warnp); + continue; + + case 'd': + pt = _conv(t->tm_mday, "%02d", pt, ptlim); + continue; + + case 'E': + case 'O': + /* + ** C99 locale modifiers. + ** The sequences + ** %Ec %EC %Ex %EX %Ey %EY + ** %Od %oe %OH %OI %Om %OM + ** %OS %Ou %OU %OV %Ow %OW %Oy + ** are supposed to provide alternate + ** representations. + */ + goto label; + + case 'e': + pt = _conv(t->tm_mday, "%2d", pt, ptlim); + continue; + + case 'F': + pt = _fmt("%Y-%m-%d", t, pt, ptlim, warnp); + continue; + + case 'H': + pt = _conv(t->tm_hour, "%02d", pt, ptlim); + continue; + + case 'I': + pt = _conv((t->tm_hour % 12) ? (t->tm_hour % 12) : 12, "%02d", pt, ptlim); + continue; + + case 'j': + pt = _conv(t->tm_yday + 1, "%03d", pt, ptlim); + continue; + + case 'k': + /* + ** This used to be... + ** _conv(t->tm_hour % 12 ? + ** t->tm_hour % 12 : 12, 2, ' '); + ** ...and has been changed to the below to + ** match SunOS 4.1.1 and Arnold Robbins' + ** strftime version 3.0. That is, "%k" and + ** "%l" have been swapped. + ** (ado, 1993-05-24) + */ + pt = _conv(t->tm_hour, "%2d", pt, ptlim); + continue; + + case 'l': + /* + ** This used to be... + ** _conv(t->tm_hour, 2, ' '); + ** ...and has been changed to the below to + ** match SunOS 4.1.1 and Arnold Robbin's + ** strftime version 3.0. That is, "%k" and + ** "%l" have been swapped. + ** (ado, 1993-05-24) + */ + pt = _conv((t->tm_hour % 12) ? (t->tm_hour % 12) : 12, "%2d", pt, ptlim); + continue; + + case 'M': + pt = _conv(t->tm_min, "%02d", pt, ptlim); + continue; + + case 'm': + pt = _conv(t->tm_mon + 1, "%02d", pt, ptlim); + continue; + + case 'n': + pt = _add("\n", pt, ptlim); + continue; + + case 'p': + pt = _add((t->tm_hour >= (HOURSPERDAY / 2)) ? Locale->pm : Locale->am, pt, ptlim); + continue; + + case 'R': + pt = _fmt("%H:%M", t, pt, ptlim, warnp); + continue; + + case 'r': + pt = _fmt("%I:%M:%S %p", t, pt, ptlim, warnp); + continue; + case 'S': + pt = _conv(t->tm_sec, "%02d", pt, ptlim); + continue; + case 's': + { + struct tm tm; + char buf[INT64_STRLEN_MAX]; + ra6w1_time_t mkt; + tm = * t; + ra6w1_mktime64(&tm, &mkt); + { + char ull_str[21]; + if (TYPE_SIGNED(ra6w1_time_t)) { + lltoa((long long)mkt, ull_str, 10); + } else { + ulltoa(mkt, ull_str, 10); + } + sprintf(buf, "%s", ull_str); + } + pt = _add(buf, pt, ptlim); + } + + continue; + + case 'T': + pt = _fmt("%H:%M:%S", t, pt, ptlim, warnp); + continue; + + case 't': + pt = _add("\t", pt, ptlim); + continue; + + case 'U': + pt = _conv((t->tm_yday + DAYSPERWEEK - t->tm_wday) / DAYSPERWEEK, "%02d", pt, ptlim); + continue; + + case 'u': + /* + ** From Arnold Robbins' strftime version 3.0: + ** "ISO 8601: Weekday as a decimal number + ** [1 (Monday) - 7]" + ** (ado, 1993-05-24) + */ + pt = _conv((t->tm_wday == 0) ? DAYSPERWEEK : t->tm_wday, "%d", pt, ptlim); + continue; + + case 'V': /* ISO 8601 week number */ + case 'G': /* ISO 8601 year (four digits) */ + case 'g': /* ISO 8601 year (two digits) */ + /* + ** From Arnold Robbins' strftime version 3.0: "the week number of the + ** year (the first Monday as the first day of week 1) as a decimal number + ** (01-53)." + ** (ado, 1993-05-24) + ** + ** From by Markus Kuhn: + ** "Week 01 of a year is per definition the first week which has the + ** Thursday in this year, which is equivalent to the week which contains + ** the fourth day of January. In other words, the first week of a new year + ** is the week which has the majority of its days in the new year. Week 01 + ** might also contain days from the previous year and the week before week + ** 01 of a year is the last week (52 or 53) of the previous year even if + ** it contains days from the new year. A week starts with Monday (day 1) + ** and ends with Sunday (day 7). For example, the first week of the year + ** 1997 lasts from 1996-12-30 to 1997-01-05..." + ** (ado, 1996-01-02) + */ + { + int year; + int base; + int yday; + int wday; + int w; + + year = t->tm_year; + base = TM_YEAR_BASE; + yday = t->tm_yday; + wday = t->tm_wday; + + for ( ; ; ) { + int len; + int bot; + int top; + + len = isleap_sum(year, base) ? DAYSPERLYEAR : DAYSPERNYEAR; + /* + ** What yday (-3 ... 3) does + ** the ISO year begin on? + */ + bot = ((yday + 11 - wday) % DAYSPERWEEK) - 3; + + /* + ** What yday does the NEXT + ** ISO year begin on? + */ + top = bot - (len % DAYSPERWEEK); + + if (top < -3) { + top += DAYSPERWEEK; + } + + top += len; + + if (yday >= top) { + ++base; + w = 1; + break; + } + + if (yday >= bot) { + w = 1 + ((yday - bot) / DAYSPERWEEK); + break; + } + + --base; + yday += isleap_sum(year, base) ? DAYSPERLYEAR : DAYSPERNYEAR; + } + +#ifdef XPG4_1994_04_09 + + if ((w == 52 && t->tm_mon == TM_JANUARY) || (w == 1 && t->tm_mon == TM_DECEMBER)) { + w = 53; + } + +#endif /* defined XPG4_1994_04_09 */ + + if (*format == 'V') { + pt = _conv(w, "%02d", pt, ptlim); + } else if (*format == 'g') { + *warnp = IN_ALL; + pt = _yconv(year, base, false, true, pt, ptlim); + } else { + pt = _yconv(year, base, true, true, pt, ptlim); + } + } + + continue; + + case 'v': + /* + ** From Arnold Robbins' strftime version 3.0: + ** "date as dd-bbb-YYYY" + ** (ado, 1993-05-24) + */ + pt = _fmt("%e-%b-%Y", t, pt, ptlim, warnp); + continue; + + case 'W': + pt = _conv((t->tm_yday + DAYSPERWEEK - + (t->tm_wday ? + (t->tm_wday - 1) : + (DAYSPERWEEK - 1))) / DAYSPERWEEK, + "%02d", pt, ptlim); + continue; + + case 'w': + pt = _conv(t->tm_wday, "%d", pt, ptlim); + continue; + + case 'X': + pt = _fmt(Locale->X_fmt, t, pt, ptlim, warnp); + continue; + + case 'x': + { + int warn2 = IN_SOME; + + pt = _fmt(Locale->x_fmt, t, pt, ptlim, &warn2); + + if (warn2 == IN_ALL) { + warn2 = IN_THIS; + } + + if (warn2 > *warnp) { + *warnp = warn2; + } + } + + continue; + case 'y': + *warnp = IN_ALL; + pt = _yconv(t->tm_year, TM_YEAR_BASE, false, true, pt, ptlim); + continue; + case 'Y': + pt = _yconv(t->tm_year, TM_YEAR_BASE, true, true, pt, ptlim); + continue; + case '+': + pt = _fmt(Locale->date_fmt, t, pt, ptlim, warnp); + continue; + case '%': + /* + ** X311J/88-090 (4.12.3.5): if conversion char is + ** undefined, behavior is undefined. Print out the + ** character itself as printf(3) also does. + */ + default: + break; + } + } + if (pt == ptlim) { + break; + } + *pt++ = *format; + } + return pt; +} + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_time2string.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_time2string.c new file mode 100644 index 000000000000..817af6bc325e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_rtc_w/r_rtc_w_time2string.c @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_rtc_w.h" + +#include +#include + +char *_fmt(const char *format, const struct tm *const t, char *pt, + const char *const ptlim, int *warnp); + +#define Locale (&C_time_locale) + +#ifndef YEAR_2000_NAME +#define YEAR_2000_NAME "CHECK_STRFTIME_FORMATS_FOR_TWO_DIGIT_YEARS" +#endif /* !defined YEAR_2000_NAME */ + +#define IN_NONE 0 + +size_t ra6w1_strftime(char * ptr, size_t maxsize, const char * format, const struct tm * t) +{ + char * p; + int warn; + + warn = IN_NONE; + p = _fmt(((format == NULL) ? "%c" : format), t, ptr, ptr + maxsize, &warn); +#ifdef RUN_TIME_WARNINGS_ABOUT_YEAR_2000_PROBLEMS_THANK_YOU + + if (warn != IN_NONE && getenv(YEAR_2000_NAME) != NULL) { + printf("\n"); + + if (format == NULL) { + printf("NULL strftime format "); + } else { + printf("strftime format \"%s\" ", format); + } + + printf("yields only two digits of years in "); + + if (warn == IN_SOME) { + printf("some locales"); + } else if (warn == IN_THIS) { + printf("the current locale"); + } else { + printf("all locales"); + } + + printf("\n"); + } + +#endif /* defined RUN_TIME_WARNINGS_ABOUT_YEAR_2000_PROBLEMS_THANK_YOU */ + + if (p == ptr + maxsize) { + return 0; + } + + *p = '\0'; + return (size_t)(p - ptr); +} + +/* EOF */ diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_spi_w/r_spi_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_spi_w/r_spi_w.c new file mode 100644 index 000000000000..4b2da4c499ab --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_spi_w/r_spi_w.c @@ -0,0 +1,1803 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_w.h" + +#if CFG_PMGR + #include "rm_pmgr_w_instance.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "SPIW" in ASCII, used to determine if channel is open. */ +#define SPI_W_OPEN (0x53504957ULL) + +/** Channel is sleeping. */ +#define SPI_W_SLEEPING (0x5ULL) + +/** SPI base register access macro. */ +#define SPI_W_REG(channel) ((SPI_Type *) ((uint32_t) SPI + \ + ((uint32_t) SPI2 - (uint32_t) SPI) * (channel))) + +/** SPI enable register access macros. */ +#if defined(CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk) + #define SPI_W_SET_CLK_COM_REG_SPI1_ENABLE(val) CRG_COM->SET_CLK_COM_REG_b.SPI_ENABLE = (val) + #define SPI_W_SET_CLK_COM_REG_SPI2_ENABLE(val) CRG_COM->SET_CLK_COM_REG_b.SPI2_ENABLE = (val) + #define SPI_W_SET_CLK_COM_REG_SPI3_ENABLE(val) CRG_COM->SET_CLK_COM_REG_b.SPI3_ENABLE = (val) +#elif defined(CRG_PER_CLK_COM_REG_SPI_ENABLE_Msk) + #define SPI_W_SET_CLK_COM_REG_SPI1_ENABLE(val) CRG_PER->SET_CLK_COM_REG_b.SPI_ENABLE = (val) + #define SPI_W_SET_CLK_COM_REG_SPI2_ENABLE(val) CRG_PER->SET_CLK_COM_REG_b.SPI2_ENABLE = (val) + #define SPI_W_SET_CLK_COM_REG_SPI3_ENABLE(val) CRG_PER->SET_CLK_COM_REG_b.SPI3_ENABLE = (val) +#endif + +/** SPI reset register access macros. */ +#if defined(CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk) + #define SPI_W_RESET_CLK_COM_REG_SPI1_ENABLE(val) CRG_COM->RESET_CLK_COM_REG_b.SPI_ENABLE = (val) + #define SPI_W_RESET_CLK_COM_REG_SPI2_ENABLE(val) CRG_COM->RESET_CLK_COM_REG_b.SPI2_ENABLE = (val) + #define SPI_W_RESET_CLK_COM_REG_SPI3_ENABLE(val) CRG_COM->RESET_CLK_COM_REG_b.SPI3_ENABLE = (val) +#elif defined(CRG_PER_RESET_CLK_COM_REG_SPI_ENABLE_Msk) + #define SPI_W_RESET_CLK_COM_REG_SPI1_ENABLE(val) CRG_PER->RESET_CLK_COM_REG_b.SPI_ENABLE = (val) + #define SPI_W_RESET_CLK_COM_REG_SPI2_ENABLE(val) CRG_PER->RESET_CLK_COM_REG_b.SPI2_ENABLE = (val) + #define SPI_W_RESET_CLK_COM_REG_SPI3_ENABLE(val) CRG_PER->RESET_CLK_COM_REG_b.SPI3_ENABLE = (val) +#endif + +/** SPI clock control register access macros. */ +#if defined(CRG_TOP_SPI_CLK_CTRL_REG_SPI_CLK_EN_Msk) + #define SPI_W_SPI_CLK_CTRL_REG_SPI1_CLK_EN(val) CRG_TOP->SPI_CLK_CTRL_REG_b.SPI_CLK_EN = (val) + #define SPI_W_SPI_CLK_CTRL_REG_SPI2_CLK_EN(val) CRG_TOP->SPI_CLK_CTRL_REG_b.SPI2_CLK_EN = (val) + #define SPI_W_SPI_CLK_CTRL_REG_SPI3_CLK_EN(val) CRG_TOP->SPI_CLK_CTRL_REG_b.SPI3_CLK_EN = (val) +#else + #define SPI_W_SPI_CLK_CTRL_REG_SPI1_CLK_EN(val) do {} while (0) + #define SPI_W_SPI_CLK_CTRL_REG_SPI2_CLK_EN(val) do {} while (0) + #define SPI_W_SPI_CLK_CTRL_REG_SPI3_CLK_EN(val) do {} while (0) +#endif + +#if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) + #define SPI_W_TRANSFER_MAX_LENGTH (0x10000) +#elif (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + #define SPI_W_TRANSFER_MAX_LENGTH (0xFFFF) +#endif + +#define SPI_W_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_W_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_W_CLK_DIV_SETTING_MASK (0x7FU) ///< Bit mask for SPI_CLK_DIV setting. +#define SPI_W_CLK_DIV_SETTING_MIN_DIV (127U) ///< SPI_CLK_DIV setting for Minimum SPI CLK divider. +#define SPI_W_CLK_MAX_DIV (254U) ///< Maximum SPI CLK divider. +#define SPI_W_CLK_MIN_DIV (1UL) ///< Minimum SPI CLK divider. + +/* SPI_CONFIG_REG Bit Field Definitions */ +#define SPI_W_CONFIG_REG_CPHA_POS (0U) ///< Clock Phase setting offset. +#define SPI_W_CONFIG_REG_CPOL_POS (1U) ///< Clock Polarity setting offset. + +#define SPI_W_1_WORD (0x000000FFU) ///< Mask value for 8-bit width. +#define SPI_W_2_WORDS (0x0000FFFFU) ///< Mask value for 16-bit width. +#define SPI_W_4_WORDS (0xFFFFFFFFU) ///< Mask value for 32-bit width. + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * spi_w_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_w_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + +#if CFG_PMGR + +/** SPI sleep context required by PMGR */ + +typedef struct st_spi_w_pmgr_context +{ + pmgr_instance_info_t pmgr_info; + pmgr_callback_args_t clbk_args; + pmgr_w_notifier_extend_t pmgr_notifier_ext; + spi_w_instance_ctrl_t * p_ctrl; +} spi_w_pmgr_context_t; +#endif + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +static fsp_err_t r_spi_w_transfer_config(spi_cfg_t const * const p_cfg); +static void r_spi_w_hw_config(spi_w_instance_ctrl_t * p_ctrl); +static void r_spi_w_nvic_config(spi_w_instance_ctrl_t * p_ctrl); +static void r_spi_w_bit_width_config(spi_w_instance_ctrl_t * p_ctrl); +static fsp_err_t r_spi_w_start_transfer(spi_w_instance_ctrl_t * p_ctrl); +static fsp_err_t r_spi_w_write_read_common(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width, + uint32_t const fast_max_count); + +static void r_spi_w_receive(spi_w_instance_ctrl_t * p_ctrl); +static void r_spi_w_transmit(spi_w_instance_ctrl_t * p_ctrl); + +#if (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) || !BSP_MCU_GROUP_RA6W1 +static void r_spi_w_transfer_zero_pad_restore(spi_w_instance_ctrl_t * p_ctrl); + +#endif +static void r_spi_w_transfer_end(spi_w_instance_ctrl_t * p_ctrl); +static void r_spi_w_call_callback(spi_w_instance_ctrl_t * p_ctrl, spi_event_t event); + +#if CFG_PMGR +static fsp_err_t r_spi_w_subscribe_for_pmgr_notifications(spi_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_spi_w_unsubscribe_from_pmgr_notifications(spi_w_instance_ctrl_t * const p_ctrl); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +#if (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) +extern void spi_w_rx_dmac_callback(spi_w_instance_ctrl_t * p_ctrl); +extern void spi_w_tx_dmac_callback(spi_w_instance_ctrl_t const * const p_ctrl); + +#endif + +void spi_w_gen_isr(void); + +#if !BSP_MCU_GROUP_RA6W1 +void spi_w_txi_isr(void); +void spi_w_rxi_isr(void); +void spi_w_tei_isr(void); +void spi_w_eri_isr(void); + +#endif + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* SPI implementation of SPI interface. */ +const spi_api_t g_spi_on_spi_w = +{ + .open = R_SPI_W_Open, + .read = R_SPI_W_Read, + .write = R_SPI_W_Write, + .writeRead = R_SPI_W_WriteRead, + .close = R_SPI_W_Close, + .callbackSet = R_SPI_W_CallbackSet +}; + +#if CFG_PMGR + +/* Keep SPI PMGR context here */ +static spi_w_pmgr_context_t g_spi_pmgr_context[BSP_FEATURE_SPI_MAX_CHANNEL]; +#endif + +/*******************************************************************************************************************//** + * @addtogroup SPI_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This functions initializes a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Configures the peripheral registers according to the configuration. + * - Initialize the control structure for use in other @ref SPI_API functions. + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * @param[in] p_cfg Configuration structure which contains all the user provided configurations. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ALREADY_OPEN Instance was already initialized. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + * @retval FSP_ERR_UNSUPPORTED A requested setting is not possible on this device with the current build + * configuration. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open + * @note This function is reentrant. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_api_ctrl; + +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_W_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_extend); + + spi_w_extended_cfg_t * p_extend = (spi_w_extended_cfg_t *) p_cfg->p_extend; + + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + FSP_ASSERT(bsp_pd_is_up_check(BSP_PD_COM)); + #endif + + FSP_ERROR_RETURN(BSP_FEATURE_SPI_MAX_CHANNEL > p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(BSP_FEATURE_SPI_VALID_CHANNEL_MASK & (1 << (p_cfg->channel + SPI_W_CHANNEL_OFFSET)), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + #if !BSP_FEATURE_TRANSFER_HAS_DTC + FSP_ASSERT(1 != SPI_W_CFG_TRANSFER_API_SUPPORT); + #endif + + FSP_ASSERT(0 <= p_extend->gen_irq); + + #if !BSP_MCU_GROUP_RA6W1 + if (SPI_MODE_MASTER == p_cfg->operating_mode) + { + FSP_ASSERT(0 <= p_cfg->tei_irq); + } + + #if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (p_cfg->p_transfer_rx) + { + FSP_ASSERT(0 <= p_cfg->rxi_irq); + } + + if (p_cfg->p_transfer_tx) + { + FSP_ASSERT(0 <= p_cfg->txi_irq); + } + #endif + #endif + + #if SPI_W_CFG_TRANSMIT_FROM_RXI_ISR + + /* When the TXI Interrupt is handled in the RXI ISR, a TX DTC instance must be present if there is a + * RX DTC instance present otherwise the TXI Interrupts will not be processed. */ + if (p_cfg->p_transfer_rx) + { + FSP_ERROR_RETURN(NULL != p_cfg->p_transfer_tx, FSP_ERR_UNSUPPORTED); + } + #endif + + #if BSP_MCU_GROUP_RA6W1 + + /* When TX DMAC is used, RX DMAC must be used because the reception process cannot be completed in time. */ + if (p_cfg->p_transfer_tx) + { + FSP_ASSERT(NULL != p_cfg->p_transfer_rx); + } + #endif + + /* Checking for unsupported configurations. */ + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + FSP_ASSERT(SPI_W_CS_SELECT_CS0 == p_extend->cs_select); + FSP_ASSERT(SPI_W_CAPTURE_CURRENT_EDGE == p_extend->cap_edge); + } +#endif + + /* Configure transfers if they are provided in p_cfg. */ + err = r_spi_w_transfer_config(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get the register address of the channel. */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_regs = SPI_W_REG(p_ctrl->p_cfg->channel); + + /* Configure hardware registers according to the r_spi_api configuration structure. */ + r_spi_w_hw_config(p_ctrl); + + /* Enable interrupts in NVIC. */ + r_spi_w_nvic_config(p_ctrl); + +#if CFG_PMGR + r_spi_w_subscribe_for_pmgr_notifications(p_ctrl); +#endif + + p_ctrl->open = SPI_W_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * This function receives data from a SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI read operation. + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * @param[out] p_dest Reference to receiving buffer. + * @param[in] length No of transfers. + * @param[in] bit_width Data frame width. + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or destination parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_dest); +#endif + + return r_spi_w_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width, 0); +} + +/*******************************************************************************************************************//** + * This function transmits data to a SPI device. Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI write operation. + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * @param[in] p_src Reference to transmitting buffer. + * @param[in] length No of transfers. + * @param[in] bit_width Data frame width. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or source parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_src); +#endif + + return r_spi_w_write_read_common(p_api_ctrl, p_src, NULL, length, bit_width, 0); +} + +/*******************************************************************************************************************//** + * This function simultaneously transmits and receive data. Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI writeRead operation. + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * @param[in] p_src Reference to transmitting buffer. + * @param[out] p_dest Reference to receiving buffer. + * @param[in] length No of transfers. + * @param[in] bit_width Data frame width. + * + * @retval FSP_SUCCESS WriteRead operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control, source or destination parameters or + * transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + *********************************************************************************************************************/ +fsp_err_t R_SPI_W_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); +#endif + + return r_spi_w_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width, 0); +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * @param[in] p_callback Pointer to user callback function. + * @param[in] p_context User defined context passed to callback function. + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_api_ctrl; + +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SPI_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close. + * + * Disables SPI operations by disabling the SPI bus. + * - Disables the SPI peripheral. + * - Disables all the associated interrupts. + * - Update control structure so it will not work with @ref SPI_API functions. + * + * @param[in] p_api_ctrl Pointer to the instance control structure. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION A required pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_Close (spi_ctrl_t * const p_api_ctrl) +{ + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_api_ctrl; + +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_ctrl->p_cfg); + FSP_ASSERT(NULL != p_ctrl->p_cfg->p_extend); +#endif + + spi_w_extended_cfg_t * p_extend = ((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + p_ctrl->open = 0U; + +#if CFG_PMGR + r_spi_w_unsubscribe_from_pmgr_notifications(p_ctrl); +#endif + +#if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) || (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable interrupts in NVIC. */ + R_BSP_IrqDisable(p_extend->gen_irq); + +#if !BSP_MCU_GROUP_RA6W1 + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + if (BSP_IRQ_DISABLED != p_ctrl->p_cfg->eri_ipl) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + } + + #if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (p_ctrl->p_cfg->p_transfer_rx) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + } + + if (p_ctrl->p_cfg->p_transfer_tx) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + } + #endif +#endif + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPI_CTRL_REG = 0U; + + /* Disable the Clock for SPI */ + if (0U == p_ctrl->p_cfg->channel) + { + SPI_W_RESET_CLK_COM_REG_SPI1_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI1_CLK_EN(0U); + } + else if (1U == p_ctrl->p_cfg->channel) + { + SPI_W_RESET_CLK_COM_REG_SPI2_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI2_CLK_EN(0U); + } + +#if !BSP_MCU_GROUP_RA6W1 + else if (2U == p_ctrl->p_cfg->channel) + { + SPI_W_RESET_CLK_COM_REG_SPI3_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI3_CLK_EN(0U); + } +#endif + else + { + /* Nothing TODO */ + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates the SPI_CLOCK_REG register value (the closest quantized value) for a desired bitrate. + * If the desired bitrate is faster than the maximum bitrate, then the bitrate is set to the + * maximum bitrate. If the desired bitrate is slower than the minimum bitrate, an error is returned. + * + * @param[in] bitrate Desired bitrate. + * @param[out] spck_div Memory location to store bitrate register settings. + * @param[in] channel Selected channel. + * + * @retval FSP_SUCCESS Valid clkdiv value was calculated. + * @retval FSP_ERR_UNSUPPORTED Bitrate is not achievable. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_CalculateBitrate (uint32_t bitrate, uint8_t * spck_div, uint8_t channel) +{ +#if !BSP_MCU_GROUP_RA6W3 + FSP_PARAMETER_NOT_USED(channel); +#endif + fsp_err_t err = FSP_SUCCESS; + +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != spck_div); + #if BSP_MCU_GROUP_RA6W3 + FSP_ASSERT(BSP_FEATURE_SPI_MAX_CHANNEL > channel); + #endif +#endif + + /* Checking for division by zero. */ + if (0U == bitrate) + { + err = FSP_ERR_UNSUPPORTED; + + return err; + } + +#if BSP_MCU_GROUP_RA6W3 + + /* desired_divider = Smallest integer greater than or equal to DIV1 / (SPIx_CORE_CLK_DIV + (1 or 2)) / bitrate. */ + uint32_t sys_clk = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_SYS_CLK); + uint32_t spi_core_clock_div = (CRG_TOP->SPI_CLK_CTRL_REG >> (channel * 4)) & 0x7; + spi_core_clock_div = (spi_core_clock_div <= 1) ? (spi_core_clock_div + 1) : (spi_core_clock_div + 2); + uint32_t desired_divider = sys_clk / (bitrate * spi_core_clock_div); +#elif BSP_MCU_GROUP_RA6W1 + + /* desired_divider = Smallest integer greater than or equal to SPI_CLK / bitrate. */ + uint32_t spi_clk = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_SPI); + uint32_t desired_divider = spi_clk / bitrate; +#else + + /* desired_divider = Smallest integer greater than or equal to BSP_DIVN_FREQ_HZ(32Mhz) / bitrate. */ + uint32_t desired_divider = BSP_DIVN_FREQ_HZ / bitrate; +#endif + + /* Can't achieve bitrate slower than desired. */ + if (SPI_W_CLK_MAX_DIV < desired_divider) + { + err = FSP_ERR_UNSUPPORTED; + } + else if (SPI_W_CLK_MIN_DIV >= desired_divider) + { + /* Configure max bitrate. */ + *spck_div = SPI_W_CLK_DIV_SETTING_MIN_DIV; + } + else + { + *spck_div = ((uint8_t) ((desired_divider >> 1U) - 1U)) & SPI_W_CLK_DIV_SETTING_MASK; + } + + return err; +} + +#if SPI_W_CFG_FAST_MODE_ENABLE + +/*******************************************************************************************************************//** + * This function receives data from a SPI device in fast mode. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI read operation. + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or destination parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_W_FastRead (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + uint32_t const max_count, + spi_bit_width_t const bit_width) +{ + #if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(0U != max_count); + #endif + + return r_spi_w_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width, max_count); +} + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup SPI_W) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the given transfer instances for receiving and transmitting data without CPU intervention. + * + * @param[in] p_cfg Configuration structure with references to receive and transmit transfer instances. + * + * @retval FSP_SUCCESS The given transfer instances were configured successfully. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally calls + * @ref transfer_api_t::open. + **********************************************************************************************************************/ +static fsp_err_t r_spi_w_transfer_config (spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + +#if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) || (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + const transfer_instance_t * p_transfer_tx = p_cfg->p_transfer_tx; + void * p_spdr_tx = (void *) &(SPI_W_REG(p_cfg->channel)->SPI_FIFO_WRITE_REG); + if (NULL != p_transfer_tx) + { + p_transfer_tx->p_cfg->p_info->transfer_settings_word = SPI_W_TX_TRANSFER_SETTINGS; + p_transfer_tx->p_cfg->p_info->p_dest = p_spdr_tx; + p_transfer_tx->p_cfg->p_info->length = 1U; + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + const transfer_instance_t * p_transfer_rx = p_cfg->p_transfer_rx; + void * p_spdr_rx = (void *) &(SPI_W_REG(p_cfg->channel)->SPI_FIFO_READ_REG); + if (NULL != p_transfer_rx) + { + p_transfer_rx->p_cfg->p_info->transfer_settings_word = SPI_W_RX_TRANSFER_SETTINGS; + p_transfer_rx->p_cfg->p_info->p_src = p_spdr_rx; + p_transfer_rx->p_cfg->p_info->length = 1U; + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + + if ((FSP_SUCCESS != err) && p_transfer_tx) + { + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Hardware configuration for settings given by the configuration structure. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_hw_config (spi_w_instance_ctrl_t * p_ctrl) +{ + uint32_t ctrl_reg = 0U; + uint32_t config_reg = 0U; + uint32_t clock_reg = 0U; + uint32_t fifo_config_reg = 0U; + + /* Configure operating mode setting. */ + config_reg |= (uint32_t) ((SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode) << SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos); + + /* Configure Clock Phase setting. */ + config_reg |= (uint32_t) ((SPI_CLK_PHASE_EDGE_EVEN == p_ctrl->p_cfg->clk_phase) << SPI_W_CONFIG_REG_CPHA_POS); + + /* Configure Clock Polarity setting. */ + config_reg |= (uint32_t) ((SPI_CLK_POLARITY_HIGH == p_ctrl->p_cfg->clk_polarity) << SPI_W_CONFIG_REG_CPOL_POS); + + spi_w_extended_cfg_t * p_extend = ((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + /* Configure Full Duplex Setting. */ + ctrl_reg |= (SPI_SPI_CTRL_REG_SPI_RX_EN_Msk | SPI_SPI_CTRL_REG_SPI_TX_EN_Msk); + +#if (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + /* Configure DMA TX Enable Setting. */ + ctrl_reg |= SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk; + } + + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + /* Configure DMA RX Enable Setting. */ + ctrl_reg |= SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk; + } +#endif + + /* Configure byte swapping for 16/32-Bit mode. */ + ctrl_reg |= (uint32_t) ((SPI_W_BYTE_SWAP_ENABLE == p_extend->byte_swap) << SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos); + + /* Configure capture clock edge. */ + ctrl_reg |= (uint32_t) ((SPI_W_CAPTURE_NEXT_EDGE == p_extend->cap_edge) << + SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos); + + /* Configure the Bitrate Division Setting */ + clock_reg |= (uint32_t) (p_extend->spck_div << SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos); + + /* Power up the SPI module. */ + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Enable the Clock for SPI */ +#if BSP_MCU_GROUP_RA6W1 + CRG_TOP->CLK_AMBA_REG |= CRG_TOP_CLK_AMBA_REG_SPI_CLK_ENABLE_Msk; + CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_PLL_SPI_ENABLE_Msk; +#endif + + if (0U == p_ctrl->p_cfg->channel) + { + SPI_W_SET_CLK_COM_REG_SPI1_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI1_CLK_EN(1U); + } + else if (1U == p_ctrl->p_cfg->channel) + { + SPI_W_SET_CLK_COM_REG_SPI2_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI2_CLK_EN(1U); + } + +#if !BSP_MCU_GROUP_RA6W1 + else if (2U == p_ctrl->p_cfg->channel) + { + SPI_W_SET_CLK_COM_REG_SPI3_ENABLE(1U); + SPI_W_SPI_CLK_CTRL_REG_SPI3_CLK_EN(1U); + } +#endif + else + { + /* Nothing TODO */ + } + + FSP_CRITICAL_SECTION_EXIT; + + /* Configure RX/TX FIFO threshold level. */ + fifo_config_reg = + ((p_extend->rx_fifo_lvl_thres << SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos) & + SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk); + fifo_config_reg |= + ((p_extend->tx_fifo_lvl_thres << SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos) & + SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk); + + /* Clear the status and disable SPI. */ + p_ctrl->p_regs->SPI_CTRL_REG = SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk; + + /* Write registers */ + p_ctrl->p_regs->SPI_CONFIG_REG = config_reg; + p_ctrl->p_regs->SPI_CLOCK_REG = clock_reg; + p_ctrl->p_regs->SPI_FIFO_CONFIG_REG = fifo_config_reg; + p_ctrl->p_regs->SPI_IRQ_MASK_REG = 0U; + p_ctrl->p_regs->SPI_CS_CONFIG_REG = 0U; + p_ctrl->p_regs->SPI_CTRL_REG = ctrl_reg; +} + +/*******************************************************************************************************************//** + * Enable Interrupts in the NVIC. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_nvic_config (spi_w_instance_ctrl_t * p_ctrl) +{ + spi_w_extended_cfg_t * p_extend = ((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + R_BSP_IrqCfgEnable(p_extend->gen_irq, p_extend->gen_ipl, p_ctrl); + +#if !BSP_MCU_GROUP_RA6W1 + if (BSP_IRQ_DISABLED != p_ctrl->p_cfg->tei_ipl) + { + /* Note tei_irq is not enabled until the last data frame is transferred. */ + R_BSP_IrqCfg(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->tei_ipl, p_ctrl); + } + if (BSP_IRQ_DISABLED != p_ctrl->p_cfg->eri_ipl) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl); + } + + #if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (p_ctrl->p_cfg->p_transfer_rx) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->rxi_ipl, p_ctrl); + } + + if (p_ctrl->p_cfg->p_transfer_tx) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->txi_ipl, p_ctrl); + } + #endif +#endif +} + +/*******************************************************************************************************************//** + * Setup the bit width configuration for a transfer. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_bit_width_config (spi_w_instance_ctrl_t * p_ctrl) +{ + uint32_t ctrl_reg = p_ctrl->p_regs->SPI_CTRL_REG; + + /* Disable SPI. */ + p_ctrl->p_regs->SPI_CTRL_REG = 0U; /* SPI_EN = 0 */ + + /* Configure data length based on the selected bit width. */ + p_ctrl->p_regs->SPI_CONFIG_REG_b.SPI_WORD_LENGTH = p_ctrl->bit_width; + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths > 16 bits */ + { + p_ctrl->mask_width = (SPI_W_4_WORDS >> (SPI_BIT_WIDTH_32_BITS - p_ctrl->bit_width)); + p_ctrl->wordsize = 4; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width <= 8 bits */ + { + p_ctrl->mask_width = (SPI_W_1_WORD >> (SPI_BIT_WIDTH_8_BITS - p_ctrl->bit_width)); + p_ctrl->wordsize = 1; + } + else /* 8 bits < Bit Width <= 16 bits */ + { + p_ctrl->mask_width = (SPI_W_2_WORDS >> (SPI_BIT_WIDTH_16_BITS - p_ctrl->bit_width)); + p_ctrl->wordsize = 2; + } + + /* Restore SPI_EN. */ + p_ctrl->p_regs->SPI_CTRL_REG = ctrl_reg; +} + +#if (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) || !BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************//** + * A helper function to assist on cleaning up data by masking them. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_transfer_zero_pad_restore (spi_w_instance_ctrl_t * p_ctrl) +{ + if ((SPI_BIT_WIDTH_8_BITS != p_ctrl->bit_width) && (SPI_BIT_WIDTH_16_BITS != p_ctrl->bit_width) && + (SPI_BIT_WIDTH_32_BITS != p_ctrl->bit_width) && (NULL != p_ctrl->p_rx_data)) + { + uint16_t rx_count; + for (rx_count = 0U; rx_count < p_ctrl->count; rx_count++) + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths > 16 bits */ + { + uint32_t * p32 = p_ctrl->p_rx_data; + *(p32 + rx_count) &= (uint32_t) p_ctrl->mask_width; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width <= 8 bits */ + { + uint8_t * p8 = p_ctrl->p_rx_data; + *(p8 + rx_count) &= (uint8_t) p_ctrl->mask_width; + } + else /* 8 bits < Bit Width <= 16 bits */ + { + uint16_t * p16 = p_ctrl->p_rx_data; + *(p16 + rx_count) &= (uint16_t) p_ctrl->mask_width; + } + } + } +} + +#endif + +/*******************************************************************************************************************//** + * A helper function to assist on deasserting slave, disabling SPI and call callback to signal the end of the transfer. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_transfer_end (spi_w_instance_ctrl_t * p_ctrl) +{ + /* Deassert the Slave Select. */ + p_ctrl->p_regs->SPI_CS_CONFIG_REG = 0U; + + /* Disable the SPI Transfer. */ +#if SPI_W_CFG_FAST_MODE_ENABLE + if (!((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->skip_disable) + { + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 0U; + } + +#else + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 0U; +#endif + + /* Signal that a transfer has completed. */ + r_spi_w_call_callback((spi_w_instance_ctrl_t *) p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); +} + +/*******************************************************************************************************************//** + * Initiates a SPI transfer by setting the SPI_EN bit in SPI_CTRL_REG. + * + * @param[in] p_ctrl Pointer to control structure. + * + * @retval FSP_SUCCESS Transfer was started successfully. + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_NOT_OPEN The instance has not been initialized. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally calls + * @ref transfer_api_t::reconfigure. + * Note: When not using the DMAC to transmit, this function pre-loads the SPI shift-register and shift-register-buffer + * instead of waiting for the transmit buffer empty interrupt. This is required when transmitting from the + * Receive Buffer Full interrupt, but it does not interfere with transmitting when using the transmit buffer empty + * interrupt. + **********************************************************************************************************************/ +static fsp_err_t r_spi_w_start_transfer (spi_w_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t irq_mask_reg = 0U; + uint32_t tx_data; + spi_w_extended_cfg_t * p_extend = ((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + /* Clear the status. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_FIFO_RESET = 1U; + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_FIFO_RESET = 0U; + +#if !BSP_MCU_GROUP_RA6W1 + + /* Enable Receive dedicated interrupt. */ + irq_mask_reg = SPI_SPI_IRQ_MASK_REG_SPI_RX_IRQ_MASK_Msk; + + /* Enable Transmit end dedicated interrupt (TX FIFO empty). */ + irq_mask_reg |= SPI_SPI_IRQ_MASK_REG_SPI_TXE_IRQ_MASK_Msk; + + /* Enable Error dedicated interrupt (RX FIFO overflow). */ + irq_mask_reg |= SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FIFO_OVFL_Msk; + + /* Unmask Idle decicated interrupt (transastion completion for Master). */ + /* Note: Idle Interrupt (tei_irq) is not enabled until the last data frame is transferred. */ + irq_mask_reg |= SPI_SPI_IRQ_MASK_REG_SPI_TXR_IRQ_MASK_Msk; +#endif + + if (NULL == p_ctrl->p_cfg->p_transfer_rx) + { + /* Enable Receive Buffer Full interrupt. */ + irq_mask_reg |= SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk; + } + + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* Assert the Slave Select. */ + p_ctrl->p_regs->SPI_CS_CONFIG_REG = (uint32_t) p_extend->cs_select; + } + + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + { + /* Only the first word of the Slave transmission data must be set to SPI_TXBUFFER_FORCE_REG register, + * otherwise the transmission will be delayed. */ + if (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode) + { + if (NULL == p_ctrl->p_tx_data) + { + /* Transmit zero if no tx buffer present. */ + tx_data = 0U; + } + else + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths > 16 bits */ + { + tx_data = *((uint32_t *) p_ctrl->p_tx_data); + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width <= 8 bits */ + { + tx_data = (uint32_t) (*((uint8_t *) p_ctrl->p_tx_data)); + } + else /* 8 bits < Bit Width <= 16 bits */ + { + tx_data = (uint32_t) (*((uint16_t *) p_ctrl->p_tx_data)); + } + + p_ctrl->p_tx_data = (void *) ((uint8_t *) p_ctrl->p_tx_data + p_ctrl->wordsize); + } + + p_ctrl->p_regs->SPI_TXBUFFER_FORCE_REG = tx_data; + p_ctrl->tx_count++; + } + } + + /* Must call transmit to kick off transfer when transmitting. + * Multiple transmits significantly improves slave mode performance in high bitrate. */ + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + { + r_spi_w_transmit(p_ctrl); + } + +#if SPI_W_CFG_TRANSMIT_FROM_RXI_ISR + + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + { + /* Set IRQ Mask */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG = irq_mask_reg; + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 1U; + + return err; + } +#endif + + if (((NULL != p_ctrl->p_tx_data) || (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode)) && + (NULL == p_ctrl->p_cfg->p_transfer_tx)) + { + /* Enable the TX buffer empty interrupt. */ + irq_mask_reg |= SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk; + } + +#if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) || (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + + /* Only the first word of the Slave transmission data must be set to SPI_TXBUFFER_FORCE_REG register, + * otherwise the transmission will be delayed. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && (NULL != p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src)) + { + if (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode) + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + tx_data = *((uint32_t *) p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src); + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + tx_data = (uint32_t) (*((uint8_t *) p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src)); + } + else + { + tx_data = (uint32_t) (*((uint16_t *) p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src)); + } + + if (TRANSFER_ADDR_MODE_FIXED != + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = + (void *) ((uint8_t *) p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src + p_ctrl->wordsize); + } + + p_ctrl->p_regs->SPI_TXBUFFER_FORCE_REG = tx_data; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length--; + } + + if (0U != p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length) + { + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->enable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + } +#endif + + /* Set IRQ Mask */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG = irq_mask_reg; + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 1U; + + return err; +} + +/*******************************************************************************************************************//** + * Configures the driver state and initiates a SPI transfer for all modes of operation. + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_src Buffer to transmit data from. + * @param[out] p_dest Buffer to store received data in. + * @param[in] length Number of transfers. + * @param[in] bit_width Data frame size (8-Bit, 16-Bit, 32-Bit). + * @param[in] fast_max_count Maximum read count used only for R_SPI_W_FastRead. + * + * @retval FSP_SUCCESS Transfer was started successfully. + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_NOT_OPEN The instance has not been initialized. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally calls + * @ref transfer_api_t::reconfigure. + **********************************************************************************************************************/ +static fsp_err_t r_spi_w_write_read_common (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width, + uint32_t const fast_max_count) +{ + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; +#if !SPI_W_CFG_FAST_MODE_ENABLE + FSP_PARAMETER_NOT_USED(fast_max_count); +#endif + +#if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0U != length); + + #if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) || (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) || (NULL != p_ctrl->p_cfg->p_transfer_tx)) + { + FSP_ASSERT(SPI_W_TRANSFER_MAX_LENGTH >= length); + } + #endif +#endif + +#if SPI_W_CFG_FAST_MODE_ENABLE + if (0 != fast_max_count) + { + p_ctrl->fast_mode_st = SPI_W_FAST_MODE_ON; + p_ctrl->fast_max_count = fast_max_count; + } + else + { + p_ctrl->fast_mode_st = SPI_W_FAST_MODE_OFF; + } + + if (!((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->skip_disable) + { + FSP_ERROR_RETURN(0U == (p_ctrl->p_regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_EN_Msk), FSP_ERR_IN_USE); + } + +#else + if (!((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->skip_busy_check) + { + FSP_ERROR_RETURN(0U == (p_ctrl->p_regs->SPI_CTRL_REG & SPI_SPI_CTRL_REG_SPI_EN_Msk), FSP_ERR_IN_USE); + } +#endif + + p_ctrl->p_tx_data = p_src; + p_ctrl->p_rx_data = p_dest; + p_ctrl->tx_count = 0U; + p_ctrl->rx_count = 0U; + p_ctrl->count = length; + p_ctrl->bit_width = bit_width; + +#if (1 == SPI_W_CFG_TRANSFER_API_SUPPORT) || (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + /* When the rxi interrupt is called, all transfers will be finished. */ + p_ctrl->rx_count = length; + + /* Configure the receive DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = (uint16_t) length; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = p_dest; + + if (NULL == p_dest) + { + static uint32_t dummy_rx; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = &dummy_rx; + } + + err = p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_ctrl->p_cfg->p_transfer_rx->p_api->enable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + /* When the txi interrupt is called, all transfers will be finished. */ + p_ctrl->tx_count = length; + + /* Configure the transmit DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = (uint16_t) length; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = p_src; + + if (NULL == p_src) + { + static uint32_t dummy_tx = 0U; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = &dummy_tx; + } + } +#endif + + r_spi_w_bit_width_config(p_ctrl); + err = r_spi_w_start_transfer(p_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the SPI data register to the current rx data location. + * If the receive buffer is NULL, just read the SPI data register. + * If the total transfer length has already been received then do nothing. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_receive (spi_w_instance_ctrl_t * p_ctrl) +{ + uint32_t data; +#if SPI_W_CFG_FAST_MODE_ENABLE + uint8_t * p_fast_data = p_ctrl->fast_mode_buffer + p_ctrl->rx_count; +#endif + + while ((p_ctrl->rx_count < p_ctrl->count) && p_ctrl->p_regs->SPI_FIFO_STATUS_REG_b.SPI_RX_FIFO_LEVEL) + { + data = p_ctrl->p_regs->SPI_FIFO_READ_REG; + p_ctrl->rx_count++; + + if (NULL != p_ctrl->p_rx_data) + { + data &= p_ctrl->mask_width; + + if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width <= 8 bits */ + { + *((uint8_t *) p_ctrl->p_rx_data) = (uint8_t) data; + +#if SPI_W_CFG_FAST_MODE_ENABLE + if ((SPI_W_FAST_MODE_ON == p_ctrl->fast_mode_st) && (SPI_W_FAST_READ_HEADER_SIZE > p_ctrl->rx_count)) + { + *p_fast_data++ = (uint8_t ) data; + } +#endif + } + else if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths > 16 bits */ + { + *((uint32_t *) p_ctrl->p_rx_data) = (uint32_t) data; + } + else /* 8 bits < Bit Width <= 16 bits */ + { + *((uint16_t *) p_ctrl->p_rx_data) = (uint16_t) data; + } + + p_ctrl->p_rx_data = (void *) ((uint8_t *) p_ctrl->p_rx_data + p_ctrl->wordsize); + } + } +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the current tx data location into the SPI data register. + * If the transmit buffer is NULL, then write zero to the SPI data register. + * If the total transfer length has already been transmitted then do nothing. + * + * @param[in] p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_w_transmit (spi_w_instance_ctrl_t * p_ctrl) +{ + uint32_t fifo_lvl_rem; + uint32_t tx_data = 0U; /* Transmit zero if no tx buffer present. */ + +#if BSP_MCU_GROUP_RA6W3 + if (0U == p_ctrl->p_cfg->channel) + { + fifo_lvl_rem = (SPI_W_TX_FIFO_MAX_SIZE_BYTE_SPI1 - p_ctrl->p_regs->SPI_FIFO_STATUS_REG_b.SPI_TX_FIFO_LEVEL); + } + else + { + fifo_lvl_rem = (SPI_W_TX_FIFO_MAX_SIZE_BYTE - p_ctrl->p_regs->SPI_FIFO_STATUS_REG_b.SPI_TX_FIFO_LEVEL); + } + +#else + fifo_lvl_rem = (SPI_W_RX_FIFO_MAX_SIZE_BYTE - p_ctrl->p_regs->SPI_FIFO_STATUS_REG_b.SPI_TX_FIFO_LEVEL); +#endif + + fifo_lvl_rem /= p_ctrl->wordsize; + + while ((p_ctrl->tx_count < p_ctrl->count) && fifo_lvl_rem--) + { + if (NULL != p_ctrl->p_tx_data) + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths > 16 bits */ + { + tx_data = *((uint32_t *) p_ctrl->p_tx_data); + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width <= 8 bits */ + { + tx_data = (uint32_t) (*((uint8_t *) p_ctrl->p_tx_data)); + } + else /* 8 bits < Bit Width <= 16 bits */ + { + tx_data = (uint32_t) (*((uint16_t *) p_ctrl->p_tx_data)); + } + + p_ctrl->p_tx_data = (void *) ((uint8_t *) p_ctrl->p_tx_data + p_ctrl->wordsize); + } + + p_ctrl->p_regs->SPI_FIFO_WRITE_REG = tx_data; + p_ctrl->tx_count++; + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block. + * @param[in] event Event code. + **********************************************************************************************************************/ +static void r_spi_w_call_callback (spi_w_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + + p_ctrl->p_callback(p_args); + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if (2 == SPI_W_CFG_TRANSFER_API_SUPPORT) + +/*******************************************************************************************************************//** + * Callback that must be called after an RX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI instance control block + **********************************************************************************************************************/ +void spi_w_rx_dmac_callback (spi_w_instance_ctrl_t * p_ctrl) +{ +#if !BSP_MCU_GROUP_RA6W1 + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* If Generic ISR is too slow to keep up at high bitrates, + * the hardware will generate Idle Interrupt before all of the transfers are completed. + * By enabling Idle Interrupt here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else +#endif + { + r_spi_w_transfer_zero_pad_restore(p_ctrl); + + r_spi_w_transfer_end(p_ctrl); + } +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI instance control block + **********************************************************************************************************************/ +void spi_w_tx_dmac_callback (spi_w_instance_ctrl_t const * const p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); +} + +#endif + +/*******************************************************************************************************************//** + * Generic ISR for SPI. + **********************************************************************************************************************/ +void spi_w_gen_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + +#if !BSP_MCU_GROUP_RA6W1 + R_BSP_IrqStatusClear(irq); +#endif + + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); +#if BSP_MCU_GROUP_RA6W1 + uint32_t status_reg = p_ctrl->p_regs->SPI_STATUS_REG; +#endif + + /* Rx Overflow error interrupt. */ + if (1U == p_ctrl->p_regs->SPI_FIFO_STATUS_REG_b.SPI_RX_FIFO_OVFL) + { + /* Disable SPI interrupt. */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG = 0U; + + /* Deassert the Slave Select. */ + p_ctrl->p_regs->SPI_CS_CONFIG_REG = 0U; + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 0U; + + /* Reset FIFO. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_FIFO_RESET = 1U; + + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + /* Disable Rx DMA/DTC */ + p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + /* Receive Buffer Overflow Error. */ + r_spi_w_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + } + + /* FIFO RX full interrupt. */ +#if BSP_MCU_GROUP_RA6W1 + if ((0U != (status_reg & SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk)) && + (1U == p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_RX_FULL)) +#else + if (1U == p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_RX_FULL) +#endif + { + r_spi_w_receive(p_ctrl); + +#if SPI_W_CFG_FAST_MODE_ENABLE + if (SPI_W_FAST_MODE_ON == p_ctrl->fast_mode_st) + { + if (SPI_W_FAST_READ_HEADER_SIZE == p_ctrl->rx_count) + { + uint32_t inc_length = (uint32_t) (p_ctrl->fast_mode_buffer[5] << 16) | + (p_ctrl->fast_mode_buffer[6] << 8) | + (p_ctrl->fast_mode_buffer[7]); + + p_ctrl->count = SPI_W_FAST_READ_HEADER_SIZE + inc_length; + p_ctrl->count = (p_ctrl->count <= p_ctrl->fast_max_count) ? p_ctrl->count : p_ctrl->fast_max_count; + } + else if ((SPI_W_FAST_READ_HEADER_SIZE < p_ctrl->rx_count) && (p_ctrl->rx_count == p_ctrl->count)) + { + /* Disable Receive Buffer Full interrupt. */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_RX_FULL = 0U; + + /* Deassert the Slave Select. */ + p_ctrl->p_regs->SPI_CS_CONFIG_REG = 0U; + + /* Disable the SPI Transfer. */ + if (!((spi_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->skip_disable) + { + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 0U; + } + + /* Signal that a transfer has completed. */ + r_spi_w_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + + p_ctrl->fast_mode_st = SPI_W_FAST_MODE_OFF; + } + } + else +#endif + { + if (p_ctrl->rx_count == p_ctrl->count) + { + /* Disable Receive Buffer Full interrupt. */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_RX_FULL = 0U; + +#if BSP_MCU_GROUP_RA6W1 + r_spi_w_transfer_end(p_ctrl); +#else + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* If Generic ISR is too slow to keep up at high bitrates, + * the hardware will generate Idle Interrupt before all of the transfers are completed. + * By enabling Idle Interrupt here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else + { + r_spi_w_transfer_end(p_ctrl); + } +#endif + } + } + +#if SPI_W_CFG_TRANSMIT_FROM_RXI_ISR + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + { + r_spi_w_transmit(p_ctrl); + } +#endif + } + +#if !SPI_W_CFG_TRANSMIT_FROM_RXI_ISR + + /* FIFO TX empty interrupt. */ + #if BSP_MCU_GROUP_RA6W1 + if ((0U != (status_reg & SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk)) && + (1U == p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_TX_EMPTY)) + #else + if (1U == p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_TX_EMPTY) + #endif + { + r_spi_w_transmit(p_ctrl); + + if (p_ctrl->tx_count == p_ctrl->count) + { + /* Disable the TX buffer empty interrupt. */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG_b.SPI_IRQ_MASK_TX_EMPTY = 0U; + } + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#if !BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************//** + * ISR called when the SPI peripheral transitions from the transferring state to the IDLE state. + **********************************************************************************************************************/ +void spi_w_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + R_BSP_IrqStatusClear(irq); + + spi_w_instance_ctrl_t * p_ctrl = R_FSP_IsrContextGet(irq); + + if (p_ctrl->p_cfg->p_transfer_rx) + { + r_spi_w_transfer_zero_pad_restore(p_ctrl); + } + + r_spi_w_transfer_end(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called when data is copied from the SPI data register into the SPI shift register. + **********************************************************************************************************************/ +void spi_w_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called when data is loaded into SPI data register from the shift register. + **********************************************************************************************************************/ +void spi_w_rxi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Handle interrupt for a channel associated with received IRQn. */ + spi_w_instance_ctrl_t * p_ctrl = R_FSP_IsrContextGet(irq); + + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* If Generic ISR is too slow to keep up at high bitrates, + * the hardware will generate Idle Interrupt before all of the transfers are completed. + * By enabling Idle Interrupt here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else + { + r_spi_w_transfer_zero_pad_restore(p_ctrl); + + r_spi_w_transfer_end(p_ctrl); + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called in the event that an error occurs (Ex: RX_OVERFLOW). + **********************************************************************************************************************/ +void spi_w_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + R_BSP_IrqStatusClear(irq); + + /* Handle interrupt for a channel associated with received IRQn. */ + spi_w_instance_ctrl_t * p_ctrl = R_FSP_IsrContextGet(irq); + + /* Disable SPI interrupt. */ + p_ctrl->p_regs->SPI_IRQ_MASK_REG = 0U; + + /* Deassert the Slave Select. */ + p_ctrl->p_regs->SPI_CS_CONFIG_REG = 0U; + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_EN = 0U; + + /* Reset FIFO. */ + p_ctrl->p_regs->SPI_CTRL_REG_b.SPI_FIFO_RESET = 1U; + + /* Restore context if RTOS is used. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + /* Disable Rx DMA */ + p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + /* Receive Buffer Overflow Error. */ + r_spi_w_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if CFG_PMGR + +/*******************************************************************************************************************/ /** + * Prepare SPI for sleep mode 4/5 + * + * @param[in] p_context Pointer to PMGR interface of SPI instance + **********************************************************************************************************************/ +static fsp_err_t spi_w_enter_sleep (spi_w_pmgr_context_t * p_context) +{ + fsp_err_t err = FSP_SUCCESS; + #if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_context); + #endif + + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_context->p_ctrl; + + p_ctrl->open = SPI_W_SLEEPING; + + return err; +} + +/*******************************************************************************************************************/ /** + * Restore SPI from wakeup + * + * @param[in] p_context Pointer to PMGR interface of SPI instance + **********************************************************************************************************************/ +static fsp_err_t spi_w_wakeup (spi_w_pmgr_context_t * p_context) +{ + fsp_err_t err = FSP_SUCCESS; + #if SPI_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_context); + #endif + + spi_w_instance_ctrl_t * p_ctrl = (spi_w_instance_ctrl_t *) p_context->p_ctrl; + + /* Configure hardware registers according to the r_spi_api configuration structure. */ + r_spi_w_hw_config(p_ctrl); + + /* Enable interrupts in NVIC. */ + r_spi_w_nvic_config(p_ctrl); + + p_ctrl->open = SPI_W_OPEN; + + return err; +} + +static void spi_w_pmgr_callback (pmgr_callback_args_t * p_args) +{ + pmgr_instance_info_t * p_pmgr_info = (pmgr_instance_info_t *) p_args->p_instance_info; + + if (PMGR_LLD_POWER_MODE_SLEEP4 == p_pmgr_info->power_mode) + { + if (PMGR_EVENT_ENTERING_SLEEP == p_args->event) + { + /* Entering sleep 4/5 - close SPI */ + spi_w_enter_sleep((spi_w_pmgr_context_t *) p_args->p_context); + } + else if (PMGR_EVENT_EXITING_SLEEP == p_args->event) + { + /* Open SPI with previous settings */ + spi_w_wakeup((spi_w_pmgr_context_t *) p_args->p_context); + } + } +} + +static fsp_err_t r_spi_w_subscribe_for_pmgr_notifications (spi_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + + spi_w_pmgr_context_t * context = &g_spi_pmgr_context[p_ctrl->p_cfg->channel]; + + context->pmgr_info.power_mode = PMGR_LLD_POWER_MODE_SLEEP4; + context->pmgr_info.wake_source = PMGR_WAKE_SOURCE_NONE, + context->pmgr_notifier_ext.order = PMGR_W_NOTIFIER_ORDER_SYS_HIGH; + context->p_ctrl = p_ctrl; + + context->clbk_args.constraints = PMGR_CONSTRAINT_NONE; + context->clbk_args.event = PMGR_EVENT_NOT_SET; + context->clbk_args.p_context = (void *) context; + context->clbk_args.p_instance_info = (void *) &context->pmgr_info; + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(NULL != pmgr_ctrl); + + err = RM_PMGR_W_notifier_register(pmgr_ctrl, spi_w_pmgr_callback, &context->clbk_args, &context->pmgr_notifier_ext); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + +static fsp_err_t r_spi_w_unsubscribe_from_pmgr_notifications (spi_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(NULL != pmgr_ctrl); + + spi_w_pmgr_context_t * context = &g_spi_pmgr_context[p_ctrl->p_cfg->channel]; + err = RM_PMGR_W_notifier_unregister(pmgr_ctrl, context->pmgr_notifier_ext.notifier_id); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_tim_w/r_tim_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_tim_w/r_tim_w.c new file mode 100644 index 000000000000..bc1a9bc17023 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_tim_w/r_tim_w.c @@ -0,0 +1,1942 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_tim_w.h" +#include "r_tim_w_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "TIMW" in ASCII, used to determine if channel is open. */ +#define TIM_W_OPEN (0x54494D57ULL) +#define TIM_W_PRV_ONESHOT_WAIT (0x0) +#define TIM_W_PRV_GPIO_TRIGGER_OFFSET (0x1U) +#define TIM_W_PRV_DELAY_CYCLES (0x3U) + +#if TIMER_TIMER_SETTINGS_REG_TIM_RELOAD2_Msk + #define TIM_W_THRESHOLD_REG TIMER_SETTINGS_REG + #define TIM_W_PULSE_CNT_GPIO_REG TIMER_PULSE_GPIO_SEL_REG + #define TIM_W_PULSE_CNT_THRESHOLD_REG TIMER_PULSE_CNT_CTRL_REG + #define TIM_W_PRESCALER TIMER_PRE_SETTINGS_REG +#else + #define TIM_W_THRESHOLD_REG TIMER_THRESHOLD_REG + #define TIM_W_PULSE_CNT_GPIO_REG TIMER_PULSE_CNT_CTRL_REG + #define TIM_W_PULSE_CNT_THRESHOLD_REG TIMER_PULSE_CNT_THRESHOLD_REG + #define TIM_W_PRESCALER TIMER_SETTINGS_REG +#endif + +#if BSP_FEATURE_CGC_HAS_LP_CLOCK //! TIN_TODO: Remove when TIN lp clocks are added + #define TIM_W_PRV_SYNC_DELAY_US(clk_cycles) (((clk_cycles) * (1000000)) / (g_bsp_lp_clock) + 1) +#else + #define TIM_W_PRV_LP_CLK_HZ (32768U) //! TIN_TODO: Remove when TIN lp clocks are added + #define TIM_W_PRV_SYNC_DELAY_US(clk_cycles) (((clk_cycles) * (1000000)) / (TIM_W_PRV_LP_CLK_HZ) +1) +#endif +#if BSP_MCU_GROUP_RA6W1 + #define TIM_W_PWM_SYNC_TIMER_ALL (0b00111) + #define TIM_W_ONESHOT_TRIGGER_ALL (0x2U) + #define TIM_W_SLAVE_CCM_CHANNEL_SIZE (0x2U) + + #define TIM_W_EVENT_GPIO1 (0x0U) + #define TIM_W_EVENT_GPIO2 (0x1U) + #define TIM_W_EVENT_GPIO3 (0x2U) + #define TIM_W_EVENT_GPIO4 (0x3U) + +#else + #define TIM_W_ONESHOT_TRIGGER_ALL (0x4U) +#endif + +#define TIM_W_TIMEOUT (UINT16_MAX) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * tim_w_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile tim_w_prv_ns_callback)(timer_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_tim_w_hardware_initialize(tim_w_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg); +static void r_tim_w_common_open(tim_w_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); +static uint32_t r_tim_w_clock_frequency_get(tim_w_instance_ctrl_t * const p_instance_ctrl); +static void r_tim_w_hardware_events_disable(tim_w_instance_ctrl_t * p_instance_ctrl); +static void r_tim_w_disable_irq(IRQn_Type irq); +static void r_tim_w_call_callback(tim_w_instance_ctrl_t * p_ctrl, uint8_t event, uint32_t capture); +static void r_tim_w_freeze(tim_w_instance_ctrl_t * const p_instance_ctrl); +static void r_tim_w_unfreeze(tim_w_instance_ctrl_t * const p_instance_ctrl); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void r_tim_w_generic_isr(void); + +#if BSP_FEATURE_TIM_W_SUPPORTS_OVERFLOW_UNDERFLOW +void r_tim_w_counter_overflow_isr(void); +void r_tim_w_counter_underflow_isr(void); + +#endif +void r_tim_w_ccm_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* TIM_W implementation of timer interface */ +const timer_api_t g_timer_on_tim_w = +{ + .open = R_TIM_W_Open, + .stop = R_TIM_W_Stop, + .start = R_TIM_W_Start, + .reset = R_TIM_W_Reset, + .enable = R_TIM_W_Enable, + .disable = R_TIM_W_Disable, + .periodSet = R_TIM_W_PeriodSet, + .dutyCycleSet = R_TIM_W_DutyCycleSet, + .compareMatchSet = R_TIM_W_CompareMatchSet, + .infoGet = R_TIM_W_InfoGet, + .statusGet = R_TIM_W_StatusGet, + .callbackSet = R_TIM_W_CallbackSet, + .close = R_TIM_W_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup TIM_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * @note TIM_W hardware does not support one-shot interrupt on cycle_end. When using one-shot mode, the timer will be switched + * to periodic in order to generate the cycle_end irq, then switch back to one-shot inside the ISR. + * + * The TIM_W implementation of the general timer can accept a tim_w_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::p_callback is not NULL, but ISR is not enabled. + * @retval FSP_ERR_INVALID_MODE PWM mode cant be accessed without TIM_W_CFG_OUTPUT_SUPPORT_ENABLE == 1 + * @retval FSP_ERR_INVALID_CHANNEL PWM sync supports only TIM as master. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid argument passed for one-shot mode, capture/compare as well as count down + * are not supported. + * Capture/compare channel size is out of limit. + * PWM period or duty cycle values are not within valid limits. + * PWM sync can not be set without the PWM mode active. + * CCM Channel configuration is empty while channel size is not zero. + * Elc_channel exceeds the CCM channel size. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) // NOLINT(readability-function-cognitive-complexity) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_cfg->p_extend; + + /* Check power domains before setting any hardware registers */ + #if BSP_MCU_GROUP_RA6B1 || BSP_MCU_GROUP_RA6U1 + if (TIM_W_TIM8 == p_cfg->channel) + { + FSP_ASSERT(bsp_pd_is_up_check(BSP_PD_COM)); + } + else + { + FSP_ASSERT(bsp_pd_is_up_check(BSP_PD_TMR)); + } + #endif + + /* Check the source divider is within valid range */ + FSP_ASSERT(p_cfg->source_div <= TIM_W_SOURCE_DIV_MAX); + FSP_ERROR_RETURN(TIM_W_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + uint32_t channel_mask = 1U << (p_cfg->channel + TIM_W_CHANNEL_OFFSET); // Channel bitmask + + /* Ensure channel selected is valid/Available */ + FSP_ERROR_RETURN(0 != (channel_mask & BSP_FEATURE_TIM_W_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* If callback is not null make sure the general IRQ is enabled. */ + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + /* One-shot does not support count down */ + FSP_ERROR_RETURN(p_extend->direction == TIMER_DIRECTION_UP, FSP_ERR_INVALID_ARGUMENT); + } + + #if BSP_MCU_GROUP_RA6W1 //! Add PC test + if (p_extend->oneshot_switch_to_periodic) + { + /* Oneshot_switch_to_periodic is supported only by channels TIM_W_TIM1 and TIM_W_TIM5 */ + FSP_ERROR_RETURN((TIM_W_TIM1 == p_cfg->channel) || (TIM_W_TIM5 == p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + } + #endif + + if (NULL != p_extend->p_ccm_cfg) + { + #if BSP_MCU_GROUP_RA6W1 //! Add PC test + if (p_extend->p_ccm_cfg->single_capture_mode) + { + /* Feature supported only by channels TIM_W_TIM1 and TIM_W_TIM5 */ + FSP_ERROR_RETURN((TIM_W_TIM1 == p_cfg->channel) || (TIM_W_TIM5 == p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + } + #endif + + /* One-shot mode does not support any capture/compare operations. */ + FSP_ERROR_RETURN(TIMER_MODE_ONE_SHOT != p_cfg->mode, FSP_ERR_INVALID_ARGUMENT); + + #if BSP_MCU_GROUP_RA6W1 //! Add PC test + if ((TIM_W_TIM1 == p_cfg->channel) || (TIM_W_TIM5 == p_cfg->channel)) + { + FSP_ERROR_RETURN(BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS >= + p_extend->p_ccm_cfg->ccm_channel_size, + FSP_ERR_INVALID_ARGUMENT); + } + else + { + FSP_ERROR_RETURN(TIM_W_SLAVE_CCM_CHANNEL_SIZE >= //! Modify for RA6W1 + p_extend->p_ccm_cfg->ccm_channel_size, + FSP_ERR_INVALID_ARGUMENT); + } + + #else + FSP_ERROR_RETURN(BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS >= //! Modify for RA6W1 + p_extend->p_ccm_cfg->ccm_channel_size, + FSP_ERR_INVALID_ARGUMENT); + #endif + + #if !BSP_FEATURE_ELC_MISSING + if (TIM_W_ELC_CAPTURE == p_extend->elc_task) + { + FSP_ERROR_RETURN(p_extend->p_ccm_cfg->elc_channel <= + p_extend->p_ccm_cfg->ccm_channel_size, + FSP_ERR_INVALID_ARGUMENT); + } + #endif + if (0U < p_extend->p_ccm_cfg->ccm_channel_size) + { + FSP_ERROR_RETURN(NULL != p_extend->p_ccm_cfg->p_ccm_channel_cfg, FSP_ERR_INVALID_ARGUMENT); + } + } + + #if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + if (TIMER_MODE_PWM == p_cfg->mode) + { + /* Ensure PWM period does not exceed max value */ + FSP_ERROR_RETURN(p_cfg->period_counts <= TIM_W_PWM_MAX, FSP_ERR_INVALID_ARGUMENT); + + /* Ensure Duty Cycle does not exceed Period value */ + FSP_ERROR_RETURN(p_cfg->duty_cycle_counts <= p_cfg->period_counts, FSP_ERR_INVALID_ARGUMENT); + } + + if (0U != p_extend->pwm_sync_map) + { + /* Ensure PWM sync is not activated without pwm mode */ + FSP_ERROR_RETURN(TIMER_MODE_PWM == p_cfg->mode, FSP_ERR_INVALID_ARGUMENT); + + #if BSP_MCU_GROUP_RA6W3 + + /* Ensure the master channel on pwm sync is TIM_W_TIM1 or TIM_W_TIM8 */ + FSP_ERROR_RETURN((TIM_W_TIM1 == p_cfg->channel) || (TIM_W_TIM8 == p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + #elif BSP_MCU_GROUP_RA6W1 + + /* Ensure the master channel on pwm sync is TIM_W_TIM1 or TIM_W_TIM5 */ + FSP_ERROR_RETURN((TIM_W_TIM1 == p_cfg->channel) || (TIM_W_TIM5 == p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + #else + + /* Ensure the master channel on pwm sync is TIM */ + FSP_ERROR_RETURN(TIM_W_TIM1 == p_cfg->channel, FSP_ERR_INVALID_CHANNEL); + #endif + } + + #else + FSP_ERROR_RETURN(TIMER_MODE_PWM != p_cfg->mode, FSP_ERR_INVALID_MODE); + #endif +#endif + + /* Initialize control structure based on configurations. */ + r_tim_w_common_open(p_instance_ctrl, p_cfg); + r_tim_w_hardware_initialize(p_instance_ctrl, p_cfg); + + p_instance_ctrl->open = TIM_W_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops timer. Implements @ref timer_api_t::stop. + * + * @note In case the timer runs on low power clock, a max of 2 lp_clk sync cycles are required for the TIM_PAUSE bit + * to be effective. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Stop (timer_ctrl_t * const p_ctrl) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + + /* Pause does not affect the timer's behaviour for synced channels when on PWM mode. */ + if (0U != p_extend->pwm_sync_map) + { + /* Stop pwm on synced channels */ + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG_b.PWM_START = 0U; + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + } +#endif + + /* Edge detect needs to be disabled to stop counting edges for edge detect mode. */ + if (TIMER_MODE_EDGE_DETECT == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EDGE_DET_CNT_EN = 0U; + } + + /* Pause timer */ + r_tim_w_freeze(p_instance_ctrl); + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Start (timer_ctrl_t * const p_ctrl) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + if (0U != p_extend->pwm_sync_map) + { + /* Start pwm_sync */ + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG_b.PWM_START = 1U; + } +#endif + + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN = 1U; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); + p_instance_ctrl->p_reg->TIMER_ONESHOT_TRIGGER_REG = 1U; + } + else if (TIMER_MODE_EDGE_DETECT == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EDGE_DET_CNT_EN = 1U; + } + else + { + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN = 1U; + } + + /* Resume Counter */ + r_tim_w_unfreeze(p_instance_ctrl); + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter to the initial value. Implements @ref timer_api_t::reset. + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Reset (timer_ctrl_t * const p_ctrl) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Keep track of the timer state */ + timer_state_t timer_pause_state = TIMER_STATE_COUNTING; + timer_state_t timer_en_state = TIMER_STATE_COUNTING; + +#if !BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY + + /* Calculate the freeze bit corresponding to the channel. + * The range of SET_FREEZE_REG_b.FRZ_SWTIM..FRZ_SWTIM8 is [1..8]. The channel range is [0..7]. */ + uint8_t freeze_bit = p_instance_ctrl->p_cfg->channel + 1; + + /* Check if the timer is frozen */ + timer_pause_state = CRG_TOP->SET_FREEZE_REG & (1 << (freeze_bit)) ? TIMER_STATE_STOPPED : TIMER_STATE_COUNTING; +#else + timer_pause_state = + p_instance_ctrl->p_reg->TIMER_PAUSE_REG_b.TIM_PAUSE ? TIMER_STATE_STOPPED : TIMER_STATE_COUNTING; +#endif + + if (TIMER_STATE_STOPPED == timer_pause_state) + { + r_tim_w_unfreeze(p_instance_ctrl); + + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + } + + if (0U == p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN) + { + timer_en_state = TIMER_STATE_STOPPED; + } + else + { + /* Clear timer counter. */ + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN = 0U; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); + } + + if (TIMER_STATE_STOPPED == timer_pause_state) + { + r_tim_w_freeze(p_instance_ctrl); + } + + if (TIMER_STATE_COUNTING == timer_en_state) + { + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN = 1U; + } + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that capture the counter and sets the elc task. Implements @ref timer_api_t::enable. + * + * @note The timer could be running before R_TIM_W_Enable(). To ensure it is stopped, call R_TIM_W_Stop(). + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Enable (timer_ctrl_t * const p_ctrl) // NOLINT(readability-function-cognitive-complexity) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + tim_w_extended_cfg_t * p_extend; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint32_t tim_w_input_event_fall_en_lut[BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS] = + { + TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos, +#if !BSP_MCU_GROUP_RA6W1 + TIMER_TIMER_CTRL_REG_TIM_IN5_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN6_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN7_EVENT_FALL_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_IN8_EVENT_FALL_EN_Pos, +#endif + }; + + uint32_t tim_w_cap_event_irq_en_lut[BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS] = + { + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos, +#if !BSP_MCU_GROUP_RA6W1 + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO5_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO6_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO7_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO8_IRQ_EN_Pos, +#endif + }; + + uint32_t actual_pin; + bsp_io_port_pin_t pin_id; + bsp_io_port_t port_id; + + uint32_t ctrl_reg = p_instance_ctrl->p_reg->TIMER_CTRL_REG; + + switch (p_instance_ctrl->p_cfg->mode) + { + case TIMER_MODE_PERIODIC: + { + if ((NULL == p_extend->p_ccm_cfg) || (NULL == p_extend->p_ccm_cfg->p_ccm_channel_cfg)) + { + break; + } + +#if BSP_MCU_GROUP_RA6W1 + ctrl_reg &= + ~((TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk) + ); + + ctrl_reg &= + ~((TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk) + ); +#else + ctrl_reg &= + ~((TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN5_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN6_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN7_EVENT_FALL_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_IN8_EVENT_FALL_EN_Msk) + ); + + ctrl_reg &= + ~((TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO5_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO6_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO7_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO8_IRQ_EN_Msk) + ); +#endif + + for (uint8_t index = 0; index < p_extend->p_ccm_cfg->ccm_channel_size; index++) + { +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + if ((TIM_W_CCM_OPERATION_CAPTURE != p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].operation) || + (TIM_W_GPIO_TRIGGER_DISABLED == p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].capture_trigger)) +#else + if (TIM_W_GPIO_TRIGGER_DISABLED == p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].capture_trigger) +#endif + { + continue; + } + + pin_id = + (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & + (uint16_t) p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].capture_source); + port_id = + (bsp_io_port_t) ((BSP_IO_PORT_BITS & + (uint16_t) p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].capture_source) >> + BSP_IO_PORT_OFFSET); + + actual_pin = (port_id == 0U) ? pin_id + 1U : + (port_id == 1U) ? pin_id + 1U + BSP_FEATURE_IO_PORT0_GPIO_COUNT : + pin_id + 1U + BSP_FEATURE_IO_PORT1_GPIO_COUNT + BSP_FEATURE_IO_PORT0_GPIO_COUNT; + + ctrl_reg |= + (p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].capture_trigger - TIM_W_PRV_GPIO_TRIGGER_OFFSET) << + tim_w_input_event_fall_en_lut[index]; + ctrl_reg |= 1U << tim_w_cap_event_irq_en_lut[index]; + +#if BSP_MCU_GROUP_RA6W1 + if (TIM_W_EVENT_GPIO1 == index) + { + p_instance_ctrl->p_reg->TIMER_GPIO1_CONF_REG = actual_pin; + } + else if (TIM_W_EVENT_GPIO2 == index) + { + p_instance_ctrl->p_reg->TIMER_GPIO2_CONF_REG = actual_pin; + } + else if (TIM_W_EVENT_GPIO3 == index) + { + p_instance_ctrl->p_reg->TIMER_GPIO3_CONF_REG = actual_pin; + } + else if (TIM_W_EVENT_GPIO4 == index) + { + p_instance_ctrl->p_reg->TIMER_GPIO4_CONF_REG = actual_pin; + } + +#else + p_instance_ctrl->p_reg->TIMER_GPIO_CONF_REG[index] = actual_pin; +#endif + } + + break; + } + + case TIMER_MODE_EDGE_DETECT: + { + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_EDGE_DET_CNT_EN, ctrl_reg, 1U); + + if (TIM_W_GPIO_TRIGGER_DISABLED == p_extend->gpio_trigger) + { + break; + } + + /* Calculate the actual tim_w gpio configure register value */ + pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) p_extend->gpio_source); + port_id = (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) p_extend->gpio_source) >> BSP_IO_PORT_OFFSET); + + actual_pin = (port_id == 0U) ? pin_id + 1U : + (port_id == 1U) ? pin_id + 1U + BSP_FEATURE_IO_PORT0_GPIO_COUNT : + pin_id + 1U + BSP_FEATURE_IO_PORT1_GPIO_COUNT + BSP_FEATURE_IO_PORT0_GPIO_COUNT; + + p_instance_ctrl->p_reg->TIM_W_PULSE_CNT_GPIO_REG = actual_pin; + + FSP_REG_VAR_FIELD_SET(TIMER, + TIMER_CTRL_REG, + TIM_EDGE_DET_CNT_FALL_EN, + ctrl_reg, + p_extend->gpio_trigger - TIM_W_PRV_GPIO_TRIGGER_OFFSET); + + break; + } + + case TIMER_MODE_ONE_SHOT: + { + /* TIM_EN bit does not trigger the one-shot pulse operation in one-shot mode, + * but we need to set it before the trigger takes place + */ + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_EN, ctrl_reg, 1U); + + if (TIM_W_GPIO_TRIGGER_DISABLED == p_extend->gpio_trigger) + { + break; + } + + /* Calculate the actual tim_w gpio configure register value */ + pin_id = (bsp_io_port_pin_t) (BSP_IO_PIN_BITS & (uint16_t) p_extend->gpio_source); + port_id = (bsp_io_port_t) ((BSP_IO_PORT_BITS & (uint16_t) p_extend->gpio_source) >> BSP_IO_PORT_OFFSET); + + actual_pin = (port_id == 0U) ? pin_id + 1U : + (port_id == 1U) ? pin_id + 1U + BSP_FEATURE_IO_PORT0_GPIO_COUNT : + pin_id + 1U + BSP_FEATURE_IO_PORT1_GPIO_COUNT + BSP_FEATURE_IO_PORT0_GPIO_COUNT; + +#if BSP_MCU_GROUP_RA6W1 + p_instance_ctrl->p_reg->TIMER_GPIO1_CONF_REG = actual_pin; +#else + p_instance_ctrl->p_reg->TIMER_GPIO_CONF_REG[0U] = actual_pin; +#endif + FSP_REG_VAR_FIELD_SET(TIMER, + TIMER_CTRL_REG, + TIM_IN1_EVENT_FALL_EN, + ctrl_reg, + p_extend->gpio_trigger - TIM_W_PRV_GPIO_TRIGGER_OFFSET); + + break; + } + + case TIMER_MODE_PWM: + { + /* global SYNC_ENABLE signal is set here for TIMER_MODE_PWM mode */ + if (p_extend->pwm_sync_map != 0U) + { + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG_b.SYNC_ENABLE = 1U; + } + } + + default: + { + break; + } + } + +#if !BSP_FEATURE_ELC_MISSING + if ((TIM_W_ELC_CAPTURE == p_extend->elc_task) && + (p_extend->p_ccm_cfg->p_ccm_channel_cfg[p_extend->p_ccm_cfg->elc_channel].ccm_operation_irq >= + (IRQn_Type) 0U)) + { + ctrl_reg |= 1U << tim_w_cap_event_irq_en_lut[p_extend->p_ccm_cfg->elc_channel]; + } + + /* Set timer elc task */ + p_instance_ctrl->p_reg->TIMER_ELC_TASK_REG = + ((p_extend->elc_task << TIMER_TIMER_ELC_TASK_REG_TIM_ELC_TASK_Pos) & + TIMER_TIMER_ELC_TASK_REG_TIM_ELC_TASK_Msk) | + ((p_extend->p_ccm_cfg->elc_channel << + TIMER_TIMER_ELC_TASK_REG_TIM_ELC_TASK_CAPTURE_Pos) & + TIMER_TIMER_ELC_TASK_REG_TIM_ELC_TASK_CAPTURE_Msk); +#endif + + p_instance_ctrl->p_reg->TIMER_CTRL_REG = ctrl_reg; + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, capture or compare. + * Implements @ref timer_api_t::disable. + * + * @note The timer could be running after R_TIM_W_Disable(). To ensure it is stopped, call R_TIM_W_Stop(). + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Disable (timer_ctrl_t * const p_ctrl) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + r_tim_w_hardware_events_disable(p_instance_ctrl); + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets period value provided. + * + * Implements @ref timer_api_t::periodSet. + * + * @warning Period will be updated immediately regardless of the timer's state. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL, or selected value exceeds HW specifications. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Selected value exceeds the maximum register value. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + timer_cfg_t * p_cfg = (timer_cfg_t *) p_instance_ctrl->p_cfg; + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + if (TIMER_MODE_PWM == p_cfg->mode) + { + /* in TIMER_MODE_PWM, period_counts value does not exceed max pwm_freq register value */ + FSP_ERROR_RETURN(period_counts <= TIM_W_PWM_MAX, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIM_W_THRESHOLD_REG = period_counts; + } + else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + if (p_extend->oneshot_switch_to_periodic) + { + p_instance_ctrl->p_reg->TIM_W_THRESHOLD_REG = period_counts; + } + else + { + p_instance_ctrl->p_reg->TIMER_SHOTWIDTH_REG = period_counts; + } + } + else if (TIMER_MODE_EDGE_DETECT == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIM_W_PULSE_CNT_THRESHOLD_REG = period_counts; + } + +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_PWM_BUSY, 0U); + p_instance_ctrl->p_reg->TIMER_PWM_CTRL_REG = + ((period_counts << TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos) & + TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk) | + (((period_counts >> 1) << TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos) & + TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk); + } + else if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_PWM_BUSY, 0U); + p_instance_ctrl->p_reg->TIMER_PWM_CTRL_REG_b.TIM_PWM_FREQ = (uint16_t) period_counts; + } +#endif + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets period value provided. + * + * Implements @ref timer_api_t::periodSet. + * + * @warning Light version of periodSet, the new period will be applied without any checks. + * + * + * @retval FSP_SUCCESS Period value written successfully. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_PeriodSet_light (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->p_reg->TIM_W_THRESHOLD_REG = period_counts; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets duty cycle. Implements @ref timer_api_t::dutyCycleSet. + * + * @warning Duty cycle will be updated immediately regardless of the timer's state. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_DutyCycleSet + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] duty_cycle_counts Duty cycle to set in counts. + * @param[in] pin Use tim_w_io_pin_t to select TIM_W_IO_PIN_GTIOCA or TIM_W_IO_PIN_GTIOCB + * + * @retval FSP_SUCCESS Duty cycle updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL or the pin is not one of tim_w_io_pin_t + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle is larger than period. + * @retval FSP_ERR_INVALID_MODE Duty cycle can only be configured in PWM mode. + * @retval FSP_ERR_UNSUPPORTED TIM_W_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ + FSP_PARAMETER_NOT_USED(pin); +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + #if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + timer_cfg_t * p_cfg = (timer_cfg_t *) p_instance_ctrl->p_cfg; + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Duty Cycle can be configured only in TIMER_MODE_PWM mode. */ + FSP_ERROR_RETURN(TIMER_MODE_PWM == p_cfg->mode, FSP_ERR_INVALID_MODE); + + /* DC value can not exceed period value */ + FSP_ERROR_RETURN(duty_cycle_counts <= p_cfg->period_counts, FSP_ERR_INVALID_ARGUMENT); + #endif + + p_instance_ctrl->p_reg->TIMER_PWM_CTRL_REG_b.TIM_PWM_DC = (uint16_t) duty_cycle_counts; + + /* Wait until the updated values are effective */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_PWM_BUSY, 0U); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Set value for compare match feature. Implements @ref timer_api_t::compareMatchSet. + * + * @note This API should be used when timer has stop counting and shall not be used along with PWM operation. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_CompareMatchSet + * + * @retval FSP_SUCCESS Set the compare match value successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_NOT_ENABLED Requested compare channel is disabled. + * CCM channel configuration is NULL. + * @retval FSP_ERR_INVALID_MODE Compare match operation is only available on periodic mode. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + + #if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); + + /* Confirm that requested compare match channel is enabled */ + FSP_ERROR_RETURN((NULL != p_extend->p_ccm_cfg) && (NULL != p_extend->p_ccm_cfg->p_ccm_channel_cfg), + FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN( + TIM_W_CCM_OPERATION_COMPARE_MATCH == p_extend->p_ccm_cfg->p_ccm_channel_cfg[match_channel].operation, + FSP_ERR_NOT_ENABLED); + #else + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + #endif + + /* Set compare match value. */ + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_REG[match_channel] = compare_match_value; + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(TIM_W_PRV_DELAY_CYCLES), BSP_DELAY_UNITS_MICROSECONDS); + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Get captured values for all configured capturing channels when sequential capturing is enabled. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_SequentialCapturesGet + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] p_captures Pointer to the captured snapshot values. + * + * @note p_captures length must be greater or equal than the number of sequential captures. + * + * @retval FSP_SUCCESS Captured values stored successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_captures was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_MODE Capture operation is only available on periodic mode. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_SequentialCapturesGet (timer_ctrl_t * const p_ctrl, uint32_t * const p_captures) +{ +#if BSP_FEATURE_TIM_W_SUPPORTS_SEQ_CAPTURES + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + + #if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_captures); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); + #endif + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (NULL != p_extend->p_ccm_cfg) + { + for (uint8_t index = 0; index < p_extend->p_ccm_cfg->seq_captures; index++) + { + *(p_captures + index) = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO_REG[index]; + } + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_captures); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's + * structure successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + p_info->period_counts = p_instance_ctrl->p_reg->TIM_W_THRESHOLD_REG; + } + else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + p_info->period_counts = p_instance_ctrl->p_reg->TIMER_SHOTWIDTH_REG; + } + else if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + p_info->period_counts = p_instance_ctrl->p_reg->TIMER_PWM_CTRL_REG_b.TIM_PWM_FREQ; + } + + /* Get and store clock frequency after prescaler */ + p_info->clock_frequency = r_tim_w_clock_frequency_get(p_instance_ctrl); + + /* Get and store clock counting direction. Read count direction setting */ + p_info->count_direction = (timer_direction_t) !(p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_COUNT_DOWN_EN); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_tim_w_example.c R_TIM_W_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value set successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if !BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY + + /* Read the refreeze register */ + uint32_t freeze_reg = CRG_TOP->RESET_FREEZE_REG; + + /* Calculate the freeze bit corresponding to the channel. + * The range of RESET_FREEZE_REG_b.FRZ_SWTIM..FRZ_SWTIM8 is [1..8]. The channel range is [0..7]. */ + uint32_t freeze_bit = p_instance_ctrl->p_cfg->channel + 1; +#endif + + /* Get counter value */ + if (TIMER_MODE_EDGE_DETECT == p_instance_ctrl->p_cfg->mode) + { + p_status->counter = 0U; + } + else + { + p_status->counter = p_instance_ctrl->p_reg->TIMER_TIMER_VAL_REG_b.TIM_TIMER_VALUE; + } + + p_status->state = TIMER_STATE_COUNTING; + + /* Get counter state */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* The TIM_W state can not be determined with certainty in case ONESHOT_SWITCH is set. */ + if (1U == p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_ONESHOT_SWITCH) + { + p_status->state = TIMER_STATE_UNKNOWN; + } + else if (TIM_W_PRV_ONESHOT_WAIT == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_ONESHOT_PHASE) + { + p_status->state = TIMER_STATE_STOPPED; + } + } + +#if !BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY + if (freeze_reg & (1 << freeze_bit) || (0U == p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN)) +#else + if ((1U == p_instance_ctrl->p_reg->TIMER_PAUSE_REG) || (0U == p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN)) +#endif + { + p_status->state = TIMER_STATE_STOPPED; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + tim_w_instance_ctrl_t * p_ctrl = (tim_w_instance_ctrl_t *) p_api_ctrl; + +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(TIM_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @note In case the timer runs on low power clock, a max of 2 lp_clk sync cycles are required for the TIM_EN bit + * to be effective. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TIM_W_Close (timer_ctrl_t * const p_ctrl) +{ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) p_ctrl; + +#if TIM_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIM_W_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Disables external events */ + r_tim_w_hardware_events_disable(p_instance_ctrl); + + r_tim_w_unfreeze(p_instance_ctrl); + +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + + /* Set capture_compare mode to reset value (capture) and clear compare match irq reg */ + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_ENABLE_REG = 0U; + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_IRQ_REG = 0U; +#endif + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG = 0U; + + /* Disable interrupts. */ + r_tim_w_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); + + if ((NULL != p_extend->p_ccm_cfg) && (NULL != p_extend->p_ccm_cfg->p_ccm_channel_cfg)) + { + for (uint8_t index = 0; index < p_extend->p_ccm_cfg->ccm_channel_size; index++) + { + if (p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_irq >= 0) + { + r_tim_w_disable_irq(p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_irq); + } + } + } + + /* + * Reset the TIM_EN bit field before resetting the ctrl register. + * This way we ensure that the TIM_W resets properly before closing. + */ + p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_EN = 0U; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); + + /* Stop timer clock. */ + p_instance_ctrl->p_reg->TIMER_CTRL_REG = 0U; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; + +#if BSP_MCU_GROUP_RA6W3 + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + if (TIM_W_TIM8 <= p_instance_ctrl->p_cfg->channel) + { + /* Disable the PD_SLP timer clock only if all TIM8–TIM10 are closed */ + if ((0 == TIMER8->TIMER8_CTRL_REG) && + (0 == TIMER9->TIMER9_CTRL_REG) && + (0 == TIMER10->TIMER10_CTRL_REG)) + { + CRG_TOP->CLK_PD_SLP_REG_b.SLP_TIMER_ENABLE = 0; + } + } + FSP_CRITICAL_SECTION_EXIT; +#endif + + return FSP_SUCCESS; +} + +/** @} (end addtogroup TIM_W) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes control structure based on configuration. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void r_tim_w_common_open (tim_w_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Initialize control structure. */ + p_instance_ctrl->p_cfg = p_cfg; + +#if defined(TIMER9) && defined(TIMER10) + + /* Save register base address. */ + #if BSP_MCU_GROUP_RA6W3 + if (TIM_W_TIM8 > p_cfg->channel) + { + uint32_t base_address = (uint32_t) TIMER + (p_cfg->channel * ((uint32_t) TIMER2 - (uint32_t) TIMER)); + p_instance_ctrl->p_reg = (TIMER_Type *) base_address; + } + else + { + uint32_t base_address = (uint32_t) TIMER8 + + ((p_cfg->channel - TIM_W_TIM8) * ((uint32_t) TIMER9 - (uint32_t) TIMER8)); + p_instance_ctrl->p_reg = (TIMER_Type *) base_address; + } + #endif +#else + if (TIM_W_TIM8 > p_cfg->channel) + { + uint32_t base_address = (uint32_t) TIMER + (p_cfg->channel * ((uint32_t) TIMER2 - (uint32_t) TIMER)); + p_instance_ctrl->p_reg = (TIMER_Type *) base_address; + } + else + { + p_instance_ctrl->p_reg = (TIMER_Type *) TIMER8; + } +#endif + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; +} + +/*******************************************************************************************************************//** + * Performs hardware initialization of the TIM_W. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void r_tim_w_hardware_initialize (tim_w_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) // NOLINT(readability-function-cognitive-complexity) +{ + /* Save pointer to extended configuration structure. */ + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_cfg->p_extend; + + uint32_t ctrl_reg = 0U; + uint32_t threshold_reg = 0U; + + uint32_t tim_w_cap_event_irq_en_lut[BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS] = //! Add bsp feature in TIN + { + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos, +#if !BSP_MCU_GROUP_RA6W1 + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO5_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO6_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO7_IRQ_EN_Pos, + TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO8_IRQ_EN_Pos, +#endif + }; + +#if BSP_MCU_GROUP_RA6W3 + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (TIM_W_TIM8 <= p_cfg->channel) + { + /* Enable the PD_SLP timer clock */ + CRG_TOP->CLK_PD_SLP_REG_b.SLP_TIMER_ENABLE = 1; + } +#endif + + /* Check busy flag & set timer's clk prescaler ( 1/(2^N), N = 0 to 8 ). */ + uint32_t timeout = TIM_W_TIMEOUT; + while ((1 == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY) && --timeout) + { + ; + } + + p_instance_ctrl->p_reg->TIM_W_PRESCALER = p_cfg->source_div; + + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_SYS_CLK_EN, ctrl_reg, p_extend->count_source); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_CLK_EN, ctrl_reg, 1U); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_COUNT_DOWN_EN, ctrl_reg, !(p_extend->direction)); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_FREE_RUN_MODE_EN, ctrl_reg, p_extend->free_run); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_IRQ_EN, ctrl_reg, 1U); + + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + /* + * Set timer mode to one-shot + * Configure one-shot trigger to access all sources available (GPIO, ELC, SW). + */ + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_ONESHOT_MODE_EN, ctrl_reg, 1U); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_ONESHOT_TRIGGER, ctrl_reg, TIM_W_ONESHOT_TRIGGER_ALL); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_ONESHOT_SWITCH, ctrl_reg, + p_extend->oneshot_switch_to_periodic); + + /* + * When in one-shot mode, TIMER_THRESHOLD_REG value represents a delay + * before the one-shot pulse. + */ + threshold_reg = p_extend->oneshot_delay; + + /* Check busy flag & set shot fire duration. */ + timeout = TIM_W_TIMEOUT; + while ((1 == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY) && --timeout) + { + ; + } + + p_instance_ctrl->p_reg->TIMER_SHOTWIDTH_REG = p_cfg->period_counts; + } + else if (TIMER_MODE_EDGE_DETECT == p_cfg->mode) + { + threshold_reg = UINT32_MAX; + + /* Set after how many pulses an interrupt is generated. + * The first pulse shall be ignored by HW due to metastability issues. + */ + p_instance_ctrl->p_reg->TIM_W_PULSE_CNT_THRESHOLD_REG = (p_cfg->period_counts) - 1U; + } + else if (TIMER_MODE_PERIODIC == p_cfg->mode) + { + threshold_reg = p_cfg->period_counts; + + if (NULL != p_extend->p_ccm_cfg) + { +#if BSP_FEATURE_TIM_W_SUPPORTS_SEQ_CAPTURES + if (p_extend->p_ccm_cfg->seq_captures > 0U) + { + /* Set sequential capturing to be triggered by both gpio and elc triggers */ + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_SEQ_CAPTURING_MODE, ctrl_reg, 3U); + + /* Set the number of sequential captures needed for the capture IRQ to be triggered. */ + p_instance_ctrl->p_reg->TIMER_CONF_CAP_EVENTS_REG = + p_extend->p_ccm_cfg->seq_captures; + } +#endif + + /* Configure CCM channels */ + if (NULL != p_extend->p_ccm_cfg->p_ccm_channel_cfg) + { + /* + * Fill the compare_match regs with desired value, enable compare mode + * and enable dedicated capture_compare irq lines + */ + for (uint8_t index = 0; index < p_extend->p_ccm_cfg->ccm_channel_size; index++) + { +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + if (TIM_W_CCM_OPERATION_COMPARE_MATCH == p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].operation) + { + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_REG[index] = + p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].compare_value; + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_ENABLE_REG |= 1U << index; + } +#endif + + if (p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_irq >= + (IRQn_Type) 0U) + { +#if BSP_FEATURE_TIM_W_SUPPORTS_COMPARE_MATCH + if (TIM_W_CCM_OPERATION_COMPARE_MATCH == + p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].operation) + { + p_instance_ctrl->p_reg->TIMER_COMPARE_MATCH_IRQ_REG |= 1U << index; + } + else + { + ctrl_reg |= 1U << tim_w_cap_event_irq_en_lut[index]; + } + +#else + ctrl_reg |= 1U << tim_w_cap_event_irq_en_lut[index]; +#endif + + //! Add PC test for timer5 only +#if BSP_FEATURE_TIM_W_HAS_IRQ_PER_CAPTURE_CHANNEL + R_BSP_IrqCfgEnable(p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_irq, + p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_ipl, + p_instance_ctrl); +#else + R_BSP_IrqCfgEnable(p_extend->p_ccm_cfg->p_ccm_channel_cfg[0].ccm_operation_irq, + p_extend->p_ccm_cfg->p_ccm_channel_cfg[0].ccm_operation_ipl, + p_instance_ctrl); +#endif + } + } + } + } + + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CTRL_REG, TIM_SINGLE_EVENT_CAPTURE, ctrl_reg, + ((NULL != p_extend->p_ccm_cfg) ? p_extend->p_ccm_cfg->single_capture_mode : 0)); + } + + p_instance_ctrl->p_reg->TIMER_CTRL_REG = ctrl_reg; +#if BSP_MCU_GROUP_RA6W3 + FSP_CRITICAL_SECTION_EXIT; +#endif + +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + uint32_t pwm_reg = 0U; + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_CTRL_REG, TIM_PWM_FREQ, pwm_reg, p_cfg->period_counts); + + if (TIMER_MODE_PERIODIC == p_cfg->mode) + { + /* Periodic with output support generates a 50% duty cycle PWM along with timer functionality */ + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_CTRL_REG, TIM_PWM_DC, pwm_reg, p_cfg->period_counts >> 1); + } + else if (TIMER_MODE_PWM == p_cfg->mode) + { + threshold_reg = UINT32_MAX; + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_CTRL_REG, TIM_PWM_DC, pwm_reg, p_cfg->duty_cycle_counts); + + if (p_extend->pwm_sync_map != 0U) + { + uint32_t pwm_sync_reg = 0; + #if BSP_MCU_GROUP_RA6W1 + pwm_sync_reg = (p_extend->pwm_sync_map & TIM_W_PWM_SYNC_TIMER_ALL) << + TIMER_TIMER_PWM_SYNC_REG_TIMER2_SYNC_Pos; + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_SYNC_REG, TIMER_SYNC, pwm_sync_reg, 1U); + #else + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_SYNC_REG, TIMER_SLAVE_SYNC, pwm_sync_reg, p_extend->pwm_sync_map); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_PWM_SYNC_REG, TIMER_MASTER_SYNC, pwm_sync_reg, 1U); + #endif + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG = pwm_sync_reg; + } + } + + /* Check busy flag & set PWM register. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_PWM_BUSY, 0U); + p_instance_ctrl->p_reg->TIMER_PWM_CTRL_REG = pwm_reg; +#endif + + /* Check busy flag & set counter threshold. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); + + p_instance_ctrl->p_reg->TIM_W_THRESHOLD_REG = threshold_reg; + + /* Enable CPU interrupts if callback is not null. Also enable interrupts for one shot mode. + * @note The TIM_W hardware does not support one-shot mode natively. To support one-shot mode, the timer will be + * stopped and cleared using software in the ISR. + */ + if (p_cfg->cycle_end_irq >= (IRQn_Type) 0U) + { + R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + } + +#if BSP_FEATURE_TIM_W_SUPPORTS_OVERFLOW_UNDERFLOW + if (p_extend->overflow_irq >= (IRQn_Type) 0U) + { + R_BSP_IrqCfgEnable(p_extend->overflow_irq, p_extend->overflow_ipl, p_instance_ctrl); + } + + if (p_extend->underflow_irq >= (IRQn_Type) 0U) + { + R_BSP_IrqCfgEnable(p_extend->underflow_irq, p_extend->underflow_ipl, p_instance_ctrl); + } +#endif + + /* Wait until the configuration values are effective */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_TIMER_BUSY, 0U); +#if TIM_W_CFG_OUTPUT_SUPPORT_ENABLE + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_PWM_BUSY, 0U); +#endif + + /* Wait 3 lp clock cycles for register changes to be effective */ + if (TIM_W_CLOCK_LP_CLK == p_extend->count_source) + { + R_BSP_SoftwareDelay(TIM_W_PRV_SYNC_DELAY_US(1), BSP_DELAY_UNITS_MICROSECONDS); + } +} + +/*******************************************************************************************************************//** + * Disables hardware events that would cause the timer to start, stop, clear, or capture. + * + * @param[in] p_instance_ctrl Instance control structure + **********************************************************************************************************************/ +static void r_tim_w_hardware_events_disable (tim_w_instance_ctrl_t * p_instance_ctrl) +{ +#if BSP_MCU_GROUP_RA6W1 + p_instance_ctrl->p_reg->TIMER_GPIO1_CONF_REG = TIM_W_GPIO_TRIGGER_DISABLED; + p_instance_ctrl->p_reg->TIMER_GPIO2_CONF_REG = TIM_W_GPIO_TRIGGER_DISABLED; + if ((TIM_W_TIM1 == p_instance_ctrl->p_cfg->channel) || + (TIM_W_TIM5 == p_instance_ctrl->p_cfg->channel)) ///< ! only TIM_W_TIM1 and TIM_W_TIM5 supports 4 capture events + { + p_instance_ctrl->p_reg->TIMER_GPIO3_CONF_REG = TIM_W_GPIO_TRIGGER_DISABLED; + p_instance_ctrl->p_reg->TIMER_GPIO4_CONF_REG = TIM_W_GPIO_TRIGGER_DISABLED; + + uint32_t tmp = p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG; + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CLEAR_GPIO_EVENT_REG, TIM_CLEAR_GPIO1_EVENT, tmp, true); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CLEAR_GPIO_EVENT_REG, TIM_CLEAR_GPIO2_EVENT, tmp, true); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CLEAR_GPIO_EVENT_REG, TIM_CLEAR_GPIO3_EVENT, tmp, true); + FSP_REG_VAR_FIELD_SET(TIMER, TIMER_CLEAR_GPIO_EVENT_REG, TIM_CLEAR_GPIO4_EVENT, tmp, true); + p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG = tmp; + } + + p_instance_ctrl->p_reg->TIMER_CTRL_REG &= + ~((TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk) + ); +#else + p_instance_ctrl->p_reg->TIMER_CTRL_REG &= + ~((TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO5_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO6_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO7_IRQ_EN_Msk) | + (TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO8_IRQ_EN_Msk) + ); + + for (uint8_t index = 0U; index < BSP_FEATURE_TIM_W_NUM_OF_CCM_CHANNELS; index++) + { + p_instance_ctrl->p_reg->TIMER_GPIO_CONF_REG[index] = TIM_W_GPIO_TRIGGER_DISABLED; + } +#endif + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIMER_PWM_SYNC_REG_b.SYNC_ENABLE = 0U; + } + else if (TIMER_MODE_EDGE_DETECT == p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->TIM_W_PULSE_CNT_GPIO_REG = 0U; + } + +#if !BSP_FEATURE_ELC_MISSING + p_instance_ctrl->p_reg->TIMER_ELC_TASK_REG = 0U; +#endif +} + +/*******************************************************************************************************************//** + * Disables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +static void r_tim_w_disable_irq (IRQn_Type irq) +{ + /* Disable interrupts. */ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Calculates clock frequency of TIM_W counter. Divides TIM_W clock by TIM_W clock divisor. + * + * @param[in] p_instance_ctrl Instance control block + * ********************************************************************************************************/ +static uint32_t r_tim_w_clock_frequency_get (tim_w_instance_ctrl_t * const p_instance_ctrl) +{ + /* Frequency = Timer clock frequency / 2^N, where N = 0 to 8 */ + uint32_t prescaler_val = 0; + + tim_w_clock_t src = (tim_w_clock_t) p_instance_ctrl->p_reg->TIMER_CTRL_REG_b.TIM_SYS_CLK_EN; + + prescaler_val = p_instance_ctrl->p_reg->TIM_W_PRESCALER; + + uint32_t timer_clk_freq = 0; + + if (src == TIM_W_CLOCK_DIVN) + { +#if BSP_MCU_GROUP_RA6W1 + timer_clk_freq = BSP_CFG_XTALM_HZ; +#else + timer_clk_freq = BSP_DIVN_FREQ_HZ; +#endif + } + else if (src == TIM_W_CLOCK_LP_CLK) + { +#if BSP_FEATURE_CGC_HAS_LP_CLOCK //! TIN_TODO: Remove when TIN lp clocks are added + + /* Get the LP clock Hz */ + timer_clk_freq = R_BSP_LPClockHzGet(); +#else //! TIN_TODO: Remove when TIN lp clocks are added + timer_clk_freq = TIM_W_PRV_LP_CLK_HZ; +#endif + } + + /* Calculate the timer's frequency after the prescaler */ + return timer_clk_freq / (1 << prescaler_val); +} + +/*******************************************************************************************************************//** + * Freeze selected timer + * + * @param[in] p_instance_ctrl Instance control structure + **********************************************************************************************************************/ +static void r_tim_w_freeze (tim_w_instance_ctrl_t * const p_instance_ctrl) +{ +#if BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY + p_instance_ctrl->p_reg->TIMER_PAUSE_REG = 1U; +#else + + /* Calculate the freeze bit corresponding to the channel. + * The range of SET_FREEZE_REG_b.FRZ_SWTIM..FRZ_SWTIM8 is [1..8]. The channel range is [0..7]. + */ + uint32_t freeze_bit = p_instance_ctrl->p_cfg->channel + 1; + CRG_TOP->SET_FREEZE_REG = (1 << freeze_bit); +#endif +} + +/*******************************************************************************************************************//** + * Unfreeze selected timer + * + * @param[in] p_instance_ctrl Instance control structure + **********************************************************************************************************************/ +static void r_tim_w_unfreeze (tim_w_instance_ctrl_t * const p_instance_ctrl) +{ +#if BSP_FEATURE_TIM_W_SUPPORTS_PAUSE_NATIVELY + p_instance_ctrl->p_reg->TIMER_PAUSE_REG = 0U; +#else + + /* Calculate the freeze bit corresponding to the channel. + * The range of RESET_FREEZE_REG_b.FRZ_SWTIM..FRZ_SWTIM8 is [1..8]. The channel range is [0..7]. + */ + uint32_t freeze_bit = p_instance_ctrl->p_cfg->channel + 1; + CRG_TOP->RESET_FREEZE_REG = (1 << freeze_bit); +#endif +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to TIM_W instance control block + * @param[in] event Event code + * @param[in] capture Event capture counts (if applicable) + **********************************************************************************************************************/ +static void r_tim_w_call_callback (tim_w_instance_ctrl_t * p_ctrl, uint8_t event, uint32_t capture) +{ + timer_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = (timer_event_t) event; + p_args->capture = capture; + p_args->p_context = p_ctrl->p_context; + p_ctrl->p_callback(p_args); + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void r_tim_w_ccm_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t capture_val = 0U; + timer_event_t callback_event = (timer_event_t) 0U; + +#if BSP_FEATURE_TIM_W_HAS_IRQ_PER_CAPTURE_CHANNEL + tim_w_extended_cfg_t * p_extend = (tim_w_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + timer_event_t event_base = TIMER_EVENT_COMPARE_A; + + for (uint8_t index = 0; index < p_extend->p_ccm_cfg->ccm_channel_size; index++) + { + if (p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].ccm_operation_irq == irq) + { + if (TIM_W_CCM_OPERATION_CAPTURE == p_extend->p_ccm_cfg->p_ccm_channel_cfg[index].operation) + { + event_base = TIMER_EVENT_CAPTURE_A; + } + + callback_event = (timer_event_t) ((uint32_t) event_base + (uint32_t) index); + + /* Get the corresponding captured snapshot */ + capture_val = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO_REG[index]; + + /* + * Since this isr is called for one ccm event at a time, + * we can break and exit the loop on the first irq we find that triggered + * the ISR. + */ + break; + } + } + +#else + + /* Get captured value. */ + if (true == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_GPIO1_EVENT_PENDING) + { + callback_event = TIMER_EVENT_CAPTURE_A; + capture_val = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO1_REG; + p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG_b.TIM_CLEAR_GPIO1_EVENT = true; + } + else if (true == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_GPIO2_EVENT_PENDING) + { + callback_event = TIMER_EVENT_CAPTURE_B; + capture_val = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO2_REG; + p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG_b.TIM_CLEAR_GPIO2_EVENT = true; + } + else if (true == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_GPIO3_EVENT_PENDING) + { + callback_event = TIMER_EVENT_CAPTURE_C; + capture_val = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO3_REG; + p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG_b.TIM_CLEAR_GPIO3_EVENT = true; + } + else if (true == p_instance_ctrl->p_reg->TIMER_STATUS_REG_b.TIM_GPIO4_EVENT_PENDING) + { + callback_event = TIMER_EVENT_CAPTURE_D; + capture_val = p_instance_ctrl->p_reg->TIMER_CAPTURE_GPIO4_REG; + p_instance_ctrl->p_reg->TIMER_CLEAR_GPIO_EVENT_REG_b.TIM_CLEAR_GPIO4_EVENT = true; + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + p_instance_ctrl->p_reg->TIMER_CLEAR_IRQ_REG = 0; +#endif + if (NULL != p_instance_ctrl->p_callback) + { + r_tim_w_call_callback(p_instance_ctrl, callback_event, capture_val); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void r_tim_w_generic_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + timer_event_t event; + uint32_t timer_status = p_instance_ctrl->p_reg->TIMER_STATUS_REG; + + /* Store the event that caused the generic irq + * and clear the equivalent status register + */ + if (timer_status & TIMER_TIMER_STATUS_REG_TIM_IRQ_PULSE_STATUS_Msk) + { + event = TIMER_EVENT_PULSE_CNT_CYCLE_END; +#if BSP_MCU_GROUP_RA6W1 + p_instance_ctrl->p_reg->TIMER_CLEAR_IRQ_PULSE_REG_b.TIM_CLEAR_PULSE_IRQ = 1U; +#else + p_instance_ctrl->p_reg->TIMER_CLEAR_REG = TIMER_TIMER_CLEAR_REG_TIM_CLEAR_IRQ_PULSE_STATUS_Msk; +#endif + } + +#if BSP_FEATURE_TIM_W_SUPPORTS_SEQ_CAPTURES + else if (timer_status & TIMER_TIMER_STATUS_REG_TIM_IRQ_SEQ_STATUS_Msk) //! + { + event = TIMER_EVENT_SEQUENTIAL_CAPTURE_CYCLE_END; + p_instance_ctrl->p_reg->TIMER_CLEAR_REG = TIMER_TIMER_CLEAR_REG_TIM_CLEAR_IRQ_SEQ_STATUS_Msk; + } +#endif + else /* Counter has wrapped around */ + { + event = TIMER_EVENT_CYCLE_END; +#if BSP_MCU_GROUP_RA6W1 + p_instance_ctrl->p_reg->TIMER_CLEAR_IRQ_REG = 1U; +#else + p_instance_ctrl->p_reg->TIMER_CLEAR_REG = TIMER_TIMER_CLEAR_REG_TIM_CLEAR_IRQ_STATUS_Msk; +#endif + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqClearPending(irq); + + if (NULL != p_instance_ctrl->p_callback) + { + r_tim_w_call_callback(p_instance_ctrl, event, 0); + } + + /* Clear pending IRQ a second time after callback to account for repeated interrupts from 0 period setting. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + R_BSP_IrqClearPending(irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#if BSP_FEATURE_TIM_W_SUPPORTS_OVERFLOW_UNDERFLOW + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void r_tim_w_counter_overflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear irq status bit */ + p_instance_ctrl->p_reg->TIMER_CLEAR_REG = TIMER_TIMER_CLEAR_REG_TIM_CLEAR_IRQ_STATUS_Msk; + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + + if (NULL != p_instance_ctrl->p_callback) + { + r_tim_w_call_callback(p_instance_ctrl, TIMER_EVENT_OVERFLOW, 0); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * Clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void r_tim_w_counter_underflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + tim_w_instance_ctrl_t * p_instance_ctrl = (tim_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + + /* Clear irq status bit */ + p_instance_ctrl->p_reg->TIMER_CLEAR_REG = TIMER_TIMER_CLEAR_REG_TIM_CLEAR_IRQ_STATUS_Msk; + + if (NULL != p_instance_ctrl->p_callback) + { + r_tim_w_call_callback(p_instance_ctrl, TIMER_EVENT_UNDERFLOW, 0); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_uart_w/r_uart_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_uart_w/r_uart_w.c new file mode 100644 index 000000000000..2004d3a93a9d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_uart_w/r_uart_w.c @@ -0,0 +1,2065 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_uart_w.h" +#if UART_W_DMA_SUPPORT_ENABLE == 1 + #include "r_dmac_w.h" +#endif +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + #include "rm_pmgr_w_instance.h" + #endif +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* UART number */ +#define UART_W_INDEX_MAX (2U) +#define UART_W_MASK_9BITS (0x01FFU) +#define COEFFICIENT_10 (10U) +#define COEFFICIENT_1000 (1000U) +#if !BSP_MCU_GROUP_RA6W1 + #define UART_W_DATA_BITS_9 0 +#endif + +/* UART interrupt ID */ +#define UART_W_INTR_ID_NO_PEND (0x00) +#define UART_W_INTR_MDM_STATUS (UART_UART_MIS_REG_RIMMIS_Msk | UART_UART_MIS_REG_CTSMMIS_Msk | \ + UART_UART_MIS_REG_DCDMMIS_Msk | UART_UART_MIS_REG_DSRMMIS_Msk) +#define UART_W_INTR_ID_TI (UART_UART_MIS_REG_TXMIS_Msk) +#define UART_W_INTR_ID_RDI (UART_UART_MIS_REG_RXMIS_Msk) +#define UART_W_INTR_ID_RLSI (UART_UART_MIS_REG_FEMIS_Msk | UART_UART_MIS_REG_PEMIS_Msk | \ + UART_UART_MIS_REG_BEMIS_Msk | UART_UART_MIS_REG_OEMIS_Msk) +#define UART_W_INTR_ID_TIMEOUT (UART_UART_MIS_REG_RTMIS_Msk) + +#define UART_W_INTR_MASK (UART_UART_MIS_REG_RIMMIS_Msk | UART_UART_MIS_REG_CTSMMIS_Msk | \ + UART_UART_MIS_REG_DCDMMIS_Msk | UART_UART_MIS_REG_DSRMMIS_Msk | \ + UART_UART_MIS_REG_RXMIS_Msk | UART_UART_MIS_REG_TXMIS_Msk | \ + UART_UART_MIS_REG_RTMIS_Msk | UART_UART_MIS_REG_FEMIS_Msk | \ + UART_UART_MIS_REG_PEMIS_Msk | UART_UART_MIS_REG_BEMIS_Msk | \ + UART_UART_MIS_REG_OEMIS_Msk) + +#define UART_W_INTR_CLEAR_MASK (UART_UART_ICR_REG_RIMIC_Msk | UART_UART_ICR_REG_CTSMIC_Msk | \ + UART_UART_ICR_REG_DCDMIC_Msk | UART_UART_ICR_REG_DSRMIC_Msk | \ + UART_UART_ICR_REG_RXIC_Msk | UART_UART_ICR_REG_TXIC_Msk | \ + UART_UART_ICR_REG_RTIC_Msk | UART_UART_ICR_REG_FEIC_Msk | \ + UART_UART_ICR_REG_PEIC_Msk | UART_UART_ICR_REG_BEIC_Msk | \ + UART_UART_ICR_REG_OEIC_Msk) + +#define UART_W_EVENT_NO_EVENT (0) + +/* No limit to the number of bytes to read or write if DMA is not used. */ +#define UART_W_MAX_READ_WRITE_NO_DMA (0xFFFFFFFFU) + +/* "UART" in ASCII. Used to determine if the control block is open. */ +#define UART_W_OPEN (0x55655A5AU) +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR == 1 + #define UART_W_SLEEP (0xAAAAAAAAU) + #endif +#endif + +#define UART_W_INT_MASK (0xFFFU) +#define UART_W_FRA_MASK (0x3FU) + +#define UART_W_REG_SIZE (UART2_BASE - UART_BASE) + +#define UART_W_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define UART_W_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + +/** UART sleep context required by PMGR */ + +typedef struct st_uart_w_pre_sleep_state +{ + uint32_t UART_IBRD_REG; + uint32_t UART_FBRD_REG; +} uart_w_pre_sleep_state_t; + +typedef struct st_r_uart_w_pmgr_context +{ + pmgr_instance_info_t pmgr_info; + pmgr_callback_args_t clbk_args; + uart_w_pre_sleep_state_t state; + pmgr_w_notifier_extend_t pmgr_notifier_ext; + uart_w_instance_ctrl_t * p_ctrl; +} r_uart_w_pmgr_context_t; + #endif +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_uart_w_read_write_param_check(uart_w_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +#if UART_W_DMA_SUPPORT_ENABLE == 1 +static fsp_err_t r_uart_w_dma_config(uart_w_instance_ctrl_t * p_ctrl); +static fsp_err_t r_uart_w_dma_rx_config(uart_w_instance_ctrl_t * p_ctrl); +static fsp_err_t r_uart_w_dma_tx_config(uart_w_instance_ctrl_t * p_ctrl); + +/* ISR call when interrupt is generated */ +void uart_w_dma_handler(dmac_callback_args_t * p_args); + +#endif + +static void r_uart_w_config_set(uart_w_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); +static void r_uart_w_irq_cfg(uart_w_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq); +static void r_uart_w_clear_tx_fifo_intr(uart_w_instance_ctrl_t * const p_ctrl); +static void r_uart_w_baud_set(UART_Type * p_uart_reg, uart_w_baud_setting_t const * const p_baud_setting); +static void r_uart_w_fill_tx_fifo(uart_w_instance_ctrl_t * const p_ctrl, uint32_t size); +static void r_uart_w_call_callback(uart_w_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); +static uint32_t r_uart_w_get_fifo_trigger_len(uart_w_instance_ctrl_t * const p_ctrl, uint32_t fifo_trigger); + +static void r_uart_w_handle_incoming_data(uart_w_instance_ctrl_t * const p_ctrl); +static void r_uart_w_handle_incoming_frame(uart_w_instance_ctrl_t * const p_ctrl); +static void r_uart_w_stop_rx(uart_w_instance_ctrl_t * const p_ctrl); + +#if !BSP_MCU_GROUP_RA6W1 +void hw_clk_enable_uart_w_clk(uint8_t channel); +void hw_clk_disable_uart_w_clk(uint8_t channel); +static uart_w_data_bits_t r_uart_w_get_data_bits(uart_cfg_t const * const p_cfg); +static uart_event_t r_uart_w_get_line_error(uart_w_instance_ctrl_t * const p_ctrl); + +#else +static uart_event_t r_uart_w_get_line_error(uint32_t uart_intr_flag); + + #if CFG_PMGR +static fsp_err_t r_uart_w_enter_sleep(r_uart_w_pmgr_context_t * p_context); +static fsp_err_t r_uart_w_wakeup(r_uart_w_pmgr_context_t * p_context); +static void r_uart_w_pmgr_callback(pmgr_callback_args_t * args); \ + static fsp_err_t r_uart_w_subscribe_for_pmgr_notifications(uart_w_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_uart_w_unsubscribe_from_pmgr_notifications(uart_w_instance_ctrl_t * const p_ctrl); \ + static void r_uart_w_tx_done_timer_cb(TimerHandle_t xTimer); +static uint32_t r_uart_w_get_expected_tx_time_ms(uart_w_instance_ctrl_t * p_ctrl, uint32_t tx_bytes); + + #endif +#endif + +/* ISR call when interrupt is generated */ +void uart_w_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* UART_W HAL API mapping for UART interface */ +const uart_api_t g_uart_on_uart_w = +{ + .open = R_UART_W_Open, + .close = R_UART_W_Close, + .write = R_UART_W_Write, + .read = R_UART_W_Read, + .infoGet = R_UART_W_InfoGet, + .baudSet = R_UART_W_BaudSet, + .communicationAbort = R_UART_W_Abort, + .callbackSet = R_UART_W_CallbackSet, + .readStop = R_UART_W_ReadStop, +#if BSP_MCU_GROUP_RA6W1 + .receiveSuspend = R_UART_W_ReceiveSuspend, + .receiveResume = R_UART_W_ReceiveResume, +#endif +}; + +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + #define R_UART_W_MAX_CHANNELS __builtin_popcount(BSP_FEATURE_UART_W_VALID_CHANNEL_MASK) + +// Min time possible is 1 rtos tic ~ 2ms + #define R_UART_W_TX_TIME_MIN_MS 2 + +/* Keep UART PMGR context here */ +static r_uart_w_pmgr_context_t g_uart_pmgr_context[R_UART_W_MAX_CHANNELS]; + + #define UART_TX_DONE_TIMER_NAME "UART_TX_DONE" + #define UART_TX_DONE_TIMER_DEFAULT_TIMEOUT_TICKS pdMS_TO_TICKS(50) + #endif +#endif + +/*******************************************************************************************************************//** + * @addtogroup UART_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Data bits specified is not supported by the driver. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_UART_W_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((uart_w_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(UART_W_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + #if !BSP_MCU_GROUP_RA6W1 + FSP_ERROR_RETURN(UART_W_DATA_BITS_9 < p_cfg->data_bits, FSP_ERR_INVALID_ARGUMENT); + #endif + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_UART_W_VALID_CHANNEL_MASK & (1U << (p_cfg->channel + UART_W_CHANNEL_OFFSET)), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ASSERT(p_cfg->rxi_irq >= 0); + + #if BSP_MCU_GROUP_RA6W3 + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(((uart_w_extended_cfg_t *) p_cfg->p_extend)->gen_irq >= 0); + #endif + + #if UART_W_DMA_SUPPORT_ENABLE == 1 + if (p_cfg->p_transfer_tx) + { + const dmac_extended_cfg_t * p_extend_tx = p_cfg->p_transfer_tx->p_cfg->p_extend; + + /* UART TX should occupy odd DMA channels */ + FSP_ASSERT((uint32_t) p_extend_tx->channel & 1); + } + + if (p_cfg->p_transfer_rx) + { + const dmac_extended_cfg_t * p_extend_rx = p_cfg->p_transfer_rx->p_cfg->p_extend; + + /* UART RX should occupy even DMA channels */ + FSP_ASSERT(!((uint32_t) p_extend_rx->channel & 1)); + } + #endif +#endif + + /* Get the register address of the channel. */ + p_ctrl->p_reg = (UART_Type *) (UART_BASE + (UART_W_REG_SIZE * p_cfg->channel)); + + /* Initialize uart_ctrl_t */ + p_ctrl->fifo_depth = BSP_FEATURE_UART_W_FIFO_DEPTH; + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + + /* Configure the interrupts. */ + r_uart_w_irq_cfg(p_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#if !BSP_MCU_GROUP_RA6W1 + r_uart_w_irq_cfg(p_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); +#endif + +#if BSP_MCU_GROUP_RA6W3 + r_uart_w_irq_cfg(p_ctrl, ((uart_w_extended_cfg_t *) p_cfg->p_extend)->gen_ipl, + ((uart_w_extended_cfg_t *) p_cfg->p_extend)->gen_irq); +#endif + + hw_clk_enable_uart_w_clk(p_cfg->channel); + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::uart_w_extended_cfg_t. */ + r_uart_w_config_set(p_ctrl, p_cfg); + +#if UART_W_DMA_SUPPORT_ENABLE == 1 + + /* Config dma rx/tx */ + r_uart_w_dma_config(p_ctrl); +#endif + +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + p_ctrl->uart_tx_done_timer = xTimerCreate(UART_TX_DONE_TIMER_NAME, + UART_TX_DONE_TIMER_DEFAULT_TIMEOUT_TICKS, + pdFALSE, + (void *) p_ctrl, + r_uart_w_tx_done_timer_cb); + FSP_ASSERT(p_ctrl->uart_tx_done_timer); + r_uart_w_subscribe_for_pmgr_notifications((uart_w_instance_ctrl_t *) p_ctrl); + #endif +#endif + + p_ctrl->open = UART_W_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Reduces power consumption. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UART_W_Close (uart_ctrl_t * const p_api_ctrl) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + p_ctrl->fifo_depth = 0; + +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + r_uart_w_unsubscribe_from_pmgr_notifications((uart_w_instance_ctrl_t *) p_ctrl); + xTimerDelete(p_ctrl->uart_tx_done_timer, 0); + #endif +#endif + + /* Disable irq. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#endif + + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->UART_FR_REG_b.BUSY, 0); + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 0; + FSP_CRITICAL_SECTION_EXIT; + + hw_clk_disable_uart_w_clk(p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_UART_W_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; +#if UART_W_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = FSP_SUCCESS; +#endif +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + uint32_t expected_tx_time_ms; + #endif +#endif + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + err = r_uart_w_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); +#endif + + p_ctrl->tx_src_bytes = bytes; + p_ctrl->p_tx_src = p_src; + +#if UART_W_DMA_SUPPORT_ENABLE == 1 + + /* DMA mode,transfer tx should be set */ + if (p_ctrl->p_cfg->p_transfer_tx) + { + r_uart_w_dma_tx_config(p_ctrl); + } + else +#endif + { +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 0; + R_BSP_IrqEnable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 0; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); +#endif + + /* If the fifo is not used the first write will be done from this function. Subsequent writes will be done + * from uart isr. */ + uint32_t cnt = 1; + + /* Is FIFO enabled for the channel */ + if (p_ctrl->p_reg->UART_LCR_H_REG_b.FEN) + { + cnt = p_ctrl->tx_src_bytes > p_ctrl->fifo_depth ? p_ctrl->fifo_depth : p_ctrl->tx_src_bytes; + } + +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + if (p_ctrl->tx_onging_flag == false) + { + RM_PMGR_W_add_sleep_constraint(RM_PMGR_W_get_ctrl(), PMGR_CONSTRAINT_SLEEP_PROHIBITED); + } + p_ctrl->tx_onging_flag = true; + #endif +#endif + r_uart_w_fill_tx_fifo(p_ctrl, cnt); + + if (!p_ctrl->tx_src_bytes) + { +#if BSP_MCU_GROUP_RA6W1 + #if (CFG_PMGR == 1) + expected_tx_time_ms = r_uart_w_get_expected_tx_time_ms(p_ctrl, bytes); + if (xTimerIsTimerActive(p_ctrl->uart_tx_done_timer) == pdFALSE) + { + xTimerChangePeriod(p_ctrl->uart_tx_done_timer, pdMS_TO_TICKS(expected_tx_time_ms), portMAX_DELAY); + xTimerStart(p_ctrl->uart_tx_done_timer, portMAX_DELAY); + } + #endif +#endif + if (p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + } + else + { +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 1; + R_BSP_IrqEnableNoClear(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 1; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); +#endif + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_UART_W_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + err = r_uart_w_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); +#endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + +#if UART_W_DMA_SUPPORT_ENABLE == 1 + + /* DMA mode, transfer rx set */ + if (p_ctrl->p_cfg->p_transfer_rx) + { + r_uart_w_dma_rx_config(p_ctrl); + #if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 0; + R_BSP_IrqEnable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + #else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 0; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + #endif + } + else +#endif + { + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Is FIFO enabled for the channel */ + if (p_ctrl->p_reg->UART_LCR_H_REG_b.FEN && (r_uart_w_get_fifo_trigger_len(p_ctrl, p_extend->rx_fifo_trigger) > + p_ctrl->rx_dest_bytes)) + { +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 1; + R_BSP_IrqEnableNoClear(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 1; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); +#endif + } + } + + return err; +} + +/*******************************************************************************************************************/ /** + * Updates the Uart configuration. p_baud_setting is a pointer to a uart_w_baud_setting_t structure. + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Uart been reconfiugred was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UART_W_ConfSet (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); +#endif + p_ctrl->p_cfg = p_cfg; + + /* Apply new baud rate register settings. */ + r_uart_w_config_set(p_ctrl, p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UART_W_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if UART_W_CFG_PARAM_CHECKING_ENABLE + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = UART_W_MAX_READ_WRITE_NO_DMA; + p_info->write_bytes_max = UART_W_MAX_READ_WRITE_NO_DMA; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a uart_w_baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UART_W_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + uart_w_baud_setting_t * p_baud = (uart_w_baud_setting_t *) p_baud_setting; +#if BSP_MCU_GROUP_RA6W1 + uint32_t lcr_h_reg_b_fen; + uint32_t RS485EN_REG; + uint32_t UART_IFLS_REG; + uint32_t UART_LCR_H_REG; + uint32_t UART_CR_REG; +#endif + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(p_baud); +#endif + +#if BSP_MCU_GROUP_RA6W1 + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 0; + r_uart_w_clear_tx_fifo_intr(p_ctrl); + RS485EN_REG = p_ctrl->p_reg->UART_RS485EN_REG; + p_ctrl->p_reg->UART_RS485EN_REG = RS485EN_REG; + UART_IFLS_REG = p_ctrl->p_reg->UART_IFLS_REG; + p_ctrl->p_reg->UART_IFLS_REG = UART_IFLS_REG; + + lcr_h_reg_b_fen = p_ctrl->p_reg->UART_LCR_H_REG_b.FEN; + p_ctrl->p_reg->UART_LCR_H_REG_b.FEN = lcr_h_reg_b_fen & + (UART_UART_LCR_H_REG_FEN_Msk >> UART_UART_LCR_H_REG_FEN_Pos); +#endif + + /* Apply new baud rate register settings. */ + r_uart_w_baud_set(p_ctrl->p_reg, p_baud); +#if BSP_MCU_GROUP_RA6W1 + p_ctrl->p_reg->UART_WA_REG_b.WAE = 0; + UART_LCR_H_REG = p_ctrl->p_reg->UART_LCR_H_REG; + p_ctrl->p_reg->UART_LCR_H_REG = UART_LCR_H_REG; + UART_CR_REG = p_ctrl->p_reg->UART_CR_REG; + p_ctrl->p_reg->UART_CR_REG = UART_CR_REG; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 1; + FSP_CRITICAL_SECTION_EXIT; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_W_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_UART_W_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + p_ctrl->tx_src_bytes = 0U; +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 0; + R_BSP_IrqEnable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.TXIM = 0; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); +#endif + +#if UART_W_DMA_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_reg->UART_DMACR_REG_b.TXDMAE = 0; + + err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } +#endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + p_ctrl->rx_dest_bytes = 0U; + +#if UART_W_DMA_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_reg->UART_DMACR_REG_b.RXDMAE = 0; + #if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + R_BSP_IrqEnableNoClear(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + #else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); + #endif + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_UART_W_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if UART_W_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : (void (*)(uart_callback_args_t *))cmse_nsfptr_create( + p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_UART_W_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + *remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0U; +#if UART_W_DMA_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_reg->UART_DMACR_REG_b.RXDMAE = 0; + + R_BSP_IrqDisable(irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + R_BSP_IrqEnable(irq); + + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } +#endif + + return FSP_SUCCESS; +} + +#if BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************//** + * Provides API to stop any RX activity. Reception isn't enabled after receiveSuspend(). No UART_EVENT_RX_CHAR event is + * generated and character reception is suspended until next call receiveResume(). + * Implements @ref uart_api_t::receiveSuspend + * + * @retval FSP_SUCCESS UART RX activity suspended successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_STATE Hardware flow control isn't enabled for this channel. + * @retval FSP_ERR_UNSUPPORTED Operation isn't supported for current configuration. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_UART_W_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + + #if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + FSP_ERROR_RETURN(UART_W_AUTO_FLOW_CONTROL_ENABLED == p_extend->flow_control, FSP_ERR_INVALID_STATE); + #endif + + #if !UART_W_DMA_SUPPORT_ENABLE + + /* Enable RX interrupts */ + + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 0; + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 0; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); + + return FSP_SUCCESS; + #else + + return FSP_ERR_UNSUPPORTED; + #endif +} + +/*******************************************************************************************************************//** + * Provides API to resume receiving of data over UART. Suspended read() operation is resumed. UART_EVENT_RX_CHAR event + * is generated upon receiving character without prior read() operation. + * Implements @ref uart_api_t::receiveResume + * + * @retval FSP_SUCCESS UART RX activity resumed successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_STATE Hardware flow control isn't enabled for this channel. + * @retval FSP_ERR_UNSUPPORTED Operation isn't supported for current configuration. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_UART_W_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + + #if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + FSP_ERROR_RETURN(UART_W_AUTO_FLOW_CONTROL_ENABLED == p_extend->flow_control, FSP_ERR_INVALID_STATE); + #endif + + #if !UART_W_DMA_SUPPORT_ENABLE + + /* Enable RX interrupts */ + + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = !!p_ctrl->p_reg->UART_LCR_H_REG_b.FEN; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + + return FSP_SUCCESS; + #else + + return FSP_ERR_UNSUPPORTED; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Invalid baudrate + **********************************************************************************************************************/ +fsp_err_t R_UART_W_BaudCalculate (uint32_t baudrate, uart_w_baud_setting_t * const p_baud_setting) +{ +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + +#if !BSP_MCU_GROUP_RA6W3 + uint64_t frac_coeff = COEFFICIENT_1000; +#endif + uint64_t div_fraction_part; + uint64_t freq_hz; + uint64_t div_integer_part; + uint64_t frac_hz; + + freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_UART); + div_integer_part = freq_hz / (16 * baudrate); + frac_hz = freq_hz - div_integer_part * 16 * baudrate; +#if !BSP_MCU_GROUP_RA6W3 + div_fraction_part = (((frac_hz * frac_coeff) / (16 * baudrate)) * 64 + 5 * frac_coeff / 10) / frac_coeff; +#else + div_fraction_part = (frac_hz * 64U + (16U * baudrate) / 2U) / (16U * baudrate); + if (div_fraction_part >= 64U) + { + div_fraction_part = 0U; + div_integer_part++; + } +#endif + + p_baud_setting->fra_baud = div_fraction_part & UART_W_FRA_MASK; + p_baud_setting->int_baud = div_integer_part & UART_W_INT_MASK; + + return FSP_SUCCESS; +} + +#if BSP_MCU_GROUP_RA6W1 +bool R_UART_W_IsWritting (uart_ctrl_t * const p_api_ctrl) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + + return p_ctrl->tx_src_bytes || !p_ctrl->p_reg->UART_FR_REG_b.TXFE || p_ctrl->p_reg->UART_FR_REG_b.BUSY; +} + +bool R_UART_W_IsOpened (uart_ctrl_t * const p_api_ctrl) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_api_ctrl; + + return p_ctrl->open == UART_W_OPEN; +} + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup UART_W) + **********************************************************************************************************************/ +#if !BSP_MCU_GROUP_RA6W1 + +/** + * \brief Enable clock for specific UART channel + * + * \param[in] channel UART channel to activate clock + */ +void hw_clk_enable_uart_w_clk (uint8_t channel) +{ + // CRG_TOP->CLK_AMBA_REG_b.PERI_CLK_ENABLE = 1; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case 0: + { + CRG_COM->CLK_COM_REG_b.UART_ENABLE = 1; + break; + } + + case 1: + { + CRG_COM->CLK_COM_REG_b.UART2_ENABLE = 1; + break; + } + + case 2: + { + CRG_COM->CLK_COM_REG_b.UART3_ENABLE = 1; + break; + } + + case 3: + { + CRG_COM->CLK_COM_REG_b.UART4_ENABLE = 1; + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; +} + +/** + * \brief Disable clock for specific UART channel + * + * \param[in] channel UART channel to deactivate clock + */ +void hw_clk_disable_uart_w_clk (uint8_t channel) +{ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + switch (channel) + { + case 0: + { + CRG_COM->CLK_COM_REG_b.UART_ENABLE = 0; + break; + } + + case 1: + { + CRG_COM->CLK_COM_REG_b.UART2_ENABLE = 0; + break; + } + + case 2: + { + CRG_COM->CLK_COM_REG_b.UART3_ENABLE = 0; + break; + } + + case 3: + { + CRG_COM->CLK_COM_REG_b.UART4_ENABLE = 0; + break; + } + } + + FSP_CRITICAL_SECTION_EXIT; +} + +#endif + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ +#if (UART_W_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + **********************************************************************************************************************/ +static fsp_err_t r_uart_w_read_write_param_check (uart_w_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(UART_W_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +#if UART_W_DMA_SUPPORT_ENABLE == 1 +static fsp_err_t r_uart_w_dma_config (uart_w_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (p_transfer_tx) + { + p_transfer_tx->p_cfg->p_info->transfer_settings_word = UART_W_TX_TRANSFER_SETTINGS; + p_transfer_tx->p_cfg->p_info->p_dest = (void *) &(p_ctrl->p_reg->UART_DR_REG); + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (p_transfer_rx) + { + p_transfer_rx->p_cfg->p_info->transfer_settings_word = UART_W_RX_TRANSFER_SETTINGS; + p_transfer_rx->p_cfg->p_info->p_src = (void *) &(p_ctrl->p_reg->UART_DR_REG); + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + return err; +} + +static fsp_err_t r_uart_w_dma_rx_config (uart_w_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + if (p_ctrl->p_cfg->p_transfer_rx) + { + /* Configure the receive DMA instance. */ + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = (uint16_t) p_ctrl->rx_dest_bytes; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) p_ctrl->p_rx_dest; + if (NULL == p_ctrl->p_rx_dest) + { + static uint32_t dummy_rx = 0; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = &dummy_rx; + } + + err = p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->p_reg->UART_DMACR_REG_b.RXDMAE = 1; + } + + return err; +} + +static fsp_err_t r_uart_w_dma_tx_config (uart_w_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* Configure the transmit DMA instance. */ + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = (uint16_t) p_ctrl->tx_src_bytes; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = p_ctrl->p_tx_src; + + if (NULL == p_ctrl->p_tx_src) + { + static uint32_t dummy_tx = 0; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = &dummy_tx; + } + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->p_reg->UART_DMACR_REG_b.TXDMAE = 1; + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_ctrl Pointer to UART channel control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_uart_w_irq_cfg (uart_w_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + R_BSP_IrqCfgEnable(irq, ipl, p_ctrl); +} + +static void r_uart_w_baud_set (UART_Type * p_uart_reg, uart_w_baud_setting_t const * const p_baud_setting) +{ + uint32_t uart_enabled = p_uart_reg->UART_CR_REG_b.UARTEN; + + /* Disable UART channel before changing the baud rate */ + p_uart_reg->UART_CR_REG_b.UARTEN = 0; + + p_uart_reg->UART_IBRD_REG_b.BAUD_DIVINT = (p_baud_setting->int_baud & UART_W_INT_MASK); + p_uart_reg->UART_FBRD_REG_b.BAUD_DIVFRAC = (p_baud_setting->fra_baud & UART_W_FRA_MASK); + + /* Clear interrupts before re-enabling the channel */ + p_uart_reg->UART_ICR_REG = UART_W_INTR_CLEAR_MASK; + + p_uart_reg->UART_CR_REG_b.UARTEN = uart_enabled & UART_UART_CR_REG_UARTEN_Msk; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART channel control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_uart_w_call_callback (uart_w_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* The p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + uart_prv_ns_callback p_callback = (uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * ISR called when interrupt is generated. + **********************************************************************************************************************/ +#if UART_W_DMA_SUPPORT_ENABLE == 1 +void uart_w_dma_handler (dmac_callback_args_t * p_args) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) p_args->p_context; + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + if (p_transfer_rx != NULL) + { + const dmac_extended_cfg_t * p_extend_rx = p_transfer_rx->p_cfg->p_extend; + if ((p_args->event == DMAC_B_EVENT_TRANSFER_COMPLETE) && (p_args->channel == p_extend_rx->channel)) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + p_ctrl->rx_dest_bytes = 0; + + /* TODO Partial read */ + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + + p_ctrl->p_reg->UART_DMACR_REG_b.RXDMAE = 0; + #if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + R_BSP_IrqEnableNoClear(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + #else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RXIM = 1; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); + #endif + } + } + + if (p_transfer_tx != NULL) + { + const dmac_extended_cfg_t * p_extend_tx = p_transfer_tx->p_cfg->p_extend; + if ((p_args->event == DMAC_B_EVENT_TRANSFER_COMPLETE) && (p_args->channel == p_extend_tx->channel)) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + p_ctrl->tx_src_bytes = 0; + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + + p_ctrl->p_reg->UART_DMACR_REG_b.TXDMAE = 0; + } + } +} + +#endif + +/*******************************************************************************************************************//** + * ISR called when interrupt is generated. + **********************************************************************************************************************/ +void uart_w_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + volatile uint32_t uart_intr_flag = (p_ctrl->p_reg->UART_MIS_REG & UART_W_INTR_MASK); + UART_Type * p_uart_reg = p_ctrl->p_reg; + +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + uint32_t expected_tx_time_ms; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + #endif +#endif +#if BSP_MCU_GROUP_RA6W3 + volatile uint32_t * ielsrn_reg = ICU_IELSRn_REG(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting. */ + R_BSP_IrqStatusClear(irq); +#endif + + while (UART_W_INTR_ID_NO_PEND != uart_intr_flag) + { + if ((UART_W_INTR_ID_RDI | UART_W_INTR_ID_TIMEOUT) & uart_intr_flag) + { + r_uart_w_handle_incoming_data(p_ctrl); + + p_uart_reg->UART_ICR_REG = (UART_UART_ICR_REG_RXIC_Msk | UART_UART_ICR_REG_RTIC_Msk); +#if BSP_MCU_GROUP_RA6W3 + switch (p_ctrl->p_cfg->channel) + { + case UART1_CHANNEL_NUM: + { + FSP_REG_VAR_FIELD_SET(ICU, ICU_IELSR0_REG, ICU_IELS, *ielsrn_reg, ICU_EVENT_UARTWB1_IRQ); + break; + } + + case UART2_CHANNEL_NUM: + { + FSP_REG_VAR_FIELD_SET(ICU, ICU_IELSR0_REG, ICU_IELS, *ielsrn_reg, ICU_EVENT_UARTWB2_IRQ); + break; + } + + case UART3_CHANNEL_NUM: + { + FSP_REG_VAR_FIELD_SET(ICU, ICU_IELSR0_REG, ICU_IELS, *ielsrn_reg, ICU_EVENT_UARTWB3_IRQ); + break; + } + + case UART4_CHANNEL_NUM: + { + FSP_REG_VAR_FIELD_SET(ICU, ICU_IELSR0_REG, ICU_IELS, *ielsrn_reg, ICU_EVENT_UARTWB4_IRQ); + break; + } + } +#endif + } + else if (UART_W_INTR_ID_TI & uart_intr_flag) + { + uint32_t cnt = 1; /* The data sent should be at least 1 */ + + p_uart_reg->UART_ICR_REG_b.TXIC = 1; + + /* Is FIFO enabled for the channel */ + if (p_uart_reg->UART_LCR_H_REG_b.FEN) + { + cnt = p_ctrl->tx_src_bytes > p_ctrl->fifo_depth / 2 ? p_ctrl->fifo_depth / 2 : p_ctrl->tx_src_bytes; + } + + r_uart_w_fill_tx_fifo(p_ctrl, cnt); + + if (!p_ctrl->tx_src_bytes) + { + p_uart_reg->UART_IMSC_REG_b.TXIM = 0; +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR + expected_tx_time_ms = + r_uart_w_get_expected_tx_time_ms(p_ctrl, + r_uart_w_get_fifo_trigger_len(p_ctrl, p_extend->rx_fifo_trigger)); + if (xTimerIsTimerActive(p_ctrl->uart_tx_done_timer) == pdFALSE) + { + xTimerChangePeriodFromISR(p_ctrl->uart_tx_done_timer, + pdMS_TO_TICKS(expected_tx_time_ms), + &xHigherPriorityTaskWoken); + xTimerStartFromISR(p_ctrl->uart_tx_done_timer, &xHigherPriorityTaskWoken); + } + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + #endif +#endif + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + } + } + else if (UART_W_INTR_ID_RLSI & uart_intr_flag) + { + /* Return Line status. */ +#if BSP_MCU_GROUP_RA6W1 + uart_event_t error_code = r_uart_w_get_line_error(uart_intr_flag); +#else + uart_event_t error_code = r_uart_w_get_line_error(p_ctrl); +#endif + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, error_code); + } + +#if BSP_MCU_GROUP_RA6W1 + + /* Need to pop corrupted byte from the top of the FIFO */ + if (uart_intr_flag & (UART_UART_MIS_REG_FEMIS_Msk | \ + UART_UART_MIS_REG_PEMIS_Msk | \ + UART_UART_MIS_REG_BEMIS_Msk)) + { + (void) (*(volatile uint8_t *) &p_ctrl->p_reg->UART_DR_REG); + + /* Clear irq status register condition. */ + p_uart_reg->UART_RSR_REG = 0; + } + +#else + + /* Clear irq status register condition. */ + p_uart_reg->UART_RSR_REG = 0; +#endif + p_uart_reg->UART_ICR_REG = (UART_UART_ICR_REG_FEIC_Msk | UART_UART_ICR_REG_PEIC_Msk | \ + UART_UART_ICR_REG_BEIC_Msk | UART_UART_ICR_REG_OEIC_Msk); + } + else if (UART_W_INTR_MDM_STATUS & uart_intr_flag) + { + p_uart_reg->UART_ICR_REG = (UART_UART_ICR_REG_RIMIC_Msk | UART_UART_ICR_REG_CTSMIC_Msk | \ + UART_UART_ICR_REG_DCDMIC_Msk | UART_UART_ICR_REG_DSRMIC_Msk); + } + else + { + /* Clear unidentified interrupts */ + p_uart_reg->UART_ICR_REG = UART_W_INTR_CLEAR_MASK; + } + + uart_intr_flag = (p_ctrl->p_reg->UART_MIS_REG & UART_W_INTR_MASK); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * Clear pending TX FIFO interrupt. + * + * @param[in] p_ctrl Pointer to UART channel control block + **********************************************************************************************************************/ +static void r_uart_w_clear_tx_fifo_intr (uart_w_instance_ctrl_t * const p_ctrl) +{ + (void) p_ctrl->p_reg->UART_FR_REG_b.TXFE; +} + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to UART channel control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_uart_w_config_set (uart_w_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_cfg->p_extend; +#if BSP_MCU_GROUP_RA6W1 + uint32_t data_bits = (uint32_t) p_cfg->data_bits; +#else + uint32_t data_bits = (uint32_t) r_uart_w_get_data_bits(p_cfg); +#endif + + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 0; + + r_uart_w_clear_tx_fifo_intr(p_ctrl); + + /* Enable RS485 */ + p_ctrl->p_reg->UART_RS485EN_REG = ((p_ctrl->p_reg->UART_RS485EN_REG & ~UART_UART_RS485EN_REG_RS485E_Msk) | + (uint32_t) p_extend->rs485_enable << UART_UART_RS485EN_REG_RS485E_Pos); + + if (!(p_ctrl->p_cfg->p_transfer_rx || p_ctrl->p_cfg->p_transfer_tx || p_extend->fifo_enable || + p_extend->flow_control)) + { + p_ctrl->p_reg->UART_LCR_H_REG_b.FEN = 0; + p_ctrl->p_reg->UART_IFLS_REG &= ~(UART_UART_IFLS_REG_RXIFLSEL_Msk | UART_UART_IFLS_REG_TXIFLSEL_Msk); + } + else + { + p_ctrl->p_reg->UART_LCR_H_REG_b.FEN = 1; + p_ctrl->p_reg->UART_IFLS_REG = ((p_ctrl->p_reg->UART_IFLS_REG & + ~(UART_UART_IFLS_REG_RXIFLSEL_Msk | UART_UART_IFLS_REG_TXIFLSEL_Msk)) | + ((uint32_t) p_extend->rx_fifo_trigger << + UART_UART_IFLS_REG_RXIFLSEL_Pos) | + ((uint32_t) p_extend->tx_fifo_trigger << + UART_UART_IFLS_REG_TXIFLSEL_Pos)); + } + + /* Set the baud rate. */ + r_uart_w_baud_set(p_ctrl->p_reg, p_extend->p_baud_setting); + + p_ctrl->p_reg->UART_CR_REG = ((p_ctrl->p_reg->UART_LCR_H_REG & ~UART_UART_CR_REG_LBE_Msk) | + ((uint32_t) p_extend->loop_back_enable << UART_UART_CR_REG_LBE_Pos) | + UART_UART_CR_REG_RXE_Msk | UART_UART_CR_REG_TXE_Msk); + p_ctrl->p_reg->UART_WA_REG_b.WAE = 0; + + if (UART_PARITY_OFF != p_cfg->parity) + { + if (UART_PARITY_ODD == p_cfg->parity) + { + p_ctrl->p_reg->UART_LCR_H_REG = ((p_ctrl->p_reg->UART_LCR_H_REG & ~UART_UART_LCR_H_REG_EPS_Msk) | + UART_UART_LCR_H_REG_PEN_Msk); + } + else + { + p_ctrl->p_reg->UART_LCR_H_REG |= UART_UART_LCR_H_REG_EPS_Msk | UART_UART_LCR_H_REG_PEN_Msk; + } + } + else + { + p_ctrl->p_reg->UART_LCR_H_REG &= ~(UART_UART_LCR_H_REG_PEN_Msk | UART_UART_LCR_H_REG_EPS_Msk); + } + + p_ctrl->p_reg->UART_LCR_H_REG = ((p_ctrl->p_reg->UART_LCR_H_REG & + ~(UART_UART_LCR_H_REG_WLEN_Msk | UART_UART_LCR_H_REG_STP2_Msk)) | + ((uint32_t) p_cfg->stop_bits << UART_UART_LCR_H_REG_STP2_Pos) | + (data_bits << UART_UART_LCR_H_REG_WLEN_Pos)); + p_ctrl->p_reg->UART_CR_REG = ((p_ctrl->p_reg->UART_CR_REG & + ~(UART_UART_CR_REG_RTSEn_Msk | UART_UART_CR_REG_CTSEn_Msk)) | + ((uint32_t) p_extend->flow_control << UART_UART_CR_REG_RTSEn_Pos) | + ((uint32_t) p_extend->flow_control << UART_UART_CR_REG_CTSEn_Pos)); + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 1; + FSP_CRITICAL_SECTION_EXIT; + +#if !UART_W_DMA_SUPPORT_ENABLE + #if BSP_MCU_GROUP_RA6W3 + + /* Enable RX and line status interrupts */ + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG |= (UART_UART_IMSC_REG_FEIM_Msk | UART_UART_IMSC_REG_PEIM_Msk | \ + UART_UART_IMSC_REG_BEIM_Msk | UART_UART_IMSC_REG_OEIM_Msk | \ + UART_UART_IMSC_REG_RXIM_Msk); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = !!p_ctrl->p_reg->UART_LCR_H_REG_b.FEN; + R_BSP_IrqEnable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + #else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG |= (UART_UART_IMSC_REG_FEIM_Msk | UART_UART_IMSC_REG_PEIM_Msk | \ + UART_UART_IMSC_REG_BEIM_Msk | UART_UART_IMSC_REG_OEIM_Msk | \ + UART_UART_IMSC_REG_RXIM_Msk); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = !!p_ctrl->p_reg->UART_LCR_H_REG_b.FEN; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + #endif +#endif +} + +#if !BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************//** + * Return UART data bits configuration. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval UART data bits configuration. + **********************************************************************************************************************/ +static uart_w_data_bits_t r_uart_w_get_data_bits (uart_cfg_t const * const p_cfg) +{ + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_cfg->p_extend; + + if (p_extend->extended_data_bits_enable) + { + return p_extend->data_bits; + } + + if (UART_DATA_BITS_7 == p_cfg->data_bits) + { + return UART_W_DATA_BITS_7; + } + + return UART_W_DATA_BITS_8; +} + +#endif + +/*******************************************************************************************************************//** + * Fill number of bytes from the source buffer pointer. + * + * @param[in] p_ctrl Pointer to UART channel control block + * @param[in] size number of bytes + **********************************************************************************************************************/ +static void r_uart_w_fill_tx_fifo (uart_w_instance_ctrl_t * const p_ctrl, uint32_t size) +{ + for ( ; size; size--) + { + if (p_ctrl->p_reg->UART_FR_REG_b.TXFF) + { + + /* FIFO buffer is full, wait for next interrupt to retry */ + return; + } + + (*(volatile uint8_t *) &p_ctrl->p_reg->UART_DR_REG) = *p_ctrl->p_tx_src; + + p_ctrl->tx_src_bytes--; + p_ctrl->p_tx_src++; + } +} + +/*******************************************************************************************************************//** + * Return the number of bytes required to trigger FIFO event. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] fifo_trigger Trigger level for FIFO operations + * + * @retval The number of bytes corresponding to specified FIFO trigger level. + **********************************************************************************************************************/ +static uint32_t r_uart_w_get_fifo_trigger_len (uart_w_instance_ctrl_t * const p_ctrl, uint32_t fifo_trigger) +{ + switch (fifo_trigger) + { + case UART_W_RX_FIFO_TRIGGER_EIGHTH: + { + return p_ctrl->fifo_depth / 8U; + } + + case UART_W_RX_FIFO_TRIGGER_QUARTER: + { + return p_ctrl->fifo_depth / 4U; + } + + case UART_W_RX_FIFO_TRIGGER_HALF: + { + return p_ctrl->fifo_depth / 2U; + } + + case UART_W_RX_FIFO_TRIGGER_THREE_QUARTERS: + { + return p_ctrl->fifo_depth * 3U / 4U; + } + + case UART_W_RX_FIFO_TRIGGER_SEVEN_EIGHTHS: + { + return p_ctrl->fifo_depth * 7U / 8U; + } + + default: + { + return 1; + } + } +} + +#if BSP_MCU_GROUP_RA6W1 + +/*******************************************************************************************************************/ /** + * Return UART line status event error code. + * + * @retval UART line status event error code. + **********************************************************************************************************************/ +static uart_event_t r_uart_w_get_line_error (uint32_t uart_intr_flag) +{ + uart_event_t error_code = UART_W_EVENT_NO_EVENT; + + if (UART_UART_MIS_REG_FEMIS_Msk & uart_intr_flag) + { + error_code |= UART_EVENT_ERR_FRAMING; + } + + if (UART_UART_MIS_REG_PEMIS_Msk & uart_intr_flag) + { + error_code |= UART_EVENT_ERR_PARITY; + } + + if (UART_UART_MIS_REG_BEMIS_Msk & uart_intr_flag) + { + error_code |= UART_EVENT_BREAK_DETECT; + } + + if (UART_UART_MIS_REG_OEMIS_Msk & uart_intr_flag) + { + error_code |= UART_EVENT_ERR_OVERFLOW; + } + + return error_code; +} + +#else + +/*******************************************************************************************************************//** + * Return UART line status event error code. + * + * @param[in] p_ctrl Pointer to UART channel control block + * + * @retval UART line status event error code. + **********************************************************************************************************************/ +static uart_event_t r_uart_w_get_line_error (uart_w_instance_ctrl_t * const p_ctrl) +{ + uint32_t rsr = p_ctrl->p_reg->UART_RSR_REG; + uart_event_t error_code = UART_W_EVENT_NO_EVENT; + + if (UART_UART_RSR_REG_RSR_FE_Msk & rsr) + { + error_code |= UART_EVENT_ERR_FRAMING; + } + + if (UART_UART_RSR_REG_RSR_PE_Msk & rsr) + { + error_code |= UART_EVENT_ERR_PARITY; + } + + if (UART_UART_RSR_REG_RSR_BE_Msk & rsr) + { + error_code |= UART_EVENT_BREAK_DETECT; + } + + if (UART_UART_RSR_REG_RSR_OE_Msk & rsr) + { + error_code |= UART_EVENT_ERR_OVERFLOW; + } + + return error_code; +} + +#endif + +/*******************************************************************************************************************//** + * Handle incoming UART data. + * + * @param[in] p_ctrl Pointer to UART channel control block + **********************************************************************************************************************/ +static void r_uart_w_handle_incoming_data (uart_w_instance_ctrl_t * const p_ctrl) +{ + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Is FIFO enabled for the channel */ + if (p_ctrl->p_reg->UART_LCR_H_REG_b.FEN) + { + uint32_t byte; + uint32_t cnt = r_uart_w_get_fifo_trigger_len(p_ctrl, p_extend->rx_fifo_trigger); + + for (byte = 0; byte < cnt; byte++) + { + if (p_ctrl->p_reg->UART_FR_REG_b.RXFE) + { + /* No frames left to process */ + break; + } + + r_uart_w_handle_incoming_frame(p_ctrl); + } + } + else + { + if (!p_ctrl->p_reg->UART_FR_REG_b.RXFE) + { + /* We have pending frame */ + r_uart_w_handle_incoming_frame(p_ctrl); + } + } + + if (p_ctrl->p_reg->UART_LCR_H_REG_b.FEN && p_ctrl->rx_dest_bytes) + { + if (r_uart_w_get_fifo_trigger_len(p_ctrl, p_extend->rx_fifo_trigger) > p_ctrl->rx_dest_bytes) + { +#if BSP_MCU_GROUP_RA6W3 + R_BSP_IrqDisable(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 1; + R_BSP_IrqEnableNoClear(((uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->gen_irq); +#else + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + p_ctrl->p_reg->UART_IMSC_REG_b.RTIM = 1; + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); +#endif + } + } +} + +/*******************************************************************************************************************//** + * Handle incoming UART frame. + * + * @param[in] p_ctrl Pointer to UART channel control block + **********************************************************************************************************************/ +static void r_uart_w_handle_incoming_frame (uart_w_instance_ctrl_t * const p_ctrl) +{ + uint8_t data = (*(volatile uint8_t *) &p_ctrl->p_reg->UART_DR_REG); + + /* No pending RX flow. Calling user callback with UART_EVENT_RX_CHAR code */ + if (0 == p_ctrl->rx_dest_bytes) + { + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); + } + } + else + { + *p_ctrl->p_rx_dest = data; + + p_ctrl->p_rx_dest++; + p_ctrl->rx_dest_bytes--; + + if (0 == p_ctrl->rx_dest_bytes) + { + r_uart_w_stop_rx(p_ctrl); + } + } +} + +/*******************************************************************************************************************//** + * Finish current UART RX flow. + * + * @param[in] p_ctrl Pointer to UART channel control block + **********************************************************************************************************************/ +static void r_uart_w_stop_rx (uart_w_instance_ctrl_t * const p_ctrl) +{ + /* Trying to pull all the data remaining */ + while (p_ctrl->rx_dest_bytes) + { + if (p_ctrl->p_reg->UART_FR_REG_b.RXFE) + { + /* No frames left to process */ + break; + } + + /* We have pending frame */ + r_uart_w_handle_incoming_frame(p_ctrl); + } + + p_ctrl->rx_dest_bytes = 0; + + if (NULL != p_ctrl->p_callback) + { + r_uart_w_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } +} + +#if BSP_MCU_GROUP_RA6W1 + #if CFG_PMGR == 1 + +/*******************************************************************************************************************/ /** + * Prepare UART for sleep mode 4/5 + * + * @param[in] p_context Pointer to PMGR interface of UART instance + **********************************************************************************************************************/ +static fsp_err_t r_uart_w_enter_sleep (r_uart_w_pmgr_context_t * p_context) +{ + fsp_err_t err = FSP_SUCCESS; + #if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_context); + #endif + + uart_w_instance_ctrl_t * p_ctrl = p_context->p_ctrl; + FSP_ERROR_RETURN(p_ctrl->open == UART_W_OPEN, FSP_ERR_INVALID_MODE); + + /* Store the baud rate and CR after reset */ + p_context->state.UART_IBRD_REG = p_ctrl->p_reg->UART_IBRD_REG; + p_context->state.UART_FBRD_REG = p_ctrl->p_reg->UART_FBRD_REG; + + p_ctrl->p_reg->UART_CR_REG_b.UARTEN = 0; + + p_ctrl->open = UART_W_SLEEP; + + return err; +} + +/*******************************************************************************************************************/ /** + * Restore UART from wakeup + * + * @param[in] p_context Pointer to PMGR interface of UART instance + **********************************************************************************************************************/ +static fsp_err_t r_uart_w_wakeup (r_uart_w_pmgr_context_t * p_context) +{ + fsp_err_t err = FSP_SUCCESS; + #if (UART_W_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_context); + #endif + uart_w_instance_ctrl_t * p_ctrl = p_context->p_ctrl; + + FSP_ERROR_RETURN(p_ctrl->open == UART_W_SLEEP, FSP_ERR_INVALID_MODE); + + r_uart_w_irq_cfg(p_ctrl, p_ctrl->p_cfg->rxi_ipl, p_ctrl->p_cfg->rxi_irq); + hw_clk_enable_uart_w_clk(p_ctrl->p_cfg->channel); + r_uart_w_config_set(p_ctrl, p_ctrl->p_cfg); + + /* Restore the baud rate - + * Can be modified by setter func so can't be restored as part of r_uart_w_config_set() + */ + p_ctrl->p_reg->UART_IBRD_REG = p_context->state.UART_IBRD_REG; + p_ctrl->p_reg->UART_FBRD_REG = p_context->state.UART_FBRD_REG; + + p_ctrl->open = UART_W_OPEN; + + return err; +} + +static void r_uart_w_pmgr_callback (pmgr_callback_args_t * p_args) +{ + pmgr_instance_info_t * p_pmgr_info = (pmgr_instance_info_t *) p_args->p_instance_info; + + if (p_pmgr_info->power_mode == PMGR_LLD_POWER_MODE_SLEEP4) + { + if (p_args->event == PMGR_EVENT_ENTERING_SLEEP) + { + /* Entering sleep 4/5 - close UART */ + r_uart_w_enter_sleep((r_uart_w_pmgr_context_t *) p_args->p_context); + } + else if (p_args->event == PMGR_EVENT_EXITING_SLEEP) + { + /* Open UART with previous settings */ + r_uart_w_wakeup((r_uart_w_pmgr_context_t *) p_args->p_context); + } + } +} + +static fsp_err_t r_uart_w_subscribe_for_pmgr_notifications (uart_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + + r_uart_w_pmgr_context_t * context = &g_uart_pmgr_context[p_ctrl->p_cfg->channel]; + + context->pmgr_info.power_mode = PMGR_LLD_POWER_MODE_SLEEP4; + context->pmgr_info.wake_source = PMGR_WAKE_SOURCE_NONE, + context->pmgr_notifier_ext.order = PMGR_W_NOTIFIER_ORDER_SYS_HIGH; + context->p_ctrl = p_ctrl; + + context->clbk_args.constraints = PMGR_CONSTRAINT_NONE; + context->clbk_args.event = PMGR_EVENT_NOT_SET; + context->clbk_args.p_context = (void *) context; + context->clbk_args.p_instance_info = (void *) &context->pmgr_info; + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(pmgr_ctrl != NULL); + + err = RM_PMGR_W_notifier_register(pmgr_ctrl, + r_uart_w_pmgr_callback, + &context->clbk_args, + &context->pmgr_notifier_ext); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + +static fsp_err_t r_uart_w_unsubscribe_from_pmgr_notifications (uart_w_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + pmgr_ctrl_t * pmgr_ctrl = NULL; + + pmgr_ctrl = RM_PMGR_W_get_ctrl(); + FSP_ASSERT(pmgr_ctrl != NULL); + + r_uart_w_pmgr_context_t * context = &g_uart_pmgr_context[p_ctrl->p_cfg->channel]; + err = RM_PMGR_W_notifier_unregister(pmgr_ctrl, context->pmgr_notifier_ext.notifier_id); + FSP_ASSERT(FSP_SUCCESS == err); + + return FSP_SUCCESS; +} + +static uint32_t r_uart_w_get_expected_tx_time_ms (uart_w_instance_ctrl_t * p_ctrl, uint32_t tx_bytes) +{ + uart_cfg_t const * const p_cfg = p_ctrl->p_cfg; + uint8_t bits_per_byte = p_cfg->data_bits + p_cfg->parity + p_cfg->stop_bits + 1; + uint32_t total_bits = tx_bytes * bits_per_byte; + uint64_t freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_UART); + uint32_t baudrate = 0; + uint32_t expected_time_ms = 0; + + if (p_ctrl->p_reg->UART_IBRD_REG_b.BAUD_DIVINT) + { + baudrate = (uint32_t) (freq_hz / (16 * p_ctrl->p_reg->UART_IBRD_REG_b.BAUD_DIVINT)); + } + + if (baudrate) + { + expected_time_ms = ((total_bits * 1000) / baudrate); + } + + return (expected_time_ms < R_UART_W_TX_TIME_MIN_MS) ? R_UART_W_TX_TIME_MIN_MS : expected_time_ms; +} + +static void r_uart_w_tx_done_timer_cb (TimerHandle_t xTimer) +{ + uart_w_instance_ctrl_t * p_ctrl = (uart_w_instance_ctrl_t *) pvTimerGetTimerID(xTimer); + uart_w_extended_cfg_t * p_extend = (uart_w_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + uint32_t uart_expected_time_ms; + + vPortEnterCritical(); + if (R_UART_W_IsWritting(p_ctrl) == false) + { + if (p_ctrl->tx_onging_flag) + { + p_ctrl->tx_onging_flag = false; + RM_PMGR_W_remove_sleep_constraint(RM_PMGR_W_get_ctrl(), PMGR_CONSTRAINT_SLEEP_PROHIBITED); + } + + vPortExitCritical(); + } + else + { + vPortExitCritical(); + + // Uart still busy wait for next timer cb + uart_expected_time_ms = + r_uart_w_get_expected_tx_time_ms(p_ctrl, r_uart_w_get_fifo_trigger_len(p_ctrl, p_extend->rx_fifo_trigger)); + + if (xTimerIsTimerActive(xTimer) == pdFALSE) + { + xTimerChangePeriod(xTimer, pdMS_TO_TICKS(uart_expected_time_ms), portMAX_DELAY); + + xTimerStart(xTimer, portMAX_DELAY); + } + } +} + + #endif +#endif diff --git a/bsp/renesas/ra6w1-ek/ra/fsp/src/r_wdog_w/r_wdog_w.c b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_wdog_w/r_wdog_w.c new file mode 100644 index 000000000000..45da61ac840d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/ra/fsp/src/r_wdog_w/r_wdog_w.c @@ -0,0 +1,705 @@ +/* +* Copyright (c) 2020 - 2026 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_wdog_w.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define WDOG_W_OPEN (0x00574454ULL) + +#define WDOG_W_NMI_ON_EXPIRATION (0U) +#define WDOG_W_RESET_ON_EXPIRATION (1U) + +/** + * At least 3 low power clock cycles required for the new value to be synchronized. In the worst case scenario this is equal to 93.75 us. + * Several additional PCLK cycles are required as well. In the worst case scenario, PCLK runs at 250KHz (i.e. 4us clock period). + */ +#define WDOG_W_PRV_SYNC_DELAY_US (10) // 10us per sync delay iteration +#define WDOG_W_PRV_WAIT_TIMEOUT_TICK (13) // Up to 130us delay for synchronization + +#if defined(WDTSYS_WDTSYS_REG_WDTSYS_VAL_Msk) + #define WDOG_W_REG WDTSYS->WDTSYS_REG + #define WDOG_W_VAL_FIELD WDTSYS->WDTSYS_REG_b.WDTSYS_VAL + #define WDOG_W_VAL_NEG_FIELD WDTSYS->WDTSYS_REG_b.WDTSYS_VAL_NEG +#elif defined(SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk) + #define WDOG_W_REG SYS_WDOG->WATCHDOG_REG + #define WDOG_W_VAL_FIELD SYS_WDOG->WATCHDOG_REG_b.WDOG_VAL + #define WDOG_W_VAL_NEG_FIELD SYS_WDOG->WATCHDOG_REG_b.WDOG_VAL_NEG +#endif +#if defined(WDTSYS_WDTSYS_CTRL_REG_WDTSYS_NMI_RST_Msk) + #define WDOG_W_NMI_RST_FIELD WDTSYS->WDTSYS_CTRL_REG_b.WDTSYS_NMI_RST + #define WDOG_W_WRITE_BUSY_FIELD WDTSYS->WDTSYS_CTRL_REG_b.WDTSYS_WRITE_BUSY + #define WDOG_W_FREEZE_ENABLE WDTSYS->WDTSYS_CTRL_REG_b.WDTSYS_FREEZE_EN + #define WDOG_W_WINDOWED_MODE_ENABLE WDTSYS->WDTSYS_CTRL_REG_b.WDTSYS_WINDOW_EN +#elif defined(SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk) + #define WDOG_W_NMI_RST_FIELD SYS_WDOG->WATCHDOG_CTRL_REG_b.NMI_RST + #define WDOG_W_WRITE_BUSY_FIELD SYS_WDOG->WATCHDOG_CTRL_REG_b.WRITE_BUSY + #define WDOG_W_FREEZE_ENABLE SYS_WDOG->WATCHDOG_CTRL_REG_b.WDOG_FREEZE_EN +#endif +#if defined(WDTSYS_WDTSYS_WINDOW_HIGH_REG_WDTSYS_HIGH_THR_Msk) + #define WDOG_W_WINDOWED_MODE_HIGH_THRES WDTSYS->WDTSYS_WINDOW_HIGH_REG +#endif +#if defined(WDTSYS_WDTSYS_WINDOW_LOW_REG_WDTSYS_LOW_THR_Msk) + #define WDOG_W_WINDOWED_MODE_LOW_THRES WDTSYS->WDTSYS_WINDOW_LOW_REG +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Public function prototypes + **********************************************************************************************************************/ + +#if BSP_MCU_GROUP_RA6W1 +void bsp_wdt_freeze_cfg(void); + +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_wdog_w_nmi_internal_callback(const uint32_t * p_exception_args); + +static fsp_err_t r_wdog_w_parameter_checking(wdog_w_instance_ctrl_t * const p_instance_ctrl, + wdt_cfg_t const * const p_cfg); +static void r_wdog_w_freeze(void); +static void r_wdog_w_unfreeze(void); + +#if WDOG_W_CFG_NMI_SUPPORTED +static void r_wdog_w_nmi_initialize(wdog_w_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg); + +#endif + +static fsp_err_t r_wdog_w_not_busy_wait(void); + +static fsp_err_t r_wdog_w_timeout_write(uint32_t timeout); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Global pointer to control structure for use by the NMI callback. */ +static volatile wdog_w_instance_ctrl_t * gp_wdt_ctrl = NULL; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/** Watchdog implementation of WDOG_W Driver */ +const wdt_api_t g_wdt_on_wdog_w = +{ + .open = R_WDOG_W_Open, + .refresh = R_WDOG_W_Refresh, + .statusGet = R_WDOG_W_StatusGet, + .statusClear = R_WDOG_W_StatusClear, + .counterGet = R_WDOG_W_CounterGet, + .timeoutGet = R_WDOG_W_TimeoutGet, + .callbackSet = R_WDOG_W_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup WDOG_W + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the watchdog timer. Implements @ref wdt_api_t::open. + * + * This function should only be called once. Subsequent calls will have no effect. + * + * Example: + * @snippet r_wdog_w_example.c R_WDOG_W_Open + * + * @retval FSP_SUCCESS WDT successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_Open (wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg) +{ + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + fsp_err_t err; + + /* Check validity of the parameters */ + err = r_wdog_w_parameter_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_instance_ctrl->timeout = p_cfg->timeout; + +#ifdef CRG_TOP_CLK_CTRL_REG_WDTSYS_CLK_SEL_Msk + + /* Apply clock source settings */ + CRG_TOP->CLK_CTRL_REG_b.WDTSYS_CLK_SEL = ((wdog_w_extended_cfg_t *) p_cfg->p_extend)->wdt_clk_src; +#endif + + /* Stop the watchdog, in case it is running. It is possible only for NMI. */ + WDOG_W_FREEZE_ENABLE = 1; + R_BSP_PeripheralFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); + +#if WDOG_W_CFG_NMI_SUPPORTED + if (WDT_RESET_CONTROL_NMI == p_cfg->reset_control) + { + /* Register callback with BSP NMI ISR and set NMI mode. */ + r_wdog_w_nmi_initialize(p_instance_ctrl, p_cfg); + } + +#else + + /* Eliminate toolchain warning when NMI output is not being used. */ + FSP_PARAMETER_NOT_USED(r_wdog_w_nmi_internal_callback); +#endif + + if (WDT_RESET_CONTROL_RESET == p_cfg->reset_control) + { + /* + * Defer setting the NMI_RST field until the first call to R_WDOG_W_Refresh(), + * to avoid immediate start of the countdown. The watchdog cannot be frozen once it is set + * to trigger a reset on expiration. + */ + } + +#ifdef WDTSYS_WDTSYS_CTRL_REG_WDTSYS_WINDOW_EN_Msk + if (((p_cfg->window_start < p_cfg->timeout) || (p_cfg->window_end > 0)) && + (p_cfg->window_start > p_cfg->window_end)) + { + WDOG_W_WINDOWED_MODE_LOW_THRES = p_cfg->window_end; + WDOG_W_WINDOWED_MODE_HIGH_THRES = p_cfg->window_start; + WDOG_W_WINDOWED_MODE_ENABLE = 1; + } + else + { + WDOG_W_WINDOWED_MODE_ENABLE = 0; + } +#endif + + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->wdt_open = WDOG_W_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read timeout information for the watchdog timer. Implements @ref wdt_api_t::timeoutGet. + * + * @retval FSP_SUCCESS WDT timeout information retrieved successfully. + * @retval FSP_ERR_ASSERTION Null Pointer. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_TimeoutGet (wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout) +{ + const wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_timeout); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + p_timeout->timeout_clocks = p_instance_ctrl->timeout; + p_timeout->clock_frequency_hz = BSP_FEATURE_WDT_CLOCK_FREQUENCY; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set timeout value. + * + * @retval FSP_SUCCESS WDT timeout value is set successfully. + * @retval FSP_ERR_ASSERTION Null Pointer. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_INVALID_SIZE WDT timeout value is out of range. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_TimeoutSet (wdt_ctrl_t * p_ctrl, uint32_t timeout) +{ + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((WDOG_W_TIMEOUT_MIN <= timeout) && (WDOG_W_TIMEOUT_MAX >= timeout), FSP_ERR_INVALID_SIZE); +#endif + + /* Set the timeout value */ + p_instance_ctrl->timeout = timeout; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Refresh the watchdog timer. Implements @ref wdt_api_t::refresh. + * + * In addition to refreshing the watchdog counter this function can be used to start the counter. + * + * Example: + * @snippet r_wdog_w_example.c R_WDOG_W_Refresh + * + * @retval FSP_SUCCESS WDT successfully refreshed. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_IN_USE The watchdog is busy writing and the count value cannot be refreshed. + * + * @note When windowed mode is used: a) if the refresh is attempted before the high threshold is reached, nothing happens; + * b) if the refresh is attempted after the low threshold is reached, a reset is triggered. + * @note This function reloads the watchdog timer counter value with the timeout period configured by Open. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_Refresh (wdt_ctrl_t * const p_ctrl) +{ + fsp_err_t err; + const wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + err = r_wdog_w_timeout_write(p_instance_ctrl->timeout); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_IN_USE); + + if (WDT_RESET_CONTROL_RESET == p_instance_ctrl->p_cfg->reset_control) + { + /* Reset mode, the countdown starts immediately when NMI_RST is set to 1 and NMI_RST cannot be cleared. */ + WDOG_W_NMI_RST_FIELD = WDOG_W_RESET_ON_EXPIRATION; + } + else + { + /* NMI mode, NMI_RST is 0 already, only need to unfreeze the counter. */ + R_BSP_PeripheralUnFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read the WDT status flags. Implements @ref wdt_api_t::statusGet. + * + * Indicates both status and error conditions. + * + * Example: + * @snippet r_wdog_w_example.c R_WDOG_W_StatusGet + * + * @retval FSP_SUCCESS WDT status successfully read. + * @retval FSP_ERR_ASSERTION Null pointer as a parameter. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_UNSUPPORTED This function is only valid if the watchdog generates an NMI when an error occurs. + * + * @note When the WDT is configured to output a reset on underflow or refresh error reading the status serves no purpose + * as they will always indicate that no underflow has occurred and there is no refresh error. + * Reading the status and error flags is only valid when NMI is enabled. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_StatusGet (wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status) +{ +#if WDOG_W_CFG_NMI_SUPPORTED + #if WDOG_W_CFG_PARAM_CHECKING_ENABLE + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_status); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + if (WDOG_W_VAL_NEG_FIELD) + { + *p_status = WDT_STATUS_UNDERFLOW; + } + else + { + *p_status = WDT_STATUS_NO_ERROR; + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_status); + + /* This function is only supported when the NMI is used. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Clear the WDT status and error flags. Implements @ref wdt_api_t::statusClear. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_StatusClear (wdt_ctrl_t * const p_ctrl, const wdt_status_t status) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(status); + + /* This function is not supported. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Read the current count value of the WDT. Implements @ref wdt_api_t::counterGet. + * + * Example: + * @snippet r_wdog_w_example.c R_WDOG_W_CounterGet + * + * @retval FSP_SUCCESS WDT current count successfully read. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_IN_USE The watchdog is busy writing and the count value cannot be read. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_CounterGet (wdt_ctrl_t * const p_ctrl, uint32_t * const p_count) +{ +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_count); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + fsp_err_t err = r_wdog_w_not_busy_wait(); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_IN_USE); + + *p_count = WDOG_W_VAL_FIELD; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements wdt_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_CallbackSet (wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory) +{ + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if WDOG_W_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + wdt_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(wdt_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Freeze/unfreeze the watchdog timer. + * + * Example: + * @snippet r_wdog_w_example.c R_WDOG_W_Freeze + * + * @retval FSP_SUCCESS Freeze watchdog timer successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NOT_ENABLED Freezing watchdog timer is not allowed. + * + * @note The watchdog timer can only be frozen in the following configurations. Otherwise, this function has no effect. + * - NMI Support: Enabled + * - Reset Control: NMI Generated + **********************************************************************************************************************/ +fsp_err_t R_WDOG_W_Freeze (wdt_ctrl_t * const p_ctrl, bool freeze) +{ +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + wdog_w_instance_ctrl_t * p_instance_ctrl = (wdog_w_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + if (WDOG_W_NMI_ON_EXPIRATION != WDOG_W_NMI_RST_FIELD) + { + FSP_RETURN(FSP_ERR_NOT_ENABLED); + } + + if (freeze) + { + r_wdog_w_freeze(); + r_wdog_w_not_busy_wait(); + } + else + { + r_wdog_w_unfreeze(); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup WDOG_W) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Internal NMI ISR callback which calls the user provided callback passing the context provided by the user. + * + * @param[in] p_exception_args Pointer to exception arguments. + **********************************************************************************************************************/ +static void r_wdog_w_nmi_internal_callback (const uint32_t * p_exception_args) +{ + /* Call user registered callback */ + if (NULL != gp_wdt_ctrl) + { + if (NULL != gp_wdt_ctrl->p_callback) + { + wdt_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + wdt_callback_args_t * p_args = gp_wdt_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + /* When the input of callback argument is NULL, + * the pointer to the exception arguments is passed to the callback. */ + if (NULL == gp_wdt_ctrl->p_context) + { + p_args->p_context = (void *) p_exception_args; + } + else + { + p_args->p_context = gp_wdt_ctrl->p_context; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(gp_wdt_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_wdt_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + wdt_prv_ns_callback p_callback = (wdt_prv_ns_callback) (gp_wdt_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_wdt_ctrl->p_callback(p_args); +#endif + if (NULL != gp_wdt_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_wdt_ctrl->p_callback_memory = args; + } + } + } +} + +/*******************************************************************************************************************//** + * Initialize the NMI. + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + **********************************************************************************************************************/ +#if WDOG_W_CFG_NMI_SUPPORTED +static void r_wdog_w_nmi_initialize (wdog_w_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) +{ + /* Initialize global pointer to WDT for NMI callback use. */ + gp_wdt_ctrl = p_instance_ctrl; + + R_BSP_GroupNmiWrite(r_wdog_w_nmi_internal_callback); + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + WDOG_W_NMI_RST_FIELD = WDOG_W_NMI_ON_EXPIRATION; + + /* Some devices have multiple NMI sources, we need to enable the one from WDT. */ + #ifdef ICU_ICU_NMIER_REG_ICU_WDTSYS_EN_Msk + + /* Enable watchdog timer as an NMI source. */ + ICU->ICU_NMIER_REG = ICU_ICU_NMIER_REG_ICU_WDTSYS_EN_Msk; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Parameter checking function for WDT Open + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS WDT successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + * @retval FSP_ERR_INVALID_SIZE Timeout value setting is out of range. + **********************************************************************************************************************/ +static fsp_err_t r_wdog_w_parameter_checking (wdog_w_instance_ctrl_t * const p_instance_ctrl, + wdt_cfg_t const * const p_cfg) +{ +#if WDOG_W_CFG_PARAM_CHECKING_ENABLE + + /* Check that control and config structure pointers are valid. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDOG_W_OPEN != p_instance_ctrl->wdt_open, FSP_ERR_ALREADY_OPEN); + + /* Ensure this module is in the same security state as the NMI */ + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + FSP_ERROR_RETURN(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk, FSP_ERR_INVALID_STATE); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + FSP_ERROR_RETURN(!(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk), FSP_ERR_INVALID_STATE); + #endif + + /* Check timeout parameter is within range. */ + FSP_ASSERT((p_cfg->timeout >= WDOG_W_TIMEOUT_MIN) && (p_cfg->timeout <= WDOG_W_TIMEOUT_MAX)); + + #if WDOG_W_CFG_NMI_SUPPORTED + + /* Register callback with BSP NMI ISR. */ + if (WDT_RESET_CONTROL_NMI == p_cfg->reset_control) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + else + { + FSP_ASSERT(NULL == p_cfg->p_callback); + } + + #else + FSP_ASSERT(WDT_RESET_CONTROL_RESET == p_cfg->reset_control); + FSP_ASSERT(NULL == p_cfg->p_callback); + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Busy-wait until WRITE_BUSY becomes 0, with a timeout WDOG_W_PRV_WAIT_TIMEOUT_TICK + **********************************************************************************************************************/ +static fsp_err_t r_wdog_w_not_busy_wait (void) +{ + uint8_t timeout; + + for (timeout = WDOG_W_PRV_WAIT_TIMEOUT_TICK; WDOG_W_WRITE_BUSY_FIELD && timeout; timeout--) + { + R_BSP_SoftwareDelay(WDOG_W_PRV_SYNC_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + + FSP_ERROR_RETURN((timeout > 0) || !WDOG_W_WRITE_BUSY_FIELD, FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Write the watchdog counter value. + * + * @param[in] timeout The timeout value, in watchdog ticks. + **********************************************************************************************************************/ +static fsp_err_t r_wdog_w_timeout_write (uint32_t timeout) +{ + fsp_err_t err; + + err = r_wdog_w_not_busy_wait(); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_IN_USE); + + WDOG_W_REG = timeout; + + return r_wdog_w_not_busy_wait(); +} + +/*******************************************************************************************************************//** + * Freeze the watchdog timer. + **********************************************************************************************************************/ +static void r_wdog_w_freeze (void) +{ + WDOG_W_FREEZE_ENABLE = 1; + R_BSP_PeripheralFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); +} + +/*******************************************************************************************************************//** + * Unfreeze the watchdog timer. + **********************************************************************************************************************/ +static void r_wdog_w_unfreeze (void) +{ + WDOG_W_FREEZE_ENABLE = 1; + R_BSP_PeripheralUnFreeze(BSP_FREEZE_PERIPHERAL_SYS_WDOG); + WDOG_W_FREEZE_ENABLE = 0; +} + +#if BSP_MCU_GROUP_RA6W1 +void bsp_wdt_freeze_cfg (void) +{ + /* Stub function - Do not remove !!! + * This function should be compiled instead of the Weak bsp_wdt_freeze_cfg. + * Details: + * WDT is enabled by default. + * In case wdt module does not include in the project, WDT should be disabled. + * bsp_wdt_freeze_cfg weak function - will disable WDT in case wdt module is not included. + * bsp_wdt_freeze_cfg normal function - will do nothing, hence WDT remains enabled in case wdt included. */ +} + +#endif diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/SConscript b/bsp/renesas/ra6w1-ek/rafw_cfg/SConscript new file mode 100644 index 000000000000..48bcc8beebb8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd + '/fsp_cfg', cwd + '/fsp_cfg/bsp'] + +src = Glob('*.c') +group = DefineGroup('rafw_cfg', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000000..454d4f48766d --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/rrq61xxx_evb/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000000..bef3d34a1737 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,75 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define FSP_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef FSP_NOT_DEFINED +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (FSP_NOT_DEFINED) +#endif +#undef RRQ_NOT_DEFINED +#if defined(_RRQ_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #else +#define BSP_CFG_BOOT_IMAGE ((0)) +#endif +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0) +#define BSP_CFG_NVM_SIZE_BYTES (0x180000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) +#define BSP_CFG_WAKEUP_RESET_HANDLER_ENABLE (0) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_XTAL32M_STABILIZATION_USEC +#define BSP_CLOCK_CFG_XTAL32M_STABILIZATION_USEC 0 +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 600 +#endif +#ifndef BSP_CFG_CLOCK_CALIBRATION_CYCLES +#define BSP_CFG_CLOCK_CALIBRATION_CYCLES 25 +#endif + +#ifndef BSP_CFG_IMAGE_HEADER_VERSION +#define BSP_CFG_IMAGE_HEADER_VERSION 0x00000000 +#endif +#ifndef BSP_CFG_PRODUCTION_HEADER_CRC +#define BSP_CFG_PRODUCTION_HEADER_CRC 0xFDA8 +#endif + +#ifndef BSP_CFG_CMN_TIMING_DEBUG +/* TODO add a property for this */ +#define BSP_CFG_CMN_TIMING_DEBUG (0U) +#endif + +#define __PROGRAM_START + +#ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000000..bd6a901c32d6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000000..6617fb0932c0 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,12 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7SA6W1CEDZDD +#define BSP_MCU_FEATURE_SET ('D') +#define BSP_ROM_SIZE_BYTES (134217728) +#define BSP_RAM_SIZE_BYTES (675840) +#define BSP_DATA_FLASH_SIZE_BYTES (0x40000) +#define BSP_NUMBER_OF_CORES (1) +#define BSP_PACKAGE_WLCSP +#define BSP_PACKAGE_PINS (70) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000000..f829a0b11c14 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,481 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#ifndef __ASSEMBLER__ +#include "../../../ra/fsp/src/bsp_w/mcu/ra6w1/bsp_override.h" +#include "../../../ra/fsp/src/bsp_w/mcu/ra6w1/bsp_mcu_info.h" +#endif +#include "bsp_clock_cfg.h" +#define BSP_API_OVERRIDE "../../../ra/fsp/src/bsp_w/mcu/all/bsp_api_override.h" +#define BSP_MCU_GROUP_RA6W1 (1) + +#define TIN_SKU_WIFI4_B24 (0x26) +#define TIN_SKU_WIFI6_B24 (0x22) +#define TIN_SKU_WIFI6_B24_5 (0x20) +#define TIN_SKU_WIFI6_B24_5_BLE (0x28) + +/** Chipset part number pre-definition. Used in cmake build only. In e2s build, + * this macro is auto generated by device selection in FSP configurator */ +#define BSP_MCU_R7SA6W1CEDZDd + +#if defined(BSP_MCU_R7SA6W1AEDZDD) || defined(BSP_MCU_R7SA6W1AEDZNR) || defined(BSP_MCU_RRQ61051_208) + #define TIN_SKU_BUILD_ID TIN_SKU_WIFI4_B24 + #elif defined(BSP_MCU_R7SA6W1BEDZDD) || defined(BSP_MCU_R7SA6W1BEDZNR) || defined(BSP_MCU_RRQ61051_408) + #define TIN_SKU_BUILD_ID TIN_SKU_WIFI6_B24 + #elif defined(BSP_MCU_R7SA6W1CEDZDD) || defined(BSP_MCU_R7SA6W1CEDZNR) || defined(BSP_MCU_RRQ61001_008) || \ + defined(BSP_MCU_RRQ61001_009) || defined(BSP_MCU_RRQ61001_010) + #define TIN_SKU_BUILD_ID TIN_SKU_WIFI6_B24_5 + #elif defined(BSP_MCU_R7JA6W2DEDZNR) || defined(BSP_MCU_RRQ61051_008) || defined(BSP_MCU_RRQ61051_009) || \ + defined(BSP_MCU_RRQ61051_010) + #define TIN_SKU_BUILD_ID TIN_SKU_WIFI6_B24_5_BLE + #else +#define TIN_SKU_BUILD_ID TIN_SKU_WIFI6_B24_5 +#endif + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +#define CFG_PMGR FSP_NOT_DEFINED + +#define CFG_CLI (FSP_NOT_DEFINED) + +#define CFG_MBEDTLS (FSP_NOT_DEFINED) + +#define CFG_RTC_W (FSP_NOT_DEFINED) + +#define SUPPORT_FSP_RM_OTA_W (FSP_NOT_DEFINED) + +#if (1 == FSP_NOT_DEFINED) + #define RM_MAP_PERSISTANT_W + #endif + +#if (1 == FSP_NOT_DEFINED) + #define RM_STDIO_W + #endif + +#ifndef __SUPPORT_WIFI_USER_GPIO__ +#if (1 == 1) +#define __SUPPORT_WIFI_USER_GPIO__ (1) +#endif +#endif + +#if (1 == FSP_NOT_DEFINED) + #ifndef SUPPORT_FSP_RM_OTA_W + #define SUPPORT_FSP_RM_OTA_W (1) + #endif + #ifndef __SUPPORT_OTA__ + #define __SUPPORT_OTA__ (1) + #endif + #endif + +#ifndef CFG_WIFI +#if (1 == FSP_NOT_DEFINED) + #define CFG_WIFI (1) + #else +#define CFG_WIFI (0) +#endif +#endif + +#ifndef OS_FREERTOS +#define OS_FREERTOS /* Define this to use FreeRTOS */ +#endif + +#define CONFIG_PLL + +#define dg_configXTAL_BASED_CPU40M ( 0 ) +#define dg_configUSE_PM_STATISTICS ( 1 ) + +#ifndef dg_configSYSTEMVIEW +#define dg_configSYSTEMVIEW ( 0 ) +#endif + +#if (dg_configSYSTEMVIEW == 1) + #define dg_configSYSTEMVIEW_MONITOR_QUEUE ( 0 ) + #define dg_configSYSTEMVIEW_MONITOR_MALLOC ( 0 ) + #define dg_configSYSTEMVIEW_MONITOR_EVENT_GROUP ( 0 ) + #define dg_configSYSTEMVIEW_STUCK_UNTIL_ATTACH ( 0 ) + #endif + +#ifdef dg_configEXEC_MODE + #undef dg_configEXEC_MODE + #endif +#define dg_configEXEC_MODE MODE_IS_CACHED + +#ifdef dg_configCODE_LOCATION + #undef dg_configCODE_LOCATION + #endif +#define dg_configCODE_LOCATION NON_VOLATILE_IS_FLASH + +#ifndef dg_configUSE_ROMCRYPTO +#define dg_configUSE_ROMCRYPTO (1) +#endif + +#ifndef dg_configUSE_HW_OTPC +#define dg_configUSE_HW_OTPC ( 1 ) +#endif + +#ifndef dg_configUSE_HW_TIMER +#define dg_configUSE_HW_TIMER (1) +#endif + +#define BSP_CFG_OSPI_8_LINES_SUPPORT (0) + +#define BSP_LOCO_HZ (15000) +#define BSP_MOCO_HZ (512000) + +#define BSP_HOCO_HZ (32000000) +#define BSP_SUB_CLOCK_HZ (32768) +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (76U) + +#define BSP_RCX_HZ (32000) + +#ifndef BSP_CFG_PRODUCTION_BUILD +#define BSP_CFG_PRODUCTION_BUILD (0) +#endif +#ifndef BSP_CFG_DEBUGGER_ENABLE +#define BSP_CFG_DEBUGGER_ENABLE (1) +#endif +#ifndef BSP_CFG_CMAC_DEBUGGER_ENABLE +#define BSP_CFG_CMAC_DEBUGGER_ENABLE (0) +#endif +#ifndef BSP_CFG_SNC_DEBUGGER_ENABLE +#define BSP_CFG_SNC_DEBUGGER_ENABLE (0) +#endif +#ifndef BSP_CFG_DEBUG_CMN_TIMING +#define BSP_CFG_DEBUG_CMN_TIMING (1) +#endif +#ifndef BSP_CFG_PFS_PROTECT +#define BSP_CFG_PFS_PROTECT (0) +#endif + +#define BSP_CFG_IVT_COPY_ENABLE (0) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +#define dg_configUSE_CLOCK_MGR (0U) + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + 0x07b3fcff) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* TFU */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* IIRFA */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE5 */ | \ + 0x77cfdffc) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* DAC121 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* ACMPHS3 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* ACMPHS2 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */ | \ + 0xe1a687f3) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* KINT */ | \ + 0xffffffec) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((FSP_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((FSP_NOT_DEFINED > 0) ? 0xFFEC0000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFE1F482U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (FSP_NOT_DEFINED) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_DMASARA +#define BSP_TZ_CFG_DMASARA (\ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((FSP_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((FSP_NOT_DEFINED > 0) ? 0x00E2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((FSP_NOT_DEFINED > 0) ? 0xFFFF80F7U : 0xFFFFFFFFU) +#endif + +/* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. */ +#ifndef BSP_TZ_CFG_TEVTRCR +#define BSP_TZ_CFG_TEVTRCR (1) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if FSP_NOT_DEFINED == FSP_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMASARA) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) +#define OFS_SEQ2 (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) +#define OFS_SEQ3 (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) +#define OFS_SEQ4 (FSP_NOT_DEFINED) |(FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) +#define OFS_SEQ5 (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +#define BSP_CFG_ROM_REG_OFS2 ((FSP_NOT_DEFINED) | 0xFFFFFFFEU) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFCF0F0D0U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((FSP_NOT_DEFINED > 0) ? 0U : 0x2FU)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFCF0F0D0U) +#endif +#endif +#define BSP_CFG_ROM_REG_OFS1_INITECCEN (FSP_NOT_DEFINED) +#define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (FSP_NOT_DEFINED) | (BSP_CFG_ROM_REG_OFS1_INITECCEN)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (FSP_NOT_DEFINED)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (~(FSP_NOT_DEFINED 0U)) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (FSP_NOT_DEFINED) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h new file mode 100644 index 000000000000..675955a03e16 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_OFS_CFG_H_ +#define BSP_MCU_OFS_CFG_H_ + +#endif /* BSP_MCU_OFS_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000000..c4eb21d4c600 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,18 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_gpio_w.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +extern const ioport_cfg_t g_bsp_pin_cfg; /* RRQ61xxx-EVB */ +#if !defined(BSP_MCU_GROUP_RA6W1) //TIN-TODO +extern gpio_w_extended_cfg_t g_bsp_pin_cfg_extd; /* RRQ61xxx-EVB_extd */ +#endif + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_adc_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_adc_w_cfg.h new file mode 100644 index 000000000000..0498f07ac90c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_adc_w_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_W_CFG_H_ +#define R_ADC_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define ADC_W_CFG_INTERRUPT_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ext_irq_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ext_irq_w_cfg.h new file mode 100644 index 000000000000..1a4b652aa0af --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ext_irq_w_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_EXT_IRQ_W_CFG_H_ +#define R_EXT_IRQ_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define EXT_IRQ_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_EXT_IRQ_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_gpio_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_gpio_w_cfg.h new file mode 100644 index 000000000000..e3d09d8292f6 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_gpio_w_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_GPIO_W_CFG_H_ +#define R_GPIO_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_GPIO_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_i2c_master_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_i2c_master_w_cfg.h new file mode 100644 index 000000000000..332f87e01bba --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_i2c_master_w_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef R_I2C_MASTER_W_CFG_H_ +#define R_I2C_MASTER_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_MASTER_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define I2C_MASTER_W_CFG_GENERIC_ONLY (1) +#define I2C_MASTER_W_CFG_DTC_ENABLE (0) +#define I2C_MASTER_W_CFG_DMA_ENABLE (0) +#define I2C_MASTER_W_CFG_TRANSFER_API_TX_BUFFER_SIZE (256) + +#ifdef __cplusplus +} +#endif +#endif /* R_I2C_MASTER_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ospi_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ospi_w_cfg.h new file mode 100644 index 000000000000..832d4d137ab7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_ospi_w_cfg.h @@ -0,0 +1,20 @@ +/* generated configuration header file - do not edit */ +#ifndef R_OSPI_W_CFG_H_ +#define R_OSPI_W_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define RRQ61X_OSPI_W_ENABLED +#define OSPI_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define OSPI_W_CFG_DMAC_SUPPORT_ENABLE (0) +#define OSPI_W_CFG_XIP_SUPPORT_ENABLE (1) +#define OSPI_W_CFG_AUTOCALIBRATION_SUPPORT_ENABLE (0) +#define OSPI_W_CFG_PREFETCH_FUNCTION (1) + +#define OSPI_W_CFG_DOTF_SUPPORT_ENABLE (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_OSPI_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_qspi_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_qspi_w_cfg.h new file mode 100644 index 000000000000..ce3dcd5d3887 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_qspi_w_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_W_CFG_H_ +#define R_QSPI_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_rtc_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_rtc_w_cfg.h new file mode 100644 index 000000000000..115e7ce53c09 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_rtc_w_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_W_CFG_H_ +#define R_RTC_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_spi_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_spi_w_cfg.h new file mode 100644 index 000000000000..871e5725c043 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_spi_w_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_W_CFG_H_ +#define R_SPI_W_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SPI_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_W_CFG_TRANSFER_API_SUPPORT (0) +#define SPI_W_CFG_TRANSMIT_FROM_RXI_ISR (0) +#define SPI_W_CFG_FAST_MODE_ENABLE (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_SPI_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_tim_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_tim_w_cfg.h new file mode 100644 index 000000000000..a4e620355f5c --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_tim_w_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_TIM_W_CFG_H_ +#define R_TIM_W_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define TIM_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define TIM_W_CFG_OUTPUT_SUPPORT_ENABLE (1) +#ifdef __cplusplus +} +#endif +#endif /* R_TIM_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_uart_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_uart_w_cfg.h new file mode 100644 index 000000000000..563610cb9e57 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_uart_w_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_UART_W_CFG_H_ +#define R_UART_W_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define UART_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define UART_W_DMA_SUPPORT_ENABLE (0) +#define UART_W_CTRL_FLOW_CONTROL_SUPPORT FSP_NOT_DEFINED + +#ifdef __cplusplus + } + #endif +#endif /* R_UART_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_wdog_w_cfg.h b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_wdog_w_cfg.h new file mode 100644 index 000000000000..9d6f7dd8376e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/r_wdog_w_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_WDOG_W_CFG_H_ +#define R_WDOG_W_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define WDOG_W_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define WDOG_W_CFG_NMI_SUPPORTED ((1)) + +#ifdef __cplusplus + } + #endif +#endif /* R_WDOG_W_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/SConscript b/bsp/renesas/ra6w1-ek/rafw_gen/SConscript new file mode 100644 index 000000000000..180db757ac47 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/SConscript @@ -0,0 +1,18 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + print("\nThe current project does not support IAR build\n") + Return('group') +elif rtconfig.PLATFORM in ['gcc', 'armclang']: + src = Glob('*.c') + CPPPATH = [cwd] + +group = DefineGroup('ra_gen', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h b/bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h new file mode 100644 index 000000000000..7d3fcb7840ce --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h @@ -0,0 +1,30 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTALM_HZ (40000000) /* XTAL 40MHz */ +#define BSP_CFG_XTALK_HZ (32768) /* XTAL 32768Hz */ +#define BSP_RCX_HZ (32000) /* RCX 32kHz */ +#define BSP_CFG_PLL480M_HZ (480000000) /* PLL 480MHz */ +#define BSP_CFG_XTAL40M_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTALM) /* XTAL40M_CLK Enabled */ +#define BSP_CFG_XTAL_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTALK) /* XTAL_CLK Enabled */ +#define BSP_CFG_RCX_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_RCX) /* RCX_CLK Enabled */ +#define BSP_CFG_PLL_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTALM) /* PLL Src: XTAL40M */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_CLOCK_MUL_12_1) /* PLL Mul 12/1 */ +#define BSP_CFG_LP_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTALK) /* LP_CLK Src: XTAL */ +#define BSP_CFG_PLL_SYS_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* PLL_SYS Src: PLL */ +#define BSP_CFG_PLL_SYS_MUL (BSP_CLOCKS_PLL_SYS_CLOCK_MUL_1_3) /* PLL_SYS Mul 1/3 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* SYS_CLK Src: PLL_SYS */ +#define BSP_CFG_HCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* HCLK Div /1 */ +#define BSP_CFG_QSPICLK_DIV (BSP_CLOCKS_QSPI_CLK_DIV_2) /* QSPICLK Div /2 */ +#define BSP_CFG_PLL_SPI_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL_SPI Disabled */ +#define BSP_CFG_PLL_SPI_MUL (BSP_CLOCKS_PLL_SPI_CLOCK_MUL_1_6) /* PLL_SPI Mul 1/6 */ +#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTAL_SYS) /* SPI_CLK Src: XTAL_SYS */ +#define BSP_CFG_PLL_PERI_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* PLL_PERI Src: PLL */ +#define BSP_CFG_PLL_PERI_DIV (BSP_CLOCKS_PLL_PERI_CLOCK_DIV_1_6) /* PLL_PERI Div /6 */ +#define BSP_CFG_PERI_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_XTAL_SYS) /* PERI_CLK Src: XTAL_SYS */ +#define BSP_CFG_I2C1CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C1 Div /1 */ +#define BSP_CFG_I2C2CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C2 Div /1 */ +#define BSP_CFG_WDOG_DIV (BSP_CLOCKS_WDOG_DIV_320) /* WDOG Div /320 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/common_data.c b/bsp/renesas/ra6w1-ek/rafw_gen/common_data.c new file mode 100644 index 000000000000..86ff4994ec7a --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +gpio_w_instance_ctrl_t g_gpio_w_ctrl; +const ioport_instance_t g_gpio_w = { .p_api = &g_ioport_on_gpio_w, .p_ctrl = + &g_gpio_w_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/common_data.h b/bsp/renesas/ra6w1-ek/rafw_gen/common_data.h new file mode 100644 index 000000000000..88563494ee40 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_gpio_w.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_GPIO_W_Open +#define IOPORT_CFG_CTRL g_gpio_w_ctrl + +/* GPIO_W Instance */ +extern const ioport_instance_t g_gpio_w; + +/* GPIO_W control structure. */ +extern gpio_w_instance_ctrl_t g_gpio_w_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c b/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c new file mode 100644 index 000000000000..f2e6b10bd5c9 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c @@ -0,0 +1,47 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +uart_w_instance_ctrl_t g_uart1_ctrl; +/** UART_W extended configuration for UART HAL driver */ +uart_w_baud_setting_t g_uart1_baud_setting = { .fra_baud = 26, .int_baud = 43 }; + +/** UART extended configuration for UART_W HAL driver */ +const uart_w_extended_cfg_t g_uart1_cfg_extend = + { .fifo_enable = UART_W_FIFO_ENABLE, .rx_fifo_trigger = + UART_W_RX_FIFO_TRIGGER_SEVEN_EIGHTHS, .tx_fifo_trigger = + UART_W_TX_FIFO_TRIGGER_EIGHTH, .p_baud_setting = + &g_uart1_baud_setting, .flow_control = + UART_W_AUTO_FLOW_CONTROL_DISABLED, .loop_back_enable = + UART_W_LOOP_BACK_DISABLE, .rs485_enable = UART_W_RS485_DISABLE, }; + +/** UART interface configuration */ +const uart_cfg_t g_uart1_cfg = { .channel = 1 - UART_W_CHANNEL_OFFSET, + .data_bits = UART_W_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = + UART_STOP_BITS_1, .p_callback = user_uart0_callback, .p_context = + NULL, .p_extend = &g_uart1_cfg_extend, +#define FSP_NOT_DEFINED (1) +#if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &FSP_NOT_DEFINED, +#endif +#if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &FSP_NOT_DEFINED, +#endif +#undef FSP_NOT_DEFINED + .rxi_ipl = (12), +#if defined(VECTOR_NUMBER_UARTW1_IRQ) + .rxi_irq = VECTOR_NUMBER_UARTW1_IRQ, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif + + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart1 = { .p_ctrl = &g_uart1_ctrl, + .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_uart_w }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.h b/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.h new file mode 100644 index 000000000000..32c889808291 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/hal_data.h @@ -0,0 +1,24 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_uart_w.h" +#include "r_uart_api.h" +FSP_HEADER +/** UART_W Instance. */ +extern const uart_instance_t g_uart1; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern uart_w_instance_ctrl_t g_uart1_ctrl; +extern const uart_cfg_t g_uart1_cfg; +extern const uart_w_extended_cfg_t g_uart1_cfg_extend; + +#ifndef user_uart0_callback +void user_uart0_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/main.c b/bsp/renesas/ra6w1-ek/rafw_gen/main.c new file mode 100644 index 000000000000..a36b37275936 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c b/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c new file mode 100644 index 000000000000..8b8eec63a0f7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c @@ -0,0 +1,100 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_gpio_w.h" + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { { .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = (GPIO_W_CFG_DRV_8mA | GPIO_W_CFG_PERIPHERAL_PIN + | GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_SLW_FAST + | GPIO_W_PERIPHERAL_UART_RX) }, { .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = (GPIO_W_CFG_DRV_8mA | GPIO_W_CFG_PERIPHERAL_PIN + | GPIO_W_CFG_PORT_DIRECTION_OUTPUT | GPIO_W_CFG_SLW_SLOW + | GPIO_W_PERIPHERAL_UART_TX) }, { .pin = BSP_IO_PORT_00_PIN_02, + .pin_cfg = (GPIO_W_CFG_ANALOG_ENABLE | GPIO_W_CFG_DRV_8mA + | GPIO_W_CFG_SLW_SLOW) }, { .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = (GPIO_W_CFG_ANALOG_ENABLE | GPIO_W_CFG_DRV_8mA + | GPIO_W_CFG_SLW_SLOW) }, { .pin = BSP_IO_PORT_00_PIN_10, + .pin_cfg = (GPIO_W_CFG_DRV_8mA | GPIO_W_CFG_PORT_DIRECTION_OUTPUT + | GPIO_W_CFG_PORT_OUTPUT_LOW | GPIO_W_CFG_SLW_SLOW) }, { .pin = + BSP_IO_PORT_01_PIN_00, .pin_cfg = (GPIO_W_CFG_DRV_8mA + | GPIO_W_CFG_PORT_DIRECTION_OUTPUT | GPIO_W_CFG_PORT_OUTPUT_LOW + | GPIO_W_CFG_SLW_SLOW) }, { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = + (GPIO_W_CFG_DRV_8mA | GPIO_W_CFG_PORT_DIRECTION_OUTPUT + | GPIO_W_CFG_PORT_OUTPUT_LOW | GPIO_W_CFG_SLW_SLOW) }, { .pin = + BSP_IO_PORT_01_PIN_02, .pin_cfg = (GPIO_W_CFG_DRV_8mA + | GPIO_W_CFG_PORT_DIRECTION_OUTPUT | GPIO_W_CFG_PORT_OUTPUT_LOW + | GPIO_W_CFG_SLW_SLOW) }, { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = + (GPIO_W_CFG_DRV_8mA | GPIO_W_CFG_PORT_DIRECTION_OUTPUT + | GPIO_W_CFG_PORT_OUTPUT_LOW | GPIO_W_CFG_SLW_SLOW) }, { .pin = + BSP_IO_PORT_01_PIN_16, .pin_cfg = (GPIO_W_CFG_PERIPHERAL_PIN + | GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_PERIPHERAL_SWCLK) }, { .pin = + BSP_IO_PORT_01_PIN_17, .pin_cfg = (GPIO_W_CFG_PERIPHERAL_PIN + | GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_PERIPHERAL_SWDIO) }, }; + +#if !defined(BSP_MCU_GROUP_RA6W1) //TIN-TODO +gpio_w_extended_cfg_t g_bsp_pin_cfg_extd = { .power.p1_pwr = + GPIO_W_CFG_SUPPLY_V30, +#if BSP_FEATURE_IO_HAS_WEAK_CONFIG_PER_PORT + .weak_pad_power = + { + .p0_pwr = GPIO_W_CFG_DRV_NORMAL, + .p1_pwr = GPIO_W_CFG_DRV_NORMAL, + #if BSP_FEATURE_IO_PORT2_GPIO_COUNT > 0 + .p2_pwr = GPIO_W_CFG_DRV_NORMAL, + #endif + }, +#else + .weak_pad_power.aggregate = GPIO_W_CFG_DRV_NORMAL, +#endif + .fixed_pin_clk_out = BSP_IO_CLK_NONE_OUT, +#if BSP_CFG_CLKOUT_SOURCE + .sel_pin_clk_out.clk_en = 1, + .sel_pin_clk_out.clk_sel = BSP_CFG_CLKOUT_SOURCE - 1, +#else + .sel_pin_clk_out.clk_en = 0, .sel_pin_clk_out.clk_sel = + (bsp_io_clk_func_t) 0, +#endif + }; +#endif + +const ioport_cfg_t g_bsp_pin_cfg = { .number_of_pins = + sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = + &g_bsp_pin_cfg_data[0], +#if !defined(BSP_MCU_GROUP_RA6W1) //TIN-TODO + .p_extend = &g_bsp_pin_cfg_extd, +#endif + }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.c b/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.c new file mode 100644 index 000000000000..2652fdaef8aa --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.c @@ -0,0 +1,22 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if BSP_FEATURE_BSP_HAS_ICU + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = uart_w_isr, /* UARTW1 IRQ (Generic interrupt) */ + }; + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = + { + [0] = BSP_PRV_IELS_ENUM(EVENT_UARTW1_IRQ), /* UARTW1 IRQ (Generic interrupt) */ + }; + #endif + #else +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_IRQ_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ +#if VECTOR_DATA_IRQ_COUNT > 0 + [2] = uart_w_isr, /* UARTW1 IRQ (Generic interrupt) */ + #endif +}; +#endif diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.h b/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.h new file mode 100644 index 000000000000..c6ccaacd440e --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rafw_gen/vector_data.h @@ -0,0 +1,25 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +#ifdef __cplusplus + extern "C" { + #endif +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (1) +#endif +/* ISR prototypes */ +void uart_w_isr(void); +#if defined(BSP_MCU_GROUP_RA6B1) || defined(BSP_MCU_GROUP_RA6U1) //BROMINE-TODO + /* Vector table allocations */ + #define VECTOR_NUMBER_UARTW1_IRQ ((IRQn_Type) 0) /* UARTW1 IRQ (Generic interrupt) */ + #define UARTW1_IRQ_IRQn ((IRQn_Type) 0) /* UARTW1 IRQ (Generic interrupt) */ +#else +/* Vector table allocations */ +#define VECTOR_NUMBER_UARTW1_IRQ ((IRQn_Type) 2) /* UARTW1 IRQ (Generic interrupt) */ +#define UARTW1_IRQ_IRQn ((IRQn_Type) 2) /* UARTW1 IRQ (Generic interrupt) */ +#endif +#ifdef __cplusplus + } + #endif +#endif /* VECTOR_DATA_H */ diff --git a/bsp/renesas/ra6w1-ek/rtconfig.h b/bsp/renesas/ra6w1-ek/rtconfig.h new file mode 100644 index 000000000000..f13cfde9ecb7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rtconfig.h @@ -0,0 +1,430 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_R7SA6W1CED + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_RENESAS_RA_WIRELESS +#define SOC_SERIES_R7SA6W1 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO_W +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 256 +#define BSP_UART0_TX_BUFSIZE 0 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/renesas/ra6w1-ek/rtconfig.py b/bsp/renesas/ra6w1-ek/rtconfig.py new file mode 100644 index 000000000000..f806d3bf7f08 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/rtconfig.py @@ -0,0 +1,63 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +# BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + NM = PREFIX + 'nm' + + DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp.ld -L script/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g -Wall' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + POST_ACTION += 'python3 scripts/gen_rrq61_flash_image.py rtthread.bin rtthread.img.bin RA6W1-RRQ61001\n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/renesas/ra6w1-ek/script/fsp.ld b/bsp/renesas/ra6w1-ek/script/fsp.ld new file mode 100644 index 000000000000..55e7ceb358f8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/script/fsp.ld @@ -0,0 +1,385 @@ +INCLUDE memory_regions.ld +MEMORY +{ + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + RAMCODE (rx) : ORIGIN = RAMCODE_START, LENGTH = RAMCODE_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + IPDRAM (rwx) : ORIGIN = IPDRAM_START, LENGTH = IPDRAM_LENGTH + FRAGRAM (rwx) : ORIGIN = FRAGRAM_START, LENGTH = FRAGRAM_LENGTH + MACHW_MIB (rwx) : ORIGIN = MACHW_MIB_START, LENGTH = MACHW_MIB_LENGTH +} + +/* code entry point...need to define to keep crt0 _start out */ +ENTRY( Reset_Handler) +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +SECTIONS +{ + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = .; + __ROM_Start = .; + + }> FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = .; _VECTORS = .; + PROVIDE(__Vectors = .); + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __flash_vectors$$Limit = .; + }> FLASH + __Vectors_Size = __Vectors_End - __flash_vectors$$Base; + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = .; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = .; + }> FLASH + /***** IPDRAM memory section allocations ******/ + .ipdram.startof : + { + __ddsc_IPDRAM_START = .; + + }> IPDRAM + /* ipdram initialized from flash */ + __ipdram_from_flash$$ : ALIGN(4) + { + __ipdram_from_flash$$Base = .;__ipdram_from_flash$$Load = LOADADDR(__ipdram_from_flash$$); + /* section.ipdram.from_flash */ + *(.ipdram_from_flash) + /* section.ipdram.code_from_flash */ + *(.ipdram_code_from_flash) + . = ALIGN(4); + __ipdram_from_flash$$Limit = .; + }> IPDRAM AT > FLASH + /* Non-initialized ipdram */ + __ipdram_noinit$$ (NOLOAD) : + { + __ipdram_noinit$$Base = .; + /* section.ipdram.noinit */ + *(.ipdram_noinit) + __ipdram_noinit$$Limit = .; + }> IPDRAM + /* Zeroed ipdram */ + __ipdram_zero$$ (NOLOAD) : ALIGN(4) + { + __ipdram_zero$$Base = .; + /* section.ipdram.zero */ + *(.ipdram) + . = ALIGN(4); + __ipdram_zero$$Limit = .; + }> IPDRAM + .ipdram.endof ALIGN(.,512) : + { + __ddsc_IPDRAM_END = .; + + }> IPDRAM + + /***** FRAGRAM memory section allocations ******/ + .fragram.startof : + { + __ddsc_FRAGRAM_START = .; + + }> FRAGRAM + /* fragram initialized from flash */ + __fragram_from_flash$$ : ALIGN(4) + { + __fragram_from_flash$$Base = .;__fragram_from_flash$$Load = LOADADDR(__fragram_from_flash$$); + /* section.fragram.from_flash */ + *(.fragram_from_flash) + /* section.fragram.code_from_flash */ + *(.fragram_code_from_flash) + . = ALIGN(4); + __fragram_from_flash$$Limit = .; + }> FRAGRAM AT > FLASH + /* Non-initialized fragram */ + __fragram_noinit$$ (NOLOAD) : + { + __fragram_noinit$$Base = .; + /* section.fragram.noinit */ + *(.fragram_noinit) + __fragram_noinit$$Limit = .; + }> FRAGRAM + /* Zeroed fragram */ + __fragram_zero$$ (NOLOAD) : ALIGN(4) + { + __fragram_zero$$Base = .; + /* section.fragram.zero */ + *(.fragram) + . = ALIGN(4); + __fragram_zero$$Limit = .; + }> FRAGRAM + .fragram.endof ALIGN(.,512) : + { + __ddsc_FRAGRAM_END = .; + + }> FRAGRAM + + /***** MACHW_MIB memory section allocations ******/ + .machw_mib.startof : + { + __ddsc_MACHW_MIB_START = .; + + }> MACHW_MIB + /* machw_mib initialized from flash */ + __machw_mib_from_flash$$ : ALIGN(4) + { + __machw_mib_from_flash$$Base = .;__machw_mib_from_flash$$Load = LOADADDR(__machw_mib_from_flash$$); + /* section.machw_mib.from_flash */ + *(.machw_mib_from_flash) + /* section.machw_mib.code_from_flash */ + *(.machw_mib_code_from_flash) + . = ALIGN(4); + __machw_mib_from_flash$$Limit = .; + }> MACHW_MIB AT > FLASH + /* Non-initialized machw_mib */ + __machw_mib_noinit$$ (NOLOAD) : + { + __machw_mib_noinit$$Base = .; + /* section.machw_mib.noinit */ + *(.machw_mib_noinit) + __machw_mib_noinit$$Limit = .; + }> MACHW_MIB + /* Zeroed machw_mib */ + __machw_mib_zero$$ (NOLOAD) : ALIGN(4) + { + __machw_mib_zero$$Base = .; + /* section.machw_mib.zero */ + *(.machw_mib) + . = ALIGN(4); + __machw_mib_zero$$Limit = .; + }> MACHW_MIB + .machw_mib.endof ALIGN(.,512) : + { + __ddsc_MACHW_MIB_END = .; + + }> MACHW_MIB + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = .; + + }> RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = .; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = .; + }> RAM + /* ram initialized from flash */ + __ram_from_flash$$ : ALIGN(4) + { + __ram_from_flash$$Base = .;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$); + __data_start__ = .; + /* section.ram.from_flash */ + *(.ram_from_flash) + *(.data*) + *(vtable) + . = ALIGN(4); + __data_end__ = .; + __ram_from_flash$$Limit = .; + }> RAM AT > FLASH + __etext = LOADADDR(__ram_from_flash$$); + /* Main Stack */ + __ram_main_stack$$ (NOLOAD) : + { + __ram_main_stack$$Base = .; + /* section.ram.main_stack */ + *(.bss.g_main_stack) + __ram_main_stack$$Limit = .; + }> RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = .; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = .; + }> RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : ALIGN(4) + { + __ram_zero$$Base = .; + __bss_start__ = .; + /* section.ram.zero */ + *(.ram) + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + __ram_zero$$Limit = .; + }> RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = .; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = .; + }> RAM + .ram.endof ALIGN(.,512) : + { + __ddsc_RAM_END = .; + + }> RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = .; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* RT-Thread metadata must live in normal flash, not in the MCU vector table. */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + KEEP(*(FalPartTable)) + __flash_readonly$$Limit = .; + }> FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + }> FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + }> FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + }> FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = .; + }> FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = .; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = .; + }> FLASH + /* .ARM.extab sections contain exception unwinding information. */ + __flash_arm.extab$$ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + }> FLASH + /* .ARM.exidx sections contains index entries for section unwinding. */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + __exidx_end = .; + }> FLASH + .flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_FLASH_END = .; + __ROM_End = .; + + }> FLASH + + /***** RAMCODE memory section allocations ******/ + .ramcode.startof (READONLY) : + { + + . += __ddsc_RAM_END - __ddsc_RAM_START; __ddsc_RAMCODE_START = .; + + }> RAMCODE + /* ramcode initialized from flash */ + __ramcode_from_flash$$ (READONLY) : + { + __ramcode_from_flash$$Base = .;__ramcode_from_flash$$Load = LOADADDR(__ramcode_from_flash$$); + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *libnosys.a:sbrk.o(.text*) + *libgcc.a:_aeabi_uldivmod.o(.text*) + *libgcc.a:_muldi3.o(.text*) + *libmacsw.a:txl_he.o(.text*) + *libmacsw.a:txl_cntrl.o(.text*) + *libmacsw.a:txl_hwdesc.o(.text*) + *libgcc.a:_dvmd_tls.o(.text*) + *libgcc.a:bpabi.o(.text*) + *libgcc.a:_udivdi3.o(.text*) + *libgcc.a:_clzdi2.o(.text*) + *libgcc.a:_clzsi2.o(.text*) + __ramcode_from_flash$$Limit = .; + }> RAMCODE AT > FLASH + .ramcode.endof ALIGN(.,512) (READONLY) : + { + __ddsc_RAMCODE_END = .; + + }> RAMCODE + +} + +PROVIDE( __StackLimit = __ram_main_stack$$Base); +PROVIDE( __StackTop = __ram_main_stack$$Limit); +PROVIDE( __StackTopAll = __ram_thread_stack$$Limit); +PROVIDE( __stack = __StackTop); +PROVIDE( __HeapBase = ALIGN(ORIGIN(RAM) + (__ddsc_RAMCODE_END - ORIGIN(RAMCODE)), 8)); +PROVIDE( __HeapLimit = ORIGIN(RAM) + LENGTH(RAM)); +PROVIDE( __RAM_segment_used_end__ = __HeapBase); +PROVIDE( __bss_start__ = __ram_zero$$Base); +PROVIDE( __bss_end__ = __ram_zero$$Limit); +PROVIDE( end = __HeapBase); +PROVIDE( _end = __HeapBase); +PROVIDE( __end__ = __HeapBase); + +ASSERT(__HeapBase <= __HeapLimit, "RAM overflow: no space left for RT-Thread heap"); + diff --git a/bsp/renesas/ra6w1-ek/script/memory_regions.ld b/bsp/renesas/ra6w1-ek/script/memory_regions.ld new file mode 100644 index 000000000000..4292c2e7c4e7 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/script/memory_regions.ld @@ -0,0 +1,13 @@ +/* generated memory regions file - do not edit */ +RAM_START = 0x20000000; +RAM_LENGTH = 0x000a5000; +RAMCODE_START = 0x08000000; +RAMCODE_LENGTH = 0x000a5000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x08000000; +IPDRAM_START = 0x200a5000; +IPDRAM_LENGTH = 0x00003b00; +FRAGRAM_START = 0x200aa500; +FRAGRAM_LENGTH = 0x00005700; +MACHW_MIB_START = 0x60b00800; +MACHW_MIB_LENGTH = 0x00001000; diff --git a/bsp/renesas/ra6w1-ek/scripts/gen_rrq61_flash_image.py b/bsp/renesas/ra6w1-ek/scripts/gen_rrq61_flash_image.py new file mode 100644 index 000000000000..695dcf5e72f8 --- /dev/null +++ b/bsp/renesas/ra6w1-ek/scripts/gen_rrq61_flash_image.py @@ -0,0 +1,334 @@ +#!/usr/bin/env python3 + +"""Generate flash image for EK-RRQ61000 board.""" +# See reference implementation in the following legacy SDK files: +# binaries/mkimage/mkimage_new_header.py +# binaries/mkimage/non_secure_cfg.xml.AT25SL641-8MB + +import argparse +import binascii +from collections import namedtuple +from rrq61_fw_version import get_fw_version +import os +from os import path +import re + + +# The following code is taken from mkimage_new_header.py (slightly modified): +def _initial(byte): + polynomial = 0x1021 + crc = 0 + byte <<= 8 + for _i in range(8): + if (crc ^ byte) & 0x8000: + crc = (crc << 1) ^ polynomial + else: + crc <<= 1 + byte <<= 1 + return crc + + +_tab = [_initial(byte) for byte in range(256)] + + +def _update_crc(crc, byte): + tmp = (crc >> 8) ^ byte + crc = (crc << 8) ^ _tab[tmp & 0xFF] + return crc & 0xFFFF + + +def crcb(data): + """Calculate 16-bit long CRC.""" + crc = 0xFFFF # preset + for byte in data: + crc = _update_crc(crc, byte) + return crc + + +def to_bytes(value, num_bytes, byteorder='little', signed=False): + """Convert integer value to specified number of bytes.""" + return value.to_bytes(num_bytes, byteorder, signed=signed) + +ProductHeaderValues = namedtuple('ProductHeaderValues', [ + 'is_corrupt', 'sram_boot', 'crc_corrupt', 'active_fw_addr', + 'update_fw_addr', 'burstcmda_reg', 'burstcmdb_reg', 'ctrlmode_reg', + 'flash_config']) + + +def get_product_header(header): + """Produce product header binary blob.""" + # See calcCRC() in mkimage_new_header.py + data = bytearray() + if header.crc_corrupt: + data.extend(b'\xDE\xAD\xC0\xDE') + else: + data.extend(b'\x53\x73' if header.is_corrupt else b'\x50\x70') + data.extend(to_bytes(header.active_fw_addr, 4)) + data.extend(to_bytes(header.update_fw_addr, 4)) + data.extend(to_bytes(header.burstcmda_reg, 4)) + data.extend(to_bytes(header.burstcmdb_reg, 4)) + data.extend(to_bytes(header.ctrlmode_reg, 4)) + flash_config_id = to_bytes(0x22AA if header.sram_boot else 0x11AA, 2) + data.extend(flash_config_id) + flash_config_len = to_bytes(len(header.flash_config), 2) + data.extend(flash_config_len) + data.extend(header.flash_config) + crc = to_bytes(crcb(data), 2) + data.extend(crc) + product_header_size = 0x1000 # 4096 bytes + num_bytes_uninitialized = product_header_size - len(data) + data.extend(b'\xFF' * num_bytes_uninitialized) + return data + + +ImageHeaderValues = namedtuple('ImageHeaderValues', [ + 'is_corrupt', 'security', 'version', 'timestamp', 'image_size', + 'image_crc']) + + +def get_image_header(header): + """Produce image header binary blob.""" + # See __init__() from ImageHeader class in mkimage_new_header.py + data = bytearray() + if header.is_corrupt: + raise ValueError('image_header_corrupt is not supported') + data.extend(b'DA16') + data.extend(to_bytes(header.timestamp, 4)) + data.extend(header.version) + num_zeros = 64 - len(header.version) + data.extend(b'\x00' * num_zeros) + if header.security: + raise ValueError('security for image header is not supported') + pointer_to_ivt = 1024 + data.extend(to_bytes(pointer_to_ivt, 4)) + data.extend(to_bytes(header.image_size, 4)) + data.extend(to_bytes(header.image_crc, 4)) + secure_boot_option = 0 + data.extend(to_bytes(secure_boot_option, 4)) + secure_cert_size = 0 + data.extend(to_bytes(secure_cert_size, 4)) + secure_cert_crc = 0 + data.extend(to_bytes(secure_cert_crc, 4)) + crc = binascii.crc32(data) + data.extend(to_bytes(crc, 4)) + image_header_size = 0x400 + num_bytes_uninitialized = image_header_size - len(data) + data.extend(b'\xFF' * num_bytes_uninitialized) + return data + +def get_firmware_version_e2s(fw_version_file): + """ + Reads the firmware version from fw_version.h. + If not found, defaults to '1.0.0'. + """ + try: + with open(fw_version_file, "r") as file: + content = file.read() + match = re.search(r'#define FIRMWARE_VERSION\s+"([^"]+)"', content) + if match: + return match.group(1) + except FileNotFoundError: + print("fw_version.h file not found, using default version.") + + return "1.0.0" # Default version + +def gen_flash_image(in_file, out_file, ra6w_grp): + """Generate output flash image.""" + in_file_data = in_file.read() + in_file.close() + out_file_name = out_file.name + + # From non_secure_cfg.xml.AT25SL641-8MB (product headers 1 and 2): + ph_values = ProductHeaderValues( + is_corrupt=False, + sram_boot=False, + crc_corrupt=False, + active_fw_addr=0x00002000, + update_fw_addr=0x00002000, + burstcmda_reg=0xa8a500eb, + burstcmdb_reg=0x00030616, + ctrlmode_reg=0xF8000532, + flash_config=b'\x02\x31\x02', + ) + + headers_data = get_product_header(ph_values) # first product header + # Second product header is the same as first one according to file + # non_secure_cfg.xml.AT25SL641-8MB, hence: + headers_data.extend(headers_data) + + # Set f/w version info + fw_version = get_fw_version() + if not fw_version: + # This condition will be true when we are building project + # using e2studio and project is prepared outside the repo + # In this case fetch the value from fw_version.h which is generated + # when packs are created. + script_dir = os.path.dirname(os.path.abspath(__file__)) # Get script directory + fw_version_file = os.path.abspath(os.path.join(script_dir, "../ra/fsp/src/rm_wifi/fw_version.h")) + if not os.path.isfile(fw_version_file): + # Try another location + fw_version_file = os.path.abspath(os.path.join(script_dir, "../ra/fsp/inc/fw_version.h")) + fw_version = get_firmware_version_e2s(fw_version_file) + + else: + # Check if out_file_name contains 'rm_wifi_test_app.img' + if 'rm_wifi_test_app' in out_file_name or 'vndm_wlan' in out_file_name: + fw_version = fw_version+"-e2studio" + else: + # If not, append "-cmake" + fw_version = fw_version+"-cmake" + header_fw_version = ra6w_grp + '-' + fw_version + # From non_secure_cfg.xml.AT25SL641-8MB (image header): + ih_values = ImageHeaderValues( + is_corrupt=False, + security=False, + version=header_fw_version.encode(), + timestamp=0x5939110D, + image_size=len(in_file_data), + image_crc=binascii.crc32(in_file_data), + ) + img_header=get_image_header(ih_values) + headers_data.extend(img_header) + out_file.write(headers_data) + out_file.write(in_file_data) + out_file.close() + + #gen OTA images for test + if((os.getcwd().find('rm_wifi') != -1) and out_file_name.find('rm_wifi_typical.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_typical_', ra6w_grp) + + elif((os.getcwd().find('rm_wifi') != -1) and out_file_name.find('rm_wifi_ba.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_ba_', ra6w_grp) + + elif((os.getcwd().find('rm_matter') != -1) and out_file_name.find('rm_matter_wifi_atcmd_test_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_matter_wifi_atcmd_test_app_', ra6w_grp) + + elif((os.getcwd().find('rm_matter') != -1) and out_file_name.find('rm_matter_wifi_lock_test_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_matter_wifi_lock_test_app_', ra6w_grp) + + elif((os.getcwd().find('vndm_rm_matter') != -1) and out_file_name.find('vndm_rm_matter_wifi_lock_test_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_rm_matter_wifi_lock_test_app_', ra6w_grp) + + elif((os.getcwd().find('rm_wifi_test_app') != -1) and out_file_name.find('rm_wifi_test_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_test_app_', ra6w_grp) + + elif((os.getcwd().find('rm_wifi_test_app') != -1) and out_file_name.find('rm_wifi_test_app_at_sdio.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_test_app_at_sdio_', ra6w_grp) + + elif((os.getcwd().find('rm_wifi_test_app') != -1) and out_file_name.find('rm_wifi_test_app_at_spi.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_test_app_at_spi_', ra6w_grp) + + elif((os.getcwd().find('rm_wifi_test_app') != -1) and out_file_name.find('rm_wifi_test_app_at_uart.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'rm_wifi_test_app_at_uart_', ra6w_grp) + + elif((os.getcwd().find('red_wifi_test_app') != -1) and out_file_name.find('red_wifi_test_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'red_wifi_test_app_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_coex_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_coex_app_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_coex_app_at_sdio.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_coex_app_at_sdio_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_coex_app_at_spi.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_coex_app_at_spi_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_coex_app_at_uart.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_coex_app_at_uart_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_sps_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_sps_app_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_codeless_app.img') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_codeless_app_', ra6w_grp) + + elif((os.getcwd().find('vndm_wlan') != -1) and out_file_name.find('vndm_wlan_ble_coex_provisioning_app') != -1) : + gen_ota_flash_images(in_file_data, fw_version, 'vndm_wlan_ble_coex_provisioning_app_', ra6w_grp) + + elif((os.getcwd().find('rm_ota_w') != -1) and out_file_name.find('rm_ota_w_typical.img')) : + # Same version ex) RA6W1-0000000000-00000 + test_fw_version = ra6w_grp + '-' + fw_version + gen_ota_flash_image(in_file_data, test_fw_version, 'rm_ota_w_ota') + + else: + project_root = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) + configuration_file_path = project_root + "/configuration.xml" + try: + with open(configuration_file_path, "r", encoding="utf-8") as f: + configuration_file_content = f.read() + if(' +#include "hal_data.h" +#ifdef RT_USING_NANO +#include +#else +#include +#endif /* RT_USING_NANO */ + + +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread on RA6W1!\n"); + + while (1) + { + rt_thread_mdelay(1000); + } +} +

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