From 9f539b46f392f0642ee42687233a745b687f082c Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 17:13:06 +0800 Subject: [PATCH 01/31] updated template files, conifg files and script files to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat. --- .../imx/imxrt/imxrt1180-nxp-evk/cm33/.config | 55 +- .../cm33/applications/SConscript | 17 +- .../imxrt1180-nxp-evk/cm33/board/Kconfig | 704 ++- .../cm33/board/MCUX_Config/pin_mux.c | 134 +- .../cm33/board/MCUX_Config/pin_mux.h | 2 + .../imxrt1180-nxp-evk/cm33/board/SConscript | 50 +- .../imxrt1180-nxp-evk/cm33/board/board.c | 340 +- .../imxrt1180-nxp-evk/cm33/board/board.h | 10 +- .../imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h | 33 +- .../imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py | 99 +- .../imxrt/imxrt1180-nxp-evk/cm33/template.ewd | 4924 +++++++++++++++++ .../imxrt/imxrt1180-nxp-evk/cm33/template.ewp | 1281 ++++- .../imxrt1180-nxp-evk/cm33/template.uvoptx | 1332 ++--- .../imxrt1180-nxp-evk/cm33/template.uvprojx | 2597 +++------ .../imxrt1180-nxp-evk/cm33/xip/SConscript | 7 +- 15 files changed, 8265 insertions(+), 3320 deletions(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config index 716a1d80d1d3..ba1a0be158c0 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -118,7 +118,7 @@ CONFIG_RT_ALIGN_SIZE=8 CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y @@ -126,7 +126,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=4096 -# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set # @@ -190,7 +193,6 @@ CONFIG_ARCH_USING_HW_ATOMIC_16=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_FPU=y CONFIG_ARCH_ARM_CORTEX_SECURE=y CONFIG_ARCH_ARM_CORTEX_M33=y @@ -587,8 +589,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_VECTOR is not set -# CONFIG_PKG_USING_SORCH is not set -# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -735,8 +735,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set -# CONFIG_PKG_USING_EVENT_LOOP is not set -# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -820,21 +818,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# MM32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set -# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set -# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set -# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set -# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set -# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set -# end of MM32 HAL & SDK Drivers +# CONFIG_PKG_USING_MM32 is not set # # WCH HAL & SDK Drivers @@ -899,7 +883,9 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -925,12 +911,6 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers - -# -# NOVOSNS Drivers -# -# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set -# end of NOVOSNS Drivers # end of HAL & SDK Drivers # @@ -1111,7 +1091,6 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set -# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set @@ -1467,7 +1446,6 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y # On-chip Peripheral Drivers # # CONFIG_BSP_USING_DMA is not set -# CONFIG_BSP_USING_LPADC is not set CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set @@ -1476,18 +1454,26 @@ CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_LPUART1_RX_USING_DMA is not set # CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART2 is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_LPUART4 is not set +# CONFIG_BSP_USING_LPUART5 is not set +# CONFIG_BSP_USING_LPUART6 is not set +# CONFIG_BSP_USING_LPUART7 is not set +# CONFIG_BSP_USING_LPUART8 is not set +# CONFIG_BSP_USING_LPUART9 is not set # CONFIG_BSP_USING_LPUART10 is not set +# CONFIG_BSP_USING_LPUART11 is not set # CONFIG_BSP_USING_LPUART12 is not set -# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_CLOCK_TIMER is not set # CONFIG_BSP_USING_FLEXSPI is not set # end of On-chip Peripheral Drivers # # Onboard Peripheral Drivers # -# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USE_HYPERRAM is not set +# CONFIG_BSP_USE_MULTICORE is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_FS is not set # end of Onboard Peripheral Drivers @@ -1495,4 +1481,7 @@ CONFIG_BSP_USING_LPUART1=y # # Board extended module Drivers # +# CONFIG_BSP_LINKER_SCRIPT_RAM is not set +CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y +# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript index 8f55fb0d82f5..e617b6f728ff 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript @@ -3,7 +3,11 @@ from building import * import os cwd = GetCurrentDir() -src = Glob('*.c') + +src = Split(""" +main.c +""") + CPPPATH = [cwd] # add for startup script @@ -12,6 +16,17 @@ if rtconfig.PLATFORM in ['gcc']: else: CPPDEFINES = [] +if GetDepend(['BSP_USE_MULTICORE']): + src += Split(""" + multicore_thread.c + """) + +if GetDepend(['BSP_USING_FS']): + src += Split(""" + mnt.c + """) + +# Create application group group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig index d1493215554f..7e2a35c94e49 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -17,7 +17,6 @@ config SOC_MIMXRT1189CVM8C_CM33 default y depends on SOC_MIMXRT1189CVM8C select ARCH_ARM_CORTEX_M33 - select ARCH_ARM_CORTEX_FPU select ARCH_ARM_CORTEX_SECURE menu "On-chip Peripheral Drivers" @@ -26,25 +25,6 @@ menu "On-chip Peripheral Drivers" bool "Enable DMA" default n - menuconfig BSP_USING_LPADC - bool "Enable ADC" - select RT_USING_ADC - default n - - if BSP_USING_LPADC - - config BSP_USING_LPADC1 - bool "Enable LPADC1" - default n - - config BSP_LPADC1_USING_DMA - bool "Enable LPADC1 DMA" - depends on BSP_USING_LPADC1 - depends on BSP_USING_DMA - default n - - endif - config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN @@ -55,18 +35,42 @@ menu "On-chip Peripheral Drivers" select RT_USING_RTC default n - config BSP_USING_USB - bool "Enable USB" - select RT_USING_USB_HOST + menuconfig BSP_USING_USB + bool "Enable USB (CherryUSB)" default n if BSP_USING_USB - config BSP_USB0_HOST - bool "Enable USB0" - default n - - config BSP_USB1_HOST - bool "Enable USB1" + choice + prompt "USB controller" + default BSP_CHERRYUSB_USING_OTG1 + + config BSP_CHERRYUSB_USING_OTG1 + bool "USB OTG1" + + config BSP_CHERRYUSB_USING_OTG2 + bool "USB OTG2" + endchoice + + choice + prompt "USB role" + default BSP_USING_CHERRYUSB_DEVICE + + config BSP_USING_CHERRYUSB_DEVICE + bool "Enable USB Device" + select RT_USING_CHERRYUSB + select RT_CHERRYUSB_DEVICE + + config BSP_USING_CHERRYUSB_HOST + bool "Enable USB Host" + select RT_USING_CHERRYUSB + select RT_CHERRYUSB_HOST + select RT_USING_TIMER_SOFT + endchoice + + config BSP_CHERRYUSB_HOST_MOUSE_DEMO + bool "Enable CherryUSB host mouse shell demo" + depends on BSP_USING_CHERRYUSB_HOST + select RT_CHERRYUSB_HOST_HID default n endif @@ -94,224 +98,444 @@ menu "On-chip Peripheral Drivers" bool "Enable LPUART1" default y - config BSP_LPUART1_RX_USING_DMA - bool "Enable LPUART1 RX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_RX_DMA_CHANNEL - depends on BSP_LPUART1_RX_USING_DMA - int "Set LPUART1 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART1_TX_USING_DMA - bool "Enable LPUART1 TX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_TX_DMA_CHANNEL - depends on BSP_LPUART1_TX_USING_DMA - int "Set LPUART1 TX DMA channel (0-32)" - default 1 - - config BSP_USING_LPUART10 - bool "Enable LPUART10" - default n - - config BSP_LPUART10_RX_USING_DMA - bool "Enable LPUART10 RX DMA" - depends on BSP_USING_LPUART10 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART10_RX_DMA_CHANNEL - depends on BSP_LPUART10_RX_USING_DMA - int "Set LPUART10 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART10_TX_USING_DMA - bool "Enable LPUART10 TX DMA" - depends on BSP_USING_LPUART10 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART10_TX_DMA_CHANNEL - depends on BSP_LPUART10_TX_USING_DMA - int "Set LPUART10 TX DMA channel (0-32)" - default 1 - - config BSP_USING_LPUART12 - bool "Enable LPUART12" - default n - - config BSP_LPUART12_RX_USING_DMA - bool "Enable LPUART12 RX DMA" - depends on BSP_USING_LPUART12 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART12_RX_DMA_CHANNEL - depends on BSP_LPUART12_RX_USING_DMA - int "Set LPUART12 RX DMA channel (0-32)" - default 2 - - config BSP_LPUART12_TX_USING_DMA - bool "Enable LPUART12 TX DMA" - depends on BSP_USING_LPUART12 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART12_TX_DMA_CHANNEL - depends on BSP_LPUART12_TX_USING_DMA - int "Set LPUART12 TX DMA channel (0-32)" - default 3 - endif - - menuconfig BSP_USING_I2C - bool "Enable I2C" - select RT_USING_I2C - default n - if BSP_USING_I2C - config BSP_USING_I2C2 - bool "Enable I2C2" - default y - - config BSP_USING_I2C3 - bool "Enable I2C3" - default n - - choice I2C2_BAUD_SEL - prompt "Select I2C2 badurate" - default HW_I2C2_BADURATE_100kHZ - - config HW_I2C2_BADURATE_100kHZ - bool "Badurate 100kHZ" - - config HW_I2C2_BADURATE_400kHZ - bool "Badurate 400kHZ" - endchoice - - choice I2C3_BAUD_SEL - prompt "Select I2C3 badurate" - default HW_I2C3_BADURATE_100kHZ - - config HW_I2C3_BADURATE_100kHZ - bool "Badurate 100kHZ" - - config HW_I2C3_BADURATE_400kHZ - bool "Badurate 400kHZ" - endchoice - endif + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - menuconfig BSP_USING_CAN - bool "Enable CAN" - select RT_USING_CAN - default n - if BSP_USING_CAN - config BSP_USING_CAN3 - bool "Enable FLEXCAN3" - default n - endif + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 - menuconfig BSP_USING_CLOCK_TIMER - bool "Enable GPT" - default n - select RT_USING_CLOCK_TIME - if BSP_USING_CLOCK_TIMER - config BSP_USING_CLOCK_TIMER1 - bool "Enable GPT1" - default n - - config BSP_USING_CLOCK_TIMER2 - bool "Enable GPT2" - default n - endif + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - menuconfig BSP_USING_FLEXSPI - bool "Enable FLEXSPI" - default n - if BSP_USING_FLEXSPI - config BSP_USING_FLEXSPI1 - bool "Enable FLEXSPI1" - default n - config BSP_USING_FLEXSPI2 - bool "Enable FLEXSPI2" - default n - endif -endmenu + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 -menu "Onboard Peripheral Drivers" + config BSP_USING_LPUART2 + bool "Enable LPUART2" + default n - config BSP_USING_SDRAM - bool "Enable SDRAM" - default n + config BSP_LPUART2_RX_USING_DMA + bool "Enable LPUART2 RX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - menuconfig BSP_USING_ETH - bool "Enable Ethernet" - select RT_USING_NETDEV - select RT_USING_LWIP - default n + config BSP_LPUART2_RX_DMA_CHANNEL + depends on BSP_LPUART2_RX_USING_DMA + int "Set LPUART2 RX DMA channel (0-32)" + default 2 + config BSP_LPUART2_TX_USING_DMA + bool "Enable LPUART2 TX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - if BSP_USING_ETH - config BSP_USING_PHY - select RT_USING_PHY - bool "Enable ethernet phy" - default y + config BSP_LPUART2_TX_DMA_CHANNEL + depends on BSP_LPUART2_TX_USING_DMA + int "Set LPUART2 TX DMA channel (0-32)" + default 3 - if BSP_USING_PHY - config PHY_USING_KSZ8081 - bool "i.MX RT1189EVK uses ksz8081 phy" - default y + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n - if PHY_USING_KSZ8081 - config PHY_KSZ8081_ADDRESS - int "Specify address of phy device" - default 2 + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 4 - config PHY_RESET_KSZ8081_PORT - int "indicate port of reset" - default 6 + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - config PHY_RESET_KSZ8081_PIN - int "indicate pin of reset" - default 12 + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 5 - config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE - bool "Enable the PHY ksz8081 RMII50M mode" - depends on PHY_USING_KSZ8081 - default y - endif + config BSP_USING_LPUART4 + bool "Enable LPUART4" + default n + + config BSP_LPUART4_RX_USING_DMA + bool "Enable LPUART4 RX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART4_RX_DMA_CHANNEL + depends on BSP_LPUART4_RX_USING_DMA + int "Set LPUART4 RX DMA channel (0-32)" + default 6 + + config BSP_LPUART4_TX_USING_DMA + bool "Enable LPUART4 TX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART4_TX_DMA_CHANNEL + depends on BSP_LPUART4_TX_USING_DMA + int "Set LPUART4 TX DMA channel (0-32)" + default 7 + + config BSP_USING_LPUART5 + bool "Enable LPUART5" + default n + + config BSP_LPUART5_RX_USING_DMA + bool "Enable LPUART5 RX DMA" + depends on BSP_USING_LPUART5 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART5_RX_DMA_CHANNEL + depends on BSP_LPUART5_RX_USING_DMA + int "Set LPUART5 RX DMA channel (0-32)" + default 8 + + config BSP_LPUART5_TX_USING_DMA + bool "Enable LPUART5 TX DMA" + depends on BSP_USING_LPUART5 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART5_TX_DMA_CHANNEL + depends on BSP_LPUART5_TX_USING_DMA + int "Set LPUART5 TX DMA channel (0-32)" + default 9 + + config BSP_USING_LPUART6 + bool "Enable LPUART6" + default n + + config BSP_LPUART6_RX_USING_DMA + bool "Enable LPUART6 RX DMA" + depends on BSP_USING_LPUART6 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART6_RX_DMA_CHANNEL + depends on BSP_LPUART6_RX_USING_DMA + int "Set LPUART6 RX DMA channel (0-32)" + default 10 + + config BSP_LPUART6_TX_USING_DMA + bool "Enable LPUART6 TX DMA" + depends on BSP_USING_LPUART6 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART6_TX_DMA_CHANNEL + depends on BSP_LPUART6_TX_USING_DMA + int "Set LPUART6 TX DMA channel (0-32)" + default 11 + + config BSP_USING_LPUART7 + bool "Enable LPUART7" + default n + + config BSP_LPUART7_RX_USING_DMA + bool "Enable LPUART7 RX DMA" + depends on BSP_USING_LPUART7 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART7_RX_DMA_CHANNEL + depends on BSP_LPUART7_RX_USING_DMA + int "Set LPUART7 RX DMA channel (0-32)" + default 12 + + config BSP_LPUART7_TX_USING_DMA + bool "Enable LPUART7 TX DMA" + depends on BSP_USING_LPUART7 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART7_TX_DMA_CHANNEL + depends on BSP_LPUART7_TX_USING_DMA + int "Set LPUART7 TX DMA channel (0-32)" + default 13 + + config BSP_USING_LPUART8 + bool "Enable LPUART8" + default n + + config BSP_LPUART8_RX_USING_DMA + bool "Enable LPUART8 RX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_RX_DMA_CHANNEL + depends on BSP_LPUART8_RX_USING_DMA + int "Set LPUART8 RX DMA channel (0-32)" + default 14 + + config BSP_LPUART8_TX_USING_DMA + bool "Enable LPUART8 TX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_TX_DMA_CHANNEL + depends on BSP_LPUART8_TX_USING_DMA + int "Set LPUART8 TX DMA channel (0-32)" + default 15 + + config BSP_USING_LPUART9 + bool "Enable LPUART9" + default n + + config BSP_LPUART9_RX_USING_DMA + bool "Enable LPUART9 RX DMA" + depends on BSP_USING_LPUART9 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART9_RX_DMA_CHANNEL + depends on BSP_LPUART9_RX_USING_DMA + int "Set LPUART9 RX DMA channel (0-32)" + default 16 + + config BSP_LPUART9_TX_USING_DMA + bool "Enable LPUART9 TX DMA" + depends on BSP_USING_LPUART9 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART9_TX_DMA_CHANNEL + depends on BSP_LPUART9_TX_USING_DMA + int "Set LPUART9 TX DMA channel (0-32)" + default 17 + + config BSP_USING_LPUART10 + bool "Enable LPUART10" + default n + + config BSP_LPUART10_RX_USING_DMA + bool "Enable LPUART10 RX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_RX_DMA_CHANNEL + depends on BSP_LPUART10_RX_USING_DMA + int "Set LPUART10 RX DMA channel (0-32)" + default 18 + + config BSP_LPUART10_TX_USING_DMA + bool "Enable LPUART10 TX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_TX_DMA_CHANNEL + depends on BSP_LPUART10_TX_USING_DMA + int "Set LPUART10 TX DMA channel (0-32)" + default 19 + + config BSP_USING_LPUART11 + bool "Enable LPUART11" + default n + + config BSP_LPUART11_RX_USING_DMA + bool "Enable LPUART11 RX DMA" + depends on BSP_USING_LPUART11 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART11_RX_DMA_CHANNEL + depends on BSP_LPUART11_RX_USING_DMA + int "Set LPUART11 RX DMA channel (0-32)" + default 20 + + config BSP_LPUART11_TX_USING_DMA + bool "Enable LPUART11 TX DMA" + depends on BSP_USING_LPUART11 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART11_TX_DMA_CHANNEL + depends on BSP_LPUART11_TX_USING_DMA + int "Set LPUART11 TX DMA channel (0-32)" + default 21 + + config BSP_USING_LPUART12 + bool "Enable LPUART12" + default n + + config BSP_LPUART12_RX_USING_DMA + bool "Enable LPUART12 RX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_RX_DMA_CHANNEL + depends on BSP_LPUART12_RX_USING_DMA + int "Set LPUART12 RX DMA channel (0-32)" + default 22 + + config BSP_LPUART12_TX_USING_DMA + bool "Enable LPUART12 TX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_TX_DMA_CHANNEL + depends on BSP_LPUART12_TX_USING_DMA + int "Set LPUART12 TX DMA channel (0-32)" + default 23 endif - if BSP_USING_PHY - config PHY_USING_RTL8211F - bool "i.MX RT1189EVK uses rtl8211f phy" - default y + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif - if PHY_USING_RTL8211F - config PHY_RTL8211F_ADDRESS - int "Specify address of phy device" - default 1 + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif +endmenu + menu "Onboard Peripheral Drivers" + + # config BSP_USING_SDRAM + # bool "Enable SDRAM" + # default n - config PHY_RESET_RTL8211F_PORT - int "indicate port of reset" - default 5 + config BSP_USE_HYPERRAM + bool "Enable HyperRAM" + default n - config PHY_RESET_RTL8211F_PIN - int "indicate pin of reset" - default 14 + menuconfig BSP_USE_MULTICORE + bool "Enable Multicore" + default n - endif + if BSP_USE_MULTICORE + config BSP_USE_MULTICORE_KICK_OFF + bool "Enable CM33 Kick-off CM7" + default y + help + Enable CM33 core to kick-off CM7 core startup. + This is required for proper initialization sequence + when CM33 (master) boots CM7 (remote) core. + + config BSP_USE_MULTICORE_RPMSG_LITE + bool "Enable RPMsg-Lite for Inter-Core Communication" + default y + help + Enable RPMsg-Lite messaging system for communication between cores. + RPMsg-Lite provides a lightweight implementation of the RPMsg protocol + for inter-processor communication using shared memory. + CM33 runs as master core, CM7 runs as remote core. + + if BSP_USE_MULTICORE_RPMSG_LITE + config RPMSG_LITE_LINK_ID + int "RPMsg-Lite Link ID" + default 0 + help + Specify the link ID for RPMsg-Lite communication. + Default is RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID (0). + + config RPMSG_LOCAL_EPT_ADDR + int "Local Endpoint Address (CM33 side)" + range 0 65535 + default 40 + help + Specify the local endpoint address for RPMsg communication on CM33 side. + + config RPMSG_NS_ANNOUNCE_STRING + string "RPMsg Nameservice Announce String" + default "rpmsg-openamp-demo-channel" + help + The string used by CM7 remote core to announce the service. + + config RPMSG_SHARED_MEM_SIZE + int "RPMsg Shared Memory Size (bytes)" + default 6144 + help + Size of shared memory region for RPMsg communication. + endif endif + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_SAL + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + depends on RT_USING_LWIP_VER_NUM >= 0x20000 + default 1 + + config NETC_USE_SWT + int "Enable NETC switch mode (0: EP0, 1: switch)" + range 0 1 + default 0 + + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y endif menuconfig BSP_USING_FS @@ -326,7 +550,7 @@ menu "Onboard Peripheral Drivers" select BSP_USING_SDIO select RT_USING_DFS_ELMFAT default n - + config BSP_USING_QSPI_FLASH_FS bool "Enable QSPI Flash (LittleFS)" select BSP_USING_FLEXSPI @@ -344,4 +568,28 @@ menu "Board extended module Drivers" endmenu +choice + prompt "Linker Script Selection" + default BSP_LINKER_SCRIPT_RAM + help + Select the linker script that matches your target memory configuration. + + config BSP_LINKER_SCRIPT_RAM + bool "RAM (internal SRAM only)" + help + Link the image to run entirely from internal SRAM. + + config BSP_LINKER_SCRIPT_FLEXSPI_NOR + bool "FlexSPI NOR Flash (XIP from external NOR flash)" + help + Link the image to execute-in-place (XIP) from external NOR flash + connected via FlexSPI. + + config BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM + bool "FlexSPI NOR Flash + HyperRAM (XIP + external HyperRAM)" + help + Link the image to XIP from external NOR flash and use HyperRAM + as additional RAM. +endchoice + endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c index 4e483fad36ab..6fa3317b2309 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c @@ -59,70 +59,116 @@ void BOARD_InitPins(void) CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ +#ifdef BSP_USING_LPUART1 IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_08_LPUART1_TX, - 0U); + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_09_LPUART1_RX, - 0U); + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_08_LPUART1_TX, - 0x02U); + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_09_LPUART1_RX, - 0x02U); - + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +#endif + +#ifdef BSP_USING_LPUART10 IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_32_LPUART10_TX, - 0U); + IOMUXC_GPIO_AD_32_LPUART10_TX, /* GPIO_AD_32 is configured as LPUART10_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_33_LPUART10_RX, - 0U); + IOMUXC_GPIO_AD_33_LPUART10_RX, /* GPIO_AD_33 is configured as LPUART10_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_32_LPUART10_TX, - 0x02U); + IOMUXC_GPIO_AD_32_LPUART10_TX, /* GPIO_AD_32 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_33_LPUART10_RX, - 0x02U); - + IOMUXC_GPIO_AD_33_LPUART10_RX, /* GPIO_AD_33 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +#endif + +#ifdef BSP_USING_LPUART12 IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_19_LPUART12_TX, - 0U); + IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 is configured as LPUART12_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_20_LPUART12_RX, - 0U); + IOMUXC_GPIO_AON_20_LPUART12_RX, /* GPIO_AON_20 is configured as LPUART12_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_19_LPUART12_TX, - 0x02U); + IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_20_LPUART12_RX, - 0x02U); - + IOMUXC_GPIO_AON_20_LPUART12_RX, /* GPIO_AON_20 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +#endif + +#ifdef BSP_USING_I2C2 IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, - 1U); + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, - 1U); + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, - 0x1DU); + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, - 0x1DU); - + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ +#endif + +#ifdef BSP_USING_I2C3 IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_18_LPI2C3_SCL, - 0U); + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_19_LPI2C3_SDA, - 0U); + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_18_LPI2C3_SCL, - 0x1DU); + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_19_LPI2C3_SDA, - 0x1DU); + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ +#endif } void BOARD_InitLeds(void) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h index 03590a1759b4..c2838ad1d2ff 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h @@ -12,6 +12,8 @@ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ +#include + /*! * @addtogroup pin_mux * @{ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript index 55443c4c38bf..bc237a49c489 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript @@ -1,7 +1,8 @@ Import('rtconfig') +Import('RTT_ROOT') from building import * -import rtconfig +import os cwd = GetCurrentDir() @@ -30,19 +31,58 @@ if GetDepend(['BSP_USING_LPADC1']): else: CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'ARM_MATH_CM33'] +LINKFLAGS = '' if rtconfig.PLATFORM in ['gcc']: CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION'] if rtconfig.PLATFORM in ['armcc', 'armclang']: - # CPPDEFINES += ['SDK_DEBUGCONSOLE'] CPPDEFINES += ['NDEBUG'] if rtconfig.PLATFORM in ['iccarm']: CPPDEFINES += ['NDEBUG'] - # CPPDEFINES += ['FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) +if GetDepend(['BSP_USE_HYPERRAM']): + CPPDEFINES += ['USE_HYPERRAM=1'] + +if GetDepend(['BSP_USE_MULTICORE']): + CPPDEFINES += ['__USE_SHMEM', 'MULTICORE_APP=1'] + if rtconfig.PLATFORM in ['gcc']: + LINKFLAGS += ' -Wl,-defsym,__use_shmem__=1' + LINKFLAGS += ' -Wl,-defsym,__multicore__=1' + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS += ' --predefine="-D__use_shmem__=1"' + LINKFLAGS += ' --predefine="-D__multicore__=1"' + if rtconfig.PLATFORM in ['iccarm']: + LINKFLAGS += ' __use_shmem__=1' + LINKFLAGS += ' __multicore__=1' + +if GetDepend(['BSP_USING_ETH']): + CPPDEFINES += ['SDK_NETC_USED=1', 'FSL_ETH_ENABLE_CACHE_CONTROL=1'] + +if GetDepend(['RT_USING_CHERRYUSB']): + cherryusb_path = os.path.join(RTT_ROOT, 'components', 'drivers', 'usb', 'cherryusb') + src += ['cherryusb_port.c'] + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM']): + src += ['cherryusb_cdc_acm.c'] + if GetDepend(['BSP_CHERRYUSB_HOST_MOUSE_DEMO']): + src += ['usbh_mouse_demo.c'] + CPPPATH += [ + cherryusb_path, + os.path.join(cherryusb_path, 'common'), + os.path.join(cherryusb_path, 'core'), + os.path.join(cherryusb_path, 'class', 'hub'), + os.path.join(cherryusb_path, 'class', 'cdc'), + os.path.join(cherryusb_path, 'class', 'hid'), + ] + +if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR']): + CPPDEFINES += ['XIP_BOOT_HEADER_ENABLE=1', 'XIP_EXTERNAL_FLASH=1'] + +if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM']): + CPPDEFINES += ['XIP_BOOT_HEADER_ENABLE=1', 'XIP_EXTERNAL_FLASH=1'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES, LINKFLAGS = LINKFLAGS) Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index c1b909fc8a57..a3b5b1ae33e8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -22,11 +22,59 @@ #include "fsl_dcdc.h" #include "fsl_trdc.h" #include "fsl_rgpio.h" + +#ifdef BSP_USING_ETH +#include "fsl_netc_endpoint.h" +#include "fsl_netc_switch.h" +#include "fsl_netc_mdio.h" +#endif + +#ifdef BSP_USE_MULTICORE +#include "mcmgr.h" +#endif + /******************************************************************************* * Definitions ******************************************************************************/ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) +#ifdef BSP_USE_MULTICORE +#define ENABLE_CM7_TCM_ECC 0U + +/* + * This workaround is used for kick-off CM7 when CM7 image vector table is not + * at 0x0 and CM7 TCM ECC fuse is set(1). + * When CM7 TCM ECC fuse is unset(0), this workaround is useless and no side + * effect when applied. + */ +#define ENABLE_WORKAROUND_CM7_KICK_OFF 1U + +#define CONTAINER_BASE_ADDR 0x38001000UL /* For FlexSPI, base addr(0x38000000) + 0x1000 offset */ +#define CONTAINER_MAX_NUM 2U +#define CONTAINER_SIZE 0x400U /* in bytes */ +#define CONTAINER_HEADER_SIZE 16U /* in bytes */ +#define IMAGE_ENTRY_SIZE 0x80U /* in bytes */ +#define IMAGE_TAG_NUM 0x87U +#define IMAGE_TYPE_EXECUTABLE 0x03U +#define CORE_ID_CM7 0x02U + +#define CM7_ITCM_START_ADDR 0x0UL /* from pespective of CM7 */ +#define CM7_ITCM_END_ADDR 0x80000UL /* from pespective of CM7 */ +#define CM7_ITCM_SIZE 0x80000UL /* from pespective of CM7 */ +#define CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN 0x303C0000 /* from pespective of CM33 */ +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -37,6 +85,196 @@ AT_QUICKACCESS_SECTION_DATA(volatile uint32_t g_systickCounter); * Code ******************************************************************************/ +#ifdef BSP_USE_MULTICORE +/*! + * @brief Get CM7 Image Address and size information from container header + * + * Container Header structure are shown as the following + * + * 31 23 15 7 0 + * +--------------------+--------------------+--------------------+--------------------+ + * 0x0 | Tag (0x87) | Length | Version (0x00) | + * +--------------------+--------------------+--------------------+--------------------+ + * 0x4 | SRK Flags | + * +--------------------+--------------------+--------------------+--------------------+ + * 0x8 | Num of Images | Fuse Version | SW Version | + * +--------------------+--------------------+--------------------+--------------------+ + * 0xC | R | Signature Block Offset | + * +--------------------+--------------------+--------------------+--------------------+ + * | | + * + | Image Array Entry | + * | | + * +--------------------+--------------------+--------------------+--------------------+ + * | | + * + | Signature Block | + * | | + * +--------------------+--------------------+--------------------+--------------------+ + * + * Its' image entry are further layout as the following + * + * +0x4 +0x8 +0xC + * +--------------------+--------------------+--------------------+--------------------+ + * 0x0 | Image Offset | Image Size | Load Address | + * +--------------------+--------------------+--------------------+--------------------+ + * 0x10 | Entry Point | Flags | Meta | + * +--------------------+--------------------+--------------------+--------------------+ + * 0x20 | | + * | HASH | + * | | + * +--------------------+--------------------+--------------------+--------------------+ + * 0x60 | R | + * +--------------------+--------------------+--------------------+--------------------+ + * + * Its' Flag contains the Image Type and Core + * + * 31 23 15 11 7 3 0 + * +--------------------+--------------------+----------+---------+----------+---------+ + * Flags | R | H/E | Core | Type | + * +--------------------+--------------------+--------------------+----------+---------+ + * + * The function iterate through each container header and its image entries until it find + * CM7 Exexutable Image. The information of the image is then returned to user + * + * More information can be found in RM "System Boot" Chapter + * + * @param pImageSrcAddr CM7 Image Srouce Address from CM33 perspective + * @param pImageDestAddr CM7 Image Destination Address from CM33 perspective + * @param pImageSize CM7 Image Size + * @param pImageBootAddr CM7 Image Load Address from CM7 prespective + */ +status_t BOARD_GetCore1ImageAddrSize(uint32_t *pImageSrcAddr, + uint32_t *pImageDestAddr, + uint32_t *pImageSize, + uint32_t *pImageBootAddr) +{ + /* parser the container to get the CM7 image location and size */ + + uint32_t i, j; + + uint32_t image_src_addr = 0U; + uint32_t image_dest_addr = 0U; + uint32_t image_size = 0U; + uint32_t image_boot_addr = 0U; + + status_t ret = kStatus_Fail; + + uint32_t *pContainer = (uint32_t *)CONTAINER_BASE_ADDR; + + for (i = 0U; i < CONTAINER_MAX_NUM; i++) + { + uint32_t image_num, image_tag = pContainer[0] >> 24U; + + if (image_tag != IMAGE_TAG_NUM) + { + break; + } + + image_num = pContainer[2] >> 24U; + if (image_num >= 2U) + { + uint32_t *pImage = &pContainer[CONTAINER_HEADER_SIZE / sizeof(uint32_t)]; + for (j = 0U; j < image_num; j++) + { + uint32_t image_type = pImage[6] & 0xFU; + uint32_t image_core = (pImage[6] >> 4U) & 0xFU; + + if ((image_type == IMAGE_TYPE_EXECUTABLE) && (image_core == CORE_ID_CM7)) + { + /* pImage[0] is the image offset, which is based on current container header */ + image_src_addr = ((uint32_t)pContainer) + pImage[0]; + image_size = pImage[1]; + image_dest_addr = pImage[2]; + image_boot_addr = pImage[4]; + ret = kStatus_Success; + break; + } + + pImage += IMAGE_ENTRY_SIZE / sizeof(uint32_t); + } + } + + pContainer += CONTAINER_SIZE / sizeof(uint32_t); + } + + if (pImageSrcAddr != NULL) + { + *pImageSrcAddr = image_src_addr; + } + + if (pImageDestAddr != NULL) + { + *pImageDestAddr = image_dest_addr; + } + + if (pImageSize != NULL) + { + *pImageSize = image_size; + } + + if (pImageBootAddr != NULL) + { + *pImageBootAddr = image_boot_addr; + } + + return ret; +} + +/* + * image_src_addr image_dest_addr is address from perspective of core0(CM33) + * boot_addr is address from perspective of core1(CM7) + */ +void BOARD_PrepareCore1(uint32_t image_src_addr, uint32_t image_dest_addr, uint32_t image_size, uint32_t boot_addr) +{ + /* The Cortex M7 XIP image runs from NOR Flash */ + if ((boot_addr >= CM7_ITCM_END_ADDR) || ((CM7_ITCM_START_ADDR > 0U) && (boot_addr < CM7_ITCM_START_ADDR))) + { + /* Out of CM7 ITCM address space, CM7 core and its TCM ECC probably not initialized yet, do it here */ + Prepare_CM7(boot_addr); + +#if (defined(ENABLE_WORKAROUND_CM7_KICK_OFF) && (ENABLE_WORKAROUND_CM7_KICK_OFF > 0U)) + /* + * When CM7 TCM ECC fuse is set(1) + * ROM will powerup CM7 domain, CM7 VTOR is settled(always 0) only when powerup, + * so CM33 image has no chance to update CM7 VTOR. Thus those CM7 image with + * vector table is not located at 0x0, boot fails. + * The workaround here, is to copy two header word of image vector(normally SP + * and Reset_Handler) to CM7 initial VTOR addr(0x0), as a fake vector table and stepping-stone, + * then CM7 boot successfully. + * + * Note: + * 1. The fake vector table is one-time used, memory(0x0~0x07) is released when CM7 + * starts to execute Reset_Handler. + * 2. CM7 Reset_Handler will update CM7 VTOR to real vector addr of the CM7 image. + * 3. The workaround doesn't take effect(also no side effect), when CM7 TCM ECC fuse is set(0) + */ + uint32_t *pRamVect = (uint32_t *)CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN; + uint32_t *pBootVect = (uint32_t *)boot_addr; + pRamVect[0] = pBootVect[0]; + pRamVect[1] = pBootVect[1]; +#endif /* (defined(ENABLE_WORKAROUND_CM7_KICK_OFF) && (ENABLE_WORKAROUND_CM7_KICK_OFF > 0U)) */ + } + /* The Cortex M7 image runs from internal ITCM RAM */ + else + { +#if ENABLE_CM7_TCM_ECC + /* Do noting, CM7 image has been copied by ROM */ +#else + Prepare_CM7(boot_addr); + /* Copy CM7 image from FLASH to CM7 ITCM */ + if ((image_size > 0) && (image_size < CM7_ITCM_SIZE)) + { + /* Use memcpy to copy the image */ + (void)memcpy((void *)CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN, (void *)image_src_addr, image_size); + + /* Ensure data is written to memory before CM7 starts */ + __DSB(); + __ISB(); + } +#endif + } +} +#endif + /* MPU configuration. */ #if __CORTEX_M == 7 void BOARD_ConfigMPU(void) @@ -434,14 +672,6 @@ void BOARD_ConfigMPU(void) ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 1U)); #endif - // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] - // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 - // ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); - - // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] - // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 - ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 2U)); - /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); @@ -1206,47 +1436,65 @@ void SysTick_Handler(void) } -#ifdef BSP_USING_LPUART -void imxrt_uart_pins_init(void) +#ifdef BSP_USE_MULTICORE +static int second_core_boot(void) { -#ifdef BSP_USING_LPUART1 - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ + /* + * RT1180 Specific CM7 Kick Off operation + */ + /* Trigger S401 */ + while ((MU_RT_S3MUA->TSR & MU_TSR_TE0_MASK) == 0) { + ; } /* Wait TR empty */ + MU_RT_S3MUA->TR[0] = 0x17d20106; + while ((MU_RT_S3MUA->RSR & MU_RSR_RF0_MASK) == 0) { + ; } /* Wait RR Full */ + while ((MU_RT_S3MUA->RSR & MU_RSR_RF1_MASK) == 0) { + ; } /* Wait RR Full */ + + /* Response from ELE must be always read */ + __attribute__((unused)) volatile uint32_t result1, result2; + result1 = MU_RT_S3MUA->RR[0]; + result2 = MU_RT_S3MUA->RR[1]; + + /* Deassert Wait */ + BLK_CTRL_S_AONMIX->M7_CFG = + (BLK_CTRL_S_AONMIX->M7_CFG & (~BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK)) | + BLK_CTRL_S_AONMIX_M7_CFG_WAIT(0); + + return 0; +} +/*! + * @brief Application-specific implementation of the SystemInitHook() weak function. + */ +void SystemInitHook(void) +{ + /* Initialize MCMGR - low level multicore management library. Call this + function as close to the reset entry as possible to allow CoreUp event + triggering. The SystemInitHook() weak function overloading is used in this + application. */ + (void)MCMGR_EarlyInit(); +} #endif +#ifdef BSP_USING_ETH +void PHY_Reset(void) +{ + /* Reset PHY8201 for ETH4. Reset 10ms, wait 72ms. */ + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 0); + SDK_DelayAtLeastUs(10000, CLOCK_GetFreq(kCLOCK_CpuClk)); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 1); + SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); } -#endif /* BSP_USING_LPUART */ - -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ +#endif void rt_hw_board_init() { @@ -1254,10 +1502,8 @@ void rt_hw_board_init() BOARD_CommonSetting(); BOARD_ConfigMPU(); BOARD_InitPins(); - -// BOARD_InitLeds(); BOARD_BootClockRUN(); - BOARD_InitPeripherals(); +// BOARD_InitPeripherals(); NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h index 46f34985b9e9..82e65d68f392 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h @@ -161,6 +161,7 @@ void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage); void BOARD_NETC_Init(void); void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega); void BOARD_CommonSetting(void); +void PHY_Reset(void); /* */ #if defined(__ARMCC_VERSION) @@ -179,11 +180,14 @@ extern int __HeapLimit; #define HEAP_END ((void *)&__HeapLimit) #endif -/*! @brief The board flash size */ -#define BOARD_FLASH_SIZE (0x1000000U) - void rt_hw_board_init(void); +status_t BOARD_GetCore1ImageAddrSize(uint32_t *pImageSrcAddr, + uint32_t *pImageDestAddr, + uint32_t *pImageSize, + uint32_t *pImageBootAddr); +void BOARD_PrepareCore1(uint32_t image_src_addr, uint32_t image_dest_addr, uint32_t image_size, uint32_t boot_addr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h index c09fa5d163b8..9e88a2b2dd04 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -61,18 +61,21 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 4096 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 /* kservice options */ @@ -101,10 +104,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -113,7 +116,6 @@ #define RT_USING_CPU_FFS #define ARCH_ARM #define ARCH_ARM_CORTEX_M -#define ARCH_ARM_CORTEX_FPU #define ARCH_ARM_CORTEX_SECURE #define ARCH_ARM_CORTEX_M33 @@ -122,12 +124,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 4096 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -160,8 +162,8 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ @@ -296,10 +298,6 @@ /* end of Kendryte SDK */ -/* MM32 HAL & SDK Drivers */ - -/* end of MM32 HAL & SDK Drivers */ - /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -333,10 +331,6 @@ /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ - -/* NOVOSNS Drivers */ - -/* end of NOVOSNS Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -437,6 +431,7 @@ /* Board extended module Drivers */ +#define BSP_LINKER_SCRIPT_FLEXSPI_NOR /* end of Hardware Drivers Config */ #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py index ce740398c1b5..4c71e5232c82 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py @@ -32,6 +32,36 @@ BUILD = 'debug' # BUILD = 'release' +# Read linker script selection from rtconfig.h (set by Kconfig BSP_LINKER_SCRIPT_* choice). +# Supported types: RAM, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM +# Default to RAM when no match is found. +_LINKER_SCRIPT_TYPE = 'RAM' +_rtconfig_h = os.path.join(os.path.dirname(__file__), 'rtconfig.h') +if os.path.exists(_rtconfig_h): + with open(_rtconfig_h, 'r') as _f: + for _line in _f: + _s = _line.strip() + if _s.startswith('//'): + continue + # Check the most specific name first to avoid false matches. + if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM'): + _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR_HYPERRAM' + break + if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR'): + _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR' + break + if _s.startswith('#define BSP_LINKER_SCRIPT_RAM'): + _LINKER_SCRIPT_TYPE = 'RAM' + break + +# Base filename (without extension) for the selected linker script. +_LINKER_SCRIPT_BASE = { + 'RAM': 'MIMXRT1189xxxxx_cm33_ram', + 'FLEXSPI_NOR': 'MIMXRT1189xxxxx_cm33_flexspi_nor', + 'FLEXSPI_NOR_HYPERRAM': 'MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram', +}[_LINKER_SCRIPT_TYPE] + + if PLATFORM == 'gcc': PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' @@ -46,10 +76,13 @@ STRIP = PREFIX + 'strip' DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' - LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage -T board/linker_scripts/link.lds' + + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.ld' + + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage -T ' + LINKER_SCRIPT CPATH = '' LPATH = '' @@ -60,17 +93,17 @@ if BUILD == 'debug': CFLAGS += ' -g' AFLAGS += ' -g' - # CFLAGS += ' -O1' + # CFLAGS += ' -O1' CFLAGS += ' -O0' else: CFLAGS += ' -O2 -Os' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - # module setting + # module setting CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' - CXXFLAGS += CFLAGS - + CXXFLAGS += CFLAGS + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ @@ -88,9 +121,12 @@ DEVICE = ' --cpu ' + CPU + '.fp.sp' CFLAGS = DEVICE + ' --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.scf"' - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.scf' + + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "' + LINKER_SCRIPT + '"' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' CFLAGS += ' --diag_suppress=66,1296,186,6314' CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' @@ -129,9 +165,13 @@ AFLAGS = DEVICE + ' --apcs=interwork ' AFLAGS += ' -x assembler-with-cpp' AFLAGS += ' -Wa,-mimplicit-it=thumb' + + # armlink --scatter accepts the file with extension. + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.scf' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board/linker_scripts/link" ' + LFLAGS += r' --strict --scatter "' + LINKER_SCRIPT + '" ' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' @@ -142,7 +182,7 @@ AFLAGS += ' -g' else: CFLAGS += ' -O2' - + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' @@ -179,7 +219,9 @@ else: CFLAGS += ' -Oh' - LFLAGS = ' --config "board/linker_scripts/link.icf"' + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.icf' + + LFLAGS = ' --config "' + LINKER_SCRIPT + '"' LFLAGS += ' --redirect _Printf=_PrintfTiny' CXXFLAGS = CFLAGS @@ -187,9 +229,42 @@ EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' +# Map from linker script type to the matching Keil target name. +_LINKER_SCRIPT_TO_KEIL_TARGET = { + 'RAM': 'rtthread_ram', + 'FLEXSPI_NOR': 'rtthread_flexspi_nor', + 'FLEXSPI_NOR_HYPERRAM': 'rtthread_flexspi_nor_hyperram', +} + +def update_keil_active_target(uvoptx_path='project.uvoptx'): + """Set in project.uvoptx to match the selected linker script.""" + import xml.etree.ElementTree as etree + + active = _LINKER_SCRIPT_TO_KEIL_TARGET.get(_LINKER_SCRIPT_TYPE, 'rtthread_ram') + + if not os.path.exists(uvoptx_path): + return + + tree = etree.parse(uvoptx_path) + root = tree.getroot() + + for tgt in tree.findall('Target'): + tname = tgt.find('TargetName') + is_current = tgt.find('TargetOption/OPTFL/IsCurrentTarget') + if tname is not None and is_current is not None: + is_current.text = '1' if tname.text == active else '0' + + out = open(uvoptx_path, 'w') + out.write('\n') + out.write(etree.tostring(root, encoding='utf-8').decode()) + out.close() + + print('Keil active target set to: ' + active) + def dist_handle(BSP_ROOT, dist_dir): import sys cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(os.path.dirname(BSP_ROOT)), 'tools')) + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) from sdk_dist import dist_do_building dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd new file mode 100644 index 000000000000..7d85c610659e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd @@ -0,0 +1,4924 @@ + + + 4 + + rtthread_ram + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + rtthread_flexspi_nor + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + + + IJET_ID + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + rtthread_flexspi_nor_hyperram + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp index 6de7ddc90f83..202125caf683 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp @@ -2,33 +2,1132 @@ 4 - Debug + rtthread_ram ARM - 1 + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + + rtthread_flexspi_nor + + ARM + + 0 General 3 - 36 + 37 1 - 1 + 0 + ICCARM 2 - 38 + 39 1 - 1 + 0 + + @@ -480,7 +1591,7 @@ 12 1 - 1 + 0 CUSTOM - 3 + 4 - 0 inputOutputBased @@ -688,9 +1798,9 @@ ILINK 0 - 27 + 28 1 - 1 + 0 + @@ -1064,7 +2178,7 @@ 0 1 - 1 + 0 - Release + rtthread_flexspi_nor_hyperram ARM @@ -1095,24 +2209,24 @@ General 3 - 36 + 37 1 0 + @@ -1306,12 +2424,12 @@ ICCARM 2 - 38 + 39 1 0 + + @@ -1688,7 +2814,7 @@ CUSTOM - 3 + 4 - 0 inputOutputBased @@ -1772,7 +2897,7 @@ ILINK 0 - 27 + 28 1 0 + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx index 0dab8ecf45ec..9d840ecb20b4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx @@ -22,7 +22,7 @@ - rtthread + rtthread_ram 0x4 ARM-ADS @@ -73,11 +73,11 @@ 0 - 0 + 1 0 - 1 + 0 - 0 + 8 0 1 @@ -113,14 +113,14 @@ - + .\evkmimxrt1180_ram_cm33.ini Segger\JL2CM3.dll 0 JL2CM3 - -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33.FMIMXRT1180 CM33 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) + -U600109563 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33.FMIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) 0 @@ -181,1008 +181,324 @@ - - Applications - 0 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - applications\mnt.c - mnt.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Compiler - 0 - 0 - 0 - 0 - - 2 - 3 - 1 - 0 - 0 - 0 - ..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c - syscall_mem.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c - syscalls.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\..\..\..\..\components\libc\compilers\common\cctype.c - cctype.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\..\..\..\..\components\libc\compilers\common\cstdlib.c - cstdlib.c - 0 - 0 - - - 2 - 7 - 1 - 0 - 0 - 0 - ..\..\..\..\..\components\libc\compilers\common\cstring.c - cstring.c - 0 - 0 - - - 2 - 8 - 1 - 0 - 0 - 0 - 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-FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx index d396836dbb68..953b5687c1fb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx @@ -7,7 +7,7 @@ - rtthread + rtthread_ram 0x4 ARM-ADS 6220000::V6.22::ARMCLANG @@ -52,7 +52,757 @@ rtthread 1 0 - 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 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XIP_EXTERNAL_FLASH=1, MCUXPRESSO_SDK, MCUX_META_BUILD, RT_USING_ARMLIBC, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, CPU_MIMXRT1189CVM8C_cm33, XIP_BOOT_HEADER_ENABLE=1, NDEBUG, MIMXRT1189_cm33_SERIES, ARM_MATH_CM33, XIP_BOOT_HEADER_DCD_ENABLE=1 + - ..\..\..\..\..\libcpu\arm\common;packages\nxp-imxrt-sdk-latest\MIMXRT1180\CMSIS\Core\Include;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\utilities\debug_console_lite;..\..\..\..\..\libcpu\arm\cortex-m33;applications;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\cm33;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\..\components\libc\compilers\common\include;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\periph;board\ports;board;..\..\..\..\..\components\libc\posix\ipc;xip;..\libraries\drivers;..\..\..\..\..\components\finsh;..\..\..\..\..\components\drivers\include;..\..\..\..\..\include;..\..\..\..\..\components\drivers\phy;..\..\..\..\..\components\libc\posix\io\epoll;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\net\utest;..\..\..\..\..\components\libc\posix\io\eventfd;board\MCUX_Config;..\..\..\..\..\components\drivers\smp_call;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\compilers\common\extension;packages\nxp-imxrt-sdk-latest\MIMXRT1180\CMSIS\Core\m-profile;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189;..\..\..\..\..\components\libc\posix\io\poll;. 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packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart_edma.c - - - fsl_edma.c - 1 - packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma.c - - - fsl_edma_soc.c - 1 - packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma_soc.c - - - fsl_dcdc.c - 1 - packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c - - - fsl_common_arm.c - 1 - packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common_arm.c - - - fsl_s3mu.c - 1 - packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_s3mu.c - - - - - xip - - - fsl_flexspi_nor_boot.c - 1 - xip\fsl_flexspi_nor_boot.c - - - evkmimxrt1180_flexspi_nor_config.c - 1 - xip\evkmimxrt1180_flexspi_nor_config.c - - - - @@ -2221,7 +1142,7 @@ - <Project Info> + template 0 1 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript index 88aa7fb12a7f..37a5aad92e90 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript @@ -8,13 +8,8 @@ if GetDepend('BSP_USING_QSPIFLASH'): CPPPATH = [cwd] LINKFLAGS = '' - if rtconfig.PLATFORM in ['armcc', 'armclang']: - LINKFLAGS += ' --keep=*(.boot_hdr.container)' - # LINKFLAGS += ' --keep=*(.boot_hdr.xmcd_data)' - LINKFLAGS += ' --keep=*(.boot_hdr.conf)' - LINKFLAGS += ' --entry=Reset_Handler ' + if rtconfig.PLATFORM in ['armcc', 'armclang']: LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' - LINKFLAGS += ' --predefine="-DXIP_EXTERNAL_FLASH=1"' group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) Return('group') From 1f9ecba7f26bf1152bbe9c341b7eabafb8c517ef Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 17:18:37 +0800 Subject: [PATCH 02/31] updated different link files of GCC, IAR and KEIL, for supporting multicore kick-off and different loading methods --- ...f => MIMXRT1189xxxxx_cm33_flexspi_nor.icf} | 4 +- ...ds => MIMXRT1189xxxxx_cm33_flexspi_nor.ld} | 21 +- ...f => MIMXRT1189xxxxx_cm33_flexspi_nor.scf} | 6 +- ...XRT1189xxxxx_cm33_flexspi_nor_hyperram.icf | 187 +++ ...MXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld | 383 ++++++ ...XRT1189xxxxx_cm33_flexspi_nor_hyperram.scf | 248 ++++ .../MIMXRT1189xxxxx_cm33_ram.icf | 158 +++ .../MIMXRT1189xxxxx_cm33_ram.ld | 341 ++++++ .../MIMXRT1189xxxxx_cm33_ram.scf | 197 ++++ .../evkmimxrt1180_cm33.jlinkscript | 1041 ----------------- .../evkmimxrt1180_flexspi_nor_cm33.ini | 417 ------- 11 files changed, 1532 insertions(+), 1471 deletions(-) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/{link.icf => MIMXRT1189xxxxx_cm33_flexspi_nor.icf} (96%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/{link.lds => MIMXRT1189xxxxx_cm33_flexspi_nor.ld} (96%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/{link.scf => MIMXRT1189xxxxx_cm33_flexspi_nor.scf} (98%) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.scf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.icf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.ld create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.scf delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf similarity index 96% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf index 9dc0fc389dc4..4b08ecca3c88 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf @@ -74,7 +74,7 @@ if (isdefinedsymbol(__stack_size__)) { if (isdefinedsymbol(__heap_size__)) { define symbol __size_heap__ = __heap_size__; } else { - define symbol __size_heap__ = 0x04000; + define symbol __size_heap__ = 0x08000; } define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); @@ -155,7 +155,7 @@ define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_imag define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; -initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess }; +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; do not initialize { section .noinit }; if (isdefinedsymbol(__use_shmem__)) { do not initialize { section rpmsg_sh_mem_section }; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld similarity index 96% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld index 890bc3f57649..2e4cafeabe52 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld @@ -1,18 +1,20 @@ /* ** ################################################################### ** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 ** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1180RM, Rev 2, 12/2022 -** Version: rev. 0.1, 2021-03-09 -** Build: b240109 +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -24,6 +26,9 @@ /* Entry Point */ ENTRY(Reset_Handler) +__use_shmem__ = 1; +__multicore__ = 1; + /* Board memory map */ m_code_tcm_start = 0x0FFE0000; m_code_tcm_size = 0x00020000; @@ -40,7 +45,7 @@ m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; m_flash_start = 0x28000000; -m_flash_size = 0x01000000; +m_flash_size = 0x00800000; m_core1_image_maximum_size = 0x00040000; @@ -59,7 +64,7 @@ m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; m_container_start = m_flash_start + m_container_offset; m_container_end = m_container_start + m_container_size - 1; -app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000; +app_image_offset = 0x0000B000; vector_table_size = 0x00000400; m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; @@ -67,7 +72,7 @@ m_qadata_start = m_system_tcm_start; m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; m_ram_vector_table_start = m_code_tcm_start; m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; -m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; /* Target specific definition, code & data allocation */ m_code_size = m_flash_size - app_image_offset - vector_table_size; @@ -277,7 +282,6 @@ SECTIONS { . = ALIGN(4); __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) *(.data) /* .data sections */ *(.data*) /* .data* sections */ *(DataQuickAccess) /* quick access data section */ @@ -336,7 +340,6 @@ SECTIONS /* This is used by the startup in order to initialize the .bss section */ . = ALIGN(4); __bss_start__ = .; - *(m_usb_dma_noninit_data) *(.bss) *(.bss*) *(COMMON) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.scf similarity index 98% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.scf index 5473f23127c9..1002a3e3a03e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.scf @@ -78,7 +78,7 @@ #if defined(__heap_size__) #define heap_size __heap_size__ #else - #define heap_size 0x20000 + #define heap_size 0x08000 #endif /* Target specific definition, code & data allocation */ @@ -173,8 +173,10 @@ LR_m_text m_text_start m_text_size ER_m_QuickAccessCode m_qacode_start m_qacode_size { - fsl_flexspi.o (+RO-CODE) .ANY (CodeQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) } ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf new file mode 100644 index 000000000000..263c64ce5dcc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf @@ -0,0 +1,187 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x00800000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol m_fcb_offset = 0x400; +define symbol m_fcb_size = 0x200; +define symbol m_fcb_start = m_flash_start + m_fcb_offset; +define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; + +define symbol m_xmcd_offset = 0x800; +define symbol m_xmcd_size = 0x400; +define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; +define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; + +define symbol m_container_offset = 0x1000; +define symbol m_container_size = 0x2000; +define symbol m_container_start = m_flash_start + m_container_offset; +define symbol m_container_end = m_container_start + m_container_size - 1; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x08000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_hyperram_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; +define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; +define region CONTAINER_region = mem:[from m_container_start to m_container_end]; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); +define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); +define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +/* cache line size = 16 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 16, end alignment = 16 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 16, end alignment = 16 { section CacheLineData.init }; + +define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; + +place in FCB_region { section .boot_hdr.conf }; +place in XMCD_region { section .boot_hdr.xmcd_data }; +place in CONTAINER_region { section .boot_hdr.container }; +place in TEXT_region { first block RO }; +place in QACODE_region { section .textrw, block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld new file mode 100644 index 000000000000..7dd7070dd5a4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld @@ -0,0 +1,383 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__use_shmem__ = 1; +__multicore__ = 1; + +/* Board memory map */ +m_code_tcm_start = 0x0FFE0000; +m_code_tcm_size = 0x00020000; +m_system_tcm_start = 0x20000000; +m_system_tcm_size = 0x00020000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000; +m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; +m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; +m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; +m_flash_start = 0x28000000; +m_flash_size = 0x08000000; + +m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +m_fcb_offset = 0x400; +m_fcb_size = 0x200; +m_xmcd_offset = 0x800; +m_xmcd_size = 0x400; +m_container_offset = 0x1000; +m_container_size = 0x2000; + +m_fcb_start = m_flash_start + m_fcb_offset; +m_fcb_end = m_fcb_start + m_fcb_size - 1; +m_xmcd_start = m_flash_start + m_xmcd_offset; +m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; +m_container_start = m_flash_start + m_container_offset; +m_container_end = m_container_start + m_container_size - 1; + +app_image_offset = 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +m_qadata_start = m_system_tcm_start; +m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +m_ram_vector_table_start = m_code_tcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = m_hyperram_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : 0; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_hyperram_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; +__CONTAINER_IMG_OFFSET = m_interrupts_start - m_container_start; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_fcb_data (RX) : ORIGIN = m_fcb_start, LENGTH = m_fcb_end - m_fcb_start + 1 + m_xmcd_data (RX) : ORIGIN = m_xmcd_start, LENGTH = m_xmcd_end - m_xmcd_start + 1 + m_container_data (RX) : ORIGIN = m_container_start, LENGTH = m_container_end - m_container_start + 1 + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + .fcb : + { + KEEP(*(.boot_hdr.conf)) + } > m_fcb_data + + .xmcd : + { + KEEP(*(.boot_hdr.xmcd_data)) + } > m_xmcd_data + + .container : + { + KEEP(*(.boot_hdr.container)) + } > m_container_data + + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(16); + core1_image_start = .; + KEEP (*(.core1_code)) + *(.core1_code*) + core1_image_end = .; + . = ALIGN(4) ; + } > m_text + + ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit") + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(CacheLineData.init) + . = ALIGN(16); /* cache line size = 16 bytes */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + *(DataQuickAccess) /* quick access data section */ + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + __CONTAINER_IMG_SIZE = text_data_end - m_interrupts_start; + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(CacheLineData) + . = ALIGN(16); /* cache line size = 16 bytes */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.scf new file mode 100644 index 000000000000..40618d83c7d4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.scf @@ -0,0 +1,248 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_code_tcm_start 0x0FFE0000 +#define m_code_tcm_size 0x00020000 + +#define m_system_tcm_start 0x20000000 +#define m_system_tcm_size 0x00020000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#if defined(__dual_image__) +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +#define m_sdram_start 0x81E00000 +#define m_sdram_size 0x00200000 +#define m_hyperram_start 0x04600000 +#define m_hyperram_size 0x00200000 +#else +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x02000000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00800000 +#endif + +#define m_flash_start 0x28000000 +#define m_flash_size 0x00800000 +#define m_core1_image_maximum_size 0x00040000 + +/* General definition */ +#define app_image_offset 0x0000B000 + +#define m_fcb_offset 0x400 +#define m_fcb_size 0x200 +#define m_xmcd_offset 0x800 +#define m_xmcd_size 0x400 +#define m_container_offset 0x1000 +#define m_container_size 0x2000 + +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_code_tcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x08000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size +#define m_qadata_start m_system_tcm_start +#define m_qacode_size m_code_tcm_size - (m_qacode_start - m_code_tcm_start) +#define m_qadata_size m_system_tcm_size + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size m_hyperram_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0 +#endif +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_fcb_start m_flash_start + m_fcb_offset +#define m_xmcd_start m_flash_start + m_xmcd_offset +#define m_container_start m_flash_start + m_container_offset +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_hyperram_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size +#define m_heap_start m_ocram1_start + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +; load region +LR_m_header m_fcb_start (m_container_start) + (m_container_size) - (m_fcb_start) +{ + ; Flash Configuration Block + FCB m_fcb_start FIXED m_fcb_size + { + .ANY (.boot_hdr.conf) + } + + ; XMCD Block + XMCD m_xmcd_start FIXED m_xmcd_size + { + .ANY (.boot_hdr.xmcd_data) + } + + ; Container + Container m_container_start FIXED m_container_size + { + .ANY (.boot_hdr.container) + } + + ; Empty region added for container configuration + ER_m_container_image_offset (m_text_start) - (m_container_start) EMPTY 0 + { + } +} +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size + { + .ANY (.core1_code) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) + } + + ER_m_QuickAccessData m_qadata_start m_qadata_size + { + .ANY (DataQuickAccess) + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + } + + ; cache line size is 16 bytes + RW_m_CacheLineData +0 ALIGN 16 (m_data_size-stack_size-ImageLength(RW_m_data))/16*16 + { + * (CacheLineData) + * (CacheLineData.init) + } + + ; auxiliary to make sure RW_m_CacheLineData end-aligned CACHE LINE SIZE + ; DO NOT insert any region between RW_m_CacheLineData and RW_m_CacheLineData_Aux + RW_m_CacheLineData_Aux +0 ALIGN 16 EMPTY 0 + { + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.icf new file mode 100644 index 000000000000..30f6a9eae969 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.icf @@ -0,0 +1,158 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol app_image_offset = isdefinedsymbol(__dual_image__) ? 0x0010B000 : 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x08000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_code_tcm_size; +define symbol m_data_size = m_system_tcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_code_tcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_system_tcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block CORE1_IMAGE_BLOCK }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.ld new file mode 100644 index 000000000000..a002c692580b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.ld @@ -0,0 +1,341 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_code_tcm_start = 0x0FFE0000; +m_code_tcm_size = 0x00020000; +m_system_tcm_start = 0x20000000; +m_system_tcm_size = 0x00020000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000; +m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; +m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; +m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +m_qadata_start = m_system_tcm_start; +m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +m_ram_vector_table_start = m_code_tcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x400; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x400; + +/* Target specific definition, code & data allocation */ +m_code_size = m_code_tcm_size - vector_table_size; +m_data_size = m_system_tcm_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : 0; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? 0 : 0; + +m_interrupts_start = m_code_tcm_start; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_system_tcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(CodeQuickAccess) + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(16); + core1_image_start = .; + KEEP (*(.core1_code)) + *(.core1_code*) + core1_image_end = .; + . = ALIGN(4) ; + } > m_text + + ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit") + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.scf new file mode 100644 index 000000000000..48e0d1207606 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram.scf @@ -0,0 +1,197 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_code_tcm_start 0x0FFE0000 +#define m_code_tcm_size 0x00020000 + +#define m_system_tcm_start 0x20000000 +#define m_system_tcm_size 0x00020000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#if defined(__dual_image__) +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +#define m_sdram_start 0x81E00000 +#define m_sdram_size 0x00200000 +#define m_hyperram_start 0x04600000 +#define m_hyperram_size 0x00200000 +#else +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x02000000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00800000 +#endif + +#define m_flash_start 0x28000000 +#define m_flash_size 0x01000000 +#define m_core1_image_maximum_size 0x00040000 + +/* General definition */ +#if defined(__dual_image__) +#define app_image_offset 0x0010B000 +#else +#define app_image_offset 0x0000B000 +#endif + +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_code_tcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x08000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size 0 +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size +#define m_qadata_start m_system_tcm_start +#define m_qacode_size 0 +#define m_qadata_size 0 + +#define m_text_size m_code_tcm_size +#define m_data_size m_system_tcm_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0 +#endif +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_text_start m_code_tcm_start +#define m_interrupts_start m_text_start +#define m_data_start m_system_tcm_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size +#define m_heap_start m_ocram1_start + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + .ANY (CodeQuickAccess) + } + + CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size + { + .ANY (.core1_code) + } + + ER_m_QuickAccessCode m_qacode_start EMPTY m_qacode_size + { + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript deleted file mode 100644 index 23137a7f7487..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript +++ /dev/null @@ -1,1041 +0,0 @@ -__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; -__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); -__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; -__constant U32 _ACCESS_AP = 1; -__constant U32 _CM33_CPUID = 0xD210; -__constant U32 _CM7_CPUID = 0x0C27; - -/* ROM trap address for CM33 core, after system reset */ -__constant U32 _ROM_TRAP0_ADDR = 0x10002932; -__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; -__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; - -__constant U32 _SRC_SRSR_ADDR = 0x44460050; -__constant U32 _SRC_SRMASK_ADDR = 0x44460018; -__constant U32 _SRC_SCR_ADDR = 0x44460010; -__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; -__constant U32 _SRC_SBMR2_ADDR = 0x44460044; -__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; - -__constant U32 _DWT_COMP0_ADDR = 0xE0001020; -__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; - -__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; -__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; - -__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; - -__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; -__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; - -__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; - -__constant U32 _SI_VER_ADDR = 0x5751804C; - -unsigned int cpuID; -unsigned int rom_trap_addr; - -static int _WriteViaCM33AP16(U32 Addr, U16 Data) { - int r; - - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); - Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); - r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); - r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); - return r; -} - -static U32 _ReadViaCM33AP16(U32 Addr) { - U32 r; - - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); - JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); - JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); - return r; -} - -static int _WriteViaCM33AP32(U32 Addr, U32 Data) { - int r; - - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); - r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); - r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); - return r; -} - -static U32 _ReadViaCM33AP32(U32 Addr) { - int r; - - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); - r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); - r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); - return r; -} - -/* For Debug Start */ -__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; -__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; -__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; - -__constant U32 _REG_R0 = 0x0; -__constant U32 _REG_R1 = 0x1; -__constant U32 _REG_R2 = 0x2; -__constant U32 _REG_R3 = 0x3; -__constant U32 _REG_R4 = 0x4; -__constant U32 _REG_R5 = 0x5; -__constant U32 _REG_R6 = 0x6; -__constant U32 _REG_R7 = 0x7; -__constant U32 _REG_R8 = 0x8; -__constant U32 _REG_R9 = 0x9; -__constant U32 _REG_R10 = 0xA; -__constant U32 _REG_R11 = 0xB; -__constant U32 _REG_R12 = 0xC; -__constant U32 _REG_SP = 0xD; -__constant U32 _REG_LR = 0xE; -__constant U32 _REG_PC = 0xF; -__constant U32 _REG_SP_main = 0x11; -__constant U32 _REG_SP_process = 0x12; -__constant U32 _REG_MSPLIM_S = 0x1C; -__constant U32 _REG_PSPLIM_S = 0x1D; -__constant U32 _REG_MSPLIM_NS = 0x1E; -__constant U32 _REG_PSPLIM_NS = 0x1F; - -static U32 _ReadCPUReg(int RegIndex) { - U32 v; - - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); - v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); - return v; -} - -static U32 _ReadCPURegViaAP(int AP, int RegIndex) { - int r; - - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); - JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); - - r = _ReadCPUReg(RegIndex); - return r; -} - -int debug = 0; - -void ShowDAPInfo(void) -{ - int r; - - if ( debug ) - { - JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); - r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); - JLINK_SYS_Report1("CM33 AP CSW = ", r); - } -} - -void DBG_ShowCM33Reg(void) -{ - int r, sp, pc; - - r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); - JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); - r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); - JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); - r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); - JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); - - r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); - JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); - r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); - JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); - - r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); - JLINK_SYS_Report1(" CM33 DFSR = ", r); - r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); - JLINK_SYS_Report1(" CM33 DEMCR = ", r); - r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); - JLINK_SYS_Report1(" CM33 DHCSR = ", r); - if ( (r & 0x02) != 0) - { - sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); - pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); - JLINK_SYS_Report1(" CM33 PC = ", pc); - JLINK_SYS_Report1(" CM33 SP = ", sp); - } - else - { - JLINK_SYS_Report(" CM33 core is not halted!"); - } -} - -void DBG_ShowCoreReg(void) -{ - int r, sp, pc; - - r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); - JLINK_SYS_Report1(" DFSR = ", r); - r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); - JLINK_SYS_Report1(" DHCSR = ", r); - if ( (r & 0x02) != 0) - { - sp = _ReadCPUReg(_REG_SP); - pc = _ReadCPUReg(_REG_PC); - JLINK_SYS_Report1(" PC = ", pc); - JLINK_SYS_Report1(" SP = ", sp); - } - else - { - JLINK_SYS_Report(" Core is not halted!"); - } -} - -void DBG_ShowReg(int seq) -{ - int r; - if( debug ) - { - JLINK_SYS_Report1("Seq: ", seq); - - r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); - JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); - r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); - JLINK_SYS_Report1(" SRSR = ", r); - r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); - JLINK_SYS_Report1(" SRMASK = ", r); - r = _ReadViaCM33AP32(_SRC_SCR_ADDR); - JLINK_SYS_Report1(" SCR = ", r); - r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); - JLINK_SYS_Report1(" M7_CFG = ", r); - - if(cpuID == _CM7_CPUID) - { - if((r & 0x10) == 0) - { - DBG_ShowCoreReg(); - } - - } - - DBG_ShowCM33Reg(); - } -} -/* For Debug End */ - -void _FLEXSPI1_ModuleReset() -{ - unsigned int reg; - - reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = MEM_ReadU32(0x425E0000); - MEM_WriteU32(0x425E0000, (reg | 0x1)); - do - { - reg = MEM_ReadU32(0x425E0000); - } while ((reg & 0x1) != 0); - } -} - -void _FLEXSPI1_WaitBusIdle() -{ - unsigned int reg; - reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = MEM_ReadU32(0x425E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -void _FLEXSPI1_ClockInit() -{ - _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 - MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 -} - -void _FLEXSPI1_SetPinForQuadMode(void) { - // Set 4 Pin Mode for JLink - // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS - MEM_WriteU32(0x42A1023C, 0x17); - MEM_WriteU32(0x42A10544, 0x1); - // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK - MEM_WriteU32(0x42A10240, 0x17); - // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B - MEM_WriteU32(0x42A10244, 0x17); - // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 - MEM_WriteU32(0x42A10248, 0x17); - // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 - MEM_WriteU32(0x42A1024C, 0x17); - // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 - MEM_WriteU32(0x42A10250, 0x17); - // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 - MEM_WriteU32(0x42A10254, 0x17); -} - -void _FLEXSPI1_ModuleInit(void) { - - unsigned int reg; - reg = MEM_ReadU32(0x425E0000); - MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); - - //FLEXSPI1->MCR0 = 0xFFFF8010; - MEM_WriteU32(0x425E0000, 0xFFFF8010); - //FLEXSPI1->MCR2 = 0x200001F7; - MEM_WriteU32(0x425E0008, 0x200001F7); - //FLEXSPI1->AHBCR = 0x78; - MEM_WriteU32(0x425E000C, 0x78); - - //FLEXSPI1->FLSHCR0[0] = 0x00004000; - MEM_WriteU32(0x425E0060, 0x00004000); - - - //FLEXSPI1->FLSHCR4 = 0xC3; - MEM_WriteU32(0x425E0094, 0xC3); - //FLEXSPI1->IPRXFCR = 0x1C; - MEM_WriteU32(0x425E00B8, 0x1C); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - MEM_WriteU32(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x02; - MEM_WriteU32(0x425E001C, 0x02); - - //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad - MEM_WriteU32(0x425E0200, 0x0A1804EB); - //FLEXSPI1->LUT[1] = 0x26043206; - MEM_WriteU32(0x425E0204, 0x26043206); - //FLEXSPI1->LUT[2] = 0x00000000; - MEM_WriteU32(0x425E0208, 0x00000000); - //FLEXSPI1->LUT[3] = 0x00000000; - MEM_WriteU32(0x425E020C, 0x00000000); - - //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable - MEM_WriteU32(0x425E0210, 0x00000406); - //FLEXSPI1->LUT[5] = 0x00000000; - MEM_WriteU32(0x425E0214, 0x00000000); - //FLEXSPI1->LUT[6] = 0x00000000; - MEM_WriteU32(0x425E0218, 0x00000000); - //FLEXSPI1->LUT[7] = 0x00000000; - MEM_WriteU32(0x425E021C, 0x00000000); - - //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 - MEM_WriteU32(0x425E0220, 0x20040401); - //FLEXSPI1->LUT[9] = 0x00000000; - MEM_WriteU32(0x425E0224, 0x00000000); - //FLEXSPI1->LUT[10] = 0x00000000; - MEM_WriteU32(0x425E0228, 0x00000000); - //FLEXSPI1->LUT[11] = 0x00000000; - MEM_WriteU32(0x425E022C, 0x00000000); - - //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 - MEM_WriteU32(0x425E0230, 0x24040405); - //FLEXSPI1->LUT[13] = 0x00000000; - MEM_WriteU32(0x425E0234, 0x00000000); - //FLEXSPI1->LUT[14] = 0x00000000; - MEM_WriteU32(0x425E0238, 0x00000000); - //FLEXSPI1->LUT[15] = 0x00000000; - MEM_WriteU32(0x425E023C, 0x00000000); - - //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable - MEM_WriteU32(0x425E0240, 0x00000404); - //FLEXSPI1->LUT[17] = 0x00000000; - MEM_WriteU32(0x425E0244, 0x00000000); - //FLEXSPI1->LUT[18] = 0x00000000; - MEM_WriteU32(0x425E0248, 0x00000000); - //FLEXSPI1->LUT[19] = 0x00000000; - MEM_WriteU32(0x425E024C, 0x00000000); - - //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 - MEM_WriteU32(0x425E0250, 0x20040431); - //FLEXSPI1->LUT[21] = 0x00000000; - MEM_WriteU32(0x425E0254, 0x00000000); - //FLEXSPI1->LUT[22] = 0x00000000; - MEM_WriteU32(0x425E0258, 0x00000000); - //FLEXSPI1->LUT[23] = 0x00000000; - MEM_WriteU32(0x425E025C, 0x00000000); - - //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 - MEM_WriteU32(0x425E0260, 0x24040435); - //FLEXSPI1->LUT[25] = 0x00000000; - MEM_WriteU32(0x425E0264, 0x00000000); - //FLEXSPI1->LUT[26] = 0x00000000; - MEM_WriteU32(0x425E0268, 0x00000000); - //FLEXSPI1->LUT[27] = 0x00000000; - MEM_WriteU32(0x425E026C, 0x00000000); - - //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile - MEM_WriteU32(0x425E0270, 0x00000450); - //FLEXSPI1->LUT[29] = 0x00000000; - MEM_WriteU32(0x425E0274, 0x00000000); - //FLEXSPI1->LUT[30] = 0x00000000; - MEM_WriteU32(0x425E0278, 0x00000000); - //FLEXSPI1->LUT[31] = 0x00000000; - MEM_WriteU32(0x425E027C, 0x00000000); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - MEM_WriteU32(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x01; - MEM_WriteU32(0x425E001C, 0x01); -} - -void _FLEXSPI2_ModuleReset() -{ - unsigned int reg; - - reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = MEM_ReadU32(0x445E0000); - MEM_WriteU32(0x445E0000, (reg | 0x1)); - do - { - reg = MEM_ReadU32(0x445E0000); - } while ((reg & 0x1) != 0); - } -} - -void _FLEXSPI2_WaitBusIdle() -{ - unsigned int reg; - - reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = MEM_ReadU32(0x445E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -void _FlexSPI2_SetPinForOctalMode() -{ - // Config IOMUX for FlexSPI2 - MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 - MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 - MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 - MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 - MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 - MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 - MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 - MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 - MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B - MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS - MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK - - //The input daisy!! - MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 - MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 - MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 - MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 - MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 - MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 - MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 - MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 - MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS - MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK - - // PAD ctrl - MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 - MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 - MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 - MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 - MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 - MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 - MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 - MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 - MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B - MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS - MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK -} - -void _FLEXSPI2_ClockInit() -{ - _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 - MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 -} - -void _FLEXSPI2_ModuleInit() -{ - // Config FlexSPI2 Registers - - unsigned int reg; - reg = MEM_ReadU32(0x445E0000); - MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); - - _FLEXSPI2_ModuleReset(); - - MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 - MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 - MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 - MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable - MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 - MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 - MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 - MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 - MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 - MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 - MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 - MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 - MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR - MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR - - MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 - MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 - MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 - MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 - - _FLEXSPI2_WaitBusIdle(); - - MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 - MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 - MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 - - _FLEXSPI2_WaitBusIdle(); - - MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA - MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 - - do - { - reg = MEM_ReadU32(0x445E00E8); - } while (0x3 != (reg & 0x3)); - JLINK_SYS_Sleep(1); - // __delay(100);//100us - - MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 - MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 - MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 - MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 - - _FLEXSPI2_WaitBusIdle(); - - MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY - MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR - MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] - MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] - MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] - MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] - MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] - MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] - MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] - MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] - MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] - MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] - MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] - MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] - MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] - MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] - MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] - MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] - MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] - MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] - MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] - MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] - MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY - MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR - - /* Restore hyperram CR0 register */ - MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 - MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 - MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR - MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 - MEM_WriteU32(0x445E0014, 0x00000040); // INTR - MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = MEM_ReadU32(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - MEM_WriteU32(0x445E0014, 0x00000001); // INTR - - /* Restore hyperram CR1 register */ - MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 - MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 - MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR - MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 - MEM_WriteU32(0x445E0014, 0x00000040); // INTR - MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = MEM_ReadU32(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - MEM_WriteU32(0x445E0014, 0x00000001); // INTR - - _FLEXSPI2_ModuleReset(); -} - -void CM7_InitTCM(U32 targetAddr, U32 size) { - U32 reg; - - reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR - - if((reg & 0x80000000) != 0) - { - // DMA channel is active, wait it get finished - do - { - reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR - } while((reg & 0x40000000) == 0); - } - - _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag - - _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA - _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA - - _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR - - _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR - _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR - _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO - _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO - _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO - _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR - _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF - _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF - _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR - _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR - _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR - - do - { - reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR - } while((reg & 0x40000000) == 0); - _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag -} - -void CM7_KickOff(int ecc_init) -{ - U32 reg, resp1, resp2; - - reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); - if((reg & 0x10) == 0) - { - JLINK_SYS_Report("CM7 is running already"); - } - else - { - JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); - - // Clock Preparation - JLINK_SYS_Report("******** Prepare Clock *********"); - _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 - _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 - - // Release CM7 - _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); - - if (ecc_init) - { - // DMA initialization - JLINK_SYS_Report("******** DMA operation *********"); - CM7_InitTCM(0x303C0000, 0x40000); - CM7_InitTCM(0x30400000, 0x40000); - } - - // Making Landing Zone - JLINK_SYS_Report("******** Creating Landing Zone *********"); - _WriteViaCM33AP32(0x303C0000, 0x20020000); - _WriteViaCM33AP32(0x303C0004, 0x00000009); - _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); - - // VTOR 0x00 - _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); - - // Trigger ELE - JLINK_SYS_Report("******** ELE Trigger *********"); - _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] - resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] - resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] - JLINK_SYS_Report1("ELE RESP1 : ", resp1); - JLINK_SYS_Report1("ELE RESP2 : ", resp2); - - // Deassert CM7 Wait - JLINK_SYS_Report("******** Kickoff CM7 *********"); - _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); - } -} - -void DAP_Init(void) -{ - JLINK_CORESIGHT_Configure(""); - - CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); - CORESIGHT_AddAP(1, CORESIGHT_APB_AP); - CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); - CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); - CORESIGHT_AddAP(4, CORESIGHT_APB_AP); - CORESIGHT_AddAP(5, CORESIGHT_APB_AP); - CORESIGHT_AddAP(6, CORESIGHT_APB_AP); - - JLINK_SYS_Report("***************************************************"); - if(cpuID == _CM7_CPUID) - { - CPU = CORTEX_M7; - CORESIGHT_IndexAHBAPToUse = 2; - JLINK_SYS_Report("Current core is CM7"); - } - else if(cpuID == _CM33_CPUID) - { - CPU = CORTEX_M33; - CORESIGHT_IndexAHBAPToUse = 3; - JLINK_SYS_Report("Current core is CM33"); - - ShowDAPInfo(); - CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); - } - else - { - JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); - } - JLINK_SYS_Report("***************************************************"); -} - -void CM33_Halt(void) -{ - U32 reg; - - reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; - - if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse - { - JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); - - reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); - - if(0 == (reg & 0x02)) - { - JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); - - _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control - _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 - reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); - if(0 != (reg & 0x02)) - { - JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); - } - else - { - JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); - } - } - else - { - JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); - } - } - else - { - JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); - } -} - -void Flash_Init() { - JLINK_SYS_Report("***************************************************"); - JLINK_SYS_Report("Init Flash"); - - _FLEXSPI1_WaitBusIdle(); - _FLEXSPI1_ModuleReset(); - - _FLEXSPI1_SetPinForQuadMode(); - _FLEXSPI1_ClockInit(); - _FLEXSPI1_ModuleInit(); - - JLINK_SYS_Report("***************************************************"); -} - -void HyperRAM_Init() -{ - JLINK_SYS_Report("***************************************************"); - JLINK_SYS_Report("Init HyperRAM"); - - _FLEXSPI2_WaitBusIdle(); - _FLEXSPI2_ModuleReset(); - - _FlexSPI2_SetPinForOctalMode(); - _FLEXSPI2_ClockInit(); - _FLEXSPI2_ModuleInit(); - - JLINK_SYS_Report("***************************************************"); -} - -void CM33_ClearNVIC(void) { - JLINK_SYS_Report("***************************************************"); - JLINK_SYS_Report("Clear NVIC"); - JLINK_SYS_Report("***************************************************"); - JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); - JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); -} - -int InitTarget(void) -{ - int r; - cpuID = _CM33_CPUID; - - DAP_Init(); - - if(cpuID == _CM7_CPUID) - { - CM33_Halt(); - CM7_KickOff(1); - - /* Avoid to access TPIU to prevent soc hang */ - JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal - } - - r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; - - if ( r == 1 ) - { - rom_trap_addr = _ROM_TRAP1_ADDR; - } - else if ( r == 2 ) - { - rom_trap_addr = _ROM_TRAP2_ADDR; - } - else - { - rom_trap_addr = _ROM_TRAP0_ADDR; - } - JLINK_SYS_Report1("SI_VER = ", r); - JLINK_SYS_Report1("TRAP = ", rom_trap_addr); - - return 0; -} - -int SetupTarget(void) -{ - return 0; -} - -void ResetTarget_CM33(void) -{ - int r, w; - int comp, func; - int core_reset_request_bit_mask; - - core_reset_request_bit_mask = 0x100; /* for CM33 core */ - - DBG_ShowReg(0); - - /* Halt the CPU and wait sometime for possible peripheral operation finish */ - JLINK_TARGET_Halt(); - JLINK_SYS_Sleep(10); - - r = JLINK_TARGET_IsHalted(); - if (r != 1) - { - JLINK_SYS_Report("ERR: CM33 core can't be halted!"); - } - - DBG_ShowReg(1); - - /* check and enable core request system reset */ - r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); - if ( (r & core_reset_request_bit_mask) != 0 ) - { - if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) - { - w = r & (~core_reset_request_bit_mask); - r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); - if ( (r & 0x80) == 0 ) - { - JLINK_SYS_Report("Enable system reset via CM33 core reset"); - JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); - ShowDAPInfo(); - } - else - { - JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); - } - } - else - { - JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); - } - } - - DBG_ShowReg(2); - - JLINK_SYS_Report("Set CM33 watch point"); - comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ - func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); - JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); - JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); - - /* Clear the reset status to avoid ROM clean the core TCM after reset */ - r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); - JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); - - DBG_ShowReg(3); - - JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); - JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); - JLINK_SYS_Sleep(100); - - r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); - if ((r & 0x01000000) == 0) - { - JLINK_SYS_Report("ERR: CM33 core is not trapped!"); - } - - DBG_ShowReg(4); - - r = JLINK_TARGET_IsHalted(); - if (r == 1) - { - JLINK_SYS_Report("restore CM33 watch point"); - JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); - JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); - } - else - { - JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); - } -} - -void ResetTarget_CM7(void) -{ - int r, w; - int comp, func; - int core_reset_request_bit_mask; - int mem_0, mem_1, mem_2; - - core_reset_request_bit_mask = 0x400; /* for CM7 core */ - - DBG_ShowReg(0); - - /* Halt the CPU and wait sometime for possible peripheral operation finish */ - JLINK_TARGET_Halt(); - JLINK_SYS_Sleep(10); - - r = JLINK_TARGET_IsHalted(); - if (r != 1) - { - JLINK_SYS_Report("ERR: CM7 core can't be halted!"); - } - - DBG_ShowReg(1); - - /* check and enable core request system reset */ - r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); - if ( (r & core_reset_request_bit_mask) != 0 ) - { - if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) - { - w = r & (~core_reset_request_bit_mask); - r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); - if ( (r & 0x80) == 0 ) - { - JLINK_SYS_Report("Enable system reset via CM7 core reset"); - JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); - } - else - { - JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); - } - } - else - { - JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); - } - } - - DBG_ShowReg(2); - - /* Clear the reset status to avoid ROM clean the core TCM after reset */ - r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); - JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); - - DBG_ShowReg(3); - - /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ - mem_0 = JLINK_MEM_ReadU32(0); - mem_1 = JLINK_MEM_ReadU32(4); - mem_2 = JLINK_MEM_ReadU32(8); - - JLINK_SYS_Report("Set CM33 watch point"); - _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core - comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ - func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); - _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core - _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); - _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); - - DBG_ShowReg(4); - - JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); - JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); - JLINK_SYS_Sleep(100); - - r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); - if ((r & 0x01000000) == 0) - { - JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); - } - - DBG_ShowReg(5); - - CM7_KickOff(0); - - // Halt CM7 core - JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); - - DBG_ShowReg(6); - - r = JLINK_TARGET_IsHalted(); - if (r == 1) - { - JLINK_SYS_Report("restore CM7 ITCM"); - - JLINK_MEM_WriteU32(0, mem_0); - JLINK_MEM_WriteU32(4, mem_1); - JLINK_MEM_WriteU32(8, mem_2); - - JLINK_SYS_Report("restore CM33 watch points"); - _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); - _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); - } - else - { - JLINK_SYS_Report("ERR: CM7 core can not be halted!"); - } -} - -void ResetTarget(void) { - if(cpuID == _CM7_CPUID) - { - ResetTarget_CM7(); - } - else if(cpuID == _CM33_CPUID) - { - ResetTarget_CM33(); - } -} - -int AfterResetTarget(void) -{ - U32 reg; - - if(cpuID == _CM33_CPUID) - { - // CM33 NVIC may be enabled by ROM after reset - CM33_ClearNVIC(); - } - - Flash_Init(); - HyperRAM_Init(); - - return 0; -} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini deleted file mode 100644 index 993fb2be1eac..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini +++ /dev/null @@ -1,417 +0,0 @@ -/* - * Copyright 2023-2024 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -FUNC void _FLEXSPI1_ModuleReset(void) -{ - unsigned int reg; - - reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = _RDWORD(0x425E0000); - _WDWORD(0x425E0000, (reg | 0x1)); - do - { - reg = _RDWORD(0x425E0000); - } while ((reg & 0x1) != 0); - } -} - -FUNC void _FLEXSPI1_WaitBusIdle(void) -{ - unsigned int reg; - reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = _RDWORD(0x425E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -FUNC void _FLEXSPI1_ClockInit(void) -{ - _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 - _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 -} - -FUNC void _FLEXSPI1_SetPinForQuadMode(void) { - // Set 4 Pin Mode - // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS - _WDWORD(0x42A1023C, 0x17); - _WDWORD(0x42A10544, 0x1); - // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK - _WDWORD(0x42A10240, 0x17); - // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B - _WDWORD(0x42A10244, 0x17); - // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 - _WDWORD(0x42A10248, 0x17); - // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 - _WDWORD(0x42A1024C, 0x17); - // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 - _WDWORD(0x42A10250, 0x17); - // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 - _WDWORD(0x42A10254, 0x17); -} - -FUNC void _FLEXSPI1_ModuleInit(void) { - - unsigned int reg; - reg = _RDWORD(0x425E0000); - _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); - - //FLEXSPI1->MCR0 = 0xFFFF8010; - _WDWORD(0x425E0000, 0xFFFF8010); - //FLEXSPI1->MCR2 = 0x200001F7; - _WDWORD(0x425E0008, 0x200001F7); - //FLEXSPI1->AHBCR = 0x78; - _WDWORD(0x425E000C, 0x78); - - //FLEXSPI1->FLSHCR0[0] = 0x00004000; - _WDWORD(0x425E0060, 0x00004000); - - //FLEXSPI1->FLSHCR4 = 0xC3; - _WDWORD(0x425E0094, 0xC3); - //FLEXSPI1->IPRXFCR = 0x1C; - _WDWORD(0x425E00B8, 0x1C); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - _WDWORD(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x02; - _WDWORD(0x425E001C, 0x02); - - //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad - _WDWORD(0x425E0200, 0x0A1804EB); - //FLEXSPI1->LUT[1] = 0x26043206; - _WDWORD(0x425E0204, 0x26043206); - //FLEXSPI1->LUT[2] = 0x00000000; - _WDWORD(0x425E0208, 0x00000000); - //FLEXSPI1->LUT[3] = 0x00000000; - _WDWORD(0x425E020C, 0x00000000); - - //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable - _WDWORD(0x425E0210, 0x00000406); - //FLEXSPI1->LUT[5] = 0x00000000; - _WDWORD(0x425E0214, 0x00000000); - //FLEXSPI1->LUT[6] = 0x00000000; - _WDWORD(0x425E0218, 0x00000000); - //FLEXSPI1->LUT[7] = 0x00000000; - _WDWORD(0x425E021C, 0x00000000); - - //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 - _WDWORD(0x425E0220, 0x20040401); - //FLEXSPI1->LUT[9] = 0x00000000; - _WDWORD(0x425E0224, 0x00000000); - //FLEXSPI1->LUT[10] = 0x00000000; - _WDWORD(0x425E0228, 0x00000000); - //FLEXSPI1->LUT[11] = 0x00000000; - _WDWORD(0x425E022C, 0x00000000); - - //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 - _WDWORD(0x425E0230, 0x24040405); - //FLEXSPI1->LUT[13] = 0x00000000; - _WDWORD(0x425E0234, 0x00000000); - //FLEXSPI1->LUT[14] = 0x00000000; - _WDWORD(0x425E0238, 0x00000000); - //FLEXSPI1->LUT[15] = 0x00000000; - _WDWORD(0x425E023C, 0x00000000); - - //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable - _WDWORD(0x425E0240, 0x00000404); - //FLEXSPI1->LUT[17] = 0x00000000; - _WDWORD(0x425E0244, 0x00000000); - //FLEXSPI1->LUT[18] = 0x00000000; - _WDWORD(0x425E0248, 0x00000000); - //FLEXSPI1->LUT[19] = 0x00000000; - _WDWORD(0x425E024C, 0x00000000); - - //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 - _WDWORD(0x425E0250, 0x20040431); - //FLEXSPI1->LUT[21] = 0x00000000; - _WDWORD(0x425E0254, 0x00000000); - //FLEXSPI1->LUT[22] = 0x00000000; - _WDWORD(0x425E0258, 0x00000000); - //FLEXSPI1->LUT[23] = 0x00000000; - _WDWORD(0x425E025C, 0x00000000); - - //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 - _WDWORD(0x425E0260, 0x24040435); - //FLEXSPI1->LUT[25] = 0x00000000; - _WDWORD(0x425E0264, 0x00000000); - //FLEXSPI1->LUT[26] = 0x00000000; - _WDWORD(0x425E0268, 0x00000000); - //FLEXSPI1->LUT[27] = 0x00000000; - _WDWORD(0x425E026C, 0x00000000); - - //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile - _WDWORD(0x425E0270, 0x00000450); - //FLEXSPI1->LUT[29] = 0x00000000; - _WDWORD(0x425E0274, 0x00000000); - //FLEXSPI1->LUT[30] = 0x00000000; - _WDWORD(0x425E0278, 0x00000000); - //FLEXSPI1->LUT[31] = 0x00000000; - _WDWORD(0x425E027C, 0x00000000); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - _WDWORD(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x01; - _WDWORD(0x425E001C, 0x01); -} - -FUNC void _FLEXSPI2_ModuleReset(void) -{ - unsigned int reg; - - reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = _RDWORD(0x445E0000); - _WDWORD(0x445E0000, (reg | 0x1)); - do - { - reg = _RDWORD(0x445E0000); - } while ((reg & 0x1) != 0); - } -} - -FUNC void _FLEXSPI2_WaitBusIdle(void) -{ - unsigned int reg; - - reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = _RDWORD(0x445E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -FUNC void _FlexSPI2_SetPinForOctalMode(void) -{ - // Config IOMUX for FlexSPI2 - _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B - _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS - _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK - - //The input daisy!! - _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS - _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK - - // PAD ctrl - _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B - _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS - _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK -} - -FUNC void _FLEXSPI2_ClockInit(void) -{ - _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 - _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 -} - -FUNC void _FLEXSPI2_ModuleInit(void) -{ - // Config FlexSPI2 Registers - - unsigned int reg; - reg = _RDWORD(0x445E0000); - _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); - - _FLEXSPI2_ModuleReset(); - - _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 - _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 - _WDWORD(0x445E0008, 0x200001F7); // MCR2 - _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable - _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 - _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 - _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 - _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 - _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 - _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 - _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 - _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 - _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR - _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR - - _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 - _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 - _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 - _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 - _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 - _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E00C0, 0x00000079); // DLLCRA - _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 - - do - { - reg = _RDWORD(0x445E00E8); - } while (0x3 != (reg & 0x3)); - _Sleep_(1); - // __delay(100);//100us - - _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 - _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 - _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 - _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY - _WDWORD(0x445E001C, 0x00000002); // LUTCR - _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] - _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] - _WDWORD(0x445E0208, 0x0000A704); // LUT[2] - _WDWORD(0x445E020C, 0x00000000); // LUT[3] - _WDWORD(0x445E0210, 0x8B188720); // LUT[4] - _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] - _WDWORD(0x445E0218, 0x0000A304); // LUT[6] - _WDWORD(0x445E021C, 0x00000000); // LUT[7] - _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] - _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] - _WDWORD(0x445E0228, 0x0000A704); // LUT[10] - _WDWORD(0x445E022C, 0x00000000); // LUT[11] - _WDWORD(0x445E0230, 0x8B188760); // LUT[12] - _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] - _WDWORD(0x445E0238, 0x00000000); // LUT[14] - _WDWORD(0x445E023C, 0x00000000); // LUT[15] - _WDWORD(0x445E0240, 0x00000000); // LUT[16] - _WDWORD(0x445E0244, 0x00000000); // LUT[17] - _WDWORD(0x445E0248, 0x00000000); // LUT[18] - _WDWORD(0x445E024C, 0x00000000); // LUT[19] - _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY - _WDWORD(0x445E001C, 0x00000001); // LUTCR - - /* Restore hyperram CR0 register */ - _WDWORD(0x445E00A0, 0x00001000); // IPCR0 - _WDWORD(0x445E00A4, 0x00030002); // IPCR1 - _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR - _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 - _WDWORD(0x445E0014, 0x00000040); // INTR - _WDWORD(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = _RDWORD(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - _WDWORD(0x445E0014, 0x00000001); // INTR - - /* Restore hyperram CR1 register */ - _WDWORD(0x445E00A0, 0x00001002); // IPCR0 - _WDWORD(0x445E00A4, 0x00030002); // IPCR1 - _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR - _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 - _WDWORD(0x445E0014, 0x00000040); // INTR - _WDWORD(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = _RDWORD(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - _WDWORD(0x445E0014, 0x00000001); // INTR - - _FLEXSPI2_ModuleReset(); -} - -FUNC void Flash_Init(void) -{ - printf("***************************************************\r\n"); - printf("Init Flash\r\n"); - - _FLEXSPI1_WaitBusIdle(); - _FLEXSPI1_ModuleReset(); - - _FLEXSPI1_SetPinForQuadMode(); - _FLEXSPI1_ClockInit(); - _FLEXSPI1_ModuleInit(); - - printf("***************************************************\r\n"); -} - -FUNC void HyperRAM_Init(void) -{ - printf("***************************************************\r\n"); - printf("Init HyperRAM\r\n"); - - _FLEXSPI2_WaitBusIdle(); - _FLEXSPI2_ModuleReset(); - - _FlexSPI2_SetPinForOctalMode(); - _FLEXSPI2_ClockInit(); - _FLEXSPI2_ModuleInit(); - - printf("***************************************************\r\n"); -} - -FUNC void ClearNVIC(void) { - printf("***************************************************\r\n"); - printf("Clear NVIC\r\n"); - printf("***************************************************\r\n"); - memset(0xE000E180, 0x40, 0xFF); - memset(0xE000E280, 0x40, 0xFF); -} - -FUNC void Setup_PC_SP(void) -{ - SP = _RDWORD(0x2800B000); // Setup Stack Pointer - PC = _RDWORD(0x2800B004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x2800B000); // Setup Vector Table Offset Register -} - -FUNC void Setup (void) { - ClearNVIC(); - Flash_Init(); - HyperRAM_Init(); - Setup_PC_SP(); -} - -FUNC void OnResetExec (void) -{ - // executes upon RESET - Setup(); -} - -// Disable the software breakpoint for nor flash memory region -SBC 0x28000000, 0x28FFFFFF, 0 - -Setup(); From 919fb342acb5a298486dfcce715047a09d80af42 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 17:26:12 +0800 Subject: [PATCH 03/31] Updated .ini files to support debugging in keil. And updeated .mac files to support deugging in iar. --- .../imxrt1180-nxp-evk/cm33/JLinkSettings.ini | 2 +- .../imxrt1180-nxp-evk/cm33/evkmimxrt1180.mac | 430 ++++++++++++++++++ .../cm33/evkmimxrt1180_flexspi_nor_cm33.ini | 417 +++++++++++++++++ .../cm33/evkmimxrt1180_hyperram_txt_cm33.ini | 419 +++++++++++++++++ .../cm33/evkmimxrt1180_ram_cm33.ini | 414 +++++++++++++++++ 5 files changed, 1681 insertions(+), 1 deletion(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180.mac create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_flexspi_nor_cm33.ini create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_hyperram_txt_cm33.ini create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_ram_cm33.ini diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini index fb02d5216cd9..f5db86072299 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini @@ -13,7 +13,7 @@ MaxNumAPs = 0 LowPowerHandlingMode = 0 OverrideMemMap = 0 AllowSimulation = 1 -ScriptFile="" +ScriptFile="evkmimxrt1180_cm33.jlinkscript" [FLASH] RMWThreshold = 0x400 Loaders="" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180.mac b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180.mac new file mode 100644 index 000000000000..8b21a75c9e9b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180.mac @@ -0,0 +1,430 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +_FLEXSPI1_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x425E0000, "Memory"); + do + { + reg = __readMemory32(0x425E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI1_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x425E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FLEXSPI1_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + __writeMemory32(0x103, 0x54450A80, "Memory"); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +_FLEXSPI1_SetPinForQuadMode() { + // Set 4 Pin Mode for JLink + __writeMemory32(0x17, 0x42A1023C, "Memory"); // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + __writeMemory32(0x1, 0x42A10544, "Memory"); + __writeMemory32(0x17, 0x42A10240, "Memory"); // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + __writeMemory32(0x17, 0x42A10244, "Memory"); // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + __writeMemory32(0x17, 0x42A10248, "Memory"); // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + __writeMemory32(0x17, 0x42A1024C, "Memory"); // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + __writeMemory32(0x17, 0x42A10250, "Memory"); // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + __writeMemory32(0x17, 0x42A10254, "Memory"); // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 +} + +_FLEXSPI1_ModuleInit() { + + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x425E0000, "Memory"); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + __writeMemory32(0xFFFF8010, 0x425E0000, "Memory"); + //FLEXSPI1->MCR2 = 0x200001F7; + __writeMemory32(0x200001F7, 0x425E0008, "Memory"); + //FLEXSPI1->AHBCR = 0x78; + __writeMemory32(0x78, 0x425E000C, "Memory"); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + __writeMemory32(0x00004000, 0x425E0060, "Memory"); + + //FLEXSPI1->FLSHCR4 = 0xC3; + __writeMemory32(0xC3, 0x425E0094, "Memory"); + //FLEXSPI1->IPRXFCR = 0x1C; + __writeMemory32(0x1C, 0x425E00B8, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x02; + __writeMemory32(0x02, 0x425E001C, "Memory"); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + __writeMemory32(0x0A1804EB, 0x425E0200, "Memory"); + //FLEXSPI1->LUT[1] = 0x26043206; + __writeMemory32(0x26043206, 0x425E0204, "Memory"); + //FLEXSPI1->LUT[2] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0208, "Memory"); + //FLEXSPI1->LUT[3] = 0x00000000; + __writeMemory32(0x00000000, 0x425E020C, "Memory"); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + __writeMemory32(0x00000406, 0x425E0210, "Memory"); + //FLEXSPI1->LUT[5] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0214, "Memory"); + //FLEXSPI1->LUT[6] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0218, "Memory"); + //FLEXSPI1->LUT[7] = 0x00000000; + __writeMemory32(0x00000000, 0x425E021C, "Memory"); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + __writeMemory32(0x20040401, 0x425E0220, "Memory"); + //FLEXSPI1->LUT[9] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0224, "Memory"); + //FLEXSPI1->LUT[10] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0228, "Memory"); + //FLEXSPI1->LUT[11] = 0x00000000; + __writeMemory32(0x00000000, 0x425E022C, "Memory"); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + __writeMemory32(0x24040405, 0x425E0230, "Memory"); + //FLEXSPI1->LUT[13] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0234, "Memory"); + //FLEXSPI1->LUT[14] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0238, "Memory"); + //FLEXSPI1->LUT[15] = 0x00000000; + __writeMemory32(0x00000000, 0x425E023C, "Memory"); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + __writeMemory32(0x00000404, 0x425E0240, "Memory"); + //FLEXSPI1->LUT[17] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0244, "Memory"); + //FLEXSPI1->LUT[18] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0248, "Memory"); + //FLEXSPI1->LUT[19] = 0x00000000; + __writeMemory32(0x00000000, 0x425E024C, "Memory"); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + __writeMemory32(0x20040431, 0x425E0250, "Memory"); + //FLEXSPI1->LUT[21] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0254, "Memory"); + //FLEXSPI1->LUT[22] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0258, "Memory"); + //FLEXSPI1->LUT[23] = 0x00000000; + __writeMemory32(0x00000000, 0x425E025C, "Memory"); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + __writeMemory32(0x24040435, 0x425E0260, "Memory"); + //FLEXSPI1->LUT[25] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0264, "Memory"); + //FLEXSPI1->LUT[26] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0268, "Memory"); + //FLEXSPI1->LUT[27] = 0x00000000; + __writeMemory32(0x00000000, 0x425E026C, "Memory"); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + __writeMemory32(0x00000450, 0x425E0270, "Memory"); + //FLEXSPI1->LUT[29] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0274, "Memory"); + //FLEXSPI1->LUT[30] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0278, "Memory"); + //FLEXSPI1->LUT[31] = 0x00000000; + __writeMemory32(0x00000000, 0x425E027C, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x01; + __writeMemory32(0x01, 0x425E001C, "Memory"); +} + +_FLEXSPI2_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x445E0000, "Memory"); + do + { + reg = __readMemory32(0x445E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI2_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x445E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for HyperRAM + __writeMemory32(0x00000013, 0x42A10088, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000013, 0x42A1008C, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000013, 0x42A10090, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000013, 0x42A10094, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000013, 0x42A1009C, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000013, 0x42A100A0, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000013, 0x42A100A4, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000013, 0x42A100A8, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000013, 0x42A100AC, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000013, 0x42A100B0, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000013, 0x42A100B4, "Memory");// FLEXSPI2_A_SCLK + + //The input daisy!! + __writeMemory32(0x00000001, 0x42A10594, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000001, 0x42A10590, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000001, 0x42A1058C, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000001, 0x42A10588, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000000, 0x42A10578, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000000, 0x42A1057C, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000000, 0x42A10580, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000000, 0x42A10584, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000000, 0x42A10570, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000000, 0x42A10598, "Memory");// FLEXSPI2_A_SCLK + + // PAD ctrl + __writeMemory32(0x00000008, 0x42A102D0, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000008, 0x42A102D4, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000008, 0x42A102D8, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000008, 0x42A102DC, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000008, 0x42A102E4, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000008, 0x42A102E8, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000008, 0x42A102EC, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000008, 0x42A102F0, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000008, 0x42A102F4, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000008, 0x42A102F8, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000008, 0x42A102FC, "Memory");// FLEXSPI2_A_SCLK +} + +_FLEXSPI2_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + __writeMemory32(0x101, 0x44450B00, "Memory"); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +_FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + __var reg; + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x445E0000, "Memory"); + + _FLEXSPI2_ModuleReset(); + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0xFFFFFFFF, 0x445E0004, "Memory"); // MCR1 + __writeMemory32(0x200001F7, 0x445E0008, "Memory"); // MCR2 + __writeMemory32(0x00000078, 0x445E000C, "Memory"); // AHBCR prefetch enable + __writeMemory32(0x800F0000, 0x445E0020, "Memory"); // AHBRXBUF0CR0 + __writeMemory32(0x800F0000, 0x445E0024, "Memory"); // AHBRXBUF1CR0 + __writeMemory32(0x800F0000, 0x445E0028, "Memory"); // AHBRXBUF2CR0 + __writeMemory32(0x800F0000, 0x445E002C, "Memory"); // AHBRXBUF3CR0 + __writeMemory32(0x800F0000, 0x445E0030, "Memory"); // AHBRXBUF4CR0 + __writeMemory32(0x800F0000, 0x445E0034, "Memory"); // AHBRXBUF5CR0 + __writeMemory32(0x80000020, 0x445E0038, "Memory"); // AHBRXBUF6CR0 + __writeMemory32(0x80000020, 0x445E003C, "Memory"); // AHBRXBUF7CR0 + __writeMemory32(0x00000000, 0x445E00B8, "Memory"); // IPRXFCR + __writeMemory32(0x00000000, 0x445E00BC, "Memory"); // IPTXFCR + + __writeMemory32(0x00000000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00000000, 0x445E0064, "Memory"); // FLASHA2CR0 + __writeMemory32(0x00000000, 0x445E0068, "Memory"); // FLASHB1CR0 + __writeMemory32(0x00000000, 0x445E006C, "Memory"); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00002000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00021C63, 0x445E0070, "Memory"); // FLASHA1CR1 + __writeMemory32(0x00000100, 0x445E0080, "Memory"); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00000079, 0x445E00C0, "Memory"); // DLLCRA + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + do + { + reg = __readMemory32(0x445E00E8, "Memory"); + } while (0x3 != (reg & 0x3)); + __delay(1000); // 1ms + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0x000000C2, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0x000000C6, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000002, 0x445E001C, "Memory"); // LUTCR + __writeMemory32(0x8B1887A0, 0x445E0200, "Memory"); // LUT[0] + __writeMemory32(0xB7078F10, 0x445E0204, "Memory"); // LUT[1] + __writeMemory32(0x0000A704, 0x445E0208, "Memory"); // LUT[2] + __writeMemory32(0x00000000, 0x445E020C, "Memory"); // LUT[3] + __writeMemory32(0x8B188720, 0x445E0210, "Memory"); // LUT[4] + __writeMemory32(0xB7078F10, 0x445E0214, "Memory"); // LUT[5] + __writeMemory32(0x0000A304, 0x445E0218, "Memory"); // LUT[6] + __writeMemory32(0x00000000, 0x445E021C, "Memory"); // LUT[7] + __writeMemory32(0x8B1887E0, 0x445E0220, "Memory"); // LUT[8] + __writeMemory32(0xB7078F10, 0x445E0224, "Memory"); // LUT[9] + __writeMemory32(0x0000A704, 0x445E0228, "Memory"); // LUT[10] + __writeMemory32(0x00000000, 0x445E022C, "Memory"); // LUT[11] + __writeMemory32(0x8B188760, 0x445E0230, "Memory"); // LUT[12] + __writeMemory32(0xA3028F10, 0x445E0234, "Memory"); // LUT[13] + __writeMemory32(0x00000000, 0x445E0238, "Memory"); // LUT[14] + __writeMemory32(0x00000000, 0x445E023C, "Memory"); // LUT[15] + __writeMemory32(0x00000000, 0x445E0240, "Memory"); // LUT[16] + __writeMemory32(0x00000000, 0x445E0244, "Memory"); // LUT[17] + __writeMemory32(0x00000000, 0x445E0248, "Memory"); // LUT[18] + __writeMemory32(0x00000000, 0x445E024C, "Memory"); // LUT[19] + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000001, 0x445E001C, "Memory"); // LUTCR + + /* Restore hyperram CR0 register */ + __writeMemory32(0x00001000, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0x2F8F2F8F, 0x445E0180, "Memory"); // TFDR 0x8F2F is default value of W756/7x of CR0 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + /* Restore hyperram CR1 register */ + __writeMemory32(0x00001002, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0xC1FFC1FF, 0x445E0180, "Memory"); // TFDR 0xFFC1 is default value of W756/7x of CR1 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + _FLEXSPI2_ModuleReset(); +} + +HyperRAM_Init() +{ + __message "Init HyperRAM"; + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + __message "HyperRAM init done\n"; +} + +Flash_Init() +{ + __message "Init Flash"; + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + __message "Flash init done\n"; +} + +execUserPreload() +{ + Flash_Init(); + HyperRAM_Init(); +} + +execUserReset() +{ + Flash_Init(); + HyperRAM_Init(); +} + +CleanInvalidateCache(cache) +{ + __var reg; + reg = __readMemory32(cache, "Memory"); + if((reg & 0x01) != 0) + { + __writeMemory32(0x0F000000 | reg, cache, "Memory"); + __writeMemory32(0x8F000000 | reg, cache, "Memory"); + + do + { + reg = __readMemory32(cache, "Memory"); + } while (( reg & 0x80000000) != 0); + } +} + +execUserExecutionStarted() +{ + /* + CMSIS-DAP probably use software breakpoint by default, + which fails debug for those code within cached memory, + e.g. hyperram_txt_debug/release. + With cache operation below, it helps debug for software + breakpoint, but still fails in assembly instruction + step debug, since execUserExecutionStarted is not invoked + in assembly instruction setp debug. + + The final solution for cached memory code debug, is to use + hardware breakpoint, which can be set in IAR project option: + Debug->CMSIS DAP->breakpoint. + */ + + __var reg; + reg = __readMemory32(0xE000ED00, "Memory"); // SCB->CPUID + if(__driverType("cmsisdap") && (reg == 0x411FD210)) + { + // CMSIS-DAP and CM33 core + CleanInvalidateCache(0x44400000); // XCACHE_PC_CCR + CleanInvalidateCache(0x44400800); // XCACHE_PS_CCR + } +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_flexspi_nor_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_flexspi_nor_cm33.ini new file mode 100644 index 000000000000..993fb2be1eac --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_flexspi_nor_cm33.ini @@ -0,0 +1,417 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x2800B000); // Setup Stack Pointer + PC = _RDWORD(0x2800B004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x2800B000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +// Disable the software breakpoint for nor flash memory region +SBC 0x28000000, 0x28FFFFFF, 0 + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_hyperram_txt_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_hyperram_txt_cm33.ini new file mode 100644 index 000000000000..a087c8c053dc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_hyperram_txt_cm33.ini @@ -0,0 +1,419 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x04000000); // Setup Stack Pointer + PC = _RDWORD(0x04000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x04000000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + // Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + + +HyperRAM_Init(); + +LOAD %L INCREMENTAL // Download + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_ram_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_ram_cm33.ini new file mode 100644 index 000000000000..141b0c9f4429 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_ram_cm33.ini @@ -0,0 +1,414 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x0FFE0000); // Setup Stack Pointer + PC = _RDWORD(0x0FFE0004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x0FFE0000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + // Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +Setup(); From 167d2d1565019874da827611e741ecd849176058 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 17:54:42 +0800 Subject: [PATCH 04/31] Updated template files, conifg files and script files of CM7 to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat. --- .../imx/imxrt/imxrt1180-nxp-evk/cm7/.config | 69 +- .../cm7/applications/SConscript | 22 +- .../imxrt1180-nxp-evk/cm7/applications/main.c | 7 + .../imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig | 685 ++- .../cm7/board/MCUX_Config/clock_config.c | 4 +- .../cm7/board/MCUX_Config/pin_mux.c | 582 +- .../cm7/board/MCUX_Config/pin_mux.h | 108 + .../imxrt1180-nxp-evk/cm7/board/SConscript | 53 +- .../imxrt/imxrt1180-nxp-evk/cm7/board/board.c | 592 +- .../imxrt/imxrt1180-nxp-evk/cm7/board/board.h | 164 +- .../imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h | 40 +- .../imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py | 103 +- .../imxrt/imxrt1180-nxp-evk/cm7/template.ewd | 5000 ++++++++++++++++- .../imxrt/imxrt1180-nxp-evk/cm7/template.ewp | 3324 ++++++++++- .../imxrt/imxrt1180-nxp-evk/cm7/template.ewt | 2153 ++++--- .../imxrt1180-nxp-evk/cm7/template.uvoptx | 499 +- .../imxrt1180-nxp-evk/cm7/template.uvprojx | 1135 +++- 17 files changed, 13025 insertions(+), 1515 deletions(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config index 628682e7815e..adda3dafdd39 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -126,7 +126,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=4096 -# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set # @@ -177,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_THREADSAFE_PRINTF is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart12" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set @@ -236,7 +239,9 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set @@ -587,8 +592,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_VECTOR is not set -# CONFIG_PKG_USING_SORCH is not set -# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -736,8 +739,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set -# CONFIG_PKG_USING_EVENT_LOOP is not set -# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -821,21 +822,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# MM32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set -# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set -# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set -# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set -# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set -# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set -# end of MM32 HAL & SDK Drivers +# CONFIG_PKG_USING_MM32 is not set # # WCH HAL & SDK Drivers @@ -900,7 +887,9 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -926,12 +915,6 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers - -# -# NOVOSNS Drivers -# -# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set -# end of NOVOSNS Drivers # end of HAL & SDK Drivers # @@ -1112,7 +1095,6 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set -# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set @@ -1468,31 +1450,44 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y # On-chip Peripheral Drivers # # CONFIG_BSP_USING_DMA is not set -CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_SDIO is not set CONFIG_BSP_USING_LPUART=y -CONFIG_BSP_USING_LPUART1=y -# CONFIG_BSP_LPUART1_RX_USING_DMA is not set -# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART1 is not set +# CONFIG_BSP_USING_LPUART2 is not set # CONFIG_BSP_USING_LPUART3 is not set -# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LPUART4 is not set +# CONFIG_BSP_USING_LPUART5 is not set +# CONFIG_BSP_USING_LPUART6 is not set +# CONFIG_BSP_USING_LPUART7 is not set +# CONFIG_BSP_USING_LPUART8 is not set +# CONFIG_BSP_USING_LPUART9 is not set +# CONFIG_BSP_USING_LPUART10 is not set +# CONFIG_BSP_USING_LPUART11 is not set +CONFIG_BSP_USING_LPUART12=y +# CONFIG_BSP_LPUART12_RX_USING_DMA is not set +# CONFIG_BSP_LPUART12_TX_USING_DMA is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_FLEXSPI is not set -# CONFIG_BSP_USING_CLOCK_TIMER is not set # end of On-chip Peripheral Drivers # # Onboard Peripheral Drivers # -# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USE_HYPERRAM is not set +# CONFIG_BSP_USE_MULTICORE is not set +# CONFIG_BSP_USING_ETHERCAT is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_FS is not set -# CONFIG_BSP_USING_VGLITE is not set # end of Onboard Peripheral Drivers # # Board extended module Drivers # +CONFIG_BSP_LINKER_SCRIPT_RAM=y +# CONFIG_BSP_LINKER_SCRIPT_HYPERRAM is not set +# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR is not set +# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript index 8f55fb0d82f5..84029503eb9f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript @@ -3,7 +3,11 @@ from building import * import os cwd = GetCurrentDir() -src = Glob('*.c') + +src = Split(""" +main.c +""") + CPPPATH = [cwd] # add for startup script @@ -12,6 +16,22 @@ if rtconfig.PLATFORM in ['gcc']: else: CPPDEFINES = [] +if GetDepend(['BSP_USE_MULTICORE']): + src += Split(""" + multicore_thread.c + """) + +if GetDepend(['BSP_USING_ETHERCAT']): + src += Split(""" + ecat_thread.c + """) + +if GetDepend(['BSP_USING_FS']): + src += Split(""" + mnt.c + """) + +# Create application group group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c index 9a7f3eadac18..243336989bdc 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c @@ -14,12 +14,19 @@ #include #include +#define LED_PIN GET_PIN(4, 27) + int main(void) { rt_kprintf("MIMXRT1180_CM7 Hello_World\r\n"); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + while (1) { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); rt_thread_mdelay(500); } } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig index 2f01e1b5de2d..2c4c78b6a118 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -19,10 +19,6 @@ config SOC_MIMXRT1189CVM8C_CM7 select ARCH_ARM_CORTEX_M7 select ARCH_ARM_CORTEX_FPU -config BSP_USING_LCD_MIPI - bool - default n - menu "On-chip Peripheral Drivers" config BSP_USING_DMA @@ -39,18 +35,42 @@ menu "On-chip Peripheral Drivers" select RT_USING_RTC default n - config BSP_USING_USB - bool "Enable USB" - select RT_USING_USB_HOST + menuconfig BSP_USING_USB + bool "Enable USB (CherryUSB)" default n if BSP_USING_USB - config BSP_USB0_HOST - bool "Enable USB0" - default n - - config BSP_USB1_HOST - bool "Enable USB1" + choice + prompt "USB controller" + default BSP_CHERRYUSB_USING_OTG1 + + config BSP_CHERRYUSB_USING_OTG1 + bool "USB OTG1" + + config BSP_CHERRYUSB_USING_OTG2 + bool "USB OTG2" + endchoice + + choice + prompt "USB role" + default BSP_USING_CHERRYUSB_DEVICE + + config BSP_USING_CHERRYUSB_DEVICE + bool "Enable USB Device" + select RT_USING_CHERRYUSB + select RT_CHERRYUSB_DEVICE + + config BSP_USING_CHERRYUSB_HOST + bool "Enable USB Host" + select RT_USING_CHERRYUSB + select RT_CHERRYUSB_HOST + select RT_USING_TIMER_SOFT + endchoice + + config BSP_CHERRYUSB_HOST_MOUSE_DEMO + bool "Enable CherryUSB host mouse shell demo" + depends on BSP_USING_CHERRYUSB_HOST + select RT_CHERRYUSB_HOST_HID default n endif @@ -78,201 +98,445 @@ menu "On-chip Peripheral Drivers" bool "Enable LPUART1" default y - config BSP_LPUART1_RX_USING_DMA - bool "Enable LPUART1 RX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_RX_DMA_CHANNEL - depends on BSP_LPUART1_RX_USING_DMA - int "Set LPUART1 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART1_TX_USING_DMA - bool "Enable LPUART1 TX DMA" - depends on BSP_USING_LPUART1 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART1_TX_DMA_CHANNEL - depends on BSP_LPUART1_TX_USING_DMA - int "Set LPUART1 TX DMA channel (0-32)" - default 1 + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART2 + bool "Enable LPUART2" + default n + + config BSP_LPUART2_RX_USING_DMA + bool "Enable LPUART2 RX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_RX_DMA_CHANNEL + depends on BSP_LPUART2_RX_USING_DMA + int "Set LPUART2 RX DMA channel (0-32)" + default 2 + + config BSP_LPUART2_TX_USING_DMA + bool "Enable LPUART2 TX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_TX_DMA_CHANNEL + depends on BSP_LPUART2_TX_USING_DMA + int "Set LPUART2 TX DMA channel (0-32)" + default 3 config BSP_USING_LPUART3 bool "Enable LPUART3" default n - config BSP_LPUART3_RX_USING_DMA - bool "Enable LPUART3 RX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_RX_DMA_CHANNEL - depends on BSP_LPUART3_RX_USING_DMA - int "Set LPUART3 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART3_TX_USING_DMA - bool "Enable LPUART3 TX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_TX_DMA_CHANNEL - depends on BSP_LPUART3_TX_USING_DMA - int "Set LPUART3 TX DMA channel (0-32)" - default 1 - endif + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - menuconfig BSP_USING_I2C - bool "Enable I2C" - select RT_USING_I2C - default n - if BSP_USING_I2C - config BSP_USING_I2C2 - bool "Enable I2C2" - default y + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 4 - config BSP_USING_I2C3 - bool "Enable I2C3" - default n + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - choice I2C2_BAUD_SEL - prompt "Select I2C2 badurate" - default HW_I2C2_BADURATE_100kHZ + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 5 - config HW_I2C2_BADURATE_100kHZ - bool "Badurate 100kHZ" + config BSP_USING_LPUART4 + bool "Enable LPUART4" + default n - config HW_I2C2_BADURATE_400kHZ - bool "Badurate 400kHZ" - endchoice + config BSP_LPUART4_RX_USING_DMA + bool "Enable LPUART4 RX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - choice I2C3_BAUD_SEL - prompt "Select I2C3 badurate" - default HW_I2C3_BADURATE_100kHZ + config BSP_LPUART4_RX_DMA_CHANNEL + depends on BSP_LPUART4_RX_USING_DMA + int "Set LPUART4 RX DMA channel (0-32)" + default 6 - config HW_I2C3_BADURATE_100kHZ - bool "Badurate 100kHZ" + config BSP_LPUART4_TX_USING_DMA + bool "Enable LPUART4 TX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - config HW_I2C3_BADURATE_400kHZ - bool "Badurate 400kHZ" - endchoice - endif + config BSP_LPUART4_TX_DMA_CHANNEL + depends on BSP_LPUART4_TX_USING_DMA + int "Set LPUART4 TX DMA channel (0-32)" + default 7 - menuconfig BSP_USING_CAN - bool "Enable CAN" - select RT_USING_CAN - default n - if BSP_USING_CAN - config BSP_USING_CAN3 - bool "Enable FLEXCAN3" - default n - endif + config BSP_USING_LPUART5 + bool "Enable LPUART5" + default n - menuconfig BSP_USING_FLEXSPI - bool "Enable FLEXSPI" - default n - if BSP_USING_FLEXSPI - config BSP_USING_FLEXSPI1 - bool "Enable FLEXSPI1" - default n - config BSP_USING_FLEXSPI2 - bool "Enable FLEXSPI2" - default n - endif + config BSP_LPUART5_RX_USING_DMA + bool "Enable LPUART5 RX DMA" + depends on BSP_USING_LPUART5 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n - menuconfig BSP_USING_CLOCK_TIMER - bool "Enable GPT" - default n - select RT_USING_CLOCK_TIME - if BSP_USING_CLOCK_TIMER - config BSP_USING_CLOCK_TIMER1 - bool "Enable GPT1" - default n - - config BSP_USING_CLOCK_TIMER2 - bool "Enable GPT2" - default n - endif + config BSP_LPUART5_RX_DMA_CHANNEL + depends on BSP_LPUART5_RX_USING_DMA + int "Set LPUART5 RX DMA channel (0-32)" + default 8 + + config BSP_LPUART5_TX_USING_DMA + bool "Enable LPUART5 TX DMA" + depends on BSP_USING_LPUART5 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART5_TX_DMA_CHANNEL + depends on BSP_LPUART5_TX_USING_DMA + int "Set LPUART5 TX DMA channel (0-32)" + default 9 + + config BSP_USING_LPUART6 + bool "Enable LPUART6" + default n + + config BSP_LPUART6_RX_USING_DMA + bool "Enable LPUART6 RX DMA" + depends on BSP_USING_LPUART6 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART6_RX_DMA_CHANNEL + depends on BSP_LPUART6_RX_USING_DMA + int "Set LPUART6 RX DMA channel (0-32)" + default 10 + + config BSP_LPUART6_TX_USING_DMA + bool "Enable LPUART6 TX DMA" + depends on BSP_USING_LPUART6 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART6_TX_DMA_CHANNEL + depends on BSP_LPUART6_TX_USING_DMA + int "Set LPUART6 TX DMA channel (0-32)" + default 11 + + config BSP_USING_LPUART7 + bool "Enable LPUART7" + default n + + config BSP_LPUART7_RX_USING_DMA + bool "Enable LPUART7 RX DMA" + depends on BSP_USING_LPUART7 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART7_RX_DMA_CHANNEL + depends on BSP_LPUART7_RX_USING_DMA + int "Set LPUART7 RX DMA channel (0-32)" + default 12 + + config BSP_LPUART7_TX_USING_DMA + bool "Enable LPUART7 TX DMA" + depends on BSP_USING_LPUART7 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART7_TX_DMA_CHANNEL + depends on BSP_LPUART7_TX_USING_DMA + int "Set LPUART7 TX DMA channel (0-32)" + default 13 + + config BSP_USING_LPUART8 + bool "Enable LPUART8" + default n + + config BSP_LPUART8_RX_USING_DMA + bool "Enable LPUART8 RX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_RX_DMA_CHANNEL + depends on BSP_LPUART8_RX_USING_DMA + int "Set LPUART8 RX DMA channel (0-32)" + default 14 + + config BSP_LPUART8_TX_USING_DMA + bool "Enable LPUART8 TX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_TX_DMA_CHANNEL + depends on BSP_LPUART8_TX_USING_DMA + int "Set LPUART8 TX DMA channel (0-32)" + default 15 + + config BSP_USING_LPUART9 + bool "Enable LPUART9" + default n + + config BSP_LPUART9_RX_USING_DMA + bool "Enable LPUART9 RX DMA" + depends on BSP_USING_LPUART9 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART9_RX_DMA_CHANNEL + depends on BSP_LPUART9_RX_USING_DMA + int "Set LPUART9 RX DMA channel (0-32)" + default 16 + + config BSP_LPUART9_TX_USING_DMA + bool "Enable LPUART9 TX DMA" + depends on BSP_USING_LPUART9 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART9_TX_DMA_CHANNEL + depends on BSP_LPUART9_TX_USING_DMA + int "Set LPUART9 TX DMA channel (0-32)" + default 17 + + config BSP_USING_LPUART10 + bool "Enable LPUART10" + default n + + config BSP_LPUART10_RX_USING_DMA + bool "Enable LPUART10 RX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_RX_DMA_CHANNEL + depends on BSP_LPUART10_RX_USING_DMA + int "Set LPUART10 RX DMA channel (0-32)" + default 18 + + config BSP_LPUART10_TX_USING_DMA + bool "Enable LPUART10 TX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_TX_DMA_CHANNEL + depends on BSP_LPUART10_TX_USING_DMA + int "Set LPUART10 TX DMA channel (0-32)" + default 19 + + config BSP_USING_LPUART11 + bool "Enable LPUART11" + default n + + config BSP_LPUART11_RX_USING_DMA + bool "Enable LPUART11 RX DMA" + depends on BSP_USING_LPUART11 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART11_RX_DMA_CHANNEL + depends on BSP_LPUART11_RX_USING_DMA + int "Set LPUART11 RX DMA channel (0-32)" + default 20 + + config BSP_LPUART11_TX_USING_DMA + bool "Enable LPUART11 TX DMA" + depends on BSP_USING_LPUART11 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART11_TX_DMA_CHANNEL + depends on BSP_LPUART11_TX_USING_DMA + int "Set LPUART11 TX DMA channel (0-32)" + default 21 + + config BSP_USING_LPUART12 + bool "Enable LPUART12" + default n + + config BSP_LPUART12_RX_USING_DMA + bool "Enable LPUART12 RX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_RX_DMA_CHANNEL + depends on BSP_LPUART12_RX_USING_DMA + int "Set LPUART12 RX DMA channel (0-32)" + default 22 + + config BSP_LPUART12_TX_USING_DMA + bool "Enable LPUART12 TX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_TX_DMA_CHANNEL + depends on BSP_LPUART12_TX_USING_DMA + int "Set LPUART12 TX DMA channel (0-32)" + default 23 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif endmenu menu "Onboard Peripheral Drivers" - config BSP_USING_OSPI_FLASH - bool "Enable HyperFlash Example" - depends on BSP_USING_FLEXSPI1 + # config BSP_USING_SDRAM + # bool "Enable SDRAM" + # default n + + config BSP_USE_HYPERRAM + bool "Enable HyperRAM" default n - config BSP_USING_SDRAM - bool "Enable SDRAM" + menuconfig BSP_USE_MULTICORE + bool "Enable Multicore" + default n + + if BSP_USE_MULTICORE + config BSP_USE_MULTICORE_KICK_OFF + bool "Enable CM33 Kick-off CM7" + default y + help + Enable CM33 core to kick-off CM7 core startup. + This is required for proper initialization sequence + when CM33 (master) boots CM7 (remote) core. + + config BSP_USE_MULTICORE_RPMSG_LITE + bool "Enable RPMsg-Lite for Inter-Core Communication" + default y + help + Enable RPMsg-Lite messaging system for communication between cores. + RPMsg-Lite provides a lightweight implementation of the RPMsg protocol + for inter-processor communication using shared memory. + CM7 runs as remote core, CM33 runs as master core. + + if BSP_USE_MULTICORE_RPMSG_LITE + config RPMSG_LITE_LINK_ID + int "RPMsg-Lite Link ID" + default 0 + help + Specify the link ID for RPMsg-Lite communication. + Default is RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID (0). + + config RPMSG_LOCAL_EPT_ADDR + int "Local Endpoint Address (CM7 side)" + range 0 65535 + default 30 + help + Specify the local endpoint address for RPMsg communication on CM7 side. + + config RPMSG_NS_ANNOUNCE_STRING + string "RPMsg Nameservice Announce String" + default "rpmsg-openamp-demo-channel" + help + The string used to announce the service to the CM33 master core. + endif + endif + + config BSP_USING_ETHERCAT + bool "Enable ETHERCAT" + select RT_USING_ETHERCAT default n menuconfig BSP_USING_ETH bool "Enable Ethernet" + select RT_USING_SAL select RT_USING_NETDEV select RT_USING_LWIP default n if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + depends on RT_USING_LWIP_VER_NUM >= 0x20000 + default 1 + + config NETC_USE_SWT + int "Enable NETC switch mode (0: EP0, 1: switch)" + range 0 1 + default 0 + config BSP_USING_PHY select RT_USING_PHY bool "Enable ethernet phy" default y - - if BSP_USING_PHY - config PHY_USING_KSZ8081 - bool "i.MX RT1176EVK uses ksz8081 phy" - default y - - if PHY_USING_KSZ8081 - config PHY_KSZ8081_ADDRESS - int "Specify address of phy device" - default 2 - - config PHY_RESET_KSZ8081_PORT - int "indicate port of reset" - default 6 - - config PHY_RESET_KSZ8081_PIN - int "indicate pin of reset" - default 12 - - config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE - bool "Enable the PHY ksz8081 RMII50M mode" - depends on PHY_USING_KSZ8081 - default y - endif - endif - - if BSP_USING_PHY - config PHY_USING_RTL8211F - bool "i.MX RT1176EVK uses rtl8211f phy" - default y - - if PHY_USING_RTL8211F - config PHY_RTL8211F_ADDRESS - int "Specify address of phy device" - default 1 - - config PHY_RESET_RTL8211F_PORT - int "indicate port of reset" - default 5 - - config PHY_RESET_RTL8211F_PIN - int "indicate pin of reset" - default 14 - - endif - endif endif menuconfig BSP_USING_FS @@ -287,49 +551,56 @@ menu "Onboard Peripheral Drivers" select BSP_USING_SDIO select RT_USING_DFS_ELMFAT default n + + config BSP_USING_QSPI_FLASH_FS + bool "Enable QSPI Flash (LittleFS)" + select BSP_USING_FLEXSPI + select BSP_USING_FLEXSPI1 + select RT_USING_FAL + select FAL_PART_HAS_TABLE_CFG + select RT_USING_MTD_NOR + select PKG_USING_LITTLEFS + default n endif - menuconfig BSP_USING_VGLITE - bool "Enable VGLite" - select RT_USING_PIN - select BSP_USING_LCD_MIPI + config BSP_USING_OSPI_FLASH + bool "Enable HyperFlash Example" + depends on BSP_USING_FLEXSPI1 default n - if BSP_USING_VGLITE - choice DISP_RK055_SEL - prompt "Select display panel" - default DISPLAY_USING_RK055AHD091 - - config DISPLAY_USING_RK055AHD091 - bool "RK055AHD091-CTG (RK055HDMIPI4M 720 * 1280)" - - config DISPLAY_USING_RK055IQH091 - bool "RK055IQH091-CTG (540 * 960)" - - config DISPLAY_USING_RK055MHD091 - bool "RK055MHD091A0-CTG (RK055HDMIPI4MA0 720 * 1280)" - endchoice - - choice DISP_CTRL_SEL - prompt "Select display controller" - default BSP_USING_LCDIFV2 - - config BSP_USING_ELCDIF - bool "ELCDIF" - - config BSP_USING_LCDIFV2 - bool "LCDIFV2" - endchoice - - config VGLITE_USING_ELM - bool "Enable Elementary" - default y - endif - endmenu menu "Board extended module Drivers" endmenu +choice + prompt "Linker Script Selection" + default BSP_LINKER_SCRIPT_RAM + help + Select the linker script that matches your target memory configuration. + + config BSP_LINKER_SCRIPT_RAM + bool "RAM (internal SRAM only)" + help + Link the image to run entirely from internal SRAM. + + config BSP_LINKER_SCRIPT_HYPERRAM + bool "HyperRAM (internal SRAM + external HyperRAM)" + help + Link the image to run from internal SRAM with HyperRAM support. + + config BSP_LINKER_SCRIPT_FLEXSPI_NOR + bool "FlexSPI NOR Flash (XIP from external NOR flash)" + help + Link the image to execute-in-place (XIP) from external NOR flash + connected via FlexSPI. + + config BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM + bool "FlexSPI NOR Flash + HyperRAM (XIP + external HyperRAM)" + help + Link the image to XIP from external NOR flash and use HyperRAM + as additional RAM. +endchoice + endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c index 7c1d7f6afdf5..29cd9fde59d9 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c @@ -412,8 +412,8 @@ void BOARD_BootClockRUN(void) #endif #if (__CORTEX_M == 7) - DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P1V); - DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P1V); + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V); /* FBB need to be enabled in OverDrive(OD) mode */ PMU_EnableFBB(ANADIG_PMU, true); #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c index e5f2f5f8ba26..528f26fd746f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c @@ -22,6 +22,7 @@ processor_version: 0.15.9 #include "fsl_common.h" #include "fsl_iomuxc.h" +#include "fsl_rgpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -32,89 +33,534 @@ processor_version: 0.15.9 * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); + +#ifdef BSP_USING_ETH + BOARD_InitPhyAccessPins(); + BOARD_InitEpPins(); + BOARD_InitSwtPort0Pins(); +#endif } +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M7 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + +#ifdef BSP_USING_LPUART12 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 is configured as LPUART12_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_20_LPUART12_RX, /* GPIO_AON_20 is configured as LPUART12_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_20_LPUART12_RX, /* GPIO_AON_20 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +#endif + +#ifdef BSP_USING_I2C2 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ +#endif + +#ifdef BSP_USING_I2C3 + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + 0x1DU); /* Slew Rate Field: Slow Slew Rate + Pull Enable Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled */ +#endif + +} + + +#ifdef BSP_USING_ETH /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: +BOARD_InitPhyAccessPins: - options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} - pin_list: - - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, - slew_rate: Slow} - - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, - slew_rate: Slow} + - {pin_num: L17, peripheral: NETC, signal: netc_emdc, pin_signal: GPIO_AD_30, pull_up_down_config: Pull_Down, open_drain: Disable} + - {pin_num: K17, peripheral: NETC, signal: netc_emdio, pin_signal: GPIO_AD_31, identifier: NETC_ECAT_MDIO, pull_up_down_config: Pull_Down, open_drain: Enable} + - {pin_num: M15, peripheral: RGPIO4, signal: 'gpio_io, 25', pin_signal: GPIO_AD_25, direction: OUTPUT, pull_up_down_config: Pull_Down} + - {pin_num: B11, peripheral: RGPIO6, signal: 'gpio_io, 13', pin_signal: GPIO_B1_13, direction: OUTPUT} + - {pin_num: L16, peripheral: RGPIO4, signal: 'gpio_io, 28', pin_signal: GPIO_AD_28, identifier: ENET2_RST_B, direction: OUTPUT} + - {pin_num: E10, peripheral: RGPIO6, signal: 'gpio_io, 15', pin_signal: GPIO_B2_01, direction: OUTPUT} + - {pin_num: N15, peripheral: RGPIO4, signal: 'gpio_io, 13', pin_signal: GPIO_AD_13, direction: OUTPUT} + - {pin_num: P17, peripheral: RGPIO4, signal: 'gpio_io, 12', pin_signal: GPIO_AD_12, direction: INPUT, gpio_interrupt: no_init, gpio_interrupt_output: no_init, pull_up_down_config: no_init, + open_drain: Disable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Function Name : BOARD_InitPhyAccessPins, assigned for the Cortex-M33 core. * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ - 0x1DU); /* Slew Rate Field: Slow Slew Rate - Pull Enable Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ - 0x1DU); /* Slew Rate Field: Slow Slew Rate - Pull Enable Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 is configured as LPI2C3_SCL */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 is configured as LPI2C3_SDA */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 PAD functional properties : */ - 0x1DU); /* Slew Rate Field: Slow Slew Rate - Pull Enable Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 PAD functional properties : */ - 0x1DU); /* Slew Rate Field: Slow Slew Rate - Pull Enable Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled */ +void BOARD_InitPhyAccessPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + /* GPIO configuration of ENET4_INT_B on GPIO_AD_12 (pin P17) */ + rgpio_pin_config_t ENET4_INT_B_config = { + .pinDirection = kRGPIO_DigitalInput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_12 (pin P17) */ + RGPIO_PinInit(RGPIO4, 12U, &ENET4_INT_B_config); + /* Configures GPIO pin interrupt/DMA request on GPIO_AD_12 (pin P17) */ + RGPIO_SetPinInterruptConfig(RGPIO4, 12U, kRGPIO_InterruptOutput0, kRGPIO_InterruptOrDMADisabled); + + /* GPIO configuration of ENET4_RST_B on GPIO_AD_13 (pin N15) */ + rgpio_pin_config_t ENET4_RST_B_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_13 (pin N15) */ + RGPIO_PinInit(RGPIO4, 13U, &ENET4_RST_B_config); + + /* GPIO configuration of ENET0_RST_B on GPIO_AD_25 (pin M15) */ + rgpio_pin_config_t ENET0_RST_B_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_25 (pin M15) */ + RGPIO_PinInit(RGPIO4, 25U, &ENET0_RST_B_config); + + /* GPIO configuration of ENET2_RST_B on GPIO_AD_28 (pin L16) */ + rgpio_pin_config_t ENET2_RST_B_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_28 (pin L16) */ + RGPIO_PinInit(RGPIO4, 28U, &ENET2_RST_B_config); + + /* GPIO configuration of ENET1_RST_B on GPIO_B1_13 (pin B11) */ + rgpio_pin_config_t ENET1_RST_B_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_B1_13 (pin B11) */ + RGPIO_PinInit(RGPIO6, 13U, &ENET1_RST_B_config); + + /* GPIO configuration of ENET3_RST_B on GPIO_B2_01 (pin E10) */ + rgpio_pin_config_t ENET3_RST_B_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_B2_01 (pin E10) */ + RGPIO_PinInit(RGPIO6, 15U, &ENET3_RST_B_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_12_GPIO4_IO12, /* GPIO_AD_12 is configured as GPIO4_IO12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_13_GPIO4_IO13, /* GPIO_AD_13 is configured as GPIO4_IO13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_GPIO4_IO25, /* GPIO_AD_25 is configured as GPIO4_IO25 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_28_GPIO4_IO28, /* GPIO_AD_28 is configured as GPIO4_IO28 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_30_NETC_EMDC, /* GPIO_AD_30 is configured as NETC_EMDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_31_NETC_EMDIO, /* GPIO_AD_31 is configured as NETC_EMDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_13_GPIO6_IO13, /* GPIO_B1_13 is configured as GPIO6_IO13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_01_GPIO6_IO15, /* GPIO_B2_01 is configured as GPIO6_IO15 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_12_GPIO4_IO12, /* GPIO_AD_12 PAD functional properties : */ + 0x0EU); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Disabled + Force ibe off Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_25_GPIO4_IO25, /* GPIO_AD_25 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Force ibe off Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_30_NETC_EMDC, /* GPIO_AD_30 PAD functional properties : */ + 0x06U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Force ibe off Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_31_NETC_EMDIO, /* GPIO_AD_31 PAD functional properties : */ + 0x16U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Enabled + Force ibe off Field: Disabled */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitEpPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: R4, peripheral: NETC_ENETC0_ETH4, signal: TX_EN, pin_signal: GPIO_EMC_B2_15} + - {pin_num: R7, peripheral: NETC_ENETC0_ETH4, signal: TX_CLK, pin_signal: GPIO_EMC_B2_16, software_input_on: Enable} + - {pin_num: R6, peripheral: NETC_ENETC0_ETH4, signal: 'TX_DATA, 0', pin_signal: GPIO_EMC_B2_13} + - {pin_num: N8, peripheral: NETC_ENETC0_ETH4, signal: 'TX_DATA, 1', pin_signal: GPIO_EMC_B2_14} + - {pin_num: U8, peripheral: NETC_ENETC0_ETH4, signal: RX_EN, pin_signal: GPIO_EMC_B2_19} + - {pin_num: R8, peripheral: NETC_ENETC0_ETH4, signal: RX_ER, pin_signal: GPIO_EMC_B2_20} + - {pin_num: U7, peripheral: NETC_ENETC0_ETH4, signal: 'RX_DATA, 0', pin_signal: GPIO_EMC_B2_17} + - {pin_num: P8, peripheral: NETC_ENETC0_ETH4, signal: 'RX_DATA, 1', pin_signal: GPIO_EMC_B2_18} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitEpPins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitEpPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_13_NETC_PINMUX_ETH4_TXD00, /* GPIO_EMC_B2_13 is configured as NETC_PINMUX_ETH4_TXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_14_NETC_PINMUX_ETH4_TXD01, /* GPIO_EMC_B2_14 is configured as NETC_PINMUX_ETH4_TXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_15_NETC_PINMUX_ETH4_TX_EN, /* GPIO_EMC_B2_15 is configured as NETC_PINMUX_ETH4_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_16_NETC_PINMUX_ETH4_TX_CLK, /* GPIO_EMC_B2_16 is configured as NETC_PINMUX_ETH4_TX_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_16 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_17_NETC_PINMUX_ETH4_RXD00, /* GPIO_EMC_B2_17 is configured as NETC_PINMUX_ETH4_RXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_18_NETC_PINMUX_ETH4_RXD01, /* GPIO_EMC_B2_18 is configured as NETC_PINMUX_ETH4_RXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_19_NETC_PINMUX_ETH4_RX_DV, /* GPIO_EMC_B2_19 is configured as NETC_PINMUX_ETH4_RX_DV */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_20_NETC_PINMUX_ETH4_RX_ER, /* GPIO_EMC_B2_20 is configured as NETC_PINMUX_ETH4_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSwtPort0Pins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: T7, peripheral: NETC_SWT_ETH0, signal: TX_EN, pin_signal: GPIO_EMC_B2_07} + - {pin_num: U4, peripheral: NETC_SWT_ETH0, signal: TX_CLK, pin_signal: GPIO_EMC_B2_08, software_input_on: Enable} + - {pin_num: T4, peripheral: NETC_SWT_ETH0, signal: 'TX_DATA, 0', pin_signal: GPIO_EMC_B2_05} + - {pin_num: T6, peripheral: NETC_SWT_ETH0, signal: 'TX_DATA, 1', pin_signal: GPIO_EMC_B2_06} + - {pin_num: P6, peripheral: NETC_SWT_ETH0, signal: RX_EN, pin_signal: GPIO_EMC_B2_11} + - {pin_num: R5, peripheral: NETC_SWT_ETH0, signal: RX_ER, pin_signal: GPIO_EMC_B2_12} + - {pin_num: U5, peripheral: NETC_SWT_ETH0, signal: 'RX_DATA, 0', pin_signal: GPIO_EMC_B2_09} + - {pin_num: U6, peripheral: NETC_SWT_ETH0, signal: 'RX_DATA, 1', pin_signal: GPIO_EMC_B2_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSwtPort0Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSwtPort0Pins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_05_NETC_PINMUX_ETH0_TXD00, /* GPIO_EMC_B2_05 is configured as NETC_PINMUX_ETH0_TXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_06_NETC_PINMUX_ETH0_TXD01, /* GPIO_EMC_B2_06 is configured as NETC_PINMUX_ETH0_TXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_07_NETC_PINMUX_ETH0_TX_EN, /* GPIO_EMC_B2_07 is configured as NETC_PINMUX_ETH0_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_08_NETC_PINMUX_ETH0_TX_CLK, /* GPIO_EMC_B2_08 is configured as NETC_PINMUX_ETH0_TX_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_08 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_09_NETC_PINMUX_ETH0_RXD00, /* GPIO_EMC_B2_09 is configured as NETC_PINMUX_ETH0_RXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_10_NETC_PINMUX_ETH0_RXD01, /* GPIO_EMC_B2_10 is configured as NETC_PINMUX_ETH0_RXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_11_NETC_PINMUX_ETH0_RX_DV, /* GPIO_EMC_B2_11 is configured as NETC_PINMUX_ETH0_RX_DV */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_12_NETC_PINMUX_ETH0_RX_ER, /* GPIO_EMC_B2_12 is configured as NETC_PINMUX_ETH0_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSwtPort1Pins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: A14, peripheral: NETC_SWT_ETH1, signal: TX_CLK, pin_signal: GPIO_B1_03} + - {pin_num: E12, peripheral: NETC_SWT_ETH1, signal: TX_EN, pin_signal: GPIO_B1_02} + - {pin_num: E13, peripheral: NETC_SWT_ETH1, signal: 'TX_DATA, 0', pin_signal: GPIO_B1_00} + - {pin_num: C12, peripheral: NETC_SWT_ETH1, signal: 'TX_DATA, 1', pin_signal: GPIO_B1_01} + - {pin_num: D13, peripheral: NETC_SWT_ETH1, signal: 'TX_DATA, 2', pin_signal: GPIO_B1_07} + - {pin_num: B14, peripheral: NETC_SWT_ETH1, signal: 'TX_DATA, 3', pin_signal: GPIO_B1_08} + - {pin_num: A12, peripheral: NETC_SWT_ETH1, signal: RX_CLK, pin_signal: GPIO_B1_11} + - {pin_num: B10, peripheral: NETC_SWT_ETH1, signal: RX_EN, pin_signal: GPIO_B1_06} + - {pin_num: B13, peripheral: NETC_SWT_ETH1, signal: 'RX_DATA, 0', pin_signal: GPIO_B1_04} + - {pin_num: B12, peripheral: NETC_SWT_ETH1, signal: 'RX_DATA, 1', pin_signal: GPIO_B1_05} + - {pin_num: A15, peripheral: NETC_SWT_ETH1, signal: 'RX_DATA, 2', pin_signal: GPIO_B1_09} + - {pin_num: A13, peripheral: NETC_SWT_ETH1, signal: 'RX_DATA, 3', pin_signal: GPIO_B1_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSwtPort1Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSwtPort1Pins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_NETC_PINMUX_ETH1_TXD00, /* GPIO_B1_00 is configured as NETC_PINMUX_ETH1_TXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_NETC_PINMUX_ETH1_TXD01, /* GPIO_B1_01 is configured as NETC_PINMUX_ETH1_TXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_02_NETC_PINMUX_ETH1_TX_EN, /* GPIO_B1_02 is configured as NETC_PINMUX_ETH1_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_03_NETC_PINMUX_ETH1_TX_CLK, /* GPIO_B1_03 is configured as NETC_PINMUX_ETH1_TX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_NETC_PINMUX_ETH1_RXD00, /* GPIO_B1_04 is configured as NETC_PINMUX_ETH1_RXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_NETC_PINMUX_ETH1_RXD01, /* GPIO_B1_05 is configured as NETC_PINMUX_ETH1_RXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_NETC_PINMUX_ETH1_RX_DV, /* GPIO_B1_06 is configured as NETC_PINMUX_ETH1_RX_DV */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_NETC_PINMUX_ETH1_TXD02, /* GPIO_B1_07 is configured as NETC_PINMUX_ETH1_TXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_NETC_PINMUX_ETH1_TXD03, /* GPIO_B1_08 is configured as NETC_PINMUX_ETH1_TXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_NETC_PINMUX_ETH1_RXD02, /* GPIO_B1_09 is configured as NETC_PINMUX_ETH1_RXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_NETC_PINMUX_ETH1_RXD03, /* GPIO_B1_10 is configured as NETC_PINMUX_ETH1_RXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_NETC_PINMUX_ETH1_RX_CLK, /* GPIO_B1_11 is configured as NETC_PINMUX_ETH1_RX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSwtPort2Pins: +- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: E4, peripheral: NETC_SWT_ETH2, signal: TX_CLK, pin_signal: GPIO_EMC_B1_29} + - {pin_num: F5, peripheral: NETC_SWT_ETH2, signal: TX_EN, pin_signal: GPIO_EMC_B1_28} + - {pin_num: J3, peripheral: NETC_SWT_ETH2, signal: 'TX_DATA, 0', pin_signal: GPIO_EMC_B1_27} + - {pin_num: N4, peripheral: NETC_SWT_ETH2, signal: 'TX_DATA, 1', pin_signal: GPIO_EMC_B1_26} + - {pin_num: N3, peripheral: NETC_SWT_ETH2, signal: 'TX_DATA, 2', pin_signal: GPIO_EMC_B1_25} + - {pin_num: P2, peripheral: NETC_SWT_ETH2, signal: 'TX_DATA, 3', pin_signal: GPIO_EMC_B1_24} + - {pin_num: K4, peripheral: NETC_SWT_ETH2, signal: RX_CLK, pin_signal: GPIO_EMC_B1_21} + - {pin_num: F3, peripheral: NETC_SWT_ETH2, signal: RX_EN, pin_signal: GPIO_EMC_B1_13} + - {pin_num: H1, peripheral: NETC_SWT_ETH2, signal: 'RX_DATA, 0', pin_signal: GPIO_EMC_B1_16} + - {pin_num: E2, peripheral: NETC_SWT_ETH2, signal: 'RX_DATA, 1', pin_signal: GPIO_EMC_B1_17} + - {pin_num: L3, peripheral: NETC_SWT_ETH2, signal: 'RX_DATA, 2', pin_signal: GPIO_EMC_B1_22} + - {pin_num: F1, peripheral: NETC_SWT_ETH2, signal: 'RX_DATA, 3', pin_signal: GPIO_EMC_B1_23} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSwtPort2Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSwtPort2Pins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_13_NETC_PINMUX_ETH2_RX_DV, /* GPIO_EMC_B1_13 is configured as NETC_PINMUX_ETH2_RX_DV */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_16_NETC_PINMUX_ETH2_RXD00, /* GPIO_EMC_B1_16 is configured as NETC_PINMUX_ETH2_RXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_17_NETC_PINMUX_ETH2_RXD01, /* GPIO_EMC_B1_17 is configured as NETC_PINMUX_ETH2_RXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_21_NETC_PINMUX_ETH2_RX_CLK, /* GPIO_EMC_B1_21 is configured as NETC_PINMUX_ETH2_RX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_22_NETC_PINMUX_ETH2_RXD02, /* GPIO_EMC_B1_22 is configured as NETC_PINMUX_ETH2_RXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_23_NETC_PINMUX_ETH2_RXD03, /* GPIO_EMC_B1_23 is configured as NETC_PINMUX_ETH2_RXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_24_NETC_PINMUX_ETH2_TXD03, /* GPIO_EMC_B1_24 is configured as NETC_PINMUX_ETH2_TXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_25_NETC_PINMUX_ETH2_TXD02, /* GPIO_EMC_B1_25 is configured as NETC_PINMUX_ETH2_TXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_26_NETC_PINMUX_ETH2_TXD01, /* GPIO_EMC_B1_26 is configured as NETC_PINMUX_ETH2_TXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_27_NETC_PINMUX_ETH2_TXD00, /* GPIO_EMC_B1_27 is configured as NETC_PINMUX_ETH2_TXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_28_NETC_PINMUX_ETH2_TX_EN, /* GPIO_EMC_B1_28 is configured as NETC_PINMUX_ETH2_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_29_NETC_PINMUX_ETH2_TX_CLK, /* GPIO_EMC_B1_29 is configured as NETC_PINMUX_ETH2_TX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSwtPort3Pins: +- options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: H5, peripheral: NETC_SWT_ETH3, signal: TX_CLK, pin_signal: GPIO_EMC_B1_08} + - {pin_num: M3, peripheral: NETC_SWT_ETH3, signal: TX_EN, pin_signal: GPIO_EMC_B1_07} + - {pin_num: H6, peripheral: NETC_SWT_ETH3, signal: 'TX_DATA, 0', pin_signal: GPIO_EMC_B1_05} + - {pin_num: K3, peripheral: NETC_SWT_ETH3, signal: 'TX_DATA, 1', pin_signal: GPIO_EMC_B1_06} + - {pin_num: H4, peripheral: NETC_SWT_ETH3, signal: 'TX_DATA, 2', pin_signal: GPIO_EMC_B1_01} + - {pin_num: H3, peripheral: NETC_SWT_ETH3, signal: 'TX_DATA, 3', pin_signal: GPIO_EMC_B1_00} + - {pin_num: K2, peripheral: NETC_SWT_ETH3, signal: RX_CLK, pin_signal: GPIO_EMC_B1_02} + - {pin_num: F2, peripheral: NETC_SWT_ETH3, signal: RX_EN, pin_signal: GPIO_EMC_B1_11} + - {pin_num: E1, peripheral: NETC_SWT_ETH3, signal: 'RX_DATA, 0', pin_signal: GPIO_EMC_B1_09} + - {pin_num: E3, peripheral: NETC_SWT_ETH3, signal: 'RX_DATA, 1', pin_signal: GPIO_EMC_B1_10} + - {pin_num: J4, peripheral: NETC_SWT_ETH3, signal: 'RX_DATA, 2', pin_signal: GPIO_EMC_B1_04} + - {pin_num: G3, peripheral: NETC_SWT_ETH3, signal: 'RX_DATA, 3', pin_signal: GPIO_EMC_B1_03} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSwtPort3Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSwtPort3Pins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_00_NETC_PINMUX_ETH3_TXD03, /* GPIO_EMC_B1_00 is configured as NETC_PINMUX_ETH3_TXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_01_NETC_PINMUX_ETH3_TXD02, /* GPIO_EMC_B1_01 is configured as NETC_PINMUX_ETH3_TXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_02_NETC_PINMUX_ETH3_RX_CLK, /* GPIO_EMC_B1_02 is configured as NETC_PINMUX_ETH3_RX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_03_NETC_PINMUX_ETH3_RXD03, /* GPIO_EMC_B1_03 is configured as NETC_PINMUX_ETH3_RXD03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_04_NETC_PINMUX_ETH3_RXD02, /* GPIO_EMC_B1_04 is configured as NETC_PINMUX_ETH3_RXD02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_05_NETC_PINMUX_ETH3_TXD00, /* GPIO_EMC_B1_05 is configured as NETC_PINMUX_ETH3_TXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_06_NETC_PINMUX_ETH3_TXD01, /* GPIO_EMC_B1_06 is configured as NETC_PINMUX_ETH3_TXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_07_NETC_PINMUX_ETH3_TX_EN, /* GPIO_EMC_B1_07 is configured as NETC_PINMUX_ETH3_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_08_NETC_PINMUX_ETH3_TX_CLK, /* GPIO_EMC_B1_08 is configured as NETC_PINMUX_ETH3_TX_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_09_NETC_PINMUX_ETH3_RXD00, /* GPIO_EMC_B1_09 is configured as NETC_PINMUX_ETH3_RXD00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_10_NETC_PINMUX_ETH3_RXD01, /* GPIO_EMC_B1_10 is configured as NETC_PINMUX_ETH3_RXD01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B1_11_NETC_PINMUX_ETH3_RX_DV, /* GPIO_EMC_B1_11 is configured as NETC_PINMUX_ETH3_RX_DV */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ } +#endif /*********************************************************************************************************************** * EOF diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h index cc4b717363ba..2fa7fab64716 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h @@ -12,6 +12,8 @@ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ +#include + /*! * @addtogroup pin_mux * @{ @@ -37,6 +39,112 @@ void BOARD_InitBootPins(void); */ void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ +#ifdef BSP_USING_ETH +/* GPIO_AD_25 (coord M15), ENET0_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_CHANNEL 25U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN 25U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN_MASK (1U << 25U) /*!< GPIO pin mask */ + +/* GPIO_B1_13 (coord B11), ENET1_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_CHANNEL 13U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ + +/* GPIO_AD_28 (coord L16), ENET2_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_CHANNEL 28U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN 28U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */ + +/* GPIO_B2_01 (coord E10), ENET3_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_CHANNEL 15U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ + +/* GPIO_AD_13 (coord N15), ENET4_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_CHANNEL 13U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ + +/* GPIO_AD_12 (coord P17), ENET4_INT_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_CHANNEL 12U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN 12U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN_MASK (1U << 12U) /*!< GPIO pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPhyAccessPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitEpPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort0Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort1Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort2Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort3Pins(void); /* Function assigned for the Cortex-M33 */ + +#endif + + #if defined(__cplusplus) } #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript index dabd72da3f2b..fc2d191f9403 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -1,4 +1,8 @@ +Import('rtconfig') +Import('RTT_ROOT') + from building import * +import os cwd = GetCurrentDir() @@ -17,6 +21,9 @@ else: MCUX_Config/pin_mux.c """) +if GetDepend(['BSP_USING_QSPI_FLASH_FS']): + src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c'] + if GetDepend(['BSP_USING_OSPI_FLASH']): src += ['ports/flexspi_octal_flash_ops.c'] @@ -25,7 +32,8 @@ if GetDepend(['BSP_USING_OSPI_FLASH']): else: CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 'ARM_MATH_CM7'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'ARM_MATH_CM7'] +LINKFLAGS = '' if rtconfig.PLATFORM in ['gcc']: CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION'] @@ -37,6 +45,47 @@ if rtconfig.PLATFORM in ['armcc', 'armclang']: if rtconfig.PLATFORM in ['iccarm']: CPPDEFINES += ['NDEBUG'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) +if GetDepend(['BSP_USE_HYPERRAM']): + CPPDEFINES += ['USE_HYPERRAM=1'] + +if GetDepend(['BSP_USE_MULTICORE']): + CPPDEFINES += ['__USE_SHMEM', 'MULTICORE_APP=1'] + CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] + if rtconfig.PLATFORM in ['gcc']: + LINKFLAGS += ' -Wl,-defsym,__use_shmem__=1' + LINKFLAGS += ' -Wl,-defsym,__multicore__=1' + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS += ' --predefine="-D__use_shmem__=1"' + LINKFLAGS += ' --predefine="-D__multicore__=1"' + if rtconfig.PLATFORM in ['iccarm']: + LINKFLAGS += ' __use_shmem__=1' + LINKFLAGS += ' __multicore__=1' + +if GetDepend(['BSP_USING_ETH']): + CPPDEFINES += ['SDK_NETC_USED=1', 'FSL_ETH_ENABLE_CACHE_CONTROL=1'] + +if GetDepend(['RT_USING_CHERRYUSB']): + cherryusb_path = os.path.join(RTT_ROOT, 'components', 'drivers', 'usb', 'cherryusb') + src += ['cherryusb_port.c'] + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM']): + src += ['cherryusb_cdc_acm.c'] + if GetDepend(['BSP_CHERRYUSB_HOST_MOUSE_DEMO']): + src += ['usbh_mouse_demo.c'] + CPPPATH += [ + cherryusb_path, + os.path.join(cherryusb_path, 'common'), + os.path.join(cherryusb_path, 'core'), + os.path.join(cherryusb_path, 'class', 'hub'), + os.path.join(cherryusb_path, 'class', 'cdc'), + os.path.join(cherryusb_path, 'class', 'hid'), + ] + +if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR']): + CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] + +if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM']): + CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES, LINKFLAGS=LINKFLAGS) Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c index f0303bfc9162..ee761f45868e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -7,16 +7,35 @@ #include #include + +#include "drv_uart.h" + +#include "fsl_common.h" #include "board.h" -#include "pin_mux.h" +#if defined(SDK_NETC_USED) && SDK_NETC_USED + #include "fsl_netc_soc.h" + #include "fsl_netc_ierb.h" +#endif /* SDK_NETC_USED */ #include "fsl_iomuxc.h" -#include "fsl_rgpio.h" #include "fsl_cache.h" #include "fsl_ele_base_api.h" #include "fsl_dcdc.h" #include "fsl_trdc.h" #include "fsl_rgpio.h" +#ifdef BSP_USING_ETH +#include "fsl_netc_endpoint.h" +#include "fsl_netc_switch.h" +#include "fsl_netc_mdio.h" +#endif + +#ifdef BSP_USE_MULTICORE +#include "mcmgr.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority @@ -26,9 +45,22 @@ #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ + 0 bits for subpriority */ + +#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +AT_QUICKACCESS_SECTION_DATA(volatile uint32_t g_systickCounter); + +/******************************************************************************* + * Code + ******************************************************************************/ /* MPU configuration. */ +#if __CORTEX_M == 7 void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -232,6 +264,485 @@ void BOARD_ConfigMPU(void) L1CACHE_EnableDCache(); L1CACHE_EnableICache(); } +#elif __CORTEX_M == 33 +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + uint32_t i; + uint8_t attr; + + /* Disable code & system cache */ + XCACHE_DisableCache(XCACHE_PC); + XCACHE_DisableCache(XCACHE_PS); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: device. */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: non cacheable. */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: non transient, write through, read allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: non transient, write back, read/write allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* NOTE: + * 1. When memory regions overlap, the processor generates a fault if a core access hits the overlapping regions + */ + +#if defined(USE_HYPERRAM) + /* + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + */ + + /* Region 0 (FlexSPI2, Hyperram): [0x04000000, 0x047FFFFFF, 8M] */ +#if !defined(CACHE_MODE_WRITE_THROUGH) + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x04000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x047FFFFF, 3U)); +#endif +#endif + + /* Region 1 (Code TCM): [0x0FFE0000, 0x0FFFFFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 2 */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x0FFE0000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x0FFFFFFF, 2U)); + + /* Region 2 (System TCM): [0x20000000, 0x2001FFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(2U, ARM_MPU_RBAR(0x20000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2001FFFF, 3U)); + + /* Region 3 (CM7 I/D TCM): [0x203C0000, 0x2043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(3U, ARM_MPU_RBAR(0x203C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x2043FFFF, 1U)); + + /* Region 4 (CM7 I/D TCM): [0x303C0000, 0x3043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(4U, ARM_MPU_RBAR(0x303C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x3043FFFF, 1U)); + + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write back, write/read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 3U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 3U)); + */ + + /* Region 5 (FlexSPI1, Nor Flash): [0x28000000, 0x28FFFFFF, 16M] */ + /* non-shareable, read only in privilege and non-privileged, executable. Attr 2 */ + ARM_MPU_SetRegion(5U, ARM_MPU_RBAR(0x28000000, ARM_MPU_SH_NON, 1U, 1U, 0U), ARM_MPU_RLAR(0x28FFFFFF, 2U)); + + /* Region 6 (Peripherals): [0x40000000, 0x7FFFFFFF, 1G ] */ + /* non-shareable, read/write in privilege and non-privileged, execute-never. Attr 0 (device). */ + ARM_MPU_SetRegion(6U, ARM_MPU_RBAR(0x40000000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x7FFFFFFF, 0U)); + +#if defined(USE_SDRAM) + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 7 (SEMC, SDRAM): [0x80000000, 0x81FFFFFF, 32M] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(7U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x81FFFFFF, 3U)); + */ +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32 */ + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 8: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(nonCacheStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(nonCacheStart + nonCacheSize - 1, 1U)); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 9: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(rpmsgShmemStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(rpmsgShmemStart + rpmsgShmemSize - 1, 1U)); + } +#endif + +#if defined(CACHE_MODE_WRITE_THROUGH) + /* + * CM33 MPU settings can't overlay, so the common MPU settings for CM33 can't handle the + * CACHE_MODE_WRITE_THROUGH, otherwise it may conflict(overlay) with NCACHE and SHMEN. + * + * Assume the NCACHE/SHMEM region are located in OCRAM. + * This is a workaround that disable the cache of OCRAM1 and OCRAM 2, based on current link settings. + * It impacts the performance, application may fine tune MPU according to its own linkage. + */ + + // Region 8 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 1U)); + + // Region 9 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 1U)); +#endif + + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 2U)); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable code & system cache */ + XCACHE_EnableCache(XCACHE_PS); + XCACHE_EnableCache(XCACHE_PC); +} +#endif + +void BOARD_DeinitFlash(FLEXSPI_Type *base) +{ +#if (__CORTEX_M == 7) + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 1U) /* disabled if enabled */ + { + /* Enable the to push all modified lines. */ + XCACHE_PC->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0x00U) + { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + XCACHE_PC->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); + XCACHE_PC->CCR &= ~XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* Wait until FLEXSPI is not busy */ + while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + /* Disable module during the reset procedure */ + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; +} + +void BOARD_InitFlash(FLEXSPI_Type *base) +{ + uint32_t status; + uint32_t lastStatus; + uint32_t retry; + + /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is + * recommended. */ + base->DLLCR[0] = 0x1U; + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } + + /* Need to wait DLL locked if DLL enabled */ + if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) + { + lastStatus = base->STS2; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + /* Wait slave delay line locked and slave reference delay line locked. */ + do + { + status = base->STS2; + if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) == + (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) + { + /* Locked */ + retry = 100; + break; + } + else if (status == lastStatus) + { + /* Same delay cell number in calibration */ + retry--; + } + else + { + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + lastStatus = status; + } + } + while (retry > 0); + /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ + for (; retry > 0U; retry--) + { + __NOP(); + } + } + +#if (__CORTEX_M == 7) + SCB_EnableICache(); +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) + { + /* set command to invalidate all ways and write GO bit to initiate command */ + XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; + XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; + /* Wait until the command completes */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) + { + } + /* Enable cache */ + XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif +} + +/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */ +void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ + clock_root_t root; + clock_lpcg_t lpcg; + + if (base == FLEXSPI1) + { + root = kCLOCK_Root_Flexspi1; + lpcg = kCLOCK_Flexspi1; + } + else if (base == FLEXSPI2) + { + root = kCLOCK_Root_Flexspi2; + lpcg = kCLOCK_Flexspi2; + } + else + { + return; + } + + if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) || + ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) + { + /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the + FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock + frequency. */ + BOARD_DeinitFlash(base); + + /* Disable clock before changing clock source */ + CCM->LPCG[lpcg].DIRECT &= ~CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) + { + } + + /* Update flexspi clock. */ + CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(src) | CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1); + __DSB(); + __ISB(); + (void)CCM->CLOCK_ROOT[root].CONTROL; + + /* Enable FLEXSPI clock again */ + CCM->LPCG[lpcg].DIRECT |= CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (!(CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK)) + { + } + + BOARD_InitFlash(base); + } +} + +/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock) + * updating in case XIP(execute code on FLEXSPI memory.) */ +void BOARD_FlexspiClockSafeConfig(void) +{ + /* Move FLEXSPI clock source to OSC_RC_24M to avoid instruction/data fetch issue in XIP when updating PLL. */ + BOARD_SetFlexspiClock(FLEXSPI1, 0U, 1U); +} + +/* This function is used to set EdgeLock clock via safe method */ +void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ + if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) || + (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) + { + status_t sts; + uint32_t ele_clk_mhz; + + clock_root_config_t rootCfg = + { + .div = div, + .mux = mux, + .clockOff = false, + }; + + do + { + sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA); + } + while (sts != kStatus_Success); + + CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg); + + ele_clk_mhz = CLOCK_GetRootClockFreq(kCLOCK_Root_Edgelock) / 1000000UL; + do + { + sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0); + } + while (sts != kStatus_Success); + } +} + +/* This function is used to set DCDC output voltage via safe method */ +void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ + /* + * When GDET is enabled, it is required to work with special ELE FW, which + * support ELE API VOLTAGE_CHANGE_START and VOLTAGE_CHANGE_FINISH, and + * DCDC voltage setting must be guarded with VOLTAGE_CHANGE_START and + * VOLTAGE_CHANGE_FINISH. + * + * For those ELE FW or ELE ROM, which doesn't support ELE API VOLTAGE_CHANGE_START + * and VOLTAGE_CHANGE_FINISH, there is no side effect to send such API command, + * since ELE just responde with ERROR and ingore the API command. + */ + ELE_BaseAPI_VoltageChangeStart(MU_RT_S3MUA); + + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, (dcdc_core_slice_t)core, (dcdc_1P0_target_vol_t)targetVoltage); + + ELE_BaseAPI_VoltageChangeFinish(MU_RT_S3MUA); +} + +#if defined(SDK_NETC_USED) && SDK_NETC_USED +void BOARD_NETC_Init(void) +{ + /* EP and Switch port 0 use RMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkEp0, kNETC_RmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort0, kNETC_RmiiMode); + + /* Switch port 1~3 use RGMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort1, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort2, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort3, kNETC_RgmiiMode); + + /* Output reference clock for RMII interface. */ + NETC_SocSetRmiiRefClk(kNETC_SocLinkEp0, true); + NETC_SocSetRmiiRefClk(kNETC_SocLinkSwitchPort0, true); + + /* Unlock the IERB. It will warm reset whole NETC. */ + if (NETC_IERBUnlock() == kStatus_Success) + { + while (!NETC_IERBIsUnlockOver()) + { + } + } + + /* Set the access attribute, otherwise MSIX access will be blocked. */ + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR &= ~(7U << 27); + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR |= (1U << 27); + + /* Set PHY address in IERB to use MAC port MDIO, otherwise the access will be blocked. */ + NETC_SocSetLinkAddr(kNETC_SocLinkEp0, BOARD_EP0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort0, BOARD_SWT_PORT0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort1, BOARD_SWT_PORT1_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort2, BOARD_SWT_PORT2_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort3, BOARD_SWT_PORT3_PHY_ADDR); + + /* Lock the IERB. */ + assert(NETC_IERBLock() == kStatus_Success); + while (!NETC_IERBIsLockOver()) + { + } +} +#endif /* SDK_NETC_USED */ void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) { @@ -705,7 +1216,6 @@ void BOARD_CommonSetting(void) BOARD_GrantTRDCFullPermissions(); } -/* This is the timer interrupt service routine. */ void SysTick_Handler(void) { /* enter interrupt */ @@ -717,51 +1227,51 @@ void SysTick_Handler(void) rt_interrupt_leave(); } -void imxrt_uart_pins_init(void) +#ifdef BSP_USE_MULTICORE +/*! + * @brief Application-specific implementation of the SystemInitHook() weak function. + */ +void SystemInitHook(void) { -#ifdef BSP_USING_LPUART1 - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ + /* Initialize MCMGR - low level multicore management library. Call this + function as close to the reset entry as possible to allow CoreUp event + triggering. The SystemInitHook() weak function overloading is used in this + application. */ + (void)MCMGR_EarlyInit(); +} #endif + +#ifdef BSP_USING_ETH +void PHY_Reset(void) +{ + /* Reset PHY8201 for ETH4. Reset 10ms, wait 72ms. */ + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 0); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 0); + SDK_DelayAtLeastUs(10000, CLOCK_GetFreq(kCLOCK_CpuClk)); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 1); + RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 1); + SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); } +#endif void rt_hw_board_init() { BOARD_CommonSetting(); BOARD_ConfigMPU(); - BOARD_InitPins(); + BOARD_InitBootPins(); BOARD_BootClockRUN(); NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); -#ifdef BSP_USING_LPUART - imxrt_uart_pins_init(); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif + /*init uart device*/ + rt_hw_uart_init(); #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); @@ -770,5 +1280,15 @@ void rt_hw_board_init() #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif + +#ifdef RT_USING_HEAP + rt_kprintf("SystemCoreClock: %d Hz\n", SystemCoreClock); + rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n", + HEAP_BEGIN, HEAP_END, + (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); + + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h index a69a6880caec..e8833eed44e5 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h @@ -1,12 +1,12 @@ /* - * Copyright 2021-2025 NXP + * Copyright 2021-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __BOARD_H__ -#define __BOARD_H__ +#ifndef _BOARD_H_ +#define _BOARD_H_ #include "clock_config.h" #include "pin_mux.h" @@ -14,6 +14,156 @@ #include "fsl_rgpio.h" #include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1180-EVK" +#ifndef DEBUG_CONSOLE_UART_INDEX +#define DEBUG_CONSOLE_UART_INDEX 1 +#endif + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#ifndef BOARD_DEBUG_UART_CLK_ROOT +#define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102 +#endif +#ifndef BOARD_DEBUG_UART_BASEADDR +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#endif +#ifndef BOARD_DEBUG_UART_INSTANCE +#define BOARD_DEBUG_UART_INSTANCE 1U +#endif +#ifndef BOARD_UART_IRQ +#define BOARD_UART_IRQ LPUART1_IRQn +#endif +#ifndef BOARD_UART_IRQ_HANDLER +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler +#endif +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif + +/* Definitions for eRPC MU transport layer */ +#if defined(FSL_FEATURE_MU_SIDE_A) +#define MU_BASE MU1_MUA +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#if defined(FSL_FEATURE_MU_SIDE_B) +#define MU_BASE MU1_MUB +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#define MU_IRQ_PRIORITY (2) + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (1U) +#define LOGIC_LED_OFF (0U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO RGPIO4 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (27U) +#endif + +#define USER_LED_INIT(output) \ + RGPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->PDDR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_OFF() \ + RGPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_ON() RGPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!*/ #if defined(__ARMCC_VERSION) extern int Image$$ARM_LIB_HEAP$$ZI$$Base; extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; @@ -30,10 +180,10 @@ extern int __HeapLimit; #define HEAP_END ((void *)&__HeapLimit) #endif -/*! @brief The board flash size */ -#define BOARD_FLASH_SIZE (0x1000000U) - void rt_hw_board_init(void); -#endif +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h index 17bd2f87acf0..cf59d84e602e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -61,18 +61,21 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 4096 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 /* kservice options */ @@ -100,10 +103,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart12" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -121,12 +124,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 4096 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -145,6 +148,9 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 @@ -159,8 +165,8 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ @@ -295,10 +301,6 @@ /* end of Kendryte SDK */ -/* MM32 HAL & SDK Drivers */ - -/* end of MM32 HAL & SDK Drivers */ - /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -332,10 +334,6 @@ /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ - -/* NOVOSNS Drivers */ - -/* end of NOVOSNS Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -425,9 +423,8 @@ /* On-chip Peripheral Drivers */ -#define BSP_USING_GPIO #define BSP_USING_LPUART -#define BSP_USING_LPUART1 +#define BSP_USING_LPUART12 /* end of On-chip Peripheral Drivers */ /* Onboard Peripheral Drivers */ @@ -436,6 +433,7 @@ /* Board extended module Drivers */ +#define BSP_LINKER_SCRIPT_RAM /* end of Hardware Drivers Config */ #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py index 41010bfddc44..a8a5831225eb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py @@ -20,7 +20,7 @@ PLATFORM = 'gcc' EXEC_PATH = r'C:\Users\XXYYZZ' elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' + PLATFORM = 'armclang' EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iccarm' @@ -29,8 +29,42 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') -#BUILD = 'debug' -BUILD = 'release' +BUILD = 'debug' +# BUILD = 'release' + +# Read linker script selection from rtconfig.h (set by Kconfig BSP_LINKER_SCRIPT_* choice). +# Supported types: RAM, HYPERRAM, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM +# Default to RAM when no match is found. +_LINKER_SCRIPT_TYPE = 'RAM' +_rtconfig_h = os.path.join(os.path.dirname(__file__), 'rtconfig.h') +if os.path.exists(_rtconfig_h): + with open(_rtconfig_h, 'r') as _f: + for _line in _f: + _s = _line.strip() + if _s.startswith('//'): + continue + # Check the most specific name first to avoid false matches. + if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM'): + _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR_HYPERRAM' + break + if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR'): + _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR' + break + if _s.startswith('#define BSP_LINKER_SCRIPT_HYPERRAM'): + _LINKER_SCRIPT_TYPE = 'HYPERRAM' + break + if _s.startswith('#define BSP_LINKER_SCRIPT_RAM'): + _LINKER_SCRIPT_TYPE = 'RAM' + break + +# Base filename (without extension) for the selected linker script. +_LINKER_SCRIPT_BASE = { + 'RAM': 'MIMXRT1189xxxxx_cm7_ram', + 'HYPERRAM': 'MIMXRT1189xxxxx_cm7_hyperram', + 'FLEXSPI_NOR': 'MIMXRT1189xxxxx_cm7_flexspi_nor', + 'FLEXSPI_NOR_HYPERRAM': 'MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram', +}[_LINKER_SCRIPT_TYPE] + if PLATFORM == 'gcc': PREFIX = 'arm-none-eabi-' @@ -48,7 +82,10 @@ DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link_ram.lds' + + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.ld' + + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ' + LINKER_SCRIPT CPATH = '' LPATH = '' @@ -65,7 +102,7 @@ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - # module setting + # module setting CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' @@ -84,9 +121,12 @@ DEVICE = ' --cpu ' + CPU + '.fp.sp' CFLAGS = DEVICE + ' --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link_ram.scf"' - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.scf' + + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "' + LINKER_SCRIPT + '"' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' CFLAGS += ' --diag_suppress=66,1296,186,6314' CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' @@ -125,9 +165,13 @@ AFLAGS = DEVICE + ' --apcs=interwork ' AFLAGS += ' -x assembler-with-cpp' AFLAGS += ' -Wa,-mimplicit-it=thumb' + + # armlink --scatter accepts the file without extension; append .scf explicitly. + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.scf' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board/linker_scripts/link_ram" ' + LFLAGS += r' --strict --scatter "' + LINKER_SCRIPT + '" ' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' @@ -138,7 +182,7 @@ AFLAGS += ' -g' else: CFLAGS += ' -O2' - + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' @@ -185,7 +229,10 @@ else: CFLAGS += ' -Oh' - LFLAGS = ' --config "board/linker_scripts/link_ram.icf"' + LINKER_SCRIPT = 'board/linker_scripts/' + _LINKER_SCRIPT_BASE + '.icf' + + LFLAGS = ' --config "' + LINKER_SCRIPT + '"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' @@ -195,9 +242,43 @@ EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' +# Map from linker script type to the matching Keil target name. +_LINKER_SCRIPT_TO_KEIL_TARGET = { + 'RAM': 'rtthread_ram', + 'HYPERRAM': 'rtthread_hyperram', + 'FLEXSPI_NOR': 'rtthread_flexspi_nor', + 'FLEXSPI_NOR_HYPERRAM': 'rtthread_flexspi_nor_hyperram', +} + +def update_keil_active_target(uvoptx_path='project.uvoptx'): + """Set in project.uvoptx to match the selected linker script.""" + import xml.etree.ElementTree as etree + + active = _LINKER_SCRIPT_TO_KEIL_TARGET.get(_LINKER_SCRIPT_TYPE, 'rtthread_ram') + + if not os.path.exists(uvoptx_path): + return + + tree = etree.parse(uvoptx_path) + root = tree.getroot() + + for tgt in tree.findall('Target'): + tname = tgt.find('TargetName') + is_current = tgt.find('TargetOption/OPTFL/IsCurrentTarget') + if tname is not None and is_current is not None: + is_current.text = '1' if tname.text == active else '0' + + out = open(uvoptx_path, 'w') + out.write('\n') + out.write(etree.tostring(root, encoding='utf-8').decode()) + out.close() + + print('Keil active target set to: ' + active) + def dist_handle(BSP_ROOT, dist_dir): import sys cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(os.path.dirname(BSP_ROOT)), 'tools')) + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) from sdk_dist import dist_do_building dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd index f728737cac82..820c6102c6e8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd @@ -2,7 +2,7 @@ 4 - rtthread + rtthread_ram ARM @@ -32,11 +32,11 @@ + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + IJET_ID 2 - 9 + 10 1 1 + @@ -948,12 +972,12 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1580,11 +1608,4927 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + rtthread_hyperram + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + rtthread_flexspi_nor + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + rtthread_flexspi_nor_hyperram + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin 0 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp index d283c339789c..16894708157c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp @@ -2,7 +2,7 @@ 4 - rtthread + rtthread_ram ARM @@ -16,19 +16,19 @@ 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + rtthread_hyperram + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + rtthread_flexspi_nor + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + rtthread_flexspi_nor_hyperram + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + true + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt index 0a51a951d6d8..46fd34703f19 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt @@ -17,1370 +17,1369 @@ 1 600 - 0 - 2 + 1 + 6 0 1 100 rtthread/C-STAT - 2.7.5 + 2.7.2 - + - - - - - - + + + + + + - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - + - - + + - + - + - + - - - - - - - - - - - + + + + + + + + + + + - - - - - - - - + + + + + + + + - + - + - + - - - - - - + + + + + + - + - - - + + + - - - + + + - + - - + + - - - - - - + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - + - - - - - - - - + + + + + + + + - + - - + + - - - - - - + + + + + + - - + + - + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - + + + + + - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - - - - - - - + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + - + - - - - - - - - - - - - + + + + + + + + + + + + - + - + - - - + + + - - - - - - + + + + + + - - - - + + + + - - + + - - + + - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + - - - - + + + + - + - + - + - + - - - + + + - - - - + + + + - - - - - - - - + + + + + + + + - - - - - - - + + + + + + + - - - - + + + + - - + + - + - + - - - - - - - - + + + + + + + + - + - - - + + + - - - - + + + + - - + + - + - - - + + + - - - + + + - + - - + + - - - - - + + + + + - + - - + + - - - - + + + + - - + + - - - + + + - - - - - + + + + + - + - + - + - + - + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx index 58bc2c9befff..55a3a16d0e3b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx @@ -22,7 +22,7 @@ - rtthread + rtthread_ram 0x4 ARM-ADS @@ -113,7 +113,502 @@ - .\board\linker_scripts\evkmimxrt1180_ram_cm7.ini + .\evkmimxrt1180_ram_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + rtthread_hyperram + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_ram_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + rtthread_flexspi_nor + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_flexspi_nor_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + rtthread_flexspi_nor_hyperram + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_flexspi_nor_cm7.ini Segger\JL2CM3.dll diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx index 5e369a5e63eb..78acfd77ca4d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx @@ -7,10 +7,10 @@ - rtthread + rtthread_ram 0x4 ARM-ADS - 6150000::V6.15::ARMCLANG + 6220000::V6.22::ARMCLANG 1 @@ -138,7 +138,7 @@ 1 BIN\UL2CM3.DLL - + "" () @@ -371,7 +371,1132 @@ 0x00000000 0x10000000 - .\board\linker_scripts\link_ram.scf + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_ram.scf + + + --legacyalign + + 6439,6314 + + + + + + rtthread_hyperram + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20500000,0x040000) IROM(0x00000000,0x028000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20500000 + 0x40000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_hyperram.scf + + + --legacyalign + + 6439,6314 + + + + + + rtthread_flexspi_nor + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20500000,0x040000) IROM(0x00000000,0x028000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20500000 + 0x40000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_flexspi_nor.scf + + + --legacyalign + + 6439,6314 + + + + + + rtthread_flexspi_nor_hyperram + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20500000,0x040000) IROM(0x00000000,0x028000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20500000 + 0x40000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf --legacyalign @@ -392,7 +1517,7 @@ - <Project Info> + template 0 1 From c3ee28473727f2e75b659fc792b208fcdad2a188 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:04:02 +0800 Subject: [PATCH 05/31] Updated different link files of GCC, IAR and KEIL of CM7 project, for supporting multicore kick-off and different loading methods. --- .../MIMXRT1189xxxxx_cm7_flexspi_nor.icf | 153 +++++++ .../MIMXRT1189xxxxx_cm7_flexspi_nor.ld | 333 ++++++++++++++ .../MIMXRT1189xxxxx_cm7_flexspi_nor.scf | 181 ++++++++ ...MXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf | 157 +++++++ ...IMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld | 337 ++++++++++++++ ...MXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf | 194 ++++++++ ...nk_ram.icf => MIMXRT1189xxxxx_cm7_ram.icf} | 4 +- ...ink_ram.lds => MIMXRT1189xxxxx_cm7_ram.ld} | 5 +- ...nk_ram.scf => MIMXRT1189xxxxx_cm7_ram.scf} | 2 +- .../linker_scripts/evkmimxrt1180_ram_cm7.ini | 414 ------------------ 10 files changed, 1361 insertions(+), 419 deletions(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.scf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/{link_ram.icf => MIMXRT1189xxxxx_cm7_ram.icf} (96%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/{link_ram.lds => MIMXRT1189xxxxx_cm7_ram.ld} (99%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/{link_ram.scf => MIMXRT1189xxxxx_cm7_ram.scf} (99%) delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf new file mode 100644 index 000000000000..9741eea988aa --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf @@ -0,0 +1,153 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28800000; +define symbol m_flash_size = 0x00800000; + +/* General definition */ +define symbol app_image_offset = 0x00000000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_dtcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, + ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in QACODE_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld new file mode 100644 index 000000000000..e62c0c9bcf86 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld @@ -0,0 +1,333 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__use_shmem__ = 1; +__multicore__ = 1; + +/* Board memory map */ +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_flash_start = 0x28800000; +m_flash_size = 0x00800000; + +/* General definition */ +app_image_offset = 0x00000000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_dtcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = m_dtcm_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : m_ocram1_size; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_dtcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* RT-Thread FinSH symbol table */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + /* RT-Thread init table */ + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* RT-Thread init functions */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.scf new file mode 100644 index 000000000000..f9371f1d1e77 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.scf @@ -0,0 +1,181 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 + +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_flash_start 0x28800000 +#define m_flash_size 0x00800000 + +/* General definition */ +#define app_image_offset 0x00000000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x08000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size m_itcm_size - (m_qacode_start - m_itcm_start) +#define m_qadata_size 0 + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size m_dtcm_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 m_ocram1_size +#endif + +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_dtcm_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size +#define m_heap_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf new file mode 100644 index 000000000000..6867ac591025 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf @@ -0,0 +1,157 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28800000; +define symbol m_flash_size = 0x00800000; + +/* General definition */ +define symbol app_image_offset = 0x00000000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = 0x00600000; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +/* cache line size = 32 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, + ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in QACODE_region { block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld new file mode 100644 index 000000000000..c1a7b3648dd8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld @@ -0,0 +1,337 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__use_shmem__ = 1; +__multicore__ = 1; + +/* Board memory map */ +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_flash_start = 0x28800000; +m_flash_size = 0x00800000; + +/* General definition */ +app_image_offset = 0x00000000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_dtcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = 0x00600000; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : m_ocram1_size; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_hyperram_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* RT-Thread FinSH symbol table */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + /* RT-Thread init table */ + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* RT-Thread init functions */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(CacheLineData.init) + . = ALIGN(32); /* cache line size = 32 bytes */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + *(DataQuickAccess) /* quick access data section */ + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(CacheLineData) + . = ALIGN(32); /* cache line size = 32 bytes */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf new file mode 100644 index 000000000000..5f77343005db --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf @@ -0,0 +1,194 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 + +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_flash_start 0x28800000 +#define m_flash_size 0x00800000 + +/* General definition */ +#define app_image_offset 0x00000000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x08000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size m_itcm_size - (m_qacode_start - m_itcm_start) +#define m_qadata_size m_dtcm_size + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size 0x00600000 +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 m_ocram1_size +#endif + +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_hyperram_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size +#define m_heap_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + } + + ER_m_QuickAccessData m_qadata_start m_qadata_size + { + .ANY (DataQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + } + + ; cache line size is 32 bytes + RW_m_CacheLineData +0 ALIGN 32 (m_data_size-stack_size-ImageLength(RW_m_data))/32*32 + { + * (CacheLineData) + * (CacheLineData.init) + } + + ; auxiliary to make sure RW_m_CacheLineData end-aligned CACHE LINE SIZE + ; DO NOT insert any region between RW_m_CacheLineData and RW_m_CacheLineData_Aux + RW_m_CacheLineData_Aux +0 ALIGN 32 EMPTY 0 + { + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf similarity index 96% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf index 62301304f73a..232bebba5ef0 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf @@ -55,7 +55,7 @@ if (isdefinedsymbol(__stack_size__)) { if (isdefinedsymbol(__heap_size__)) { define symbol __size_heap__ = __heap_size__; } else { - define symbol __size_heap__ = 0x4000; + define symbol __size_heap__ = 0x8000; } define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); @@ -105,8 +105,6 @@ if (isdefinedsymbol(__use_shmem__)) { define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; } -define exported symbol __RTT_HEAP_END = m_ocram2_start + m_ocram2_size - 1; - /* Region definition */ define memory mem with size = 4G; define region TEXT_region = mem:[from m_text_start to m_text_end]; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.ld similarity index 99% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.ld index b07f7f41179d..32ed082e27ff 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.ld @@ -26,6 +26,9 @@ /* Entry Point */ ENTRY(Reset_Handler) +__use_shmem__ = 1; +__multicore__ = 1; + /* Board memory map */ m_itcm_start = 0x00000000; m_itcm_size = 0x00040000; @@ -51,7 +54,7 @@ m_qadata_start = m_dtcm_start; m_qadata_end = m_dtcm_start + m_dtcm_size - 1; m_ram_vector_table_start = m_itcm_start; m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; -m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; /* Target specific definition, code & data allocation */ m_code_size = m_itcm_size - vector_table_size; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.scf similarity index 99% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.scf index 8b6b98562ce2..b8ada8845e8d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.scf @@ -60,7 +60,7 @@ #if defined(__heap_size__) #define heap_size __heap_size__ #else - #define heap_size 0x04000 + #define heap_size 0x08000 #endif /* Target specific definition, code & data allocation */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini deleted file mode 100644 index d21f38d50c88..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Copyright 2023-2024 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -FUNC void _FLEXSPI1_ModuleReset(void) -{ - unsigned int reg; - - reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = _RDWORD(0x425E0000); - _WDWORD(0x425E0000, (reg | 0x1)); - do - { - reg = _RDWORD(0x425E0000); - } while ((reg & 0x1) != 0); - } -} - -FUNC void _FLEXSPI1_WaitBusIdle(void) -{ - unsigned int reg; - reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = _RDWORD(0x425E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -FUNC void _FLEXSPI1_ClockInit(void) -{ - _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 - _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 -} - -FUNC void _FLEXSPI1_SetPinForQuadMode(void) { - // Set 4 Pin Mode - // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS - _WDWORD(0x42A1023C, 0x17); - _WDWORD(0x42A10544, 0x1); - // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK - _WDWORD(0x42A10240, 0x17); - // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B - _WDWORD(0x42A10244, 0x17); - // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 - _WDWORD(0x42A10248, 0x17); - // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 - _WDWORD(0x42A1024C, 0x17); - // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 - _WDWORD(0x42A10250, 0x17); - // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 - _WDWORD(0x42A10254, 0x17); -} - -FUNC void _FLEXSPI1_ModuleInit(void) { - - unsigned int reg; - reg = _RDWORD(0x425E0000); - _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); - - //FLEXSPI1->MCR0 = 0xFFFF8010; - _WDWORD(0x425E0000, 0xFFFF8010); - //FLEXSPI1->MCR2 = 0x200001F7; - _WDWORD(0x425E0008, 0x200001F7); - //FLEXSPI1->AHBCR = 0x78; - _WDWORD(0x425E000C, 0x78); - - //FLEXSPI1->FLSHCR0[0] = 0x00004000; - _WDWORD(0x425E0060, 0x00004000); - - //FLEXSPI1->FLSHCR4 = 0xC3; - _WDWORD(0x425E0094, 0xC3); - //FLEXSPI1->IPRXFCR = 0x1C; - _WDWORD(0x425E00B8, 0x1C); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - _WDWORD(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x02; - _WDWORD(0x425E001C, 0x02); - - //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad - _WDWORD(0x425E0200, 0x0A1804EB); - //FLEXSPI1->LUT[1] = 0x26043206; - _WDWORD(0x425E0204, 0x26043206); - //FLEXSPI1->LUT[2] = 0x00000000; - _WDWORD(0x425E0208, 0x00000000); - //FLEXSPI1->LUT[3] = 0x00000000; - _WDWORD(0x425E020C, 0x00000000); - - //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable - _WDWORD(0x425E0210, 0x00000406); - //FLEXSPI1->LUT[5] = 0x00000000; - _WDWORD(0x425E0214, 0x00000000); - //FLEXSPI1->LUT[6] = 0x00000000; - _WDWORD(0x425E0218, 0x00000000); - //FLEXSPI1->LUT[7] = 0x00000000; - _WDWORD(0x425E021C, 0x00000000); - - //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 - _WDWORD(0x425E0220, 0x20040401); - //FLEXSPI1->LUT[9] = 0x00000000; - _WDWORD(0x425E0224, 0x00000000); - //FLEXSPI1->LUT[10] = 0x00000000; - _WDWORD(0x425E0228, 0x00000000); - //FLEXSPI1->LUT[11] = 0x00000000; - _WDWORD(0x425E022C, 0x00000000); - - //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 - _WDWORD(0x425E0230, 0x24040405); - //FLEXSPI1->LUT[13] = 0x00000000; - _WDWORD(0x425E0234, 0x00000000); - //FLEXSPI1->LUT[14] = 0x00000000; - _WDWORD(0x425E0238, 0x00000000); - //FLEXSPI1->LUT[15] = 0x00000000; - _WDWORD(0x425E023C, 0x00000000); - - //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable - _WDWORD(0x425E0240, 0x00000404); - //FLEXSPI1->LUT[17] = 0x00000000; - _WDWORD(0x425E0244, 0x00000000); - //FLEXSPI1->LUT[18] = 0x00000000; - _WDWORD(0x425E0248, 0x00000000); - //FLEXSPI1->LUT[19] = 0x00000000; - _WDWORD(0x425E024C, 0x00000000); - - //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 - _WDWORD(0x425E0250, 0x20040431); - //FLEXSPI1->LUT[21] = 0x00000000; - _WDWORD(0x425E0254, 0x00000000); - //FLEXSPI1->LUT[22] = 0x00000000; - _WDWORD(0x425E0258, 0x00000000); - //FLEXSPI1->LUT[23] = 0x00000000; - _WDWORD(0x425E025C, 0x00000000); - - //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 - _WDWORD(0x425E0260, 0x24040435); - //FLEXSPI1->LUT[25] = 0x00000000; - _WDWORD(0x425E0264, 0x00000000); - //FLEXSPI1->LUT[26] = 0x00000000; - _WDWORD(0x425E0268, 0x00000000); - //FLEXSPI1->LUT[27] = 0x00000000; - _WDWORD(0x425E026C, 0x00000000); - - //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile - _WDWORD(0x425E0270, 0x00000450); - //FLEXSPI1->LUT[29] = 0x00000000; - _WDWORD(0x425E0274, 0x00000000); - //FLEXSPI1->LUT[30] = 0x00000000; - _WDWORD(0x425E0278, 0x00000000); - //FLEXSPI1->LUT[31] = 0x00000000; - _WDWORD(0x425E027C, 0x00000000); - - //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; - _WDWORD(0x425E0018, 0x5AF05AF0); - //FLEXSPI1->LUTCR = 0x01; - _WDWORD(0x425E001C, 0x01); -} - -FUNC void _FLEXSPI2_ModuleReset(void) -{ - unsigned int reg; - - reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - reg = _RDWORD(0x445E0000); - _WDWORD(0x445E0000, (reg | 0x1)); - do - { - reg = _RDWORD(0x445E0000); - } while ((reg & 0x1) != 0); - } -} - -FUNC void _FLEXSPI2_WaitBusIdle(void) -{ - unsigned int reg; - - reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 - if( (reg & 0x02) == 0) // Module Enabled - { - do - { - reg = _RDWORD(0x445E00E0); - } while ((reg & 0x3) != 0x3); - } -} - -FUNC void _FlexSPI2_SetPinForOctalMode(void) -{ - // Config IOMUX for FlexSPI2 - _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B - _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS - _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK - - //The input daisy!! - _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS - _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK - - // PAD ctrl - _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 - _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 - _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 - _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 - _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 - _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 - _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 - _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 - _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B - _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS - _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK -} - -FUNC void _FLEXSPI2_ClockInit(void) -{ - _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 - - // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 - _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 -} - -FUNC void _FLEXSPI2_ModuleInit(void) -{ - // Config FlexSPI2 Registers - - unsigned int reg; - reg = _RDWORD(0x445E0000); - _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); - - _FLEXSPI2_ModuleReset(); - - _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 - _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 - _WDWORD(0x445E0008, 0x200001F7); // MCR2 - _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable - _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 - _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 - _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 - _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 - _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 - _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 - _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 - _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 - _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR - _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR - - _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 - _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 - _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 - _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 - _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 - _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E00C0, 0x00000079); // DLLCRA - _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 - - do - { - reg = _RDWORD(0x445E00E8); - } while (0x3 != (reg & 0x3)); - _Sleep_(1); - // __delay(100);//100us - - _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 - _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 - _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 - _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 - - _FLEXSPI2_WaitBusIdle(); - - _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY - _WDWORD(0x445E001C, 0x00000002); // LUTCR - _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] - _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] - _WDWORD(0x445E0208, 0x0000A704); // LUT[2] - _WDWORD(0x445E020C, 0x00000000); // LUT[3] - _WDWORD(0x445E0210, 0x8B188720); // LUT[4] - _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] - _WDWORD(0x445E0218, 0x0000A304); // LUT[6] - _WDWORD(0x445E021C, 0x00000000); // LUT[7] - _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] - _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] - _WDWORD(0x445E0228, 0x0000A704); // LUT[10] - _WDWORD(0x445E022C, 0x00000000); // LUT[11] - _WDWORD(0x445E0230, 0x8B188760); // LUT[12] - _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] - _WDWORD(0x445E0238, 0x00000000); // LUT[14] - _WDWORD(0x445E023C, 0x00000000); // LUT[15] - _WDWORD(0x445E0240, 0x00000000); // LUT[16] - _WDWORD(0x445E0244, 0x00000000); // LUT[17] - _WDWORD(0x445E0248, 0x00000000); // LUT[18] - _WDWORD(0x445E024C, 0x00000000); // LUT[19] - _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY - _WDWORD(0x445E001C, 0x00000001); // LUTCR - - /* Restore hyperram CR0 register */ - _WDWORD(0x445E00A0, 0x00001000); // IPCR0 - _WDWORD(0x445E00A4, 0x00030002); // IPCR1 - _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR - _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 - _WDWORD(0x445E0014, 0x00000040); // INTR - _WDWORD(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = _RDWORD(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - _WDWORD(0x445E0014, 0x00000001); // INTR - - /* Restore hyperram CR1 register */ - _WDWORD(0x445E00A0, 0x00001002); // IPCR0 - _WDWORD(0x445E00A4, 0x00030002); // IPCR1 - _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR - _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 - _WDWORD(0x445E0014, 0x00000040); // INTR - _WDWORD(0x445E00B0, 0x00000001); // IPCMD - do - { - reg = _RDWORD(0x445E0014); // INTR - } while ((reg & 0x1) == 0x0); - _WDWORD(0x445E0014, 0x00000001); // INTR - - _FLEXSPI2_ModuleReset(); -} - -FUNC void Flash_Init(void) -{ - printf("***************************************************\r\n"); - printf("Init Flash\r\n"); - - _FLEXSPI1_WaitBusIdle(); - _FLEXSPI1_ModuleReset(); - - _FLEXSPI1_SetPinForQuadMode(); - _FLEXSPI1_ClockInit(); - _FLEXSPI1_ModuleInit(); - - printf("***************************************************\r\n"); -} - -FUNC void HyperRAM_Init(void) -{ - printf("***************************************************\r\n"); - printf("Init HyperRAM\r\n"); - - _FLEXSPI2_WaitBusIdle(); - _FLEXSPI2_ModuleReset(); - - _FlexSPI2_SetPinForOctalMode(); - _FLEXSPI2_ClockInit(); - _FLEXSPI2_ModuleInit(); - - printf("***************************************************\r\n"); -} - -FUNC void ClearNVIC(void) { - printf("***************************************************\r\n"); - printf("Clear NVIC\r\n"); - printf("***************************************************\r\n"); - memset(0xE000E180, 0x40, 0xFF); - memset(0xE000E280, 0x40, 0xFF); -} - -FUNC void Setup_PC_SP(void) -{ - SP = _RDWORD(0x00000000); // Setup Stack Pointer - PC = _RDWORD(0x00000004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register -} - -FUNC void Setup (void) { - ClearNVIC(); - // Flash_Init(); - HyperRAM_Init(); - Setup_PC_SP(); -} - -FUNC void OnResetExec (void) -{ - // executes upon RESET - Setup(); -} - -Setup(); From 404adf9dea5c5d7d0d4bb809c98585d26e9d3504 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:09:42 +0800 Subject: [PATCH 06/31] Modify LittleFS to use the last 1 MB of flash and update CM7 support for LittleFS on QSPI flash. --- .../cm33/board/ports/drv_flexspi_nor_flash.c | 12 +- .../cm33/board/ports/drv_flexspi_nor_flash.h | 8 +- .../cm33/board/ports/fal_cfg.h | 4 +- .../cm33/board/ports/fal_flash_port.c | 4 +- .../cm7/board/ports/drv_flexspi_nor_flash.c | 521 ++++++++++++++++++ .../cm7/board/ports/drv_flexspi_nor_flash.h | 59 ++ .../cm7/board/ports/fal_cfg.h | 37 ++ .../cm7/board/ports/fal_flash_port.c | 57 ++ .../cm7/board/ports/flexspi_octal_flash_ops.c | 2 +- .../cm7/board/ports/flexspi_port.h | 66 ++- 10 files changed, 754 insertions(+), 16 deletions(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c index 2132bd4d26fc..60f31b39fd74 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c @@ -104,7 +104,7 @@ rt_inline int _addr_safe(rt_uint32_t offset, rt_size_t size) /* * _nor_write_enable - send WREN command (SDK: flexspi_nor_write_enable) */ -QSPI_RAM_CODE static status_t _nor_write_enable(rt_uint32_t base_addr) +static status_t _nor_write_enable(rt_uint32_t base_addr) { flexspi_transfer_t xfer; @@ -123,7 +123,7 @@ QSPI_RAM_CODE static status_t _nor_write_enable(rt_uint32_t base_addr) * W25Q128JWSIQ SR1[0] = WIP (Write In Progress) * FLASH_BUSY_STATUS_POL = 1: bit set means busy */ -QSPI_RAM_CODE static status_t _nor_wait_busy(void) +static status_t _nor_wait_busy(void) { rt_uint32_t read_val = 0; rt_uint32_t timeout = 0; @@ -172,7 +172,7 @@ QSPI_RAM_CODE static status_t _nor_wait_busy(void) * * @addr: Flash internal offset (not AHB address) */ -QSPI_RAM_CODE static status_t _nor_erase_sector(rt_uint32_t addr) +static status_t _nor_erase_sector(rt_uint32_t addr) { rt_base_t level; status_t status; @@ -218,7 +218,7 @@ QSPI_RAM_CODE static status_t _nor_erase_sector(rt_uint32_t addr) * Uses PAGEPROGRAM_QUAD (0x32, 1-1-4 mode) for faster write speed, * consistent with the SDK example. src must be a 4-byte aligned SRAM buffer. */ -QSPI_RAM_CODE static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) +static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) { rt_base_t level; status_t status; @@ -407,7 +407,7 @@ void *rt_qspi_flash_mmap(rt_uint32_t offset, rt_size_t size) * * Data path: src -> s_write_buf (SRAM) -> Flash */ -QSPI_RAM_CODE int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size) +int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size) { rt_size_t written = 0; status_t status; @@ -473,7 +473,7 @@ QSPI_RAM_CODE int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, * offset and size must be sector-aligned (4KB). * Only the filesystem partition is allowed to be erased (_addr_safe guard). */ -QSPI_RAM_CODE int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) +int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) { rt_uint32_t addr; rt_uint32_t addr_end; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h index aceb7680a618..51b51a3c0836 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h @@ -26,11 +26,11 @@ /* * Partition Plan (Total 16MB): - * 0x00000000 ~ 0x007FFFFF: Application Code Area (8MB, limited by Scatter) - * 0x00800000 ~ 0x00FFFFFF: File System Area (8MB, LittleFS) + * 0x00000000 ~ 0x00EFFFFF: Application Code Area (15MB, limited by Scatter) + * 0x00F00000 ~ 0x00FFFFFF: File System Area (1MB, LittleFS) */ -#define QSPI_FS_OFFSET 0x00800000U -#define QSPI_FS_SIZE 0x00800000U +#define QSPI_FS_OFFSET 0x00F00000U +#define QSPI_FS_SIZE 0x00100000U /* ============================================================ * RAM Code Section Attributes diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h index 757254283048..8b452d177368 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h @@ -28,8 +28,8 @@ extern const struct fal_flash_dev imxrt1180_nor_flash; /* partition table */ #define FAL_PART_TABLE \ { \ - {FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 8*1024*1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 8*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15*1024*1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15*1024*1024, 1*1024*1024, 0}, \ } #endif /* FAL_PART_HAS_TABLE_CFG */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c index 6e31c51c9184..ae1c3c41338a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c @@ -34,12 +34,12 @@ static int _fal_read(long offset, rt_uint8_t *buf, size_t size) return rt_qspi_flash_read((rt_uint32_t)offset, buf, size); } -QSPI_RAM_CODE static int _fal_write(long offset, const rt_uint8_t *buf, size_t size) +static int _fal_write(long offset, const rt_uint8_t *buf, size_t size) { return rt_qspi_flash_write((rt_uint32_t)offset, buf, size); } -QSPI_RAM_CODE static int _fal_erase(long offset, size_t size) +static int _fal_erase(long offset, size_t size) { return rt_qspi_flash_erase((rt_uint32_t)offset, size); } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c new file mode 100644 index 000000000000..60f31b39fd74 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CoreBoxer support IMXRT1180-EVK + */ + +#include +#include + +#include "drv_flexspi_nor_flash.h" +#include "drv_flexspi.h" +#include "flexspi_port.h" +#include "fsl_flexspi.h" +#include "fsl_cache.h" + +/* + * Logging configuration + */ +#define LOG_TAG "drv.flash" +#define LOG_LVL LOG_LVL_INFO +#include + +/* + * FLASH_BUSY_STATUS_POL = 1 : SR[bit] = 1 means busy + * FLASH_BUSY_STATUS_OFFSET = 0 : WIP bit is SR[0] + * FLASH_QUAD_ENABLE = 0x40 : write to SR to enable Quad mode + */ +#define FLASH_QUAD_ENABLE_VAL 0x40U + +/* WIP polling upper limit to prevent infinite loop on Flash failure */ +#define WIP_TIMEOUT_COUNT 2000000UL + +/* + * Internal write buffer (must reside in SRAM) + * + * Reason: src data may come from const sections in XIP Flash. + * During FLEXSPI IP write commands, AHB access is suspended. + * If CPU tries to read src via AHB at that moment, bus hang or + * corrupted data may occur. Pre-copying to SRAM avoids this. + */ +static uint8_t SDK_ALIGN(s_write_buf[QSPI_PAGE_SIZE], 4); + +/* Internal state */ +static imxrt_flexspi_handle_t *s_handle = RT_NULL; +static struct rt_mutex s_mutex; +static int s_inited = 0; + +/* + * _range_valid - check whether [offset, offset+size) is within Flash + */ +rt_inline int _range_valid(rt_uint32_t offset, rt_size_t size) +{ + if (size == 0U) + { + return 1; + } + if ((offset + (rt_uint32_t)size) < offset) + { + return 0; /* overflow */ + } + if ((offset + (rt_uint32_t)size) > QSPI_FLASH_SIZE) + { + return 0; + } + return 1; +} + +/* + * _addr_safe - check whether [offset, offset+size) is within the FS partition + */ +rt_inline int _addr_safe(rt_uint32_t offset, rt_size_t size) +{ + if (size == 0U) + { + return 1; + } + if ((offset + (rt_uint32_t)size) < offset) + { + return 0; + } + if (offset < QSPI_FS_OFFSET) + { + return 0; + } + if ((offset + (rt_uint32_t)size) > (QSPI_FS_OFFSET + QSPI_FS_SIZE)) + { + return 0; + } + return 1; +} + +/* + * Low-level NOR Flash operations (mapped from SDK flexspi_nor_flash_ops.c) + * + * All functions are marked QSPI_RAM_CODE (placed in ITCM) because they are + * called while a FLEXSPI IP command is in progress, during which AHB access + * is suspended and the CPU must fetch instructions from ITCM. + */ + +/* + * _nor_write_enable - send WREN command (SDK: flexspi_nor_write_enable) + */ +static status_t _nor_write_enable(rt_uint32_t base_addr) +{ + flexspi_transfer_t xfer; + + xfer.deviceAddress = base_addr; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + return FLEXSPI_TransferBlocking(s_handle->base, &xfer); +} + +/* + * _nor_wait_busy - poll WIP bit until Flash is idle (SDK: flexspi_nor_wait_bus_busy) + * + * W25Q128JWSIQ SR1[0] = WIP (Write In Progress) + * FLASH_BUSY_STATUS_POL = 1: bit set means busy + */ +static status_t _nor_wait_busy(void) +{ + rt_uint32_t read_val = 0; + rt_uint32_t timeout = 0; + status_t status; + rt_bool_t is_busy; + flexspi_transfer_t xfer; + + xfer.deviceAddress = 0; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + xfer.data = &read_val; + xfer.dataSize = 1; + + do + { + status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); + if (status != kStatus_Success) + { + return status; + } + + /* Busy detection logic identical to SDK example */ + if (FLASH_BUSY_STATUS_POL) + { + is_busy = (read_val & (1U << FLASH_BUSY_STATUS_OFFSET)) != 0U; + } + else + { + is_busy = (read_val & (1U << FLASH_BUSY_STATUS_OFFSET)) == 0U; + } + + if (++timeout > WIP_TIMEOUT_COUNT) + { + return kStatus_Timeout; + } + } + while (is_busy); + + return kStatus_Success; +} + +/* + * _nor_erase_sector - erase one 4KB sector (SDK: flexspi_nor_flash_erase_sector) + * + * @addr: Flash internal offset (not AHB address) + */ +static status_t _nor_erase_sector(rt_uint32_t addr) +{ + rt_base_t level; + status_t status; + flexspi_transfer_t xfer; + + level = rt_hw_interrupt_disable(); + + xfer.deviceAddress = addr; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + status = _nor_wait_busy(); + if (status == kStatus_Success) + { + FLEXSPI_SoftwareReset(s_handle->base); + } + + rt_hw_interrupt_enable(level); + + return status; +} + +/* + * _nor_page_program - program one page (SDK: flexspi_nor_flash_page_program) + * + * Uses PAGEPROGRAM_QUAD (0x32, 1-1-4 mode) for faster write speed, + * consistent with the SDK example. src must be a 4-byte aligned SRAM buffer. + */ +static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) +{ + rt_base_t level; + status_t status; + flexspi_transfer_t xfer; + + level = rt_hw_interrupt_disable(); + + status = _nor_wait_busy(); + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + status = _nor_write_enable(addr); + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + xfer.deviceAddress = addr; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Write; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + xfer.data = (rt_uint32_t *)src; + xfer.dataSize = QSPI_PAGE_SIZE; + + status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + status = _nor_wait_busy(); + if (status == kStatus_Success) + { + FLEXSPI_SoftwareReset(s_handle->base); + } + + rt_hw_interrupt_enable(level); + + return status; +} + +/* + * rt_qspi_flash_init - initialize the QSPI NOR Flash driver + * + * Note: drv_flexspi.c has already performed the following via INIT_DEVICE_EXPORT: + * - flexspi_clock_init + * - FLEXSPI_Init + * - FLEXSPI_SetFlashConfig + * - FLEXSPI_UpdateLUT + * - FLEXSPI_SoftwareReset + * This function only acquires the handle and verifies Flash connectivity. + */ +int rt_qspi_flash_init(void) +{ + rt_uint8_t vendor_id = 0; + rt_uint32_t temp = 0; + status_t status; + flexspi_transfer_t xfer; + + if (s_inited) + { + return RT_EOK; + } + + /* Acquire the controller handle already initialized by drv_flexspi.c */ + s_handle = imxrt_flexspi_get_handle(); + if ((s_handle == RT_NULL) || (s_handle->base == RT_NULL)) + { + LOG_E("FlexSPI handle not ready, check INIT order"); + return -RT_ERROR; + } + + /* Read Vendor ID to verify Flash connectivity (SDK: flexspi_nor_get_vendor_id) */ + xfer.deviceAddress = 0; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; + xfer.data = &temp; + xfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); + if (status != kStatus_Success) + { + LOG_E("read vendor ID failed, status=0x%X", (unsigned)status); + return -RT_ERROR; + } + + vendor_id = (rt_uint8_t)(temp & 0xFFU); + if ((vendor_id == 0x00U) || (vendor_id == 0xFFU)) + { + LOG_E("Flash not detected (vendor=0x%02X)", vendor_id); + return -RT_ERROR; + } + + LOG_I("Vendor ID: 0x%02X", vendor_id); + + /* + * W25Q128JWSIQ: QE bit is set by default from factory, no Quad Enable + * sequence is needed. For other Flash models, refer to SDK example + * flexspi_nor_enable_quad_mode() to add this step. + */ + + if (rt_mutex_init(&s_mutex, "flashmtx", RT_IPC_FLAG_PRIO) != RT_EOK) + { + LOG_E("mutex init failed"); + return -RT_ERROR; + } + + s_inited = 1; + + LOG_I("init OK, base=0x%08X total=%uKB sector=%uB page=%uB", + (unsigned)QSPI_FLASH_BASE, + (unsigned)(QSPI_FLASH_SIZE / 1024U), + (unsigned)QSPI_SECTOR_SIZE, + (unsigned)QSPI_PAGE_SIZE); + LOG_I("fs partition: 0x%08X~0x%08X (%uKB)", + (unsigned)(QSPI_FLASH_BASE + QSPI_FS_OFFSET), + (unsigned)(QSPI_FLASH_BASE + QSPI_FS_OFFSET + QSPI_FS_SIZE - 1U), + (unsigned)(QSPI_FS_SIZE / 1024U)); + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_qspi_flash_init); + +/* + * rt_qspi_flash_read - read data via AHB direct memcpy (XIP mapping) + * + * Read operations do not interfere with FlexSPI IP commands, so this + * function does not need to be placed in ITCM. + */ +int rt_qspi_flash_read(rt_uint32_t offset, rt_uint8_t *buf, rt_size_t size) +{ + if (!s_inited) + { + return -RT_ERROR; + } + if (size == 0U) + { + return 0; + } + if (buf == RT_NULL) + { + return -RT_EINVAL; + } + if (!_range_valid(offset, size)) + { + return -RT_EINVAL; + } + + rt_memcpy(buf, (const void *)(QSPI_FLASH_BASE + offset), size); + + return (int)size; +} + +/* + * rt_qspi_flash_mmap - zero-copy read by returning AHB mapping pointer + */ +void *rt_qspi_flash_mmap(rt_uint32_t offset, rt_size_t size) +{ + if (!s_inited) + { + return RT_NULL; + } + if (!_range_valid(offset, size)) + { + return RT_NULL; + } + return (void *)(QSPI_FLASH_BASE + offset); +} + +/* + * rt_qspi_flash_write - write data to Flash (page-granular) + * + * This function is placed in ITCM (QSPI_RAM_CODE). + * + * Constraints (aligned with LittleFS prog_size = 256): + * - offset must be page-aligned (256B) + * - size must be a multiple of page size (256B) + * + * Data path: src -> s_write_buf (SRAM) -> Flash + */ +int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size) +{ + rt_size_t written = 0; + status_t status; + + if (!s_inited) + { + return -RT_ERROR; + } + if (size == 0U) + { + return 0; + } + if (buf == RT_NULL) + { + return -RT_EINVAL; + } + if (!_addr_safe(offset, size)) + { + return -RT_EINVAL; + } + if ((offset % QSPI_PAGE_SIZE != 0U) || (size % QSPI_PAGE_SIZE != 0U)) + { + return -RT_EINVAL; + } + + rt_mutex_take(&s_mutex, RT_WAITING_FOREVER); + + while (written < size) + { + /* + * Data must be relayed through an SRAM buffer. + * SDK example declares s_nor_program_buffer as SDK_ALIGN(static uint8_t, 4). + * s_write_buf is equivalently 4-byte aligned and resides in SRAM. + */ + rt_memcpy(s_write_buf, buf + written, QSPI_PAGE_SIZE); + + status = _nor_page_program(offset + written, (const rt_uint32_t *)s_write_buf); + if (status != kStatus_Success) + { + rt_mutex_release(&s_mutex); + return -RT_ERROR; + } + + /* + * Cache maintenance (consistent with SDK DCACHE_InvalidateByRange): + * Invalidate the AHB-mapped cache region after write completes to + * ensure subsequent memcpy/mmap reads return newly written data. + */ + DCACHE_InvalidateByRange(QSPI_FLASH_BASE + offset + written, QSPI_PAGE_SIZE); + + written += QSPI_PAGE_SIZE; + } + + rt_mutex_release(&s_mutex); + return (int)size; +} + +/* + * rt_qspi_flash_erase - erase Flash sectors + * + * This function is placed in ITCM (QSPI_RAM_CODE). + * + * offset and size must be sector-aligned (4KB). + * Only the filesystem partition is allowed to be erased (_addr_safe guard). + */ +int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) +{ + rt_uint32_t addr; + rt_uint32_t addr_end; + status_t status; + + if (!s_inited) + { + return -RT_ERROR; + } + if (size == 0U) + { + return 0; + } + if (!_addr_safe(offset, size)) + { + return -RT_EINVAL; + } + if ((offset % QSPI_SECTOR_SIZE != 0U) || (size % QSPI_SECTOR_SIZE != 0U)) + { + return -RT_EINVAL; + } + + addr = offset; + addr_end = offset + (rt_uint32_t)size; + + rt_mutex_take(&s_mutex, RT_WAITING_FOREVER); + + while (addr < addr_end) + { + status = _nor_erase_sector(addr); + if (status != kStatus_Success) + { + rt_mutex_release(&s_mutex); + return -RT_ERROR; + } + + /* Invalidate D-Cache for the erased AHB region */ + DCACHE_InvalidateByRange(QSPI_FLASH_BASE + addr, QSPI_SECTOR_SIZE); + + addr += QSPI_SECTOR_SIZE; + } + + rt_mutex_release(&s_mutex); + return (int)size; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h new file mode 100644 index 000000000000..51b51a3c0836 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-06-03 CoreBoxer support IMXRT1180-EVK + */ + +#ifndef __DRV_FLEXSPI_NOR_FLASH_H__ +#define __DRV_FLEXSPI_NOR_FLASH_H__ + +#include + +/* ============================================================ + * Flash Physical Parameters + * Source: SDK example app.h + * FLASH_SIZE = 0x4000 (Unit: KB) = 16MB + * FlexSPI1_AMBA_BASE = 0x28000000 + * ============================================================ */ +#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */ +#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */ +#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */ +#define QSPI_PAGE_SIZE 256U /* 256B */ + +/* + * Partition Plan (Total 16MB): + * 0x00000000 ~ 0x00EFFFFF: Application Code Area (15MB, limited by Scatter) + * 0x00F00000 ~ 0x00FFFFFF: File System Area (1MB, LittleFS) + */ +#define QSPI_FS_OFFSET 0x00F00000U +#define QSPI_FS_SIZE 0x00100000U + +/* ============================================================ + * RAM Code Section Attributes + * Write/Erase functions placed in CodeQuickAccess (ITCM), + * CPU can safely fetch instructions during FlexSPI IP command execution. + * ============================================================ */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + #define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) +#elif defined(__GNUC__) + #define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline)) +#elif defined(__ICCARM__) + #define QSPI_RAM_CODE __ramfunc +#else + #define QSPI_RAM_CODE +#endif + +/* ============================================================ + * External APIs + * ============================================================ */ +int rt_qspi_flash_init(void); +int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size); +int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size); +int rt_qspi_flash_erase(uint32_t offset, size_t size); +void *rt_qspi_flash_mmap(uint32_t offset, size_t size); + +#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */ \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h new file mode 100644 index 000000000000..8b452d177368 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-01 RT-Thread first version + */ + +#ifndef __FAL_CFG_H__ +#define __FAL_CFG_H__ + +#include +#include + +extern const struct fal_flash_dev imxrt1180_nor_flash; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &imxrt1180_nor_flash, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15*1024*1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15*1024*1024, 1*1024*1024, 0}, \ +} + +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* __FAL_CFG_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c new file mode 100644 index 000000000000..ae1c3c41338a --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CoreBoxer support IMXRT1180-EVK + */ + +#include +#include +#include + +#include "drv_flexspi_nor_flash.h" + +/* + * Logging configuration + */ +#define LOG_TAG "fal.flash" +#define LOG_LVL LOG_LVL_INFO +#include + +/* FAL ops bridge */ +#ifdef RT_USING_FAL + +static int _fal_init(void) +{ + return rt_qspi_flash_init(); +} + +static int _fal_read(long offset, rt_uint8_t *buf, size_t size) +{ + return rt_qspi_flash_read((rt_uint32_t)offset, buf, size); +} + +static int _fal_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return rt_qspi_flash_write((rt_uint32_t)offset, buf, size); +} + +static int _fal_erase(long offset, size_t size) +{ + return rt_qspi_flash_erase((rt_uint32_t)offset, size); +} + +const struct fal_flash_dev imxrt1180_nor_flash = +{ + .name = "norflash0", + .addr = QSPI_FLASH_BASE, + .len = QSPI_FLASH_SIZE, + .blk_size = QSPI_SECTOR_SIZE, + .ops = { _fal_init, _fal_read, _fal_write, _fal_erase }, + .write_gran = QSPI_PAGE_SIZE, +}; + +#endif /* RT_USING_FAL */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c index 0007dd5f95ee..cfd4d5f0770c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c @@ -8,7 +8,7 @@ #include "flexspi_port.h" #include "rtconfig.h" -#ifdef BSP_USING_FLEXSPI1 +#ifdef BSP_USING_OSPI_FLASH #ifdef BSP_USING_DMA #include "fsl_flexspi_edma.h" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h index f3e9c8e102f7..4b9a55cd1c86 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h @@ -6,11 +6,74 @@ * Change Logs: * Date Author Notes * 2022-08-15 xjy198903 The first version for rt1170 + * 2026-06-03 CoreBoxer support IMXRT1180-EVK */ #ifndef FLEXSPI_PORT_H__ #define FLEXSPI_PORT_H__ +#include + +#if defined(BSP_USING_QSPI_FLASH_FS) && defined(BSP_USING_OSPI_FLASH) +#error "Please enable only one of BSP_USING_QSPI_FLASH_FS or BSP_USING_OSPI_FLASH" +#endif + +#if defined(BSP_USING_QSPI_FLASH_FS) +/* parameters for flexpsi peripheral */ +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI2_CONTROL_BASE FLEXSPI2 +#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/ +#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */ +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ +#define ARD_SEQ_CMD 0xBB /* cmd for read */ +#define AWR_SEQ_CMD 0xAA /* cmd for write */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M +#define CLOCK_DIV 2U +#define CUSTOM_LUT_LENGTH 60U +#define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U) +#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) + +#define COMBINATION_MODE 0U +#define FREE_RUNNING_MODE 0U + +#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE +#define FLASH_PAGE_SIZE 256 +#define SECTOR_SIZE 0x1000 /* 4K */ +#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1 +#define FLASH_PORT kFLEXSPI_PortA1 + +/* DMA related. */ +#define FLEXSPI_DMA (DMA4) +#define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx +#define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx +#define FLEXSPI_TX_DMA_CHANNEL 0U +#define FLEXSPI_RX_DMA_CHANNEL 2U + +#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 +#define NOR_CMD_LUT_SEQ_IDX_READID 8 +#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 +#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10 +#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 +#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 + +#define FLASH_QUAD_ENABLE 0x40 +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +#elif defined(BSP_USING_OSPI_FLASH) #include "fsl_cache.h" /* parameters for flexpsi peripheral */ @@ -90,8 +153,9 @@ typedef struct _flexspi_cache_status } flexspi_cache_status_t; #endif +#else - +#endif #endif /* FLEXSPI_PORT_H__ */ From 58bd17b2f4b28df5e0d6e10ca53105408cf643c8 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:11:07 +0800 Subject: [PATCH 07/31] Updated different link files of loading to hyperram. --- .../MIMXRT1189xxxxx_cm7_hyperram.icf | 156 ++++++++ .../MIMXRT1189xxxxx_cm7_hyperram.ld | 338 ++++++++++++++++++ .../MIMXRT1189xxxxx_cm7_hyperram.scf | 190 ++++++++++ 3 files changed, 684 insertions(+) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.ld create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.scf diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf new file mode 100644 index 000000000000..f5d3f6296550 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf @@ -0,0 +1,156 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +/* General definition */ +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x8000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x4000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = 0x00600000; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +/* cache line size = 32 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.ld new file mode 100644 index 000000000000..015839633477 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.ld @@ -0,0 +1,338 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__use_shmem__ = 1; +__multicore__ = 1; + +/* Board memory map */ +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +/* General definition */ +app_image_offset = 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_dtcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_itcm_size - vector_table_size; +m_data_size = 0x00600000; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : m_ocram1_size; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? 0 : 0; + +m_interrupts_start = m_itcm_start; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_hyperram_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(CodeQuickAccess) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* RT-Thread FinSH symbol table */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + /* RT-Thread init table */ + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* RT-Thread init functions */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(CacheLineData.init) + . = ALIGN(32); /* cache line size = 32 bytes */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + *(DataQuickAccess) /* quick access data section */ + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(CacheLineData) + . = ALIGN(32); /* cache line size = 32 bytes */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.scf new file mode 100644 index 000000000000..1dde9d0bf6af --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.scf @@ -0,0 +1,190 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 + +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_flash_start 0x28000000 +#define m_flash_size 0x01000000 + +/* General definition */ +#define app_image_offset 0x0000B000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x08000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size 0 +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size 0 +#define m_qadata_size m_dtcm_size + +#define m_text_size m_itcm_size +#define m_data_size 0x00600000 +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 m_ocram1_size +#endif +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_text_start m_itcm_start +#define m_interrupts_start m_text_start +#define m_data_start m_hyperram_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size +#define m_heap_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + .ANY (CodeQuickAccess) + } + + ER_m_QuickAccessCode m_qacode_start EMPTY m_qacode_size + { + } + + ER_m_QuickAccessData m_qadata_start m_qadata_size + { + .ANY (DataQuickAccess) + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + } + + ; cache line size is 32 bytes + RW_m_CacheLineData +0 ALIGN 32 (m_data_size-stack_size-ImageLength(RW_m_data))/32*32 + { + * (CacheLineData) + * (CacheLineData.init) + } + + ; auxiliary to make sure RW_m_CacheLineData end-aligned CACHE LINE SIZE + ; DO NOT insert any region between RW_m_CacheLineData and RW_m_CacheLineData_Aux + RW_m_CacheLineData_Aux +0 ALIGN 32 EMPTY 0 + { + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} From ca3b725152d446b449a2831b5bec5f3dcf70774d Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:13:05 +0800 Subject: [PATCH 08/31] Updated .ini files of CM7 to support debugging in keil. And updeated .mac files of CM7 to support deugging in iar. --- .../imxrt1180-nxp-evk/cm7/JLinkSettings.ini | 2 +- .../cm7/evkmimxrt1180_flexspi_nor_cm7.ini | 417 ++++++++++++++++++ .../cm7/evkmimxrt1180_ram_cm7.ini | 414 +++++++++++++++++ 3 files changed, 832 insertions(+), 1 deletion(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_flexspi_nor_cm7.ini create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_ram_cm7.ini diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini index c2434b347af2..feca68fb036f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini @@ -11,7 +11,7 @@ MaxNumAPs = 0 LowPowerHandlingMode = 0 OverrideMemMap = 0 AllowSimulation = 1 -ScriptFile="" +ScriptFile="evkmimxrt1180_cm7.jlinkscript" [FLASH] RMWThreshold = 0x400 Loaders="" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_flexspi_nor_cm7.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_flexspi_nor_cm7.ini new file mode 100644 index 000000000000..988ff61c1c60 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_flexspi_nor_cm7.ini @@ -0,0 +1,417 @@ +/* + * Copyright 2023-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x28800000); // Setup Stack Pointer + PC = _RDWORD(0x28800004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x28800000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +// Disable the software breakpoint for nor flash memory region +SBC 0x28000000, 0x28FFFFFF, 0 + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_ram_cm7.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_ram_cm7.ini new file mode 100644 index 000000000000..d21f38d50c88 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_ram_cm7.ini @@ -0,0 +1,414 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x00000000); // Setup Stack Pointer + PC = _RDWORD(0x00000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + // Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +Setup(); From fa194940858f411385965c6ff0a1b9a77eaa27f2 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:17:53 +0800 Subject: [PATCH 09/31] Remove Keil projects and keep templates only. --- .../imxrt1180-nxp-evk/cm33/project.uvoptx | 1204 --------- .../imxrt1180-nxp-evk/cm33/project.uvprojx | 2221 ----------------- 2 files changed, 3425 deletions(-) delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvprojx diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx deleted file mode 100644 index 2d4e331b3ae0..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx +++ /dev/null @@ -1,1204 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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RAMFUNC due to IAR compilation issues, and use linker configuration to place all flash operation code in RAM. --- bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c index d643c73f6187..c1ab4b66d64d 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c @@ -258,7 +258,7 @@ static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div) CLOCK_SetRootClockMux(root, src); } -FLEXSPI_RAM_CODE static int rt_hw_imxrt_flexspi_init(void) +static int rt_hw_imxrt_flexspi_init(void) { flexspi_config_t config; FLEXSPI_Type *base; From 8baa3ef2b7064b1186adf3ecd759202e6e0299e3 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:22:48 +0800 Subject: [PATCH 11/31] Add related code to support kick-offing CM7 and rpmsg-lite. --- .../cm33/applications/multicore_thread.c | 367 ++++++++++++++++++ .../cm33/multicore/SConscript | 56 +++ .../cm7/applications/multicore_thread.c | 290 ++++++++++++++ .../cm7/multicore/SConscript | 56 +++ 4 files changed, 769 insertions(+) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c new file mode 100644 index 000000000000..dc04a7c2dbaf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-02 Ran Chen multicore communication thread + */ + +#include +#include + +#ifdef BSP_USE_MULTICORE + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#endif + +#ifdef BSP_USE_MULTICORE_KICK_OFF +#include "mcmgr.h" +#include "board.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MULTICORE_THREAD_STACK_SIZE 2048 +#define MULTICORE_THREAD_PRIORITY 10 +#define MULTICORE_THREAD_TIMESLICE 5 + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +#ifndef RPMSG_LITE_LINK_ID +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) +#endif + +#ifndef RPMSG_NS_ANNOUNCE_STRING +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-openamp-demo-channel" +#else +#define RPMSG_LITE_NS_ANNOUNCE_STRING RPMSG_NS_ANNOUNCE_STRING +#endif + +#ifndef RPMSG_LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (40U) +#else +#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR +#endif + +#ifndef RPMSG_SHARED_MEM_SIZE +#define SH_MEM_TOTAL_SIZE (6144U) +#else +#define SH_MEM_TOTAL_SIZE RPMSG_SHARED_MEM_SIZE +#endif + +#define APP_RPMSG_READY_EVENT_DATA (1U) + +typedef struct the_message +{ + uint32_t DATA; +} THE_MESSAGE, *THE_MESSAGE_PTR; + +static THE_MESSAGE msg = {0}; + +/* Shared memory for RPMsg */ +#if defined(__ICCARM__) /* IAR Workbench */ +#pragma location = "rpmsg_sh_mem_section" +static char rpmsg_lite_base[SH_MEM_TOTAL_SIZE]; +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /* Keil MDK */ +static char rpmsg_lite_base[SH_MEM_TOTAL_SIZE] __attribute__((section("rpmsg_sh_mem_section"))); +#elif defined(__GNUC__) +static char rpmsg_lite_base[SH_MEM_TOTAL_SIZE] __attribute__((section(".noinit.$rpmsg_sh_mem"))); +#else +#error "RPMsg: Please provide your definition of rpmsg_lite_base[]!" +#endif + +static struct rpmsg_lite_instance *my_rpmsg = NULL; +static struct rpmsg_lite_endpoint *my_ept = NULL; +static rpmsg_queue_handle my_queue = NULL; +static rpmsg_ns_handle ns_handle = NULL; +static bool error_occurred = false; +static volatile uint32_t remote_addr = 0U; +#endif /* BSP_USE_MULTICORE_RPMSG_LITE */ + +#ifdef BSP_USE_MULTICORE_KICK_OFF +static volatile uint16_t RPMsgRemoteReadyEventData = 0U; +#endif + +/******************************************************************************* + * Private Functions + ******************************************************************************/ + +#ifdef BSP_USE_MULTICORE_KICK_OFF +static void RPMsgRemoteReadyEventHandler(mcmgr_core_t coreNum, uint16_t eventData, void *context) +{ + uint16_t *data = (uint16_t *)context; + *data = eventData; +} + +static rt_err_t multicore_kickoff_init(void) +{ + uint32_t core1_image_size, core1_image_source_addr, core1_image_dest_addr; + uint32_t core1_boot_addr; + mcmgr_status_t status; + + rt_kprintf("[Multicore] Initializing MCMGR (CM33 as master core)...\r\n"); + status = MCMGR_Init(); + if (status != kStatus_MCMGR_Success) + { + rt_kprintf("[Multicore] MCMGR initialization failed!\r\n"); + return -RT_ERROR; + } + rt_kprintf("[Multicore] MCMGR initialized successfully\r\n"); + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE + /* Register the application event before starting the secondary core */ + (void)MCMGR_RegisterEvent(kMCMGR_RemoteApplicationEvent, RPMsgRemoteReadyEventHandler, + (void *)&RPMsgRemoteReadyEventData); +#endif + + /* Get CM7 core image information */ + if (kStatus_Success != BOARD_GetCore1ImageAddrSize(&core1_image_source_addr, + &core1_image_dest_addr, + &core1_image_size, + &core1_boot_addr)) + { + rt_kprintf("[Multicore] Failed to get CM7 core image info!\r\n"); + return -RT_ERROR; + } + + rt_kprintf("[Multicore] CM7 core image info:\r\n"); + rt_kprintf(" Source addr = 0x%08x\r\n", core1_image_source_addr); + rt_kprintf(" Dest addr = 0x%08x\r\n", core1_image_dest_addr); + rt_kprintf(" Size = %u (~%uK) bytes\r\n", + core1_image_size, (core1_image_size + 1023UL) / 1024UL); + rt_kprintf(" Boot addr = 0x%08x\r\n", core1_boot_addr); + + /* Prepare CM7 core */ + BOARD_PrepareCore1(core1_image_source_addr, core1_image_dest_addr, + core1_image_size, core1_boot_addr); + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE + /* Boot CM7 core application */ + rt_kprintf("[Multicore] Starting CM7 core...\r\n"); + (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, + (uint32_t)rpmsg_lite_base, kMCMGR_Start_Synchronous); + + /* Wait until the CM7 core signals it's ready */ + rt_kprintf("[Multicore] Waiting for CM7 core ready signal...\r\n"); + while (APP_RPMSG_READY_EVENT_DATA != RPMsgRemoteReadyEventData) + { + rt_thread_mdelay(10); + } + rt_kprintf("[Multicore] CM7 core is ready!\r\n"); +#else + /* Boot CM7 core without RPMsg */ + rt_kprintf("[Multicore] Starting CM7 core...\r\n"); + (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, + 0, kMCMGR_Start_Synchronous); + rt_kprintf("[Multicore] CM7 core started!\r\n"); +#endif + + return RT_EOK; +} +#endif /* BSP_USE_MULTICORE_KICK_OFF */ + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, + uint32_t flags, void *user_data) +{ + uint32_t *data = (uint32_t *)user_data; + *data = new_ept; +} + +static rt_err_t rpmsg_lite_init(void) +{ + rt_kprintf("[RPMsg] Initializing RPMsg-Lite (CM33 as master)...\r\n"); + + /* Initialize RPMsg-Lite as master */ + my_rpmsg = rpmsg_lite_master_init(rpmsg_lite_base, SH_MEM_TOTAL_SIZE, + RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + if (my_rpmsg == NULL) + { + rt_kprintf("[RPMsg] Failed to initialize rpmsg!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Create queue */ + my_queue = rpmsg_queue_create(my_rpmsg); + if (my_queue == NULL) + { + rt_kprintf("[RPMsg] Failed to create queue!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Create endpoint */ + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + if (my_ept == NULL) + { + rt_kprintf("[RPMsg] Failed to create endpoint!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Bind nameservice */ + ns_handle = rpmsg_ns_bind(my_rpmsg, app_nameservice_isr_cb, (void *)&remote_addr); + if (ns_handle == NULL) + { + rt_kprintf("[RPMsg] Failed to bind name service!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Wait until the CM7 core issues the nameservice announce */ + rt_kprintf("[RPMsg] Waiting for CM7 nameservice announce...\r\n"); + while (0U == remote_addr) + { + } + rt_kprintf("[RPMsg] Got remote endpoint address: 0x%x\r\n", remote_addr); + + return RT_EOK; +} + +static void rpmsg_lite_communication(void) +{ + uint32_t len = 0U; + + rt_kprintf("[RPMsg] Starting ping-pong communication...\r\n"); + + /* Send the first message to CM7 */ + msg.DATA = 0U; + rt_kprintf("[RPMsg] Sending initial ping: %u\r\n", msg.DATA); + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + sizeof(THE_MESSAGE), RL_DONT_BLOCK); + + while (msg.DATA <= 100U) + { + uint32_t recv_addr = 0; + + rt_kprintf("[RPMsg] Waiting for pong from CM7...\r\n"); + + (void)rpmsg_queue_recv(my_rpmsg, my_queue, &recv_addr, (char *)&msg, + sizeof(THE_MESSAGE), &len, RL_BLOCK); + + rt_kprintf("[RPMsg] Received pong: %u (size=%u)\r\n", msg.DATA, len); + + msg.DATA++; + + if (msg.DATA <= 100U) + { + rt_kprintf("[RPMsg] Sending ping: %u\r\n", msg.DATA); + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + sizeof(THE_MESSAGE), RL_BLOCK); + } + } + + rt_kprintf("[RPMsg] Ping-pong communication completed!\r\n"); +} + +static void rpmsg_lite_cleanup(void) +{ + rt_kprintf("[RPMsg] Cleaning up resources...\r\n"); + + if (my_ept != NULL) + { + (void)rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = NULL; + } + + if (my_queue != NULL) + { + (void)rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = NULL; + } + + if (ns_handle != NULL) + { + (void)rpmsg_ns_unbind(my_rpmsg, ns_handle); + ns_handle = NULL; + } + + if (my_rpmsg != NULL) + { + (void)rpmsg_lite_deinit(my_rpmsg); + my_rpmsg = NULL; + } + + msg.DATA = 0U; +} +#endif /* BSP_USE_MULTICORE_RPMSG_LITE */ + +/******************************************************************************* + * Thread Entry + ******************************************************************************/ +static void multicore_thread_entry(void *parameter) +{ + rt_kprintf("\r\n=== Multicore Communication Thread Started (CM33 Master) ===\r\n"); + +#ifdef BSP_USE_MULTICORE_KICK_OFF + /* Initialize and kickoff CM7 core */ + if (multicore_kickoff_init() != RT_EOK) + { + rt_kprintf("[Multicore] Kickoff initialization failed!\r\n"); + return; + } +#endif + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE + /* Initialize RPMsg-Lite */ + if (rpmsg_lite_init() != RT_EOK) + { + rt_kprintf("[Multicore] RPMsg-Lite initialization failed!\r\n"); + goto cleanup; + } + + /* Start communication */ + rpmsg_lite_communication(); + +cleanup: + /* Cleanup resources */ + rpmsg_lite_cleanup(); + + if (error_occurred) + { + rt_kprintf("[Multicore] Error occurred during communication!\r\n"); + } + else + { + rt_kprintf("[Multicore] Communication completed successfully!\r\n"); + } +#endif + + rt_kprintf("=== Multicore Communication Thread Ended ===\r\n"); +} + +/******************************************************************************* + * Public Functions + ******************************************************************************/ +int multicore_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("multicore", + multicore_thread_entry, + RT_NULL, + MULTICORE_THREAD_STACK_SIZE, + MULTICORE_THREAD_PRIORITY, + MULTICORE_THREAD_TIMESLICE); + + if (tid != RT_NULL) + { + rt_thread_startup(tid); + rt_kprintf("[Multicore] Communication thread created successfully\r\n"); + return RT_EOK; + } + else + { + rt_kprintf("[Multicore] Failed to create communication thread!\r\n"); + return -RT_ERROR; + } +} +INIT_APP_EXPORT(multicore_init); + +#endif /* BSP_USE_MULTICORE */ \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript new file mode 100644 index 000000000000..48333c4fc8eb --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript @@ -0,0 +1,56 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# multicore libraries are stored in the nxp-imxrt-sdk package to avoid duplication +sdk_multicore = cwd + '/../packages/nxp-imxrt-sdk-latest/MIMXRT1180/multicore' + +# Base multicore sources (always included when BSP_USE_MULTICORE is enabled) +src = Split(""" +mcmgr/src/mcmgr.c +mcmgr/src/mcmgr_internal_core_api_imxrt1180.c +mcmgr/src/mcmgr_mu_internal.c +""") + +src = [sdk_multicore + '/' + f.strip() for f in src] + +# Add RPMsg-Lite sources if enabled +if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + rpmsg_src = Split(""" + rpmsg-lite/lib/common/llist.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_lite.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_queue.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_ns.c + rpmsg-lite/lib/virtio/virtqueue.c + rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c + rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c + """) + src += [sdk_multicore + '/' + f.strip() for f in rpmsg_src] + +# Base include paths +CPPPATH = [ + cwd, + sdk_multicore + '/mcmgr/inc', + sdk_multicore + '/mcmgr/inc/platform/imxrt1180' +] + +# Add RPMsg-Lite include paths if enabled +if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + CPPPATH += [ + sdk_multicore + '/rpmsg-lite/lib/include', + sdk_multicore + '/rpmsg-lite/lib/include/environment/rtthread', + sdk_multicore + '/rpmsg-lite/lib/include/platform/imxrt1180' + ] + +# Define preprocessor macros +CPPDEFINES = [] + +# Create component group with dependency on BSP_USE_MULTICORE +group = DefineGroup('MultiCore', + src, + depend=['BSP_USE_MULTICORE'], + CPPPATH=CPPPATH, + CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c new file mode 100644 index 000000000000..75c5503f34ec --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c @@ -0,0 +1,290 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * Change Logs: + * Date Author Notes + * 2026-06-02 Ran Chen multicore communication thread + */ + +#include +#include + +#ifdef BSP_USE_MULTICORE + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#endif + +#ifdef BSP_USE_MULTICORE_KICK_OFF +#include "mcmgr.h" +#include "board.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MULTICORE_THREAD_STACK_SIZE 2048 +#define MULTICORE_THREAD_PRIORITY 10 +#define MULTICORE_THREAD_TIMESLICE 5 +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +#ifndef RPMSG_LITE_LINK_ID +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) +#endif + +#ifndef RPMSG_NS_ANNOUNCE_STRING +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-openamp-demo-channel" +#else +#define RPMSG_LITE_NS_ANNOUNCE_STRING RPMSG_NS_ANNOUNCE_STRING +#endif + +#ifndef RPMSG_LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (30U) +#else +#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR +#endif + +#define APP_RPMSG_READY_EVENT_DATA (1U) + +typedef struct the_message +{ + uint32_t DATA; +} THE_MESSAGE, *THE_MESSAGE_PTR; + +static volatile THE_MESSAGE msg = {0}; +static struct rpmsg_lite_instance *volatile my_rpmsg = NULL; +static struct rpmsg_lite_endpoint *volatile my_ept = NULL; +static volatile rpmsg_queue_handle my_queue = NULL; +static bool error_occurred = false; +#endif /* BSP_USE_MULTICORE_RPMSG_LITE */ + +/******************************************************************************* + * Private Functions + ******************************************************************************/ +#ifdef BSP_USE_MULTICORE_KICK_OFF +static rt_err_t multicore_kickoff_init(void) +{ + mcmgr_status_t status; + + rt_kprintf("[Multicore] Initializing MCMGR ...\r\n"); + status = MCMGR_Init(); + if (status != kStatus_MCMGR_Success) + { + rt_kprintf("[Multicore] MCMGR initialization failed!\r\n"); + return -RT_ERROR; + } + rt_kprintf("[Multicore] MCMGR initialized successfully\r\n"); + + return RT_EOK; +} +#endif /* BSP_USE_MULTICORE_KICK_OFF */ +#ifdef BSP_USE_MULTICORE_RPMSG_LITE +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, + uint32_t flags, void *user_data) +{ + /* Nameservice callback - can be extended as needed */ +} + +static rt_err_t rpmsg_lite_init(void) +{ + uint32_t startupData; + mcmgr_status_t status; + + rt_kprintf("[RPMsg] Initializing RPMsg-Lite (CM7 as remote)...\r\n"); + + /* Get the startup data from CM33 master core */ + do + { + status = MCMGR_GetStartupData(kMCMGR_Core0, &startupData); + } while (status != kStatus_MCMGR_Success); + + /* Initialize RPMsg-Lite as remote (CM7 side) */ + my_rpmsg = rpmsg_lite_remote_init((void *)(char *)(platform_patova(startupData)), + RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + if (my_rpmsg == NULL) + { + rt_kprintf("[RPMsg] Failed to initialize rpmsg!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Signal the CM33 master core we are ready */ + (void)MCMGR_TriggerEvent(kMCMGR_Core0, kMCMGR_RemoteApplicationEvent, + APP_RPMSG_READY_EVENT_DATA); + + /* Wait for link up with CM33 master */ + rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK); + rt_kprintf("[RPMsg] Link is up with CM33 master!\r\n"); + + /* Create queue */ + my_queue = rpmsg_queue_create(my_rpmsg); + if (my_queue == NULL) + { + rt_kprintf("[RPMsg] Failed to create queue!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Create endpoint */ + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + if (my_ept == NULL) + { + rt_kprintf("[RPMsg] Failed to create endpoint!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Bind nameservice */ + rpmsg_ns_handle ns_handle = rpmsg_ns_bind(my_rpmsg, app_nameservice_isr_cb, NULL); + if (ns_handle == NULL) + { + rt_kprintf("[RPMsg] Failed to bind name service!\r\n"); + error_occurred = true; + return -RT_ERROR; + } + + /* Announce service */ +// SDK_DelayAtLeastUs(1000000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, + (uint32_t)RL_NS_CREATE); + rt_kprintf("[RPMsg] Nameservice announced\r\n"); + + return RT_EOK; +} + +static void rpmsg_lite_communication(void) +{ + volatile uint32_t remote_addr = 0U; + + rt_kprintf("[RPMsg] Starting ping-pong communication...\r\n"); + + while (msg.DATA <= 100U) + { + rt_kprintf("[RPMsg] Waiting for ping...\r\n"); + + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, + (char *)&msg, sizeof(THE_MESSAGE), NULL, RL_BLOCK); + + msg.DATA++; + + rt_kprintf("[RPMsg] Received: %u, Sending pong: %u\r\n", msg.DATA - 1, msg.DATA); + + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + sizeof(THE_MESSAGE), RL_BLOCK); + } + + rt_kprintf("[RPMsg] Ping-pong communication completed!\r\n"); +} + +static void rpmsg_lite_cleanup(void) +{ + rt_kprintf("[RPMsg] Cleaning up resources...\r\n"); + + if (my_ept) + { + (void)rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = NULL; + } + + if (my_queue) + { + (void)rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = NULL; + } + + if (my_rpmsg) + { + (void)rpmsg_lite_deinit(my_rpmsg); + my_rpmsg = NULL; + } + + msg.DATA = 0U; +} +#endif /* BSP_USE_MULTICORE_RPMSG_LITE */ + +/******************************************************************************* + * Thread Entry + ******************************************************************************/ +static void multicore_thread_entry(void *parameter) +{ +#ifndef BSP_USE_MULTICORE_RPMSG_LITE + uint32_t startupData; + mcmgr_status_t status; +#endif + + rt_kprintf("\r\n=== Multicore Communication Thread Started ===\r\n"); + +#ifdef BSP_USE_MULTICORE_KICK_OFF + /* Initialize and kickoff CM33 core */ + if (multicore_kickoff_init() != RT_EOK) + { + rt_kprintf("[Multicore] Kickoff initialization failed!\r\n"); + return; + } +#endif + +#ifdef BSP_USE_MULTICORE_RPMSG_LITE + /* Initialize RPMsg-Lite */ + if (rpmsg_lite_init() != RT_EOK) + { + rt_kprintf("[Multicore] RPMsg-Lite initialization failed!\r\n"); + goto cleanup; + } + + /* Start communication */ + rpmsg_lite_communication(); + +cleanup: + /* Cleanup resources */ + rpmsg_lite_cleanup(); + + if (error_occurred) + { + rt_kprintf("[Multicore] Error occurred during communication!\r\n"); + } + else + { + rt_kprintf("[Multicore] Communication completed successfully!\r\n"); + } +#else + /* Get the startup data */ + do + { + status = MCMGR_GetStartupData(kMCMGR_Core0, &startupData); + } while (status != kStatus_MCMGR_Success); +#endif + + rt_kprintf("=== Multicore Communication Thread Ended ===\r\n"); +} + +/******************************************************************************* + * Public Functions + ******************************************************************************/ +int multicore_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("multicore", + multicore_thread_entry, + RT_NULL, + MULTICORE_THREAD_STACK_SIZE, + MULTICORE_THREAD_PRIORITY, + MULTICORE_THREAD_TIMESLICE); + + if (tid != RT_NULL) + { + rt_thread_startup(tid); +// rt_kprintf("[Multicore] Communication thread created successfully\r\n"); + return RT_EOK; + } + else + { + rt_kprintf("[Multicore] Failed to create communication thread!\r\n"); + return -RT_ERROR; + } +} +INIT_APP_EXPORT(multicore_init); + +#endif /* BSP_USE_MULTICORE */ \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript new file mode 100644 index 000000000000..48333c4fc8eb --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript @@ -0,0 +1,56 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# multicore libraries are stored in the nxp-imxrt-sdk package to avoid duplication +sdk_multicore = cwd + '/../packages/nxp-imxrt-sdk-latest/MIMXRT1180/multicore' + +# Base multicore sources (always included when BSP_USE_MULTICORE is enabled) +src = Split(""" +mcmgr/src/mcmgr.c +mcmgr/src/mcmgr_internal_core_api_imxrt1180.c +mcmgr/src/mcmgr_mu_internal.c +""") + +src = [sdk_multicore + '/' + f.strip() for f in src] + +# Add RPMsg-Lite sources if enabled +if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + rpmsg_src = Split(""" + rpmsg-lite/lib/common/llist.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_lite.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_queue.c + rpmsg-lite/lib/rpmsg_lite/rpmsg_ns.c + rpmsg-lite/lib/virtio/virtqueue.c + rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c + rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c + """) + src += [sdk_multicore + '/' + f.strip() for f in rpmsg_src] + +# Base include paths +CPPPATH = [ + cwd, + sdk_multicore + '/mcmgr/inc', + sdk_multicore + '/mcmgr/inc/platform/imxrt1180' +] + +# Add RPMsg-Lite include paths if enabled +if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + CPPPATH += [ + sdk_multicore + '/rpmsg-lite/lib/include', + sdk_multicore + '/rpmsg-lite/lib/include/environment/rtthread', + sdk_multicore + '/rpmsg-lite/lib/include/platform/imxrt1180' + ] + +# Define preprocessor macros +CPPDEFINES = [] + +# Create component group with dependency on BSP_USE_MULTICORE +group = DefineGroup('MultiCore', + src, + depend=['BSP_USE_MULTICORE'], + CPPPATH=CPPPATH, + CPPDEFINES=CPPDEFINES) + +Return('group') From 795eca8d4ca6bd5e03935dda5d3498a560a823e6 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:25:07 +0800 Subject: [PATCH 12/31] Add codes to support cherryUSB for CM33 and CM7. --- .../cm33/board/cherryusb_cdc_acm.c | 211 +++++++ .../cm33/board/cherryusb_port.c | 521 ++++++++++++++++++ .../imxrt1180-nxp-evk/cm33/board/usb_config.h | 129 +++++ .../cm33/board/usbh_mouse_demo.c | 277 ++++++++++ .../cm7/board/cherryusb_cdc_acm.c | 211 +++++++ .../cm7/board/cherryusb_port.c | 521 ++++++++++++++++++ .../imxrt1180-nxp-evk/cm7/board/usb_config.h | 129 +++++ .../cm7/board/usbh_mouse_demo.c | 277 ++++++++++ 8 files changed, 2276 insertions(+) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usb_config.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usb_config.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c new file mode 100644 index 000000000000..03b3d097efa2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include "usbd_core.h" +#include "usbd_cdc_acm.h" + +#define RT1180_CDC_IN_EP 0x81 +#define RT1180_CDC_OUT_EP 0x02 +#define RT1180_CDC_INT_EP 0x83 +#define RT1180_CDC_INTF_NUM 0x00 +#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 + +#define RT1180_USBD_VID 0xFFFF +#define RT1180_USBD_PID 0xFFFF +#define RT1180_USBD_MAX_POWER 100 + +#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define RT1180_CDC_MAX_MPS 512 +#else +#define RT1180_CDC_MAX_MPS 64 +#endif + +static const uint8_t rt1180_cdc_device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, + RT1180_USBD_VID, RT1180_USBD_PID, 0x0100, 0x01) +}; + +static const uint8_t rt1180_cdc_config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT(RT1180_USB_CONFIG_SIZE, 0x02, 0x01, + USB_CONFIG_BUS_POWERED, RT1180_USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(RT1180_CDC_INTF_NUM, RT1180_CDC_INT_EP, + RT1180_CDC_OUT_EP, RT1180_CDC_IN_EP, + RT1180_CDC_MAX_MPS, 0x02) +}; + +static const uint8_t rt1180_cdc_device_quality_descriptor[] = { + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, +}; + +static const char *rt1180_cdc_string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, + "CherryUSB", + "RT1180 CDC ACM", + "2022123456", +}; + +static const uint8_t rt1180_cdc_msos_string_descriptor[] = { + USB_MSOSV1_STRING_DESCRIPTOR_INIT(RT1180_CDC_MSOS_VENDOR_CODE) +}; + +static const uint8_t rt1180_cdc_msos_compat_id_descriptor[] = { + USB_MSOSV1_COMP_ID_HEADER_DESCRIPTOR_INIT(0) +}; + +static const uint8_t rt1180_cdc_msos_properties_descriptor[] = { + 0x0a, 0x00, 0x00, 0x00, + 0x00, 0x01, + 0x05, 0x00, + 0x00, 0x00, +}; + +static const uint8_t *rt1180_cdc_msos_properties[] = { + rt1180_cdc_msos_properties_descriptor, + rt1180_cdc_msos_properties_descriptor, +}; + +static const struct usb_msosv1_descriptor rt1180_cdc_msosv1_descriptor = { + .string = rt1180_cdc_msos_string_descriptor, + .vendor_code = RT1180_CDC_MSOS_VENDOR_CODE, + .compat_id = rt1180_cdc_msos_compat_id_descriptor, + .comp_id_property = rt1180_cdc_msos_properties, +}; + +static const uint8_t *rt1180_cdc_device_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_device_descriptor; +} + +static const uint8_t *rt1180_cdc_config_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_config_descriptor; +} + +static const uint8_t *rt1180_cdc_device_quality_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_device_quality_descriptor; +} + +static const char *rt1180_cdc_string_descriptor_callback(uint8_t speed, uint8_t index) +{ + (void)speed; + + if (index > 3) + { + return NULL; + } + + return rt1180_cdc_string_descriptors[index]; +} + +static const struct usb_descriptor rt1180_cdc_descriptor = { + .device_descriptor_callback = rt1180_cdc_device_descriptor_callback, + .config_descriptor_callback = rt1180_cdc_config_descriptor_callback, + .device_quality_descriptor_callback = rt1180_cdc_device_quality_descriptor_callback, + .string_descriptor_callback = rt1180_cdc_string_descriptor_callback, + .msosv1_descriptor = &rt1180_cdc_msosv1_descriptor, +}; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_cdc_read_buffer[2048]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_cdc_write_buffer[2048]; + +static void rt1180_cdc_start_read(uint8_t busid) +{ + usbd_ep_start_read(busid, RT1180_CDC_OUT_EP, + rt1180_cdc_read_buffer, + sizeof(rt1180_cdc_read_buffer)); +} + +static void rt1180_cdc_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) + { + case USBD_EVENT_CONFIGURED: + rt1180_cdc_start_read(busid); + break; + default: + break; + } +} + +static void rt1180_cdc_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + + USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); + + if (nbytes == 0) + { + rt1180_cdc_start_read(busid); + return; + } + + if (nbytes > sizeof(rt1180_cdc_write_buffer)) + { + nbytes = sizeof(rt1180_cdc_write_buffer); + } + + memcpy(rt1180_cdc_write_buffer, rt1180_cdc_read_buffer, nbytes); + + if (usbd_ep_start_write(busid, RT1180_CDC_IN_EP, rt1180_cdc_write_buffer, nbytes) != 0) + { + rt1180_cdc_start_read(busid); + } +} + +static void rt1180_cdc_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", (unsigned int)nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) + { + usbd_ep_start_write(busid, RT1180_CDC_IN_EP, NULL, 0); + } + else + { + rt1180_cdc_start_read(busid); + } +} + +static struct usbd_endpoint rt1180_cdc_out_ep = { + .ep_addr = RT1180_CDC_OUT_EP, + .ep_cb = rt1180_cdc_bulk_out, +}; + +static struct usbd_endpoint rt1180_cdc_in_ep = { + .ep_addr = RT1180_CDC_IN_EP, + .ep_cb = rt1180_cdc_bulk_in, +}; + +static struct usbd_interface rt1180_cdc_intf0; +static struct usbd_interface rt1180_cdc_intf1; + +void rt1180_cdc_acm_init(uint8_t busid, uintptr_t reg_base) +{ + usbd_desc_register(busid, &rt1180_cdc_descriptor); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &rt1180_cdc_intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &rt1180_cdc_intf1)); + usbd_add_endpoint(busid, &rt1180_cdc_out_ep); + usbd_add_endpoint(busid, &rt1180_cdc_in_ep); + usbd_initialize(busid, reg_base, rt1180_cdc_event_handler); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c new file mode 100644 index 000000000000..b35f55adef77 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include +#include +#include + +#include "board.h" +#include "usb_config.h" + +#ifdef CONFIG_USB_DCACHE_ENABLE +#include "fsl_cache.h" +#endif + +#ifdef RT_CHERRYUSB_HOST +#include "usbh_core.h" +#endif + +#define RT1180_USB_EHCI0_ID 2U +#define RT1180_USB_EHCI_COUNT 2U +#define RT1180_USB_INVALID_INDEX 0xffU +#define RT1180_USB_IRQ_PRIORITY 3U + +typedef enum _usb_controller_index +{ + kUSB_ControllerEhci0 = RT1180_USB_EHCI0_ID, + kUSB_ControllerEhci1 = RT1180_USB_EHCI0_ID + 1U, +} usb_controller_index_t; + +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; + uint8_t TXCAL45DP; + uint8_t TXCAL45DM; +} usb_phy_config_struct_t; + +static void (*s_usb_irq_handler)(uint8_t busid); +static uint8_t s_usb_clock_initialized[RT1180_USB_EHCI_COUNT]; + +static uint8_t rt1180_usb_selected_index(void) +{ +#if defined(BSP_CHERRYUSB_USING_OTG2) + return 1U; +#else + return 0U; +#endif +} + +static uint8_t rt1180_usb_index_from_controller(uint8_t controller_id) +{ +#if defined(BSP_CHERRYUSB_USING_OTG2) + (void)controller_id; + return 1U; +#else + if ((controller_id >= RT1180_USB_EHCI0_ID) && + (controller_id < (RT1180_USB_EHCI0_ID + RT1180_USB_EHCI_COUNT))) + { + return controller_id - RT1180_USB_EHCI0_ID; + } + + return RT1180_USB_INVALID_INDEX; +#endif +} + +static usb_controller_index_t rt1180_usb_controller_id(uint8_t busid) +{ + (void)busid; + return (usb_controller_index_t)(RT1180_USB_EHCI0_ID + rt1180_usb_selected_index()); +} + +static uintptr_t rt1180_usb_base(uint8_t busid) +{ + static const uintptr_t usb_base[] = USBHS_STACK_BASE_ADDRS; + + (void)busid; + return usb_base[rt1180_usb_selected_index()]; +} + +static IRQn_Type rt1180_usb_irqn(uint8_t busid) +{ + static const IRQn_Type usb_irq[] = USBHS_IRQS; + + (void)busid; + return usb_irq[rt1180_usb_selected_index()]; +} + +static USBPHY_Type *rt1180_usb_phy(uint8_t index) +{ + static const uintptr_t usbphy_base[] = USBPHY_STACK_BASE_ADDRS; + + return (USBPHY_Type *)usbphy_base[index]; +} + +static USBNC_Type *rt1180_usb_nc(uint8_t index) +{ + static const uintptr_t usbnc_base[] = USBNC_STACK_BASE_ADDRS; + + return (USBNC_Type *)usbnc_base[index]; +} + +static void rt1180_usb_nc_init(uint8_t index) +{ + USBNC_Type *nc = rt1180_usb_nc(index); + +#if defined(USBNC_CTRL1_OVER_CUR_DIS_MASK) + nc->CTRL1 |= USBNC_CTRL1_OVER_CUR_DIS_MASK; +#endif + +#if defined(USBNC_CTRL2_UTMI_CLK_VLD_MASK) + nc->CTRL2 |= USBNC_CTRL2_UTMI_CLK_VLD_MASK; +#endif + +#if defined(USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + nc->USB_OTGn_PHY_CTRL_0 |= USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK; +#endif +} + +static void rt1180_usb_phy_enable_vbus_override(USBPHY_Type *phy) +{ +#if defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + uint32_t vbus_detect = + USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK | + USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK | + USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK | + USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK; + +#if defined(USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + vbus_detect |= USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK | + USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK; +#endif + + phy->USB1_VBUS_DETECT_SET = vbus_detect; +#elif defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + phy->USB1_VBUS_DETECT_SET = USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK; +#else + (void)phy; +#endif +} + +void *USB_EhciPhyGetBase(uint8_t controller_id) +{ + uint8_t index = rt1180_usb_index_from_controller(controller_id); + + if (index >= RT1180_USB_EHCI_COUNT) + { + return RT_NULL; + } + + return (void *)rt1180_usb_phy(index); +} + +uint32_t USB_EhciPhyInit(uint8_t controller_id, uint32_t freq, usb_phy_config_struct_t *phy_config) +{ + uint8_t index = rt1180_usb_index_from_controller(controller_id); + USBPHY_Type *phy; + + (void)freq; + + if (index >= RT1180_USB_EHCI_COUNT) + { + return (uint32_t)-1; + } + + phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + if (phy == RT_NULL) + { + return (uint32_t)-1; + } + + rt1180_usb_nc_init(index); + +#if defined(FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN) && (FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN > 0U) + phy->TRIM_OVERRIDE_EN = 0x001fU; +#endif + +#if defined(USBPHY_CTRL_CLR_SFTRST_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_SFTRST_MASK; +#endif +#if defined(USBPHY_CTRL_CLR_CLKGATE_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#endif + + phy->CTRL_SET = USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; + phy->PWD = 0U; + + if (phy_config != RT_NULL) + { + phy->TX = (phy->TX & ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DN_MASK | USBPHY_TX_TXCAL45DP_MASK)) | + USBPHY_TX_D_CAL(phy_config->D_CAL) | + USBPHY_TX_TXCAL45DP(phy_config->TXCAL45DP) | + USBPHY_TX_TXCAL45DN(phy_config->TXCAL45DM); + } + + rt1180_usb_phy_enable_vbus_override(phy); + + return 0U; +} + +uint32_t USB_EhciLowPowerPhyInit(uint8_t controller_id, uint32_t freq, usb_phy_config_struct_t *phy_config) +{ + USBPHY_Type *phy; + uint32_t status; + + status = USB_EhciPhyInit(controller_id, freq, phy_config); + if (status != 0U) + { + return status; + } + + phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + if (phy == RT_NULL) + { + return (uint32_t)-1; + } + +#if defined(USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_AUTORESUME_EN_MASK; +#elif defined(USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK; +#endif +#if defined(USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; +#endif +#if defined(USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; +#endif + + return 0U; +} + +void USB_EhciPhyDeinit(uint8_t controller_id) +{ + USBPHY_Type *phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + + if (phy == RT_NULL) + { + return; + } + +#if defined(USBPHY_PLL_SIC_PLL_POWER_MASK) + phy->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; +#endif +#if defined(USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + phy->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; +#endif +#if defined(USBPHY_CTRL_SET_CLKGATE_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_CLKGATE_MASK; +#endif +} + +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controller_id, uint8_t enable) +{ + USBPHY_Type *phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + + if (phy == RT_NULL) + { + return; + } + + if (enable) + { +#if defined(USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK; +#elif defined(USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + phy->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; +#endif + } + else + { +#if defined(USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK; +#elif defined(USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + phy->CTRL &= ~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; +#endif + } +} + +static bool USB_ClockInit(uint8_t busid) +{ + bool clock_ok; + uint8_t index = rt1180_usb_selected_index(); + usb_controller_index_t controller_id = rt1180_usb_controller_id(busid); + usb_phy_config_struct_t phy_config = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + if (s_usb_clock_initialized[index]) + { + return true; + } + + if (index == 0U) + { + clock_ok = CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + clock_ok = CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcUnused, BOARD_XTAL0_CLK_HZ) && clock_ok; + } + else + { + clock_ok = CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + clock_ok = CLOCK_EnableUsbhs1Clock(kCLOCK_UsbSrcUnused, BOARD_XTAL0_CLK_HZ) && clock_ok; + } + + if (!clock_ok) + { + rt_kprintf("RT1180 CherryUSB OTG%u clock init failed\n", (unsigned int)(index + 1U)); + return false; + } + + if (USB_EhciPhyInit((uint8_t)controller_id, BOARD_XTAL0_CLK_HZ, &phy_config) != 0U) + { + rt_kprintf("RT1180 CherryUSB OTG%u PHY init failed\n", (unsigned int)(index + 1U)); + return false; + } + + s_usb_clock_initialized[index] = 1U; + return true; +} + +static void USB_ClockDeinit(uint8_t busid) +{ + uint8_t index = rt1180_usb_selected_index(); + + if (!s_usb_clock_initialized[index]) + { + return; + } + + USB_EhciPhyDeinit((uint8_t)rt1180_usb_controller_id(busid)); + + if (index == 0U) + { + CLOCK_DisableUsbhs0PhyPllClock(); + } + else + { + CLOCK_DisableUsbhs1PhyPllClock(); + } + + s_usb_clock_initialized[index] = 0U; +} + +static void rt1180_usb_irq_enable(uint8_t busid) +{ + IRQn_Type irq = rt1180_usb_irqn(busid); + + NVIC_SetPriority(irq, RT1180_USB_IRQ_PRIORITY); + NVIC_ClearPendingIRQ(irq); + EnableIRQ(irq); +} + +static void rt1180_usb_irq_disable(uint8_t busid) +{ + DisableIRQ(rt1180_usb_irqn(busid)); +} + +static void rt1180_usb_irq_dispatch(void) +{ + if (s_usb_irq_handler == RT_NULL) + { + return; + } + + rt_interrupt_enter(); + s_usb_irq_handler(0); + rt_interrupt_leave(); +} + +#if defined(BSP_CHERRYUSB_USING_OTG2) +void USB_OTG2_IRQHandler(void) +{ + rt1180_usb_irq_dispatch(); +} +#else +void USB_OTG1_IRQHandler(void) +{ + rt1180_usb_irq_dispatch(); +} +#endif + +#ifdef RT_CHERRYUSB_DEVICE +void usb_dc_low_level_init(uint8_t busid) +{ + extern void USBD_IRQHandler(uint8_t busid); + + if (!USB_ClockInit(busid)) + { + return; + } + + s_usb_irq_handler = USBD_IRQHandler; + rt1180_usb_irq_enable(busid); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + rt1180_usb_irq_disable(busid); + s_usb_irq_handler = RT_NULL; + USB_ClockDeinit(busid); +} +#endif + +#ifdef RT_CHERRYUSB_HOST +static void rt1180_usb_host_mode_init(USB_Type *ptr) +{ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM(3); + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + extern void USBH_IRQHandler(uint8_t busid); + + if (!USB_ClockInit(bus->hcd.hcd_id)) + { + return; + } + + s_usb_irq_handler = USBH_IRQHandler; + rt1180_usb_irq_enable(bus->hcd.hcd_id); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + rt1180_usb_host_mode_init((USB_Type *)bus->hcd.reg_base); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + rt1180_usb_irq_disable(bus->hcd.hcd_id); + s_usb_irq_handler = RT_NULL; + USB_ClockDeinit(bus->hcd.hcd_id); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed; + USB_Type *ptr = (USB_Type *)bus->hcd.reg_base; + + (void)port; + speed = (uint8_t)((ptr->PORTSC1 & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT); + + if (speed == 0x00U) + { + return USB_SPEED_FULL; + } + if (speed == 0x01U) + { + return USB_SPEED_LOW; + } + if (speed == 0x02U) + { + USB_EhcihostPhyDisconnectDetectCmd((uint8_t)rt1180_usb_controller_id(bus->hcd.hcd_id), 1U); + return USB_SPEED_HIGH; + } + + return 0U; +} + +static int cherryusb_hostinit(void) +{ + usbh_initialize(0, rt1180_usb_base(0), RT_NULL); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_hostinit); +#endif + +#if defined(BSP_CHERRYUSB_DEVICE_CDC_ACM_ECHO) || defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) +static int cherryusb_cdc_acm_init(void) +{ + extern void rt1180_cdc_acm_init(uint8_t busid, uintptr_t reg_base); + + rt1180_cdc_acm_init(0, rt1180_usb_base(0)); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_cdc_acm_init); +#endif + +#ifdef RT_CHERRYUSB_DEVICE_TEMPLATE_MSC +static int cherryusb_msc_init(void) +{ + extern void msc_ram_init(uint8_t busid, uintptr_t reg_base); + + msc_ram_init(0, rt1180_usb_base(0)); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_msc_init); +#endif + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + DCACHE_CleanByRange(addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + DCACHE_InvalidateByRange(addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + DCACHE_CleanInvalidateByRange(addr, size); +} +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usb_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usb_config.h new file mode 100644 index 000000000000..6cdecf39a7aa --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usb_config.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include + +/* USB common configuration */ +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +#if defined(BSP_CHERRYUSB_DEBUG_ENUM) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#elif !defined(CONFIG_USB_DBG_LEVEL) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* USB DMA buffers are placed in NonCacheable sections on CM7. */ +#define CONFIG_USB_DCACHE_ENABLE + +#ifdef CONFIG_USB_DCACHE_ENABLE +#define CONFIG_USB_ALIGN_SIZE 32 +#else +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +#if defined(__GNUC__) +#define USB_NOCACHE_RAM_SECTION __attribute__((section("NonCacheable,\"aw\",%nobits @"))) +#else +#define USB_NOCACHE_RAM_SECTION __attribute__((section("NonCacheable"))) +#endif + +/* USB device stack configuration */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +#define CONFIG_USBDEV_ADVANCE_DESC + +#ifndef CONFIG_USBDEV_EP0_PRIO +#define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* USB host stack configuration */ +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif + +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* EHCI port configuration */ +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x100) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3) +#define CONFIG_USB_EHCI_ITD_NUM 4 + +#ifndef usb_phyaddr2ramaddr +#define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr +#define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#define CONFIG_USB_EHCI_NXP 1 + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c new file mode 100644 index 000000000000..d8feb974dd4a --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include + +#if defined(BSP_CHERRYUSB_HOST_MOUSE_DEMO) && defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_HOST_HID) + +#include +#include +#include + +#include "usb_config.h" +#include "usb_errno.h" +#include "usb_osal.h" +#include "usbh_core.h" +#include "usbh_hid.h" +#include "usb_hid.h" + +#define RT1180_USBH_MOUSE_REPORT_LEN 64U +#define RT1180_USBH_MOUSE_THREAD_STACK 2048U + +struct rt1180_usbh_mouse_state +{ + bool active; + uint8_t buttons; +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_mouse_report[CONFIG_USBHOST_MAX_HID_CLASS][RT1180_USBH_MOUSE_REPORT_LEN]; +static struct rt1180_usbh_mouse_state rt1180_mouse_state[CONFIG_USBHOST_MAX_HID_CLASS]; + +static uint8_t rt1180_hid_minor(struct usbh_hid *hid_class) +{ + if (hid_class == RT_NULL) + { + return CONFIG_USBHOST_MAX_HID_CLASS; + } + + return hid_class->minor; +} + +static uint32_t rt1180_mouse_xfer_len(struct usbh_hid *hid_class) +{ + uint32_t len; + + if ((hid_class == RT_NULL) || (hid_class->intin == RT_NULL)) + { + return 0; + } + + len = hid_class->intin->wMaxPacketSize; + if (len > RT1180_USBH_MOUSE_REPORT_LEN) + { + len = RT1180_USBH_MOUSE_REPORT_LEN; + } + + return len; +} + +static void rt1180_mouse_button_event(const char *name, bool pressed) +{ + rt_kprintf("USB mouse: %s button %s\r\n", name, pressed ? "down" : "up"); +} + +static void rt1180_mouse_report_button(uint8_t changed, uint8_t buttons, uint8_t mask, const char *name) +{ + if (changed & mask) + { + rt1180_mouse_button_event(name, (buttons & mask) != 0U); + } +} + +static void rt1180_mouse_parse_report(struct usbh_hid *hid_class, const uint8_t *report, int nbytes) +{ + struct rt1180_usbh_mouse_state *state; + uint8_t minor; + uint8_t buttons; + uint8_t changed; + int8_t x; + int8_t y; + int8_t wheel = 0; + + if ((report == RT_NULL) || (nbytes < 3)) + { + return; + } + + minor = rt1180_hid_minor(hid_class); + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + state = &rt1180_mouse_state[minor]; + + buttons = report[0]; + x = (int8_t)report[1]; + y = (int8_t)report[2]; + if (nbytes >= 4) + { + wheel = (int8_t)report[3]; + } + + changed = buttons ^ state->buttons; + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_LEFT, "left"); + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_RIGHT, "right"); + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_MIDDLE, "middle"); + + if (x < 0) + { + rt_kprintf("USB mouse: move left dx=%d\r\n", x); + } + else if (x > 0) + { + rt_kprintf("USB mouse: move right dx=%d\r\n", x); + } + + if (y < 0) + { + rt_kprintf("USB mouse: move up dy=%d\r\n", y); + } + else if (y > 0) + { + rt_kprintf("USB mouse: move down dy=%d\r\n", y); + } + + if (wheel < 0) + { + rt_kprintf("USB mouse: wheel down delta=%d\r\n", wheel); + } + else if (wheel > 0) + { + rt_kprintf("USB mouse: wheel up delta=%d\r\n", wheel); + } + + state->buttons = buttons; +} + +static void rt1180_mouse_submit(struct usbh_hid *hid_class); + +static void rt1180_mouse_callback(void *arg, int nbytes) +{ + struct usbh_hid *hid_class = (struct usbh_hid *)arg; + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (!rt1180_mouse_state[minor].active) + { + return; + } + + if (nbytes > 0) + { + rt1180_mouse_parse_report(hid_class, rt1180_mouse_report[minor], nbytes); + rt1180_mouse_submit(hid_class); + } + else if (nbytes == -USB_ERR_NAK) + { + rt1180_mouse_submit(hid_class); + } + else + { + rt_kprintf("USB mouse: interrupt transfer stopped, ret=%d\r\n", nbytes); + rt1180_mouse_state[minor].active = false; + } +} + +static void rt1180_mouse_submit(struct usbh_hid *hid_class) +{ + uint8_t minor = rt1180_hid_minor(hid_class); + uint32_t len; + int ret; + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (!rt1180_mouse_state[minor].active) + { + return; + } + + len = rt1180_mouse_xfer_len(hid_class); + if (len == 0U) + { + rt_kprintf("USB mouse: invalid interrupt IN endpoint\r\n"); + rt1180_mouse_state[minor].active = false; + return; + } + + usbh_int_urb_fill(&hid_class->intin_urb, + hid_class->hport, + hid_class->intin, + rt1180_mouse_report[minor], + len, + 0, + rt1180_mouse_callback, + hid_class); + + ret = usbh_submit_urb(&hid_class->intin_urb); + if (ret < 0) + { + rt_kprintf("USB mouse: submit interrupt IN failed, ret=%d\r\n", ret); + rt1180_mouse_state[minor].active = false; + } +} + +static void rt1180_usbh_mouse_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + struct usbh_hid *hid_class = (struct usbh_hid *)CONFIG_USB_OSAL_THREAD_GET_ARGV; + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + goto exit; + } + + if ((hid_class->intin == RT_NULL) || (hid_class->protocol != HID_PROTOCOL_MOUSE)) + { + rt_kprintf("USB HID: ignore non-mouse device, minor=%u, protocol=%u\r\n", + (unsigned int)minor, + (unsigned int)((hid_class != RT_NULL) ? hid_class->protocol : 0U)); + goto exit; + } + + memset(&rt1180_mouse_state[minor], 0, sizeof(rt1180_mouse_state[minor])); + memset(rt1180_mouse_report[minor], 0, sizeof(rt1180_mouse_report[minor])); + rt1180_mouse_state[minor].active = true; + + (void)usbh_hid_set_idle(hid_class, 0, 0); + (void)usbh_hid_set_protocol(hid_class, HID_PROTOCOL_BOOT); + + rt_kprintf("USB mouse: connected, dev=/dev/input%u\r\n", (unsigned int)minor); + rt1180_mouse_submit(hid_class); + +exit: + usb_osal_thread_delete(RT_NULL); +} + +void usbh_hid_run(struct usbh_hid *hid_class) +{ + usb_osal_thread_create("usbh_mouse", + RT1180_USBH_MOUSE_THREAD_STACK, + CONFIG_USBHOST_PSC_PRIO + 1, + rt1180_usbh_mouse_thread, + hid_class); +} + +void usbh_hid_stop(struct usbh_hid *hid_class) +{ + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (rt1180_mouse_state[minor].active) + { + rt_kprintf("USB mouse: disconnected, dev=/dev/input%u\r\n", (unsigned int)minor); + } + + rt1180_mouse_state[minor].active = false; + rt1180_mouse_state[minor].buttons = 0; +} + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c new file mode 100644 index 000000000000..03b3d097efa2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include "usbd_core.h" +#include "usbd_cdc_acm.h" + +#define RT1180_CDC_IN_EP 0x81 +#define RT1180_CDC_OUT_EP 0x02 +#define RT1180_CDC_INT_EP 0x83 +#define RT1180_CDC_INTF_NUM 0x00 +#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 + +#define RT1180_USBD_VID 0xFFFF +#define RT1180_USBD_PID 0xFFFF +#define RT1180_USBD_MAX_POWER 100 + +#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define RT1180_CDC_MAX_MPS 512 +#else +#define RT1180_CDC_MAX_MPS 64 +#endif + +static const uint8_t rt1180_cdc_device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, + RT1180_USBD_VID, RT1180_USBD_PID, 0x0100, 0x01) +}; + +static const uint8_t rt1180_cdc_config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT(RT1180_USB_CONFIG_SIZE, 0x02, 0x01, + USB_CONFIG_BUS_POWERED, RT1180_USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(RT1180_CDC_INTF_NUM, RT1180_CDC_INT_EP, + RT1180_CDC_OUT_EP, RT1180_CDC_IN_EP, + RT1180_CDC_MAX_MPS, 0x02) +}; + +static const uint8_t rt1180_cdc_device_quality_descriptor[] = { + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, +}; + +static const char *rt1180_cdc_string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, + "CherryUSB", + "RT1180 CDC ACM", + "2022123456", +}; + +static const uint8_t rt1180_cdc_msos_string_descriptor[] = { + USB_MSOSV1_STRING_DESCRIPTOR_INIT(RT1180_CDC_MSOS_VENDOR_CODE) +}; + +static const uint8_t rt1180_cdc_msos_compat_id_descriptor[] = { + USB_MSOSV1_COMP_ID_HEADER_DESCRIPTOR_INIT(0) +}; + +static const uint8_t rt1180_cdc_msos_properties_descriptor[] = { + 0x0a, 0x00, 0x00, 0x00, + 0x00, 0x01, + 0x05, 0x00, + 0x00, 0x00, +}; + +static const uint8_t *rt1180_cdc_msos_properties[] = { + rt1180_cdc_msos_properties_descriptor, + rt1180_cdc_msos_properties_descriptor, +}; + +static const struct usb_msosv1_descriptor rt1180_cdc_msosv1_descriptor = { + .string = rt1180_cdc_msos_string_descriptor, + .vendor_code = RT1180_CDC_MSOS_VENDOR_CODE, + .compat_id = rt1180_cdc_msos_compat_id_descriptor, + .comp_id_property = rt1180_cdc_msos_properties, +}; + +static const uint8_t *rt1180_cdc_device_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_device_descriptor; +} + +static const uint8_t *rt1180_cdc_config_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_config_descriptor; +} + +static const uint8_t *rt1180_cdc_device_quality_descriptor_callback(uint8_t speed) +{ + (void)speed; + return rt1180_cdc_device_quality_descriptor; +} + +static const char *rt1180_cdc_string_descriptor_callback(uint8_t speed, uint8_t index) +{ + (void)speed; + + if (index > 3) + { + return NULL; + } + + return rt1180_cdc_string_descriptors[index]; +} + +static const struct usb_descriptor rt1180_cdc_descriptor = { + .device_descriptor_callback = rt1180_cdc_device_descriptor_callback, + .config_descriptor_callback = rt1180_cdc_config_descriptor_callback, + .device_quality_descriptor_callback = rt1180_cdc_device_quality_descriptor_callback, + .string_descriptor_callback = rt1180_cdc_string_descriptor_callback, + .msosv1_descriptor = &rt1180_cdc_msosv1_descriptor, +}; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_cdc_read_buffer[2048]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_cdc_write_buffer[2048]; + +static void rt1180_cdc_start_read(uint8_t busid) +{ + usbd_ep_start_read(busid, RT1180_CDC_OUT_EP, + rt1180_cdc_read_buffer, + sizeof(rt1180_cdc_read_buffer)); +} + +static void rt1180_cdc_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) + { + case USBD_EVENT_CONFIGURED: + rt1180_cdc_start_read(busid); + break; + default: + break; + } +} + +static void rt1180_cdc_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)ep; + + USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); + + if (nbytes == 0) + { + rt1180_cdc_start_read(busid); + return; + } + + if (nbytes > sizeof(rt1180_cdc_write_buffer)) + { + nbytes = sizeof(rt1180_cdc_write_buffer); + } + + memcpy(rt1180_cdc_write_buffer, rt1180_cdc_read_buffer, nbytes); + + if (usbd_ep_start_write(busid, RT1180_CDC_IN_EP, rt1180_cdc_write_buffer, nbytes) != 0) + { + rt1180_cdc_start_read(busid); + } +} + +static void rt1180_cdc_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", (unsigned int)nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) + { + usbd_ep_start_write(busid, RT1180_CDC_IN_EP, NULL, 0); + } + else + { + rt1180_cdc_start_read(busid); + } +} + +static struct usbd_endpoint rt1180_cdc_out_ep = { + .ep_addr = RT1180_CDC_OUT_EP, + .ep_cb = rt1180_cdc_bulk_out, +}; + +static struct usbd_endpoint rt1180_cdc_in_ep = { + .ep_addr = RT1180_CDC_IN_EP, + .ep_cb = rt1180_cdc_bulk_in, +}; + +static struct usbd_interface rt1180_cdc_intf0; +static struct usbd_interface rt1180_cdc_intf1; + +void rt1180_cdc_acm_init(uint8_t busid, uintptr_t reg_base) +{ + usbd_desc_register(busid, &rt1180_cdc_descriptor); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &rt1180_cdc_intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &rt1180_cdc_intf1)); + usbd_add_endpoint(busid, &rt1180_cdc_out_ep); + usbd_add_endpoint(busid, &rt1180_cdc_in_ep); + usbd_initialize(busid, reg_base, rt1180_cdc_event_handler); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c new file mode 100644 index 000000000000..b35f55adef77 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include +#include +#include + +#include "board.h" +#include "usb_config.h" + +#ifdef CONFIG_USB_DCACHE_ENABLE +#include "fsl_cache.h" +#endif + +#ifdef RT_CHERRYUSB_HOST +#include "usbh_core.h" +#endif + +#define RT1180_USB_EHCI0_ID 2U +#define RT1180_USB_EHCI_COUNT 2U +#define RT1180_USB_INVALID_INDEX 0xffU +#define RT1180_USB_IRQ_PRIORITY 3U + +typedef enum _usb_controller_index +{ + kUSB_ControllerEhci0 = RT1180_USB_EHCI0_ID, + kUSB_ControllerEhci1 = RT1180_USB_EHCI0_ID + 1U, +} usb_controller_index_t; + +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; + uint8_t TXCAL45DP; + uint8_t TXCAL45DM; +} usb_phy_config_struct_t; + +static void (*s_usb_irq_handler)(uint8_t busid); +static uint8_t s_usb_clock_initialized[RT1180_USB_EHCI_COUNT]; + +static uint8_t rt1180_usb_selected_index(void) +{ +#if defined(BSP_CHERRYUSB_USING_OTG2) + return 1U; +#else + return 0U; +#endif +} + +static uint8_t rt1180_usb_index_from_controller(uint8_t controller_id) +{ +#if defined(BSP_CHERRYUSB_USING_OTG2) + (void)controller_id; + return 1U; +#else + if ((controller_id >= RT1180_USB_EHCI0_ID) && + (controller_id < (RT1180_USB_EHCI0_ID + RT1180_USB_EHCI_COUNT))) + { + return controller_id - RT1180_USB_EHCI0_ID; + } + + return RT1180_USB_INVALID_INDEX; +#endif +} + +static usb_controller_index_t rt1180_usb_controller_id(uint8_t busid) +{ + (void)busid; + return (usb_controller_index_t)(RT1180_USB_EHCI0_ID + rt1180_usb_selected_index()); +} + +static uintptr_t rt1180_usb_base(uint8_t busid) +{ + static const uintptr_t usb_base[] = USBHS_STACK_BASE_ADDRS; + + (void)busid; + return usb_base[rt1180_usb_selected_index()]; +} + +static IRQn_Type rt1180_usb_irqn(uint8_t busid) +{ + static const IRQn_Type usb_irq[] = USBHS_IRQS; + + (void)busid; + return usb_irq[rt1180_usb_selected_index()]; +} + +static USBPHY_Type *rt1180_usb_phy(uint8_t index) +{ + static const uintptr_t usbphy_base[] = USBPHY_STACK_BASE_ADDRS; + + return (USBPHY_Type *)usbphy_base[index]; +} + +static USBNC_Type *rt1180_usb_nc(uint8_t index) +{ + static const uintptr_t usbnc_base[] = USBNC_STACK_BASE_ADDRS; + + return (USBNC_Type *)usbnc_base[index]; +} + +static void rt1180_usb_nc_init(uint8_t index) +{ + USBNC_Type *nc = rt1180_usb_nc(index); + +#if defined(USBNC_CTRL1_OVER_CUR_DIS_MASK) + nc->CTRL1 |= USBNC_CTRL1_OVER_CUR_DIS_MASK; +#endif + +#if defined(USBNC_CTRL2_UTMI_CLK_VLD_MASK) + nc->CTRL2 |= USBNC_CTRL2_UTMI_CLK_VLD_MASK; +#endif + +#if defined(USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + nc->USB_OTGn_PHY_CTRL_0 |= USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK; +#endif +} + +static void rt1180_usb_phy_enable_vbus_override(USBPHY_Type *phy) +{ +#if defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + uint32_t vbus_detect = + USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK | + USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK | + USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK | + USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK; + +#if defined(USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + vbus_detect |= USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK | + USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK; +#endif + + phy->USB1_VBUS_DETECT_SET = vbus_detect; +#elif defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + phy->USB1_VBUS_DETECT_SET = USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK; +#else + (void)phy; +#endif +} + +void *USB_EhciPhyGetBase(uint8_t controller_id) +{ + uint8_t index = rt1180_usb_index_from_controller(controller_id); + + if (index >= RT1180_USB_EHCI_COUNT) + { + return RT_NULL; + } + + return (void *)rt1180_usb_phy(index); +} + +uint32_t USB_EhciPhyInit(uint8_t controller_id, uint32_t freq, usb_phy_config_struct_t *phy_config) +{ + uint8_t index = rt1180_usb_index_from_controller(controller_id); + USBPHY_Type *phy; + + (void)freq; + + if (index >= RT1180_USB_EHCI_COUNT) + { + return (uint32_t)-1; + } + + phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + if (phy == RT_NULL) + { + return (uint32_t)-1; + } + + rt1180_usb_nc_init(index); + +#if defined(FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN) && (FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN > 0U) + phy->TRIM_OVERRIDE_EN = 0x001fU; +#endif + +#if defined(USBPHY_CTRL_CLR_SFTRST_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_SFTRST_MASK; +#endif +#if defined(USBPHY_CTRL_CLR_CLKGATE_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#endif + + phy->CTRL_SET = USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; + phy->PWD = 0U; + + if (phy_config != RT_NULL) + { + phy->TX = (phy->TX & ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DN_MASK | USBPHY_TX_TXCAL45DP_MASK)) | + USBPHY_TX_D_CAL(phy_config->D_CAL) | + USBPHY_TX_TXCAL45DP(phy_config->TXCAL45DP) | + USBPHY_TX_TXCAL45DN(phy_config->TXCAL45DM); + } + + rt1180_usb_phy_enable_vbus_override(phy); + + return 0U; +} + +uint32_t USB_EhciLowPowerPhyInit(uint8_t controller_id, uint32_t freq, usb_phy_config_struct_t *phy_config) +{ + USBPHY_Type *phy; + uint32_t status; + + status = USB_EhciPhyInit(controller_id, freq, phy_config); + if (status != 0U) + { + return status; + } + + phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + if (phy == RT_NULL) + { + return (uint32_t)-1; + } + +#if defined(USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_AUTORESUME_EN_MASK; +#elif defined(USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK; +#endif +#if defined(USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; +#endif +#if defined(USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; +#endif + + return 0U; +} + +void USB_EhciPhyDeinit(uint8_t controller_id) +{ + USBPHY_Type *phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + + if (phy == RT_NULL) + { + return; + } + +#if defined(USBPHY_PLL_SIC_PLL_POWER_MASK) + phy->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; +#endif +#if defined(USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + phy->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; +#endif +#if defined(USBPHY_CTRL_SET_CLKGATE_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_CLKGATE_MASK; +#endif +} + +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controller_id, uint8_t enable) +{ + USBPHY_Type *phy = (USBPHY_Type *)USB_EhciPhyGetBase(controller_id); + + if (phy == RT_NULL) + { + return; + } + + if (enable) + { +#if defined(USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + phy->CTRL_SET = USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK; +#elif defined(USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + phy->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; +#endif + } + else + { +#if defined(USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + phy->CTRL_CLR = USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK; +#elif defined(USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + phy->CTRL &= ~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; +#endif + } +} + +static bool USB_ClockInit(uint8_t busid) +{ + bool clock_ok; + uint8_t index = rt1180_usb_selected_index(); + usb_controller_index_t controller_id = rt1180_usb_controller_id(busid); + usb_phy_config_struct_t phy_config = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + if (s_usb_clock_initialized[index]) + { + return true; + } + + if (index == 0U) + { + clock_ok = CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + clock_ok = CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcUnused, BOARD_XTAL0_CLK_HZ) && clock_ok; + } + else + { + clock_ok = CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + clock_ok = CLOCK_EnableUsbhs1Clock(kCLOCK_UsbSrcUnused, BOARD_XTAL0_CLK_HZ) && clock_ok; + } + + if (!clock_ok) + { + rt_kprintf("RT1180 CherryUSB OTG%u clock init failed\n", (unsigned int)(index + 1U)); + return false; + } + + if (USB_EhciPhyInit((uint8_t)controller_id, BOARD_XTAL0_CLK_HZ, &phy_config) != 0U) + { + rt_kprintf("RT1180 CherryUSB OTG%u PHY init failed\n", (unsigned int)(index + 1U)); + return false; + } + + s_usb_clock_initialized[index] = 1U; + return true; +} + +static void USB_ClockDeinit(uint8_t busid) +{ + uint8_t index = rt1180_usb_selected_index(); + + if (!s_usb_clock_initialized[index]) + { + return; + } + + USB_EhciPhyDeinit((uint8_t)rt1180_usb_controller_id(busid)); + + if (index == 0U) + { + CLOCK_DisableUsbhs0PhyPllClock(); + } + else + { + CLOCK_DisableUsbhs1PhyPllClock(); + } + + s_usb_clock_initialized[index] = 0U; +} + +static void rt1180_usb_irq_enable(uint8_t busid) +{ + IRQn_Type irq = rt1180_usb_irqn(busid); + + NVIC_SetPriority(irq, RT1180_USB_IRQ_PRIORITY); + NVIC_ClearPendingIRQ(irq); + EnableIRQ(irq); +} + +static void rt1180_usb_irq_disable(uint8_t busid) +{ + DisableIRQ(rt1180_usb_irqn(busid)); +} + +static void rt1180_usb_irq_dispatch(void) +{ + if (s_usb_irq_handler == RT_NULL) + { + return; + } + + rt_interrupt_enter(); + s_usb_irq_handler(0); + rt_interrupt_leave(); +} + +#if defined(BSP_CHERRYUSB_USING_OTG2) +void USB_OTG2_IRQHandler(void) +{ + rt1180_usb_irq_dispatch(); +} +#else +void USB_OTG1_IRQHandler(void) +{ + rt1180_usb_irq_dispatch(); +} +#endif + +#ifdef RT_CHERRYUSB_DEVICE +void usb_dc_low_level_init(uint8_t busid) +{ + extern void USBD_IRQHandler(uint8_t busid); + + if (!USB_ClockInit(busid)) + { + return; + } + + s_usb_irq_handler = USBD_IRQHandler; + rt1180_usb_irq_enable(busid); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + rt1180_usb_irq_disable(busid); + s_usb_irq_handler = RT_NULL; + USB_ClockDeinit(busid); +} +#endif + +#ifdef RT_CHERRYUSB_HOST +static void rt1180_usb_host_mode_init(USB_Type *ptr) +{ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM(3); + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + extern void USBH_IRQHandler(uint8_t busid); + + if (!USB_ClockInit(bus->hcd.hcd_id)) + { + return; + } + + s_usb_irq_handler = USBH_IRQHandler; + rt1180_usb_irq_enable(bus->hcd.hcd_id); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + rt1180_usb_host_mode_init((USB_Type *)bus->hcd.reg_base); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + rt1180_usb_irq_disable(bus->hcd.hcd_id); + s_usb_irq_handler = RT_NULL; + USB_ClockDeinit(bus->hcd.hcd_id); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed; + USB_Type *ptr = (USB_Type *)bus->hcd.reg_base; + + (void)port; + speed = (uint8_t)((ptr->PORTSC1 & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT); + + if (speed == 0x00U) + { + return USB_SPEED_FULL; + } + if (speed == 0x01U) + { + return USB_SPEED_LOW; + } + if (speed == 0x02U) + { + USB_EhcihostPhyDisconnectDetectCmd((uint8_t)rt1180_usb_controller_id(bus->hcd.hcd_id), 1U); + return USB_SPEED_HIGH; + } + + return 0U; +} + +static int cherryusb_hostinit(void) +{ + usbh_initialize(0, rt1180_usb_base(0), RT_NULL); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_hostinit); +#endif + +#if defined(BSP_CHERRYUSB_DEVICE_CDC_ACM_ECHO) || defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) +static int cherryusb_cdc_acm_init(void) +{ + extern void rt1180_cdc_acm_init(uint8_t busid, uintptr_t reg_base); + + rt1180_cdc_acm_init(0, rt1180_usb_base(0)); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_cdc_acm_init); +#endif + +#ifdef RT_CHERRYUSB_DEVICE_TEMPLATE_MSC +static int cherryusb_msc_init(void) +{ + extern void msc_ram_init(uint8_t busid, uintptr_t reg_base); + + msc_ram_init(0, rt1180_usb_base(0)); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_msc_init); +#endif + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + DCACHE_CleanByRange(addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + DCACHE_InvalidateByRange(addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + DCACHE_CleanInvalidateByRange(addr, size); +} +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usb_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usb_config.h new file mode 100644 index 000000000000..6cdecf39a7aa --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usb_config.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#include + +/* USB common configuration */ +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +#if defined(BSP_CHERRYUSB_DEBUG_ENUM) +#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#elif !defined(CONFIG_USB_DBG_LEVEL) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* USB DMA buffers are placed in NonCacheable sections on CM7. */ +#define CONFIG_USB_DCACHE_ENABLE + +#ifdef CONFIG_USB_DCACHE_ENABLE +#define CONFIG_USB_ALIGN_SIZE 32 +#else +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +#if defined(__GNUC__) +#define USB_NOCACHE_RAM_SECTION __attribute__((section("NonCacheable,\"aw\",%nobits @"))) +#else +#define USB_NOCACHE_RAM_SECTION __attribute__((section("NonCacheable"))) +#endif + +/* USB device stack configuration */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +#define CONFIG_USBDEV_ADVANCE_DESC + +#ifndef CONFIG_USBDEV_EP0_PRIO +#define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* USB host stack configuration */ +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif + +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* EHCI port configuration */ +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x100) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3) +#define CONFIG_USB_EHCI_ITD_NUM 4 + +#ifndef usb_phyaddr2ramaddr +#define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr +#define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#define CONFIG_USB_EHCI_NXP 1 + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c new file mode 100644 index 000000000000..d8feb974dd4a --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026/06/10 Tim first version + */ +#include + +#if defined(BSP_CHERRYUSB_HOST_MOUSE_DEMO) && defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_HOST_HID) + +#include +#include +#include + +#include "usb_config.h" +#include "usb_errno.h" +#include "usb_osal.h" +#include "usbh_core.h" +#include "usbh_hid.h" +#include "usb_hid.h" + +#define RT1180_USBH_MOUSE_REPORT_LEN 64U +#define RT1180_USBH_MOUSE_THREAD_STACK 2048U + +struct rt1180_usbh_mouse_state +{ + bool active; + uint8_t buttons; +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rt1180_mouse_report[CONFIG_USBHOST_MAX_HID_CLASS][RT1180_USBH_MOUSE_REPORT_LEN]; +static struct rt1180_usbh_mouse_state rt1180_mouse_state[CONFIG_USBHOST_MAX_HID_CLASS]; + +static uint8_t rt1180_hid_minor(struct usbh_hid *hid_class) +{ + if (hid_class == RT_NULL) + { + return CONFIG_USBHOST_MAX_HID_CLASS; + } + + return hid_class->minor; +} + +static uint32_t rt1180_mouse_xfer_len(struct usbh_hid *hid_class) +{ + uint32_t len; + + if ((hid_class == RT_NULL) || (hid_class->intin == RT_NULL)) + { + return 0; + } + + len = hid_class->intin->wMaxPacketSize; + if (len > RT1180_USBH_MOUSE_REPORT_LEN) + { + len = RT1180_USBH_MOUSE_REPORT_LEN; + } + + return len; +} + +static void rt1180_mouse_button_event(const char *name, bool pressed) +{ + rt_kprintf("USB mouse: %s button %s\r\n", name, pressed ? "down" : "up"); +} + +static void rt1180_mouse_report_button(uint8_t changed, uint8_t buttons, uint8_t mask, const char *name) +{ + if (changed & mask) + { + rt1180_mouse_button_event(name, (buttons & mask) != 0U); + } +} + +static void rt1180_mouse_parse_report(struct usbh_hid *hid_class, const uint8_t *report, int nbytes) +{ + struct rt1180_usbh_mouse_state *state; + uint8_t minor; + uint8_t buttons; + uint8_t changed; + int8_t x; + int8_t y; + int8_t wheel = 0; + + if ((report == RT_NULL) || (nbytes < 3)) + { + return; + } + + minor = rt1180_hid_minor(hid_class); + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + state = &rt1180_mouse_state[minor]; + + buttons = report[0]; + x = (int8_t)report[1]; + y = (int8_t)report[2]; + if (nbytes >= 4) + { + wheel = (int8_t)report[3]; + } + + changed = buttons ^ state->buttons; + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_LEFT, "left"); + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_RIGHT, "right"); + rt1180_mouse_report_button(changed, buttons, HID_MOUSE_INPUT_BUTTON_MIDDLE, "middle"); + + if (x < 0) + { + rt_kprintf("USB mouse: move left dx=%d\r\n", x); + } + else if (x > 0) + { + rt_kprintf("USB mouse: move right dx=%d\r\n", x); + } + + if (y < 0) + { + rt_kprintf("USB mouse: move up dy=%d\r\n", y); + } + else if (y > 0) + { + rt_kprintf("USB mouse: move down dy=%d\r\n", y); + } + + if (wheel < 0) + { + rt_kprintf("USB mouse: wheel down delta=%d\r\n", wheel); + } + else if (wheel > 0) + { + rt_kprintf("USB mouse: wheel up delta=%d\r\n", wheel); + } + + state->buttons = buttons; +} + +static void rt1180_mouse_submit(struct usbh_hid *hid_class); + +static void rt1180_mouse_callback(void *arg, int nbytes) +{ + struct usbh_hid *hid_class = (struct usbh_hid *)arg; + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (!rt1180_mouse_state[minor].active) + { + return; + } + + if (nbytes > 0) + { + rt1180_mouse_parse_report(hid_class, rt1180_mouse_report[minor], nbytes); + rt1180_mouse_submit(hid_class); + } + else if (nbytes == -USB_ERR_NAK) + { + rt1180_mouse_submit(hid_class); + } + else + { + rt_kprintf("USB mouse: interrupt transfer stopped, ret=%d\r\n", nbytes); + rt1180_mouse_state[minor].active = false; + } +} + +static void rt1180_mouse_submit(struct usbh_hid *hid_class) +{ + uint8_t minor = rt1180_hid_minor(hid_class); + uint32_t len; + int ret; + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (!rt1180_mouse_state[minor].active) + { + return; + } + + len = rt1180_mouse_xfer_len(hid_class); + if (len == 0U) + { + rt_kprintf("USB mouse: invalid interrupt IN endpoint\r\n"); + rt1180_mouse_state[minor].active = false; + return; + } + + usbh_int_urb_fill(&hid_class->intin_urb, + hid_class->hport, + hid_class->intin, + rt1180_mouse_report[minor], + len, + 0, + rt1180_mouse_callback, + hid_class); + + ret = usbh_submit_urb(&hid_class->intin_urb); + if (ret < 0) + { + rt_kprintf("USB mouse: submit interrupt IN failed, ret=%d\r\n", ret); + rt1180_mouse_state[minor].active = false; + } +} + +static void rt1180_usbh_mouse_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + struct usbh_hid *hid_class = (struct usbh_hid *)CONFIG_USB_OSAL_THREAD_GET_ARGV; + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + goto exit; + } + + if ((hid_class->intin == RT_NULL) || (hid_class->protocol != HID_PROTOCOL_MOUSE)) + { + rt_kprintf("USB HID: ignore non-mouse device, minor=%u, protocol=%u\r\n", + (unsigned int)minor, + (unsigned int)((hid_class != RT_NULL) ? hid_class->protocol : 0U)); + goto exit; + } + + memset(&rt1180_mouse_state[minor], 0, sizeof(rt1180_mouse_state[minor])); + memset(rt1180_mouse_report[minor], 0, sizeof(rt1180_mouse_report[minor])); + rt1180_mouse_state[minor].active = true; + + (void)usbh_hid_set_idle(hid_class, 0, 0); + (void)usbh_hid_set_protocol(hid_class, HID_PROTOCOL_BOOT); + + rt_kprintf("USB mouse: connected, dev=/dev/input%u\r\n", (unsigned int)minor); + rt1180_mouse_submit(hid_class); + +exit: + usb_osal_thread_delete(RT_NULL); +} + +void usbh_hid_run(struct usbh_hid *hid_class) +{ + usb_osal_thread_create("usbh_mouse", + RT1180_USBH_MOUSE_THREAD_STACK, + CONFIG_USBHOST_PSC_PRIO + 1, + rt1180_usbh_mouse_thread, + hid_class); +} + +void usbh_hid_stop(struct usbh_hid *hid_class) +{ + uint8_t minor = rt1180_hid_minor(hid_class); + + if (minor >= CONFIG_USBHOST_MAX_HID_CLASS) + { + return; + } + + if (rt1180_mouse_state[minor].active) + { + rt_kprintf("USB mouse: disconnected, dev=/dev/input%u\r\n", (unsigned int)minor); + } + + rt1180_mouse_state[minor].active = false; + rt1180_mouse_state[minor].buttons = 0; +} + +#endif From c8b8a03f75cd5b3de66a0aa0a22174b244ca33bb Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:25:54 +0800 Subject: [PATCH 13/31] Add mnt.c to support littleFS for CM7. --- .../imxrt1180-nxp-evk/cm7/applications/mnt.c | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c new file mode 100644 index 000000000000..854f9aa21ff1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-02 CoreBoxer add LittleFS on QSPI NOR Flash (IMXRT1180-EVK) + */ + +#include + +/* ==================================================================== + * QSPI NOR Flash LittleFS (controlled by BSP_USING_QSPI_FLASH_FS) + * + * Dependencies: + * - drv_flash.c (Flash read/write/erase driver via ROM API) + * - FAL framework (partition management) + * - LittleFS component (RT-Thread package) + * + * FAL partition configuration (fal_cfg.h): + * "filesystem" partition → filesystem area of norflash0 + * + * Mount procedure: + * 1. Find FAL partition to confirm correct configuration + * 2. Create MTD NOR block device + * 3. Try direct mount (for already formatted filesystem) + * 4. If failed, perform mkfs then remount (first use or format scenario) + * ==================================================================== */ +#ifdef BSP_USING_QSPI_FLASH_FS +#include +#include + +#define FS_PARTITION_NAME "filesystem" +#define FS_TYPE_NAME "lfs" +#define FS_MOUNT_POINT "/" + +static int _qspi_flash_fs_mount(void) +{ + struct fal_mtd_nor_device *mtd_dev; + int ret; + + /* Find FAL partition to confirm configuration is correct */ + if (fal_partition_find(FS_PARTITION_NAME) == RT_NULL) + { + rt_kprintf("[qspi_fs] partition '%s' not found, check fal_cfg.h\n", + FS_PARTITION_NAME); + return -RT_ERROR; + } + + /* Create MTD NOR block device for filesystem partition */ + mtd_dev = (struct fal_mtd_nor_device *)fal_mtd_nor_device_create(FS_PARTITION_NAME); + if (mtd_dev == RT_NULL) + { + rt_kprintf("[qspi_fs] failed to create MTD NOR device for '%s'\n", + FS_PARTITION_NAME); + return -RT_ERROR; + } + + /* Try direct mount (for already formatted flash) */ + ret = dfs_mount(FS_PARTITION_NAME, FS_MOUNT_POINT, FS_TYPE_NAME, 0, 0); + if (ret == 0) + { + rt_kprintf("[qspi_fs] '%s' mounted at '%s'\n", + FS_PARTITION_NAME, FS_MOUNT_POINT); + return RT_EOK; + } + + /* Mount failed, indicating flash is not formatted (first use scenario), perform mkfs */ + rt_kprintf("[qspi_fs] mount failed (ret=%d), formatting '%s'...\n", + ret, FS_PARTITION_NAME); + + ret = dfs_mkfs(FS_TYPE_NAME, FS_PARTITION_NAME); + if (ret != 0) + { + rt_kprintf("[qspi_fs] mkfs failed (ret=%d)\n", ret); + return -RT_ERROR; + } + + /* Remount after successful mkfs */ + ret = dfs_mount(FS_PARTITION_NAME, FS_MOUNT_POINT, FS_TYPE_NAME, 0, 0); + if (ret != 0) + { + rt_kprintf("[qspi_fs] mount failed after mkfs (ret=%d)\n", ret); + return -RT_ERROR; + } + + rt_kprintf("[qspi_fs] '%s' formatted and mounted at '%s'\n", + FS_PARTITION_NAME, FS_MOUNT_POINT); + return RT_EOK; +} +INIT_APP_EXPORT(_qspi_flash_fs_mount); +/* + * FAL initialization registered as INIT_COMPONENT_EXPORT: + * after Flash driver (INIT_DEVICE_EXPORT) + * before filesystem mount (INIT_APP_EXPORT) + */ +INIT_COMPONENT_EXPORT(fal_init); + +#endif /* BSP_USING_QSPI_FLASH_FS */ \ No newline at end of file From d0a28d10b01fa5003dffee524b2ea950a60f6269 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:28:13 +0800 Subject: [PATCH 14/31] Add codes to support etherCAT for CM7. --- .../cm7/applications/ecat_thread.c | 52 ++ .../imxrt1180-nxp-evk/cm7/ethercat/SConscript | 25 + .../cm7/ethercat/SSC/Src/applInterface.h | 5 + .../cm7/ethercat/SSC/Src/coeappl.c | 6 + .../cm7/ethercat/SSC/Src/coeappl.h | 5 + .../cm7/ethercat/SSC/Src/digital_io.h | 5 + .../cm7/ethercat/SSC/Src/digital_ioObjects.h | 5 + .../cm7/ethercat/SSC/Src/ecat_def.h | 6 + .../cm7/ethercat/SSC/Src/ecatappl.c | 5 + .../cm7/ethercat/SSC/Src/ecatappl.h | 5 + .../cm7/ethercat/SSC/Src/ecatcoe.c | 5 + .../cm7/ethercat/SSC/Src/ecatcoe.h | 5 + .../cm7/ethercat/SSC/Src/ecatslv.c | 5 + .../cm7/ethercat/SSC/Src/ecatslv.h | 5 + .../cm7/ethercat/SSC/Src/esc.h | 5 + .../cm7/ethercat/SSC/Src/mailbox.c | 5 + .../cm7/ethercat/SSC/Src/mailbox.h | 5 + .../cm7/ethercat/SSC/Src/objdef.c | 5 + .../cm7/ethercat/SSC/Src/objdef.h | 5 + .../cm7/ethercat/SSC/Src/sdoserv.c | 5 + .../cm7/ethercat/SSC/Src/sdoserv.h | 5 + .../cm7/ethercat/SSC/digital_io.xlsx | Bin 0 -> 22380 bytes .../cm7/ethercat/SSC/digital_io.xml | 113 ++++ .../cm7/ethercat/digital_io.c | 415 ++++++++++++++ .../imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h | 84 +++ .../cm7/ethercat/ethercat_init.c | 504 ++++++++++++++++++ 26 files changed, 1290 insertions(+) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xlsx create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xml create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c new file mode 100644 index 000000000000..1b146af0ed85 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c @@ -0,0 +1,52 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * Change Logs: + * Date Author Notes + * 2026-06-02 lucas Cao EtherCAT thread + */ + +#include +#include + +extern void ecat_main(void); + +/* EtherCAT thread stack size */ +#define ECAT_THREAD_STACK_SIZE 4096 +/* EtherCAT thread priority */ +#define ECAT_THREAD_PRIORITY 10 +/* EtherCAT thread time slice */ +#define ECAT_THREAD_TIMESLICE 20 + +static void ecat_thread_entry(void *parameter) +{ + rt_kprintf("EtherCAT thread started\r\n"); + ecat_main(); +} + +int ecat_thread_init(void) +{ + rt_thread_t ecat_thread; + + /* Create EtherCAT thread */ + ecat_thread = rt_thread_create("ecat", + ecat_thread_entry, + RT_NULL, + ECAT_THREAD_STACK_SIZE, + ECAT_THREAD_PRIORITY, + ECAT_THREAD_TIMESLICE); + + if (ecat_thread != RT_NULL) + { + rt_thread_startup(ecat_thread); + rt_kprintf("EtherCAT thread created successfully\r\n"); + return RT_EOK; + } + else + { + rt_kprintf("EtherCAT thread creation failed\r\n"); + return -RT_ERROR; + } +} +INIT_APP_EXPORT(ecat_thread_init); \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript new file mode 100644 index 000000000000..4a0ab1d32428 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript @@ -0,0 +1,25 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +ecat_src = Split(""" +ethercat_init.c +digital_io.c +""") + +# add the SSC. +ssc_src = Glob('SSC/Src/*.c') + +CPPPATH = [cwd, cwd + '/SSC/Src'] + +CPPDEFINES = [] + +group = [] + +# Only include EtherCAT code when BSP_USING_ETHERCAT is enabled +if GetDepend(['BSP_USING_ETHERCAT']): + group += DefineGroup('EtherCAT_APP', ecat_src, depend = ['BSP_USING_ETHERCAT'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + group += DefineGroup('EtherCAT_SSC', ssc_src, depend = ['BSP_USING_ETHERCAT'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c new file mode 100644 index 000000000000..c4770e7182bf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c @@ -0,0 +1,6 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#error "Please read readme.txt and generate the code by the SSC tool." diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h new file mode 100644 index 000000000000..c4770e7182bf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h @@ -0,0 +1,6 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#error "Please read readme.txt and generate the code by the SSC tool." diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h new file mode 100644 index 000000000000..7fbbf83b96d2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xlsx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xlsx new file 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8192 + 4 + 4 + + + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c new file mode 100644 index 000000000000..5b868209e154 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c @@ -0,0 +1,415 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*----------------------------------------------------------------------------------------- +------ +------ Includes +------ +-----------------------------------------------------------------------------------------*/ +#include "ecat_def.h" + +#include "applInterface.h" + +#define _DIGITAL_IO_ 1 +#include "digital_io.h" +#undef _DIGITAL_IO_ + + +#define GPIO_LED RGPIO4 + +#define GPIO_LED_PIN 27 +//#include "app.h" +/*-------------------------------------------------------------------------------------- +------ +------ local types and defines +------ +--------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------- +------ +------ local variables and constants +------ +-----------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------- +------ +------ application specific functions +------ +-----------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------- +------ +------ generic functions +------ +-----------------------------------------------------------------------------------------*/ + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \brief The function is called when an error state was acknowledged by the master + +*//////////////////////////////////////////////////////////////////////////////////////// + +void APPL_AckErrorInd(UINT16 stateTrans) +{ +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) + + \brief The function is called in the state transition from INIT to PREOP when + all general settings were checked to start the mailbox handler. This function + informs the application about the state transition, the application can refuse + the state transition when returning an AL Status error code. + The return code NOERROR_INWORK can be used, if the application cannot confirm + the state transition immediately, in that case this function will be called cyclically + until a value unequal NOERROR_INWORK is returned + +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StartMailboxHandler(void) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return 0, NOERROR_INWORK + + \brief The function is called in the state transition from PREEOP to INIT + to stop the mailbox handler. This functions informs the application + about the state transition, the application cannot refuse + the state transition. + +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StopMailboxHandler(void) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \param pIntMask pointer to the AL Event Mask which will be written to the AL event Mask + register (0x204) when this function is succeeded. The event mask can be adapted + in this function + \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) + + \brief The function is called in the state transition from PREOP to SAFEOP when + all general settings were checked to start the input handler. This function + informs the application about the state transition, the application can refuse + the state transition when returning an AL Status error code. + The return code NOERROR_INWORK can be used, if the application cannot confirm + the state transition immediately, in that case the application need to be complete + the transition by calling ECAT_StateChange. +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StartInputHandler(UINT16 *pIntMask) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return 0, NOERROR_INWORK + + \brief The function is called in the state transition from SAFEOP to PREEOP + to stop the input handler. This functions informs the application + about the state transition, the application cannot refuse + the state transition. + +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StopInputHandler(void) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) + + \brief The function is called in the state transition from SAFEOP to OP when + all general settings were checked to start the output handler. This function + informs the application about the state transition, the application can refuse + the state transition when returning an AL Status error code. + The return code NOERROR_INWORK can be used, if the application cannot confirm + the state transition immediately, in that case the application need to be complete + the transition by calling ECAT_StateChange. +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StartOutputHandler(void) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return 0, NOERROR_INWORK + + \brief The function is called in the state transition from OP to SAFEOP + to stop the output handler. This functions informs the application + about the state transition, the application cannot refuse + the state transition. + +*//////////////////////////////////////////////////////////////////////////////////////// + +UINT16 APPL_StopOutputHandler(void) +{ + return ALSTATUSCODE_NOERROR; +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** +\return 0(ALSTATUSCODE_NOERROR), NOERROR_INWORK +\param pInputSize pointer to save the input process data length +\param pOutputSize pointer to save the output process data length + +\brief This function calculates the process data sizes from the actual SM-PDO-Assign + and PDO mapping +*//////////////////////////////////////////////////////////////////////////////////////// +UINT16 APPL_GenerateMapping(UINT16 *pInputSize, UINT16 *pOutputSize) +{ + UINT16 result = ALSTATUSCODE_NOERROR; + UINT16 InputSize = 0; + UINT16 OutputSize = 0; + +#if COE_SUPPORTED + UINT16 PDOAssignEntryCnt = 0; + OBJCONST TOBJECT OBJMEM *pPDO = NULL; + UINT16 PDOSubindex0 = 0; + UINT32 *pPDOEntry = NULL; + UINT16 PDOEntryCnt = 0; + +#if MAX_PD_OUTPUT_SIZE > 0 + /*Scan object 0x1C12 RXPDO assign*/ + for (PDOAssignEntryCnt = 0; PDOAssignEntryCnt < sRxPDOassign.u16SubIndex0; PDOAssignEntryCnt++) + { + pPDO = OBJ_GetObjectHandle(sRxPDOassign.aEntries[PDOAssignEntryCnt]); + if (pPDO != NULL) + { + PDOSubindex0 = *((UINT16 *)pPDO->pVarPtr); + for (PDOEntryCnt = 0; PDOEntryCnt < PDOSubindex0; PDOEntryCnt++) + { + pPDOEntry = (UINT32 *)((UINT16 *)pPDO->pVarPtr + + (OBJ_GetEntryOffset((PDOEntryCnt + 1), pPDO) >> 3) / 2); // goto PDO entry + // we increment the expected output size depending on the mapped Entry + OutputSize += (UINT16)((*pPDOEntry) & 0xFF); + } + } + else + { + /*assigned PDO was not found in object dictionary. return invalid mapping*/ + OutputSize = 0; + result = ALSTATUSCODE_INVALIDOUTPUTMAPPING; + break; + } + } + + OutputSize = (OutputSize + 7) >> 3; +#endif + +#if MAX_PD_INPUT_SIZE > 0 + if (result == 0) + { + /*Scan Object 0x1C13 TXPDO assign*/ + for (PDOAssignEntryCnt = 0; PDOAssignEntryCnt < sTxPDOassign.u16SubIndex0; PDOAssignEntryCnt++) + { + pPDO = OBJ_GetObjectHandle(sTxPDOassign.aEntries[PDOAssignEntryCnt]); + if (pPDO != NULL) + { + PDOSubindex0 = *((UINT16 *)pPDO->pVarPtr); + for (PDOEntryCnt = 0; PDOEntryCnt < PDOSubindex0; PDOEntryCnt++) + { + pPDOEntry = (UINT32 *)((UINT16 *)pPDO->pVarPtr + + (OBJ_GetEntryOffset((PDOEntryCnt + 1), pPDO) >> 3) / 2); // goto PDO entry + // we increment the expected output size depending on the mapped Entry + InputSize += (UINT16)((*pPDOEntry) & 0xFF); + } + } + else + { + /*assigned PDO was not found in object dictionary. return invalid mapping*/ + InputSize = 0; + result = ALSTATUSCODE_INVALIDINPUTMAPPING; + break; + } + } + } + InputSize = (InputSize + 7) >> 3; +#endif + +#else +#if _WIN32 +#pragma message("Warning: Define 'InputSize' and 'OutputSize'.") +#else +#warning "Define 'InputSize' and 'OutputSize'." +#endif +#endif + + *pInputSize = InputSize; + *pOutputSize = OutputSize; + return result; +} + +unsigned char LED_status; +///////////////////////////////////////////////////////////////////////////////////////// +/** +\param pData pointer to input process data + +\brief This function will copies the inputs from the local memory to the ESC memory + to the hardware +*//////////////////////////////////////////////////////////////////////////////////////// +void APPL_InputMapping(UINT16 *pData) +{ + MEMCPY(pData, &LED_status, SIZEOF(LED_status)); +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** +\param pData pointer to output process data + +\brief This function will copies the outputs from the ESC memory to the local memory + to the hardware +*//////////////////////////////////////////////////////////////////////////////////////// +void APPL_OutputMapping(UINT16 *pData) +{ + MEMCPY(&LED_status, pData, SIZEOF(LED_status)); +} + +///////////////////////////////////////////////////////////////////////////////////////// +/** +\brief This function will called from the synchronisation ISR + or from the mainloop if no synchronisation is supported +*//////////////////////////////////////////////////////////////////////////////////////// +void APPL_Application(void) +{ + RGPIO_PinWrite(GPIO_LED, GPIO_LED_PIN, LED_status & 0x01); +} + +#if EXPLICIT_DEVICE_ID +///////////////////////////////////////////////////////////////////////////////////////// +/** + \return The Explicit Device ID of the EtherCAT slave + + \brief Calculate the Explicit Device ID +*//////////////////////////////////////////////////////////////////////////////////////// +UINT16 APPL_GetDeviceID() +{ +#if _WIN32 +#pragma message("Warning: Implement explicit Device ID latching") +#else +#warning "Implement explicit Device ID latching" +#endif + /* Explicit Device 5 is expected by Explicit Device ID conformance tests*/ + return 0x5; +} +#endif + +///////////////////////////////////////////////////////////////////////////////////////// +/** +\param index index of the requested object. +\param subindex subindex of the requested object. +\param objSize size of the requested object data, calculated with OBJ_GetObjectLength +\param pData Pointer to the buffer where the data can be copied to +\param bCompleteAccess Indicates if a complete read of all subindices of the + object shall be done or not + + \return result of the read operation (0 (success) or an abort code (ABORTIDX_.... defined in + sdosrv.h)) + *//////////////////////////////////////////////////////////////////////////////////////// +UINT8 ReadObject0x6000(UINT16 index, UINT8 subindex, UINT32 dataSize, UINT16 MBXMEM *pData, UINT8 bCompleteAccess) +{ + if (bCompleteAccess) + { + return ABORTIDX_UNSUPPORTED_ACCESS; + } + + if (subindex == 0) + { + *pData = 1; + } + else if (subindex == 1) + { + if (dataSize > 0) + { + MEMCPY(pData, &LED_status, dataSize); + } + } + return 0; +} +///////////////////////////////////////////////////////////////////////////////////////// +/** +\param index index of the requested object. +\param subindex subindex of the requested object. +\param objSize size of the requested object data, calculated with OBJ_GetObjectLength +\param pData Pointer to the buffer where the data can be copied to +\param bCompleteAccess Indicates if a complete read of all subindices of the + object shall be done or not + + \return result of the read operation (0 (success) or an abort code (ABORTIDX_.... defined in + sdosrv.h)) + *//////////////////////////////////////////////////////////////////////////////////////// +UINT8 WriteObject0x7000(UINT16 index, UINT8 subindex, UINT32 dataSize, UINT16 MBXMEM *pData, UINT8 bCompleteAccess) +{ + if (bCompleteAccess) + { + /* Complete Access is not supported for object 0x1010 */ + return ABORTIDX_UNSUPPORTED_ACCESS; + } + + if (subindex == 0) + { + /* Subindex 0 is not writable */ + return ABORTIDX_READ_ONLY_ENTRY; + } + + else if (subindex == 1) + { + /* Save the backup entries */ + MEMCPY(&LED_status, pData, SIZEOF(LED_status)); + } + else + { + return ABORTIDX_VALUE_EXCEEDED; + } + RGPIO_PinWrite(GPIO_LED, GPIO_LED_PIN, LED_status & 0x01); + return 0; +} + +#if USE_DEFAULT_MAIN +///////////////////////////////////////////////////////////////////////////////////////// +/** + + \brief This is the main function + +*//////////////////////////////////////////////////////////////////////////////////////// +int ecat_main(void) +{ + /* initialize the Hardware and the EtherCAT Slave Controller */ +#if FC1100_HW + if (HW_Init()) + { + HW_Release(); + return; + } +#else + HW_Init(); +#endif + MainInit(); + + bRunApplication = TRUE; + do + { + MainLoop(); + + } while (bRunApplication == TRUE); + + HW_Release(); + return 0; +} +#endif // #if USE_DEFAULT_MAIN +/** @} */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h new file mode 100644 index 000000000000..ceac879a2317 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h @@ -0,0 +1,84 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ECAT_HW___H__ +#define __ECAT_HW___H__ + +#include "ecat_def.h" +#include "fsl_ecat.h" + +#ifdef ECAT +/**< \brief Returns the first 16Bit of the AL Event register (0x220)*/ +#define HW_GetALEventRegister() ECAT_GetALEventRegister(ECAT) +#define HW_GetALEventRegister_Isr() ECAT_GetALEventRegister(ECAT) + +/**< \brief Generic ESC (register and DPRAM) read access.*/ +#define HW_EscRead(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) +#define HW_EscReadIsr(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) + +/**< \brief 32Bit specific ESC (register and DPRAM) read access.*/ +#define HW_EscReadDWord(DWordValue, Address) ECAT_EscReadDWord(ECAT, DWordValue, Address) +#define HW_EscReadDWordIsr(DWordValue, Address) ECAT_EscReadDWord(ECAT, DWordValue, Address) + +/**< \brief Macro to copy data from the application mailbox memory(not the ESC memory, this access is handled by + * HW_EscRead).*/ +#define HW_EscReadMbxMem(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) + +/**< \brief Generic ESC (register and DPRAM) write access.*/ +#define HW_EscWrite(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) +#define HW_EscWriteIsr(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) + +/**< \brief 32Bit specific ESC (register and DPRAM) write access.*/ +#define HW_EscWriteDWord(DWordValue, Address) ECAT_EscWriteDWord(ECAT, DWordValue, Address) +#define HW_EscWriteDWordIsr(DWordValue, Address) ECAT_EscWriteDWord(ECAT, DWordValue, Address) + +/**< \brief Macro to copy data from the application mailbox memory (not the ESC memory, this access is handled by + * HW_EscWrite).*/ +#define HW_EscWriteMbxMem(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) + +#else +/**< \brief Returns the first 16Bit of the AL Event register (0x220)*/ +#define HW_GetALEventRegister() ECAT_GetALEventRegister(ETHERCAT) +#define HW_GetALEventRegister_Isr() ECAT_GetALEventRegister(ETHERCAT) + +/**< \brief Generic ESC (register and DPRAM) read access.*/ +#define HW_EscRead(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) +#define HW_EscReadIsr(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) + +/**< \brief 32Bit specific ESC (register and DPRAM) read access.*/ +#define HW_EscReadDWord(DWordValue, Address) ECAT_EscReadDWord(ETHERCAT, DWordValue, Address) +#define HW_EscReadDWordIsr(DWordValue, Address) ECAT_EscReadDWord(ETHERCAT, DWordValue, Address) + +/**< \brief Macro to copy data from the application mailbox memory(not the ESC memory, this access is handled by + * HW_EscRead).*/ +#define HW_EscReadMbxMem(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) + +/**< \brief Generic ESC (register and DPRAM) write access.*/ +#define HW_EscWrite(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) +#define HW_EscWriteIsr(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) + +/**< \brief 32Bit specific ESC (register and DPRAM) write access.*/ +#define HW_EscWriteDWord(DWordValue, Address) ECAT_EscWriteDWord(ETHERCAT, DWordValue, Address) +#define HW_EscWriteDWordIsr(DWordValue, Address) ECAT_EscWriteDWord(ETHERCAT, DWordValue, Address) + +/**< \brief Macro to copy data from the application mailbox memory (not the ESC memory, this access is handled by + * HW_EscWrite).*/ +#define HW_EscWriteMbxMem(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) +#endif + +#define ECAT_TIMER_INC_P_MS 0x01 + +UINT16 HW_Init(void); +void HW_Release(void); + +UINT16 HW_GetTimer(void); +void HW_ClearTimer(void); +void ENABLE_ESC_INT(void); +void DISABLE_ESC_INT(void); +void HW_SetLed(UINT8 RunLed, UINT8 ErrorLed); + +#endif /* __ECAT_HW___H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c new file mode 100644 index 000000000000..fa1c4f813bdc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c @@ -0,0 +1,504 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_xbar.h" +#include "fsl_iomuxc.h" +#include "fsl_ecat.h" +#include "fsl_gpt.h" +#include "fsl_common.h" + +#include "ecat_def.h" +#include "ecatslv.h" +#include "ecat_hw.h" +#include "ecatappl.h" + + +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_PhyInitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27} + - {pin_num: M14, peripheral: RGPIO4, signal: 'gpio_io, 26', pin_signal: GPIO_AD_26} + - {pin_num: J16, peripheral: XBAR1, signal: 'IN, 17', pin_signal: GPIO_AD_33} + - {pin_num: J15, peripheral: XBAR1, signal: 'IN, 18', pin_signal: GPIO_AD_34} + - {pin_num: N15, peripheral: RGPIO4, signal: 'gpio_io, 13', pin_signal: GPIO_AD_13} + - {pin_num: M15, peripheral: RGPIO4, signal: 'gpio_io, 25', pin_signal: GPIO_AD_25} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_PhyInitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_PhyInitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + BLK_CTRL_WAKEUPMIX->XBAR_DIR_CTRL1 = ((BLK_CTRL_WAKEUPMIX->XBAR_DIR_CTRL1 & + (~(BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_MASK | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_MASK))) /* Mask bits to zero which are setting */ + | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17(0x00U) /* IOMUXC XBAR_INOUT17 function direction select: XBAR_INOUT as input */ + | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18(0x00U) /* IOMUXC XBAR_INOUT18 function direction select: XBAR_INOUT as input */ + ); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_13_GPIO4_IO13, /* GPIO_AD_13 is configured as GPIO4_IO13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_GPIO4_IO25, /* GPIO_AD_25 is configured as GPIO4_IO25 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_26_GPIO4_IO26, /* GPIO_AD_26 is configured as GPIO4_IO26 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17, /* GPIO_AD_33 is configured as XBAR1_XBAR_INOUT17 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18, /* GPIO_AD_34 is configured as XBAR1_XBAR_INOUT18 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_ECAT_MDIO_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: L17, peripheral: ECAT, signal: MDC, pin_signal: GPIO_AD_30, pull_up_down_config: Pull_Up, slew_rate: Slow} + - {pin_num: K17, peripheral: ECAT, signal: MDIO, pin_signal: GPIO_AD_31, pull_up_down_config: Pull_Up, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_ECAT_MDIO_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_ECAT_MDIO_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_30_ECAT_MCLK, /* GPIO_AD_30 is configured as ECAT_MCLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_31_ECAT_MDIO, /* GPIO_AD_31 is configured as ECAT_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_30_ECAT_MCLK, /* GPIO_AD_30 PAD functional properties : */ + 0x0EU); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Disabled + Force ibe off Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_31_ECAT_MDIO, /* GPIO_AD_31 PAD functional properties : */ + 0x0EU); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Disabled + Force ibe off Field: Disabled */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_Port0_RMII_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: T4, peripheral: ECAT, signal: 'PT0_TXD, 0', pin_signal: GPIO_EMC_B2_05} + - {pin_num: T6, peripheral: ECAT, signal: 'PT0_TXD, 1', pin_signal: GPIO_EMC_B2_06} + - {pin_num: T7, peripheral: ECAT, signal: PT0_TX_EN, pin_signal: GPIO_EMC_B2_07} + - {pin_num: U4, peripheral: ECAT, signal: PT0_TX_CLK, pin_signal: GPIO_EMC_B2_08, software_input_on: Enable} + - {pin_num: U5, peripheral: ECAT, signal: 'PT0_RXD, 0', pin_signal: GPIO_EMC_B2_09} + - {pin_num: U6, peripheral: ECAT, signal: 'PT0_RXD, 1', pin_signal: GPIO_EMC_B2_10} + - {pin_num: P6, peripheral: ECAT, signal: PT0_RX_DV, pin_signal: GPIO_EMC_B2_11} + - {pin_num: R5, peripheral: ECAT, signal: PT0_RX_ER, pin_signal: GPIO_EMC_B2_12} + - {pin_num: N17, peripheral: ECAT, signal: 'LINK_MII, 0', pin_signal: GPIO_AD_16, pull_keeper_select: Keeper} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_Port0_RMII_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_Port0_RMII_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_16_ECAT_LINK_0, /* GPIO_AD_16 is configured as ECAT_LINK_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_05_ECAT_TX_DATA0_0, /* GPIO_EMC_B2_05 is configured as ECAT_TX_DATA0_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_06_ECAT_TX_DATA1_0, /* GPIO_EMC_B2_06 is configured as ECAT_TX_DATA1_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_07_ECAT_TX_EN_0, /* GPIO_EMC_B2_07 is configured as ECAT_TX_EN_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_08_ECAT_TX_CLK_0, /* GPIO_EMC_B2_08 is configured as ECAT_TX_CLK_0 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_08 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_09_ECAT_RX_DATA0_0, /* GPIO_EMC_B2_09 is configured as ECAT_RX_DATA0_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_10_ECAT_RX_DATA1_0, /* GPIO_EMC_B2_10 is configured as ECAT_RX_DATA1_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_11_ECAT_RX_DV_0, /* GPIO_EMC_B2_11 is configured as ECAT_RX_DV_0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_12_ECAT_PT0_RX_ER, /* GPIO_EMC_B2_12 is configured as ECAT_PT0_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_16_ECAT_LINK_0, /* GPIO_AD_16 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Force ibe off Field: Disabled */ +} + + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_Port1_RMII_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: R6, peripheral: ECAT, signal: 'PT1_TXD, 0', pin_signal: GPIO_EMC_B2_13} + - {pin_num: N8, peripheral: ECAT, signal: 'PT1_TXD, 1', pin_signal: GPIO_EMC_B2_14} + - {pin_num: R4, peripheral: ECAT, signal: PT1_TX_EN, pin_signal: GPIO_EMC_B2_15} + - {pin_num: R7, peripheral: ECAT, signal: PT1_TX_CLK, pin_signal: GPIO_EMC_B2_16, software_input_on: Enable} + - {pin_num: U7, peripheral: ECAT, signal: 'PT1_RXD, 0', pin_signal: GPIO_EMC_B2_17} + - {pin_num: P8, peripheral: ECAT, signal: 'PT1_RXD, 1', pin_signal: GPIO_EMC_B2_18} + - {pin_num: U8, peripheral: ECAT, signal: PT1_RX_DV, pin_signal: GPIO_EMC_B2_19} + - {pin_num: R8, peripheral: ECAT, signal: PT1_RX_ER, pin_signal: GPIO_EMC_B2_20} + - {pin_num: M17, peripheral: ECAT, signal: 'LINK_MII, 1', pin_signal: GPIO_AD_17, pull_keeper_select: Keeper} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_Port1_RMII_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_Port1_RMII_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_17_ECAT_LINK_1, /* GPIO_AD_17 is configured as ECAT_LINK_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_13_ECAT_TX_DATA0_1, /* GPIO_EMC_B2_13 is configured as ECAT_TX_DATA0_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_14_ECAT_TX_DATA1_1, /* GPIO_EMC_B2_14 is configured as ECAT_TX_DATA1_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_15_ECAT_TX_EN_1, /* GPIO_EMC_B2_15 is configured as ECAT_TX_EN_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_16_ECAT_TX_CLK_1, /* GPIO_EMC_B2_16 is configured as ECAT_TX_CLK_1 */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_16 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_17_ECAT_RX_DATA0_1, /* GPIO_EMC_B2_17 is configured as ECAT_RX_DATA0_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_18_ECAT_RX_DATA1_1, /* GPIO_EMC_B2_18 is configured as ECAT_RX_DATA1_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_19_ECAT_RX_DV_1, /* GPIO_EMC_B2_19 is configured as ECAT_RX_DV_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_B2_20_ECAT_RX_ER_1, /* GPIO_EMC_B2_20 is configured as ECAT_RX_ER_1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_17_ECAT_LINK_1, /* GPIO_AD_17 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Force ibe off Field: Disabled */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_ECAT_I2C_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: K16, peripheral: ECAT, signal: SCL, pin_signal: GPIO_AD_18, pull_up_down_config: Pull_Up, open_drain: Enable, slew_rate: Slow} + - {pin_num: L13, peripheral: ECAT, signal: SDA, pin_signal: GPIO_AD_19, pull_up_down_config: Pull_Up, open_drain: Enable, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_ECAT_I2C_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_ECAT_I2C_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_18_ECAT_PROM_CLK, /* GPIO_AD_18 is configured as ECAT_PROM_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_19_ECAT_PROM_DATA, /* GPIO_AD_19 is configured as ECAT_PROM_DATA */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_18_ECAT_PROM_CLK, /* GPIO_AD_18 PAD functional properties : */ + 0x1EU); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled + Force ibe off Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_19_ECAT_PROM_DATA, /* GPIO_AD_19 PAD functional properties : */ + 0x1EU); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain Field: Enabled + Force ibe off Field: Disabled */ +} + + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void Ecat_InitBootPins(void) { + BOARD_PhyInitPins(); + BOARD_ECAT_MDIO_InitPins(); + BOARD_Port0_RMII_InitPins(); + BOARD_Port1_RMII_InitPins(); + BOARD_ECAT_I2C_InitPins(); +} + +UINT32 EcatTimerCnt; + +static void Ecat_KickOff(void) +{ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK | + BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= + (BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_MASK | BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_MASK); + + BLK_CTRL_WAKEUPMIX->MISC_IO_CTRL &= ~(1 << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_SHIFT); + BLK_CTRL_WAKEUPMIX->MISC_IO_CTRL &= ~(1 << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_SHIFT); + + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= (1 << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_SHIFT); + + SRC_GENERAL_REG->SRMASK &= ~(0x1 << SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_SHIFT); + + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= (BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC(2)); + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_MASK; +} + +void rt_ethercat_init() +{ + UINT16 HW_Init(void); +} + +UINT16 HW_Init(void) +{ + UINT32 intMask; + UINT16 led_startus = 0; + xbar_control_config_t xbaraConfig; + uint32_t gptFreq; + gpt_config_t gptConfig; + rgpio_pin_config_t pinConfig = {.pinDirection = kRGPIO_DigitalOutput, .outputLogic = 0}; + + /* Init board hardware. */ + Ecat_InitBootPins(); + + //PRINTF("Start the SSC digital_io example...\r\n"); + + /* Reset ecat PHY */ + RGPIO_PinInit(RGPIO4, 25, &pinConfig); + RGPIO_PinInit(RGPIO4, 13, &pinConfig); + SDK_DelayAtLeastUs(15000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + Ecat_KickOff(); + + RGPIO_PinWrite(RGPIO4, 25, 1); + RGPIO_PinWrite(RGPIO4, 13, 1); + SDK_DelayAtLeastUs(90000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + /*set port0 page register*/ + ECAT_EscMdioWrite(ECAT, 0x00, 31, 0x07); + + /*enable prot0 coustomized LED */ + ECAT_EscMdioRead(ECAT, 0x00, 19, &led_startus); + ECAT_EscMdioWrite(ECAT, 0x00, 19, led_startus | (1 << 3)); + + /*Set led1 to LINK100 and set led0 to ACK*/ + ECAT_EscMdioRead(ECAT, 0x00, 17, &led_startus); + ECAT_EscMdioWrite(ECAT, 0x00, 17, led_startus | (1 << 3) | (1 << 5)); + + /*set port1 page register*/ + ECAT_EscMdioWrite(ECAT, 0x01, 31, 0x07); + + /*enable prot1 coustomized LED */ + ECAT_EscMdioRead(ECAT, 0x01, 19, &led_startus); + ECAT_EscMdioWrite(ECAT, 0x01, 19, led_startus | (1 << 3)); + + /*Set led1 to LINK100 and set led0 to ACK*/ + ECAT_EscMdioRead(ECAT, 0x01, 17, &led_startus); + ECAT_EscMdioWrite(ECAT, 0x01, 17, led_startus | (1 << 3) | (1 << 5)); + + RGPIO_PinInit(RGPIO4, 27, &pinConfig); + RGPIO_PinInit(RGPIO4, 26, &pinConfig); + + /*config Sync0/1 IRQ*/ + XBAR_Init(kXBAR_DSC1); + + XBAR_SetSignalsConnection(kXBAR1_InputEcatSyncOut0, kXBAR1_OutputDma4MuxReq154); + BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 = 0x0; + xbaraConfig.activeEdge = kXBAR_EdgeRising; + xbaraConfig.requestType = kXBAR_RequestInterruptEnable; + XBAR_SetOutputSignalConfig(kXBAR1_OutputDma4MuxReq154, &xbaraConfig); + BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 |= 0xff << 16; + BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 |= 0xff << 8; + BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL2 |= 3; + BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL2 |= 3 << 4; + + XBAR_SetSignalsConnection(kXBAR1_InputEcatSyncOut1, kXBAR1_OutputDma4MuxReq155); + xbaraConfig.activeEdge = kXBAR_EdgeRising; + xbaraConfig.requestType = kXBAR_RequestInterruptEnable; + XBAR_SetOutputSignalConfig(kXBAR1_OutputDma4MuxReq155, &xbaraConfig); + + do + { + intMask = 0x93; + HW_EscWriteDWord(intMask, ESC_AL_EVENTMASK_OFFSET); + intMask = 0; + HW_EscReadDWord(intMask, ESC_AL_EVENTMASK_OFFSET); + } while (intMask != 0x93); + + intMask = 0x00; + + HW_EscWriteDWord(intMask, ESC_AL_EVENTMASK_OFFSET); + + /*Enable GPT1*/ + GPT_GetDefaultConfig(&gptConfig); + GPT_Init(GPT1, &gptConfig); + gptFreq = CLOCK_GetRootClockFreq(kCLOCK_Root_Gpt1); + GPT_SetClockDivider(GPT1, 100); + GPT_SetOutputCompareValue(GPT1, kGPT_OutputCompare_Channel1, gptFreq / 100000); + GPT_EnableInterrupts(GPT1, kGPT_OutputCompare1InterruptEnable); + EnableIRQ(GPT1_IRQn); + + /*Enable PDI IRQ*/ + EnableIRQ(ECAT_INT_IRQn); + NVIC_EnableIRQ(XBAR1_CH0_CH1_IRQn); + GPT_StartTimer(GPT1); + return 0; +} + +void ECAT_INT_IRQHandler(void) +{ + PDI_Isr(); + + SDK_ISR_EXIT_BARRIER; +} + +/*config Sync0/1 IRQ*/ +void XBAR1_CH0_CH1_IRQHandler(void) +{ + bool status; + XBAR_GetOutputStatusFlag(kXBAR1_OutputDma4MuxReq154, &status); + if (status) + { + XBAR_ClearOutputStatusFlag(kXBAR1_OutputDma4MuxReq154); + Sync0_Isr(); + } + + XBAR_GetOutputStatusFlag(kXBAR1_OutputDma4MuxReq155, &status); + if (status) + { + XBAR_ClearOutputStatusFlag(kXBAR1_OutputDma4MuxReq155); + Sync1_Isr(); + } + + SDK_ISR_EXIT_BARRIER; +} + +void HW_Release(void) +{ +} + +void GPT1_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); +#if ECAT_TIMER_INT + ECAT_CheckTimer(); +#endif + EcatTimerCnt++; + + SDK_ISR_EXIT_BARRIER; +} + +UINT16 HW_GetTimer(void) +{ + return EcatTimerCnt; +} + +void HW_ClearTimer(void) +{ + EcatTimerCnt = 0; +} + +void ENABLE_ESC_INT(void) +{ + NVIC_EnableIRQ(ECAT_INT_IRQn); + NVIC_EnableIRQ(XBAR1_CH0_CH1_IRQn); + NVIC_EnableIRQ(GPT1_IRQn); +} + +void DISABLE_ESC_INT(void) +{ + NVIC_DisableIRQ(XBAR1_CH0_CH1_IRQn); + NVIC_DisableIRQ(ECAT_INT_IRQn); + NVIC_DisableIRQ(GPT1_IRQn); +} + +void HW_SetLed(UINT8 RunLed, UINT8 ErrorLed) +{ +} From 1b123644b1019ef3372008e45d14e63db8f37372 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:29:24 +0800 Subject: [PATCH 15/31] Add codes to support USART12 for RT1180. --- .../imx/imxrt/libraries/drivers/drv_uart.c | 213 +++++++++++++++--- 1 file changed, 182 insertions(+), 31 deletions(-) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index 2ad546fb45ed..3933d7bcaaac 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -28,35 +28,45 @@ #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif - -enum -{ -#ifdef BSP_USING_LPUART1 - LPUART1_INDEX, -#endif -#ifdef BSP_USING_LPUART2 - LPUART2_INDEX, -#endif -#ifdef BSP_USING_LPUART3 - LPUART3_INDEX, -#endif -#ifdef BSP_USING_LPUART4 - LPUART4_INDEX, -#endif -#ifdef BSP_USING_LPUART5 - LPUART5_INDEX, -#endif -#ifdef BSP_USING_LPUART6 - LPUART6_INDEX, -#endif -#ifdef BSP_USING_LPUART7 - LPUART7_INDEX, -#endif -#ifdef BSP_USING_LPUART8 - LPUART8_INDEX, -#endif -}; - + enum + { + #ifdef BSP_USING_LPUART1 + LPUART1_INDEX, + #endif + #ifdef BSP_USING_LPUART2 + LPUART2_INDEX, + #endif + #ifdef BSP_USING_LPUART3 + LPUART3_INDEX, + #endif + #ifdef BSP_USING_LPUART4 + LPUART4_INDEX, + #endif + #ifdef BSP_USING_LPUART5 + LPUART5_INDEX, + #endif + #ifdef BSP_USING_LPUART6 + LPUART6_INDEX, + #endif + #ifdef BSP_USING_LPUART7 + LPUART7_INDEX, + #endif + #ifdef BSP_USING_LPUART8 + LPUART8_INDEX, + #endif + #ifdef BSP_USING_LPUART9 + LPUART9_INDEX, + #endif + #ifdef BSP_USING_LPUART10 + LPUART10_INDEX, + #endif + #ifdef BSP_USING_LPUART11 + LPUART11_INDEX, + #endif + #ifdef BSP_USING_LPUART12 + LPUART12_INDEX, + #endif + }; #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) struct dma_rx_config { @@ -187,6 +197,54 @@ static struct imxrt_uart uarts[] = .dma_flag = 0, }, #endif +#ifdef BSP_USING_LPUART9 + { + .name = "uart9", + .uart_base = LPUART9, + .irqn = LPUART9_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif +#ifdef BSP_USING_LPUART10 + { + .name = "uart10", + .uart_base = LPUART10, + .irqn = LPUART10_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif +#ifdef BSP_USING_LPUART11 + { + .name = "uart11", + .uart_base = LPUART11, + .irqn = LPUART11_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif +#ifdef BSP_USING_LPUART12 + { + .name = "uart12", + .uart_base = LPUART12, + .irqn = LPUART12_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif }; static void uart_get_dma_config(void) @@ -278,8 +336,51 @@ static void uart_get_dma_config(void) uarts[LPUART8_INDEX].dma_tx = &uart8_dma_tx; uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif -} +#ifdef BSP_LPUART9_RX_USING_DMA + static struct dma_rx_config uart9_dma_rx = {.request = kDmaRequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0}; + uarts[LPUART9_INDEX].dma_rx = &uart9_dma_rx; + uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART9_TX_USING_DMA + static struct dma_tx_config uart9_dma_tx = {.request = kDmaRequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL}; + uarts[LPUART9_INDEX].dma_tx = &uart9_dma_tx; + uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART10_RX_USING_DMA + static struct dma_rx_config uart10_dma_rx = {.request = kDmaRequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0}; + uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART10_TX_USING_DMA + static struct dma_tx_config uart10_dma_tx = {.request = kDmaRequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL}; + uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART11_RX_USING_DMA + static struct dma_rx_config uart11_dma_rx = {.request = kDmaRequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0}; + uarts[LPUART11_INDEX].dma_rx = &uart11_dma_rx; + uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART11_TX_USING_DMA + static struct dma_tx_config uart11_dma_tx = {.request = kDmaRequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL}; + uarts[LPUART11_INDEX].dma_tx = &uart11_dma_tx; + uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART12_RX_USING_DMA + static struct dma_rx_config uart12_dma_rx = {.request = kDmaRequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0}; + uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART12_TX_USING_DMA + static struct dma_tx_config uart12_dma_tx = {.request = kDmaRequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL}; + uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif +} static void uart_isr(struct imxrt_uart *uart); #if defined(BSP_USING_LPUART1) @@ -389,9 +490,59 @@ void LPUART8_IRQHandler(void) rt_interrupt_leave(); } + #endif /* BSP_USING_LPUART8 */ -#endif /* BSP_USING_LPUART8 */ + #if defined(BSP_USING_LPUART9) + + void LPUART9_IRQHandler(void) + { + rt_interrupt_enter(); + + uart_isr(&uarts[LPUART9_INDEX]); + + rt_interrupt_leave(); + } + + #endif /* BSP_USING_LPUART9 */ + + #if defined(BSP_USING_LPUART10) + + void LPUART10_IRQHandler(void) + { + rt_interrupt_enter(); + + uart_isr(&uarts[LPUART10_INDEX]); + + rt_interrupt_leave(); + } + + #endif /* BSP_USING_LPUART10 */ + + #if defined(BSP_USING_LPUART11) + + void LPUART11_IRQHandler(void) + { + rt_interrupt_enter(); + + uart_isr(&uarts[LPUART11_INDEX]); + + rt_interrupt_leave(); + } + + #endif /* BSP_USING_LPUART11 */ + + #if defined(BSP_USING_LPUART12) + + void LPUART12_IRQHandler(void) + { + rt_interrupt_enter(); + + uart_isr(&uarts[LPUART12_INDEX]); + + rt_interrupt_leave(); + } + #endif /* BSP_USING_LPUART12 */ static void uart_isr(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); From 3bd5c002db77068786b00f12a3b7dc1e262a316e Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 31 Jul 2026 18:31:17 +0800 Subject: [PATCH 16/31] Modify the drv_uart_v2.c to fix some bug to make it can work in CM33, but still cannot work in CM7. Will continue to update in next version. --- .../imx/imxrt/libraries/drivers/drv_uart_v2.c | 56 ++++++++++--------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c index 51d041b1231c..4be908ffc6a5 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c @@ -371,10 +371,22 @@ static void uart_isr(struct imxrt_uart *uart) LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag); } - if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag) + if ((LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag) && + (LPUART_GetEnabledInterrupts(uart->uart_base) & kLPUART_TxDataRegEmptyInterruptEnable)) { - LPUART_DisableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); - rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + /* Feed the next byte from the Serial V2 ring buffer into the TX register. + * If the ring buffer is empty, disable the TX interrupt and signal TX_DONE + * so the Serial V2 framework can unblock the waiting writer. */ + uint8_t tx_ch; + if (rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_GETC, &tx_ch) == RT_EOK) + { + LPUART_WriteByte(uart->uart_base, tx_ch); + } + else + { + LPUART_DisableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) @@ -690,7 +702,11 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar } if (RT_DEVICE_FLAG_TX_BLOCKING == ctrl_arg || RT_DEVICE_FLAG_TX_NON_BLOCKING == ctrl_arg) { - LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + /* Do NOT enable kLPUART_TxDataRegEmptyInterruptEnable here: TX reg is already + * empty at open time, enabling it now would fire an immediate spurious TX_DONE + * event and corrupt the Serial V2 TX state machine (especially visible on CM7 + * where IRQ latency is very short). The TX interrupt is enabled on demand by + * imxrt_transmit() when size == 0 (Serial V2 "kick TX" convention). */ NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); EnableIRQ(uart->irqn); break; @@ -738,7 +754,6 @@ static int imxrt_getc(struct rt_serial_device *serial) return ch; } -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) static rt_ssize_t imxrt_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag) { @@ -747,6 +762,7 @@ static rt_ssize_t imxrt_transmit(struct rt_serial_device *serial, RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct imxrt_uart, serial); +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX) { lpuart_transfer_t xfer; @@ -757,37 +773,23 @@ static rt_ssize_t imxrt_transmit(struct rt_serial_device *serial, return (rt_ssize_t)size; return -RT_EIO; } +#endif - if (size == 0) - { - LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); - return 0; - } - - { - rt_uint8_t *ptr = buf; - while (size--) - { - LPUART_WriteByte(uart->uart_base, *ptr++); - while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)) - ; - } - return (rt_ssize_t)(ptr - buf); - } + /* Interrupt TX path: the Serial V2 framework has already placed data into the + * TX ring buffer before calling transmit(). Enable the TX-empty interrupt so + * uart_isr will drain the ring buffer byte by byte via RT_HW_SERIAL_CTRL_GETC + * and fire RT_SERIAL_EVENT_TX_DONE when the buffer is empty. + * Return size immediately so the framework knows the transfer was accepted. */ + LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + return (rt_ssize_t)size; } -#endif - static const struct rt_uart_ops imxrt_uart_ops = { imxrt_configure, imxrt_control, imxrt_putc, imxrt_getc, -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) imxrt_transmit, -#else - RT_NULL -#endif }; int rt_hw_uart_init(void) From f37e15fc6437fd5c17e91032ddb47f0c0916e7ab Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Thu, 6 Aug 2026 11:17:45 +0800 Subject: [PATCH 17/31] Updated README with both Chinese and English versions. --- bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md | 126 ++++++++++++++++++ .../imx/imxrt/imxrt1180-nxp-evk/README_zh.md | 38 +++--- 2 files changed, 148 insertions(+), 16 deletions(-) create mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md new file mode 100644 index 000000000000..17decced9cd4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md @@ -0,0 +1,126 @@ +# i.MX RT1180 EVK Board BSP Guide + +## Introduction + +This document provides an initial BSP (Board Support Package) guide for the NXP i.MX RT1180 EVK development board. + +The BSP currently supports independent compilation for CM33 and CM7, with CM33 as the primary core and CM7 as the secondary core. It is also possible to use the MCUXpresso Secure Provisioning Tool to generate a bootable dual-core image. + +Main content includes: + +- Development board resource overview +- BSP quick start guide +- Advanced usage instructions + +By following the quick start guide, developers can quickly get this BSP running and bring RT-Thread up on the board. The advanced usage section introduces more features and helps developers use additional onboard resources with RT-Thread. + +## Development Board Overview + +The dual-core i.MX RT1180 combines an 800 MHz Cortex-M7 core with a 240 MHz Arm Cortex-M33 core, offering strong security and extensive networking capabilities, including dual gigabit Ethernet and multiple industrial communication interfaces. The i.MX RT1180 MCU supports a wide temperature range, making it suitable for industrial control, motor drive, and other applications. + +## Peripheral Support + +This BSP currently provides peripheral support: + +| **Onboard Peripheral** | **Support Status** | **Notes** | +| :--------------------- | :---------------: | :-------- | +| QSPI Flash XIP | Supported | | +| Flash driver(flexspi) | supported | | +| CherryUSB | Supported | | +| NETC | Supported | | +| EtherCAT | Supported | | +| **On-chip Peripheral** | **Support Status** | **Notes** | +| Multicore kick-off | Supported | | +| Rpmsg-lite | Supported | | +| GPIO | supported | | +| UART | Supported | | +| SPI | Not yet supported | | +| I2C | supported | | +| ADC | supported | | +| Timer | supported | | +| SDIO | Not yet supported | | +| RTC | Not yet supported | | +| PWM | Not yet supported | | +| CAN | Not yet supported | | + +## Usage Instructions + +Usage instructions are divided into two sections: + +- Quick Start + + This section is aimed at beginners new to RT-Thread. Following the simple steps here will get the RT-Thread operating system running on the development board. + +- Advanced Usage + + This section is for developers who want to use more board resources with RT-Thread. Using the ENV tool to configure the BSP enables additional onboard features and more advanced functionality. + +### Quick Start + +This BSP provides MDK5, IAR, and GCC projects. The following example uses the IAR development environment to describe how to run the system. + +**Please note:** + +Before compiling, open the ENV tool and run the following command to pull required packages (otherwise compilation may fail): + +```bash +pkgs --update +``` + +Generate the IAR project: + +```bash +scons --target=iar +``` + +Generate the KEIL MDK5 project: + +```bash +scons --target=mdk5 +``` + +Or compile the GCC project directly: + +```bash +scons -j8 +``` + +#### Hardware Connection + +Connect the development board to the PC using a data cable, then turn on the power switch. + +#### Build and Download + +Double-click the `project.eww` file to open the IAR project, then build and download the program to the development board. + +> The project is configured by default to use CMSIS-DAP for downloading. With CMSIS-DAP connected to the board, click the download button to program the board. + +#### Run Result + +After the program is downloaded successfully, the system starts automatically. + +Connect the board's serial port to the PC and open the corresponding serial port in a terminal tool with settings `115200-8-1-N`. After resetting the device, you should see RT-Thread output like: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build May 15 2026 17:19:35 + 2006 - 2024 Copyright by RT-Thread team +``` + +### Advanced Usage + +This BSP enables only UART1 by default. To use additional advanced peripherals, configure the BSP with the ENV tool as follows: + +1. Open the env tool in the BSP directory. +2. Enter `menuconfig` to configure the project, then save and exit. +3. Run `pkgs --update` to update the packages. +4. Run `scons --target=mdk5` or `scons --target=iar` to regenerate the project. + +## Notes + +None at this time. + +## Contact + +Maintainer: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md index f0e0365b28b9..8f178e4e10a6 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md @@ -22,22 +22,28 @@ CM33对CM7的kick off将在后续版本中支持。 ## 外设支持 -本 BSP 目前对外设仅支持UART，作为第一次push的测试，之后会逐步完善。外设支持情况如下： - -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------| -| USB 转串口 | 暂不支持 | | -| SPI Flash | 支持 | | -| 以太网 | 暂不支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 暂不支持 | | -| UART | 支持 | | -| SPI | 暂不支持 | | -| I2C | 暂不支持 | | -| SDIO | 暂不支持 | | -| RTC | 暂不支持 | | -| PWM | 暂不支持 | | -| CAN | 暂不支持 | | +本 BSP 外设支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--------------------- | :----------: | :------- | +| QSPI Flash XIP | 支持 | | +| Flash 驱动(flexspi) | 支持 | | +| CherryUSB | 支持 | | +| NETC | 支持 | | +| EtherCAT | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| 多核启动 | 支持 | | +| Rpmsg-lite | 支持 | | +| GPIO | 支持 | | +| UART | 支持 | | +| SPI | 暂不支持 | | +| I2C | 支持 | | +| ADC | 支持 | | +| Timer | 支持 | | +| SDIO | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| CAN | 暂不支持 | | ## 使用说明 From 4dd6450bcbaab92e47be0cf32e8efccf1963a5a3 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Thu, 6 Aug 2026 17:00:43 +0800 Subject: [PATCH 18/31] Move the EtherCAT code into the packages\nxp-imxrt-sdk-latest. --- .../cm33/multicore/SConscript | 26 ++++++++---- .../imxrt1180-nxp-evk/cm7/ethercat/SConscript | 40 ++++++++++++------ .../cm7/multicore/SConscript | 26 ++++++++---- .../ethercat/SSC/Src/applInterface.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/coeappl.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/coeappl.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/digital_io.h | 0 .../ethercat/SSC/Src/digital_ioObjects.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecat_def.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatappl.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatappl.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatcoe.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatcoe.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatslv.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/ecatslv.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/esc.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/mailbox.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/mailbox.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/objdef.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/objdef.h | 0 .../MIMXRT1180}/ethercat/SSC/Src/sdoserv.c | 0 .../MIMXRT1180}/ethercat/SSC/Src/sdoserv.h | 0 .../MIMXRT1180}/ethercat/SSC/digital_io.xlsx | Bin .../MIMXRT1180}/ethercat/SSC/digital_io.xml | 0 .../MIMXRT1180}/ethercat/digital_io.c | 0 .../MIMXRT1180}/ethercat/ecat_hw.h | 0 .../MIMXRT1180}/ethercat/ethercat_init.c | 0 27 files changed, 61 insertions(+), 31 deletions(-) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/applInterface.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/coeappl.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/coeappl.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/digital_io.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/digital_ioObjects.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecat_def.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatappl.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatappl.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatcoe.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatcoe.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatslv.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/ecatslv.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/esc.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/mailbox.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/mailbox.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/objdef.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/objdef.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/sdoserv.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/Src/sdoserv.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/digital_io.xlsx (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/SSC/digital_io.xml (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/digital_io.c (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/ecat_hw.h (100%) rename bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/{ => packages/nxp-imxrt-sdk-latest/MIMXRT1180}/ethercat/ethercat_init.c (100%) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript index 48333c4fc8eb..95d48f3a6ef7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript @@ -1,10 +1,18 @@ Import('rtconfig') from building import * +import os +import glob cwd = GetCurrentDir() -# multicore libraries are stored in the nxp-imxrt-sdk package to avoid duplication -sdk_multicore = cwd + '/../packages/nxp-imxrt-sdk-latest/MIMXRT1180/multicore' +# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. +# The directory is named nxp-imxrt-sdk- under packages/. +bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) +sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) +if sdk_candidates: + sdk_multicore = sdk_candidates[0] +else: + sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') # Base multicore sources (always included when BSP_USE_MULTICORE is enabled) src = Split(""" @@ -13,7 +21,7 @@ mcmgr/src/mcmgr_internal_core_api_imxrt1180.c mcmgr/src/mcmgr_mu_internal.c """) -src = [sdk_multicore + '/' + f.strip() for f in src] +src = [os.path.join(sdk_multicore, f.strip()) for f in src] # Add RPMsg-Lite sources if enabled if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): @@ -26,21 +34,21 @@ if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c """) - src += [sdk_multicore + '/' + f.strip() for f in rpmsg_src] + src += [os.path.join(sdk_multicore, f.strip()) for f in rpmsg_src] # Base include paths CPPPATH = [ cwd, - sdk_multicore + '/mcmgr/inc', - sdk_multicore + '/mcmgr/inc/platform/imxrt1180' + os.path.join(sdk_multicore, 'mcmgr', 'inc'), + os.path.join(sdk_multicore, 'mcmgr', 'inc', 'platform', 'imxrt1180'), ] # Add RPMsg-Lite include paths if enabled if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): CPPPATH += [ - sdk_multicore + '/rpmsg-lite/lib/include', - sdk_multicore + '/rpmsg-lite/lib/include/environment/rtthread', - sdk_multicore + '/rpmsg-lite/lib/include/platform/imxrt1180' + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), ] # Define preprocessor macros diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript index 4a0ab1d32428..1596f1a70a20 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript @@ -1,25 +1,39 @@ +Import('rtconfig') from building import * +import os +import glob cwd = GetCurrentDir() -# add the general drivers. -ecat_src = Split(""" -ethercat_init.c -digital_io.c -""") - -# add the SSC. -ssc_src = Glob('SSC/Src/*.c') - -CPPPATH = [cwd, cwd + '/SSC/Src'] +# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. +# The directory is named nxp-imxrt-sdk- under packages/. +bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) +sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'ethercat')) +if sdk_candidates: + sdk_ethercat = sdk_candidates[0] +else: + sdk_ethercat = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'ethercat') + +# EtherCAT application sources +ecat_src = [ + os.path.join(sdk_ethercat, 'ethercat_init.c'), + os.path.join(sdk_ethercat, 'digital_io.c'), +] + +# SSC sources +ssc_src = Glob(os.path.join(sdk_ethercat, 'SSC', 'Src', '*.c')) + +CPPPATH = [ + sdk_ethercat, + os.path.join(sdk_ethercat, 'SSC', 'Src'), +] CPPDEFINES = [] group = [] -# Only include EtherCAT code when BSP_USING_ETHERCAT is enabled if GetDepend(['BSP_USING_ETHERCAT']): - group += DefineGroup('EtherCAT_APP', ecat_src, depend = ['BSP_USING_ETHERCAT'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - group += DefineGroup('EtherCAT_SSC', ssc_src, depend = ['BSP_USING_ETHERCAT'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + group += DefineGroup('EtherCAT_APP', ecat_src, depend=['BSP_USING_ETHERCAT'], CPPPATH=CPPPATH, CPPDEFINES=CPPDEFINES) + group += DefineGroup('EtherCAT_SSC', ssc_src, depend=['BSP_USING_ETHERCAT'], CPPPATH=CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript index 48333c4fc8eb..95d48f3a6ef7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript @@ -1,10 +1,18 @@ Import('rtconfig') from building import * +import os +import glob cwd = GetCurrentDir() -# multicore libraries are stored in the nxp-imxrt-sdk package to avoid duplication -sdk_multicore = cwd + '/../packages/nxp-imxrt-sdk-latest/MIMXRT1180/multicore' +# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. +# The directory is named nxp-imxrt-sdk- under packages/. +bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) +sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) +if sdk_candidates: + sdk_multicore = sdk_candidates[0] +else: + sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') # Base multicore sources (always included when BSP_USE_MULTICORE is enabled) src = Split(""" @@ -13,7 +21,7 @@ mcmgr/src/mcmgr_internal_core_api_imxrt1180.c mcmgr/src/mcmgr_mu_internal.c """) -src = [sdk_multicore + '/' + f.strip() for f in src] +src = [os.path.join(sdk_multicore, f.strip()) for f in src] # Add RPMsg-Lite sources if enabled if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): @@ -26,21 +34,21 @@ if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c """) - src += [sdk_multicore + '/' + f.strip() for f in rpmsg_src] + src += [os.path.join(sdk_multicore, f.strip()) for f in rpmsg_src] # Base include paths CPPPATH = [ cwd, - sdk_multicore + '/mcmgr/inc', - sdk_multicore + '/mcmgr/inc/platform/imxrt1180' + os.path.join(sdk_multicore, 'mcmgr', 'inc'), + os.path.join(sdk_multicore, 'mcmgr', 'inc', 'platform', 'imxrt1180'), ] # Add RPMsg-Lite include paths if enabled if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): CPPPATH += [ - sdk_multicore + '/rpmsg-lite/lib/include', - sdk_multicore + '/rpmsg-lite/lib/include/environment/rtthread', - sdk_multicore + '/rpmsg-lite/lib/include/platform/imxrt1180' + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), ] # Define preprocessor macros diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/applInterface.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/coeappl.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_io.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/digital_ioObjects.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecat_def.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatappl.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatcoe.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/ecatslv.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/esc.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/mailbox.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/objdef.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/Src/sdoserv.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xlsx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xlsx similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xlsx rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xlsx diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xml similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SSC/digital_io.xml rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xml diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/digital_io.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ecat_hw.h rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c similarity index 100% rename from bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/ethercat_init.c rename to bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c From 0417321d0d3d9cce85f245f826d42f5c7923c276 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Thu, 6 Aug 2026 17:06:59 +0800 Subject: [PATCH 19/31] Remove EtherCAT-related sources, keep only SConscript. --- .../ethercat/SSC/Src/applInterface.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/coeappl.c | 6 - .../MIMXRT1180/ethercat/SSC/Src/coeappl.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/digital_io.h | 5 - .../ethercat/SSC/Src/digital_ioObjects.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecat_def.h | 6 - .../MIMXRT1180/ethercat/SSC/Src/ecatappl.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecatappl.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecatcoe.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecatcoe.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecatslv.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/ecatslv.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/esc.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/mailbox.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/mailbox.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/objdef.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/objdef.h | 5 - .../MIMXRT1180/ethercat/SSC/Src/sdoserv.c | 5 - .../MIMXRT1180/ethercat/SSC/Src/sdoserv.h | 5 - .../MIMXRT1180/ethercat/SSC/digital_io.xlsx | Bin 22380 -> 0 bytes .../MIMXRT1180/ethercat/SSC/digital_io.xml | 113 ---- .../MIMXRT1180/ethercat/digital_io.c | 415 -------------- .../MIMXRT1180/ethercat/ecat_hw.h | 84 --- .../MIMXRT1180/ethercat/ethercat_init.c | 504 ------------------ 24 files changed, 1213 deletions(-) delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xlsx delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xml delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/applInterface.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c deleted file mode 100644 index c4770e7182bf..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.c +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#error "Please read readme.txt and generate the code by the SSC tool." diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/coeappl.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_io.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/digital_ioObjects.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h deleted file mode 100644 index c4770e7182bf..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecat_def.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#error "Please read readme.txt and generate the code by the SSC tool." diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatappl.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatcoe.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/ecatslv.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/esc.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/mailbox.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/objdef.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.c +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h deleted file mode 100644 index 7fbbf83b96d2..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/Src/sdoserv.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xlsx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/SSC/digital_io.xlsx deleted file mode 100644 index bd8f913e78d7f1a4a52582c6cd13ec100e3659b9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22380 zcmeIabzBu|*FKJPgM@TLCcPb4M(%s#izr8mY$K&^T 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+++ /dev/null @@ -1,113 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8192 - 4 - 4 - - - - - - - diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c deleted file mode 100644 index 5b868209e154..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/digital_io.c +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright 2022-2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*----------------------------------------------------------------------------------------- ------- ------- Includes ------- ------------------------------------------------------------------------------------------*/ -#include "ecat_def.h" - -#include "applInterface.h" - -#define _DIGITAL_IO_ 1 -#include "digital_io.h" -#undef _DIGITAL_IO_ - - -#define GPIO_LED RGPIO4 - -#define GPIO_LED_PIN 27 -//#include "app.h" -/*-------------------------------------------------------------------------------------- ------- ------- local types and defines ------- ---------------------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------------------- ------- ------- local variables and constants ------- ------------------------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------------------- ------- ------- application specific functions ------- ------------------------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------------------- ------- ------- generic functions ------- ------------------------------------------------------------------------------------------*/ - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \brief The function is called when an error state was acknowledged by the master - -*//////////////////////////////////////////////////////////////////////////////////////// - -void APPL_AckErrorInd(UINT16 stateTrans) -{ -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) - - \brief The function is called in the state transition from INIT to PREOP when - all general settings were checked to start the mailbox handler. This function - informs the application about the state transition, the application can refuse - the state transition when returning an AL Status error code. - The return code NOERROR_INWORK can be used, if the application cannot confirm - the state transition immediately, in that case this function will be called cyclically - until a value unequal NOERROR_INWORK is returned - -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StartMailboxHandler(void) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return 0, NOERROR_INWORK - - \brief The function is called in the state transition from PREEOP to INIT - to stop the mailbox handler. This functions informs the application - about the state transition, the application cannot refuse - the state transition. - -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StopMailboxHandler(void) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \param pIntMask pointer to the AL Event Mask which will be written to the AL event Mask - register (0x204) when this function is succeeded. The event mask can be adapted - in this function - \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) - - \brief The function is called in the state transition from PREOP to SAFEOP when - all general settings were checked to start the input handler. This function - informs the application about the state transition, the application can refuse - the state transition when returning an AL Status error code. - The return code NOERROR_INWORK can be used, if the application cannot confirm - the state transition immediately, in that case the application need to be complete - the transition by calling ECAT_StateChange. -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StartInputHandler(UINT16 *pIntMask) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return 0, NOERROR_INWORK - - \brief The function is called in the state transition from SAFEOP to PREEOP - to stop the input handler. This functions informs the application - about the state transition, the application cannot refuse - the state transition. - -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StopInputHandler(void) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return AL Status Code (see ecatslv.h ALSTATUSCODE_....) - - \brief The function is called in the state transition from SAFEOP to OP when - all general settings were checked to start the output handler. This function - informs the application about the state transition, the application can refuse - the state transition when returning an AL Status error code. - The return code NOERROR_INWORK can be used, if the application cannot confirm - the state transition immediately, in that case the application need to be complete - the transition by calling ECAT_StateChange. -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StartOutputHandler(void) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return 0, NOERROR_INWORK - - \brief The function is called in the state transition from OP to SAFEOP - to stop the output handler. This functions informs the application - about the state transition, the application cannot refuse - the state transition. - -*//////////////////////////////////////////////////////////////////////////////////////// - -UINT16 APPL_StopOutputHandler(void) -{ - return ALSTATUSCODE_NOERROR; -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** -\return 0(ALSTATUSCODE_NOERROR), NOERROR_INWORK -\param pInputSize pointer to save the input process data length -\param pOutputSize pointer to save the output process data length - -\brief This function calculates the process data sizes from the actual SM-PDO-Assign - and PDO mapping -*//////////////////////////////////////////////////////////////////////////////////////// -UINT16 APPL_GenerateMapping(UINT16 *pInputSize, UINT16 *pOutputSize) -{ - UINT16 result = ALSTATUSCODE_NOERROR; - UINT16 InputSize = 0; - UINT16 OutputSize = 0; - -#if COE_SUPPORTED - UINT16 PDOAssignEntryCnt = 0; - OBJCONST TOBJECT OBJMEM *pPDO = NULL; - UINT16 PDOSubindex0 = 0; - UINT32 *pPDOEntry = NULL; - UINT16 PDOEntryCnt = 0; - -#if MAX_PD_OUTPUT_SIZE > 0 - /*Scan object 0x1C12 RXPDO assign*/ - for (PDOAssignEntryCnt = 0; PDOAssignEntryCnt < sRxPDOassign.u16SubIndex0; PDOAssignEntryCnt++) - { - pPDO = OBJ_GetObjectHandle(sRxPDOassign.aEntries[PDOAssignEntryCnt]); - if (pPDO != NULL) - { - PDOSubindex0 = *((UINT16 *)pPDO->pVarPtr); - for (PDOEntryCnt = 0; PDOEntryCnt < PDOSubindex0; PDOEntryCnt++) - { - pPDOEntry = (UINT32 *)((UINT16 *)pPDO->pVarPtr + - (OBJ_GetEntryOffset((PDOEntryCnt + 1), pPDO) >> 3) / 2); // goto PDO entry - // we increment the expected output size depending on the mapped Entry - OutputSize += (UINT16)((*pPDOEntry) & 0xFF); - } - } - else - { - /*assigned PDO was not found in object dictionary. return invalid mapping*/ - OutputSize = 0; - result = ALSTATUSCODE_INVALIDOUTPUTMAPPING; - break; - } - } - - OutputSize = (OutputSize + 7) >> 3; -#endif - -#if MAX_PD_INPUT_SIZE > 0 - if (result == 0) - { - /*Scan Object 0x1C13 TXPDO assign*/ - for (PDOAssignEntryCnt = 0; PDOAssignEntryCnt < sTxPDOassign.u16SubIndex0; PDOAssignEntryCnt++) - { - pPDO = OBJ_GetObjectHandle(sTxPDOassign.aEntries[PDOAssignEntryCnt]); - if (pPDO != NULL) - { - PDOSubindex0 = *((UINT16 *)pPDO->pVarPtr); - for (PDOEntryCnt = 0; PDOEntryCnt < PDOSubindex0; PDOEntryCnt++) - { - pPDOEntry = (UINT32 *)((UINT16 *)pPDO->pVarPtr + - (OBJ_GetEntryOffset((PDOEntryCnt + 1), pPDO) >> 3) / 2); // goto PDO entry - // we increment the expected output size depending on the mapped Entry - InputSize += (UINT16)((*pPDOEntry) & 0xFF); - } - } - else - { - /*assigned PDO was not found in object dictionary. return invalid mapping*/ - InputSize = 0; - result = ALSTATUSCODE_INVALIDINPUTMAPPING; - break; - } - } - } - InputSize = (InputSize + 7) >> 3; -#endif - -#else -#if _WIN32 -#pragma message("Warning: Define 'InputSize' and 'OutputSize'.") -#else -#warning "Define 'InputSize' and 'OutputSize'." -#endif -#endif - - *pInputSize = InputSize; - *pOutputSize = OutputSize; - return result; -} - -unsigned char LED_status; -///////////////////////////////////////////////////////////////////////////////////////// -/** -\param pData pointer to input process data - -\brief This function will copies the inputs from the local memory to the ESC memory - to the hardware -*//////////////////////////////////////////////////////////////////////////////////////// -void APPL_InputMapping(UINT16 *pData) -{ - MEMCPY(pData, &LED_status, SIZEOF(LED_status)); -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** -\param pData pointer to output process data - -\brief This function will copies the outputs from the ESC memory to the local memory - to the hardware -*//////////////////////////////////////////////////////////////////////////////////////// -void APPL_OutputMapping(UINT16 *pData) -{ - MEMCPY(&LED_status, pData, SIZEOF(LED_status)); -} - -///////////////////////////////////////////////////////////////////////////////////////// -/** -\brief This function will called from the synchronisation ISR - or from the mainloop if no synchronisation is supported -*//////////////////////////////////////////////////////////////////////////////////////// -void APPL_Application(void) -{ - RGPIO_PinWrite(GPIO_LED, GPIO_LED_PIN, LED_status & 0x01); -} - -#if EXPLICIT_DEVICE_ID -///////////////////////////////////////////////////////////////////////////////////////// -/** - \return The Explicit Device ID of the EtherCAT slave - - \brief Calculate the Explicit Device ID -*//////////////////////////////////////////////////////////////////////////////////////// -UINT16 APPL_GetDeviceID() -{ -#if _WIN32 -#pragma message("Warning: Implement explicit Device ID latching") -#else -#warning "Implement explicit Device ID latching" -#endif - /* Explicit Device 5 is expected by Explicit Device ID conformance tests*/ - return 0x5; -} -#endif - -///////////////////////////////////////////////////////////////////////////////////////// -/** -\param index index of the requested object. -\param subindex subindex of the requested object. -\param objSize size of the requested object data, calculated with OBJ_GetObjectLength -\param pData Pointer to the buffer where the data can be copied to -\param bCompleteAccess Indicates if a complete read of all subindices of the - object shall be done or not - - \return result of the read operation (0 (success) or an abort code (ABORTIDX_.... defined in - sdosrv.h)) - *//////////////////////////////////////////////////////////////////////////////////////// -UINT8 ReadObject0x6000(UINT16 index, UINT8 subindex, UINT32 dataSize, UINT16 MBXMEM *pData, UINT8 bCompleteAccess) -{ - if (bCompleteAccess) - { - return ABORTIDX_UNSUPPORTED_ACCESS; - } - - if (subindex == 0) - { - *pData = 1; - } - else if (subindex == 1) - { - if (dataSize > 0) - { - MEMCPY(pData, &LED_status, dataSize); - } - } - return 0; -} -///////////////////////////////////////////////////////////////////////////////////////// -/** -\param index index of the requested object. -\param subindex subindex of the requested object. -\param objSize size of the requested object data, calculated with OBJ_GetObjectLength -\param pData Pointer to the buffer where the data can be copied to -\param bCompleteAccess Indicates if a complete read of all subindices of the - object shall be done or not - - \return result of the read operation (0 (success) or an abort code (ABORTIDX_.... defined in - sdosrv.h)) - *//////////////////////////////////////////////////////////////////////////////////////// -UINT8 WriteObject0x7000(UINT16 index, UINT8 subindex, UINT32 dataSize, UINT16 MBXMEM *pData, UINT8 bCompleteAccess) -{ - if (bCompleteAccess) - { - /* Complete Access is not supported for object 0x1010 */ - return ABORTIDX_UNSUPPORTED_ACCESS; - } - - if (subindex == 0) - { - /* Subindex 0 is not writable */ - return ABORTIDX_READ_ONLY_ENTRY; - } - - else if (subindex == 1) - { - /* Save the backup entries */ - MEMCPY(&LED_status, pData, SIZEOF(LED_status)); - } - else - { - return ABORTIDX_VALUE_EXCEEDED; - } - RGPIO_PinWrite(GPIO_LED, GPIO_LED_PIN, LED_status & 0x01); - return 0; -} - -#if USE_DEFAULT_MAIN -///////////////////////////////////////////////////////////////////////////////////////// -/** - - \brief This is the main function - -*//////////////////////////////////////////////////////////////////////////////////////// -int ecat_main(void) -{ - /* initialize the Hardware and the EtherCAT Slave Controller */ -#if FC1100_HW - if (HW_Init()) - { - HW_Release(); - return; - } -#else - HW_Init(); -#endif - MainInit(); - - bRunApplication = TRUE; - do - { - MainLoop(); - - } while (bRunApplication == TRUE); - - HW_Release(); - return 0; -} -#endif // #if USE_DEFAULT_MAIN -/** @} */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h deleted file mode 100644 index ceac879a2317..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ecat_hw.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2024 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __ECAT_HW___H__ -#define __ECAT_HW___H__ - -#include "ecat_def.h" -#include "fsl_ecat.h" - -#ifdef ECAT -/**< \brief Returns the first 16Bit of the AL Event register (0x220)*/ -#define HW_GetALEventRegister() ECAT_GetALEventRegister(ECAT) -#define HW_GetALEventRegister_Isr() ECAT_GetALEventRegister(ECAT) - -/**< \brief Generic ESC (register and DPRAM) read access.*/ -#define HW_EscRead(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) -#define HW_EscReadIsr(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) - -/**< \brief 32Bit specific ESC (register and DPRAM) read access.*/ -#define HW_EscReadDWord(DWordValue, Address) ECAT_EscReadDWord(ECAT, DWordValue, Address) -#define HW_EscReadDWordIsr(DWordValue, Address) ECAT_EscReadDWord(ECAT, DWordValue, Address) - -/**< \brief Macro to copy data from the application mailbox memory(not the ESC memory, this access is handled by - * HW_EscRead).*/ -#define HW_EscReadMbxMem(pData, Address, Len) ECAT_EscRead(ECAT, pData, Address, Len) - -/**< \brief Generic ESC (register and DPRAM) write access.*/ -#define HW_EscWrite(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) -#define HW_EscWriteIsr(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) - -/**< \brief 32Bit specific ESC (register and DPRAM) write access.*/ -#define HW_EscWriteDWord(DWordValue, Address) ECAT_EscWriteDWord(ECAT, DWordValue, Address) -#define HW_EscWriteDWordIsr(DWordValue, Address) ECAT_EscWriteDWord(ECAT, DWordValue, Address) - -/**< \brief Macro to copy data from the application mailbox memory (not the ESC memory, this access is handled by - * HW_EscWrite).*/ -#define HW_EscWriteMbxMem(pData, Address, Len) ECAT_EscWrite(ECAT, pData, Address, Len) - -#else -/**< \brief Returns the first 16Bit of the AL Event register (0x220)*/ -#define HW_GetALEventRegister() ECAT_GetALEventRegister(ETHERCAT) -#define HW_GetALEventRegister_Isr() ECAT_GetALEventRegister(ETHERCAT) - -/**< \brief Generic ESC (register and DPRAM) read access.*/ -#define HW_EscRead(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) -#define HW_EscReadIsr(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) - -/**< \brief 32Bit specific ESC (register and DPRAM) read access.*/ -#define HW_EscReadDWord(DWordValue, Address) ECAT_EscReadDWord(ETHERCAT, DWordValue, Address) -#define HW_EscReadDWordIsr(DWordValue, Address) ECAT_EscReadDWord(ETHERCAT, DWordValue, Address) - -/**< \brief Macro to copy data from the application mailbox memory(not the ESC memory, this access is handled by - * HW_EscRead).*/ -#define HW_EscReadMbxMem(pData, Address, Len) ECAT_EscRead(ETHERCAT, pData, Address, Len) - -/**< \brief Generic ESC (register and DPRAM) write access.*/ -#define HW_EscWrite(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) -#define HW_EscWriteIsr(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) - -/**< \brief 32Bit specific ESC (register and DPRAM) write access.*/ -#define HW_EscWriteDWord(DWordValue, Address) ECAT_EscWriteDWord(ETHERCAT, DWordValue, Address) -#define HW_EscWriteDWordIsr(DWordValue, Address) ECAT_EscWriteDWord(ETHERCAT, DWordValue, Address) - -/**< \brief Macro to copy data from the application mailbox memory (not the ESC memory, this access is handled by - * HW_EscWrite).*/ -#define HW_EscWriteMbxMem(pData, Address, Len) ECAT_EscWrite(ETHERCAT, pData, Address, Len) -#endif - -#define ECAT_TIMER_INC_P_MS 0x01 - -UINT16 HW_Init(void); -void HW_Release(void); - -UINT16 HW_GetTimer(void); -void HW_ClearTimer(void); -void ENABLE_ESC_INT(void); -void DISABLE_ESC_INT(void); -void HW_SetLed(UINT8 RunLed, UINT8 ErrorLed); - -#endif /* __ECAT_HW___H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c deleted file mode 100644 index fa1c4f813bdc..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/packages/nxp-imxrt-sdk-latest/MIMXRT1180/ethercat/ethercat_init.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright 2022-2024 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pin_mux.h" -#include "clock_config.h" -#include "board.h" -#include "fsl_xbar.h" -#include "fsl_iomuxc.h" -#include "fsl_ecat.h" -#include "fsl_gpt.h" -#include "fsl_common.h" - -#include "ecat_def.h" -#include "ecatslv.h" -#include "ecat_hw.h" -#include "ecatappl.h" - - -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_PhyInitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27} - - {pin_num: M14, peripheral: RGPIO4, signal: 'gpio_io, 26', pin_signal: GPIO_AD_26} - - {pin_num: J16, peripheral: XBAR1, signal: 'IN, 17', pin_signal: GPIO_AD_33} - - {pin_num: J15, peripheral: XBAR1, signal: 'IN, 18', pin_signal: GPIO_AD_34} - - {pin_num: N15, peripheral: RGPIO4, signal: 'gpio_io, 13', pin_signal: GPIO_AD_13} - - {pin_num: M15, peripheral: RGPIO4, signal: 'gpio_io, 25', pin_signal: GPIO_AD_25} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_PhyInitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_PhyInitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ - - BLK_CTRL_WAKEUPMIX->XBAR_DIR_CTRL1 = ((BLK_CTRL_WAKEUPMIX->XBAR_DIR_CTRL1 & - (~(BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_MASK | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_MASK))) /* Mask bits to zero which are setting */ - | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17(0x00U) /* IOMUXC XBAR_INOUT17 function direction select: XBAR_INOUT as input */ - | BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18(0x00U) /* IOMUXC XBAR_INOUT18 function direction select: XBAR_INOUT as input */ - ); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_13_GPIO4_IO13, /* GPIO_AD_13 is configured as GPIO4_IO13 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_25_GPIO4_IO25, /* GPIO_AD_25 is configured as GPIO4_IO25 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_26_GPIO4_IO26, /* GPIO_AD_26 is configured as GPIO4_IO26 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17, /* GPIO_AD_33 is configured as XBAR1_XBAR_INOUT17 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18, /* GPIO_AD_34 is configured as XBAR1_XBAR_INOUT18 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_ECAT_MDIO_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: L17, peripheral: ECAT, signal: MDC, pin_signal: GPIO_AD_30, pull_up_down_config: Pull_Up, slew_rate: Slow} - - {pin_num: K17, peripheral: ECAT, signal: MDIO, pin_signal: GPIO_AD_31, pull_up_down_config: Pull_Up, slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_ECAT_MDIO_InitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_ECAT_MDIO_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_30_ECAT_MCLK, /* GPIO_AD_30 is configured as ECAT_MCLK */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_31_ECAT_MDIO, /* GPIO_AD_31 is configured as ECAT_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_30_ECAT_MCLK, /* GPIO_AD_30 PAD functional properties : */ - 0x0EU); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Disabled - Force ibe off Field: Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_31_ECAT_MDIO, /* GPIO_AD_31 PAD functional properties : */ - 0x0EU); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Disabled - Force ibe off Field: Disabled */ -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_Port0_RMII_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: T4, peripheral: ECAT, signal: 'PT0_TXD, 0', pin_signal: GPIO_EMC_B2_05} - - {pin_num: T6, peripheral: ECAT, signal: 'PT0_TXD, 1', pin_signal: GPIO_EMC_B2_06} - - {pin_num: T7, peripheral: ECAT, signal: PT0_TX_EN, pin_signal: GPIO_EMC_B2_07} - - {pin_num: U4, peripheral: ECAT, signal: PT0_TX_CLK, pin_signal: GPIO_EMC_B2_08, software_input_on: Enable} - - {pin_num: U5, peripheral: ECAT, signal: 'PT0_RXD, 0', pin_signal: GPIO_EMC_B2_09} - - {pin_num: U6, peripheral: ECAT, signal: 'PT0_RXD, 1', pin_signal: GPIO_EMC_B2_10} - - {pin_num: P6, peripheral: ECAT, signal: PT0_RX_DV, pin_signal: GPIO_EMC_B2_11} - - {pin_num: R5, peripheral: ECAT, signal: PT0_RX_ER, pin_signal: GPIO_EMC_B2_12} - - {pin_num: N17, peripheral: ECAT, signal: 'LINK_MII, 0', pin_signal: GPIO_AD_16, pull_keeper_select: Keeper} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_Port0_RMII_InitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_Port0_RMII_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_16_ECAT_LINK_0, /* GPIO_AD_16 is configured as ECAT_LINK_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_05_ECAT_TX_DATA0_0, /* GPIO_EMC_B2_05 is configured as ECAT_TX_DATA0_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_06_ECAT_TX_DATA1_0, /* GPIO_EMC_B2_06 is configured as ECAT_TX_DATA1_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_07_ECAT_TX_EN_0, /* GPIO_EMC_B2_07 is configured as ECAT_TX_EN_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_08_ECAT_TX_CLK_0, /* GPIO_EMC_B2_08 is configured as ECAT_TX_CLK_0 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_08 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_09_ECAT_RX_DATA0_0, /* GPIO_EMC_B2_09 is configured as ECAT_RX_DATA0_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_10_ECAT_RX_DATA1_0, /* GPIO_EMC_B2_10 is configured as ECAT_RX_DATA1_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_11_ECAT_RX_DV_0, /* GPIO_EMC_B2_11 is configured as ECAT_RX_DV_0 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_12_ECAT_PT0_RX_ER, /* GPIO_EMC_B2_12 is configured as ECAT_PT0_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_16_ECAT_LINK_0, /* GPIO_AD_16 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Force ibe off Field: Disabled */ -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_Port1_RMII_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: R6, peripheral: ECAT, signal: 'PT1_TXD, 0', pin_signal: GPIO_EMC_B2_13} - - {pin_num: N8, peripheral: ECAT, signal: 'PT1_TXD, 1', pin_signal: GPIO_EMC_B2_14} - - {pin_num: R4, peripheral: ECAT, signal: PT1_TX_EN, pin_signal: GPIO_EMC_B2_15} - - {pin_num: R7, peripheral: ECAT, signal: PT1_TX_CLK, pin_signal: GPIO_EMC_B2_16, software_input_on: Enable} - - {pin_num: U7, peripheral: ECAT, signal: 'PT1_RXD, 0', pin_signal: GPIO_EMC_B2_17} - - {pin_num: P8, peripheral: ECAT, signal: 'PT1_RXD, 1', pin_signal: GPIO_EMC_B2_18} - - {pin_num: U8, peripheral: ECAT, signal: PT1_RX_DV, pin_signal: GPIO_EMC_B2_19} - - {pin_num: R8, peripheral: ECAT, signal: PT1_RX_ER, pin_signal: GPIO_EMC_B2_20} - - {pin_num: M17, peripheral: ECAT, signal: 'LINK_MII, 1', pin_signal: GPIO_AD_17, pull_keeper_select: Keeper} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_Port1_RMII_InitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_Port1_RMII_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_17_ECAT_LINK_1, /* GPIO_AD_17 is configured as ECAT_LINK_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_13_ECAT_TX_DATA0_1, /* GPIO_EMC_B2_13 is configured as ECAT_TX_DATA0_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_14_ECAT_TX_DATA1_1, /* GPIO_EMC_B2_14 is configured as ECAT_TX_DATA1_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_15_ECAT_TX_EN_1, /* GPIO_EMC_B2_15 is configured as ECAT_TX_EN_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_16_ECAT_TX_CLK_1, /* GPIO_EMC_B2_16 is configured as ECAT_TX_CLK_1 */ - 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_B2_16 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_17_ECAT_RX_DATA0_1, /* GPIO_EMC_B2_17 is configured as ECAT_RX_DATA0_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_18_ECAT_RX_DATA1_1, /* GPIO_EMC_B2_18 is configured as ECAT_RX_DATA1_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_19_ECAT_RX_DV_1, /* GPIO_EMC_B2_19 is configured as ECAT_RX_DV_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_B2_20_ECAT_RX_ER_1, /* GPIO_EMC_B2_20 is configured as ECAT_RX_ER_1 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_17_ECAT_LINK_1, /* GPIO_AD_17 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled - Force ibe off Field: Disabled */ -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_ECAT_I2C_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} -- pin_list: - - {pin_num: K16, peripheral: ECAT, signal: SCL, pin_signal: GPIO_AD_18, pull_up_down_config: Pull_Up, open_drain: Enable, slew_rate: Slow} - - {pin_num: L13, peripheral: ECAT, signal: SDA, pin_signal: GPIO_AD_19, pull_up_down_config: Pull_Up, open_drain: Enable, slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_ECAT_I2C_InitPins, assigned for the Cortex-M7F core. - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_ECAT_I2C_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_18_ECAT_PROM_CLK, /* GPIO_AD_18 is configured as ECAT_PROM_CLK */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_19_ECAT_PROM_DATA, /* GPIO_AD_19 is configured as ECAT_PROM_DATA */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_18_ECAT_PROM_CLK, /* GPIO_AD_18 PAD functional properties : */ - 0x1EU); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled - Force ibe off Field: Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_19_ECAT_PROM_DATA, /* GPIO_AD_19 PAD functional properties : */ - 0x1EU); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain Field: Enabled - Force ibe off Field: Disabled */ -} - - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void Ecat_InitBootPins(void) { - BOARD_PhyInitPins(); - BOARD_ECAT_MDIO_InitPins(); - BOARD_Port0_RMII_InitPins(); - BOARD_Port1_RMII_InitPins(); - BOARD_ECAT_I2C_InitPins(); -} - -UINT32 EcatTimerCnt; - -static void Ecat_KickOff(void) -{ - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK | - BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= - (BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_MASK | BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_MASK); - - BLK_CTRL_WAKEUPMIX->MISC_IO_CTRL &= ~(1 << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_SHIFT); - BLK_CTRL_WAKEUPMIX->MISC_IO_CTRL &= ~(1 << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_SHIFT); - - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= (1 << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_SHIFT); - - SRC_GENERAL_REG->SRMASK &= ~(0x1 << SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_SHIFT); - - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= (BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC(2)); - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_MASK; - BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_MASK; -} - -void rt_ethercat_init() -{ - UINT16 HW_Init(void); -} - -UINT16 HW_Init(void) -{ - UINT32 intMask; - UINT16 led_startus = 0; - xbar_control_config_t xbaraConfig; - uint32_t gptFreq; - gpt_config_t gptConfig; - rgpio_pin_config_t pinConfig = {.pinDirection = kRGPIO_DigitalOutput, .outputLogic = 0}; - - /* Init board hardware. */ - Ecat_InitBootPins(); - - //PRINTF("Start the SSC digital_io example...\r\n"); - - /* Reset ecat PHY */ - RGPIO_PinInit(RGPIO4, 25, &pinConfig); - RGPIO_PinInit(RGPIO4, 13, &pinConfig); - SDK_DelayAtLeastUs(15000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - Ecat_KickOff(); - - RGPIO_PinWrite(RGPIO4, 25, 1); - RGPIO_PinWrite(RGPIO4, 13, 1); - SDK_DelayAtLeastUs(90000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /*set port0 page register*/ - ECAT_EscMdioWrite(ECAT, 0x00, 31, 0x07); - - /*enable prot0 coustomized LED */ - ECAT_EscMdioRead(ECAT, 0x00, 19, &led_startus); - ECAT_EscMdioWrite(ECAT, 0x00, 19, led_startus | (1 << 3)); - - /*Set led1 to LINK100 and set led0 to ACK*/ - ECAT_EscMdioRead(ECAT, 0x00, 17, &led_startus); - ECAT_EscMdioWrite(ECAT, 0x00, 17, led_startus | (1 << 3) | (1 << 5)); - - /*set port1 page register*/ - ECAT_EscMdioWrite(ECAT, 0x01, 31, 0x07); - - /*enable prot1 coustomized LED */ - ECAT_EscMdioRead(ECAT, 0x01, 19, &led_startus); - ECAT_EscMdioWrite(ECAT, 0x01, 19, led_startus | (1 << 3)); - - /*Set led1 to LINK100 and set led0 to ACK*/ - ECAT_EscMdioRead(ECAT, 0x01, 17, &led_startus); - ECAT_EscMdioWrite(ECAT, 0x01, 17, led_startus | (1 << 3) | (1 << 5)); - - RGPIO_PinInit(RGPIO4, 27, &pinConfig); - RGPIO_PinInit(RGPIO4, 26, &pinConfig); - - /*config Sync0/1 IRQ*/ - XBAR_Init(kXBAR_DSC1); - - XBAR_SetSignalsConnection(kXBAR1_InputEcatSyncOut0, kXBAR1_OutputDma4MuxReq154); - BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 = 0x0; - xbaraConfig.activeEdge = kXBAR_EdgeRising; - xbaraConfig.requestType = kXBAR_RequestInterruptEnable; - XBAR_SetOutputSignalConfig(kXBAR1_OutputDma4MuxReq154, &xbaraConfig); - BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 |= 0xff << 16; - BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL1 |= 0xff << 8; - BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL2 |= 3; - BLK_CTRL_WAKEUPMIX->XBAR_TRIG_SYNC_CTRL2 |= 3 << 4; - - XBAR_SetSignalsConnection(kXBAR1_InputEcatSyncOut1, kXBAR1_OutputDma4MuxReq155); - xbaraConfig.activeEdge = kXBAR_EdgeRising; - xbaraConfig.requestType = kXBAR_RequestInterruptEnable; - XBAR_SetOutputSignalConfig(kXBAR1_OutputDma4MuxReq155, &xbaraConfig); - - do - { - intMask = 0x93; - HW_EscWriteDWord(intMask, ESC_AL_EVENTMASK_OFFSET); - intMask = 0; - HW_EscReadDWord(intMask, ESC_AL_EVENTMASK_OFFSET); - } while (intMask != 0x93); - - intMask = 0x00; - - HW_EscWriteDWord(intMask, ESC_AL_EVENTMASK_OFFSET); - - /*Enable GPT1*/ - GPT_GetDefaultConfig(&gptConfig); - GPT_Init(GPT1, &gptConfig); - gptFreq = CLOCK_GetRootClockFreq(kCLOCK_Root_Gpt1); - GPT_SetClockDivider(GPT1, 100); - GPT_SetOutputCompareValue(GPT1, kGPT_OutputCompare_Channel1, gptFreq / 100000); - GPT_EnableInterrupts(GPT1, kGPT_OutputCompare1InterruptEnable); - EnableIRQ(GPT1_IRQn); - - /*Enable PDI IRQ*/ - EnableIRQ(ECAT_INT_IRQn); - NVIC_EnableIRQ(XBAR1_CH0_CH1_IRQn); - GPT_StartTimer(GPT1); - return 0; -} - -void ECAT_INT_IRQHandler(void) -{ - PDI_Isr(); - - SDK_ISR_EXIT_BARRIER; -} - -/*config Sync0/1 IRQ*/ -void XBAR1_CH0_CH1_IRQHandler(void) -{ - bool status; - XBAR_GetOutputStatusFlag(kXBAR1_OutputDma4MuxReq154, &status); - if (status) - { - XBAR_ClearOutputStatusFlag(kXBAR1_OutputDma4MuxReq154); - Sync0_Isr(); - } - - XBAR_GetOutputStatusFlag(kXBAR1_OutputDma4MuxReq155, &status); - if (status) - { - XBAR_ClearOutputStatusFlag(kXBAR1_OutputDma4MuxReq155); - Sync1_Isr(); - } - - SDK_ISR_EXIT_BARRIER; -} - -void HW_Release(void) -{ -} - -void GPT1_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); -#if ECAT_TIMER_INT - ECAT_CheckTimer(); -#endif - EcatTimerCnt++; - - SDK_ISR_EXIT_BARRIER; -} - -UINT16 HW_GetTimer(void) -{ - return EcatTimerCnt; -} - -void HW_ClearTimer(void) -{ - EcatTimerCnt = 0; -} - -void ENABLE_ESC_INT(void) -{ - NVIC_EnableIRQ(ECAT_INT_IRQn); - NVIC_EnableIRQ(XBAR1_CH0_CH1_IRQn); - NVIC_EnableIRQ(GPT1_IRQn); -} - -void DISABLE_ESC_INT(void) -{ - NVIC_DisableIRQ(XBAR1_CH0_CH1_IRQn); - NVIC_DisableIRQ(ECAT_INT_IRQn); - NVIC_DisableIRQ(GPT1_IRQn); -} - -void HW_SetLed(UINT8 RunLed, UINT8 ErrorLed) -{ -} From 8c0f141b0f7988b85947431e6faf1c01af496f2c Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Thu, 6 Aug 2026 17:52:47 +0800 Subject: [PATCH 20/31] updated ci.attachconfig.yml for cm33 and cm7 projects. --- .../cm33/.ci/attachconfig/ci.attachconfig.yml | 12 ++++++++-- .../cm7/.ci/attachconfig/ci.attachconfig.yml | 22 ++++++++++++++++++- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml index 3313131adbc0..d8b14a2d8f25 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml @@ -5,7 +5,7 @@ scons.args: &scons # ------ component CI ------ # ------ Peripheral CI ------ -Peripheral.flash_fs: +Peripheral.qspi_flash_FS: <<: *scons kconfig: - CONFIG_BSP_USING_QSPI_FLASH_FS=y @@ -22,4 +22,12 @@ Peripheral.lpadc1: kconfig: - CONFIG_RT_USING_ADC=y - CONFIG_BSP_USING_LPADC=y - - CONFIG_BSP_USING_LPADC1=y \ No newline at end of file + - CONFIG_BSP_USING_LPADC1=y +Peripheral.usb_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_USB=y +Peripheral.multicore: + <<: *scons + kconfig: + - CONFIG_BSP_USE_MULTICORE=y \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml index 5a48fc80d438..c85b48a3e77a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -17,4 +17,24 @@ Peripheral.hyperflash: kconfig: - CONFIG_BSP_USING_FLEXSPI=y - CONFIG_BSP_USING_FLEXSPI1=y - - CONFIG_BSP_USING_OSPI_FLASH=y \ No newline at end of file + - CONFIG_BSP_USING_OSPI_FLASH=y +Peripheral.qspi_flash_FS: + <<: *scons + kconfig: + - CONFIG_BSP_USING_QSPI_FLASH_FS=y +Peripheral.usb_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_USB=y +Peripheral.netc: + <<: *scons + kconfig: + - CONFIG_BSP_USING_ETH=y +Peripheral.ethercat: + <<: *scons + kconfig: + - CONFIG_BSP_USING_ETHERCAT=y +Peripheral.multicore: + <<: *scons + kconfig: + - CONFIG_BSP_USE_MULTICORE=y \ No newline at end of file From 780124508a3e6917f9bd78031f0a7ed51b69894c Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 10:35:57 +0800 Subject: [PATCH 21/31] Fixed BSP_ROOT path error in rtconfig.py. --- bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py | 2 +- bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py index 4c71e5232c82..ab1be162d20f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py @@ -265,6 +265,6 @@ def dist_handle(BSP_ROOT, dist_dir): import sys cwd_path = os.getcwd() # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(os.path.dirname(BSP_ROOT)), 'tools')) from sdk_dist import dist_do_building dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py index a8a5831225eb..5cd0142118f8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py @@ -279,6 +279,6 @@ def dist_handle(BSP_ROOT, dist_dir): import sys cwd_path = os.getcwd() # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(os.path.dirname(BSP_ROOT)), 'tools')) from sdk_dist import dist_do_building dist_do_building(BSP_ROOT, dist_dir) From 6007cb51b5b6b310518a610139ba3063f7b1d069 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 16:21:12 +0800 Subject: [PATCH 22/31] Added drv_netc.c and updated SConscript for netc. --- .../imx/imxrt/libraries/drivers/SConscript | 7 +- .../imx/imxrt/libraries/drivers/drv_netc.c | 1219 +++++++++++++++++ 2 files changed, 1224 insertions(+), 2 deletions(-) create mode 100644 bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript index 797b0beed987..fd9034f2fbcb 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript +++ b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript @@ -52,9 +52,12 @@ if GetDepend('BSP_USING_LCD'): src += ['drv_lcd.c'] if GetDepend('BSP_USING_ETH'): - src += ['drv_eth.c'] + if GetDepend('SOC_IMXRT1180_SERIES'): + src += ['drv_netc.c'] + else: + src += ['drv_eth.c'] -if GetDepend('BSP_USING_PHY'): +if GetDepend('BSP_USING_PHY') and not GetDepend('SOC_IMXRT1180_SERIES'): src += ['drv_mdio.c'] if GetDepend('PHY_USING_KSZ8081'): src += ['drv_ksz8081.c'] diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c new file mode 100644 index 000000000000..68f22aefe449 --- /dev/null +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c @@ -0,0 +1,1219 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-05 Tim First version for i.MXRT1180 NETC EP0 + * 2026-06-09 Tim Add Switch support + */ + +#include +#include +#include +#include "board.h" + +#ifdef RT_USING_LWIP + +#include +#include + +#ifndef NETC_RX_ZERO_COPY +#define NETC_RX_ZERO_COPY 1 +#endif + +#ifndef NETC_USE_SWT +#define NETC_USE_SWT 0 +#endif + +#if NETC_RX_ZERO_COPY && !LWIP_SUPPORT_CUSTOM_PBUF +#error "NETC RX zero-copy requires LWIP_SUPPORT_CUSTOM_PBUF=1 in lwipopts.h" +#endif + +#include "fsl_common.h" +#include "fsl_clock.h" +#include "fsl_netc_soc.h" +#include "fsl_netc_endpoint.h" +#if NETC_USE_SWT +#if defined(FSL_FEATURE_NETC_HAS_NO_SWITCH) && FSL_FEATURE_NETC_HAS_NO_SWITCH +#error "NETC_USE_SWT requires NETC switch hardware support" +#endif +#include "fsl_netc_switch.h" +#endif +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG +#include "fsl_netc_tag.h" +#endif +#include "fsl_netc_mdio.h" +#include "fsl_msgintr.h" + +#define LOG_TAG "drv.netc" +#include "drv_log.h" + +#define NETC_RING_ID 0U +#define NETC_RXBD_NUM 8U +#define NETC_TXBD_NUM 8U +#define NETC_CMDBD_NUM 8U +#define NETC_RXBUFF_SIZE 1536U +#define NETC_BUFF_ALIGNMENT 64U +#define NETC_FRAME_MAX_FRAMELEN 1518U +#define NETC_RXBUFF_ALIGNED_SIZE \ + (((NETC_RXBUFF_SIZE + NETC_BUFF_ALIGNMENT - 1U) / NETC_BUFF_ALIGNMENT) * NETC_BUFF_ALIGNMENT) +#define NETC_MAX_BUFFERS_PER_FRAME \ + ((NETC_FRAME_MAX_FRAMELEN + NETC_RXBUFF_ALIGNED_SIZE - 1U) / NETC_RXBUFF_ALIGNED_SIZE) +#define NETC_PHY_STATUS_REG 0x01U +#define NETC_PHY_LINK_UP_MASK 0x0004U +#define NETC_PHY_POLL_DELAY_TICK (RT_TICK_PER_SECOND) +#define NETC_TX_TIMEOUT_TICK (RT_TICK_PER_SECOND) + +#if NETC_RXBD_NUM < NETC_MAX_BUFFERS_PER_FRAME +#error "NETC_RXBD_NUM < NETC_MAX_BUFFERS_PER_FRAME" +#endif + +#ifndef NETC_RXBUFF_NUM +#define NETC_RXBUFF_NUM (NETC_RXBD_NUM + 5U) +#endif + +#if NETC_RX_ZERO_COPY && (NETC_RXBUFF_NUM < (NETC_RXBD_NUM + NETC_MAX_BUFFERS_PER_FRAME)) +#error "NETC_RXBUFF_NUM < (NETC_RXBD_NUM + NETC_MAX_BUFFERS_PER_FRAME)" +#endif + +#if NETC_RX_ZERO_COPY +#define NETC_RXBUFF_TOTAL_NUM NETC_RXBUFF_NUM +#else +#define NETC_RXBUFF_TOTAL_NUM NETC_RXBD_NUM +#endif + +#define NETC_MII_MODE kNETC_RmiiMode +#define NETC_LINK_SPEED kNETC_MiiSpeed100M +#define NETC_LINK_DUPLEX kNETC_MiiFullDuplex + +#if NETC_USE_SWT +#define NETC_PSI kNETC_ENETC1PSI0 +#ifndef NETC_PHY_ADDR +#define NETC_PHY_ADDR BOARD_SWT_PORT0_PHY_ADDR +#endif +#ifndef NETC_SWT_MAX_PORT_NUM +#define NETC_SWT_MAX_PORT_NUM 4U +#endif +#ifndef NETC_SWT_USED_PORT_BITMAP +#define NETC_SWT_USED_PORT_BITMAP 0x5U +#endif +#ifndef NETC_SWT_PSEUDO_PORT +#define NETC_SWT_PSEUDO_PORT 0x4U +#endif +#ifndef NETC_SWT_TX_PORT +#define NETC_SWT_TX_PORT kNETC_SWITCH0Port0 +#endif +#else +#define NETC_PSI kNETC_ENETC0PSI0 +#ifndef NETC_PHY_ADDR +#define NETC_PHY_ADDR BOARD_EP0_PHY_ADDR +#endif +#endif + +#define NETC_MSGINTR MSGINTR1 +#define NETC_MSGINTR_IRQ MSGINTR1_IRQn + +#define NETC_MSIX_ENTRY_NUM 2U +#define TX_MSIX_ENTRY_IDX 0U +#define RX_MSIX_ENTRY_IDX 1U +#define SI_COM_MSIX_ENTRY_IDX 2U +#define TX_INTR_MSG_DATA 1U +#define RX_INTR_MSG_DATA 2U +#define SI_COM_INTR_MSG_DATA 3U + +#define NETC_DEFAULT_MAC0 0x54U +#define NETC_DEFAULT_MAC1 0x27U +#define NETC_DEFAULT_MAC2 0x8DU +#define NETC_DEFAULT_MAC3 0x11U +#define NETC_DEFAULT_MAC4 0x80U +#define NETC_DEFAULT_MAC5 0x00U + +#ifndef RT_NTCP_THREAD_STACK_SIZE +#define RT_NTCP_THREAD_STACK_SIZE 4096 +#endif + +#ifndef RT_NTCP_THREAD_PRIORITY +#define RT_NTCP_THREAD_PRIORITY 15 +#endif + +struct rt_imxrt_netc +{ + struct eth_device parent; + + ep_handle_t ep_handle; +#if NETC_USE_SWT + swt_handle_t swt_handle; +#endif + netc_mdio_handle_t mdio_handle; + + struct rt_mutex lock; + struct rt_semaphore tx_isr_sem; + + rt_bool_t hw_inited; + rt_bool_t mdio_inited; + rt_bool_t link_up; +#if NETC_USE_SWT + rt_bool_t swt_inited; +#endif + + rt_uint8_t dev_addr[6]; +}; + +#if NETC_RX_ZERO_COPY +typedef struct netc_rx_pbuf_wrapper +{ + struct pbuf_custom custom; + void *buffer; + volatile rt_bool_t buffer_used; +#if NETC_USE_SWT + swt_handle_t *handle; +#else + ep_handle_t *handle; +#endif + rt_uint8_t ring; +} netc_rx_pbuf_wrapper_t; +#endif + +AT_NONCACHEABLE_SECTION_ALIGN(static netc_rx_bd_t g_netc_rx_bd[NETC_RXBD_NUM], 128); +AT_NONCACHEABLE_SECTION_ALIGN(static netc_tx_bd_t g_netc_tx_bd[NETC_TXBD_NUM], 128); +AT_NONCACHEABLE_SECTION_ALIGN(static netc_cmd_bd_t g_netc_cmd_bd[NETC_CMDBD_NUM], 128); +#if NETC_USE_SWT +AT_NONCACHEABLE_SECTION_ALIGN(static netc_cmd_bd_t g_netc_swt_cmd_bd[NETC_CMDBD_NUM], 128); +#endif +AT_NONCACHEABLE_SECTION_ALIGN(static rt_uint8_t g_netc_rx_buf[NETC_RXBUFF_TOTAL_NUM][NETC_RXBUFF_SIZE], + NETC_BUFF_ALIGNMENT); + +static uint64_t g_netc_rx_buf_addr[NETC_RXBD_NUM]; +static netc_tx_frame_info_t g_netc_tx_dirty[NETC_TXBD_NUM]; +static netc_msix_entry_t g_netc_msix_entry[NETC_MSIX_ENTRY_NUM]; + +#if NETC_USE_SWT +static swt_config_t g_netc_swt_config; +static swt_transfer_config_t g_netc_swt_transfer_config; +#endif + +#if NETC_RX_ZERO_COPY +static netc_rx_pbuf_wrapper_t g_netc_rx_pbufs[NETC_RXBUFF_TOTAL_NUM]; +#endif + +static struct rt_imxrt_netc imxrt_netc_device; + +#if NETC_RX_ZERO_COPY +#if NETC_USE_SWT +static void *_netc_rx_buff_alloc(swt_handle_t *handle, uint32_t length, void *userData) +#else +static void *_netc_rx_buff_alloc(ep_handle_t *handle, uint8_t ring, uint32_t length, void *userData) +#endif +{ + netc_rx_pbuf_wrapper_t *rx_pbufs = (netc_rx_pbuf_wrapper_t *)userData; + void *buffer = RT_NULL; + rt_base_t level; + rt_uint32_t i; + + RT_UNUSED(handle); +#if !NETC_USE_SWT + RT_UNUSED(ring); +#endif + + if ((rx_pbufs == RT_NULL) || (length > NETC_RXBUFF_SIZE)) + { + return RT_NULL; + } + + level = rt_hw_interrupt_disable(); + for (i = 0; i < NETC_RXBUFF_TOTAL_NUM; i++) + { + if (!rx_pbufs[i].buffer_used) + { + rx_pbufs[i].buffer_used = RT_TRUE; + buffer = rx_pbufs[i].buffer; + break; + } + } + rt_hw_interrupt_enable(level); + + return buffer; +} + +#if NETC_USE_SWT +static void _netc_rx_buff_free(swt_handle_t *handle, void *address, void *userData) +#else +static void _netc_rx_buff_free(ep_handle_t *handle, uint8_t ring, void *address, void *userData) +#endif +{ + netc_rx_pbuf_wrapper_t *rx_pbufs = (netc_rx_pbuf_wrapper_t *)userData; + rt_base_t level; + rt_uint32_t i; + +#if !NETC_USE_SWT + RT_UNUSED(ring); +#endif + + if ((rx_pbufs == RT_NULL) && (handle != RT_NULL)) + { + rx_pbufs = (netc_rx_pbuf_wrapper_t *)handle->cfg.userData; + } + + if ((rx_pbufs == RT_NULL) || (address == RT_NULL)) + { + return; + } + + level = rt_hw_interrupt_disable(); + for (i = 0; i < NETC_RXBUFF_TOTAL_NUM; i++) + { + if (rx_pbufs[i].buffer == address) + { + rx_pbufs[i].buffer_used = RT_FALSE; + break; + } + } + rt_hw_interrupt_enable(level); + + if (i >= NETC_RXBUFF_TOTAL_NUM) + { + LOG_W("unknown NETC Rx zero-copy buffer: %p", address); + } +} + +static void _netc_rx_pbuf_free(struct pbuf *p) +{ + netc_rx_pbuf_wrapper_t *rx_pbuf = (netc_rx_pbuf_wrapper_t *)p; + +#if NETC_USE_SWT + _netc_rx_buff_free(rx_pbuf->handle, rx_pbuf->buffer, RT_NULL); +#else + _netc_rx_buff_free(rx_pbuf->handle, rx_pbuf->ring, rx_pbuf->buffer, RT_NULL); +#endif +} + +static netc_rx_pbuf_wrapper_t *_netc_find_rx_pbuf(void *buffer) +{ + rt_uint32_t i; + + for (i = 0; i < NETC_RXBUFF_TOTAL_NUM; i++) + { + if (g_netc_rx_pbufs[i].buffer == buffer) + { + return &g_netc_rx_pbufs[i]; + } + } + + return RT_NULL; +} + +static void _netc_rx_release_frame_buffers(struct rt_imxrt_netc *netc, + netc_frame_struct_t *frame, + rt_uint16_t start) +{ + rt_uint16_t i; + + for (i = start; i < frame->length; i++) + { + if (frame->buffArray[i].buffer != RT_NULL) + { +#if NETC_USE_SWT + _netc_rx_buff_free(&netc->swt_handle, + frame->buffArray[i].buffer, + netc->swt_handle.cfg.userData); +#else + _netc_rx_buff_free(&netc->ep_handle, + NETC_RING_ID, + frame->buffArray[i].buffer, + netc->ep_handle.cfg.userData); +#endif + } + } +} + +static struct pbuf *_netc_rx_frame_to_pbufs(struct rt_imxrt_netc *netc, netc_frame_struct_t *frame) +{ + struct pbuf *p_root = RT_NULL; + struct pbuf *p; + rt_uint16_t i; + + for (i = 0; i < frame->length; i++) + { + netc_buffer_struct_t *buff = &frame->buffArray[i]; + netc_rx_pbuf_wrapper_t *rx_pbuf = _netc_find_rx_pbuf(buff->buffer); + + if (rx_pbuf == RT_NULL) + { + LOG_W("NETC Rx buffer is not in zero-copy pool"); + _netc_rx_release_frame_buffers(netc, frame, i); + if (p_root != RT_NULL) + { + pbuf_free(p_root); + } + return RT_NULL; + } + + p = pbuf_alloced_custom(PBUF_RAW, + buff->length, + PBUF_REF, + &rx_pbuf->custom, + buff->buffer, + NETC_RXBUFF_SIZE); + if (p == RT_NULL) + { + LOG_W("pbuf_alloced_custom failed"); + _netc_rx_release_frame_buffers(netc, frame, i); + if (p_root != RT_NULL) + { + pbuf_free(p_root); + } + return RT_NULL; + } + + if (p_root == RT_NULL) + { + p_root = p; + } + else + { + pbuf_cat(p_root, p); + } + } + + return p_root; +} +#endif + +static status_t _netc_tx_reclaim_callback(ep_handle_t *handle, + uint8_t ring, + netc_tx_frame_info_t *frameInfo, + void *userData) +{ + RT_UNUSED(handle); + RT_UNUSED(ring); + RT_UNUSED(userData); + + if ((frameInfo != RT_NULL) && (frameInfo->context != RT_NULL)) + { + rt_free(frameInfo->context); + frameInfo->context = RT_NULL; + } + + return kStatus_Success; +} + +#if NETC_USE_SWT +static status_t _netc_swt_reclaim_callback(swt_handle_t *handle, + netc_tx_frame_info_t *frameInfo, + void *userData) +{ + RT_UNUSED(handle); + RT_UNUSED(userData); + + if ((frameInfo != RT_NULL) && (frameInfo->context != RT_NULL)) + { + rt_free(frameInfo->context); + frameInfo->context = RT_NULL; + } + + return kStatus_Success; +} + +static status_t _netc_swt_add_table_entry(swt_handle_t *swt_handle) +{ + netc_tb_ipf_config_t ipf_entry_config; + status_t result = kStatus_Success; + uint32_t entry_id; + rt_uint32_t i; + + rt_memset(&ipf_entry_config, 0, sizeof(ipf_entry_config)); + ipf_entry_config.keye.srcPortMask = NETC_SWT_USED_PORT_BITMAP; + ipf_entry_config.cfge.hr = kNETC_SoftwareDefHR0; + ipf_entry_config.cfge.fltfa = kNETC_IPFRedirectToMgmtPort; + + for (i = 0; i < NETC_SWT_MAX_PORT_NUM; i++) + { + if (((1U << i) & NETC_SWT_USED_PORT_BITMAP) == 0U) + { + continue; + } + + entry_id = 0xFFFFFFFFU; + ipf_entry_config.keye.srcPort = i; + result = SWT_RxIPFAddTableEntry(swt_handle, &ipf_entry_config, &entry_id); + if ((result != kStatus_Success) && (entry_id != 0xFFFFFFFFU)) + { + LOG_E("SWT_RxIPFAddTableEntry failed: %d, entry %u", result, entry_id); + return result; + } + } + + return result; +} + +static rt_err_t _netc_swt_configure_link(struct rt_imxrt_netc *netc) +{ + status_t result; + rt_uint32_t i; + + for (i = 0; i < NETC_SWT_MAX_PORT_NUM; i++) + { + if (((1U << i) & NETC_SWT_USED_PORT_BITMAP) == 0U) + { + continue; + } + + result = SWT_SetEthPortMII(&netc->swt_handle, (uint8_t)i, NETC_LINK_SPEED, NETC_LINK_DUPLEX); + if (result != kStatus_Success) + { + LOG_E("SWT_SetEthPortMII port %u failed: %d", i, result); + return -RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t _netc_swt_init(struct rt_imxrt_netc *netc) +{ + status_t result; + rt_uint32_t i; + + if (netc->swt_inited) + { + return _netc_swt_configure_link(netc); + } + + result = SWT_GetDefaultConfig(&g_netc_swt_config); + if (result != kStatus_Success) + { + LOG_E("SWT_GetDefaultConfig failed: %d", result); + return -RT_ERROR; + } + + for (i = 0; i < NETC_SWT_MAX_PORT_NUM; i++) + { + if (((1U << i) & NETC_SWT_USED_PORT_BITMAP) == 0U) + { + continue; + } + + g_netc_swt_config.ports[i].ethMac.miiMode = NETC_MII_MODE; + g_netc_swt_config.ports[i].ethMac.miiSpeed = NETC_LINK_SPEED; + g_netc_swt_config.ports[i].ethMac.miiDuplex = NETC_LINK_DUPLEX; + g_netc_swt_config.ports[i].ethMac.rxMaxFrameSize = NETC_FRAME_MAX_FRAMELEN; + g_netc_swt_config.ports[i].commonCfg.ipfCfg.enIPFTable = true; + } + + g_netc_swt_config.bridgeCfg.dVFCfg.portMembership = + (1U << NETC_SWT_PSEUDO_PORT) | NETC_SWT_USED_PORT_BITMAP; + g_netc_swt_config.cmdRingUse = 1U; + g_netc_swt_config.cmdBdrCfg[0].bdBase = g_netc_swt_cmd_bd; + g_netc_swt_config.cmdBdrCfg[0].bdLength = NETC_CMDBD_NUM; + + result = SWT_Init(&netc->swt_handle, &g_netc_swt_config); + if (result != kStatus_Success) + { + LOG_E("SWT_Init failed: %d", result); + return -RT_ERROR; + } + + rt_memset(&g_netc_swt_transfer_config, 0, sizeof(g_netc_swt_transfer_config)); + g_netc_swt_transfer_config.enUseMgmtRxBdRing = false; + g_netc_swt_transfer_config.enUseMgmtTxBdRing = true; + g_netc_swt_transfer_config.mgmtTxBdrConfig.bdArray = g_netc_tx_bd; + g_netc_swt_transfer_config.mgmtTxBdrConfig.len = NETC_TXBD_NUM; + g_netc_swt_transfer_config.mgmtTxBdrConfig.dirtyArray = g_netc_tx_dirty; + g_netc_swt_transfer_config.mgmtTxBdrConfig.msixEntryIdx = TX_MSIX_ENTRY_IDX; + g_netc_swt_transfer_config.mgmtTxBdrConfig.enIntr = true; + g_netc_swt_transfer_config.reclaimCallback = _netc_swt_reclaim_callback; +#if NETC_RX_ZERO_COPY + g_netc_swt_transfer_config.rxZeroCopy = true; + g_netc_swt_transfer_config.rxBuffAlloc = _netc_rx_buff_alloc; + g_netc_swt_transfer_config.rxBuffFree = _netc_rx_buff_free; + g_netc_swt_transfer_config.userData = g_netc_rx_pbufs; +#else + g_netc_swt_transfer_config.rxZeroCopy = false; + g_netc_swt_transfer_config.rxBuffAlloc = RT_NULL; + g_netc_swt_transfer_config.rxBuffFree = RT_NULL; + g_netc_swt_transfer_config.userData = netc; +#endif + g_netc_swt_transfer_config.rxCacheMaintain = true; + g_netc_swt_transfer_config.txCacheMaintain = true; + + + result = SWT_ManagementTxRxConfig(&netc->swt_handle, &netc->ep_handle, &g_netc_swt_transfer_config); + if (result != kStatus_Success) + { + LOG_E("SWT_ManagementTxRxConfig failed: %d", result); + return -RT_ERROR; + } + + result = _netc_swt_add_table_entry(&netc->swt_handle); + if (result != kStatus_Success) + { + return -RT_ERROR; + } + + netc->swt_inited = RT_TRUE; + + return RT_EOK; +} +#endif + +static rt_bool_t _netc_phy_get_link(struct rt_imxrt_netc *netc) +{ + uint16_t phy_status = 0; + + if (!netc->mdio_inited) + { + return RT_TRUE; + } + + /* BMSR is latch-low on many PHYs, so read twice. */ + if (NETC_MDIORead(&netc->mdio_handle, NETC_PHY_ADDR, NETC_PHY_STATUS_REG, &phy_status) != kStatus_Success) + { + return netc->link_up; + } + + if (NETC_MDIORead(&netc->mdio_handle, NETC_PHY_ADDR, NETC_PHY_STATUS_REG, &phy_status) != kStatus_Success) + { + return netc->link_up; + } + + return ((phy_status & NETC_PHY_LINK_UP_MASK) != 0U) ? RT_TRUE : RT_FALSE; +} + +static void _netc_msgintr_callback(MSGINTR_Type *base, uint8_t channel, uint32_t pendingIntr) +{ + RT_UNUSED(base); + + if (channel != 0) + { + return; + } + + rt_interrupt_enter(); + + if ((pendingIntr & (1U << TX_INTR_MSG_DATA)) != 0U) + { + EP_CleanTxIntrFlags(&imxrt_netc_device.ep_handle, 1, 0); + rt_sem_release(&imxrt_netc_device.tx_isr_sem); + } + + if ((pendingIntr & (1U << RX_INTR_MSG_DATA))!= 0U) + { + EP_CleanRxIntrFlags(&imxrt_netc_device.ep_handle, 1); + (void)eth_device_ready(&imxrt_netc_device.parent); + } + + rt_interrupt_leave(); +} + +static rt_err_t _netc_wait_tx_complete(struct rt_imxrt_netc *netc) +{ + if (rt_sem_take(&netc->tx_isr_sem, NETC_TX_TIMEOUT_TICK) != RT_EOK) + { + LOG_E("NETC Tx wait timeout"); + return -RT_ETIMEOUT; + } + + rt_mutex_take(&netc->lock, RT_WAITING_FOREVER); +#if NETC_USE_SWT +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + SWT_ReclaimTxDescriptor(&netc->swt_handle, NETC_RING_ID); +#else + SWT_ReclaimTxDescriptor(&netc->swt_handle, false, NETC_RING_ID); +#endif +#else + EP_ReclaimTxDescriptor(&netc->ep_handle, NETC_RING_ID); +#endif + rt_mutex_release(&netc->lock); + + return RT_EOK; +} + +static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) +{ + ep_config_t ep_config; + netc_bdr_config_t bdr_config; + netc_rx_bdr_config_t rx_bdr_config[1]; + netc_tx_bdr_config_t tx_bdr_config[1]; + netc_mdio_config_t mdio_config; + status_t result; + rt_uint32_t i; + + if (netc->hw_inited) + { + return RT_EOK; + } + + CLOCK_EnableClock(kCLOCK_Netc); + + /* RT1180 NETC access needs TRDC permissions and board-side NETC strap setup. */ + //BOARD_CommonSetting(); + PHY_Reset(); + BOARD_NETC_Init(); + + for (i = 0; i < NETC_RXBD_NUM; i++) + { + g_netc_rx_buf_addr[i] = (uint64_t)(uintptr_t)&g_netc_rx_buf[i][0]; + } + +#if NETC_RX_ZERO_COPY + for (i = 0; i < NETC_RXBUFF_TOTAL_NUM; i++) + { + g_netc_rx_pbufs[i].custom.custom_free_function = _netc_rx_pbuf_free; + g_netc_rx_pbufs[i].buffer = &g_netc_rx_buf[i][0]; +#if NETC_USE_SWT + g_netc_rx_pbufs[i].buffer_used = (i < NETC_RXBD_NUM) ? RT_TRUE : RT_FALSE; + g_netc_rx_pbufs[i].handle = &netc->swt_handle; +#else + g_netc_rx_pbufs[i].buffer_used = RT_FALSE; + g_netc_rx_pbufs[i].handle = &netc->ep_handle; +#endif + g_netc_rx_pbufs[i].ring = NETC_RING_ID; + } +#endif + + rt_memset(g_netc_rx_bd, 0, sizeof(g_netc_rx_bd)); + rt_memset(g_netc_tx_bd, 0, sizeof(g_netc_tx_bd)); + rt_memset(g_netc_cmd_bd, 0, sizeof(g_netc_cmd_bd)); +#if NETC_USE_SWT + rt_memset(g_netc_swt_cmd_bd, 0, sizeof(g_netc_swt_cmd_bd)); +#endif + rt_memset(g_netc_tx_dirty, 0, sizeof(g_netc_tx_dirty)); + rt_memset(&ep_config, 0, sizeof(ep_config)); + rt_memset(&bdr_config, 0, sizeof(bdr_config)); + rt_memset(rx_bdr_config, 0, sizeof(rx_bdr_config)); + rt_memset(tx_bdr_config, 0, sizeof(tx_bdr_config)); + rt_memset(&mdio_config, 0, sizeof(mdio_config)); + + /* MSIX and interrupt configuration. */ + MSGINTR_Init(NETC_MSGINTR, &_netc_msgintr_callback); + uint32_t msgAddr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, 0); + g_netc_msix_entry[0].control = kNETC_MsixIntrMaskBit; + g_netc_msix_entry[0].msgAddr = msgAddr; + g_netc_msix_entry[0].msgData = TX_INTR_MSG_DATA; + g_netc_msix_entry[1].control = kNETC_MsixIntrMaskBit; + g_netc_msix_entry[1].msgAddr = msgAddr; + g_netc_msix_entry[1].msgData = RX_INTR_MSG_DATA; + + result = EP_GetDefaultConfig(&ep_config); + if (result != kStatus_Success) + { + LOG_E("EP_GetDefaultConfig failed: %d", result); + return -RT_ERROR; + } + + ep_config.si = NETC_PSI; + ep_config.siConfig.rxRingUse = 1U; + ep_config.siConfig.txRingUse = 1U; + ep_config.siConfig.rxBdrGroupNum = 0U; + ep_config.siConfig.ringPerBdrGroup = 1U; + ep_config.siConfig.defaultRxBdrGroup = kNETC_SiBDRGroupOne; + ep_config.entryNum = 2U; + ep_config.msixEntry = &g_netc_msix_entry[0]; + ep_config.cmdBdEntryIdx = 0U; + ep_config.siComEntryIdx = 0U; + ep_config.timerSyncEntryIdx = 0U; + ep_config.reclaimCallback = _netc_tx_reclaim_callback; +#if NETC_RX_ZERO_COPY + ep_config.userData = g_netc_rx_pbufs; +#else + ep_config.userData = netc; +#endif + ep_config.rxCacheMaintain = false; +#if defined(FSL_ETH_ENABLE_CACHE_CONTROL) + ep_config.txCacheMaintain = true; +#else + ep_config.txCacheMaintain = false; +#endif +#if NETC_RX_ZERO_COPY && !NETC_USE_SWT + ep_config.rxZeroCopy = true; + ep_config.rxBuffAlloc = _netc_rx_buff_alloc; + ep_config.rxBuffFree = _netc_rx_buff_free; +#else + ep_config.rxZeroCopy = false; + ep_config.rxBuffAlloc = RT_NULL; + ep_config.rxBuffFree = RT_NULL; +#endif + ep_config.cmdBdrConfig.bdBase = g_netc_cmd_bd; + ep_config.cmdBdrConfig.bdLength = NETC_CMDBD_NUM; + ep_config.cmdBdrConfig.enCompInt = false; + + ep_config.port.ethMac.miiMode = NETC_MII_MODE; + ep_config.port.ethMac.miiSpeed = NETC_LINK_SPEED; + ep_config.port.ethMac.miiDuplex = NETC_LINK_DUPLEX; + ep_config.port.ethMac.rxMaxFrameSize = NETC_FRAME_MAX_FRAMELEN; + + rx_bdr_config[0].extendDescEn = false; + rx_bdr_config[0].bdArray = g_netc_rx_bd; + rx_bdr_config[0].len = NETC_RXBD_NUM; + rx_bdr_config[0].buffAddrArray = g_netc_rx_buf_addr; + rx_bdr_config[0].buffSize = NETC_RXBUFF_SIZE; + rx_bdr_config[0].enThresIntr = true; + rx_bdr_config[0].enCoalIntr = true; + rx_bdr_config[0].intrThreshold = 1U; + rx_bdr_config[0].intrTimerThres = 0U; + rx_bdr_config[0].msixEntryIdx = RX_MSIX_ENTRY_IDX; + rx_bdr_config[0].disVlanPresent = false; + rx_bdr_config[0].enVlanExtract = false; + rx_bdr_config[0].isKeepCRC = false; + rx_bdr_config[0].congestionMode = false; + rx_bdr_config[0].enHeaderAlign = false; + + tx_bdr_config[0].len = NETC_TXBD_NUM; + tx_bdr_config[0].bdArray = g_netc_tx_bd; + tx_bdr_config[0].dirtyArray = g_netc_tx_dirty; + tx_bdr_config[0].enIntr = true; + tx_bdr_config[0].enThresIntr = false; + tx_bdr_config[0].enCoalIntr = false; + tx_bdr_config[0].intrThreshold = 0U; + tx_bdr_config[0].intrTimerThres = 0U; + tx_bdr_config[0].msixEntryIdx = TX_MSIX_ENTRY_IDX; + tx_bdr_config[0].isVlanInsert = false; + tx_bdr_config[0].isUserCRC = false; + tx_bdr_config[0].wrrWeight = 1U; + tx_bdr_config[0].priority = 0U; + + bdr_config.rxBdrConfig = rx_bdr_config; + bdr_config.txBdrConfig = tx_bdr_config; + + result = EP_Init(&netc->ep_handle, netc->dev_addr, &ep_config, &bdr_config); + if (result != kStatus_Success) + { + LOG_E("EP_Init failed: %d", result); + return -RT_ERROR; + } + + mdio_config.mdio.type = kNETC_EMdio; + mdio_config.srcClockHz = CLOCK_GetRootClockFreq(kCLOCK_Root_Netc); + mdio_config.isNegativeDriven = false; + mdio_config.isPreambleDisable = false; + + result = NETC_MDIOInit(&netc->mdio_handle, &mdio_config); + if (result == kStatus_Success) + { + netc->mdio_inited = RT_TRUE; + } + else + { + netc->mdio_inited = RT_FALSE; + LOG_W("NETC_MDIOInit failed: %d, continue with fixed MAC configuration", result); + } + + result = EP_Up(&netc->ep_handle, NETC_LINK_SPEED, NETC_LINK_DUPLEX); + if (result != kStatus_Success) + { + LOG_E("EP_Up failed: %d", result); + return -RT_ERROR; + } + +#if NETC_USE_SWT + if (_netc_swt_init(netc) != RT_EOK) + { + return -RT_ERROR; + } +#endif + + netc->link_up = _netc_phy_get_link(netc); + if (!netc->link_up) + { +#if !NETC_USE_SWT + (void)EP_Down(&netc->ep_handle); +#endif + } + + netc->hw_inited = RT_TRUE; + + EP_MsixSetEntryMask(&netc->ep_handle, TX_MSIX_ENTRY_IDX, false); + EP_MsixSetEntryMask(&netc->ep_handle, RX_MSIX_ENTRY_IDX, false); + +#if NETC_USE_SWT + LOG_I("NETC ENETC1 initialized, MAC %02x:%02x:%02x:%02x:%02x:%02x", + netc->dev_addr[0], netc->dev_addr[1], netc->dev_addr[2], + netc->dev_addr[3], netc->dev_addr[4], netc->dev_addr[5]); +#else + LOG_I("NETC ENETC0 initialized, MAC %02x:%02x:%02x:%02x:%02x:%02x", + netc->dev_addr[0], netc->dev_addr[1], netc->dev_addr[2], + netc->dev_addr[3], netc->dev_addr[4], netc->dev_addr[5]); +#endif + + return RT_EOK; +} + +static void _netc_poll_thread_entry(void *parameter) +{ + struct rt_imxrt_netc *netc = (struct rt_imxrt_netc *)parameter; + + while (1) + { + rt_bool_t link_now; + + if (!netc->hw_inited) + { + rt_thread_delay(NETC_PHY_POLL_DELAY_TICK); + continue; + } + + link_now = _netc_phy_get_link(netc); + if (link_now != netc->link_up) + { + rt_mutex_take(&netc->lock, RT_WAITING_FOREVER); + if (link_now) + { + (void)EP_Up(&netc->ep_handle, NETC_LINK_SPEED, NETC_LINK_DUPLEX); +#if NETC_USE_SWT + (void)_netc_swt_init(netc); +#endif + } + else + { +#if !NETC_USE_SWT + (void)EP_Down(&netc->ep_handle); +#endif + } + netc->link_up = link_now; + rt_mutex_release(&netc->lock); + + eth_device_linkchange(&netc->parent, netc->link_up); + } + + rt_thread_delay(NETC_PHY_POLL_DELAY_TICK); + } +} + +static rt_err_t rt_imxrt_netc_init(rt_device_t dev) +{ + RT_UNUSED(dev); + return _netc_hw_init(&imxrt_netc_device); +} + +static rt_err_t rt_imxrt_netc_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_UNUSED(dev); + RT_UNUSED(oflag); + return RT_EOK; +} + +static rt_err_t rt_imxrt_netc_close(rt_device_t dev) +{ + RT_UNUSED(dev); + return RT_EOK; +} + +static rt_ssize_t rt_imxrt_netc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_UNUSED(dev); + RT_UNUSED(pos); + RT_UNUSED(buffer); + RT_UNUSED(size); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_ssize_t rt_imxrt_netc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_UNUSED(dev); + RT_UNUSED(pos); + RT_UNUSED(buffer); + RT_UNUSED(size); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_imxrt_netc_control(rt_device_t dev, int cmd, void *args) +{ + RT_UNUSED(dev); + + switch (cmd) + { + case NIOCTL_GADDR: + if (args == RT_NULL) + { + return -RT_ERROR; + } + + rt_memcpy(args, imxrt_netc_device.dev_addr, sizeof(imxrt_netc_device.dev_addr)); + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_imxrt_netc_tx(rt_device_t dev, struct pbuf *p) +{ + struct rt_imxrt_netc *netc = &imxrt_netc_device; + netc_buffer_struct_t tx_buff; + netc_frame_struct_t frame; +#if NETC_USE_SWT + swt_tx_opt tx_opt; +#else + ep_tx_opt tx_opt; +#endif + void *tx_data; + status_t result; + + RT_UNUSED(dev); + RT_ASSERT(p != RT_NULL); + + if (!netc->hw_inited) + { + return -RT_ERROR; + } + + if (!netc->link_up) + { + return -RT_ERROR; + } + + if (p->tot_len == 0U) + { + return -RT_ERROR; + } + + while (rt_sem_take(&netc->tx_isr_sem, 0) == RT_EOK) + { + } + + tx_data = rt_malloc(p->tot_len); + if (tx_data == RT_NULL) + { + return -RT_ENOMEM; + } + + (void)pbuf_copy_partial(p, tx_data, p->tot_len, 0); + + tx_buff.buffer = tx_data; + tx_buff.length = (uint16_t)p->tot_len; + frame.buffArray = &tx_buff; + frame.length = 1U; + rt_memset(&tx_opt, 0, sizeof(tx_opt)); + + do + { + rt_mutex_take(&netc->lock, RT_WAITING_FOREVER); +#if NETC_USE_SWT +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + result = SWT_SendFrame(&netc->swt_handle, &frame, tx_data, &tx_opt); +#else + { + swt_mgmt_tx_arg_t tx_arg = {.ring = NETC_RING_ID}; + + result = SWT_SendFrame(&netc->swt_handle, + tx_arg, + NETC_SWT_TX_PORT, + false, + &frame, + tx_data, + &tx_opt); + } +#endif +#else + result = EP_SendFrame(&netc->ep_handle, NETC_RING_ID, &frame, tx_data, &tx_opt); +#endif + rt_mutex_release(&netc->lock); + + if (result == kStatus_Busy) + { + rt_thread_mdelay(1); + } + } while (result == kStatus_Busy); + + if (result != kStatus_Success) + { + rt_free(tx_data); +#if NETC_USE_SWT + LOG_E("SWT_SendFrame failed: %d", result); +#else + LOG_E("EP_SendFrame failed: %d", result); +#endif + return -RT_ERROR; + } + if (result == kStatus_Success) + { + return _netc_wait_tx_complete(netc); + } + + return RT_EOK; +} + +static struct pbuf *rt_imxrt_netc_rx(rt_device_t dev) +{ + struct rt_imxrt_netc *netc = &imxrt_netc_device; + struct pbuf *p = RT_NULL; +#if NETC_RX_ZERO_COPY + netc_buffer_struct_t rx_buffers[NETC_MAX_BUFFERS_PER_FRAME]; + netc_frame_struct_t frame; + status_t result; +#else + uint32_t length = 0U; + status_t result; +#endif + + RT_UNUSED(dev); + + if (!netc->hw_inited) + { + return RT_NULL; + } + + rt_mutex_take(&netc->lock, RT_WAITING_FOREVER); + +#if NETC_RX_ZERO_COPY + frame.buffArray = rx_buffers; + frame.length = NETC_MAX_BUFFERS_PER_FRAME; + +#if NETC_USE_SWT + result = SWT_ReceiveFrame(&netc->swt_handle, &frame, RT_NULL); +#else + result = EP_ReceiveFrame(&netc->ep_handle, NETC_RING_ID, &frame, RT_NULL); +#endif + if (result == kStatus_Success) + { + p = _netc_rx_frame_to_pbufs(netc, &frame); + } +#if NETC_USE_SWT + else if ((result == kStatus_NETC_RxFrameError) || + (result == kStatus_NETC_RxTsrResp)) + { + (void)SWT_ReceiveFrameCopy(&netc->swt_handle, RT_NULL, 0U, RT_NULL); + } + else if ((result != kStatus_NETC_RxFrameEmpty) && + (result != kStatus_NETC_LackOfResource) && + (result != kStatus_NETC_RxHRZeroFrame)) + { + LOG_W("SWT_ReceiveFrame failed: %d", result); + } +#else + else if ((result == kStatus_NETC_RxHRNotZeroFrame) || + (result == kStatus_NETC_RxTsrResp)) + { + EP_DropFrame(&netc->ep_handle, &netc->ep_handle.rxBdRing[NETC_RING_ID], NETC_RING_ID); + } + else if ((result != kStatus_NETC_RxFrameEmpty) && + (result != kStatus_NETC_LackOfResource) && + (result != kStatus_NETC_RxFrameError)) + { + LOG_W("EP_ReceiveFrame failed: %d", result); + } +#endif +#else +#if NETC_USE_SWT + result = SWT_GetRxFrameSize(&netc->swt_handle, &length); +#else + result = EP_GetRxFrameSize(&netc->ep_handle, NETC_RING_ID, &length); +#endif + if ((result == kStatus_Success) && (length != 0U)) + { + p = pbuf_alloc(PBUF_RAW, (u16_t)length, PBUF_RAM); + if (p == RT_NULL) + { +#if NETC_USE_SWT + (void)SWT_ReceiveFrameCopy(&netc->swt_handle, RT_NULL, 0U, RT_NULL); +#else + (void)EP_ReceiveFrameCopy(&netc->ep_handle, NETC_RING_ID, RT_NULL, 0U, RT_NULL); +#endif + rt_mutex_release(&netc->lock); + return RT_NULL; + } + +#if NETC_USE_SWT + result = SWT_ReceiveFrameCopy(&netc->swt_handle, p->payload, length, RT_NULL); +#else + result = EP_ReceiveFrameCopy(&netc->ep_handle, NETC_RING_ID, p->payload, length, RT_NULL); +#endif + if (result != kStatus_Success) + { + pbuf_free(p); + p = RT_NULL; +#if NETC_USE_SWT + LOG_W("SWT_ReceiveFrameCopy failed: %d", result); +#else + LOG_W("EP_ReceiveFrameCopy failed: %d", result); +#endif + } + } +#if NETC_USE_SWT + else if ((result == kStatus_NETC_RxFrameError) || + (result == kStatus_NETC_RxTsrResp)) + { + (void)SWT_ReceiveFrameCopy(&netc->swt_handle, RT_NULL, 0U, RT_NULL); + } +#else + else if ((result == kStatus_NETC_RxFrameError) || + (result == kStatus_NETC_RxHRNotZeroFrame) || + (result == kStatus_NETC_RxTsrResp)) + { + (void)EP_ReceiveFrameCopy(&netc->ep_handle, NETC_RING_ID, RT_NULL, 0U, RT_NULL); + } +#endif +#endif + + rt_mutex_release(&netc->lock); + + return p; +} + +static int rt_hw_imxrt_netc_init(void) +{ + rt_err_t state; + rt_thread_t tid; + + imxrt_netc_device.dev_addr[0] = NETC_DEFAULT_MAC0; + imxrt_netc_device.dev_addr[1] = NETC_DEFAULT_MAC1; + imxrt_netc_device.dev_addr[2] = NETC_DEFAULT_MAC2; + imxrt_netc_device.dev_addr[3] = NETC_DEFAULT_MAC3; + imxrt_netc_device.dev_addr[4] = NETC_DEFAULT_MAC4; + imxrt_netc_device.dev_addr[5] = NETC_DEFAULT_MAC5; + + rt_mutex_init(&imxrt_netc_device.lock, "netc", RT_IPC_FLAG_FIFO); + rt_sem_init(&imxrt_netc_device.tx_isr_sem, "ntx", 0, RT_IPC_FLAG_FIFO); + + imxrt_netc_device.parent.parent.init = rt_imxrt_netc_init; + imxrt_netc_device.parent.parent.open = rt_imxrt_netc_open; + imxrt_netc_device.parent.parent.close = rt_imxrt_netc_close; + imxrt_netc_device.parent.parent.read = rt_imxrt_netc_read; + imxrt_netc_device.parent.parent.write = rt_imxrt_netc_write; + imxrt_netc_device.parent.parent.control = rt_imxrt_netc_control; + imxrt_netc_device.parent.parent.user_data = &imxrt_netc_device; + + imxrt_netc_device.parent.eth_rx = rt_imxrt_netc_rx; + imxrt_netc_device.parent.eth_tx = rt_imxrt_netc_tx; + + state = _netc_hw_init(&imxrt_netc_device); + if (state != RT_EOK) + { + return state; + } + + state = eth_device_init(&imxrt_netc_device.parent, "e0"); + if (state != RT_EOK) + { + LOG_E("eth_device_init failed: %d", state); + return state; + } + + eth_device_linkchange(&imxrt_netc_device.parent, imxrt_netc_device.link_up); + + tid = rt_thread_create("netc", + _netc_poll_thread_entry, + &imxrt_netc_device, + RT_NTCP_THREAD_STACK_SIZE, + RT_NTCP_THREAD_PRIORITY, + 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_W("failed to create NETC poll thread"); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_imxrt_netc_init); + +#endif /* RT_USING_LWIP */ From 5439ff4b342b1e4aaca4d78d3363850dbcdaa542 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 16:23:38 +0800 Subject: [PATCH 23/31] Updated cherryusb_port.c to avoid worning. --- .../imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c | 3 +++ bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c index b35f55adef77..19d62658d0d5 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c @@ -74,6 +74,8 @@ static usb_controller_index_t rt1180_usb_controller_id(uint8_t busid) return (usb_controller_index_t)(RT1180_USB_EHCI0_ID + rt1180_usb_selected_index()); } +#if defined(RT_CHERRYUSB_HOST) || defined(BSP_CHERRYUSB_DEVICE_CDC_ACM_ECHO) || \ + defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) || defined(RT_CHERRYUSB_DEVICE_TEMPLATE_MSC) static uintptr_t rt1180_usb_base(uint8_t busid) { static const uintptr_t usb_base[] = USBHS_STACK_BASE_ADDRS; @@ -81,6 +83,7 @@ static uintptr_t rt1180_usb_base(uint8_t busid) (void)busid; return usb_base[rt1180_usb_selected_index()]; } +#endif static IRQn_Type rt1180_usb_irqn(uint8_t busid) { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c index b35f55adef77..19d62658d0d5 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c @@ -74,6 +74,8 @@ static usb_controller_index_t rt1180_usb_controller_id(uint8_t busid) return (usb_controller_index_t)(RT1180_USB_EHCI0_ID + rt1180_usb_selected_index()); } +#if defined(RT_CHERRYUSB_HOST) || defined(BSP_CHERRYUSB_DEVICE_CDC_ACM_ECHO) || \ + defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) || defined(RT_CHERRYUSB_DEVICE_TEMPLATE_MSC) static uintptr_t rt1180_usb_base(uint8_t busid) { static const uintptr_t usb_base[] = USBHS_STACK_BASE_ADDRS; @@ -81,6 +83,7 @@ static uintptr_t rt1180_usb_base(uint8_t busid) (void)busid; return usb_base[rt1180_usb_selected_index()]; } +#endif static IRQn_Type rt1180_usb_irqn(uint8_t busid) { From 75f21b556dd13fbcad021c13ef856d326020b97c Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 16:26:57 +0800 Subject: [PATCH 24/31] Updated sconscript to locate multicore directory in packages for header inclusion. --- .../cm33/applications/SConscript | 15 +++++++++++++++ .../imxrt1180-nxp-evk/cm7/applications/SConscript | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript index e617b6f728ff..c190629fba96 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript @@ -1,6 +1,7 @@ import rtconfig from building import * import os +import glob cwd = GetCurrentDir() @@ -20,6 +21,20 @@ if GetDepend(['BSP_USE_MULTICORE']): src += Split(""" multicore_thread.c """) + # Locate SDK multicore directory for header inclusion + bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) + sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) + if sdk_candidates: + sdk_multicore = sdk_candidates[0] + else: + sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') + CPPPATH += [os.path.join(sdk_multicore, 'mcmgr', 'inc')] + if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + CPPPATH += [ + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), + ] if GetDepend(['BSP_USING_FS']): src += Split(""" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript index 84029503eb9f..55a350f497f9 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript @@ -1,6 +1,7 @@ import rtconfig from building import * import os +import glob cwd = GetCurrentDir() @@ -20,6 +21,20 @@ if GetDepend(['BSP_USE_MULTICORE']): src += Split(""" multicore_thread.c """) + # Locate SDK multicore directory for header inclusion + bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) + sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) + if sdk_candidates: + sdk_multicore = sdk_candidates[0] + else: + sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') + CPPPATH += [os.path.join(sdk_multicore, 'mcmgr', 'inc')] + if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): + CPPPATH += [ + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), + os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), + ] if GetDepend(['BSP_USING_ETHERCAT']): src += Split(""" From 2f252bac14e0d7a681c0620fa1323f8ade28583a Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 16:28:36 +0800 Subject: [PATCH 25/31] Updated cm33/board/board.c to avoid worning when enable cm33_kickoff_cm7. --- bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index a3b5b1ae33e8..6039e87d1323 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -1436,7 +1436,7 @@ void SysTick_Handler(void) } -#ifdef BSP_USE_MULTICORE +#ifdef BSP_USE_MULTICORE_KICK_OFF_DIRECTLY static int second_core_boot(void) { /* From 93652f723ebb55c0f566ac174020a8396d8d560a Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 16:32:50 +0800 Subject: [PATCH 26/31] Deleted peripheral.ethercat, because the related protocol stack has not been uploaded. And added CONFIG_BSP_USING_GPIO=y for Peripheral.netc.: --- .../cm7/.ci/attachconfig/ci.attachconfig.yml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml index c85b48a3e77a..af8ac011088b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -30,10 +30,7 @@ Peripheral.netc: <<: *scons kconfig: - CONFIG_BSP_USING_ETH=y -Peripheral.ethercat: - <<: *scons - kconfig: - - CONFIG_BSP_USING_ETHERCAT=y + - CONFIG_BSP_USING_GPIO=y Peripheral.multicore: <<: *scons kconfig: From ed1acfb9127c71814d1b6d5749eb70d821106acf Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 19:38:04 +0800 Subject: [PATCH 27/31] Removed the SConscript of multicore and ethercat to packages. --- .../cm33/applications/SConscript | 15 ----- .../cm33/multicore/SConscript | 64 ------------------- .../cm7/applications/SConscript | 15 ----- .../imxrt1180-nxp-evk/cm7/ethercat/SConscript | 39 ----------- .../cm7/multicore/SConscript | 64 ------------------- 5 files changed, 197 deletions(-) delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript delete mode 100644 bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript index c190629fba96..e617b6f728ff 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript @@ -1,7 +1,6 @@ import rtconfig from building import * import os -import glob cwd = GetCurrentDir() @@ -21,20 +20,6 @@ if GetDepend(['BSP_USE_MULTICORE']): src += Split(""" multicore_thread.c """) - # Locate SDK multicore directory for header inclusion - bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) - sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) - if sdk_candidates: - sdk_multicore = sdk_candidates[0] - else: - sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') - CPPPATH += [os.path.join(sdk_multicore, 'mcmgr', 'inc')] - if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - CPPPATH += [ - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), - ] if GetDepend(['BSP_USING_FS']): src += Split(""" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript deleted file mode 100644 index 95d48f3a6ef7..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/multicore/SConscript +++ /dev/null @@ -1,64 +0,0 @@ -Import('rtconfig') -from building import * -import os -import glob - -cwd = GetCurrentDir() - -# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. -# The directory is named nxp-imxrt-sdk- under packages/. -bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) -sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) -if sdk_candidates: - sdk_multicore = sdk_candidates[0] -else: - sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') - -# Base multicore sources (always included when BSP_USE_MULTICORE is enabled) -src = Split(""" -mcmgr/src/mcmgr.c -mcmgr/src/mcmgr_internal_core_api_imxrt1180.c -mcmgr/src/mcmgr_mu_internal.c -""") - -src = [os.path.join(sdk_multicore, f.strip()) for f in src] - -# Add RPMsg-Lite sources if enabled -if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - rpmsg_src = Split(""" - rpmsg-lite/lib/common/llist.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_lite.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_queue.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_ns.c - rpmsg-lite/lib/virtio/virtqueue.c - rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c - rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c - """) - src += [os.path.join(sdk_multicore, f.strip()) for f in rpmsg_src] - -# Base include paths -CPPPATH = [ - cwd, - os.path.join(sdk_multicore, 'mcmgr', 'inc'), - os.path.join(sdk_multicore, 'mcmgr', 'inc', 'platform', 'imxrt1180'), -] - -# Add RPMsg-Lite include paths if enabled -if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - CPPPATH += [ - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), - ] - -# Define preprocessor macros -CPPDEFINES = [] - -# Create component group with dependency on BSP_USE_MULTICORE -group = DefineGroup('MultiCore', - src, - depend=['BSP_USE_MULTICORE'], - CPPPATH=CPPPATH, - CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript index 55a350f497f9..84029503eb9f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript @@ -1,7 +1,6 @@ import rtconfig from building import * import os -import glob cwd = GetCurrentDir() @@ -21,20 +20,6 @@ if GetDepend(['BSP_USE_MULTICORE']): src += Split(""" multicore_thread.c """) - # Locate SDK multicore directory for header inclusion - bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) - sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) - if sdk_candidates: - sdk_multicore = sdk_candidates[0] - else: - sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') - CPPPATH += [os.path.join(sdk_multicore, 'mcmgr', 'inc')] - if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - CPPPATH += [ - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), - ] if GetDepend(['BSP_USING_ETHERCAT']): src += Split(""" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript deleted file mode 100644 index 1596f1a70a20..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/ethercat/SConscript +++ /dev/null @@ -1,39 +0,0 @@ -Import('rtconfig') -from building import * -import os -import glob - -cwd = GetCurrentDir() - -# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. -# The directory is named nxp-imxrt-sdk- under packages/. -bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) -sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'ethercat')) -if sdk_candidates: - sdk_ethercat = sdk_candidates[0] -else: - sdk_ethercat = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'ethercat') - -# EtherCAT application sources -ecat_src = [ - os.path.join(sdk_ethercat, 'ethercat_init.c'), - os.path.join(sdk_ethercat, 'digital_io.c'), -] - -# SSC sources -ssc_src = Glob(os.path.join(sdk_ethercat, 'SSC', 'Src', '*.c')) - -CPPPATH = [ - sdk_ethercat, - os.path.join(sdk_ethercat, 'SSC', 'Src'), -] - -CPPDEFINES = [] - -group = [] - -if GetDepend(['BSP_USING_ETHERCAT']): - group += DefineGroup('EtherCAT_APP', ecat_src, depend=['BSP_USING_ETHERCAT'], CPPPATH=CPPPATH, CPPDEFINES=CPPDEFINES) - group += DefineGroup('EtherCAT_SSC', ssc_src, depend=['BSP_USING_ETHERCAT'], CPPPATH=CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript deleted file mode 100644 index 95d48f3a6ef7..000000000000 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/multicore/SConscript +++ /dev/null @@ -1,64 +0,0 @@ -Import('rtconfig') -from building import * -import os -import glob - -cwd = GetCurrentDir() - -# Locate the nxp-imxrt-sdk package installed by 'pkgs --update'. -# The directory is named nxp-imxrt-sdk- under packages/. -bsp_pkg_dir = os.path.normpath(os.path.join(cwd, '..', 'packages')) -sdk_candidates = glob.glob(os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-*', 'MIMXRT1180', 'multicore')) -if sdk_candidates: - sdk_multicore = sdk_candidates[0] -else: - sdk_multicore = os.path.join(bsp_pkg_dir, 'nxp-imxrt-sdk-latest', 'MIMXRT1180', 'multicore') - -# Base multicore sources (always included when BSP_USE_MULTICORE is enabled) -src = Split(""" -mcmgr/src/mcmgr.c -mcmgr/src/mcmgr_internal_core_api_imxrt1180.c -mcmgr/src/mcmgr_mu_internal.c -""") - -src = [os.path.join(sdk_multicore, f.strip()) for f in src] - -# Add RPMsg-Lite sources if enabled -if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - rpmsg_src = Split(""" - rpmsg-lite/lib/common/llist.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_lite.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_queue.c - rpmsg-lite/lib/rpmsg_lite/rpmsg_ns.c - rpmsg-lite/lib/virtio/virtqueue.c - rpmsg-lite/lib/rpmsg_lite/porting/environment/rpmsg_env_rtthread.c - rpmsg-lite/lib/rpmsg_lite/porting/platform/imxrt1180/rpmsg_platform.c - """) - src += [os.path.join(sdk_multicore, f.strip()) for f in rpmsg_src] - -# Base include paths -CPPPATH = [ - cwd, - os.path.join(sdk_multicore, 'mcmgr', 'inc'), - os.path.join(sdk_multicore, 'mcmgr', 'inc', 'platform', 'imxrt1180'), -] - -# Add RPMsg-Lite include paths if enabled -if GetDepend(['BSP_USE_MULTICORE_RPMSG_LITE']): - CPPPATH += [ - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'environment', 'rtthread'), - os.path.join(sdk_multicore, 'rpmsg-lite', 'lib', 'include', 'platform', 'imxrt1180'), - ] - -# Define preprocessor macros -CPPDEFINES = [] - -# Create component group with dependency on BSP_USE_MULTICORE -group = DefineGroup('MultiCore', - src, - depend=['BSP_USE_MULTICORE'], - CPPPATH=CPPPATH, - CPPDEFINES=CPPDEFINES) - -Return('group') From 93c8b20adfe2544bf802abb11ecf29c50f38fe93 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Fri, 7 Aug 2026 19:39:36 +0800 Subject: [PATCH 28/31] Added CONFIG_BSP_USING_GPIO=y to Peripheral.hyperflash_dma. --- .../imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml index af8ac011088b..c4d45b4a1d9b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -12,6 +12,7 @@ Peripheral.hyperflash_dma: - CONFIG_BSP_USING_FLEXSPI=y - CONFIG_BSP_USING_FLEXSPI1=y - CONFIG_BSP_USING_OSPI_FLASH=y + - CONFIG_BSP_USING_GPIO=y Peripheral.hyperflash: <<: *scons kconfig: From 8de75249a4a429a6489e862b2246634328491581 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Mon, 10 Aug 2026 11:02:25 +0800 Subject: [PATCH 29/31] Added CONFIG_BSP_USING_GPIO=y for Peripheral.hyperflash. --- .../imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml index c4d45b4a1d9b..be051e4a4ad3 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -19,6 +19,7 @@ Peripheral.hyperflash: - CONFIG_BSP_USING_FLEXSPI=y - CONFIG_BSP_USING_FLEXSPI1=y - CONFIG_BSP_USING_OSPI_FLASH=y + - CONFIG_BSP_USING_GPIO=y Peripheral.qspi_flash_FS: <<: *scons kconfig: From 0d913dc7c0dfdb0c1233d1c24982c219c11e3d73 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Mon, 10 Aug 2026 11:56:52 +0800 Subject: [PATCH 30/31] Reformat code according to coding standards. --- .../cm33/applications/multicore_thread.c | 68 +-- .../imxrt1180-nxp-evk/cm33/board/board.c | 226 +++++---- .../cm33/board/cherryusb_cdc_acm.c | 36 +- .../cm33/board/cherryusb_port.c | 12 +- .../cm33/board/ports/drv_flexspi_nor_flash.h | 30 +- .../cm33/board/ports/fal_cfg.h | 18 +- .../cm33/board/usbh_mouse_demo.c | 2 +- .../cm7/applications/ecat_thread.c | 12 +- .../imxrt1180-nxp-evk/cm7/applications/main.c | 7 - .../imxrt1180-nxp-evk/cm7/applications/mnt.c | 8 +- .../cm7/applications/multicore_thread.c | 76 +-- .../cm7/board/MCUX_Config/pin_mux.c | 31 +- .../cm7/board/MCUX_Config/pin_mux.h | 72 +-- .../imxrt/imxrt1180-nxp-evk/cm7/board/board.c | 153 +++--- .../imxrt/imxrt1180-nxp-evk/cm7/board/board.h | 18 +- .../cm7/board/cherryusb_cdc_acm.c | 36 +- .../cm7/board/cherryusb_port.c | 12 +- .../cm7/board/ports/drv_flexspi_nor_flash.c | 97 ++-- .../cm7/board/ports/drv_flexspi_nor_flash.h | 30 +- .../cm7/board/ports/fal_cfg.h | 18 +- .../cm7/board/ports/fal_flash_port.c | 17 +- .../cm7/board/ports/flexspi_port.h | 98 ++-- .../cm7/board/usbh_mouse_demo.c | 2 +- .../imx/imxrt/libraries/drivers/drv_netc.c | 94 ++-- .../imx/imxrt/libraries/drivers/drv_uart.c | 460 +++++++++--------- 25 files changed, 816 insertions(+), 817 deletions(-) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c index dc04a7c2dbaf..9cdd88d68c62 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c @@ -27,13 +27,13 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define MULTICORE_THREAD_STACK_SIZE 2048 -#define MULTICORE_THREAD_PRIORITY 10 -#define MULTICORE_THREAD_TIMESLICE 5 +#define MULTICORE_THREAD_STACK_SIZE 2048 +#define MULTICORE_THREAD_PRIORITY 10 +#define MULTICORE_THREAD_TIMESLICE 5 #ifdef BSP_USE_MULTICORE_RPMSG_LITE #ifndef RPMSG_LITE_LINK_ID -#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) #endif #ifndef RPMSG_NS_ANNOUNCE_STRING @@ -43,25 +43,25 @@ #endif #ifndef RPMSG_LOCAL_EPT_ADDR -#define LOCAL_EPT_ADDR (40U) +#define LOCAL_EPT_ADDR (40U) #else -#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR #endif #ifndef RPMSG_SHARED_MEM_SIZE -#define SH_MEM_TOTAL_SIZE (6144U) +#define SH_MEM_TOTAL_SIZE (6144U) #else -#define SH_MEM_TOTAL_SIZE RPMSG_SHARED_MEM_SIZE +#define SH_MEM_TOTAL_SIZE RPMSG_SHARED_MEM_SIZE #endif -#define APP_RPMSG_READY_EVENT_DATA (1U) +#define APP_RPMSG_READY_EVENT_DATA (1U) typedef struct the_message { uint32_t DATA; } THE_MESSAGE, *THE_MESSAGE_PTR; -static THE_MESSAGE msg = {0}; +static THE_MESSAGE msg = { 0 }; /* Shared memory for RPMsg */ #if defined(__ICCARM__) /* IAR Workbench */ @@ -76,11 +76,11 @@ static char rpmsg_lite_base[SH_MEM_TOTAL_SIZE] __attribute__((section(".noinit.$ #endif static struct rpmsg_lite_instance *my_rpmsg = NULL; -static struct rpmsg_lite_endpoint *my_ept = NULL; -static rpmsg_queue_handle my_queue = NULL; -static rpmsg_ns_handle ns_handle = NULL; -static bool error_occurred = false; -static volatile uint32_t remote_addr = 0U; +static struct rpmsg_lite_endpoint *my_ept = NULL; +static rpmsg_queue_handle my_queue = NULL; +static rpmsg_ns_handle ns_handle = NULL; +static bool error_occurred = false; +static volatile uint32_t remote_addr = 0U; #endif /* BSP_USE_MULTICORE_RPMSG_LITE */ #ifdef BSP_USE_MULTICORE_KICK_OFF @@ -120,10 +120,10 @@ static rt_err_t multicore_kickoff_init(void) #endif /* Get CM7 core image information */ - if (kStatus_Success != BOARD_GetCore1ImageAddrSize(&core1_image_source_addr, - &core1_image_dest_addr, - &core1_image_size, - &core1_boot_addr)) + if (kStatus_Success != BOARD_GetCore1ImageAddrSize(&core1_image_source_addr, + &core1_image_dest_addr, + &core1_image_size, + &core1_boot_addr)) { rt_kprintf("[Multicore] Failed to get CM7 core image info!\r\n"); return -RT_ERROR; @@ -132,18 +132,18 @@ static rt_err_t multicore_kickoff_init(void) rt_kprintf("[Multicore] CM7 core image info:\r\n"); rt_kprintf(" Source addr = 0x%08x\r\n", core1_image_source_addr); rt_kprintf(" Dest addr = 0x%08x\r\n", core1_image_dest_addr); - rt_kprintf(" Size = %u (~%uK) bytes\r\n", + rt_kprintf(" Size = %u (~%uK) bytes\r\n", core1_image_size, (core1_image_size + 1023UL) / 1024UL); rt_kprintf(" Boot addr = 0x%08x\r\n", core1_boot_addr); /* Prepare CM7 core */ - BOARD_PrepareCore1(core1_image_source_addr, core1_image_dest_addr, + BOARD_PrepareCore1(core1_image_source_addr, core1_image_dest_addr, core1_image_size, core1_boot_addr); #ifdef BSP_USE_MULTICORE_RPMSG_LITE /* Boot CM7 core application */ rt_kprintf("[Multicore] Starting CM7 core...\r\n"); - (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, + (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, (uint32_t)rpmsg_lite_base, kMCMGR_Start_Synchronous); /* Wait until the CM7 core signals it's ready */ @@ -156,7 +156,7 @@ static rt_err_t multicore_kickoff_init(void) #else /* Boot CM7 core without RPMsg */ rt_kprintf("[Multicore] Starting CM7 core...\r\n"); - (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, + (void)MCMGR_StartCore(kMCMGR_Core1, (void *)core1_boot_addr, 0, kMCMGR_Start_Synchronous); rt_kprintf("[Multicore] CM7 core started!\r\n"); #endif @@ -166,7 +166,7 @@ static rt_err_t multicore_kickoff_init(void) #endif /* BSP_USE_MULTICORE_KICK_OFF */ #ifdef BSP_USE_MULTICORE_RPMSG_LITE -static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, uint32_t flags, void *user_data) { uint32_t *data = (uint32_t *)user_data; @@ -178,7 +178,7 @@ static rt_err_t rpmsg_lite_init(void) rt_kprintf("[RPMsg] Initializing RPMsg-Lite (CM33 as master)...\r\n"); /* Initialize RPMsg-Lite as master */ - my_rpmsg = rpmsg_lite_master_init(rpmsg_lite_base, SH_MEM_TOTAL_SIZE, + my_rpmsg = rpmsg_lite_master_init(rpmsg_lite_base, SH_MEM_TOTAL_SIZE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); if (my_rpmsg == NULL) { @@ -233,26 +233,26 @@ static void rpmsg_lite_communication(void) /* Send the first message to CM7 */ msg.DATA = 0U; rt_kprintf("[RPMsg] Sending initial ping: %u\r\n", msg.DATA); - (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_DONT_BLOCK); while (msg.DATA <= 100U) { uint32_t recv_addr = 0; - + rt_kprintf("[RPMsg] Waiting for pong from CM7...\r\n"); - - (void)rpmsg_queue_recv(my_rpmsg, my_queue, &recv_addr, (char *)&msg, + + (void)rpmsg_queue_recv(my_rpmsg, my_queue, &recv_addr, (char *)&msg, sizeof(THE_MESSAGE), &len, RL_BLOCK); - + rt_kprintf("[RPMsg] Received pong: %u (size=%u)\r\n", msg.DATA, len); - + msg.DATA++; - + if (msg.DATA <= 100U) { rt_kprintf("[RPMsg] Sending ping: %u\r\n", msg.DATA); - (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); } } @@ -364,4 +364,4 @@ int multicore_init(void) } INIT_APP_EXPORT(multicore_init); -#endif /* BSP_USE_MULTICORE */ \ No newline at end of file +#endif /* BSP_USE_MULTICORE */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index 6039e87d1323..6ba6cab7485d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -13,8 +13,8 @@ #include "fsl_common.h" #include "board.h" #if defined(SDK_NETC_USED) && SDK_NETC_USED - #include "fsl_netc_soc.h" - #include "fsl_netc_ierb.h" +#include "fsl_netc_soc.h" +#include "fsl_netc_ierb.h" #endif /* SDK_NETC_USED */ #include "fsl_iomuxc.h" #include "fsl_cache.h" @@ -36,16 +36,16 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) @@ -151,9 +151,9 @@ status_t BOARD_GetCore1ImageAddrSize(uint32_t *pImageSrcAddr, uint32_t i, j; - uint32_t image_src_addr = 0U; + uint32_t image_src_addr = 0U; uint32_t image_dest_addr = 0U; - uint32_t image_size = 0U; + uint32_t image_size = 0U; uint32_t image_boot_addr = 0U; status_t ret = kStatus_Fail; @@ -181,11 +181,11 @@ status_t BOARD_GetCore1ImageAddrSize(uint32_t *pImageSrcAddr, if ((image_type == IMAGE_TYPE_EXECUTABLE) && (image_core == CORE_ID_CM7)) { /* pImage[0] is the image offset, which is based on current container header */ - image_src_addr = ((uint32_t)pContainer) + pImage[0]; - image_size = pImage[1]; + image_src_addr = ((uint32_t)pContainer) + pImage[0]; + image_size = pImage[1]; image_dest_addr = pImage[2]; image_boot_addr = pImage[4]; - ret = kStatus_Success; + ret = kStatus_Success; break; } @@ -247,25 +247,25 @@ void BOARD_PrepareCore1(uint32_t image_src_addr, uint32_t image_dest_addr, uint3 * 2. CM7 Reset_Handler will update CM7 VTOR to real vector addr of the CM7 image. * 3. The workaround doesn't take effect(also no side effect), when CM7 TCM ECC fuse is set(0) */ - uint32_t *pRamVect = (uint32_t *)CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN; + uint32_t *pRamVect = (uint32_t *)CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN; uint32_t *pBootVect = (uint32_t *)boot_addr; - pRamVect[0] = pBootVect[0]; - pRamVect[1] = pBootVect[1]; + pRamVect[0] = pBootVect[0]; + pRamVect[1] = pBootVect[1]; #endif /* (defined(ENABLE_WORKAROUND_CM7_KICK_OFF) && (ENABLE_WORKAROUND_CM7_KICK_OFF > 0U)) */ } /* The Cortex M7 image runs from internal ITCM RAM */ else { #if ENABLE_CM7_TCM_ECC - /* Do noting, CM7 image has been copied by ROM */ -#else + /* Do noting, CM7 image has been copied by ROM */ +#else Prepare_CM7(boot_addr); /* Copy CM7 image from FLASH to CM7 ITCM */ if ((image_size > 0) && (image_size < CM7_ITCM_SIZE)) { /* Use memcpy to copy the image */ (void)memcpy((void *)CM7_ITCM_ADDR_MAP_AT_CM33_DOMAIN, (void *)image_src_addr, image_size); - + /* Ensure data is written to memory before CM7 starts */ __DSB(); __ISB(); @@ -284,17 +284,17 @@ void BOARD_ConfigMPU(void) /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ extern uint32_t Image$$RW_m_ncache_aux$$Base[]; uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_NCACHE_REGION; extern uint32_t __top_NCACHE_REGION; uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __NCACHE_REGION_START[]; extern uint32_t __NCACHE_REGION_SIZE[]; uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; #endif #if defined(__USE_SHMEM) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -302,17 +302,17 @@ void BOARD_ConfigMPU(void) /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; - uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_SHMEM_REGION; extern uint32_t __top_SHMEM_REGION; uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); - uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __RPMSG_SH_MEM_START[]; extern uint32_t __RPMSG_SH_MEM_SIZE[]; uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; - uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; #endif #endif volatile uint32_t i; @@ -488,17 +488,17 @@ void BOARD_ConfigMPU(void) /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ extern uint32_t Image$$RW_m_ncache_aux$$Base[]; uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_NCACHE_REGION; extern uint32_t __top_NCACHE_REGION; uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __NCACHE_REGION_START[]; extern uint32_t __NCACHE_REGION_SIZE[]; uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; #endif #if defined(__USE_SHMEM) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -506,17 +506,17 @@ void BOARD_ConfigMPU(void) /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; - uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_SHMEM_REGION; extern uint32_t __top_SHMEM_REGION; uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); - uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __RPMSG_SH_MEM_START[]; extern uint32_t __RPMSG_SH_MEM_SIZE[]; uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; - uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; #endif #endif uint32_t i; @@ -740,13 +740,13 @@ void BOARD_InitFlash(FLEXSPI_Type *base) if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) { lastStatus = base->STS2; - retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; /* Wait slave delay line locked and slave reference delay line locked. */ do { status = base->STS2; if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) == - (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) + (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) { /* Locked */ retry = 100; @@ -759,11 +759,10 @@ void BOARD_InitFlash(FLEXSPI_Type *base) } else { - retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; lastStatus = status; } - } - while (retry > 0); + } while (retry > 0); /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ for (; retry > 0U; retry--) { @@ -815,7 +814,7 @@ void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) } if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) || - ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) + ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) { /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock @@ -860,23 +859,21 @@ void BOARD_FlexspiClockSafeConfig(void) void EdgeLock_SetClock(uint8_t mux, uint8_t div) { if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) || - (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) + (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) { status_t sts; uint32_t ele_clk_mhz; - clock_root_config_t rootCfg = - { - .div = div, - .mux = mux, + clock_root_config_t rootCfg = { + .div = div, + .mux = mux, .clockOff = false, }; do { sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA); - } - while (sts != kStatus_Success); + } while (sts != kStatus_Success); CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg); @@ -884,8 +881,7 @@ void EdgeLock_SetClock(uint8_t mux, uint8_t div) do { sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0); - } - while (sts != kStatus_Success); + } while (sts != kStatus_Success); } } @@ -999,21 +995,19 @@ void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) void APP_CommonTrdcDACSetting(void) { - trdc_processor_domain_assignment_t procAssign = {.domainId = 0U, - .domainIdSelect = kTRDC_DidInput, - .pidDomainHitConfig = kTRDC_pidDomainHitNone0, - .pidMask = 0U, - .secureAttr = kTRDC_ForceSecure, - .pid = 0U, - .lock = false - }; - - trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U, - .privilegeAttr = kTRDC_ForcePrivilege, - .secureAttr = kTRDC_ForceSecure, - .bypassDomainId = true, - .lock = false - }; + trdc_processor_domain_assignment_t procAssign = { .domainId = 0U, + .domainIdSelect = kTRDC_DidInput, + .pidDomainHitConfig = kTRDC_pidDomainHitNone0, + .pidMask = 0U, + .secureAttr = kTRDC_ForceSecure, + .pid = 0U, + .lock = false }; + + trdc_non_processor_domain_assignment_t nonProcAssign = { .domainId = 0U, + .privilegeAttr = kTRDC_ForcePrivilege, + .secureAttr = kTRDC_ForceSecure, + .bypassDomainId = true, + .lock = false }; /* 1. Set the MDAC Configuration in TRDC1. */ /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */ @@ -1103,7 +1097,7 @@ static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) uint32_t memNumber = 0U; if (trdc == TRDC1) { - uint8_t MemNum[2] = {3, 2}; + uint8_t MemNum[2] = { 3, 2 }; switch (mbc) { case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */ @@ -1116,7 +1110,7 @@ static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) } else if (trdc == TRDC2) { - uint8_t MemNum[2] = {4, 4}; + uint8_t MemNum[2] = { 4, 4 }; switch (mbc) { case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */ @@ -1249,11 +1243,11 @@ static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStart { case 0: /* TRDC1 MRC_A0 CM33 ROM */ *pStartAddr = 0x00000000UL; - *pStopAddr = 0x00027FFFUL; + *pStopAddr = 0x00027FFFUL; break; case 1: /* TRDC1 MRC_A1 FlexSPI2 */ *pStartAddr = 0x04000000UL; - *pStopAddr = 0x07FFFFFFUL; + *pStopAddr = 0x07FFFFFFUL; break; default: r = false; @@ -1266,27 +1260,27 @@ static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStart { case 1: /* TRDC2 MRC_W1 FlexSPI1 */ *pStartAddr = 0x28000000UL; - *pStopAddr = 0x2FFFFFFFUL; + *pStopAddr = 0x2FFFFFFFUL; break; case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */ *pStartAddr = 0x203C0000UL; - *pStopAddr = 0x2043FFFFUL; + *pStopAddr = 0x2043FFFFUL; break; case 3: /* TRDC2 MRC_W3 OCRAM1 */ *pStartAddr = 0x20480000UL; - *pStopAddr = 0x204FFFFFUL; + *pStopAddr = 0x204FFFFFUL; break; case 4: /* TRDC2 MRC_W4 OCRAM2 */ *pStartAddr = 0x20500000UL; - *pStopAddr = 0x2053FFFFUL; + *pStopAddr = 0x2053FFFFUL; break; case 5: /* TRDC2 MRC_W5 SEMC */ *pStartAddr = 0x80000000UL; - *pStopAddr = 0x8FFFFFFFUL; + *pStopAddr = 0x8FFFFFFFUL; break; case 6: /* TRDC2 MRC_W6 NETC */ *pStartAddr = 0x60000000UL; - *pStopAddr = 0x60FFFFFFUL; + *pStopAddr = 0x60FFFFFFUL; break; default: r = false; @@ -1307,18 +1301,18 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) /* Enable all read/write/execute access for MRC/MBC access control. */ (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig)); - memAccessConfig.nonsecureUsrX = 1U; - memAccessConfig.nonsecureUsrW = 1U; - memAccessConfig.nonsecureUsrR = 1U; + memAccessConfig.nonsecureUsrX = 1U; + memAccessConfig.nonsecureUsrW = 1U; + memAccessConfig.nonsecureUsrR = 1U; memAccessConfig.nonsecurePrivX = 1U; memAccessConfig.nonsecurePrivW = 1U; memAccessConfig.nonsecurePrivR = 1U; - memAccessConfig.secureUsrX = 1U; - memAccessConfig.secureUsrW = 1U; - memAccessConfig.secureUsrR = 1U; - memAccessConfig.securePrivX = 1U; - memAccessConfig.securePrivW = 1U; - memAccessConfig.securePrivR = 1U; + memAccessConfig.secureUsrX = 1U; + memAccessConfig.secureUsrW = 1U; + memAccessConfig.secureUsrR = 1U; + memAccessConfig.securePrivX = 1U; + memAccessConfig.securePrivW = 1U; + memAccessConfig.securePrivR = 1U; for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) { @@ -1343,14 +1337,14 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) } memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig)); - mbcBlockConfig.nseEnable = false; + mbcBlockConfig.nseEnable = false; mbcBlockConfig.memoryAccessControlSelect = 0; memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig)); mrcRegionConfig.memoryAccessControlSelect = 0U; - mrcRegionConfig.valid = true; - mrcRegionConfig.nseEnable = false; - mrcRegionConfig.regionIdx = 0U; + mrcRegionConfig.valid = true; + mrcRegionConfig.nseEnable = false; + mrcRegionConfig.regionIdx = 0U; for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++) { @@ -1370,8 +1364,8 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem); for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++) { - mbcBlockConfig.domainIdx = domain; - mbcBlockConfig.mbcIdx = mbc; + mbcBlockConfig.domainIdx = domain; + mbcBlockConfig.mbcIdx = mbc; mbcBlockConfig.slaveMemoryIdx = mem; mbcBlockConfig.memoryBlockIdx = block; TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig); @@ -1391,9 +1385,9 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr)) { mrcRegionConfig.startAddr = start_addr; - mrcRegionConfig.endAddr = end_addr; + mrcRegionConfig.endAddr = end_addr; mrcRegionConfig.domainIdx = domain; - mrcRegionConfig.mrcIdx = mrc; + mrcRegionConfig.mrcIdx = mrc; TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig); } else @@ -1433,35 +1427,40 @@ void SysTick_Handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #ifdef BSP_USE_MULTICORE_KICK_OFF_DIRECTLY static int second_core_boot(void) { - /* + /* * RT1180 Specific CM7 Kick Off operation */ - /* Trigger S401 */ - while ((MU_RT_S3MUA->TSR & MU_TSR_TE0_MASK) == 0) { - ; } /* Wait TR empty */ - MU_RT_S3MUA->TR[0] = 0x17d20106; - while ((MU_RT_S3MUA->RSR & MU_RSR_RF0_MASK) == 0) { - ; } /* Wait RR Full */ - while ((MU_RT_S3MUA->RSR & MU_RSR_RF1_MASK) == 0) { - ; } /* Wait RR Full */ - - /* Response from ELE must be always read */ - __attribute__((unused)) volatile uint32_t result1, result2; - result1 = MU_RT_S3MUA->RR[0]; - result2 = MU_RT_S3MUA->RR[1]; - - /* Deassert Wait */ - BLK_CTRL_S_AONMIX->M7_CFG = - (BLK_CTRL_S_AONMIX->M7_CFG & (~BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK)) | - BLK_CTRL_S_AONMIX_M7_CFG_WAIT(0); - - return 0; + /* Trigger S401 */ + while ((MU_RT_S3MUA->TSR & MU_TSR_TE0_MASK) == 0) + { + ; + } /* Wait TR empty */ + MU_RT_S3MUA->TR[0] = 0x17d20106; + while ((MU_RT_S3MUA->RSR & MU_RSR_RF0_MASK) == 0) + { + ; + } /* Wait RR Full */ + while ((MU_RT_S3MUA->RSR & MU_RSR_RF1_MASK) == 0) + { + ; + } /* Wait RR Full */ + + /* Response from ELE must be always read */ + __attribute__((unused)) volatile uint32_t result1, result2; + result1 = MU_RT_S3MUA->RR[0]; + result2 = MU_RT_S3MUA->RR[1]; + + /* Deassert Wait */ + BLK_CTRL_S_AONMIX->M7_CFG = + (BLK_CTRL_S_AONMIX->M7_CFG & (~BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK)) | + BLK_CTRL_S_AONMIX_M7_CFG_WAIT(0); + + return 0; } /*! @@ -1492,19 +1491,19 @@ void PHY_Reset(void) RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 1); RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 1); RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 1); - SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); + SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); } #endif void rt_hw_board_init() { - extern void BOARD_InitPeripherals(void); + extern void BOARD_InitPeripherals(void); BOARD_CommonSetting(); BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); // BOARD_InitPeripherals(); - + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); @@ -1529,6 +1528,5 @@ void rt_hw_board_init() HEAP_BEGIN, HEAP_END, (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); #endif - } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c index 03b3d097efa2..fcd6880da49b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_cdc_acm.c @@ -10,22 +10,22 @@ #include "usbd_core.h" #include "usbd_cdc_acm.h" -#define RT1180_CDC_IN_EP 0x81 -#define RT1180_CDC_OUT_EP 0x02 -#define RT1180_CDC_INT_EP 0x83 -#define RT1180_CDC_INTF_NUM 0x00 -#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 +#define RT1180_CDC_IN_EP 0x81 +#define RT1180_CDC_OUT_EP 0x02 +#define RT1180_CDC_INT_EP 0x83 +#define RT1180_CDC_INTF_NUM 0x00 +#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 -#define RT1180_USBD_VID 0xFFFF -#define RT1180_USBD_PID 0xFFFF -#define RT1180_USBD_MAX_POWER 100 +#define RT1180_USBD_VID 0xFFFF +#define RT1180_USBD_PID 0xFFFF +#define RT1180_USBD_MAX_POWER 100 -#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) +#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) #ifdef CONFIG_USB_HS -#define RT1180_CDC_MAX_MPS 512 +#define RT1180_CDC_MAX_MPS 512 #else -#define RT1180_CDC_MAX_MPS 64 +#define RT1180_CDC_MAX_MPS 64 #endif static const uint8_t rt1180_cdc_device_descriptor[] = { @@ -70,10 +70,16 @@ static const uint8_t rt1180_cdc_msos_compat_id_descriptor[] = { }; static const uint8_t rt1180_cdc_msos_properties_descriptor[] = { - 0x0a, 0x00, 0x00, 0x00, - 0x00, 0x01, - 0x05, 0x00, - 0x00, 0x00, + 0x0a, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x05, + 0x00, + 0x00, + 0x00, }; static const uint8_t *rt1180_cdc_msos_properties[] = { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c index 19d62658d0d5..545758cb256d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/cherryusb_port.c @@ -22,10 +22,10 @@ #include "usbh_core.h" #endif -#define RT1180_USB_EHCI0_ID 2U -#define RT1180_USB_EHCI_COUNT 2U -#define RT1180_USB_INVALID_INDEX 0xffU -#define RT1180_USB_IRQ_PRIORITY 3U +#define RT1180_USB_EHCI0_ID 2U +#define RT1180_USB_EHCI_COUNT 2U +#define RT1180_USB_INVALID_INDEX 0xffU +#define RT1180_USB_IRQ_PRIORITY 3U typedef enum _usb_controller_index { @@ -127,8 +127,8 @@ static void rt1180_usb_nc_init(uint8_t index) static void rt1180_usb_phy_enable_vbus_override(USBPHY_Type *phy) { #if defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) && \ - defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ - defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ defined(USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) uint32_t vbus_detect = USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK | diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h index 51b51a3c0836..0241f08353b6 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.h @@ -19,18 +19,18 @@ * FLASH_SIZE = 0x4000 (Unit: KB) = 16MB * FlexSPI1_AMBA_BASE = 0x28000000 * ============================================================ */ -#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */ -#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */ -#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */ -#define QSPI_PAGE_SIZE 256U /* 256B */ +#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */ +#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */ +#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */ +#define QSPI_PAGE_SIZE 256U /* 256B */ /* * Partition Plan (Total 16MB): * 0x00000000 ~ 0x00EFFFFF: Application Code Area (15MB, limited by Scatter) * 0x00F00000 ~ 0x00FFFFFF: File System Area (1MB, LittleFS) */ -#define QSPI_FS_OFFSET 0x00F00000U -#define QSPI_FS_SIZE 0x00100000U +#define QSPI_FS_OFFSET 0x00F00000U +#define QSPI_FS_SIZE 0x00100000U /* ============================================================ * RAM Code Section Attributes @@ -38,22 +38,22 @@ * CPU can safely fetch instructions during FlexSPI IP command execution. * ============================================================ */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) - #define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) +#define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) #elif defined(__GNUC__) - #define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline)) +#define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline)) #elif defined(__ICCARM__) - #define QSPI_RAM_CODE __ramfunc +#define QSPI_RAM_CODE __ramfunc #else - #define QSPI_RAM_CODE +#define QSPI_RAM_CODE #endif /* ============================================================ * External APIs * ============================================================ */ -int rt_qspi_flash_init(void); -int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size); -int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size); -int rt_qspi_flash_erase(uint32_t offset, size_t size); +int rt_qspi_flash_init(void); +int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size); +int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size); +int rt_qspi_flash_erase(uint32_t offset, size_t size); void *rt_qspi_flash_mmap(uint32_t offset, size_t size); -#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */ \ No newline at end of file +#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h index 8b452d177368..25ac53c78db8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_cfg.h @@ -17,20 +17,20 @@ extern const struct fal_flash_dev imxrt1180_nor_flash; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &imxrt1180_nor_flash, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &imxrt1180_nor_flash, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15*1024*1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15*1024*1024, 1*1024*1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15 * 1024 * 1024, 1 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c index d8feb974dd4a..f978c7ca58cb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/usbh_mouse_demo.c @@ -22,7 +22,7 @@ #include "usbh_hid.h" #include "usb_hid.h" -#define RT1180_USBH_MOUSE_REPORT_LEN 64U +#define RT1180_USBH_MOUSE_REPORT_LEN 64U #define RT1180_USBH_MOUSE_THREAD_STACK 2048U struct rt1180_usbh_mouse_state diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c index 1b146af0ed85..48403a17378c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/ecat_thread.c @@ -13,11 +13,11 @@ extern void ecat_main(void); /* EtherCAT thread stack size */ -#define ECAT_THREAD_STACK_SIZE 4096 +#define ECAT_THREAD_STACK_SIZE 4096 /* EtherCAT thread priority */ -#define ECAT_THREAD_PRIORITY 10 +#define ECAT_THREAD_PRIORITY 10 /* EtherCAT thread time slice */ -#define ECAT_THREAD_TIMESLICE 20 +#define ECAT_THREAD_TIMESLICE 20 static void ecat_thread_entry(void *parameter) { @@ -28,7 +28,7 @@ static void ecat_thread_entry(void *parameter) int ecat_thread_init(void) { rt_thread_t ecat_thread; - + /* Create EtherCAT thread */ ecat_thread = rt_thread_create("ecat", ecat_thread_entry, @@ -36,7 +36,7 @@ int ecat_thread_init(void) ECAT_THREAD_STACK_SIZE, ECAT_THREAD_PRIORITY, ECAT_THREAD_TIMESLICE); - + if (ecat_thread != RT_NULL) { rt_thread_startup(ecat_thread); @@ -49,4 +49,4 @@ int ecat_thread_init(void) return -RT_ERROR; } } -INIT_APP_EXPORT(ecat_thread_init); \ No newline at end of file +INIT_APP_EXPORT(ecat_thread_init); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c index 243336989bdc..9a7f3eadac18 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c @@ -14,19 +14,12 @@ #include #include -#define LED_PIN GET_PIN(4, 27) - int main(void) { rt_kprintf("MIMXRT1180_CM7 Hello_World\r\n"); - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); - while (1) { - rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED_PIN, PIN_LOW); rt_thread_mdelay(500); } } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c index 854f9aa21ff1..5ec32db446c1 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c @@ -31,9 +31,9 @@ #include #include -#define FS_PARTITION_NAME "filesystem" -#define FS_TYPE_NAME "lfs" -#define FS_MOUNT_POINT "/" +#define FS_PARTITION_NAME "filesystem" +#define FS_TYPE_NAME "lfs" +#define FS_MOUNT_POINT "/" static int _qspi_flash_fs_mount(void) { @@ -97,4 +97,4 @@ INIT_APP_EXPORT(_qspi_flash_fs_mount); */ INIT_COMPONENT_EXPORT(fal_init); -#endif /* BSP_USING_QSPI_FLASH_FS */ \ No newline at end of file +#endif /* BSP_USING_QSPI_FLASH_FS */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c index 75c5503f34ec..5f253b0e9ff4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/multicore_thread.c @@ -26,12 +26,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define MULTICORE_THREAD_STACK_SIZE 2048 -#define MULTICORE_THREAD_PRIORITY 10 -#define MULTICORE_THREAD_TIMESLICE 5 +#define MULTICORE_THREAD_STACK_SIZE 2048 +#define MULTICORE_THREAD_PRIORITY 10 +#define MULTICORE_THREAD_TIMESLICE 5 #ifdef BSP_USE_MULTICORE_RPMSG_LITE #ifndef RPMSG_LITE_LINK_ID -#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMXRT1180_M33_M7_LINK_ID) #endif #ifndef RPMSG_NS_ANNOUNCE_STRING @@ -41,21 +41,21 @@ #endif #ifndef RPMSG_LOCAL_EPT_ADDR -#define LOCAL_EPT_ADDR (30U) +#define LOCAL_EPT_ADDR (30U) #else -#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR RPMSG_LOCAL_EPT_ADDR #endif -#define APP_RPMSG_READY_EVENT_DATA (1U) +#define APP_RPMSG_READY_EVENT_DATA (1U) typedef struct the_message { uint32_t DATA; } THE_MESSAGE, *THE_MESSAGE_PTR; -static volatile THE_MESSAGE msg = {0}; -static struct rpmsg_lite_instance *volatile my_rpmsg = NULL; -static struct rpmsg_lite_endpoint *volatile my_ept = NULL; +static volatile THE_MESSAGE msg = { 0 }; +static struct rpmsg_lite_instance * volatile my_rpmsg = NULL; +static struct rpmsg_lite_endpoint * volatile my_ept = NULL; static volatile rpmsg_queue_handle my_queue = NULL; static bool error_occurred = false; #endif /* BSP_USE_MULTICORE_RPMSG_LITE */ @@ -66,22 +66,22 @@ static bool error_occurred = false; #ifdef BSP_USE_MULTICORE_KICK_OFF static rt_err_t multicore_kickoff_init(void) { - mcmgr_status_t status; - - rt_kprintf("[Multicore] Initializing MCMGR ...\r\n"); - status = MCMGR_Init(); - if (status != kStatus_MCMGR_Success) - { - rt_kprintf("[Multicore] MCMGR initialization failed!\r\n"); - return -RT_ERROR; - } - rt_kprintf("[Multicore] MCMGR initialized successfully\r\n"); - - return RT_EOK; + mcmgr_status_t status; + + rt_kprintf("[Multicore] Initializing MCMGR ...\r\n"); + status = MCMGR_Init(); + if (status != kStatus_MCMGR_Success) + { + rt_kprintf("[Multicore] MCMGR initialization failed!\r\n"); + return -RT_ERROR; + } + rt_kprintf("[Multicore] MCMGR initialized successfully\r\n"); + + return RT_EOK; } #endif /* BSP_USE_MULTICORE_KICK_OFF */ #ifdef BSP_USE_MULTICORE_RPMSG_LITE -static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, uint32_t flags, void *user_data) { /* Nameservice callback - can be extended as needed */ @@ -101,7 +101,7 @@ static rt_err_t rpmsg_lite_init(void) } while (status != kStatus_MCMGR_Success); /* Initialize RPMsg-Lite as remote (CM7 side) */ - my_rpmsg = rpmsg_lite_remote_init((void *)(char *)(platform_patova(startupData)), + my_rpmsg = rpmsg_lite_remote_init((void *)(char *)(platform_patova(startupData)), RPMSG_LITE_LINK_ID, RL_NO_FLAGS); if (my_rpmsg == NULL) { @@ -111,7 +111,7 @@ static rt_err_t rpmsg_lite_init(void) } /* Signal the CM33 master core we are ready */ - (void)MCMGR_TriggerEvent(kMCMGR_Core0, kMCMGR_RemoteApplicationEvent, + (void)MCMGR_TriggerEvent(kMCMGR_Core0, kMCMGR_RemoteApplicationEvent, APP_RPMSG_READY_EVENT_DATA); /* Wait for link up with CM33 master */ @@ -147,7 +147,7 @@ static rt_err_t rpmsg_lite_init(void) /* Announce service */ // SDK_DelayAtLeastUs(1000000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, (uint32_t)RL_NS_CREATE); rt_kprintf("[RPMsg] Nameservice announced\r\n"); @@ -163,15 +163,15 @@ static void rpmsg_lite_communication(void) while (msg.DATA <= 100U) { rt_kprintf("[RPMsg] Waiting for ping...\r\n"); - - (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, + + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE), NULL, RL_BLOCK); - + msg.DATA++; - + rt_kprintf("[RPMsg] Received: %u, Sending pong: %u\r\n", msg.DATA - 1, msg.DATA); - - (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, + + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); } @@ -209,11 +209,11 @@ static void rpmsg_lite_cleanup(void) ******************************************************************************/ static void multicore_thread_entry(void *parameter) { -#ifndef BSP_USE_MULTICORE_RPMSG_LITE +#ifndef BSP_USE_MULTICORE_RPMSG_LITE uint32_t startupData; - mcmgr_status_t status; + mcmgr_status_t status; #endif - + rt_kprintf("\r\n=== Multicore Communication Thread Started ===\r\n"); #ifdef BSP_USE_MULTICORE_KICK_OFF @@ -248,8 +248,8 @@ static void multicore_thread_entry(void *parameter) { rt_kprintf("[Multicore] Communication completed successfully!\r\n"); } -#else - /* Get the startup data */ +#else + /* Get the startup data */ do { status = MCMGR_GetStartupData(kMCMGR_Core0, &startupData); @@ -287,4 +287,4 @@ int multicore_init(void) } INIT_APP_EXPORT(multicore_init); -#endif /* BSP_USE_MULTICORE */ \ No newline at end of file +#endif /* BSP_USE_MULTICORE */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c index 528f26fd746f..a996efd45c21 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c @@ -31,13 +31,14 @@ processor_version: 0.15.9 * Description : Calls initialization functions. * * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) { +void BOARD_InitBootPins(void) +{ BOARD_InitPins(); #ifdef BSP_USING_ETH BOARD_InitPhyAccessPins(); BOARD_InitEpPins(); - BOARD_InitSwtPort0Pins(); + BOARD_InitSwtPort0Pins(); #endif } @@ -47,10 +48,11 @@ void BOARD_InitBootPins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ +void BOARD_InitPins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ - + #ifdef BSP_USING_LPUART12 IOMUXC_SetPinMux( IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 is configured as LPUART12_TX */ @@ -115,7 +117,6 @@ void BOARD_InitPins(void) { Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ #endif - } @@ -143,7 +144,8 @@ void BOARD_InitPins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitPhyAccessPins(void) { +void BOARD_InitPhyAccessPins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ /* GPIO configuration of ENET4_INT_B on GPIO_AD_12 (pin P17) */ @@ -277,7 +279,8 @@ void BOARD_InitPhyAccessPins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitEpPins(void) { +void BOARD_InitEpPins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ IOMUXC_SetPinMux( @@ -328,7 +331,8 @@ void BOARD_InitEpPins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSwtPort0Pins(void) { +void BOARD_InitSwtPort0Pins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ IOMUXC_SetPinMux( @@ -384,7 +388,8 @@ void BOARD_InitSwtPort0Pins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSwtPort1Pins(void) { +void BOARD_InitSwtPort1Pins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ IOMUXC_SetPinMux( @@ -452,7 +457,8 @@ void BOARD_InitSwtPort1Pins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSwtPort2Pins(void) { +void BOARD_InitSwtPort2Pins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ IOMUXC_SetPinMux( @@ -520,7 +526,8 @@ void BOARD_InitSwtPort2Pins(void) { * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ -void BOARD_InitSwtPort3Pins(void) { +void BOARD_InitSwtPort3Pins(void) +{ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ IOMUXC_SetPinMux( diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h index 2fa7fab64716..c09654d7706f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h @@ -42,69 +42,69 @@ void BOARD_InitPins(void); /* Function assigned for the Corte #ifdef BSP_USING_ETH /* GPIO_AD_25 (coord M15), ENET0_RST_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_CHANNEL 25U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_CHANNEL 25U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN 25U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN_MASK (1U << 25U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN 25U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN_MASK (1U << 25U) /*!< GPIO pin mask */ /* GPIO_B1_13 (coord B11), ENET1_RST_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_CHANNEL 13U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_CHANNEL 13U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ /* GPIO_AD_28 (coord L16), ENET2_RST_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_CHANNEL 28U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_CHANNEL 28U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN 28U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN 28U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */ /* GPIO_B2_01 (coord E10), ENET3_RST_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_CHANNEL 15U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_CHANNEL 15U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN 15U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ /* GPIO_AD_13 (coord N15), ENET4_RST_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_CHANNEL 13U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_CHANNEL 13U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ /* GPIO_AD_12 (coord P17), ENET4_INT_B */ /* Routed pin properties */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_CHANNEL 12U /*!< Signal channel */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_CHANNEL 12U /*!< Signal channel */ /* Symbols to be used with GPIO driver */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN 12U /*!< GPIO pin number */ -#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN_MASK (1U << 12U) /*!< GPIO pin mask */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN 12U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN_MASK (1U << 12U) /*!< GPIO pin mask */ /*! * @brief Configures pin routing and optionally pin electrical features. diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c index ee761f45868e..ffd577ad0aec 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -13,8 +13,8 @@ #include "fsl_common.h" #include "board.h" #if defined(SDK_NETC_USED) && SDK_NETC_USED - #include "fsl_netc_soc.h" - #include "fsl_netc_ierb.h" +#include "fsl_netc_soc.h" +#include "fsl_netc_ierb.h" #endif /* SDK_NETC_USED */ #include "fsl_iomuxc.h" #include "fsl_cache.h" @@ -36,17 +36,17 @@ * Definitions ******************************************************************************/ -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) /******************************************************************************* @@ -68,17 +68,17 @@ void BOARD_ConfigMPU(void) /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ extern uint32_t Image$$RW_m_ncache_aux$$Base[]; uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_NCACHE_REGION; extern uint32_t __top_NCACHE_REGION; uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __NCACHE_REGION_START[]; extern uint32_t __NCACHE_REGION_SIZE[]; uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; #endif #if defined(__USE_SHMEM) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -86,17 +86,17 @@ void BOARD_ConfigMPU(void) /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; - uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_SHMEM_REGION; extern uint32_t __top_SHMEM_REGION; uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); - uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __RPMSG_SH_MEM_START[]; extern uint32_t __RPMSG_SH_MEM_SIZE[]; uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; - uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; #endif #endif volatile uint32_t i; @@ -272,17 +272,17 @@ void BOARD_ConfigMPU(void) /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ extern uint32_t Image$$RW_m_ncache_aux$$Base[]; uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_NCACHE_REGION; extern uint32_t __top_NCACHE_REGION; uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __NCACHE_REGION_START[]; extern uint32_t __NCACHE_REGION_SIZE[]; uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; #endif #if defined(__USE_SHMEM) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -290,17 +290,17 @@ void BOARD_ConfigMPU(void) /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; - uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; #elif defined(__MCUXPRESSO) extern uint32_t __base_SHMEM_REGION; extern uint32_t __top_SHMEM_REGION; uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); - uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; #elif defined(__ICCARM__) || defined(__GNUC__) extern uint32_t __RPMSG_SH_MEM_START[]; extern uint32_t __RPMSG_SH_MEM_SIZE[]; uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; - uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; #endif #endif uint32_t i; @@ -532,13 +532,13 @@ void BOARD_InitFlash(FLEXSPI_Type *base) if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) { lastStatus = base->STS2; - retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; /* Wait slave delay line locked and slave reference delay line locked. */ do { status = base->STS2; if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) == - (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) + (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) { /* Locked */ retry = 100; @@ -551,11 +551,10 @@ void BOARD_InitFlash(FLEXSPI_Type *base) } else { - retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; lastStatus = status; } - } - while (retry > 0); + } while (retry > 0); /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ for (; retry > 0U; retry--) { @@ -607,7 +606,7 @@ void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) } if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) || - ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) + ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) { /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock @@ -652,23 +651,21 @@ void BOARD_FlexspiClockSafeConfig(void) void EdgeLock_SetClock(uint8_t mux, uint8_t div) { if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) || - (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) + (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) { status_t sts; uint32_t ele_clk_mhz; - clock_root_config_t rootCfg = - { - .div = div, - .mux = mux, + clock_root_config_t rootCfg = { + .div = div, + .mux = mux, .clockOff = false, }; do { sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA); - } - while (sts != kStatus_Success); + } while (sts != kStatus_Success); CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg); @@ -676,8 +673,7 @@ void EdgeLock_SetClock(uint8_t mux, uint8_t div) do { sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0); - } - while (sts != kStatus_Success); + } while (sts != kStatus_Success); } } @@ -791,21 +787,19 @@ void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) void APP_CommonTrdcDACSetting(void) { - trdc_processor_domain_assignment_t procAssign = {.domainId = 0U, - .domainIdSelect = kTRDC_DidInput, - .pidDomainHitConfig = kTRDC_pidDomainHitNone0, - .pidMask = 0U, - .secureAttr = kTRDC_ForceSecure, - .pid = 0U, - .lock = false - }; - - trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U, - .privilegeAttr = kTRDC_ForcePrivilege, - .secureAttr = kTRDC_ForceSecure, - .bypassDomainId = true, - .lock = false - }; + trdc_processor_domain_assignment_t procAssign = { .domainId = 0U, + .domainIdSelect = kTRDC_DidInput, + .pidDomainHitConfig = kTRDC_pidDomainHitNone0, + .pidMask = 0U, + .secureAttr = kTRDC_ForceSecure, + .pid = 0U, + .lock = false }; + + trdc_non_processor_domain_assignment_t nonProcAssign = { .domainId = 0U, + .privilegeAttr = kTRDC_ForcePrivilege, + .secureAttr = kTRDC_ForceSecure, + .bypassDomainId = true, + .lock = false }; /* 1. Set the MDAC Configuration in TRDC1. */ /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */ @@ -895,7 +889,7 @@ static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) uint32_t memNumber = 0U; if (trdc == TRDC1) { - uint8_t MemNum[2] = {3, 2}; + uint8_t MemNum[2] = { 3, 2 }; switch (mbc) { case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */ @@ -908,7 +902,7 @@ static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) } else if (trdc == TRDC2) { - uint8_t MemNum[2] = {4, 4}; + uint8_t MemNum[2] = { 4, 4 }; switch (mbc) { case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */ @@ -1041,11 +1035,11 @@ static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStart { case 0: /* TRDC1 MRC_A0 CM33 ROM */ *pStartAddr = 0x00000000UL; - *pStopAddr = 0x00027FFFUL; + *pStopAddr = 0x00027FFFUL; break; case 1: /* TRDC1 MRC_A1 FlexSPI2 */ *pStartAddr = 0x04000000UL; - *pStopAddr = 0x07FFFFFFUL; + *pStopAddr = 0x07FFFFFFUL; break; default: r = false; @@ -1058,27 +1052,27 @@ static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStart { case 1: /* TRDC2 MRC_W1 FlexSPI1 */ *pStartAddr = 0x28000000UL; - *pStopAddr = 0x2FFFFFFFUL; + *pStopAddr = 0x2FFFFFFFUL; break; case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */ *pStartAddr = 0x203C0000UL; - *pStopAddr = 0x2043FFFFUL; + *pStopAddr = 0x2043FFFFUL; break; case 3: /* TRDC2 MRC_W3 OCRAM1 */ *pStartAddr = 0x20480000UL; - *pStopAddr = 0x204FFFFFUL; + *pStopAddr = 0x204FFFFFUL; break; case 4: /* TRDC2 MRC_W4 OCRAM2 */ *pStartAddr = 0x20500000UL; - *pStopAddr = 0x2053FFFFUL; + *pStopAddr = 0x2053FFFFUL; break; case 5: /* TRDC2 MRC_W5 SEMC */ *pStartAddr = 0x80000000UL; - *pStopAddr = 0x8FFFFFFFUL; + *pStopAddr = 0x8FFFFFFFUL; break; case 6: /* TRDC2 MRC_W6 NETC */ *pStartAddr = 0x60000000UL; - *pStopAddr = 0x60FFFFFFUL; + *pStopAddr = 0x60FFFFFFUL; break; default: r = false; @@ -1099,18 +1093,18 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) /* Enable all read/write/execute access for MRC/MBC access control. */ (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig)); - memAccessConfig.nonsecureUsrX = 1U; - memAccessConfig.nonsecureUsrW = 1U; - memAccessConfig.nonsecureUsrR = 1U; + memAccessConfig.nonsecureUsrX = 1U; + memAccessConfig.nonsecureUsrW = 1U; + memAccessConfig.nonsecureUsrR = 1U; memAccessConfig.nonsecurePrivX = 1U; memAccessConfig.nonsecurePrivW = 1U; memAccessConfig.nonsecurePrivR = 1U; - memAccessConfig.secureUsrX = 1U; - memAccessConfig.secureUsrW = 1U; - memAccessConfig.secureUsrR = 1U; - memAccessConfig.securePrivX = 1U; - memAccessConfig.securePrivW = 1U; - memAccessConfig.securePrivR = 1U; + memAccessConfig.secureUsrX = 1U; + memAccessConfig.secureUsrW = 1U; + memAccessConfig.secureUsrR = 1U; + memAccessConfig.securePrivX = 1U; + memAccessConfig.securePrivW = 1U; + memAccessConfig.securePrivR = 1U; for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) { @@ -1135,14 +1129,14 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) } memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig)); - mbcBlockConfig.nseEnable = false; + mbcBlockConfig.nseEnable = false; mbcBlockConfig.memoryAccessControlSelect = 0; memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig)); mrcRegionConfig.memoryAccessControlSelect = 0U; - mrcRegionConfig.valid = true; - mrcRegionConfig.nseEnable = false; - mrcRegionConfig.regionIdx = 0U; + mrcRegionConfig.valid = true; + mrcRegionConfig.nseEnable = false; + mrcRegionConfig.regionIdx = 0U; for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++) { @@ -1162,8 +1156,8 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem); for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++) { - mbcBlockConfig.domainIdx = domain; - mbcBlockConfig.mbcIdx = mbc; + mbcBlockConfig.domainIdx = domain; + mbcBlockConfig.mbcIdx = mbc; mbcBlockConfig.slaveMemoryIdx = mem; mbcBlockConfig.memoryBlockIdx = block; TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig); @@ -1183,9 +1177,9 @@ void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr)) { mrcRegionConfig.startAddr = start_addr; - mrcRegionConfig.endAddr = end_addr; + mrcRegionConfig.endAddr = end_addr; mrcRegionConfig.domainIdx = domain; - mrcRegionConfig.mrcIdx = mrc; + mrcRegionConfig.mrcIdx = mrc; TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig); } else @@ -1256,7 +1250,7 @@ void PHY_Reset(void) RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN, 1); RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN, 1); RGPIO_PinWrite(BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO, BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN, 1); - SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); + SDK_DelayAtLeastUs(150000, CLOCK_GetFreq(kCLOCK_CpuClk)); } #endif @@ -1289,6 +1283,5 @@ void rt_hw_board_init() rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif - } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h index e8833eed44e5..a9f49e4a6038 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h @@ -30,7 +30,7 @@ #define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102 #endif #ifndef BOARD_DEBUG_UART_BASEADDR -#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#define BOARD_DEBUG_UART_BASEADDR (uint32_t)LPUART1 #endif #ifndef BOARD_DEBUG_UART_INSTANCE #define BOARD_DEBUG_UART_INSTANCE 1U @@ -88,7 +88,7 @@ #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO1_0_IRQHandler #define BOARD_USER_BUTTON_NAME "SW8" -#define BOARD_WAKEUP_BUTTON_NAME "SW4" +#define BOARD_WAKEUP_BUTTON_NAME "SW4" /*! @brief The board flash size */ #define BOARD_FLASH_SIZE (0x1000000U) @@ -167,17 +167,17 @@ void PHY_Reset(void); #if defined(__ARMCC_VERSION) extern int Image$$ARM_LIB_HEAP$$ZI$$Base; extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) -#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit) +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Limit) #elif defined(__ICCARM__) -#pragma section="HEAP" -#define HEAP_BEGIN (__section_begin("HEAP")) -#define HEAP_END (__section_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) #elif defined(__GNUC__) extern int __HeapBase; extern int __HeapLimit; -#define HEAP_BEGIN ((void *)&__HeapBase) -#define HEAP_END ((void *)&__HeapLimit) +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) #endif void rt_hw_board_init(void); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c index 03b3d097efa2..fcd6880da49b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_cdc_acm.c @@ -10,22 +10,22 @@ #include "usbd_core.h" #include "usbd_cdc_acm.h" -#define RT1180_CDC_IN_EP 0x81 -#define RT1180_CDC_OUT_EP 0x02 -#define RT1180_CDC_INT_EP 0x83 -#define RT1180_CDC_INTF_NUM 0x00 -#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 +#define RT1180_CDC_IN_EP 0x81 +#define RT1180_CDC_OUT_EP 0x02 +#define RT1180_CDC_INT_EP 0x83 +#define RT1180_CDC_INTF_NUM 0x00 +#define RT1180_CDC_MSOS_VENDOR_CODE 0x17 -#define RT1180_USBD_VID 0xFFFF -#define RT1180_USBD_PID 0xFFFF -#define RT1180_USBD_MAX_POWER 100 +#define RT1180_USBD_VID 0xFFFF +#define RT1180_USBD_PID 0xFFFF +#define RT1180_USBD_MAX_POWER 100 -#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) +#define RT1180_USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) #ifdef CONFIG_USB_HS -#define RT1180_CDC_MAX_MPS 512 +#define RT1180_CDC_MAX_MPS 512 #else -#define RT1180_CDC_MAX_MPS 64 +#define RT1180_CDC_MAX_MPS 64 #endif static const uint8_t rt1180_cdc_device_descriptor[] = { @@ -70,10 +70,16 @@ static const uint8_t rt1180_cdc_msos_compat_id_descriptor[] = { }; static const uint8_t rt1180_cdc_msos_properties_descriptor[] = { - 0x0a, 0x00, 0x00, 0x00, - 0x00, 0x01, - 0x05, 0x00, - 0x00, 0x00, + 0x0a, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x05, + 0x00, + 0x00, + 0x00, }; static const uint8_t *rt1180_cdc_msos_properties[] = { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c index 19d62658d0d5..545758cb256d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/cherryusb_port.c @@ -22,10 +22,10 @@ #include "usbh_core.h" #endif -#define RT1180_USB_EHCI0_ID 2U -#define RT1180_USB_EHCI_COUNT 2U -#define RT1180_USB_INVALID_INDEX 0xffU -#define RT1180_USB_IRQ_PRIORITY 3U +#define RT1180_USB_EHCI0_ID 2U +#define RT1180_USB_EHCI_COUNT 2U +#define RT1180_USB_INVALID_INDEX 0xffU +#define RT1180_USB_IRQ_PRIORITY 3U typedef enum _usb_controller_index { @@ -127,8 +127,8 @@ static void rt1180_usb_nc_init(uint8_t index) static void rt1180_usb_phy_enable_vbus_override(USBPHY_Type *phy) { #if defined(RT_CHERRYUSB_DEVICE) && defined(USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) && \ - defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ - defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) && \ + defined(USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) && \ defined(USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) uint32_t vbus_detect = USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK | diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c index 60f31b39fd74..eb43ad8da7fe 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.c @@ -20,8 +20,8 @@ /* * Logging configuration */ -#define LOG_TAG "drv.flash" -#define LOG_LVL LOG_LVL_INFO +#define LOG_TAG "drv.flash" +#define LOG_LVL LOG_LVL_INFO #include /* @@ -29,10 +29,10 @@ * FLASH_BUSY_STATUS_OFFSET = 0 : WIP bit is SR[0] * FLASH_QUAD_ENABLE = 0x40 : write to SR to enable Quad mode */ -#define FLASH_QUAD_ENABLE_VAL 0x40U +#define FLASH_QUAD_ENABLE_VAL 0x40U /* WIP polling upper limit to prevent infinite loop on Flash failure */ -#define WIP_TIMEOUT_COUNT 2000000UL +#define WIP_TIMEOUT_COUNT 2000000UL /* * Internal write buffer (must reside in SRAM) @@ -45,9 +45,9 @@ static uint8_t SDK_ALIGN(s_write_buf[QSPI_PAGE_SIZE], 4); /* Internal state */ -static imxrt_flexspi_handle_t *s_handle = RT_NULL; -static struct rt_mutex s_mutex; -static int s_inited = 0; +static imxrt_flexspi_handle_t *s_handle = RT_NULL; +static struct rt_mutex s_mutex; +static int s_inited = 0; /* * _range_valid - check whether [offset, offset+size) is within Flash @@ -109,10 +109,10 @@ static status_t _nor_write_enable(rt_uint32_t base_addr) flexspi_transfer_t xfer; xfer.deviceAddress = base_addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Command; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; return FLEXSPI_TransferBlocking(s_handle->base, &xfer); } @@ -125,19 +125,19 @@ static status_t _nor_write_enable(rt_uint32_t base_addr) */ static status_t _nor_wait_busy(void) { - rt_uint32_t read_val = 0; - rt_uint32_t timeout = 0; - status_t status; - rt_bool_t is_busy; + rt_uint32_t read_val = 0; + rt_uint32_t timeout = 0; + status_t status; + rt_bool_t is_busy; flexspi_transfer_t xfer; xfer.deviceAddress = 0; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Read; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; - xfer.data = &read_val; - xfer.dataSize = 1; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + xfer.data = &read_val; + xfer.dataSize = 1; do { @@ -161,8 +161,7 @@ static status_t _nor_wait_busy(void) { return kStatus_Timeout; } - } - while (is_busy); + } while (is_busy); return kStatus_Success; } @@ -174,17 +173,17 @@ static status_t _nor_wait_busy(void) */ static status_t _nor_erase_sector(rt_uint32_t addr) { - rt_base_t level; - status_t status; + rt_base_t level; + status_t status; flexspi_transfer_t xfer; level = rt_hw_interrupt_disable(); xfer.deviceAddress = addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Command; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -220,8 +219,8 @@ static status_t _nor_erase_sector(rt_uint32_t addr) */ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) { - rt_base_t level; - status_t status; + rt_base_t level; + status_t status; flexspi_transfer_t xfer; level = rt_hw_interrupt_disable(); @@ -241,12 +240,12 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) } xfer.deviceAddress = addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Write; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; - xfer.data = (rt_uint32_t *)src; - xfer.dataSize = QSPI_PAGE_SIZE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Write; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + xfer.data = (rt_uint32_t *)src; + xfer.dataSize = QSPI_PAGE_SIZE; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -279,9 +278,9 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) */ int rt_qspi_flash_init(void) { - rt_uint8_t vendor_id = 0; - rt_uint32_t temp = 0; - status_t status; + rt_uint8_t vendor_id = 0; + rt_uint32_t temp = 0; + status_t status; flexspi_transfer_t xfer; if (s_inited) @@ -299,12 +298,12 @@ int rt_qspi_flash_init(void) /* Read Vendor ID to verify Flash connectivity (SDK: flexspi_nor_get_vendor_id) */ xfer.deviceAddress = 0; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Read; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; - xfer.data = &temp; - xfer.dataSize = 1; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; + xfer.data = &temp; + xfer.dataSize = 1; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -410,7 +409,7 @@ void *rt_qspi_flash_mmap(rt_uint32_t offset, rt_size_t size) int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size) { rt_size_t written = 0; - status_t status; + status_t status; if (!s_inited) { @@ -477,7 +476,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) { rt_uint32_t addr; rt_uint32_t addr_end; - status_t status; + status_t status; if (!s_inited) { @@ -496,7 +495,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) return -RT_EINVAL; } - addr = offset; + addr = offset; addr_end = offset + (rt_uint32_t)size; rt_mutex_take(&s_mutex, RT_WAITING_FOREVER); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h index 51b51a3c0836..0241f08353b6 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/drv_flexspi_nor_flash.h @@ -19,18 +19,18 @@ * FLASH_SIZE = 0x4000 (Unit: KB) = 16MB * FlexSPI1_AMBA_BASE = 0x28000000 * ============================================================ */ -#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */ -#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */ -#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */ -#define QSPI_PAGE_SIZE 256U /* 256B */ +#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */ +#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */ +#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */ +#define QSPI_PAGE_SIZE 256U /* 256B */ /* * Partition Plan (Total 16MB): * 0x00000000 ~ 0x00EFFFFF: Application Code Area (15MB, limited by Scatter) * 0x00F00000 ~ 0x00FFFFFF: File System Area (1MB, LittleFS) */ -#define QSPI_FS_OFFSET 0x00F00000U -#define QSPI_FS_SIZE 0x00100000U +#define QSPI_FS_OFFSET 0x00F00000U +#define QSPI_FS_SIZE 0x00100000U /* ============================================================ * RAM Code Section Attributes @@ -38,22 +38,22 @@ * CPU can safely fetch instructions during FlexSPI IP command execution. * ============================================================ */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) - #define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) +#define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) #elif defined(__GNUC__) - #define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline)) +#define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline)) #elif defined(__ICCARM__) - #define QSPI_RAM_CODE __ramfunc +#define QSPI_RAM_CODE __ramfunc #else - #define QSPI_RAM_CODE +#define QSPI_RAM_CODE #endif /* ============================================================ * External APIs * ============================================================ */ -int rt_qspi_flash_init(void); -int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size); -int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size); -int rt_qspi_flash_erase(uint32_t offset, size_t size); +int rt_qspi_flash_init(void); +int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size); +int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size); +int rt_qspi_flash_erase(uint32_t offset, size_t size); void *rt_qspi_flash_mmap(uint32_t offset, size_t size); -#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */ \ No newline at end of file +#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h index 8b452d177368..25ac53c78db8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_cfg.h @@ -17,20 +17,20 @@ extern const struct fal_flash_dev imxrt1180_nor_flash; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &imxrt1180_nor_flash, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &imxrt1180_nor_flash, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15*1024*1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15*1024*1024, 1*1024*1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 15 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 15 * 1024 * 1024, 1 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c index ae1c3c41338a..6cfdb9dc6f64 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/fal_flash_port.c @@ -17,8 +17,8 @@ /* * Logging configuration */ -#define LOG_TAG "fal.flash" -#define LOG_LVL LOG_LVL_INFO +#define LOG_TAG "fal.flash" +#define LOG_LVL LOG_LVL_INFO #include /* FAL ops bridge */ @@ -44,13 +44,12 @@ static int _fal_erase(long offset, size_t size) return rt_qspi_flash_erase((rt_uint32_t)offset, size); } -const struct fal_flash_dev imxrt1180_nor_flash = -{ - .name = "norflash0", - .addr = QSPI_FLASH_BASE, - .len = QSPI_FLASH_SIZE, - .blk_size = QSPI_SECTOR_SIZE, - .ops = { _fal_init, _fal_read, _fal_write, _fal_erase }, +const struct fal_flash_dev imxrt1180_nor_flash = { + .name = "norflash0", + .addr = QSPI_FLASH_BASE, + .len = QSPI_FLASH_SIZE, + .blk_size = QSPI_SECTOR_SIZE, + .ops = { _fal_init, _fal_read, _fal_write, _fal_erase }, .write_gran = QSPI_PAGE_SIZE, }; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h index 4b9a55cd1c86..eb1f073c6967 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h @@ -20,39 +20,39 @@ #if defined(BSP_USING_QSPI_FLASH_FS) /* parameters for flexpsi peripheral */ -#define FLEXSPI1_CONTROL_BASE FLEXSPI1 -#define FLEXSPI2_CONTROL_BASE FLEXSPI2 -#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/ -#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */ -#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ -#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ -#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ -#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ -#define ARD_SEQ_CMD 0xBB /* cmd for read */ -#define AWR_SEQ_CMD 0xAA /* cmd for write */ -#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad -#define FLASH_PORT kFLEXSPI_PortA1 -#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M -#define CLOCK_DIV 2U -#define CUSTOM_LUT_LENGTH 60U +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI2_CONTROL_BASE FLEXSPI2 +#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/ +#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */ +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ +#define ARD_SEQ_CMD 0xBB /* cmd for read */ +#define AWR_SEQ_CMD 0xAA /* cmd for write */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M +#define CLOCK_DIV 2U +#define CUSTOM_LUT_LENGTH 60U #define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U) #define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) -#define COMBINATION_MODE 0U -#define FREE_RUNNING_MODE 0U +#define COMBINATION_MODE 0U +#define FREE_RUNNING_MODE 0U -#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE -#define FLASH_PAGE_SIZE 256 -#define SECTOR_SIZE 0x1000 /* 4K */ -#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1 -#define FLASH_PORT kFLEXSPI_PortA1 +#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE +#define FLASH_PAGE_SIZE 256 +#define SECTOR_SIZE 0x1000 /* 4K */ +#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1 +#define FLASH_PORT kFLEXSPI_PortA1 /* DMA related. */ -#define FLEXSPI_DMA (DMA4) +#define FLEXSPI_DMA (DMA4) #define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx #define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx -#define FLEXSPI_TX_DMA_CHANNEL 0U -#define FLEXSPI_RX_DMA_CHANNEL 2U +#define FLEXSPI_TX_DMA_CHANNEL 0U +#define FLEXSPI_RX_DMA_CHANNEL 2U #define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 #define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 @@ -77,34 +77,34 @@ #include "fsl_cache.h" /* parameters for flexpsi peripheral */ -#define FLEXSPI1_CONTROL_BASE FLEXSPI1 -#define FLEXSPI_ROOT_CLK (400000000U) /* serial root clk: 400MHz*/ -#define FLASH_SIZE (64 * 1024) /* device size 64*1024(KB) = 64MB */ -#define FLASH_PAGE_SIZE 256 -#define SECTOR_SIZE 0x1000 /* 4K */ - -#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ -#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ -#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ -#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ -#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad - -#define FLASH_PORT kFLEXSPI_PortA1 -#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M -#define CLOCK_DIV 2U -#define CUSTOM_LUT_LENGTH 60U +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI_ROOT_CLK (400000000U) /* serial root clk: 400MHz*/ +#define FLASH_SIZE (64 * 1024) /* device size 64*1024(KB) = 64MB */ +#define FLASH_PAGE_SIZE 256 +#define SECTOR_SIZE 0x1000 /* 4K */ + +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad + +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M +#define CLOCK_DIV 2U +#define CUSTOM_LUT_LENGTH 60U #define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U) #define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) -#define COMBINATION_MODE 0U -#define FREE_RUNNING_MODE 0U +#define COMBINATION_MODE 0U +#define FREE_RUNNING_MODE 0U /* DMA related. */ -#define FLEXSPI_DMA (DMA4) +#define FLEXSPI_DMA (DMA4) #define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx #define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx -#define FLEXSPI_TX_DMA_CHANNEL 0U -#define FLEXSPI_RX_DMA_CHANNEL 2U +#define FLEXSPI_TX_DMA_CHANNEL 0U +#define FLEXSPI_RX_DMA_CHANNEL 2U #define NOR_CMD_LUT_SEQ_IDX_READ 0 @@ -126,8 +126,8 @@ So we need to ensure at any time, the FlexSPI LUT sequence 9 for the flash must be set to STOP command to avoid unexpected debugger behaivor. */ -#define NOR_CMD_LUT_SEQ_IDX_WRITE 9 -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI 10 +#define NOR_CMD_LUT_SEQ_IDX_WRITE 9 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI 10 #define FLASH_BUSY_STATUS_POL 1 #define FLASH_BUSY_STATUS_OFFSET 0 @@ -137,7 +137,7 @@ * If cache is enabled, this example should maintain the cache to make sure * CPU core accesses the memory, not cache only. */ -#define CACHE_MAINTAIN 1 +#define CACHE_MAINTAIN 1 /*${macro:end}*/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c index d8feb974dd4a..f978c7ca58cb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/usbh_mouse_demo.c @@ -22,7 +22,7 @@ #include "usbh_hid.h" #include "usb_hid.h" -#define RT1180_USBH_MOUSE_REPORT_LEN 64U +#define RT1180_USBH_MOUSE_REPORT_LEN 64U #define RT1180_USBH_MOUSE_THREAD_STACK 2048U struct rt1180_usbh_mouse_state diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c index 68f22aefe449..6c4dfb1a82d9 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_netc.c @@ -20,11 +20,11 @@ #include #ifndef NETC_RX_ZERO_COPY -#define NETC_RX_ZERO_COPY 1 +#define NETC_RX_ZERO_COPY 1 #endif #ifndef NETC_USE_SWT -#define NETC_USE_SWT 0 +#define NETC_USE_SWT 0 #endif #if NETC_RX_ZERO_COPY && !LWIP_SUPPORT_CUSTOM_PBUF @@ -50,28 +50,28 @@ #define LOG_TAG "drv.netc" #include "drv_log.h" -#define NETC_RING_ID 0U -#define NETC_RXBD_NUM 8U -#define NETC_TXBD_NUM 8U -#define NETC_CMDBD_NUM 8U -#define NETC_RXBUFF_SIZE 1536U -#define NETC_BUFF_ALIGNMENT 64U -#define NETC_FRAME_MAX_FRAMELEN 1518U -#define NETC_RXBUFF_ALIGNED_SIZE \ +#define NETC_RING_ID 0U +#define NETC_RXBD_NUM 8U +#define NETC_TXBD_NUM 8U +#define NETC_CMDBD_NUM 8U +#define NETC_RXBUFF_SIZE 1536U +#define NETC_BUFF_ALIGNMENT 64U +#define NETC_FRAME_MAX_FRAMELEN 1518U +#define NETC_RXBUFF_ALIGNED_SIZE \ (((NETC_RXBUFF_SIZE + NETC_BUFF_ALIGNMENT - 1U) / NETC_BUFF_ALIGNMENT) * NETC_BUFF_ALIGNMENT) -#define NETC_MAX_BUFFERS_PER_FRAME \ +#define NETC_MAX_BUFFERS_PER_FRAME \ ((NETC_FRAME_MAX_FRAMELEN + NETC_RXBUFF_ALIGNED_SIZE - 1U) / NETC_RXBUFF_ALIGNED_SIZE) -#define NETC_PHY_STATUS_REG 0x01U -#define NETC_PHY_LINK_UP_MASK 0x0004U -#define NETC_PHY_POLL_DELAY_TICK (RT_TICK_PER_SECOND) -#define NETC_TX_TIMEOUT_TICK (RT_TICK_PER_SECOND) +#define NETC_PHY_STATUS_REG 0x01U +#define NETC_PHY_LINK_UP_MASK 0x0004U +#define NETC_PHY_POLL_DELAY_TICK (RT_TICK_PER_SECOND) +#define NETC_TX_TIMEOUT_TICK (RT_TICK_PER_SECOND) #if NETC_RXBD_NUM < NETC_MAX_BUFFERS_PER_FRAME #error "NETC_RXBD_NUM < NETC_MAX_BUFFERS_PER_FRAME" #endif #ifndef NETC_RXBUFF_NUM -#define NETC_RXBUFF_NUM (NETC_RXBD_NUM + 5U) +#define NETC_RXBUFF_NUM (NETC_RXBD_NUM + 5U) #endif #if NETC_RX_ZERO_COPY && (NETC_RXBUFF_NUM < (NETC_RXBD_NUM + NETC_MAX_BUFFERS_PER_FRAME)) @@ -84,14 +84,14 @@ #define NETC_RXBUFF_TOTAL_NUM NETC_RXBD_NUM #endif -#define NETC_MII_MODE kNETC_RmiiMode -#define NETC_LINK_SPEED kNETC_MiiSpeed100M -#define NETC_LINK_DUPLEX kNETC_MiiFullDuplex +#define NETC_MII_MODE kNETC_RmiiMode +#define NETC_LINK_SPEED kNETC_MiiSpeed100M +#define NETC_LINK_DUPLEX kNETC_MiiFullDuplex #if NETC_USE_SWT -#define NETC_PSI kNETC_ENETC1PSI0 +#define NETC_PSI kNETC_ENETC1PSI0 #ifndef NETC_PHY_ADDR -#define NETC_PHY_ADDR BOARD_SWT_PORT0_PHY_ADDR +#define NETC_PHY_ADDR BOARD_SWT_PORT0_PHY_ADDR #endif #ifndef NETC_SWT_MAX_PORT_NUM #define NETC_SWT_MAX_PORT_NUM 4U @@ -100,20 +100,20 @@ #define NETC_SWT_USED_PORT_BITMAP 0x5U #endif #ifndef NETC_SWT_PSEUDO_PORT -#define NETC_SWT_PSEUDO_PORT 0x4U +#define NETC_SWT_PSEUDO_PORT 0x4U #endif #ifndef NETC_SWT_TX_PORT -#define NETC_SWT_TX_PORT kNETC_SWITCH0Port0 +#define NETC_SWT_TX_PORT kNETC_SWITCH0Port0 #endif #else -#define NETC_PSI kNETC_ENETC0PSI0 +#define NETC_PSI kNETC_ENETC0PSI0 #ifndef NETC_PHY_ADDR -#define NETC_PHY_ADDR BOARD_EP0_PHY_ADDR +#define NETC_PHY_ADDR BOARD_EP0_PHY_ADDR #endif #endif -#define NETC_MSGINTR MSGINTR1 -#define NETC_MSGINTR_IRQ MSGINTR1_IRQn +#define NETC_MSGINTR MSGINTR1 +#define NETC_MSGINTR_IRQ MSGINTR1_IRQn #define NETC_MSIX_ENTRY_NUM 2U #define TX_MSIX_ENTRY_IDX 0U @@ -123,12 +123,12 @@ #define RX_INTR_MSG_DATA 2U #define SI_COM_INTR_MSG_DATA 3U -#define NETC_DEFAULT_MAC0 0x54U -#define NETC_DEFAULT_MAC1 0x27U -#define NETC_DEFAULT_MAC2 0x8DU -#define NETC_DEFAULT_MAC3 0x11U -#define NETC_DEFAULT_MAC4 0x80U -#define NETC_DEFAULT_MAC5 0x00U +#define NETC_DEFAULT_MAC0 0x54U +#define NETC_DEFAULT_MAC1 0x27U +#define NETC_DEFAULT_MAC2 0x8DU +#define NETC_DEFAULT_MAC3 0x11U +#define NETC_DEFAULT_MAC4 0x80U +#define NETC_DEFAULT_MAC5 0x00U #ifndef RT_NTCP_THREAD_STACK_SIZE #define RT_NTCP_THREAD_STACK_SIZE 4096 @@ -598,7 +598,7 @@ static void _netc_msgintr_callback(MSGINTR_Type *base, uint8_t channel, uint32_t rt_sem_release(&imxrt_netc_device.tx_isr_sem); } - if ((pendingIntr & (1U << RX_INTR_MSG_DATA))!= 0U) + if ((pendingIntr & (1U << RX_INTR_MSG_DATA)) != 0U) { EP_CleanRxIntrFlags(&imxrt_netc_device.ep_handle, 1); (void)eth_device_ready(&imxrt_netc_device.parent); @@ -685,10 +685,10 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) rt_memset(rx_bdr_config, 0, sizeof(rx_bdr_config)); rt_memset(tx_bdr_config, 0, sizeof(tx_bdr_config)); rt_memset(&mdio_config, 0, sizeof(mdio_config)); - + /* MSIX and interrupt configuration. */ MSGINTR_Init(NETC_MSGINTR, &_netc_msgintr_callback); - uint32_t msgAddr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, 0); + uint32_t msgAddr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, 0); g_netc_msix_entry[0].control = kNETC_MsixIntrMaskBit; g_netc_msix_entry[0].msgAddr = msgAddr; g_netc_msix_entry[0].msgData = TX_INTR_MSG_DATA; @@ -738,10 +738,10 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) ep_config.cmdBdrConfig.bdBase = g_netc_cmd_bd; ep_config.cmdBdrConfig.bdLength = NETC_CMDBD_NUM; ep_config.cmdBdrConfig.enCompInt = false; - - ep_config.port.ethMac.miiMode = NETC_MII_MODE; - ep_config.port.ethMac.miiSpeed = NETC_LINK_SPEED; - ep_config.port.ethMac.miiDuplex = NETC_LINK_DUPLEX; + + ep_config.port.ethMac.miiMode = NETC_MII_MODE; + ep_config.port.ethMac.miiSpeed = NETC_LINK_SPEED; + ep_config.port.ethMac.miiDuplex = NETC_LINK_DUPLEX; ep_config.port.ethMac.rxMaxFrameSize = NETC_FRAME_MAX_FRAMELEN; rx_bdr_config[0].extendDescEn = false; @@ -783,7 +783,7 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) LOG_E("EP_Init failed: %d", result); return -RT_ERROR; } - + mdio_config.mdio.type = kNETC_EMdio; mdio_config.srcClockHz = CLOCK_GetRootClockFreq(kCLOCK_Root_Netc); mdio_config.isNegativeDriven = false; @@ -806,7 +806,7 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) LOG_E("EP_Up failed: %d", result); return -RT_ERROR; } - + #if NETC_USE_SWT if (_netc_swt_init(netc) != RT_EOK) { @@ -823,7 +823,7 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) } netc->hw_inited = RT_TRUE; - + EP_MsixSetEntryMask(&netc->ep_handle, TX_MSIX_ENTRY_IDX, false); EP_MsixSetEntryMask(&netc->ep_handle, RX_MSIX_ENTRY_IDX, false); @@ -836,7 +836,7 @@ static rt_err_t _netc_hw_init(struct rt_imxrt_netc *netc) netc->dev_addr[0], netc->dev_addr[1], netc->dev_addr[2], netc->dev_addr[3], netc->dev_addr[4], netc->dev_addr[5]); #endif - + return RT_EOK; } @@ -976,7 +976,7 @@ static rt_err_t rt_imxrt_netc_tx(rt_device_t dev, struct pbuf *p) while (rt_sem_take(&netc->tx_isr_sem, 0) == RT_EOK) { } - + tx_data = rt_malloc(p->tot_len); if (tx_data == RT_NULL) { @@ -999,7 +999,7 @@ static rt_err_t rt_imxrt_netc_tx(rt_device_t dev, struct pbuf *p) result = SWT_SendFrame(&netc->swt_handle, &frame, tx_data, &tx_opt); #else { - swt_mgmt_tx_arg_t tx_arg = {.ring = NETC_RING_ID}; + swt_mgmt_tx_arg_t tx_arg = { .ring = NETC_RING_ID }; result = SWT_SendFrame(&netc->swt_handle, tx_arg, @@ -1035,7 +1035,7 @@ static rt_err_t rt_imxrt_netc_tx(rt_device_t dev, struct pbuf *p) { return _netc_wait_tx_complete(netc); } - + return RT_EOK; } diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index 3933d7bcaaac..cc4106a448e0 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -22,51 +22,51 @@ #include "fsl_dmamux.h" #endif -#define LOG_TAG "drv.usart" +#define LOG_TAG "drv.usart" #include #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - enum - { - #ifdef BSP_USING_LPUART1 - LPUART1_INDEX, - #endif - #ifdef BSP_USING_LPUART2 - LPUART2_INDEX, - #endif - #ifdef BSP_USING_LPUART3 - LPUART3_INDEX, - #endif - #ifdef BSP_USING_LPUART4 - LPUART4_INDEX, - #endif - #ifdef BSP_USING_LPUART5 - LPUART5_INDEX, - #endif - #ifdef BSP_USING_LPUART6 - LPUART6_INDEX, - #endif - #ifdef BSP_USING_LPUART7 - LPUART7_INDEX, - #endif - #ifdef BSP_USING_LPUART8 - LPUART8_INDEX, - #endif - #ifdef BSP_USING_LPUART9 - LPUART9_INDEX, - #endif - #ifdef BSP_USING_LPUART10 - LPUART10_INDEX, - #endif - #ifdef BSP_USING_LPUART11 - LPUART11_INDEX, - #endif - #ifdef BSP_USING_LPUART12 - LPUART12_INDEX, - #endif - }; +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif +enum +{ +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +#ifdef BSP_USING_LPUART2 + LPUART2_INDEX, +#endif +#ifdef BSP_USING_LPUART3 + LPUART3_INDEX, +#endif +#ifdef BSP_USING_LPUART4 + LPUART4_INDEX, +#endif +#ifdef BSP_USING_LPUART5 + LPUART5_INDEX, +#endif +#ifdef BSP_USING_LPUART6 + LPUART6_INDEX, +#endif +#ifdef BSP_USING_LPUART7 + LPUART7_INDEX, +#endif +#ifdef BSP_USING_LPUART8 + LPUART8_INDEX, +#endif +#ifdef BSP_USING_LPUART9 + LPUART9_INDEX, +#endif +#ifdef BSP_USING_LPUART10 + LPUART10_INDEX, +#endif +#ifdef BSP_USING_LPUART11 + LPUART11_INDEX, +#endif +#ifdef BSP_USING_LPUART12 + LPUART12_INDEX, +#endif +}; #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) struct dma_rx_config { @@ -99,8 +99,7 @@ struct imxrt_uart struct rt_serial_device serial; }; -static struct imxrt_uart uarts[] = -{ +static struct imxrt_uart uarts[] = { #ifdef BSP_USING_LPUART1 { .name = "uart1", @@ -250,133 +249,133 @@ static struct imxrt_uart uarts[] = static void uart_get_dma_config(void) { #ifdef BSP_LPUART1_RX_USING_DMA - static struct dma_rx_config uart1_dma_rx = {.request = kDmaRequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart1_dma_rx = { .request = kDmaRequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART1_INDEX].dma_rx = &uart1_dma_rx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART1_TX_USING_DMA - static struct dma_tx_config uart1_dma_tx = {.request = kDmaRequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL}; + static struct dma_tx_config uart1_dma_tx = { .request = kDmaRequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL }; uarts[LPUART1_INDEX].dma_tx = &uart1_dma_tx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART2_RX_USING_DMA - static struct dma_rx_config uart2_dma_rx = {.request = kDmaRequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart2_dma_rx = { .request = kDmaRequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART2_INDEX].dma_rx = &uart2_dma_rx; uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART2_TX_USING_DMA - static struct dma_tx_config uart2_dma_tx = {.request = kDmaRequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL}; + static struct dma_tx_config uart2_dma_tx = { .request = kDmaRequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL }; uarts[LPUART2_INDEX].dma_tx = &uart2_dma_tx; uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART3_RX_USING_DMA - static struct dma_rx_config uart3_dma_rx = {.request = kDmaRequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart3_dma_rx = { .request = kDmaRequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART3_INDEX].dma_rx = &uart3_dma_rx; uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART3_TX_USING_DMA - static struct dma_tx_config uart3_dma_tx = {.request = kDmaRequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL}; + static struct dma_tx_config uart3_dma_tx = { .request = kDmaRequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL }; uarts[LPUART3_INDEX].dma_tx = &uart3_dma_tx; uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART4_RX_USING_DMA - static struct dma_rx_config uart4_dma_rx = {.request = kDmaRequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart4_dma_rx = { .request = kDmaRequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART4_INDEX].dma_rx = &uart4_dma_rx; uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART4_TX_USING_DMA - static struct dma_tx_config uart4_dma_tx = {.request = kDmaRequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL}; + static struct dma_tx_config uart4_dma_tx = { .request = kDmaRequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL }; uarts[LPUART4_INDEX].dma_tx = &uart4_dma_tx; uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART5_RX_USING_DMA - static struct dma_rx_config uart5_dma_rx = {.request = kDmaRequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart5_dma_rx = { .request = kDmaRequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART5_INDEX].dma_rx = &uart5_dma_rx; uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART5_TX_USING_DMA - static struct dma_tx_config uart5_dma_tx = {.request = kDmaRequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL}; + static struct dma_tx_config uart5_dma_tx = { .request = kDmaRequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL }; uarts[LPUART5_INDEX].dma_tx = &uart5_dma_tx; uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART6_RX_USING_DMA - static struct dma_rx_config uart6_dma_rx = {.request = kDmaRequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart6_dma_rx = { .request = kDmaRequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART6_INDEX].dma_rx = &uart6_dma_rx; uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART6_TX_USING_DMA - static struct dma_tx_config uart6_dma_tx = {.request = kDmaRequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL}; + static struct dma_tx_config uart6_dma_tx = { .request = kDmaRequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL }; uarts[LPUART6_INDEX].dma_tx = &uart6_dma_tx; uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART7_RX_USING_DMA - static struct dma_rx_config uart7_dma_rx = {.request = kDmaRequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart7_dma_rx = { .request = kDmaRequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART7_INDEX].dma_rx = &uart7_dma_rx; uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART7_TX_USING_DMA - static struct dma_tx_config uart7_dma_tx = {.request = kDmaRequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL}; + static struct dma_tx_config uart7_dma_tx = { .request = kDmaRequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL }; uarts[LPUART7_INDEX].dma_tx = &uart7_dma_tx; uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART8_RX_USING_DMA - static struct dma_rx_config uart8_dma_rx = {.request = kDmaRequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart8_dma_rx = { .request = kDmaRequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART8_INDEX].dma_rx = &uart8_dma_rx; uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART8_TX_USING_DMA - static struct dma_tx_config uart8_dma_tx = {.request = kDmaRequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL}; + static struct dma_tx_config uart8_dma_tx = { .request = kDmaRequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL }; uarts[LPUART8_INDEX].dma_tx = &uart8_dma_tx; uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART9_RX_USING_DMA - static struct dma_rx_config uart9_dma_rx = {.request = kDmaRequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart9_dma_rx = { .request = kDmaRequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART9_INDEX].dma_rx = &uart9_dma_rx; uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART9_TX_USING_DMA - static struct dma_tx_config uart9_dma_tx = {.request = kDmaRequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL}; + static struct dma_tx_config uart9_dma_tx = { .request = kDmaRequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL }; uarts[LPUART9_INDEX].dma_tx = &uart9_dma_tx; uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART10_RX_USING_DMA - static struct dma_rx_config uart10_dma_rx = {.request = kDmaRequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart10_dma_rx = { .request = kDmaRequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx; uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART10_TX_USING_DMA - static struct dma_tx_config uart10_dma_tx = {.request = kDmaRequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL}; + static struct dma_tx_config uart10_dma_tx = { .request = kDmaRequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL }; uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx; uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART11_RX_USING_DMA - static struct dma_rx_config uart11_dma_rx = {.request = kDmaRequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart11_dma_rx = { .request = kDmaRequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART11_INDEX].dma_rx = &uart11_dma_rx; uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART11_TX_USING_DMA - static struct dma_tx_config uart11_dma_tx = {.request = kDmaRequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL}; + static struct dma_tx_config uart11_dma_tx = { .request = kDmaRequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL }; uarts[LPUART11_INDEX].dma_tx = &uart11_dma_tx; uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART12_RX_USING_DMA - static struct dma_rx_config uart12_dma_rx = {.request = kDmaRequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart12_dma_rx = { .request = kDmaRequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0 }; uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx; uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART12_TX_USING_DMA - static struct dma_tx_config uart12_dma_tx = {.request = kDmaRequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL}; + static struct dma_tx_config uart12_dma_tx = { .request = kDmaRequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL }; uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx; uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif @@ -490,59 +489,59 @@ void LPUART8_IRQHandler(void) rt_interrupt_leave(); } - #endif /* BSP_USING_LPUART8 */ +#endif /* BSP_USING_LPUART8 */ - #if defined(BSP_USING_LPUART9) +#if defined(BSP_USING_LPUART9) - void LPUART9_IRQHandler(void) - { - rt_interrupt_enter(); +void LPUART9_IRQHandler(void) +{ + rt_interrupt_enter(); - uart_isr(&uarts[LPUART9_INDEX]); + uart_isr(&uarts[LPUART9_INDEX]); - rt_interrupt_leave(); - } + rt_interrupt_leave(); +} - #endif /* BSP_USING_LPUART9 */ +#endif /* BSP_USING_LPUART9 */ - #if defined(BSP_USING_LPUART10) +#if defined(BSP_USING_LPUART10) - void LPUART10_IRQHandler(void) - { - rt_interrupt_enter(); +void LPUART10_IRQHandler(void) +{ + rt_interrupt_enter(); - uart_isr(&uarts[LPUART10_INDEX]); + uart_isr(&uarts[LPUART10_INDEX]); - rt_interrupt_leave(); - } + rt_interrupt_leave(); +} - #endif /* BSP_USING_LPUART10 */ +#endif /* BSP_USING_LPUART10 */ - #if defined(BSP_USING_LPUART11) +#if defined(BSP_USING_LPUART11) - void LPUART11_IRQHandler(void) - { - rt_interrupt_enter(); +void LPUART11_IRQHandler(void) +{ + rt_interrupt_enter(); - uart_isr(&uarts[LPUART11_INDEX]); + uart_isr(&uarts[LPUART11_INDEX]); - rt_interrupt_leave(); - } + rt_interrupt_leave(); +} - #endif /* BSP_USING_LPUART11 */ +#endif /* BSP_USING_LPUART11 */ - #if defined(BSP_USING_LPUART12) +#if defined(BSP_USING_LPUART12) - void LPUART12_IRQHandler(void) - { - rt_interrupt_enter(); +void LPUART12_IRQHandler(void) +{ + rt_interrupt_enter(); - uart_isr(&uarts[LPUART12_INDEX]); + uart_isr(&uarts[LPUART12_INDEX]); - rt_interrupt_leave(); - } + rt_interrupt_leave(); +} - #endif /* BSP_USING_LPUART12 */ +#endif /* BSP_USING_LPUART12 */ static void uart_isr(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); @@ -609,7 +608,7 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer if ((EDMA_GetChannelStatusFlags(DMA0, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U) { /* clear full interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_DoneFlag); + EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel, kEDMA_DoneFlag); recv_len = uart->serial.config.bufsz - uart->dma_rx->last_index; uart->dma_rx->last_index = 0; @@ -617,7 +616,7 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer else { /* clear half interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_InterruptFlag); + EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel, kEDMA_InterruptFlag); total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(DMA0, uart->dma_rx->channel); if (total_index > uart->dma_rx->last_index) @@ -650,27 +649,27 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } } - static void imxrt_dma_rx_config(struct imxrt_uart *uart) - { - RT_ASSERT(uart != RT_NULL); +static void imxrt_dma_rx_config(struct imxrt_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); - edma_transfer_config_t xferConfig; - struct rt_serial_rx_fifo *rx_fifo; + edma_transfer_config_t xferConfig; + struct rt_serial_rx_fifo *rx_fifo; - #ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); - #else +#ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); +#else /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); - #endif - - EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); - EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); + EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); +#endif + + EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); + EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); - rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; + rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; - EDMA_PrepareTransfer(&xferConfig, + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(uart->uart_base), sizeof(uint8_t), rx_fifo->buffer, @@ -679,123 +678,122 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t uart->serial.config.bufsz, kEDMA_PeripheralToMemory); - EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); - EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); - EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); + EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); + EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); /* complement to adjust final destination address */ - uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); - EDMA_StartTransfer(&uart->dma_rx->edma); - LPUART_EnableRxDMA(uart->uart_base, true); + uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); + EDMA_StartTransfer(&uart->dma_rx->edma); + LPUART_EnableRxDMA(uart->uart_base, true); - LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); - NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); - EnableIRQ(uart->irqn); + LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); - LOG_D("%s dma rx config done\n", uart->name); - } + LOG_D("%s dma rx config done\n", uart->name); +} - static void imxrt_dma_tx_config(struct imxrt_uart *uart) - { - RT_ASSERT(uart != RT_NULL); +static void imxrt_dma_tx_config(struct imxrt_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); - #ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); - #else +#ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); +#else /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); - #endif - - EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); - - LPUART_TransferCreateHandleEDMA(uart->uart_base, - &uart->dma_tx->uart_edma, - edma_tx_callback, - uart, - &uart->dma_tx->edma, - RT_NULL); - - LOG_D("%s dma tx config done\n", uart->name); - } -#endif - uint32_t GetUartSrcFreq(LPUART_Type *uart_base) - { - uint32_t freq; - #if defined(SOC_IMXRT1170_SERIES) - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); - break; - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); - break; - } - #elif defined(SOC_IMXRT1180_SERIES) + EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); +#endif + + EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); + + LPUART_TransferCreateHandleEDMA(uart->uart_base, + &uart->dma_tx->uart_edma, + edma_tx_callback, + uart, + &uart->dma_tx->edma, + RT_NULL); + + LOG_D("%s dma tx config done\n", uart->name); +} +#endif +uint32_t GetUartSrcFreq(LPUART_Type *uart_base) +{ + uint32_t freq; +#if defined(SOC_IMXRT1170_SERIES) + uint32_t base = (uint32_t)uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); + break; + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); + break; + } +#elif defined(SOC_IMXRT1180_SERIES) /* RT1180 uses different clock root architecture */ - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - case LPUART2_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - case LPUART3_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); - break; - case LPUART4_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); - break; - case LPUART5_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); - break; - case LPUART6_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); - break; - case LPUART7_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); - break; - case LPUART8_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); - break; - case LPUART9_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); - break; - case LPUART10_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); - break; - case LPUART11_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); - break; - - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - } - #else + uint32_t base = (uint32_t)uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART2_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART3_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART4_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART5_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART6_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART7_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART8_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART9_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART10_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART11_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + } +#else /* To make it simple, we assume default PLL and divider settings, and the only variable from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - #endif - return freq; - - } + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } +#endif + return freq; +} static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct imxrt_uart *uart; @@ -900,7 +898,8 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch) uart = rt_container_of(serial, struct imxrt_uart, serial); LPUART_WriteByte(uart->uart_base, ch); - while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); + while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)) + ; return 1; } @@ -949,8 +948,7 @@ rt_size_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_ } #endif -static const struct rt_uart_ops imxrt_uart_ops = -{ +static const struct rt_uart_ops imxrt_uart_ops = { imxrt_configure, imxrt_control, imxrt_putc, @@ -975,7 +973,7 @@ int rt_hw_uart_init(void) for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { - uarts[i].serial.ops = &imxrt_uart_ops; + uarts[i].serial.ops = &imxrt_uart_ops; uarts[i].serial.config = config; ret = rt_hw_serial_register(&uarts[i].serial, uarts[i].name, flag | uarts[i].dma_flag, NULL); From 6381e976da1d9b26befe715c33837f7eecefaee0 Mon Sep 17 00:00:00 2001 From: nxp-ran Date: Mon, 10 Aug 2026 14:05:00 +0800 Subject: [PATCH 31/31] Reformat code according to coding standards. --- bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index cc4106a448e0..eab245e79c99 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -899,8 +899,9 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch) LPUART_WriteByte(uart->uart_base, ch); while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)) - ; - + { + /* wait until transmit data register is empty */ + } return 1; }