diff --git a/mcu/attiny-hal/src/adc.rs b/mcu/attiny-hal/src/adc.rs deleted file mode 100644 index 0856312086..0000000000 --- a/mcu/attiny-hal/src/adc.rs +++ /dev/null @@ -1,209 +0,0 @@ -#![allow(non_camel_case_types)] -//! Analog-to-Digital Converter -//! -//! # Example -//! -//! For full source code, please refer to the ATmega ADC example: -//! [`atmega2560-adc.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-adc.rs) -//! -//! ``` -//! let dp = attiny_hal::Peripherals::take().unwrap(); -//! let pins = attiny_hal::pins!(dp); -//! -//! let mut adc = Adc::new(dp.ADC, Default::default()); -//! -//! let channels: [attiny_hal::adc::Channel; 4] = [ -//! pins.pa0.into_analog_input(&mut adc).into_channel(), -//! pins.pa1.into_analog_input(&mut adc).into_channel(), -//! pins.pa2.into_analog_input(&mut adc).into_channel(), -//! pins.pa3.into_analog_input(&mut adc).into_channel(), -//! ]; -//! -//! for (index, channel) in channels.iter().enumerate() { -//! let value = adc.read_blocking(channel); -//! ufmt::uwrite!(&mut serial, "CH{}: {} ", index, value).unwrap(); -//! } -//! ``` - -use crate::port; -pub use avr_hal_generic::adc::{AdcChannel, AdcOps, ClockDivider}; - -/// Select the voltage reference for the ADC peripheral -/// -/// The internal voltage reference options may not be used if an external reference voltage is -/// being applied to the AREF pin. -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[repr(u8)] -pub enum ReferenceVoltage { - /// Voltage applied to AREF pin. - #[cfg(any(feature = "attiny85", feature = "attiny167",))] - Aref, - /// Default reference voltage (default). - AVcc, - /// Internal 1.1V reference. - Internal1_1, - /// Internal 2.56V reference. - #[cfg(any(feature = "attiny85", feature = "attiny167",))] - Internal2_56, -} - -impl Default for ReferenceVoltage { - fn default() -> Self { - Self::AVcc - } -} - -/// Configuration for the ADC peripheral. -#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)] -pub struct AdcSettings { - pub clock_divider: ClockDivider, - pub ref_voltage: ReferenceVoltage, -} - -/// Check the [`avr_hal_generic::adc::Adc`] documentation. -pub type Adc = avr_hal_generic::adc::Adc; - -/// Check the [`avr_hal_generic::adc::Channel`] documentation. -pub type Channel = avr_hal_generic::adc::Channel; - -/// Additional channels -/// -/// Some channels are not directly connected to pins. This module provides types which can be used -/// to access them. -/// -/// # Example -/// ``` -/// let dp = attiny_hal::Peripherals::take().unwrap(); -/// let mut adc = attiny_hal::Adc::new(dp.ADC, Default::default()); -/// -/// let value = adc.read_blocking(&channel::Vbg); -/// ``` -pub mod channel { - #[cfg(feature = "attiny167")] - pub struct AVcc_4; - pub struct Vbg; - pub struct Gnd; - pub struct Temperature; -} - -fn apply_clock(peripheral: &crate::pac::ADC, settings: AdcSettings) { - peripheral.adcsra.write(|w| { - w.aden().set_bit(); - match settings.clock_divider { - ClockDivider::Factor2 => w.adps().prescaler_2(), - ClockDivider::Factor4 => w.adps().prescaler_4(), - ClockDivider::Factor8 => w.adps().prescaler_8(), - ClockDivider::Factor16 => w.adps().prescaler_16(), - ClockDivider::Factor32 => w.adps().prescaler_32(), - ClockDivider::Factor64 => w.adps().prescaler_64(), - ClockDivider::Factor128 => w.adps().prescaler_128(), - } - }); -} - -#[cfg(feature = "attiny85")] -avr_hal_generic::impl_adc! { - hal: crate::Attiny, - peripheral: crate::pac::ADC, - settings: AdcSettings, - apply_settings: |peripheral, settings| { - apply_clock(peripheral, settings); - peripheral.admux.write(|w| match settings.ref_voltage { - ReferenceVoltage::Aref => w.refs().aref(), - ReferenceVoltage::AVcc => w.refs().vcc(), - ReferenceVoltage::Internal1_1 => w.refs().internal().refs2().clear_bit(), - ReferenceVoltage::Internal2_56 => w.refs().internal().refs2().set_bit(), - }); - }, - channel_id: crate::pac::adc::admux::MUX_A, - set_channel: |peripheral, id| { - peripheral.admux.modify(|_, w| w.mux().variant(id)); - }, - pins: { - port::PB5: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), - port::PB2: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), - port::PB4: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), - port::PB3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), - }, - channels: { - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, - }, -} - -#[cfg(feature = "attiny88")] -avr_hal_generic::impl_adc! { - hal: crate::Attiny, - peripheral: crate::pac::ADC, - settings: AdcSettings, - apply_settings: |peripheral, settings| { - apply_clock(peripheral, settings); - peripheral.admux.write(|w| match settings.ref_voltage { - ReferenceVoltage::AVcc => w.refs0().avcc(), - ReferenceVoltage::Internal1_1 => w.refs0().internal(), - }); - }, - channel_id: crate::pac::adc::admux::MUX_A, - set_channel: |peripheral, id| { - peripheral.admux.modify(|_, w| w.mux().variant(id)); - }, - pins: { - port::PC0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), - port::PC1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), - port::PC2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), - port::PC3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), - port::PC4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), - port::PC5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), - port::PA0: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), - port::PA1: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), - }, - channels: { - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, - }, -} - -#[cfg(feature = "attiny167")] -avr_hal_generic::impl_adc! { - hal: crate::Attiny, - peripheral: crate::pac::ADC, - settings: AdcSettings, - apply_settings: |peripheral, settings| { - apply_clock(peripheral, settings); - peripheral.amiscr.write(|w| match settings.ref_voltage { - ReferenceVoltage::Aref => w.arefen().set_bit(), - _ => w.arefen().clear_bit(), - }); - peripheral.admux.write(|w| match settings.ref_voltage { - ReferenceVoltage::Aref => w.refs().avcc(), - ReferenceVoltage::AVcc => w.refs().avcc(), - ReferenceVoltage::Internal1_1 => w.refs().internal_11(), - ReferenceVoltage::Internal2_56 => w.refs().internal_256(), - }); - }, - channel_id: crate::pac::adc::admux::MUX_A, - set_channel: |peripheral, id| { - peripheral.admux.modify(|_, w| w.mux().variant(id)); - }, - pins: { - port::PA0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), - port::PA1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), - port::PA2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), - port::PA3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), - port::PA4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), - port::PA5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), - port::PA6: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), - port::PA7: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), - port::PB5: (crate::pac::adc::admux::MUX_A::ADC8, didr1::adc8d), - port::PB6: (crate::pac::adc::admux::MUX_A::ADC9, didr1::adc9d), - port::PB7: (crate::pac::adc::admux::MUX_A::ADC10, didr1::adc10d), - }, - channels: { - channel::AVcc_4: crate::pac::adc::admux::MUX_A::ADC_AVCC_4, - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, - }, -} diff --git a/mcu/attiny-hal/src/attiny167.rs b/mcu/attiny-hal/src/attiny167.rs new file mode 100644 index 0000000000..49bc48fe18 --- /dev/null +++ b/mcu/attiny-hal/src/attiny167.rs @@ -0,0 +1,132 @@ +pub mod adc { + pub use crate::periphals::adc::*; + + use crate::port; + + avr_hal_generic::impl_adc! { + hal: crate::Attiny, + peripheral: crate::pac::ADC, + settings: AdcSettings, + apply_settings: |peripheral, settings| { + apply_clock(peripheral, settings); + peripheral.amiscr.write(|w| match settings.ref_voltage { + ReferenceVoltage::Aref => w.arefen().set_bit(), + _ => w.arefen().clear_bit(), + }); + peripheral.admux.write(|w| match settings.ref_voltage { + ReferenceVoltage::Aref => w.refs().avcc(), + ReferenceVoltage::AVcc => w.refs().avcc(), + ReferenceVoltage::Internal1_1 => w.refs().internal_11(), + ReferenceVoltage::Internal2_56 => w.refs().internal_256(), + }); + }, + channel_id: crate::pac::adc::admux::MUX_A, + set_channel: |peripheral, id| { + peripheral.admux.modify(|_, w| w.mux().variant(id)); + }, + pins: { + port::PA0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), + port::PA1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), + port::PA2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), + port::PA3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), + port::PA4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), + port::PA5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), + port::PA6: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), + port::PA7: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), + port::PB5: (crate::pac::adc::admux::MUX_A::ADC8, didr1::adc8d), + port::PB6: (crate::pac::adc::admux::MUX_A::ADC9, didr1::adc9d), + port::PB7: (crate::pac::adc::admux::MUX_A::ADC10, didr1::adc10d), + }, + channels: { + channel::AVcc_4: crate::pac::adc::admux::MUX_A::ADC_AVCC_4, + channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, + channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, + channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, + }, + } +} + +pub mod eeprom { + pub use crate::periphals::eeprom::*; + + avr_hal_generic::impl_eeprom_attiny! { + hal: crate::Attiny, + peripheral: crate::pac::EEPROM, + capacity: 512, + addr_width: u16, + set_address: |peripheral, address| { + peripheral.eear.write(|w| w.bits(address)); + }, + } +} + +#[macro_export] +macro_rules! pins { + ($p:expr) => { + $crate::Pins::new($p.PORTA, $p.PORTB) + }; +} + +pub mod port { + pub use crate::periphals::port::*; + + avr_hal_generic::impl_port_traditional! { + enum Ports { + A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7], + B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], + } + } +} + +pub mod simple_pwm { + pub use crate::periphals::simple_pwm::*; + + // Fixme: Implement PWM for ATtiny167. +} + +pub mod spi { + pub use crate::periphals::spi::*; + + use crate::port; + + pub type Spi = avr_hal_generic::spi::Spi< + crate::Attiny, + crate::pac::SPI, + port::PA5, + port::PA4, + port::PA2, + port::PA6, + >; + + avr_hal_generic::impl_spi! { + hal: crate::Attiny, + peripheral: crate::pac::SPI, + sclk: port::PA5, + mosi: port::PA4, + miso: port::PA2, + cs: port::PA6, + } +} + +pub mod wdt { + pub use crate::periphals::wdt::*; + + avr_hal_generic::impl_wdt! { + hal: crate::Attiny, + peripheral: crate::pac::WDT, + mcusr: crate::pac::cpu::MCUSR, + wdtcsr_name: wdtcr, + timeout: |to, w| match to { + Timeout::Ms16 => w.wdpl().cycles_2k_512k(), + Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), + Timeout::Ms64 => w.wdpl().cycles_8k(), + Timeout::Ms125 => w.wdpl().cycles_16k(), + Timeout::Ms250 => w.wdpl().cycles_32k(), + Timeout::Ms500 => w.wdpl().cycles_64k(), + Timeout::Ms1000 => w.wdpl().cycles_128k(), + Timeout::Ms2000 => w.wdpl().cycles_256k(), + Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), + Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), + }, + } +} diff --git a/mcu/attiny-hal/src/attiny2313.rs b/mcu/attiny-hal/src/attiny2313.rs new file mode 100644 index 0000000000..020b8d3b56 --- /dev/null +++ b/mcu/attiny-hal/src/attiny2313.rs @@ -0,0 +1,67 @@ +pub mod eeprom { + pub use crate::periphals::eeprom::*; + + avr_hal_generic::impl_eeprom_attiny! { + hal: crate::Attiny, + peripheral: crate::pac::EEPROM, + capacity: 128, + addr_width: u8, + set_address: |peripheral, address| { + peripheral.eear.write(|w| w.bits(address)); + }, + } +} + +#[macro_export] +macro_rules! pins { + ($p:expr) => { + $crate::Pins::new($p.PORTA, $p.PORTB, $p.PORTD) + }; +} + +pub mod port { + pub use crate::periphals::port::*; + + avr_hal_generic::impl_port_traditional! { + enum Ports { + A: crate::pac::PORTA = [0, 1, 2], + B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], + D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6], + } + } +} + +pub mod simple_pwm { + pub use crate::periphals::simple_pwm::*; + + // Fixme: Implement PWM for ATtiny2313. +} + +pub mod spi { + pub use crate::periphals::spi::*; + + // Fixme: Implement SPI for ATtiny2313. +} + +pub mod wdt { + pub use crate::periphals::wdt::*; + + avr_hal_generic::impl_wdt! { + hal: crate::Attiny, + peripheral: crate::pac::WDT, + mcusr: crate::pac::cpu::MCUSR, + wdtcsr_name: wdtcr, + timeout: |to, w| match to { + Timeout::Ms16 => w.wdpl().cycles_2k_512k(), + Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), + Timeout::Ms64 => w.wdpl().cycles_8k(), + Timeout::Ms125 => w.wdpl().cycles_16k(), + Timeout::Ms250 => w.wdpl().cycles_32k(), + Timeout::Ms500 => w.wdpl().cycles_64k(), + Timeout::Ms1000 => w.wdpl().cycles_128k(), + Timeout::Ms2000 => w.wdpl().cycles_256k(), + Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), + Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), + }, + } +} diff --git a/mcu/attiny-hal/src/attiny84.rs b/mcu/attiny-hal/src/attiny84.rs new file mode 100644 index 0000000000..8470d1b9c2 --- /dev/null +++ b/mcu/attiny-hal/src/attiny84.rs @@ -0,0 +1,138 @@ +pub mod adc { + pub use crate::periphals::adc::*; + + // Fixme: Implement ADC for ATtiny84. +} + +pub mod eeprom { + pub use crate::periphals::eeprom::*; + + // Fixme: Implement EEPROM for ATtiny84. +} + +#[macro_export] +macro_rules! pins { + ($p:expr) => { + $crate::Pins::new($p.PORTA, $p.PORTB) + }; +} + +pub mod port { + pub use crate::periphals::port::*; + + avr_hal_generic::impl_port_traditional! { + enum Ports { + A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7], + B: crate::pac::PORTB = [0, 1, 2, 3], + } + } +} + +pub mod simple_pwm { + pub use crate::periphals::simple_pwm::*; + + use crate::port::*; + + avr_hal_generic::impl_simple_pwm! { + /// Use `TC0` for PWM (pins `PB2`, `PA7`) + pub struct Timer0Pwm { + timer: crate::pac::TC0, + init: |tim, prescaler| { + tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast()); + tim.tccr0b.modify(|_r, w| match prescaler { + Prescaler::Direct => w.cs0().direct(), + Prescaler::Prescale8 => w.cs0().prescale_8(), + Prescaler::Prescale64 => w.cs0().prescale_64(), + Prescaler::Prescale256 => w.cs0().prescale_256(), + Prescaler::Prescale1024 => w.cs0().prescale_1024(), + }); + }, + pins: { + PB2: { + ocr: ocr0a, + into_pwm: |tim| if enable { + tim.tccr0a.modify(|_r, w| w.com0a().match_clear()); + } else { + tim.tccr0a.modify(|_r, w| w.com0a().disconnected()); + }, + }, + + PA7: { + ocr: ocr0b, + into_pwm: |tim| if enable { + tim.tccr0a.modify(|_r, w| w.com0b().match_clear()); + } else { + tim.tccr0a.modify(|_r, w| w.com0b().disconnected()); + }, + }, + }, + } + } + + avr_hal_generic::impl_simple_pwm! { + /// Use `TC1` for PWM (pins `PA6`, 'PA5') + pub struct Timer1Pwm { + timer: crate::pac::TC1, + init: |tim, prescaler| { + tim.tccr1a.modify(|_, w| w.wgm1().bits(0b01)); + tim.tccr1b.modify(|_, w| w.wgm1().bits(0b01)); + + tim.tccr1b.modify(|_r, w| match prescaler { + Prescaler::Direct => w.cs1().direct(), + Prescaler::Prescale8 => w.cs1().prescale_8(), + Prescaler::Prescale64 => w.cs1().prescale_64(), + Prescaler::Prescale256 => w.cs1().prescale_256(), + Prescaler::Prescale1024 => w.cs1().prescale_1024(), + }); + }, + pins: { + PA6: { + ocr: ocr1a, + into_pwm: |tim| if enable { + tim.tccr1a.modify(|_, w| w.com1a().bits(0b10)); + } else { + tim.tccr1a.modify(|_, w| w.com1a().disconnected()); + }, + }, + + PA5: { + ocr: ocr1b, + into_pwm: |tim| if enable { + tim.tccr1a.modify(|_, w| w.com1b().bits(0b10)); + } else { + tim.tccr1a.modify(|_, w| w.com1b().disconnected()); + }, + }, + }, + } + } +} + +pub mod spi { + pub use crate::periphals::spi::*; + + // Fixme: Implement SPI for ATtiny84. +} + +pub mod wdt { + pub use crate::periphals::wdt::*; + + avr_hal_generic::impl_wdt! { + hal: crate::Attiny, + peripheral: crate::pac::WDT, + mcusr: crate::pac::cpu::MCUSR, + wdtcsr_name: wdtcsr, + timeout: |to, w| match to { + Timeout::Ms16 => w.wdpl().cycles_2k_512k(), + Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), + Timeout::Ms64 => w.wdpl().cycles_8k(), + Timeout::Ms125 => w.wdpl().cycles_16k(), + Timeout::Ms250 => w.wdpl().cycles_32k(), + Timeout::Ms500 => w.wdpl().cycles_64k(), + Timeout::Ms1000 => w.wdpl().cycles_128k(), + Timeout::Ms2000 => w.wdpl().cycles_256k(), + Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), + Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), + }, + } +} diff --git a/mcu/attiny-hal/src/attiny85.rs b/mcu/attiny-hal/src/attiny85.rs new file mode 100644 index 0000000000..bed6072125 --- /dev/null +++ b/mcu/attiny-hal/src/attiny85.rs @@ -0,0 +1,186 @@ +pub mod adc { + pub use crate::periphals::adc::*; + use crate::port; + + avr_hal_generic::impl_adc! { + hal: crate::Attiny, + peripheral: crate::pac::ADC, + settings: AdcSettings, + apply_settings: |peripheral, settings| { + apply_clock(peripheral, settings); + peripheral.admux.write(|w| match settings.ref_voltage { + ReferenceVoltage::Aref => w.refs().aref(), + ReferenceVoltage::AVcc => w.refs().vcc(), + ReferenceVoltage::Internal1_1 => w.refs().internal().refs2().clear_bit(), + ReferenceVoltage::Internal2_56 => w.refs().internal().refs2().set_bit(), + }); + }, + channel_id: crate::pac::adc::admux::MUX_A, + set_channel: |peripheral, id| { + peripheral.admux.modify(|_, w| w.mux().variant(id)); + }, + pins: { + port::PB5: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), + port::PB2: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), + port::PB4: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), + port::PB3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), + }, + channels: { + channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, + channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, + channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, + }, + } +} + +pub mod eeprom { + pub use crate::periphals::eeprom::*; + + avr_hal_generic::impl_eeprom_attiny! { + hal: crate::Attiny, + peripheral: crate::pac::EEPROM, + capacity: 512, + addr_width: u16, + set_address: |peripheral, address| { + peripheral.eear.write(|w| w.bits(address)); + }, + } +} + +#[macro_export] +macro_rules! pins { + ($p:expr) => { + $crate::Pins::new($p.PORTB) + }; +} + +pub mod port { + pub use crate::periphals::port::*; + + avr_hal_generic::impl_port_traditional! { + enum Ports { + B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5], + } + } +} + +pub mod simple_pwm { + pub use crate::periphals::simple_pwm::*; + + use crate::port::*; + + avr_hal_generic::impl_simple_pwm! { + /// Use `TC0` for PWM (pins `PB0`, `PB1`) + /// + /// # Example + /// ``` + /// let mut timer0 = Timer0Pwm::new(dp.TC0, Prescaler::Prescale64); + /// + /// let mut d0 = pins.d0.into_output().into_pwm(&mut timer0); + /// let mut d1 = pins.d1.into_output().into_pwm(&mut timer0); + /// + /// d0.set_duty(128); + /// d0.enable(); + /// ``` + pub struct Timer0Pwm { + timer: crate::pac::TC0, + init: |tim, prescaler| { + tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast()); + tim.tccr0b.modify(|_r, w| match prescaler { + Prescaler::Direct => w.cs0().direct(), + Prescaler::Prescale8 => w.cs0().prescale_8(), + Prescaler::Prescale64 => w.cs0().prescale_64(), + Prescaler::Prescale256 => w.cs0().prescale_256(), + Prescaler::Prescale1024 => w.cs0().prescale_1024(), + }); + }, + pins: { + PB0: { + ocr: ocr0a, + into_pwm: |tim| if enable { + tim.tccr0a.modify(|_r, w| w.com0a().match_clear()); + } else { + tim.tccr0a.modify(|_r, w| w.com0a().disconnected()); + }, + }, + + PB1: { + ocr: ocr0b, + into_pwm: |tim| if enable { + tim.tccr0a.modify(|_r, w| w.com0b().match_clear()); + } else { + tim.tccr0a.modify(|_r, w| w.com0b().disconnected()); + }, + }, + }, + } + } + + #[cfg(feature = "attiny85")] + avr_hal_generic::impl_simple_pwm! { + /// Use `TC1` for PWM (pins `PB4`) + /// + /// # Example + /// ``` + /// let mut timer1 = Timer1Pwm::new(dp.TC1, Prescaler::Prescale64); + /// + /// let mut d4 = pins.d4.into_output().into_pwm(&mut timer1); + /// + /// d4.set_duty(128); + /// d4.enable(); + /// ``` + pub struct Timer1Pwm { + timer: crate::pac::TC1, + init: |tim, prescaler| { + tim.gtccr.modify(|_, w| w.pwm1b().bit(true)); + + tim.tccr1.modify(|_r, w| match prescaler { + Prescaler::Direct => w.cs1().direct(), + Prescaler::Prescale8 => w.cs1().prescale_8(), + Prescaler::Prescale64 => w.cs1().prescale_64(), + Prescaler::Prescale256 => w.cs1().prescale_256(), + Prescaler::Prescale1024 => w.cs1().prescale_1024(), + }); + }, + pins: { + PB4: { + ocr: ocr1b, + into_pwm: |tim| if enable { + tim.gtccr.modify(|_, w| w.com1b().bits(0b10)); + } else { + tim.gtccr.modify(|_, w| w.com1b().disconnected()); + }, + }, + }, + } + } +} + +pub mod spi { + pub use crate::periphals::spi::*; + + // Fixme: Implement SPI for ATtiny85. +} + +pub mod wdt { + pub use crate::periphals::wdt::*; + + avr_hal_generic::impl_wdt! { + hal: crate::Attiny, + peripheral: crate::pac::WDT, + mcusr: crate::pac::cpu::MCUSR, + wdtcsr_name: wdtcr, + timeout: |to, w| match to { + Timeout::Ms16 => w.wdpl().cycles_2k_512k(), + Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), + Timeout::Ms64 => w.wdpl().cycles_8k(), + Timeout::Ms125 => w.wdpl().cycles_16k(), + Timeout::Ms250 => w.wdpl().cycles_32k(), + Timeout::Ms500 => w.wdpl().cycles_64k(), + Timeout::Ms1000 => w.wdpl().cycles_128k(), + Timeout::Ms2000 => w.wdpl().cycles_256k(), + Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), + Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), + }, + } +} diff --git a/mcu/attiny-hal/src/attiny88.rs b/mcu/attiny-hal/src/attiny88.rs new file mode 100644 index 0000000000..c4769a1c2f --- /dev/null +++ b/mcu/attiny-hal/src/attiny88.rs @@ -0,0 +1,173 @@ +pub mod adc { + pub use crate::periphals::adc::*; + + use crate::port; + + avr_hal_generic::impl_adc! { + hal: crate::Attiny, + peripheral: crate::pac::ADC, + settings: AdcSettings, + apply_settings: |peripheral, settings| { + apply_clock(peripheral, settings); + peripheral.admux.write(|w| match settings.ref_voltage { + ReferenceVoltage::AVcc => w.refs0().avcc(), + ReferenceVoltage::Internal1_1 => w.refs0().internal(), + }); + }, + channel_id: crate::pac::adc::admux::MUX_A, + set_channel: |peripheral, id| { + peripheral.admux.modify(|_, w| w.mux().variant(id)); + }, + pins: { + port::PC0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), + port::PC1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), + port::PC2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), + port::PC3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), + port::PC4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), + port::PC5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), + port::PA0: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), + port::PA1: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), + }, + channels: { + channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, + channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, + channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, + }, + } +} + +pub mod eeprom { + pub use crate::periphals::eeprom::*; + + avr_hal_generic::impl_eeprom_attiny! { + hal: crate::Attiny, + peripheral: crate::pac::EEPROM, + capacity: 64, + addr_width: u8, + set_address: |peripheral, address| { + peripheral.eearl.write(|w| w.bits(address)); + }, + } +} + +#[macro_export] +macro_rules! pins { + ($p:expr) => { + $crate::Pins::new($p.PORTA, $p.PORTB, $p.PORTC, $p.PORTD) + }; +} + +pub mod port { + pub use crate::periphals::port::*; + + avr_hal_generic::impl_port_traditional! { + enum Ports { + A: crate::pac::PORTA = [0, 1, 2, 3], + B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], + C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6, 7], + D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7], + } + } +} + +pub mod simple_pwm { + pub use crate::periphals::simple_pwm::*; + + use crate::port::*; + + avr_hal_generic::impl_simple_pwm! { + /// Use `TC1` for PWM (pins `PB1`, 'PB2') + /// + /// # Example + /// ``` + /// let mut timer1 = Timer1Pwm::new(dp.TC1, Prescaler::Prescale64); + /// + /// let mut d9 = pins.d9.into_output().into_pwm(&mut timer1); + /// let mut d10 = pins.d10.into_output().into_pwm(&mut timer1); + /// + /// d9.set_duty(128); + /// d9.enable(); + /// ``` + pub struct Timer1Pwm { + timer: crate::pac::TC1, + init: |tim, prescaler| { + tim.tccr1a.modify(|_, w| w.wgm1().bits(0b01)); + tim.tccr1b.modify(|_, w| w.wgm1().bits(0b01)); + + tim.tccr1b.modify(|_r, w| match prescaler { + Prescaler::Direct => w.cs1().direct(), + Prescaler::Prescale8 => w.cs1().prescale_8(), + Prescaler::Prescale64 => w.cs1().prescale_64(), + Prescaler::Prescale256 => w.cs1().prescale_256(), + Prescaler::Prescale1024 => w.cs1().prescale_1024(), + }); + }, + pins: { + PB1: { + ocr: ocr1a, + into_pwm: |tim| if enable { + tim.tccr1a.modify(|_, w| w.com1a().bits(0b10)); + } else { + tim.tccr1a.modify(|_, w| w.com1a().disconnected()); + }, + }, + + PB2: { + ocr: ocr1b, + into_pwm: |tim| if enable { + tim.tccr1a.modify(|_, w| w.com1b().bits(0b10)); + } else { + tim.tccr1a.modify(|_, w| w.com1b().disconnected()); + }, + }, + }, + } + } +} + +pub mod spi { + pub use crate::periphals::spi::*; + + use crate::port; + + pub type Spi = avr_hal_generic::spi::Spi< + crate::Attiny, + crate::pac::SPI, + port::PB5, + port::PB3, + port::PB4, + port::PB2, + >; + + avr_hal_generic::impl_spi! { + hal: crate::Attiny, + peripheral: crate::pac::SPI, + sclk: port::PB5, + mosi: port::PB3, + miso: port::PB4, + cs: port::PB2, + } +} + +pub mod wdt { + pub use crate::periphals::wdt::*; + + avr_hal_generic::impl_wdt! { + hal: crate::Attiny, + peripheral: crate::pac::WDT, + mcusr: crate::pac::cpu::MCUSR, + wdtcsr_name: wdtcsr, + timeout: |to, w| match to { + Timeout::Ms16 => w.wdpl().cycles_2k_512k(), + Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), + Timeout::Ms64 => w.wdpl().cycles_8k(), + Timeout::Ms125 => w.wdpl().cycles_16k(), + Timeout::Ms250 => w.wdpl().cycles_32k(), + Timeout::Ms500 => w.wdpl().cycles_64k(), + Timeout::Ms1000 => w.wdpl().cycles_128k(), + Timeout::Ms2000 => w.wdpl().cycles_256k(), + Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), + Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), + }, + } +} diff --git a/mcu/attiny-hal/src/eeprom.rs b/mcu/attiny-hal/src/eeprom.rs deleted file mode 100644 index f325215dfb..0000000000 --- a/mcu/attiny-hal/src/eeprom.rs +++ /dev/null @@ -1,56 +0,0 @@ -//! EEPROM -//! -//! # Example -//! -//! For full source code, please refer to the ATmega EEPROM example: -//! [`atmega2560-eeprom.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-eeprom.rs) -//! -//! ``` -//! const BOOT_COUNT_OFFSET: u16 = 0; -//! -//! let dp = attiny_hal::Peripherals::take().unwrap(); -//! let mut eeprom = Eeprom::new(dp.EEPROM); -//! -//! let mut boot_count = eeprom.read_byte(BOOT_COUNT_OFFSET); -//! boot_count = boot_count.wrapping_add(1); -//! eeprom.write_byte(BOOT_COUNT_OFFSET, boot_count); -//! -//! ufmt::uwriteln!(&mut serial, "Boot count: {}", boot_count).unwrap(); -//! ``` - -pub use avr_hal_generic::eeprom::{EepromOps, OutOfBoundsError}; - -pub type Eeprom = avr_hal_generic::eeprom::Eeprom; - -#[cfg(feature = "attiny2313")] -avr_hal_generic::impl_eeprom_attiny! { - hal: crate::Attiny, - peripheral: crate::pac::EEPROM, - capacity: 128, - addr_width: u8, - set_address: |peripheral, address| { - peripheral.eear.write(|w| w.bits(address)); - }, -} - -#[cfg(any(feature = "attiny167", feature = "attiny85"))] -avr_hal_generic::impl_eeprom_attiny! { - hal: crate::Attiny, - peripheral: crate::pac::EEPROM, - capacity: 512, - addr_width: u16, - set_address: |peripheral, address| { - peripheral.eear.write(|w| w.bits(address)); - }, -} - -#[cfg(feature = "attiny88")] -avr_hal_generic::impl_eeprom_attiny! { - hal: crate::Attiny, - peripheral: crate::pac::EEPROM, - capacity: 64, - addr_width: u8, - set_address: |peripheral, address| { - peripheral.eearl.write(|w| w.bits(address)); - }, -} diff --git a/mcu/attiny-hal/src/lib.rs b/mcu/attiny-hal/src/lib.rs index a8bf1541e0..0cdee2fa7e 100644 --- a/mcu/attiny-hal/src/lib.rs +++ b/mcu/attiny-hal/src/lib.rs @@ -36,22 +36,42 @@ compile_error!( /// #[cfg(feature = "attiny167")] pub use avr_device::attiny167 as pac; +#[cfg(feature = "attiny167")] +pub mod attiny167; +#[cfg(feature = "attiny167")] +pub use crate::attiny167::*; /// Reexport of `attiny2313` from `avr-device` /// #[cfg(feature = "attiny2313")] pub use avr_device::attiny2313 as pac; +#[cfg(feature = "attiny2313")] +pub mod attiny2313; +#[cfg(feature = "attiny2313")] +pub use crate::attiny2313::*; /// Reexport of `attiny84` from `avr-device` /// #[cfg(feature = "attiny84")] pub use avr_device::attiny84 as pac; +#[cfg(feature = "attiny84")] +pub mod attiny84; +#[cfg(feature = "attiny84")] +pub use crate::attiny84::*; /// Reexport of `attiny85` from `avr-device` /// #[cfg(feature = "attiny85")] pub use avr_device::attiny85 as pac; +#[cfg(feature = "attiny85")] +pub mod attiny85; +#[cfg(feature = "attiny85")] +pub use crate::attiny85::*; /// Reexport of `attiny88` from `avr-device` /// #[cfg(feature = "attiny88")] pub use avr_device::attiny88 as pac; +#[cfg(feature = "attiny88")] +pub mod attiny88; +#[cfg(feature = "attiny88")] +pub use crate::attiny88::*; /// See [`avr_device::entry`](https://docs.rs/avr-device/latest/avr_device/attr.entry.html). #[cfg(feature = "rt")] @@ -64,69 +84,23 @@ pub use avr_hal_generic::clock; pub use avr_hal_generic::delay; pub use avr_hal_generic::prelude; +#[cfg(feature = "device-selected")] +pub mod periphals; + // ATtiny2313 does not have ADC and will not compile with this module #[cfg(all(feature = "device-selected", not(feature = "attiny2313")))] -pub mod adc; -#[cfg(all(feature = "device-selected", not(feature = "attiny2313")))] pub use adc::Adc; -#[cfg(feature = "device-selected")] -pub mod port; #[cfg(feature = "device-selected")] pub use port::Pins; -#[cfg(feature = "device-selected")] -pub mod simple_pwm; - -#[cfg(feature = "device-selected")] -pub mod wdt; #[cfg(feature = "device-selected")] pub use wdt::Wdt; -#[cfg(feature = "device-selected")] -pub mod eeprom; #[cfg(feature = "device-selected")] pub use eeprom::Eeprom; -#[cfg(feature = "device-selected")] -pub mod spi; #[cfg(feature = "device-selected")] pub use spi::Spi; pub struct Attiny; - -#[cfg(feature = "attiny84")] -#[macro_export] -macro_rules! pins { - ($p:expr) => { - $crate::Pins::new($p.PORTA, $p.PORTB) - }; -} -#[cfg(feature = "attiny85")] -#[macro_export] -macro_rules! pins { - ($p:expr) => { - $crate::Pins::new($p.PORTB) - }; -} -#[cfg(feature = "attiny88")] -#[macro_export] -macro_rules! pins { - ($p:expr) => { - $crate::Pins::new($p.PORTA, $p.PORTB, $p.PORTC, $p.PORTD) - }; -} -#[cfg(feature = "attiny167")] -#[macro_export] -macro_rules! pins { - ($p:expr) => { - $crate::Pins::new($p.PORTA, $p.PORTB) - }; -} -#[cfg(feature = "attiny2313")] -#[macro_export] -macro_rules! pins { - ($p:expr) => { - $crate::Pins::new($p.PORTA, $p.PORTB, $p.PORTD) - }; -} diff --git a/mcu/attiny-hal/src/periphals/adc.rs b/mcu/attiny-hal/src/periphals/adc.rs new file mode 100644 index 0000000000..fe26195c21 --- /dev/null +++ b/mcu/attiny-hal/src/periphals/adc.rs @@ -0,0 +1,101 @@ +#![allow(non_camel_case_types)] +//! Analog-to-Digital Converter +//! +//! # Example +//! +//! For full source code, please refer to the ATmega ADC example: +//! [`atmega2560-adc.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-adc.rs) +//! +//! ``` +//! let dp = attiny_hal::Peripherals::take().unwrap(); +//! let pins = attiny_hal::pins!(dp); +//! +//! let mut adc = Adc::new(dp.ADC, Default::default()); +//! +//! let channels: [attiny_hal::adc::Channel; 4] = [ +//! pins.pa0.into_analog_input(&mut adc).into_channel(), +//! pins.pa1.into_analog_input(&mut adc).into_channel(), +//! pins.pa2.into_analog_input(&mut adc).into_channel(), +//! pins.pa3.into_analog_input(&mut adc).into_channel(), +//! ]; +//! +//! for (index, channel) in channels.iter().enumerate() { +//! let value = adc.read_blocking(channel); +//! ufmt::uwrite!(&mut serial, "CH{}: {} ", index, value).unwrap(); +//! } +//! ``` + +pub use avr_hal_generic::adc::{AdcChannel, AdcOps, ClockDivider}; + +/// Select the voltage reference for the ADC peripheral +/// +/// The internal voltage reference options may not be used if an external reference voltage is +/// being applied to the AREF pin. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[repr(u8)] +pub enum ReferenceVoltage { + /// Voltage applied to AREF pin. + #[cfg(any(feature = "attiny85", feature = "attiny167",))] + Aref, + /// Default reference voltage (default). + AVcc, + /// Internal 1.1V reference. + Internal1_1, + /// Internal 2.56V reference. + #[cfg(any(feature = "attiny85", feature = "attiny167",))] + Internal2_56, +} + +impl Default for ReferenceVoltage { + fn default() -> Self { + Self::AVcc + } +} + +/// Configuration for the ADC peripheral. +#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)] +pub struct AdcSettings { + pub clock_divider: ClockDivider, + pub ref_voltage: ReferenceVoltage, +} + +/// Check the [`avr_hal_generic::adc::Adc`] documentation. +pub type Adc = avr_hal_generic::adc::Adc; + +/// Check the [`avr_hal_generic::adc::Channel`] documentation. +pub type Channel = avr_hal_generic::adc::Channel; + +/// Additional channels +/// +/// Some channels are not directly connected to pins. This module provides types which can be used +/// to access them. +/// +/// # Example +/// ``` +/// let dp = attiny_hal::Peripherals::take().unwrap(); +/// let mut adc = attiny_hal::Adc::new(dp.ADC, Default::default()); +/// +/// let value = adc.read_blocking(&channel::Vbg); +/// ``` +pub mod channel { + #[cfg(feature = "attiny167")] + pub struct AVcc_4; + pub struct Vbg; + pub struct Gnd; + pub struct Temperature; +} + +pub(crate) fn apply_clock(peripheral: &crate::pac::ADC, settings: AdcSettings) { + peripheral.adcsra.write(|w| { + w.aden().set_bit(); + match settings.clock_divider { + ClockDivider::Factor2 => w.adps().prescaler_2(), + ClockDivider::Factor4 => w.adps().prescaler_4(), + ClockDivider::Factor8 => w.adps().prescaler_8(), + ClockDivider::Factor16 => w.adps().prescaler_16(), + ClockDivider::Factor32 => w.adps().prescaler_32(), + ClockDivider::Factor64 => w.adps().prescaler_64(), + ClockDivider::Factor128 => w.adps().prescaler_128(), + } + }); +} diff --git a/mcu/attiny-hal/src/periphals/eeprom.rs b/mcu/attiny-hal/src/periphals/eeprom.rs new file mode 100644 index 0000000000..c688632292 --- /dev/null +++ b/mcu/attiny-hal/src/periphals/eeprom.rs @@ -0,0 +1,23 @@ +//! EEPROM +//! +//! # Example +//! +//! For full source code, please refer to the ATmega EEPROM example: +//! [`atmega2560-eeprom.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-eeprom.rs) +//! +//! ``` +//! const BOOT_COUNT_OFFSET: u16 = 0; +//! +//! let dp = attiny_hal::Peripherals::take().unwrap(); +//! let mut eeprom = Eeprom::new(dp.EEPROM); +//! +//! let mut boot_count = eeprom.read_byte(BOOT_COUNT_OFFSET); +//! boot_count = boot_count.wrapping_add(1); +//! eeprom.write_byte(BOOT_COUNT_OFFSET, boot_count); +//! +//! ufmt::uwriteln!(&mut serial, "Boot count: {}", boot_count).unwrap(); +//! ``` + +pub use avr_hal_generic::eeprom::{EepromOps, OutOfBoundsError}; + +pub type Eeprom = avr_hal_generic::eeprom::Eeprom; diff --git a/mcu/attiny-hal/src/periphals/mod.rs b/mcu/attiny-hal/src/periphals/mod.rs new file mode 100644 index 0000000000..b2666298a5 --- /dev/null +++ b/mcu/attiny-hal/src/periphals/mod.rs @@ -0,0 +1,8 @@ +// ATtiny2313 does not have ADC and will not compile with this module +#[cfg(not(feature = "attiny2313"))] +pub mod adc; +pub mod eeprom; +pub mod port; +pub mod simple_pwm; +pub mod spi; +pub mod wdt; diff --git a/mcu/attiny-hal/src/periphals/port.rs b/mcu/attiny-hal/src/periphals/port.rs new file mode 100644 index 0000000000..7a6aa8e0bd --- /dev/null +++ b/mcu/attiny-hal/src/periphals/port.rs @@ -0,0 +1,20 @@ +//! Port +//! +//! # Example +//! +//! For full source code, please refer to the ATmega port example: +//! [`atmega2560-blink.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-blink.rs) +//! +//! ``` +//! let dp = attiny_hal::Peripherals::take().unwrap(); +//! let pins = attiny_hal::pins!(dp); +//! +//! let mut led = pins.pb2.into_output(); +//! +//! loop { +//! led.toggle(); +//! delay_ms(1000); +//! } +//! ``` + +pub use avr_hal_generic::port::{mode, PinMode, PinOps}; diff --git a/mcu/attiny-hal/src/periphals/simple_pwm.rs b/mcu/attiny-hal/src/periphals/simple_pwm.rs new file mode 100644 index 0000000000..013be0683b --- /dev/null +++ b/mcu/attiny-hal/src/periphals/simple_pwm.rs @@ -0,0 +1 @@ +pub use avr_hal_generic::simple_pwm::{IntoPwmPin, Prescaler, PwmPinOps}; diff --git a/mcu/attiny-hal/src/spi.rs b/mcu/attiny-hal/src/periphals/spi.rs similarity index 52% rename from mcu/attiny-hal/src/spi.rs rename to mcu/attiny-hal/src/periphals/spi.rs index 65ae277263..f1e345c89d 100644 --- a/mcu/attiny-hal/src/spi.rs +++ b/mcu/attiny-hal/src/periphals/spi.rs @@ -28,45 +28,4 @@ //! ufmt::uwriteln!(&mut serial, "data: {:?}", data_in).unwrap(); //! ``` - -#[allow(unused_imports)] -use crate::port; pub use avr_hal_generic::spi::*; - -#[cfg(feature = "attiny88")] -pub type Spi = avr_hal_generic::spi::Spi< - crate::Attiny, - crate::pac::SPI, - port::PB5, - port::PB3, - port::PB4, - port::PB2, ->; -#[cfg(feature = "attiny88")] -avr_hal_generic::impl_spi! { - hal: crate::Attiny, - peripheral: crate::pac::SPI, - sclk: port::PB5, - mosi: port::PB3, - miso: port::PB4, - cs: port::PB2, -} - -#[cfg(feature = "attiny167")] -pub type Spi = avr_hal_generic::spi::Spi< - crate::Attiny, - crate::pac::SPI, - port::PA5, - port::PA4, - port::PA2, - port::PA6, ->; -#[cfg(feature = "attiny167")] -avr_hal_generic::impl_spi! { - hal: crate::Attiny, - peripheral: crate::pac::SPI, - sclk: port::PA5, - mosi: port::PA4, - miso: port::PA2, - cs: port::PA6, -} diff --git a/mcu/attiny-hal/src/periphals/wdt.rs b/mcu/attiny-hal/src/periphals/wdt.rs new file mode 100644 index 0000000000..05ec28c634 --- /dev/null +++ b/mcu/attiny-hal/src/periphals/wdt.rs @@ -0,0 +1,4 @@ +#[allow(unused_imports)] +pub use avr_hal_generic::wdt::{Timeout, WdtOps}; + +pub type Wdt = avr_hal_generic::wdt::Wdt; diff --git a/mcu/attiny-hal/src/port.rs b/mcu/attiny-hal/src/port.rs deleted file mode 100644 index eaa0818ff1..0000000000 --- a/mcu/attiny-hal/src/port.rs +++ /dev/null @@ -1,62 +0,0 @@ -//! Port -//! -//! # Example -//! -//! For full source code, please refer to the ATmega port example: -//! [`atmega2560-blink.rs`](https://github.com/Rahix/avr-hal/blob/main/examples/atmega2560/src/bin/atmega2560-blink.rs) -//! -//! ``` -//! let dp = attiny_hal::Peripherals::take().unwrap(); -//! let pins = attiny_hal::pins!(dp); -//! -//! let mut led = pins.pb2.into_output(); -//! -//! loop { -//! led.toggle(); -//! delay_ms(1000); -//! } -//! ``` - -pub use avr_hal_generic::port::{mode, PinMode, PinOps}; - -#[cfg(feature = "attiny2313")] -avr_hal_generic::impl_port_traditional! { - enum Ports { - A: crate::pac::PORTA = [0, 1, 2], - B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], - D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6], - } -} - -#[cfg(feature = "attiny167")] -avr_hal_generic::impl_port_traditional! { - enum Ports { - A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7], - B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], - } -} - -#[cfg(feature = "attiny84")] -avr_hal_generic::impl_port_traditional! { - enum Ports { - A: crate::pac::PORTA = [0, 1, 2, 3, 4, 5, 6, 7], - B: crate::pac::PORTB = [0, 1, 2, 3], - } -} - -#[cfg(feature = "attiny85")] -avr_hal_generic::impl_port_traditional! { - enum Ports { - B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5], - } -} - -#[cfg(feature = "attiny88")] -avr_hal_generic::impl_port_traditional! { - enum Ports { - A: crate::pac::PORTA = [0, 1, 2, 3], - B: crate::pac::PORTB = [0, 1, 2, 3, 4, 5, 6, 7], - C: crate::pac::PORTC = [0, 1, 2, 3, 4, 5, 6, 7], - D: crate::pac::PORTD = [0, 1, 2, 3, 4, 5, 6, 7], - } -} diff --git a/mcu/attiny-hal/src/simple_pwm.rs b/mcu/attiny-hal/src/simple_pwm.rs deleted file mode 100644 index f16a89c9c0..0000000000 --- a/mcu/attiny-hal/src/simple_pwm.rs +++ /dev/null @@ -1,217 +0,0 @@ -pub use avr_hal_generic::simple_pwm::{IntoPwmPin, Prescaler, PwmPinOps}; - -#[cfg(any(feature = "attiny85", feature = "attiny84", feature = "attiny88"))] -use crate::port::*; - -#[cfg(feature = "attiny84")] -avr_hal_generic::impl_simple_pwm! { - /// Use `TC0` for PWM (pins `PB2`, `PA7`) - pub struct Timer0Pwm { - timer: crate::pac::TC0, - init: |tim, prescaler| { - tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast()); - tim.tccr0b.modify(|_r, w| match prescaler { - Prescaler::Direct => w.cs0().direct(), - Prescaler::Prescale8 => w.cs0().prescale_8(), - Prescaler::Prescale64 => w.cs0().prescale_64(), - Prescaler::Prescale256 => w.cs0().prescale_256(), - Prescaler::Prescale1024 => w.cs0().prescale_1024(), - }); - }, - pins: { - PB2: { - ocr: ocr0a, - into_pwm: |tim| if enable { - tim.tccr0a.modify(|_r, w| w.com0a().match_clear()); - } else { - tim.tccr0a.modify(|_r, w| w.com0a().disconnected()); - }, - }, - - PA7: { - ocr: ocr0b, - into_pwm: |tim| if enable { - tim.tccr0a.modify(|_r, w| w.com0b().match_clear()); - } else { - tim.tccr0a.modify(|_r, w| w.com0b().disconnected()); - }, - }, - }, - } -} - -#[cfg(feature = "attiny84")] -avr_hal_generic::impl_simple_pwm! { - /// Use `TC1` for PWM (pins `PA6`, 'PA5') - pub struct Timer1Pwm { - timer: crate::pac::TC1, - init: |tim, prescaler| { - tim.tccr1a.modify(|_, w| w.wgm1().bits(0b01)); - tim.tccr1b.modify(|_, w| w.wgm1().bits(0b01)); - - tim.tccr1b.modify(|_r, w| match prescaler { - Prescaler::Direct => w.cs1().direct(), - Prescaler::Prescale8 => w.cs1().prescale_8(), - Prescaler::Prescale64 => w.cs1().prescale_64(), - Prescaler::Prescale256 => w.cs1().prescale_256(), - Prescaler::Prescale1024 => w.cs1().prescale_1024(), - }); - }, - pins: { - PA6: { - ocr: ocr1a, - into_pwm: |tim| if enable { - tim.tccr1a.modify(|_, w| w.com1a().bits(0b10)); - } else { - tim.tccr1a.modify(|_, w| w.com1a().disconnected()); - }, - }, - - PA5: { - ocr: ocr1b, - into_pwm: |tim| if enable { - tim.tccr1a.modify(|_, w| w.com1b().bits(0b10)); - } else { - tim.tccr1a.modify(|_, w| w.com1b().disconnected()); - }, - }, - }, - } -} - -#[cfg(feature = "attiny85")] -avr_hal_generic::impl_simple_pwm! { - /// Use `TC0` for PWM (pins `PB0`, `PB1`) - /// - /// # Example - /// ``` - /// let mut timer0 = Timer0Pwm::new(dp.TC0, Prescaler::Prescale64); - /// - /// let mut d0 = pins.d0.into_output().into_pwm(&mut timer0); - /// let mut d1 = pins.d1.into_output().into_pwm(&mut timer0); - /// - /// d0.set_duty(128); - /// d0.enable(); - /// ``` - pub struct Timer0Pwm { - timer: crate::pac::TC0, - init: |tim, prescaler| { - tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast()); - tim.tccr0b.modify(|_r, w| match prescaler { - Prescaler::Direct => w.cs0().direct(), - Prescaler::Prescale8 => w.cs0().prescale_8(), - Prescaler::Prescale64 => w.cs0().prescale_64(), - Prescaler::Prescale256 => w.cs0().prescale_256(), - Prescaler::Prescale1024 => w.cs0().prescale_1024(), - }); - }, - pins: { - PB0: { - ocr: ocr0a, - into_pwm: |tim| if enable { - tim.tccr0a.modify(|_r, w| w.com0a().match_clear()); - } else { - tim.tccr0a.modify(|_r, w| w.com0a().disconnected()); - }, - }, - - PB1: { - ocr: ocr0b, - into_pwm: |tim| if enable { - tim.tccr0a.modify(|_r, w| w.com0b().match_clear()); - } else { - tim.tccr0a.modify(|_r, w| w.com0b().disconnected()); - }, - }, - }, - } -} - -#[cfg(feature = "attiny85")] -avr_hal_generic::impl_simple_pwm! { - /// Use `TC1` for PWM (pins `PB4`) - /// - /// # Example - /// ``` - /// let mut timer1 = Timer1Pwm::new(dp.TC1, Prescaler::Prescale64); - /// - /// let mut d4 = pins.d4.into_output().into_pwm(&mut timer1); - /// - /// d4.set_duty(128); - /// d4.enable(); - /// ``` - pub struct Timer1Pwm { - timer: crate::pac::TC1, - init: |tim, prescaler| { - tim.gtccr.modify(|_, w| w.pwm1b().bit(true)); - - tim.tccr1.modify(|_r, w| match prescaler { - Prescaler::Direct => w.cs1().direct(), - Prescaler::Prescale8 => w.cs1().prescale_8(), - Prescaler::Prescale64 => w.cs1().prescale_64(), - Prescaler::Prescale256 => w.cs1().prescale_256(), - Prescaler::Prescale1024 => w.cs1().prescale_1024(), - }); - }, - pins: { - PB4: { - ocr: ocr1b, - into_pwm: |tim| if enable { - tim.gtccr.modify(|_, w| w.com1b().bits(0b10)); - } else { - tim.gtccr.modify(|_, w| w.com1b().disconnected()); - }, - }, - }, - } -} - -#[cfg(feature = "attiny88")] -avr_hal_generic::impl_simple_pwm! { - /// Use `TC1` for PWM (pins `PB1`, 'PB2') - /// - /// # Example - /// ``` - /// let mut timer1 = Timer1Pwm::new(dp.TC1, Prescaler::Prescale64); - /// - /// let mut d9 = pins.d9.into_output().into_pwm(&mut timer1); - /// let mut d10 = pins.d10.into_output().into_pwm(&mut timer1); - /// - /// d9.set_duty(128); - /// d9.enable(); - /// ``` - pub struct Timer1Pwm { - timer: crate::pac::TC1, - init: |tim, prescaler| { - tim.tccr1a.modify(|_, w| w.wgm1().bits(0b01)); - tim.tccr1b.modify(|_, w| w.wgm1().bits(0b01)); - - tim.tccr1b.modify(|_r, w| match prescaler { - Prescaler::Direct => w.cs1().direct(), - Prescaler::Prescale8 => w.cs1().prescale_8(), - Prescaler::Prescale64 => w.cs1().prescale_64(), - Prescaler::Prescale256 => w.cs1().prescale_256(), - Prescaler::Prescale1024 => w.cs1().prescale_1024(), - }); - }, - pins: { - PB1: { - ocr: ocr1a, - into_pwm: |tim| if enable { - tim.tccr1a.modify(|_, w| w.com1a().bits(0b10)); - } else { - tim.tccr1a.modify(|_, w| w.com1a().disconnected()); - }, - }, - - PB2: { - ocr: ocr1b, - into_pwm: |tim| if enable { - tim.tccr1a.modify(|_, w| w.com1b().bits(0b10)); - } else { - tim.tccr1a.modify(|_, w| w.com1b().disconnected()); - }, - }, - }, - } -} diff --git a/mcu/attiny-hal/src/wdt.rs b/mcu/attiny-hal/src/wdt.rs deleted file mode 100644 index 1693051483..0000000000 --- a/mcu/attiny-hal/src/wdt.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[allow(unused_imports)] -pub use avr_hal_generic::wdt::{Timeout, WdtOps}; - -pub type Wdt = avr_hal_generic::wdt::Wdt; - -#[cfg(any(feature = "attiny85", feature = "attiny167", feature = "attiny2313"))] -avr_hal_generic::impl_wdt! { - hal: crate::Attiny, - peripheral: crate::pac::WDT, - mcusr: crate::pac::cpu::MCUSR, - wdtcsr_name: wdtcr, - timeout: |to, w| match to { - Timeout::Ms16 => w.wdpl().cycles_2k_512k(), - Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), - Timeout::Ms64 => w.wdpl().cycles_8k(), - Timeout::Ms125 => w.wdpl().cycles_16k(), - Timeout::Ms250 => w.wdpl().cycles_32k(), - Timeout::Ms500 => w.wdpl().cycles_64k(), - Timeout::Ms1000 => w.wdpl().cycles_128k(), - Timeout::Ms2000 => w.wdpl().cycles_256k(), - Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), - Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), - }, -} - -#[cfg(any(feature = "attiny84", feature = "attiny88"))] -avr_hal_generic::impl_wdt! { - hal: crate::Attiny, - peripheral: crate::pac::WDT, - mcusr: crate::pac::cpu::MCUSR, - wdtcsr_name: wdtcsr, - timeout: |to, w| match to { - Timeout::Ms16 => w.wdpl().cycles_2k_512k(), - Timeout::Ms32 => w.wdpl().cycles_4k_1024k(), - Timeout::Ms64 => w.wdpl().cycles_8k(), - Timeout::Ms125 => w.wdpl().cycles_16k(), - Timeout::Ms250 => w.wdpl().cycles_32k(), - Timeout::Ms500 => w.wdpl().cycles_64k(), - Timeout::Ms1000 => w.wdpl().cycles_128k(), - Timeout::Ms2000 => w.wdpl().cycles_256k(), - Timeout::Ms4000 => w.wdph().set_bit().wdpl().cycles_2k_512k(), - Timeout::Ms8000 => w.wdph().set_bit().wdpl().cycles_4k_1024k(), - }, -}