Sobel Edge Detection in Verilog

This project implements the Sobel edge detection algorithm in Verilog for image processing tasks. The Sobel operator is commonly used to detect edges in images by calculating the gradient magnitude at each pixel. This project explores Verilog, digital image processing, and hardware acceleration techniques for image processing.

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Table of Contents

• Project Overview
• Objectives
• Project Description
• Implementation Steps
• Modules Documentation

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Project Overview

This project provides an opportunity to implement and simulate a hardware-based edge detection solution. It involves using the Sobel operator to process images and generate an edge map, highlighting transitions in pixel intensity.

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Objectives

• Implement the Sobel edge detection algorithm in Verilog.
• Learn the fundamentals of edge detection and digital image processing.
• Gain experience in hardware design and simulation for image processing applications.

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Project Description

The Sobel edge detection algorithm uses two 3x3 convolution kernels to compute the image intensity gradient at each pixel. This highlights edges in the image based on gradient magnitude.

Sobel Kernels:

• Horizontal kernel (Gx):
• Vertical kernel (Gy):

The project involves designing Verilog modules to compute these convolutions and combine the results to produce an edge-detected image.

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Implementation Steps

Step 1: Project Setup

• Install Siemens Questa for Verilog simulation.
• Define the method for inputting and outputting image data (e.g., simulation files or FPGA I/O).

Step 2: Understanding the Sobel Operator

• Study the Sobel operator and its convolution kernels.
• Understand convolution operations for edge detection in images.

Step 3: Verilog Module Design

• To integrate the Sobel operator, define a top-level Verilog module (sobel_top.v).
• Design a controller module (controller.v) to manage the Sobel filter logic.
• Implement convolution logic and gradient magnitude calculations.

Step 4: Testing and Simulation

• Write test benches for simulation with sample image data.
• Use Siemens Questa for testing and waveform analysis.

Step 5: Final Report and Deliverables

• Submit Verilog code, testbenches, and simulation results.
• Include a final report documenting the design process, challenges, and results.

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Modules Documentation

The project consists of two main Verilog modules along with other sub-modules:

1. sobel_top.v:

• Integrates the Sobel operator and handles input/output.
• Processes 9 pixels per clock cycle using a sliding window approach.

2. controller.v:

• Manages control signals and timing for the Sobel filter.

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