OSC

OSC

The Gowin OSC (On-Chip) programmable crystal oscillator provides a clock source for MSPI programming mode, as well as a clock resource for user designs. It allows up to 64 different clock frequencies to be obtained by setting the FREQ_DIV parameter, which is an even number from 2 to 128 and 3, and is used in conjunction with the OSC oscillation frequency (fosc) to calculate the output clock frequency (fCLKOUT = fosc/FREQ_DIV).

This device is supported in Apicula.

Ports

Port	Size	Direction
OSCOUT	1	output

Parameters

Parameter	Default Value
DEVICE	GW1N-4
FREQ_DIV	100 (0b00000000000000000000000001100100)

Verilog Instantiation

OSC #(
    .DEVICE(DEVICE),
    .FREQ_DIV(FREQ_DIV)
) osc_inst (
    .OSCOUT(OSCOUT)
);

OSCA

The Gowin OSCA primitive is a programmable on-chip crystal oscillator that provides a clock source for MSPI programming mode, supports dynamic on/off, and supplies a clock resource for user designs. It can output up to 64 different clock frequencies by setting configuration parameters. The output clock frequency is calculated using the formula fCLKOUT = fossc/FREQ_DIV, where fossc is the OSC oscillation frequency and FREQ_DIV is an even number from 2 to 126 or 3.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
OSCEN	1	input
OSCOUT	1	output

Parameters

Parameter	Default Value
FREQ_DIV	100 (0b00000000000000000000000001100100)

Verilog Instantiation

OSCA #(
    .FREQ_DIV(FREQ_DIV)
) osca_inst (
    .OSCEN(OSCEN),
    .OSCOUT(OSCOUT)
);

OSCB

This device is not yet supported in Apicula

Ports

Port	Size	Direction
FMODE	1	input
OSCEN	1	input
OSCOUT	1	output
OSCREF	1	output
RTCTRIM	6	input
RTRIM	8	input

Parameters

Parameter	Default Value
DYN_TRIM_EN	FALSE
FREQ_DIV	10 (0b00000000000000000000000000001010)
FREQ_MODE	25

Verilog Instantiation

OSCB #(
    .DYN_TRIM_EN(DYN_TRIM_EN),
    .FREQ_DIV(FREQ_DIV),
    .FREQ_MODE(FREQ_MODE)
) oscb_inst (
    .FMODE(FMODE),
    .OSCEN(OSCEN),
    .OSCOUT(OSCOUT),
    .OSCREF(OSCREF),
    .RTCTRIM(RTCTRIM),
    .RTRIM(RTRIM)
);

OSCF

This device is not yet supported in Apicula

Ports

Port	Size	Direction
OSCEN	1	input
OSCOUT	1	output
OSCOUT30M	1	output

Parameters

Parameter	Default Value
FREQ_DIV	100 (0b00000000000000000000000001100100)

Verilog Instantiation

OSCF #(
    .FREQ_DIV(FREQ_DIV)
) oscf_inst (
    .OSCEN(OSCEN),
    .OSCOUT(OSCOUT),
    .OSCOUT30M(OSCOUT30M)
);

OSCH

The on-chip oscillator (OSCH) provides a clock source for MSPI programming and user designs, offering up to 64 possible output frequencies based on setting a single parameter called "FREQ_DIV", which can range from 2 to 128. The output frequency is calculated using the formula f_CLKOUT = 240MHz/FREQ_DIV, with FREQ_DIV being an even number only.

This device is supported in Apicula.

Ports

Port	Size	Direction
OSCOUT	1	output

Parameters

Parameter	Default Value
FREQ_DIV	96 (0b00000000000000000000000001100000)

Verilog Instantiation

OSCH #(
    .FREQ_DIV(FREQ_DIV)
) osch_inst (
    .OSCOUT(OSCOUT)
);

OSCO

The GOWIN OSCO primitive supports dynamic shutdowning of the oscillator and regulator power supply, utilizing an on-chip crystal.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
OSCEN	1	input
OSCOUT	1	output

Parameters

Parameter	Default Value
FREQ_DIV	100 (0b00000000000000000000000001100100)
REGULATOR_EN	0 (0b0)

Verilog Instantiation

OSCO #(
    .FREQ_DIV(FREQ_DIV),
    .REGULATOR_EN(REGULATOR_EN)
) osco_inst (
    .OSCEN(OSCEN),
    .OSCOUT(OSCOUT)
);

OSCW

The Gowin OSCW primitive, also known as on-chip crystal oscillator, is a clocking component that generates a clock signal. It takes in an enable input (OSCEN) and produces an output clock signal (OSCOUT). The frequency of the generated clock can be set using the FREQ_DIV parameter, which has been defined with a default value of 100. The REGULATOR_EN bit, which is initially disabled (set to '0'), appears to be related to the regulation or control of the oscillator's operation.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
OSCOUT	1	output

Parameters

Parameter	Default Value
FREQ_DIV	80 (0b00000000000000000000000001010000)

Verilog Instantiation

OSCW #(
    .FREQ_DIV(FREQ_DIV)
) oscw_inst (
    .OSCOUT(OSCOUT)
);

OSCZ

The Gowin OSCZ primitive is an on-chip oscillator that supports dynamically shutting down, with a clock accuracy up to ±5%. It provides a clock source for MSPI programming and user designs. The output clock frequency can be obtained by dividing the OSC oscillation frequency (foscz) by the FREQ_DIV parameter, which has a range of 2~128 and must be an even number.

This device is supported in Apicula.

Ports

Port	Size	Direction
OSCEN	1	input
OSCOUT	1	output

Parameters

Parameter	Default Value
FREQ_DIV	100 (0b00000000000000000000000001100100)

Verilog Instantiation

OSCZ #(
    .FREQ_DIV(FREQ_DIV)
) oscz_inst (
    .OSCEN(OSCEN),
    .OSCOUT(OSCOUT)
);