Hang during synthesis: Yosys enters an infinite loop during $dffe enable generation (or other pass), with no termination.

[1353369570]

Version

Yosys 0.55+23 (git sha1 e57a2b9, g++ 9.4.0-1ubuntu1~20.04.3 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Minimal Reproduction Example:

module top (
    input wire1,
    input wire2,
    input wire3,
    output reg y
);
    wire wire4,wire5,wire6,wire7,wire8;
    //wire c,     j,    k,     e,    g;
    reg reg1,reg2,reg3,reg4;
    //reg l, n, d, f;

    always @(posedge wire1 or negedge wire4) begin
        if (wire4) begin
            y = wire5 > reg1;
            reg1 = (reg1 | wire5) ? wire6 ? wire2 : wire3 ? 0 : reg2 : 0;      
        end
    end

    always @(wire2) begin
        reg3 = wire6;
    end

    always @(wire7 or wire8 or reg4) begin
        if (wire7) begin
            reg1 = 0;
        end else begin
            reg3 = wire8;
            reg1 = reg4;
        end
    end

endmodule

Yosys script:

read_verilog ;
hierarchy ;proc;opt; abc;clean
synth;

Yosys enters an infinite loop during synthesis of a module with multiple assignment points to a register and asynchronous control logic. This causes the synthesis process to hang, continuously printing the same Adding EN signal... log lines without termination.

Expected Behavior

synth successfully

Actual Behavior

Results in non-terminating log output like:
Adding EN signal on $auto$ff.cc:266:slice$19444669 ($dffe) ...
Adding EN signal on $auto$ff.cc:266:slice$19444674 ($dffe) ...
...

[KrystalDelusion]

Probably because reg3 has multiple drivers (see #4972 and #5058).