diff --git a/examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig b/examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig
index 0b7a6ed1f..e3a0ef97c 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig
@@ -48,7 +48,12 @@ fn adc_to_temp(val: usize) f32 {
 }
 
 pub fn main() !void {
-    try rcc.apply_clock(.{ .ADCprescaler = .RCC_ADCPCLK2_DIV2 });
+    _ = try rcc.apply(.{
+        .ADCPresc = .RCC_ADCPCLK2_DIV2,
+        .flags = .{
+            .USE_ADC1 = true,
+        },
+    });
 
     rcc.enable_clock(.DMA1);
     rcc.enable_clock(.TIM2);
diff --git a/examples/stmicro/stm32/src/stm32f1xx/gpio.zig b/examples/stmicro/stm32/src/stm32f1xx/gpio.zig
index 0d58ce66b..66fc59de0 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/gpio.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/gpio.zig
@@ -7,12 +7,16 @@ const gpio = stm32.gpio;
 const time = stm32.time;
 
 pub fn main() !void {
-    try rcc.apply_clock(.{
-        .SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
+    _ = try rcc.apply(.{
+        .SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
         .PLLSource = .RCC_PLLSOURCE_HSE,
         .PLLMUL = .RCC_PLL_MUL9,
-        .APB1Prescaler = .RCC_HCLK_DIV2,
-        .RTCClkSource = .RCC_RTCCLKSOURCE_LSI,
+        .APB1CLKDivider = .RCC_HCLK_DIV2,
+        .RTCClockSelection = .RCC_RTCCLKSOURCE_LSI,
+        .flags = .{
+            .RTCUsed_ForRCC = true,
+            .HSEOscillator = true,
+        },
     });
     rcc.enable_clock(.GPIOC);
 
diff --git a/examples/stmicro/stm32/src/stm32f1xx/rcc.zig b/examples/stmicro/stm32/src/stm32f1xx/rcc.zig
index 88eab744e..a90450628 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/rcc.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/rcc.zig
@@ -16,15 +16,20 @@ pub const microzig_options = microzig.Options{
 
 const clk_config = rcc.Config{
     .PLLSource = .RCC_PLLSOURCE_HSE,
-    .HSEDivPLL = .RCC_HSE_PREDIV_DIV2,
+    .HSEDivPLL = .RCC_HSE_PREDIV_DIV1,
     .PLLMUL = .RCC_PLL_MUL2,
-    .SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
-    .APB1Prescaler = .RCC_HCLK_DIV1,
-    .MCOMult = .RCC_MCO1SOURCE_SYSCLK,
+    .SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
+    .APB1CLKDivider = .RCC_HCLK_DIV2,
+    .RCC_MCOSource = .RCC_MCO1SOURCE_SYSCLK,
+    .flags = .{
+        .HSEOscillator = true,
+        .MCOUsed_ForRCC = true,
+        .MCOConfig = true,
+    },
 };
 
 pub fn main() !void {
-    try rcc.apply_clock(clk_config);
+    _ = try rcc.apply(clk_config);
     rcc.enable_clock(.GPIOA);
     rcc.enable_clock(.AFIO);
     rcc.enable_clock(.USART1);
diff --git a/examples/stmicro/stm32/src/stm32f1xx/rtc.zig b/examples/stmicro/stm32/src/stm32f1xx/rtc.zig
index cab16198a..50300c36e 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/rtc.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/rtc.zig
@@ -30,7 +30,10 @@ pub fn main() !void {
     //by the system reset, so we need to check if it is already running.
     //If it is not running, we will configure it and enable it.
     if (fresh_start()) {
-        try rcc.apply_clock(.{ .RTCClkSource = .RCC_RTCCLKSOURCE_LSE });
+        _ = try rcc.apply(.{
+            .RTCClockSelection = .RCC_RTCCLKSOURCE_LSE,
+            .flags = .{ .RTCUsed_ForRCC = true, .LSEOscillator = true },
+        });
         rcc.enable_clock(.PWR);
         rcc.enable_clock(.BKP);
 
@@ -66,9 +69,10 @@ pub fn main() !void {
 }
 
 fn fresh_start() bool {
+    const power_down: bool = hal.Reset_Reason == .POR_or_PDR;
     rcc.enable_clock(.PWR);
     rcc.enable_clock(.BKP);
     const data: u32 = (@as(u32, bkp.BackupData1[1].data) << 16) | bkp.BackupData1[0].data;
     rcc.disable_all_clocks();
-    return data != 0xDEADBEEF;
+    return (data != 0xDEADBEEF) or power_down;
 }
diff --git a/examples/stmicro/stm32/src/stm32f1xx/timer.zig b/examples/stmicro/stm32/src/stm32f1xx/timer.zig
index 37cbd0796..3d7a91b90 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/timer.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/timer.zig
@@ -10,6 +10,10 @@ const gpio = stm32.gpio;
 const GPTimer = stm32.timer.GPTimer;
 const time = stm32.time;
 
+//pub const microzig_options: microzig.Options = .{
+//    .interrupts = .{ .TIM3 = .{ .c = time.TIM_handler } },
+//};
+
 //gpios
 const ch1 = gpio.Pin.from_port(.A, 0);
 const ch2 = gpio.Pin.from_port(.A, 1);
@@ -23,7 +27,10 @@ pub fn main() !void {
     //first we need to enable the clocks for the GPIO and TIM peripherals
 
     //use HSE as system clock source, more stable than HSI
-    try rcc.apply_clock(.{ .SysClkSource = .RCC_SYSCLKSOURCE_HSE });
+    _ = try rcc.apply(.{
+        .SYSCLKSource = .RCC_SYSCLKSOURCE_HSE,
+        .flags = .{ .HSEOscillator = true },
+    });
 
     //enable GPIOA and TIM2, TIM3, AFIO clocks
     //AFIO is needed for alternate function remapping, not used in this example but eneble for easy remapping
diff --git a/examples/stmicro/stm32/src/stm32f1xx/timer_capture.zig b/examples/stmicro/stm32/src/stm32f1xx/timer_capture.zig
index 345a3e9b6..a7cd2c7ff 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/timer_capture.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/timer_capture.zig
@@ -65,7 +65,10 @@ pub fn main() !void {
     //first we need to enable the clocks for the GPIO and TIM peripherals
 
     //use HSE as system clock source, more stable than HSI
-    try rcc.apply_clock(.{ .SysClkSource = .RCC_SYSCLKSOURCE_HSE });
+    _ = try rcc.apply(.{
+        .SYSCLKSource = .RCC_SYSCLKSOURCE_HSE,
+        .flags = .{ .HSEOscillator = true },
+    });
 
     //enable GPIOA and TIM2, TIM3, AFIO clocks
     //AFIO is needed for alternate function remapping, not used in this example but eneble for easy remapping
diff --git a/examples/stmicro/stm32/src/stm32f1xx/usb_cdc.zig b/examples/stmicro/stm32/src/stm32f1xx/usb_cdc.zig
index 1c644937a..52ce33435 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/usb_cdc.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/usb_cdc.zig
@@ -412,12 +412,16 @@ fn CDC_read(buf: []u8, timeout: ?Duration) ![]const u8 {
 }
 
 pub fn main() !void {
-    try rcc.apply_clock(.{
+    _ = try rcc.apply(.{
         .PLLSource = .RCC_PLLSOURCE_HSE,
         .PLLMUL = .RCC_PLL_MUL9,
-        .SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
-        .APB1Prescaler = .RCC_HCLK_DIV2,
+        .SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
+        .APB1CLKDivider = .RCC_HCLK_DIV2,
         .USBPrescaler = .RCC_USBCLKSOURCE_PLL_DIV1_5,
+        .flags = .{
+            .HSEOscillator = true,
+            .USBUsed_ForRCC = true,
+        },
     });
 
     rcc.enable_clock(.GPIOA);
diff --git a/examples/stmicro/stm32/src/stm32f1xx/usb_hid.zig b/examples/stmicro/stm32/src/stm32f1xx/usb_hid.zig
index f89bddbcb..bbc2546a7 100644
--- a/examples/stmicro/stm32/src/stm32f1xx/usb_hid.zig
+++ b/examples/stmicro/stm32/src/stm32f1xx/usb_hid.zig
@@ -256,12 +256,13 @@ fn report(keys: []const u8) void {
 }
 
 pub fn main() !void {
-    try rcc.apply_clock(.{
+    _ = try rcc.apply(.{
         .PLLSource = .RCC_PLLSOURCE_HSE,
         .PLLMUL = .RCC_PLL_MUL9,
-        .SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
-        .APB1Prescaler = .RCC_HCLK_DIV2,
+        .SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
+        .APB1CLKDivider = .RCC_HCLK_DIV2,
         .USBPrescaler = .RCC_USBCLKSOURCE_PLL_DIV1_5,
+        .flags = .{ .HSEOscillator = true, .USBUsed_ForRCC = true },
     });
 
     rcc.enable_clock(.GPIOA);
diff --git a/port/stmicro/stm32/build.zig b/port/stmicro/stm32/build.zig
index 6c0610314..b29728714 100644
--- a/port/stmicro/stm32/build.zig
+++ b/port/stmicro/stm32/build.zig
@@ -15,7 +15,17 @@ boards: struct {
 
 pub fn init(dep: *std.Build.Dependency) Self {
     const b = dep.builder;
-    const chips = Chips.init(dep);
+
+    const clockhelper_dep = b.dependency("ClockHelper", .{}).module("clockhelper");
+
+    const hal_imports: []std.Build.Module.Import = b.allocator.dupe(std.Build.Module.Import, &.{
+        .{
+            .name = "ClockTree",
+            .module = clockhelper_dep,
+        },
+    }) catch @panic("out of memory");
+
+    const chips = Chips.init(dep, hal_imports);
 
     return .{
         .chips = chips,
diff --git a/port/stmicro/stm32/build.zig.zon b/port/stmicro/stm32/build.zig.zon
index e777ae72c..331ad500a 100644
--- a/port/stmicro/stm32/build.zig.zon
+++ b/port/stmicro/stm32/build.zig.zon
@@ -9,6 +9,10 @@
             .url = "git+https://github.com/embassy-rs/stm32-data-generated.git#5198a6e36b24f6d79c4ac91af5e61e8d54667d88",
             .hash = "N-V-__8AAFi8WBlOh-NikHFVBjzQE0F1KixgKjVWYnlijPNm",
         },
+        .ClockHelper = .{
+            .url = "git+https://github.com/ZigEmbeddedGroup/ClockHelper#7fd073b1be9544941c15f9a63032ed06149ddb70",
+            .hash = "ClockHelper-2.0.0-RcMaOSniGQHXH_qeoZbQDG64XThqpXTVPMfJ6P7LHpYY",
+        },
     },
     .paths = .{
         "README.md",
diff --git a/port/stmicro/stm32/src/Chips.zig b/port/stmicro/stm32/src/Chips.zig
index 16cabb2c2..b22d65cba 100644
--- a/port/stmicro/stm32/src/Chips.zig
+++ b/port/stmicro/stm32/src/Chips.zig
@@ -1,3 +1,6 @@
+//AUTOMATICALLY GENERATED FILE!
+//For modifications, consider editing the generation script in generate.zig
+
 const std = @import("std");
 const microzig = @import("microzig/build-internals");
 
@@ -1404,7 +1407,7 @@ STM32WLE5J8: *microzig.Target,
 STM32WLE5JB: *microzig.Target,
 STM32WLE5JC: *microzig.Target,
 
-pub fn init(dep: *std.Build.Dependency) Self {
+pub fn init(dep: *std.Build.Dependency, hal_imports: []std.Build.Module.Import) Self {
     const b = dep.builder;
     const embassy = b.dependency("stm32-data-generated", .{}).path(".");
     var ret: Self = undefined;
@@ -4561,6 +4564,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4586,6 +4590,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4611,6 +4616,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4636,6 +4642,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4661,6 +4668,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4686,6 +4694,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4711,6 +4720,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4736,6 +4746,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4761,6 +4772,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4786,6 +4798,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4811,6 +4824,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4837,6 +4851,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4863,6 +4878,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4888,6 +4904,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4913,6 +4930,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4938,6 +4956,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4963,6 +4982,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -4988,6 +5008,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5013,6 +5034,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5038,6 +5060,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5063,6 +5086,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5088,6 +5112,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5114,6 +5139,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5140,6 +5166,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5165,6 +5192,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5190,6 +5218,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5215,6 +5244,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5241,6 +5271,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -5267,6 +5298,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32F103.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28554,6 +28586,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28582,6 +28615,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28610,6 +28644,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28638,6 +28673,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28666,6 +28702,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28694,6 +28731,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28722,6 +28760,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28750,6 +28789,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28778,6 +28818,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28806,6 +28847,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28834,6 +28876,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28862,6 +28905,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28890,6 +28934,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28918,6 +28963,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28946,6 +28992,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -28974,6 +29021,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29002,6 +29050,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29030,6 +29079,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29058,6 +29108,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29086,6 +29137,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29114,6 +29166,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29142,6 +29195,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29170,6 +29224,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29198,6 +29253,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29226,6 +29282,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29254,6 +29311,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29282,6 +29340,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
@@ -29310,6 +29369,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
         .hal = .{
             .root_source_file = b.path("src/hals/STM32L47X.zig"),
+            .imports = hal_imports,
         },
     };
 
diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig
index 47f96e668..f46e1d717 100644
--- a/port/stmicro/stm32/src/generate.zig
+++ b/port/stmicro/stm32/src/generate.zig
@@ -89,6 +89,9 @@ fn generate_chips_file(
     chip_files: []const std.json.Parsed(ChipFile),
 ) !void {
     try writer.writeAll(
+        \\//AUTOMATICALLY GENERATED FILE!
+        \\//For modifications, consider editing the generation script in generate.zig
+        \\
         \\const std = @import("std");
         \\const microzig = @import("microzig/build-internals");
         \\
@@ -104,7 +107,7 @@ fn generate_chips_file(
 
     try writer.writeAll(
         \\
-        \\pub fn init(dep: *std.Build.Dependency) Self {
+        \\pub fn init(dep: *std.Build.Dependency, hal_imports: []std.Build.Module.Import) Self {
         \\    const b = dep.builder;
         \\    const embassy = b.dependency("stm32-data-generated", .{}).path(".");
         \\    var ret: Self = undefined;
@@ -255,6 +258,7 @@ fn generate_chips_file(
             try writer.writeAll(
                 \\        .hal = .{
                 \\            .root_source_file = b.path("src/hals/STM32F103.zig"),
+                \\            .imports = hal_imports,
                 \\        },
                 \\
             );
@@ -263,6 +267,7 @@ fn generate_chips_file(
             try writer.writeAll(
                 \\        .hal = .{
                 \\            .root_source_file = b.path("src/hals/STM32L47X.zig"),
+                \\            .imports = hal_imports,
                 \\        },
                 \\
             );
diff --git a/port/stmicro/stm32/src/hals/STM32F103.zig b/port/stmicro/stm32/src/hals/STM32F103.zig
index 1024d1595..cf1088c6a 100644
--- a/port/stmicro/stm32/src/hals/STM32F103.zig
+++ b/port/stmicro/stm32/src/hals/STM32F103.zig
@@ -21,7 +21,7 @@ const util = @import("./common/util.zig");
 //temporary solution
 pub const default_interrupts = util.load_timer_interrupt(time.TIM_handler);
 
-pub var RESET: rcc.ResetReason = .POR_or_PDR;
+pub var Reset_Reason: rcc.ResetReason = .POR_or_PDR;
 pub fn init() void {
-    RESET = rcc.get_reset_reason();
+    Reset_Reason = rcc.get_reset_reason();
 }
diff --git a/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f103.zig b/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f103.zig
deleted file mode 100644
index 1bcd57465..000000000
--- a/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f103.zig
+++ /dev/null
@@ -1,841 +0,0 @@
-//NOTE: this clock tree is valid for all STM32F1xx low to high density devices
-//NOTE: this file was manually generated from data coming from CubeMX, manual changes may be necessary
-
-const std = @import("std");
-const clock = @import("clocknodes.zig");
-const ClockNode = clock.ClockNode;
-const ClockNodeTypes = clock.ClockNodesTypes;
-const ClockState = clock.ClockState;
-const ClockError = clock.ClockError;
-
-pub const LSE_VALUEConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const HSE_VALUEConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const HSEDivPLLConf = enum {
-    RCC_HSE_PREDIV_DIV1,
-    RCC_HSE_PREDIV_DIV2,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HSE_PREDIV_DIV2 => 2,
-            .RCC_HSE_PREDIV_DIV1 => 1,
-        };
-    }
-};
-pub const SYSCLKSourceConf = enum {
-    RCC_SYSCLKSOURCE_HSI,
-    RCC_SYSCLKSOURCE_HSE,
-    RCC_SYSCLKSOURCE_PLLCLK,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const RTCClockSelectionConf = enum {
-    RCC_RTCCLKSOURCE_HSE_DIV128,
-    RCC_RTCCLKSOURCE_LSE,
-    RCC_RTCCLKSOURCE_LSI,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const MCOmultConf = enum {
-    RCC_MCO1SOURCE_PLLCLK,
-    RCC_MCO1SOURCE_HSI,
-    RCC_MCO1SOURCE_HSE,
-    RCC_MCO1SOURCE_SYSCLK,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const AHBCLKDividerConf = enum {
-    RCC_SYSCLK_DIV1,
-    RCC_SYSCLK_DIV2,
-    RCC_SYSCLK_DIV4,
-    RCC_SYSCLK_DIV8,
-    RCC_SYSCLK_DIV16,
-    RCC_SYSCLK_DIV64,
-    RCC_SYSCLK_DIV128,
-    RCC_SYSCLK_DIV256,
-    RCC_SYSCLK_DIV512,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_SYSCLK_DIV64 => 64,
-            .RCC_SYSCLK_DIV2 => 2,
-            .RCC_SYSCLK_DIV512 => 512,
-            .RCC_SYSCLK_DIV16 => 16,
-            .RCC_SYSCLK_DIV1 => 1,
-            .RCC_SYSCLK_DIV4 => 4,
-            .RCC_SYSCLK_DIV8 => 8,
-            .RCC_SYSCLK_DIV256 => 256,
-            .RCC_SYSCLK_DIV128 => 128,
-        };
-    }
-};
-pub const TimSys_DivConf = enum {
-    SYSTICK_CLKSOURCE_HCLK,
-    SYSTICK_CLKSOURCE_HCLK_DIV8,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .SYSTICK_CLKSOURCE_HCLK => 1,
-            .SYSTICK_CLKSOURCE_HCLK_DIV8 => 8,
-        };
-    }
-};
-pub const APB1CLKDividerConf = enum {
-    RCC_HCLK_DIV1,
-    RCC_HCLK_DIV2,
-    RCC_HCLK_DIV4,
-    RCC_HCLK_DIV8,
-    RCC_HCLK_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HCLK_DIV16 => 16,
-            .RCC_HCLK_DIV2 => 2,
-            .RCC_HCLK_DIV8 => 8,
-            .RCC_HCLK_DIV4 => 4,
-            .RCC_HCLK_DIV1 => 1,
-        };
-    }
-};
-pub const APB2CLKDividerConf = enum {
-    RCC_HCLK_DIV1,
-    RCC_HCLK_DIV2,
-    RCC_HCLK_DIV4,
-    RCC_HCLK_DIV8,
-    RCC_HCLK_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HCLK_DIV16 => 16,
-            .RCC_HCLK_DIV2 => 2,
-            .RCC_HCLK_DIV8 => 8,
-            .RCC_HCLK_DIV4 => 4,
-            .RCC_HCLK_DIV1 => 1,
-        };
-    }
-};
-pub const ADCPrescConf = enum {
-    RCC_ADCPCLK2_DIV2,
-    RCC_ADCPCLK2_DIV4,
-    RCC_ADCPCLK2_DIV6,
-    RCC_ADCPCLK2_DIV8,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_ADCPCLK2_DIV6 => 6,
-            .RCC_ADCPCLK2_DIV8 => 8,
-            .RCC_ADCPCLK2_DIV2 => 2,
-            .RCC_ADCPCLK2_DIV4 => 4,
-        };
-    }
-};
-pub const USBPrescalerConf = enum {
-    RCC_USBCLKSOURCE_PLL,
-    RCC_USBCLKSOURCE_PLL_DIV1_5,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_USBCLKSOURCE_PLL => 1,
-            .RCC_USBCLKSOURCE_PLL_DIV1_5 => 1.5,
-        };
-    }
-};
-pub const PLLSourceVirtualConf = enum {
-    RCC_PLLSOURCE_HSI_DIV2,
-    RCC_PLLSOURCE_HSE,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const PLLMULConf = enum {
-    RCC_PLL_MUL2,
-    RCC_PLL_MUL3,
-    RCC_PLL_MUL4,
-    RCC_PLL_MUL5,
-    RCC_PLL_MUL6,
-    RCC_PLL_MUL7,
-    RCC_PLL_MUL8,
-    RCC_PLL_MUL9,
-    RCC_PLL_MUL10,
-    RCC_PLL_MUL11,
-    RCC_PLL_MUL12,
-    RCC_PLL_MUL13,
-    RCC_PLL_MUL14,
-    RCC_PLL_MUL15,
-    RCC_PLL_MUL16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_PLL_MUL11 => 11,
-            .RCC_PLL_MUL7 => 7,
-            .RCC_PLL_MUL10 => 10,
-            .RCC_PLL_MUL12 => 12,
-            .RCC_PLL_MUL2 => 2,
-            .RCC_PLL_MUL8 => 8,
-            .RCC_PLL_MUL16 => 16,
-            .RCC_PLL_MUL14 => 14,
-            .RCC_PLL_MUL9 => 9,
-            .RCC_PLL_MUL6 => 6,
-            .RCC_PLL_MUL15 => 15,
-            .RCC_PLL_MUL3 => 3,
-            .RCC_PLL_MUL5 => 5,
-            .RCC_PLL_MUL4 => 4,
-            .RCC_PLL_MUL13 => 13,
-        };
-    }
-};
-pub const HSE_TimeoutConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const LSE_TimeoutConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const HSICalibrationValueConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const Config = struct {
-    LSEOSC: ?LSE_VALUEConf = null,
-    HSEOSC: ?HSE_VALUEConf = null,
-    HSEDivPLL: ?HSEDivPLLConf = null,
-    SysClkSource: ?SYSCLKSourceConf = null,
-    RTCClkSource: ?RTCClockSelectionConf = null,
-    MCOMult: ?MCOmultConf = null,
-    AHBPrescaler: ?AHBCLKDividerConf = null,
-    TimSysPresc: ?TimSys_DivConf = null,
-    APB1Prescaler: ?APB1CLKDividerConf = null,
-    APB2Prescaler: ?APB2CLKDividerConf = null,
-    ADCprescaler: ?ADCPrescConf = null,
-    USBPrescaler: ?USBPrescalerConf = null,
-    PLLSource: ?PLLSourceVirtualConf = null,
-    PLLMUL: ?PLLMULConf = null,
-    HSE_Timeout: ?HSE_TimeoutConf = null,
-    LSE_Timeout: ?LSE_TimeoutConf = null,
-    HSICalibrationValue: ?HSICalibrationValueConf = null,
-};
-
-pub const ConfigWithRef = struct {
-    LSE_VALUE: ?LSE_VALUEConf = null,
-    HSE_VALUE: ?HSE_VALUEConf = null,
-    HSEDivPLL: ?HSEDivPLLConf = null,
-    SYSCLKSource: ?SYSCLKSourceConf = null,
-    RTCClockSelection: ?RTCClockSelectionConf = null,
-    MCOmult: ?MCOmultConf = null,
-    AHBCLKDivider: ?AHBCLKDividerConf = null,
-    TimSys_Div: ?TimSys_DivConf = null,
-    APB1CLKDivider: ?APB1CLKDividerConf = null,
-    APB2CLKDivider: ?APB2CLKDividerConf = null,
-    ADCPresc: ?ADCPrescConf = null,
-    USBPrescaler: ?USBPrescalerConf = null,
-    PLLSourceVirtual: ?PLLSourceVirtualConf = null,
-    PLLMUL: ?PLLMULConf = null,
-    HSE_Timeout: ?HSE_TimeoutConf = null,
-    LSE_Timeout: ?LSE_TimeoutConf = null,
-    HSICalibrationValue: ?HSICalibrationValueConf = null,
-    pub fn into_config(self: *const ConfigWithRef) Config {
-        return .{
-            .LSEOSC = self.LSE_VALUE,
-            .HSEOSC = self.HSE_VALUE,
-            .HSEDivPLL = self.HSEDivPLL,
-            .SysClkSource = self.SYSCLKSource,
-            .RTCClkSource = self.RTCClockSelection,
-            .MCOMult = self.MCOmult,
-            .AHBPrescaler = self.AHBCLKDivider,
-            .TimSysPresc = self.TimSys_Div,
-            .APB1Prescaler = self.APB1CLKDivider,
-            .APB2Prescaler = self.APB2CLKDivider,
-            .ADCprescaler = self.ADCPresc,
-            .USBPrescaler = self.USBPrescaler,
-            .PLLSource = self.PLLSourceVirtual,
-            .PLLMUL = self.PLLMUL,
-            .HSE_Timeout = self.HSE_Timeout,
-            .LSE_Timeout = self.LSE_Timeout,
-            .HSICalibrationValue = self.HSICalibrationValue,
-        };
-    }
-};
-
-pub const ClockTree = struct {
-    const this = @This();
-
-    HSIRC: ClockNode,
-    FLITFCLKoutput: ClockNode,
-    HSIDivPLL: ClockNode,
-    LSIRC: ClockNode,
-    LSEOSC: ClockNode,
-    HSEOSC: ClockNode,
-    HSEDivPLL: ClockNode,
-    SysClkSource: ClockNode,
-    SysCLKOutput: ClockNode,
-    I2S2ClkOutput: ClockNode,
-    I2S3ClkOutput: ClockNode,
-    HSERTCDevisor: ClockNode,
-    RTCClkSource: ClockNode,
-    RTCOutput: ClockNode,
-    IWDGOutput: ClockNode,
-    MCOMultDivisor: ClockNode,
-    MCOMult: ClockNode,
-    MCOoutput: ClockNode,
-    AHBPrescaler: ClockNode,
-    AHBOutput: ClockNode,
-    HCLKDiv2: ClockNode,
-    SDIOHCLKDiv2: ClockNode,
-    HCLKOutput: ClockNode,
-    FSMClkOutput: ClockNode,
-    SDIOClkOutput: ClockNode,
-    FCLKCortexOutput: ClockNode,
-    TimSysPresc: ClockNode,
-    TimSysOutput: ClockNode,
-    APB1Prescaler: ClockNode,
-    APB1Output: ClockNode,
-    TimPrescalerAPB1: ClockNode,
-    TimPrescOut1: ClockNode,
-    APB2Prescaler: ClockNode,
-    APB2Output: ClockNode,
-    TimPrescalerAPB2: ClockNode,
-    TimPrescOut2: ClockNode,
-    ADCprescaler: ClockNode,
-    ADCoutput: ClockNode,
-    USBPrescaler: ClockNode,
-    USBoutput: ClockNode,
-    PLLSource: ClockNode,
-    VCO2output: ClockNode,
-    PLLMUL: ClockNode,
-    HSE_Timeout: ClockNodeTypes,
-    LSE_Timeout: ClockNodeTypes,
-    HSICalibrationValue: ClockNodeTypes,
-
-    pub fn init_comptime(comptime config: Config) this {
-        const HSIRCval = ClockNodeTypes{
-            .source = .{ .value = 8000000 },
-        };
-        const HSIRC: ClockNode = .{
-            .name = "HSIRC",
-            .Nodetype = HSIRCval,
-        };
-        const FLITFCLKoutputval = ClockNodeTypes{ .output = null };
-        const FLITFCLKoutput: ClockNode = .{
-            .name = "FLITFCLKoutput",
-            .Nodetype = FLITFCLKoutputval,
-            .parents = &[_]*const ClockNode{&HSIRC},
-        };
-        const HSIDivPLLval = ClockNodeTypes{
-            .div = .{ .value = 2 },
-        };
-        const HSIDivPLL: ClockNode = .{
-            .name = "HSIDivPLL",
-            .Nodetype = HSIDivPLLval,
-            .parents = &[_]*const ClockNode{&HSIRC},
-        };
-        const LSIRCval = ClockNodeTypes{
-            .source = .{ .value = 40000 },
-        };
-        const LSIRC: ClockNode = .{
-            .name = "LSIRC",
-            .Nodetype = LSIRCval,
-        };
-        const LSEOSCval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.LSEOSC) |val| val.get() else 32768,
-                .limit = .{ .max = 1000000, .min = 0 },
-            },
-        };
-        const LSEOSC: ClockNode = .{
-            .name = "LSEOSC",
-            .Nodetype = LSEOSCval,
-        };
-        const HSEOSCval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSEOSC) |val| val.get() else 8000000,
-                .limit = .{ .max = 16000000, .min = 4000000 },
-            },
-        };
-        const HSEOSC: ClockNode = .{
-            .name = "HSEOSC",
-            .Nodetype = HSEOSCval,
-        };
-        const HSEDivPLLval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.HSEDivPLL) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const HSEDivPLL: ClockNode = .{
-            .name = "HSEDivPLL",
-            .Nodetype = HSEDivPLLval,
-            .parents = &[_]*const ClockNode{&HSEOSC},
-        };
-        const PLLSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.PLLSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const PLLSource: ClockNode = .{
-            .name = "PLLSource",
-            .Nodetype = PLLSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSIDivPLL,
-                &HSEDivPLL,
-            },
-        };
-        const VCO2outputval = ClockNodeTypes{ .output = null };
-        const VCO2output: ClockNode = .{
-            .name = "VCO2output",
-            .Nodetype = VCO2outputval,
-            .parents = &[_]*const ClockNode{&PLLSource},
-        };
-        const PLLMULval = ClockNodeTypes{ .mul = .{
-            .value = inner: {
-                if (config.PLLMUL) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 2;
-                }
-            },
-        } };
-        const PLLMUL: ClockNode = .{
-            .name = "PLLMUL",
-            .Nodetype = PLLMULval,
-            .parents = &[_]*const ClockNode{&VCO2output},
-        };
-        const SysClkSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.SysClkSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const SysClkSource: ClockNode = .{
-            .name = "SysClkSource",
-            .Nodetype = SysClkSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSIRC,
-                &HSEOSC,
-                &PLLMUL,
-            },
-        };
-        const SysCLKOutputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const SysCLKOutput: ClockNode = .{
-            .name = "SysCLKOutput",
-            .Nodetype = SysCLKOutputval,
-            .parents = &[_]*const ClockNode{&SysClkSource},
-        };
-        const I2S2ClkOutputval = ClockNodeTypes{ .output = null };
-        const I2S2ClkOutput: ClockNode = .{
-            .name = "I2S2ClkOutput",
-            .Nodetype = I2S2ClkOutputval,
-            .parents = &[_]*const ClockNode{&SysCLKOutput},
-        };
-        const I2S3ClkOutputval = ClockNodeTypes{ .output = null };
-        const I2S3ClkOutput: ClockNode = .{
-            .name = "I2S3ClkOutput",
-            .Nodetype = I2S3ClkOutputval,
-            .parents = &[_]*const ClockNode{&SysCLKOutput},
-        };
-        const HSERTCDevisorval = ClockNodeTypes{
-            .div = .{ .value = 128 },
-        };
-        const HSERTCDevisor: ClockNode = .{
-            .name = "HSERTCDevisor",
-            .Nodetype = HSERTCDevisorval,
-            .parents = &[_]*const ClockNode{&HSEOSC},
-        };
-        const RTCClkSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.RTCClkSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 2;
-                }
-            },
-        };
-        const RTCClkSource: ClockNode = .{
-            .name = "RTCClkSource",
-            .Nodetype = RTCClkSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSERTCDevisor,
-                &LSEOSC,
-                &LSIRC,
-            },
-        };
-        const RTCOutputval = ClockNodeTypes{ .output = null };
-        const RTCOutput: ClockNode = .{
-            .name = "RTCOutput",
-            .Nodetype = RTCOutputval,
-            .parents = &[_]*const ClockNode{&RTCClkSource},
-        };
-        const IWDGOutputval = ClockNodeTypes{ .output = null };
-        const IWDGOutput: ClockNode = .{
-            .name = "IWDGOutput",
-            .Nodetype = IWDGOutputval,
-            .parents = &[_]*const ClockNode{&LSIRC},
-        };
-        const MCOMultDivisorval = ClockNodeTypes{
-            .div = .{ .value = 2 },
-        };
-        const MCOMultDivisor: ClockNode = .{
-            .name = "MCOMultDivisor",
-            .Nodetype = MCOMultDivisorval,
-            .parents = &[_]*const ClockNode{&PLLMUL},
-        };
-        const MCOMultval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.MCOMult) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 3;
-                }
-            },
-        };
-        const MCOMult: ClockNode = .{
-            .name = "MCOMult",
-            .Nodetype = MCOMultval,
-
-            .parents = &[_]*const ClockNode{
-                &MCOMultDivisor,
-                &HSIRC,
-                &HSEOSC,
-                &SysCLKOutput,
-            },
-        };
-        const MCOoutputval = ClockNodeTypes{
-            .output = .{ .max = 50000000, .min = 0 },
-        };
-        const MCOoutput: ClockNode = .{
-            .name = "MCOoutput",
-            .Nodetype = MCOoutputval,
-            .parents = &[_]*const ClockNode{&MCOMult},
-        };
-        const AHBPrescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.AHBPrescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const AHBPrescaler: ClockNode = .{
-            .name = "AHBPrescaler",
-            .Nodetype = AHBPrescalerval,
-            .parents = &[_]*const ClockNode{&SysCLKOutput},
-        };
-        const AHBOutputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const AHBOutput: ClockNode = .{
-            .name = "AHBOutput",
-            .Nodetype = AHBOutputval,
-            .parents = &[_]*const ClockNode{&AHBPrescaler},
-        };
-        const HCLKDiv2val = ClockNodeTypes{
-            .div = .{ .value = 2 },
-        };
-        const HCLKDiv2: ClockNode = .{
-            .name = "HCLKDiv2",
-            .Nodetype = HCLKDiv2val,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const SDIOHCLKDiv2val = ClockNodeTypes{ .output = null };
-        const SDIOHCLKDiv2: ClockNode = .{
-            .name = "SDIOHCLKDiv2",
-            .Nodetype = SDIOHCLKDiv2val,
-            .parents = &[_]*const ClockNode{&HCLKDiv2},
-        };
-        const HCLKOutputval = ClockNodeTypes{ .output = null };
-        const HCLKOutput: ClockNode = .{
-            .name = "HCLKOutput",
-            .Nodetype = HCLKOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const FSMClkOutputval = ClockNodeTypes{ .output = null };
-        const FSMClkOutput: ClockNode = .{
-            .name = "FSMClkOutput",
-            .Nodetype = FSMClkOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const SDIOClkOutputval = ClockNodeTypes{ .output = null };
-        const SDIOClkOutput: ClockNode = .{
-            .name = "SDIOClkOutput",
-            .Nodetype = SDIOClkOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const FCLKCortexOutputval = ClockNodeTypes{ .output = null };
-        const FCLKCortexOutput: ClockNode = .{
-            .name = "FCLKCortexOutput",
-            .Nodetype = FCLKCortexOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const TimSysPrescval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.TimSysPresc) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const TimSysPresc: ClockNode = .{
-            .name = "TimSysPresc",
-            .Nodetype = TimSysPrescval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const TimSysOutputval = ClockNodeTypes{ .output = null };
-        const TimSysOutput: ClockNode = .{
-            .name = "TimSysOutput",
-            .Nodetype = TimSysOutputval,
-            .parents = &[_]*const ClockNode{&TimSysPresc},
-        };
-        const APB1Prescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.APB1Prescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const APB1Prescaler: ClockNode = .{
-            .name = "APB1Prescaler",
-            .Nodetype = APB1Prescalerval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const APB1Outputval = ClockNodeTypes{
-            .output = .{ .max = 36000000, .min = 0 },
-        };
-        const APB1Output: ClockNode = .{
-            .name = "APB1Output",
-            .Nodetype = APB1Outputval,
-            .parents = &[_]*const ClockNode{&APB1Prescaler},
-        };
-        const TimPrescalerAPB1val = blk: {
-            if (APB1Prescalerval.num_val() == 1) {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 1 },
-                };
-            } else {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 2 },
-                };
-            }
-        };
-        const TimPrescalerAPB1: ClockNode = .{
-            .name = "TimPrescalerAPB1",
-            .Nodetype = TimPrescalerAPB1val,
-            .parents = &[_]*const ClockNode{&APB1Prescaler},
-        };
-        const TimPrescOut1val = ClockNodeTypes{ .output = null };
-        const TimPrescOut1: ClockNode = .{
-            .name = "TimPrescOut1",
-            .Nodetype = TimPrescOut1val,
-            .parents = &[_]*const ClockNode{&TimPrescalerAPB1},
-        };
-        const APB2Prescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.APB2Prescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const APB2Prescaler: ClockNode = .{
-            .name = "APB2Prescaler",
-            .Nodetype = APB2Prescalerval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const APB2Outputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const APB2Output: ClockNode = .{
-            .name = "APB2Output",
-            .Nodetype = APB2Outputval,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const TimPrescalerAPB2val = blk: {
-            if (APB2Prescalerval.num_val() == 1) {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 1 },
-                };
-            } else {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 2 },
-                };
-            }
-        };
-        const TimPrescalerAPB2: ClockNode = .{
-            .name = "TimPrescalerAPB2",
-            .Nodetype = TimPrescalerAPB2val,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const TimPrescOut2val = ClockNodeTypes{ .output = null };
-        const TimPrescOut2: ClockNode = .{
-            .name = "TimPrescOut2",
-            .Nodetype = TimPrescOut2val,
-            .parents = &[_]*const ClockNode{&TimPrescalerAPB2},
-        };
-        const ADCprescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.ADCprescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 2;
-                }
-            },
-        } };
-        const ADCprescaler: ClockNode = .{
-            .name = "ADCprescaler",
-            .Nodetype = ADCprescalerval,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const ADCoutputval = ClockNodeTypes{
-            .output = .{ .max = 14000000, .min = 0 },
-        };
-        const ADCoutput: ClockNode = .{
-            .name = "ADCoutput",
-            .Nodetype = ADCoutputval,
-            .parents = &[_]*const ClockNode{&ADCprescaler},
-        };
-        const USBPrescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.USBPrescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const USBPrescaler: ClockNode = .{
-            .name = "USBPrescaler",
-            .Nodetype = USBPrescalerval,
-            .parents = &[_]*const ClockNode{&PLLMUL},
-        };
-        const USBoutputval = ClockNodeTypes{
-            .output = .{ .max = 48120000, .min = 47880000 },
-        };
-        const USBoutput: ClockNode = .{
-            .name = "USBoutput",
-            .Nodetype = USBoutputval,
-            .parents = &[_]*const ClockNode{&USBPrescaler},
-        };
-        const HSE_Timeoutval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSE_Timeout) |val| val.get() else 100,
-                .limit = .{ .max = 4294967295.0, .min = 1 },
-            },
-        };
-        const LSE_Timeoutval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.LSE_Timeout) |val| val.get() else 5000,
-                .limit = .{ .max = 4294967295.0, .min = 1 },
-            },
-        };
-        const HSICalibrationValueval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSICalibrationValue) |val| val.get() else 16,
-                .limit = .{ .max = 31, .min = 0 },
-            },
-        };
-        return .{
-            .HSIRC = HSIRC,
-            .FLITFCLKoutput = FLITFCLKoutput,
-            .HSIDivPLL = HSIDivPLL,
-            .LSIRC = LSIRC,
-            .LSEOSC = LSEOSC,
-            .HSEOSC = HSEOSC,
-            .HSEDivPLL = HSEDivPLL,
-            .SysClkSource = SysClkSource,
-            .SysCLKOutput = SysCLKOutput,
-            .I2S2ClkOutput = I2S2ClkOutput,
-            .I2S3ClkOutput = I2S3ClkOutput,
-            .HSERTCDevisor = HSERTCDevisor,
-            .RTCClkSource = RTCClkSource,
-            .RTCOutput = RTCOutput,
-            .IWDGOutput = IWDGOutput,
-            .MCOMultDivisor = MCOMultDivisor,
-            .MCOMult = MCOMult,
-            .MCOoutput = MCOoutput,
-            .AHBPrescaler = AHBPrescaler,
-            .AHBOutput = AHBOutput,
-            .HCLKDiv2 = HCLKDiv2,
-            .SDIOHCLKDiv2 = SDIOHCLKDiv2,
-            .HCLKOutput = HCLKOutput,
-            .FSMClkOutput = FSMClkOutput,
-            .SDIOClkOutput = SDIOClkOutput,
-            .FCLKCortexOutput = FCLKCortexOutput,
-            .TimSysPresc = TimSysPresc,
-            .TimSysOutput = TimSysOutput,
-            .APB1Prescaler = APB1Prescaler,
-            .APB1Output = APB1Output,
-            .TimPrescalerAPB1 = TimPrescalerAPB1,
-            .TimPrescOut1 = TimPrescOut1,
-            .APB2Prescaler = APB2Prescaler,
-            .APB2Output = APB2Output,
-            .TimPrescalerAPB2 = TimPrescalerAPB2,
-            .TimPrescOut2 = TimPrescOut2,
-            .ADCprescaler = ADCprescaler,
-            .ADCoutput = ADCoutput,
-            .USBPrescaler = USBPrescaler,
-            .USBoutput = USBoutput,
-            .PLLSource = PLLSource,
-            .VCO2output = VCO2output,
-            .PLLMUL = PLLMUL,
-            .HSE_Timeout = HSE_Timeoutval,
-            .LSE_Timeout = LSE_Timeoutval,
-            .HSICalibrationValue = HSICalibrationValueval,
-        };
-    }
-
-    pub fn validate(comptime self: *const this) void {
-        _ = self.I2S2ClkOutput.get_comptime();
-        _ = self.I2S3ClkOutput.get_comptime();
-        _ = self.AHBOutput.get_comptime();
-        _ = self.SDIOHCLKDiv2.get_comptime();
-        _ = self.HCLKOutput.get_comptime();
-        _ = self.FSMClkOutput.get_comptime();
-        _ = self.SDIOClkOutput.get_comptime();
-        _ = self.FCLKCortexOutput.get_comptime();
-        _ = self.TimSysOutput.get_comptime();
-        _ = self.APB1Output.get_comptime();
-        _ = self.TimPrescOut1.get_comptime();
-        _ = self.APB2Output.get_comptime();
-        _ = self.TimPrescOut2.get_comptime();
-        _ = self.ADCoutput.get_comptime();
-        _ = self.USBoutput.get_comptime();
-    }
-};
diff --git a/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f105.zig b/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f105.zig
deleted file mode 100644
index 4f9e7292f..000000000
--- a/port/stmicro/stm32/src/hals/STM32F103/clocks/clock_stm32f105.zig
+++ /dev/null
@@ -1,1166 +0,0 @@
-//NOTE: this clock tree is valid only for STM32F105/107 and XL density devices
-//NOTE: this file was manually generated from data coming from CubeMX, manual changes may be necessary
-
-const std = @import("std");
-const clock = @import("clocknodes.zig");
-const ClockNode = clock.ClockNode;
-const ClockNodeTypes = clock.ClockNodesTypes;
-const ClockState = clock.ClockState;
-const ClockError = clock.ClockError;
-
-pub const LSE_VALUEConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const HSE_VALUEConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const Prediv2Conf = enum {
-    RCC_HSE_PREDIV2_DIV1,
-    RCC_HSE_PREDIV2_DIV2,
-    RCC_HSE_PREDIV2_DIV3,
-    RCC_HSE_PREDIV2_DIV4,
-    RCC_HSE_PREDIV2_DIV5,
-    RCC_HSE_PREDIV2_DIV6,
-    RCC_HSE_PREDIV2_DIV7,
-    RCC_HSE_PREDIV2_DIV8,
-    RCC_HSE_PREDIV2_DIV9,
-    RCC_HSE_PREDIV2_DIV10,
-    RCC_HSE_PREDIV2_DIV11,
-    RCC_HSE_PREDIV2_DIV12,
-    RCC_HSE_PREDIV2_DIV13,
-    RCC_HSE_PREDIV2_DIV14,
-    RCC_HSE_PREDIV2_DIV15,
-    RCC_HSE_PREDIV2_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HSE_PREDIV2_DIV12 => 12,
-            .RCC_HSE_PREDIV2_DIV16 => 16,
-            .RCC_HSE_PREDIV2_DIV1 => 1,
-            .RCC_HSE_PREDIV2_DIV6 => 6,
-            .RCC_HSE_PREDIV2_DIV9 => 9,
-            .RCC_HSE_PREDIV2_DIV15 => 15,
-            .RCC_HSE_PREDIV2_DIV3 => 3,
-            .RCC_HSE_PREDIV2_DIV5 => 5,
-            .RCC_HSE_PREDIV2_DIV4 => 4,
-            .RCC_HSE_PREDIV2_DIV13 => 13,
-            .RCC_HSE_PREDIV2_DIV7 => 7,
-            .RCC_HSE_PREDIV2_DIV10 => 10,
-            .RCC_HSE_PREDIV2_DIV2 => 2,
-            .RCC_HSE_PREDIV2_DIV11 => 11,
-            .RCC_HSE_PREDIV2_DIV8 => 8,
-            .RCC_HSE_PREDIV2_DIV14 => 14,
-        };
-    }
-};
-pub const PLL2MulConf = enum {
-    RCC_PLL2_MUL8,
-    RCC_PLL2_MUL9,
-    RCC_PLL2_MUL10,
-    RCC_PLL2_MUL11,
-    RCC_PLL2_MUL12,
-    RCC_PLL2_MUL13,
-    RCC_PLL2_MUL14,
-    RCC_PLL2_MUL16,
-    RCC_PLL2_MUL20,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_PLL2_MUL20 => 20,
-            .RCC_PLL2_MUL16 => 16,
-            .RCC_PLL2_MUL10 => 10,
-            .RCC_PLL2_MUL8 => 8,
-            .RCC_PLL2_MUL14 => 14,
-            .RCC_PLL2_MUL12 => 12,
-            .RCC_PLL2_MUL11 => 11,
-            .RCC_PLL2_MUL9 => 9,
-            .RCC_PLL2_MUL13 => 13,
-        };
-    }
-};
-pub const PLL3MulConf = enum {
-    RCC_PLLI2S_MUL8,
-    RCC_PLLI2S_MUL9,
-    RCC_PLLI2S_MUL10,
-    RCC_PLLI2S_MUL11,
-    RCC_PLLI2S_MUL12,
-    RCC_PLLI2S_MUL13,
-    RCC_PLLI2S_MUL14,
-    RCC_PLLI2S_MUL16,
-    RCC_PLLI2S_MUL20,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_PLLI2S_MUL14 => 14,
-            .RCC_PLLI2S_MUL11 => 11,
-            .RCC_PLLI2S_MUL9 => 9,
-            .RCC_PLLI2S_MUL8 => 8,
-            .RCC_PLLI2S_MUL13 => 13,
-            .RCC_PLLI2S_MUL20 => 20,
-            .RCC_PLLI2S_MUL12 => 12,
-            .RCC_PLLI2S_MUL10 => 10,
-            .RCC_PLLI2S_MUL16 => 16,
-        };
-    }
-};
-pub const SYSCLKSourceConf = enum {
-    RCC_SYSCLKSOURCE_HSI,
-    RCC_SYSCLKSOURCE_HSE,
-    RCC_SYSCLKSOURCE_PLLCLK,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const I2S2ClockSelectionConf = enum {
-    RCC_I2S2CLKSOURCE_SYSCLK,
-    RCC_I2S2CLKSOURCE_PLLI2S_VCO,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const I2S3ClockSelectionConf = enum {
-    RCC_I2S3CLKSOURCE_SYSCLK,
-    RCC_I2S3CLKSOURCE_PLLI2S_VCO,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const RTCClockSelectionConf = enum {
-    RCC_RTCCLKSOURCE_HSE_DIV128,
-    RCC_RTCCLKSOURCE_LSE,
-    RCC_RTCCLKSOURCE_LSI,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const RCC_MCOMult_Clock_Source_FROM_PLL3MULConf = enum {
-    RCC_MCO1SOURCE_PLL3CLK,
-    RCC_MCO1SOURCE_PLL3CLK_DIV2,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_MCO1SOURCE_PLL3CLK => 1,
-            .RCC_MCO1SOURCE_PLL3CLK_DIV2 => 2,
-        };
-    }
-};
-pub const RCC_MCOSourceConf = enum {
-    RCC_MCO1SOURCE_HSE,
-    RCC_MCO1SOURCE_HSI,
-    RCC_MCO1SOURCE_SYSCLK,
-    RCC_MCO1SOURCE_PLLCLK,
-    RCC_MCO1SOURCE_PLL2CLK,
-    MCOPLL3Div,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const AHBCLKDividerConf = enum {
-    RCC_SYSCLK_DIV1,
-    RCC_SYSCLK_DIV2,
-    RCC_SYSCLK_DIV4,
-    RCC_SYSCLK_DIV8,
-    RCC_SYSCLK_DIV16,
-    RCC_SYSCLK_DIV64,
-    RCC_SYSCLK_DIV128,
-    RCC_SYSCLK_DIV256,
-    RCC_SYSCLK_DIV512,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_SYSCLK_DIV64 => 64,
-            .RCC_SYSCLK_DIV2 => 2,
-            .RCC_SYSCLK_DIV512 => 512,
-            .RCC_SYSCLK_DIV16 => 16,
-            .RCC_SYSCLK_DIV1 => 1,
-            .RCC_SYSCLK_DIV4 => 4,
-            .RCC_SYSCLK_DIV8 => 8,
-            .RCC_SYSCLK_DIV256 => 256,
-            .RCC_SYSCLK_DIV128 => 128,
-        };
-    }
-};
-pub const TimSys_DivConf = enum {
-    SYSTICK_CLKSOURCE_HCLK,
-    SYSTICK_CLKSOURCE_HCLK_DIV8,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .SYSTICK_CLKSOURCE_HCLK => 1,
-            .SYSTICK_CLKSOURCE_HCLK_DIV8 => 8,
-        };
-    }
-};
-pub const APB1CLKDividerConf = enum {
-    RCC_HCLK_DIV1,
-    RCC_HCLK_DIV2,
-    RCC_HCLK_DIV4,
-    RCC_HCLK_DIV8,
-    RCC_HCLK_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HCLK_DIV16 => 16,
-            .RCC_HCLK_DIV2 => 2,
-            .RCC_HCLK_DIV8 => 8,
-            .RCC_HCLK_DIV4 => 4,
-            .RCC_HCLK_DIV1 => 1,
-        };
-    }
-};
-pub const APB2CLKDividerConf = enum {
-    RCC_HCLK_DIV1,
-    RCC_HCLK_DIV2,
-    RCC_HCLK_DIV4,
-    RCC_HCLK_DIV8,
-    RCC_HCLK_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HCLK_DIV16 => 16,
-            .RCC_HCLK_DIV2 => 2,
-            .RCC_HCLK_DIV8 => 8,
-            .RCC_HCLK_DIV4 => 4,
-            .RCC_HCLK_DIV1 => 1,
-        };
-    }
-};
-pub const ADCPrescConf = enum {
-    RCC_ADCPCLK2_DIV2,
-    RCC_ADCPCLK2_DIV4,
-    RCC_ADCPCLK2_DIV6,
-    RCC_ADCPCLK2_DIV8,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_ADCPCLK2_DIV6 => 6,
-            .RCC_ADCPCLK2_DIV8 => 8,
-            .RCC_ADCPCLK2_DIV2 => 2,
-            .RCC_ADCPCLK2_DIV4 => 4,
-        };
-    }
-};
-pub const Prediv1SourceConf = enum {
-    RCC_PREDIV1_SOURCE_HSE,
-    RCC_PREDIV1_SOURCE_PLL2,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const HSEDivPLLConf = enum {
-    RCC_HSE_PREDIV_DIV1,
-    RCC_HSE_PREDIV_DIV2,
-    RCC_HSE_PREDIV_DIV3,
-    RCC_HSE_PREDIV_DIV4,
-    RCC_HSE_PREDIV_DIV5,
-    RCC_HSE_PREDIV_DIV6,
-    RCC_HSE_PREDIV_DIV7,
-    RCC_HSE_PREDIV_DIV8,
-    RCC_HSE_PREDIV_DIV9,
-    RCC_HSE_PREDIV_DIV10,
-    RCC_HSE_PREDIV_DIV11,
-    RCC_HSE_PREDIV_DIV12,
-    RCC_HSE_PREDIV_DIV13,
-    RCC_HSE_PREDIV_DIV14,
-    RCC_HSE_PREDIV_DIV15,
-    RCC_HSE_PREDIV_DIV16,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_HSE_PREDIV_DIV16 => 16,
-            .RCC_HSE_PREDIV_DIV5 => 5,
-            .RCC_HSE_PREDIV_DIV14 => 14,
-            .RCC_HSE_PREDIV_DIV13 => 13,
-            .RCC_HSE_PREDIV_DIV8 => 8,
-            .RCC_HSE_PREDIV_DIV2 => 2,
-            .RCC_HSE_PREDIV_DIV10 => 10,
-            .RCC_HSE_PREDIV_DIV6 => 6,
-            .RCC_HSE_PREDIV_DIV9 => 9,
-            .RCC_HSE_PREDIV_DIV3 => 3,
-            .RCC_HSE_PREDIV_DIV15 => 15,
-            .RCC_HSE_PREDIV_DIV12 => 12,
-            .RCC_HSE_PREDIV_DIV11 => 11,
-            .RCC_HSE_PREDIV_DIV1 => 1,
-            .RCC_HSE_PREDIV_DIV4 => 4,
-            .RCC_HSE_PREDIV_DIV7 => 7,
-        };
-    }
-};
-pub const PLLSourceVirtualConf = enum {
-    RCC_PLLSOURCE_HSI_DIV2,
-    RCC_PLLSOURCE_HSE,
-
-    pub fn get(self: @This()) usize {
-        return @intFromEnum(self);
-    }
-};
-pub const PLLMULConf = enum {
-    RCC_PLL_MUL4,
-    RCC_PLL_MUL5,
-    RCC_PLL_MUL6,
-    RCC_PLL_MUL6_5,
-    RCC_PLL_MUL7,
-    RCC_PLL_MUL8,
-    RCC_PLL_MUL9,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_PLL_MUL7 => 7,
-            .RCC_PLL_MUL9 => 9,
-            .RCC_PLL_MUL6_5 => 6.5,
-            .RCC_PLL_MUL6 => 6,
-            .RCC_PLL_MUL5 => 5,
-            .RCC_PLL_MUL4 => 4,
-            .RCC_PLL_MUL8 => 8,
-        };
-    }
-};
-pub const USBPrescalerConf = enum {
-    RCC_USBCLKSOURCE_PLL_DIV2,
-    RCC_USBCLKSOURCE_PLL_DIV3,
-    pub fn get(self: @This()) f32 {
-        return switch (self) {
-            .RCC_USBCLKSOURCE_PLL_DIV2 => 2,
-            .RCC_USBCLKSOURCE_PLL_DIV3 => 3,
-        };
-    }
-};
-pub const HSE_TimeoutConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const LSE_TimeoutConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const HSICalibrationValueConf = enum(u32) {
-    _,
-    pub fn get(num: @This()) f32 {
-        const val: u32 = @intFromEnum(num);
-        return @as(f32, @floatFromInt(val));
-    }
-};
-pub const Config = struct {
-    LSEOSC: ?LSE_VALUEConf = null,
-    HSEOSC: ?HSE_VALUEConf = null,
-    Prediv2: ?Prediv2Conf = null,
-    PLL2Mul: ?PLL2MulConf = null,
-    PLL3Mul: ?PLL3MulConf = null,
-    SysClkSource: ?SYSCLKSourceConf = null,
-    I2S2Mult: ?I2S2ClockSelectionConf = null,
-    I2S3Mult: ?I2S3ClockSelectionConf = null,
-    RTCClkSource: ?RTCClockSelectionConf = null,
-    MCOPLL3Div: ?RCC_MCOMult_Clock_Source_FROM_PLL3MULConf = null,
-    MCOMult: ?RCC_MCOSourceConf = null,
-    AHBPrescaler: ?AHBCLKDividerConf = null,
-    TimSysPresc: ?TimSys_DivConf = null,
-    APB1Prescaler: ?APB1CLKDividerConf = null,
-    APB2Prescaler: ?APB2CLKDividerConf = null,
-    ADCprescaler: ?ADCPrescConf = null,
-    Prediv1Source: ?Prediv1SourceConf = null,
-    PreDiv1: ?HSEDivPLLConf = null,
-    PLLSource: ?PLLSourceVirtualConf = null,
-    PLLMUL: ?PLLMULConf = null,
-    USBPrescaler: ?USBPrescalerConf = null,
-    HSE_Timeout: ?HSE_TimeoutConf = null,
-    LSE_Timeout: ?LSE_TimeoutConf = null,
-    HSICalibrationValue: ?HSICalibrationValueConf = null,
-};
-
-pub const ConfigWithRef = struct {
-    LSE_VALUE: ?LSE_VALUEConf = null,
-    HSE_VALUE: ?HSE_VALUEConf = null,
-    Prediv2: ?Prediv2Conf = null,
-    PLL2Mul: ?PLL2MulConf = null,
-    PLL3Mul: ?PLL3MulConf = null,
-    SYSCLKSource: ?SYSCLKSourceConf = null,
-    I2S2ClockSelection: ?I2S2ClockSelectionConf = null,
-    I2S3ClockSelection: ?I2S3ClockSelectionConf = null,
-    RTCClockSelection: ?RTCClockSelectionConf = null,
-    RCC_MCOMult_Clock_Source_FROM_PLL3MUL: ?RCC_MCOMult_Clock_Source_FROM_PLL3MULConf = null,
-    RCC_MCOSource: ?RCC_MCOSourceConf = null,
-    AHBCLKDivider: ?AHBCLKDividerConf = null,
-    TimSys_Div: ?TimSys_DivConf = null,
-    APB1CLKDivider: ?APB1CLKDividerConf = null,
-    APB2CLKDivider: ?APB2CLKDividerConf = null,
-    ADCPresc: ?ADCPrescConf = null,
-    Prediv1Source: ?Prediv1SourceConf = null,
-    HSEDivPLL: ?HSEDivPLLConf = null,
-    PLLSourceVirtual: ?PLLSourceVirtualConf = null,
-    PLLMUL: ?PLLMULConf = null,
-    USBPrescaler: ?USBPrescalerConf = null,
-    HSE_Timeout: ?HSE_TimeoutConf = null,
-    LSE_Timeout: ?LSE_TimeoutConf = null,
-    HSICalibrationValue: ?HSICalibrationValueConf = null,
-    pub fn into_config(self: *const ConfigWithRef) Config {
-        return .{
-            .LSEOSC = self.LSE_VALUE,
-            .HSEOSC = self.HSE_VALUE,
-            .Prediv2 = self.Prediv2,
-            .PLL2Mul = self.PLL2Mul,
-            .PLL3Mul = self.PLL3Mul,
-            .SysClkSource = self.SYSCLKSource,
-            .I2S2Mult = self.I2S2ClockSelection,
-            .I2S3Mult = self.I2S3ClockSelection,
-            .RTCClkSource = self.RTCClockSelection,
-            .MCOPLL3Div = self.RCC_MCOMult_Clock_Source_FROM_PLL3MUL,
-            .MCOMult = self.RCC_MCOSource,
-            .AHBPrescaler = self.AHBCLKDivider,
-            .TimSysPresc = self.TimSys_Div,
-            .APB1Prescaler = self.APB1CLKDivider,
-            .APB2Prescaler = self.APB2CLKDivider,
-            .ADCprescaler = self.ADCPresc,
-            .Prediv1Source = self.Prediv1Source,
-            .PreDiv1 = self.HSEDivPLL,
-            .PLLSource = self.PLLSourceVirtual,
-            .PLLMUL = self.PLLMUL,
-            .USBPrescaler = self.USBPrescaler,
-            .HSE_Timeout = self.HSE_Timeout,
-            .LSE_Timeout = self.LSE_Timeout,
-            .HSICalibrationValue = self.HSICalibrationValue,
-        };
-    }
-};
-
-pub const ClockTree = struct {
-    const this = @This();
-
-    HSIRC: ClockNode,
-    FLITFCLKoutput: ClockNode,
-    HSIDivPLL: ClockNode,
-    LSIRC: ClockNode,
-    LSEOSC: ClockNode,
-    HSEOSC: ClockNode,
-    Prediv2: ClockNode,
-    Prediv2output: ClockNode,
-    PLL2Mul: ClockNode,
-    PLL2VCOMul2: ClockNode,
-    PLL2VCOoutput: ClockNode,
-    PLL2CLKoutput: ClockNode,
-    PLL3Mul: ClockNode,
-    PLL3VCOMul2: ClockNode,
-    PLL3VCOoutput: ClockNode,
-    PLL3CLKoutput: ClockNode,
-    SysClkSource: ClockNode,
-    SysCLKOutput: ClockNode,
-    I2S2Mult: ClockNode,
-    I2S2Output: ClockNode,
-    I2S3Mult: ClockNode,
-    I2S3Output: ClockNode,
-    HSERTCDevisor: ClockNode,
-    RTCClkSource: ClockNode,
-    RTCOutput: ClockNode,
-    IWDGOutput: ClockNode,
-    MCOPLL3Div: ClockNode,
-    MCOMultDivisor: ClockNode,
-    MCOMult: ClockNode,
-    MCOoutput: ClockNode,
-    AHBPrescaler: ClockNode,
-    AHBOutput: ClockNode,
-    HCLKOutput: ClockNode,
-    FCLKCortexOutput: ClockNode,
-    TimSysPresc: ClockNode,
-    TimSysOutput: ClockNode,
-    APB1Prescaler: ClockNode,
-    APB1Output: ClockNode,
-    TimPrescalerAPB1: ClockNode,
-    TimPrescOut1: ClockNode,
-    APB2Prescaler: ClockNode,
-    APB2Output: ClockNode,
-    TimPrescalerAPB2: ClockNode,
-    TimPrescOut2: ClockNode,
-    ADCprescaler: ClockNode,
-    ADCoutput: ClockNode,
-    Prediv1Source: ClockNode,
-    PreDiv1: ClockNode,
-    PLLSource: ClockNode,
-    VCO2output: ClockNode,
-    PLLMUL: ClockNode,
-    PLLVCOMul2: ClockNode,
-    USBPrescaler: ClockNode,
-    USBoutput: ClockNode,
-    HSE_Timeout: ClockNodeTypes,
-    LSE_Timeout: ClockNodeTypes,
-    HSICalibrationValue: ClockNodeTypes,
-
-    pub fn init_comptime(comptime config: Config) this {
-        const HSIRCval = ClockNodeTypes{
-            .source = .{ .value = 8000000 },
-        };
-        const HSIRC: ClockNode = .{
-            .name = "HSIRC",
-            .Nodetype = HSIRCval,
-        };
-        const FLITFCLKoutputval = ClockNodeTypes{ .output = null };
-        const FLITFCLKoutput: ClockNode = .{
-            .name = "FLITFCLKoutput",
-            .Nodetype = FLITFCLKoutputval,
-            .parents = &[_]*const ClockNode{&HSIRC},
-        };
-        const HSIDivPLLval = ClockNodeTypes{
-            .div = .{ .value = 2 },
-        };
-        const HSIDivPLL: ClockNode = .{
-            .name = "HSIDivPLL",
-            .Nodetype = HSIDivPLLval,
-            .parents = &[_]*const ClockNode{&HSIRC},
-        };
-        const LSIRCval = ClockNodeTypes{
-            .source = .{ .value = 40000 },
-        };
-        const LSIRC: ClockNode = .{
-            .name = "LSIRC",
-            .Nodetype = LSIRCval,
-        };
-        const LSEOSCval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.LSEOSC) |val| val.get() else 32768,
-                .limit = .{ .max = 1000000, .min = 0 },
-            },
-        };
-        const LSEOSC: ClockNode = .{
-            .name = "LSEOSC",
-            .Nodetype = LSEOSCval,
-        };
-        const HSEOSCval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSEOSC) |val| val.get() else 8000000,
-                .limit = .{ .max = 25000000, .min = 3000000 },
-            },
-        };
-        const HSEOSC: ClockNode = .{
-            .name = "HSEOSC",
-            .Nodetype = HSEOSCval,
-        };
-        const Prediv2val = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.Prediv2) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const Prediv2: ClockNode = .{
-            .name = "Prediv2",
-            .Nodetype = Prediv2val,
-            .parents = &[_]*const ClockNode{&HSEOSC},
-        };
-        const Prediv2outputval = ClockNodeTypes{ .output = null };
-        const Prediv2output: ClockNode = .{
-            .name = "Prediv2output",
-            .Nodetype = Prediv2outputval,
-            .parents = &[_]*const ClockNode{&Prediv2},
-        };
-        const PLL2Mulval = ClockNodeTypes{ .mul = .{
-            .value = inner: {
-                if (config.PLL2Mul) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 8;
-                }
-            },
-        } };
-        const PLL2Mul: ClockNode = .{
-            .name = "PLL2Mul",
-            .Nodetype = PLL2Mulval,
-            .parents = &[_]*const ClockNode{&Prediv2output},
-        };
-        const PLL2VCOMul2val = ClockNodeTypes{
-            .mul = .{ .value = 2 },
-        };
-        const PLL2VCOMul2: ClockNode = .{
-            .name = "PLL2VCOMul2",
-            .Nodetype = PLL2VCOMul2val,
-            .parents = &[_]*const ClockNode{&PLL2Mul},
-        };
-        const PLL2VCOoutputval = ClockNodeTypes{ .output = null };
-        const PLL2VCOoutput: ClockNode = .{
-            .name = "PLL2VCOoutput",
-            .Nodetype = PLL2VCOoutputval,
-            .parents = &[_]*const ClockNode{&PLL2VCOMul2},
-        };
-        const PLL2CLKoutputval = ClockNodeTypes{ .output = null };
-        const PLL2CLKoutput: ClockNode = .{
-            .name = "PLL2CLKoutput",
-            .Nodetype = PLL2CLKoutputval,
-            .parents = &[_]*const ClockNode{&PLL2Mul},
-        };
-        const PLL3Mulval = ClockNodeTypes{ .mul = .{
-            .value = inner: {
-                if (config.PLL3Mul) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 8;
-                }
-            },
-        } };
-        const PLL3Mul: ClockNode = .{
-            .name = "PLL3Mul",
-            .Nodetype = PLL3Mulval,
-            .parents = &[_]*const ClockNode{&Prediv2output},
-        };
-        const PLL3VCOMul2val = ClockNodeTypes{
-            .mul = .{ .value = 2 },
-        };
-        const PLL3VCOMul2: ClockNode = .{
-            .name = "PLL3VCOMul2",
-            .Nodetype = PLL3VCOMul2val,
-            .parents = &[_]*const ClockNode{&PLL3Mul},
-        };
-        const PLL3VCOoutputval = ClockNodeTypes{ .output = null };
-        const PLL3VCOoutput: ClockNode = .{
-            .name = "PLL3VCOoutput",
-            .Nodetype = PLL3VCOoutputval,
-            .parents = &[_]*const ClockNode{&PLL3VCOMul2},
-        };
-        const PLL3CLKoutputval = ClockNodeTypes{ .output = null };
-        const PLL3CLKoutput: ClockNode = .{
-            .name = "PLL3CLKoutput",
-            .Nodetype = PLL3CLKoutputval,
-            .parents = &[_]*const ClockNode{&PLL3Mul},
-        };
-        const Prediv1Sourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.Prediv1Source) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const Prediv1Source: ClockNode = .{
-            .name = "Prediv1Source",
-            .Nodetype = Prediv1Sourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSEOSC,
-                &PLL2CLKoutput,
-            },
-        };
-        const PreDiv1val = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.PreDiv1) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const PreDiv1: ClockNode = .{
-            .name = "PreDiv1",
-            .Nodetype = PreDiv1val,
-            .parents = &[_]*const ClockNode{&Prediv1Source},
-        };
-        const PLLSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.PLLSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const PLLSource: ClockNode = .{
-            .name = "PLLSource",
-            .Nodetype = PLLSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSIDivPLL,
-                &PreDiv1,
-            },
-        };
-        const VCO2outputval = ClockNodeTypes{ .output = null };
-        const VCO2output: ClockNode = .{
-            .name = "VCO2output",
-            .Nodetype = VCO2outputval,
-            .parents = &[_]*const ClockNode{&PLLSource},
-        };
-        const PLLMULval = ClockNodeTypes{ .mul = .{
-            .value = inner: {
-                if (config.PLLMUL) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 4;
-                }
-            },
-        } };
-        const PLLMUL: ClockNode = .{
-            .name = "PLLMUL",
-            .Nodetype = PLLMULval,
-            .parents = &[_]*const ClockNode{&VCO2output},
-        };
-        const SysClkSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.SysClkSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const SysClkSource: ClockNode = .{
-            .name = "SysClkSource",
-            .Nodetype = SysClkSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSIRC,
-                &HSEOSC,
-                &PLLMUL,
-            },
-        };
-        const SysCLKOutputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const SysCLKOutput: ClockNode = .{
-            .name = "SysCLKOutput",
-            .Nodetype = SysCLKOutputval,
-            .parents = &[_]*const ClockNode{&SysClkSource},
-        };
-        const I2S2Multval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.I2S2Mult) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const I2S2Mult: ClockNode = .{
-            .name = "I2S2Mult",
-            .Nodetype = I2S2Multval,
-
-            .parents = &[_]*const ClockNode{
-                &SysCLKOutput,
-                &PLL3VCOoutput,
-            },
-        };
-        const I2S2Outputval = ClockNodeTypes{ .output = null };
-        const I2S2Output: ClockNode = .{
-            .name = "I2S2Output",
-            .Nodetype = I2S2Outputval,
-            .parents = &[_]*const ClockNode{&I2S2Mult},
-        };
-        const I2S3Multval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.I2S3Mult) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 0;
-                }
-            },
-        };
-        const I2S3Mult: ClockNode = .{
-            .name = "I2S3Mult",
-            .Nodetype = I2S3Multval,
-
-            .parents = &[_]*const ClockNode{
-                &SysCLKOutput,
-                &PLL3VCOoutput,
-            },
-        };
-        const I2S3Outputval = ClockNodeTypes{ .output = null };
-        const I2S3Output: ClockNode = .{
-            .name = "I2S3Output",
-            .Nodetype = I2S3Outputval,
-            .parents = &[_]*const ClockNode{&I2S3Mult},
-        };
-        const HSERTCDevisorval = ClockNodeTypes{
-            .div = .{ .value = 128 },
-        };
-        const HSERTCDevisor: ClockNode = .{
-            .name = "HSERTCDevisor",
-            .Nodetype = HSERTCDevisorval,
-            .parents = &[_]*const ClockNode{&HSEOSC},
-        };
-        const RTCClkSourceval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.RTCClkSource) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 2;
-                }
-            },
-        };
-        const RTCClkSource: ClockNode = .{
-            .name = "RTCClkSource",
-            .Nodetype = RTCClkSourceval,
-
-            .parents = &[_]*const ClockNode{
-                &HSERTCDevisor,
-                &LSEOSC,
-                &LSIRC,
-            },
-        };
-        const RTCOutputval = ClockNodeTypes{ .output = null };
-        const RTCOutput: ClockNode = .{
-            .name = "RTCOutput",
-            .Nodetype = RTCOutputval,
-            .parents = &[_]*const ClockNode{&RTCClkSource},
-        };
-        const IWDGOutputval = ClockNodeTypes{ .output = null };
-        const IWDGOutput: ClockNode = .{
-            .name = "IWDGOutput",
-            .Nodetype = IWDGOutputval,
-            .parents = &[_]*const ClockNode{&LSIRC},
-        };
-        const MCOPLL3Divval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.MCOPLL3Div) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const MCOPLL3Div: ClockNode = .{
-            .name = "MCOPLL3Div",
-            .Nodetype = MCOPLL3Divval,
-            .parents = &[_]*const ClockNode{&PLL3CLKoutput},
-        };
-        const MCOMultDivisorval = ClockNodeTypes{
-            .div = .{ .value = 2 },
-        };
-        const MCOMultDivisor: ClockNode = .{
-            .name = "MCOMultDivisor",
-            .Nodetype = MCOMultDivisorval,
-            .parents = &[_]*const ClockNode{&PLLMUL},
-        };
-        const MCOMultval = ClockNodeTypes{
-            .multi = inner: {
-                if (config.MCOMult) |val| {
-                    switch (val) {
-                        .RCC_MCO1SOURCE_HSE,
-                        .RCC_MCO1SOURCE_HSI,
-                        .RCC_MCO1SOURCE_SYSCLK,
-                        .RCC_MCO1SOURCE_PLLCLK,
-                        .RCC_MCO1SOURCE_PLL2CLK,
-                        => {
-                            break :inner val.get();
-                        },
-                        else => {},
-                    }
-                    @compileError(std.fmt.comptimePrint("value {s} depends on an expression that returned false", .{@tagName(val)}));
-                } else {
-                    break :inner 2;
-                }
-            },
-        };
-        const MCOMult: ClockNode = .{
-            .name = "MCOMult",
-            .Nodetype = MCOMultval,
-
-            .parents = &[_]*const ClockNode{
-                &HSEOSC,
-                &HSIRC,
-                &SysCLKOutput,
-                &MCOMultDivisor,
-                &PLL2CLKoutput,
-                &MCOPLL3Div,
-            },
-        };
-        const MCOoutputval = ClockNodeTypes{
-            .output = .{ .max = 50000000, .min = 0 },
-        };
-        const MCOoutput: ClockNode = .{
-            .name = "MCOoutput",
-            .Nodetype = MCOoutputval,
-            .parents = &[_]*const ClockNode{&MCOMult},
-        };
-        const AHBPrescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.AHBPrescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const AHBPrescaler: ClockNode = .{
-            .name = "AHBPrescaler",
-            .Nodetype = AHBPrescalerval,
-            .parents = &[_]*const ClockNode{&SysCLKOutput},
-        };
-        const AHBOutputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const AHBOutput: ClockNode = .{
-            .name = "AHBOutput",
-            .Nodetype = AHBOutputval,
-            .parents = &[_]*const ClockNode{&AHBPrescaler},
-        };
-        const HCLKOutputval = ClockNodeTypes{ .output = null };
-        const HCLKOutput: ClockNode = .{
-            .name = "HCLKOutput",
-            .Nodetype = HCLKOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const FCLKCortexOutputval = ClockNodeTypes{ .output = null };
-        const FCLKCortexOutput: ClockNode = .{
-            .name = "FCLKCortexOutput",
-            .Nodetype = FCLKCortexOutputval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const TimSysPrescval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.TimSysPresc) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const TimSysPresc: ClockNode = .{
-            .name = "TimSysPresc",
-            .Nodetype = TimSysPrescval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const TimSysOutputval = ClockNodeTypes{ .output = null };
-        const TimSysOutput: ClockNode = .{
-            .name = "TimSysOutput",
-            .Nodetype = TimSysOutputval,
-            .parents = &[_]*const ClockNode{&TimSysPresc},
-        };
-        const APB1Prescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.APB1Prescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const APB1Prescaler: ClockNode = .{
-            .name = "APB1Prescaler",
-            .Nodetype = APB1Prescalerval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const APB1Outputval = ClockNodeTypes{
-            .output = .{ .max = 36000000, .min = 0 },
-        };
-        const APB1Output: ClockNode = .{
-            .name = "APB1Output",
-            .Nodetype = APB1Outputval,
-            .parents = &[_]*const ClockNode{&APB1Prescaler},
-        };
-        const TimPrescalerAPB1val = blk: {
-            if (APB1Prescalerval.num_val() == 1) {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 1 },
-                };
-            } else {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 2 },
-                };
-            }
-        };
-        const TimPrescalerAPB1: ClockNode = .{
-            .name = "TimPrescalerAPB1",
-            .Nodetype = TimPrescalerAPB1val,
-            .parents = &[_]*const ClockNode{&APB1Prescaler},
-        };
-        const TimPrescOut1val = ClockNodeTypes{ .output = null };
-        const TimPrescOut1: ClockNode = .{
-            .name = "TimPrescOut1",
-            .Nodetype = TimPrescOut1val,
-            .parents = &[_]*const ClockNode{&TimPrescalerAPB1},
-        };
-        const APB2Prescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.APB2Prescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 1;
-                }
-            },
-        } };
-        const APB2Prescaler: ClockNode = .{
-            .name = "APB2Prescaler",
-            .Nodetype = APB2Prescalerval,
-            .parents = &[_]*const ClockNode{&AHBOutput},
-        };
-        const APB2Outputval = ClockNodeTypes{
-            .output = .{ .max = 72000000, .min = 0 },
-        };
-        const APB2Output: ClockNode = .{
-            .name = "APB2Output",
-            .Nodetype = APB2Outputval,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const TimPrescalerAPB2val = blk: {
-            if (APB2Prescalerval.num_val() == 1) {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 1 },
-                };
-            } else {
-                break :blk ClockNodeTypes{
-                    .mul = .{ .value = 2 },
-                };
-            }
-        };
-        const TimPrescalerAPB2: ClockNode = .{
-            .name = "TimPrescalerAPB2",
-            .Nodetype = TimPrescalerAPB2val,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const TimPrescOut2val = ClockNodeTypes{ .output = null };
-        const TimPrescOut2: ClockNode = .{
-            .name = "TimPrescOut2",
-            .Nodetype = TimPrescOut2val,
-            .parents = &[_]*const ClockNode{&TimPrescalerAPB2},
-        };
-        const ADCprescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.ADCprescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 2;
-                }
-            },
-        } };
-        const ADCprescaler: ClockNode = .{
-            .name = "ADCprescaler",
-            .Nodetype = ADCprescalerval,
-            .parents = &[_]*const ClockNode{&APB2Prescaler},
-        };
-        const ADCoutputval = ClockNodeTypes{
-            .output = .{ .max = 14000000, .min = 0 },
-        };
-        const ADCoutput: ClockNode = .{
-            .name = "ADCoutput",
-            .Nodetype = ADCoutputval,
-            .parents = &[_]*const ClockNode{&ADCprescaler},
-        };
-        const PLLVCOMul2val = ClockNodeTypes{
-            .mul = .{ .value = 2 },
-        };
-        const PLLVCOMul2: ClockNode = .{
-            .name = "PLLVCOMul2",
-            .Nodetype = PLLVCOMul2val,
-            .parents = &[_]*const ClockNode{&PLLMUL},
-        };
-        const USBPrescalerval = ClockNodeTypes{ .div = .{
-            .value = inner: {
-                if (config.USBPrescaler) |val| {
-                    break :inner val.get();
-                } else {
-                    break :inner 3;
-                }
-            },
-        } };
-        const USBPrescaler: ClockNode = .{
-            .name = "USBPrescaler",
-            .Nodetype = USBPrescalerval,
-            .parents = &[_]*const ClockNode{&PLLVCOMul2},
-        };
-        const USBoutputval = ClockNodeTypes{
-            .output = .{ .max = 48120000, .min = 47880000 },
-        };
-        const USBoutput: ClockNode = .{
-            .name = "USBoutput",
-            .Nodetype = USBoutputval,
-            .parents = &[_]*const ClockNode{&USBPrescaler},
-        };
-        const HSE_Timeoutval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSE_Timeout) |val| val.get() else 100,
-                .limit = .{ .max = 4294967295, .min = 1 },
-            },
-        };
-        const LSE_Timeoutval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.LSE_Timeout) |val| val.get() else 5000,
-                .limit = .{ .max = 4294967295, .min = 1 },
-            },
-        };
-        const HSICalibrationValueval = ClockNodeTypes{
-            .source = .{
-                .value = if (config.HSICalibrationValue) |val| val.get() else 16,
-                .limit = .{ .max = 31, .min = 0 },
-            },
-        };
-        return .{
-            .HSIRC = HSIRC,
-            .FLITFCLKoutput = FLITFCLKoutput,
-            .HSIDivPLL = HSIDivPLL,
-            .LSIRC = LSIRC,
-            .LSEOSC = LSEOSC,
-            .HSEOSC = HSEOSC,
-            .Prediv2 = Prediv2,
-            .Prediv2output = Prediv2output,
-            .PLL2Mul = PLL2Mul,
-            .PLL2VCOMul2 = PLL2VCOMul2,
-            .PLL2VCOoutput = PLL2VCOoutput,
-            .PLL2CLKoutput = PLL2CLKoutput,
-            .PLL3Mul = PLL3Mul,
-            .PLL3VCOMul2 = PLL3VCOMul2,
-            .PLL3VCOoutput = PLL3VCOoutput,
-            .PLL3CLKoutput = PLL3CLKoutput,
-            .SysClkSource = SysClkSource,
-            .SysCLKOutput = SysCLKOutput,
-            .I2S2Mult = I2S2Mult,
-            .I2S2Output = I2S2Output,
-            .I2S3Mult = I2S3Mult,
-            .I2S3Output = I2S3Output,
-            .HSERTCDevisor = HSERTCDevisor,
-            .RTCClkSource = RTCClkSource,
-            .RTCOutput = RTCOutput,
-            .IWDGOutput = IWDGOutput,
-            .MCOPLL3Div = MCOPLL3Div,
-            .MCOMultDivisor = MCOMultDivisor,
-            .MCOMult = MCOMult,
-            .MCOoutput = MCOoutput,
-            .AHBPrescaler = AHBPrescaler,
-            .AHBOutput = AHBOutput,
-            .HCLKOutput = HCLKOutput,
-            .FCLKCortexOutput = FCLKCortexOutput,
-            .TimSysPresc = TimSysPresc,
-            .TimSysOutput = TimSysOutput,
-            .APB1Prescaler = APB1Prescaler,
-            .APB1Output = APB1Output,
-            .TimPrescalerAPB1 = TimPrescalerAPB1,
-            .TimPrescOut1 = TimPrescOut1,
-            .APB2Prescaler = APB2Prescaler,
-            .APB2Output = APB2Output,
-            .TimPrescalerAPB2 = TimPrescalerAPB2,
-            .TimPrescOut2 = TimPrescOut2,
-            .ADCprescaler = ADCprescaler,
-            .ADCoutput = ADCoutput,
-            .Prediv1Source = Prediv1Source,
-            .PreDiv1 = PreDiv1,
-            .PLLSource = PLLSource,
-            .VCO2output = VCO2output,
-            .PLLMUL = PLLMUL,
-            .PLLVCOMul2 = PLLVCOMul2,
-            .USBPrescaler = USBPrescaler,
-            .USBoutput = USBoutput,
-            .HSE_Timeout = HSE_Timeoutval,
-            .LSE_Timeout = LSE_Timeoutval,
-            .HSICalibrationValue = HSICalibrationValueval,
-        };
-    }
-
-    pub fn validate(comptime self: *const this) void {
-        _ = self.I2S2Output.get_comptime();
-        _ = self.I2S3Output.get_comptime();
-        _ = self.AHBOutput.get_comptime();
-        _ = self.HCLKOutput.get_comptime();
-        _ = self.FCLKCortexOutput.get_comptime();
-        _ = self.TimSysOutput.get_comptime();
-        _ = self.APB1Output.get_comptime();
-        _ = self.TimPrescOut1.get_comptime();
-        _ = self.APB2Output.get_comptime();
-        _ = self.TimPrescOut2.get_comptime();
-        _ = self.ADCoutput.get_comptime();
-        _ = self.USBoutput.get_comptime();
-    }
-};
diff --git a/port/stmicro/stm32/src/hals/STM32F103/clocks/clocknodes.zig b/port/stmicro/stm32/src/hals/STM32F103/clocks/clocknodes.zig
deleted file mode 100644
index ba180fa84..000000000
--- a/port/stmicro/stm32/src/hals/STM32F103/clocks/clocknodes.zig
+++ /dev/null
@@ -1,343 +0,0 @@
-const std = @import("std");
-const comptimePrint = std.fmt.comptimePrint;
-
-pub const Limit = struct {
-    min: f32 = 0,
-    max: f32,
-};
-
-pub const MUL = struct {
-    value: f32,
-    limit: ?Limit = null,
-    pub fn get(self: *const MUL, value: f32) f32 {
-        return value * self.value;
-    }
-};
-
-pub const Source = struct {
-    value: f32,
-    limit: ?Limit = null,
-};
-
-pub const MulFrac = struct {
-    value: f32,
-    limit: ?Limit = null,
-    pub fn get(self: *const MulFrac, value: f32, frac: f32, max: f32) f32 {
-        return value * (self.value + (frac / max));
-    }
-};
-
-pub const DIV = struct {
-    value: f32,
-    limit: ?Limit = null,
-    pub fn get(self: *const DIV, value: f32) f32 {
-        return value / self.value;
-    }
-};
-
-pub const ClockNodesTypes = union(enum) {
-    source: Source,
-    multi: usize,
-    mul: MUL,
-    mulfrac: MulFrac,
-    div: DIV,
-    output: ?Limit,
-    frac: Limit,
-
-    pub fn num_val(self: *const ClockNodesTypes) f32 {
-        return switch (self.*) {
-            ClockNodesTypes.source => |val| val.value,
-            ClockNodesTypes.multi => |val| @floatFromInt(val),
-            ClockNodesTypes.mulfrac => |val| val.value,
-            ClockNodesTypes.div => |val| val.value,
-            else => 0,
-        };
-    }
-};
-
-pub const ClockError = struct {
-    receive: f32 = 0,
-    limit: f32 = 0,
-    node: *const ClockNode,
-};
-
-///why f32 if the clock is given in Hz?
-///internally this structure is also used for fractional values and results of divisions
-///outputs can be converted to u32 without issues
-pub const ClockState = union(enum) {
-    Ok: f32,
-    Overflow: ClockError,
-    Underflow: ClockError,
-    NoParent: ClockError,
-};
-
-pub const ClockNode = struct {
-    const Self = *const @This();
-    name: []const u8,
-    Nodetype: ClockNodesTypes,
-    parents: ?[]const *const ClockNode = null,
-
-    pub fn get(self: Self) ClockState {
-        switch (self.Nodetype) {
-            .source => |node| {
-                return self.source(&node);
-            },
-            .multi => |node| {
-                return self.multi(node);
-            },
-            .mul => |node| {
-                return self.mul(&node);
-            },
-            .mulfrac => |node| {
-                return self.mulfrac(&node);
-            },
-            .div => |node| {
-                return self.div(&node);
-            },
-            .frac => |frac| {
-                return self.output(frac);
-            },
-            .output => |out_val| {
-                return self.output(out_val);
-            },
-        }
-    }
-
-    pub fn get_or_panic(self: Self) f32 {
-        switch (self.get()) {
-            .Ok => |val| return val,
-            else => @panic("invalid Clock configuration, use get_comptime for more details"),
-        }
-    }
-
-    pub fn get_value(self: Self) !f32 {
-        switch (self.get()) {
-            .Ok => |val| {
-                return val;
-            },
-            else => return error.InvalidOutput,
-        }
-    }
-
-    pub fn get_comptime(comptime self: Self) f32 {
-        const ret = comptime self.get();
-        switch (ret) {
-            .Ok => |val| return val,
-            else => |err| print_comptime_error(err),
-        }
-    }
-
-    pub fn get_parent(node: *const ClockNode) ?*const ClockNode {
-        if (node.parents) |parents| {
-            switch (node.Nodetype) {
-                .mul, .div, .mulfrac, .output => {
-                    return parents[0];
-                },
-                .multi => |val| {
-                    const index = val;
-                    if (parents.len > index) {
-                        return parents[index];
-                    }
-                },
-                else => {},
-            }
-        }
-        return null;
-    }
-
-    fn print_comptime_error(comptime err: ClockState) noreturn {
-        comptime {
-            const name = get_name_from_error(err);
-            const error_msg = switch (err) {
-                .NoParent => "No Parent list!",
-                .Overflow => |data| comptimePrint("Overflow | Received: {d} max: {d}", .{ data.receive, data.limit }),
-                .Underflow => |data| comptimePrint("Underflow | Received: {d} min: {d}", .{ data.receive, data.limit }),
-                else => unreachable,
-            };
-            const main_msg = comptimePrint("Error on node {s} => {s}\n", .{ name, error_msg });
-            switch (err) {
-                .NoParent => @compileError(main_msg),
-                .Overflow, .Underflow => |node| {
-                    const parent = get_parent(node.node) orelse unreachable;
-                    const tree = comptimePrint("TREE TRACE: {s} -> {s}: {d} <- ERROR\n\n", .{ print_tree(parent), node.node.name, node.receive });
-                    @compileError(comptimePrint("{s}{s}", .{ main_msg, tree }));
-                },
-                else => unreachable,
-            }
-        }
-    }
-
-    fn get_name_from_error(err: ClockState) []const u8 {
-        switch (err) {
-            .NoParent, .Overflow, .Underflow => |clk| {
-                return clk.node.name;
-            },
-            else => unreachable,
-        }
-    }
-
-    fn print_tree(comptime node: *const ClockNode) []const u8 {
-        if (get_parent(node)) |parent| {
-            return comptimePrint("{s} -> {s}", .{ print_tree(parent), print_node_info(node) });
-        }
-        return comptimePrint("ROOT -> {s}", .{print_node_info(node)});
-    }
-
-    fn print_node_info(comptime node: *const ClockNode) []const u8 {
-        const parent = get_parent(node) orelse node;
-        const value = parent.get_value() catch unreachable;
-
-        const type_data = switch (node.Nodetype) {
-            .div => |data| comptimePrint("{d}/{d}", .{ value, data.value }),
-            .mul => |data| comptimePrint("{d} * {d}", .{ value, data.value }),
-            .output, .source => comptimePrint("{d}", .{value}),
-            .multi => comptimePrint("{s}", .{parent.name}),
-            .mulfrac => comptimePrint("{d} * ({s})", .{ value, print_multi_frac(node) }),
-            else => unreachable,
-        };
-
-        return comptimePrint("|{s}: {s}|", .{ node.name, type_data });
-    }
-
-    fn print_multi_frac(node: *const ClockNode) []const u8 {
-        const mul_val = node.Nodetype.mulfrac.value;
-        const frac_val = node.parents.?[1].get_value() catch unreachable;
-        const frac_max = node.parents.?[1].Nodetype.frac.max;
-        return comptimePrint("{d} + ({d}/{d})", .{ mul_val, frac_val, frac_max });
-    }
-
-    fn limit_check(self: Self, value: f32, node_limit: ?Limit) ClockState {
-        if (node_limit) |limit| {
-            if (value > limit.max) {
-                return .{
-                    .Overflow = .{
-                        .node = self,
-                        .limit = limit.max,
-                        .receive = value,
-                    },
-                };
-            } else if (value < limit.min) {
-                return .{
-                    .Underflow = .{
-                        .node = self,
-                        .limit = limit.min,
-                        .receive = value,
-                    },
-                };
-            }
-        }
-
-        return .{ .Ok = value };
-    }
-
-    fn source(self: Self, node: *const Source) ClockState {
-        const value = node.value;
-        return self.limit_check(value, node.limit);
-    }
-
-    fn multi(self: Self, node: usize) ClockState {
-        if (self.parents) |nodes| {
-            if (nodes.len > node) {
-                return nodes[node].get();
-            }
-        }
-        return .{ .NoParent = .{ .node = self } };
-    }
-
-    fn mul(self: Self, node: *const MUL) ClockState {
-        if (self.parents) |parents| {
-            const value = node.value;
-            const limit = self.limit_check(value, node.limit);
-            switch (limit) {
-                .Ok => {
-                    const input = parents[0].get();
-                    switch (input) {
-                        .Ok => |from_input| {
-                            return .{ .Ok = node.get(from_input) };
-                        },
-                        else => {
-                            return input;
-                        },
-                    }
-                },
-                else => {
-                    return limit;
-                },
-            }
-        }
-
-        return .{ .NoParent = .{ .node = self } };
-    }
-
-    fn mulfrac(self: Self, node: *const MulFrac) ClockState {
-        if (self.parents) |parents| {
-            if (parents.len > 2) {
-                const value = node.value;
-                const limit = self.limit_check(value, node.limit);
-                switch (limit) {
-                    .Ok => {
-                        const input = parents[0].get();
-                        const frac = parents[1].get();
-
-                        switch (frac) {
-                            .Ok => |from_frac| {
-                                const frac_max = parents[1].Nodetype.frac.max;
-                                switch (input) {
-                                    .Ok => |from_input| {
-                                        return .{ .Ok = node.get(
-                                            from_input,
-                                            from_frac,
-                                            frac_max,
-                                        ) };
-                                    },
-                                    else => return input,
-                                }
-                            },
-                            else => return frac,
-                        }
-                    },
-                    else => return limit,
-                }
-            }
-        }
-        return .{ .NoParent = .{ .node = self } };
-    }
-
-    fn div(self: Self, node: *const DIV) ClockState {
-        if (self.parents) |parents| {
-            const value = node.value;
-            const limit = self.limit_check(value, node.limit);
-            switch (limit) {
-                .Ok => {
-                    const input = parents[0].get();
-                    switch (input) {
-                        .Ok => |from_input| {
-                            return .{ .Ok = node.get(from_input) };
-                        },
-                        else => {
-                            return input;
-                        },
-                    }
-                },
-                else => {
-                    return limit;
-                },
-            }
-        }
-
-        return .{ .NoParent = .{ .node = self } };
-    }
-
-    fn output(self: Self, limit: ?Limit) ClockState {
-        if (self.parents) |parents| {
-            const value = parents[0].get();
-            switch (value) {
-                .Ok => |ret| {
-                    return self.limit_check(ret, limit);
-                },
-                else => return value,
-            }
-        }
-        return .{ .NoParent = .{ .node = self } };
-    }
-};
diff --git a/port/stmicro/stm32/src/hals/STM32F103/clocks/readme.md b/port/stmicro/stm32/src/hals/STM32F103/clocks/readme.md
deleted file mode 100644
index abee33d31..000000000
--- a/port/stmicro/stm32/src/hals/STM32F103/clocks/readme.md
+++ /dev/null
@@ -1,12 +0,0 @@
-# Compile-Time Clock Configuration
-
-This is a **test** of a precise clock configuration method, using data collected directly from CubeMX.
-
-The goal is to enable any clock configuration with useful error messages for incorrect setups, similar to how CubeMX operates. Currently, only compile-time configurations are supported, but runtime configuration support is planned.
-
-At the moment, only the STM32F102/3/4xx series is being ported to microzig. However, most mainstream STM32 family chips have some level of configuration available. You can check the support status at: [ClockHelper-zig](https://github.com/RecursiveError/ClockHelper-zig).
-
-# Bugs and Feature Requests
-These files were generated automatically. Configuration errors or incomplete functionalities may exist. If you make manual modifications, consider opening an issue in the project's original repository. This can help improve support for other chips.
-
-
diff --git a/port/stmicro/stm32/src/hals/STM32F103/rcc.zig b/port/stmicro/stm32/src/hals/STM32F103/rcc.zig
index c17cfb7ff..15174f14b 100644
--- a/port/stmicro/stm32/src/hals/STM32F103/rcc.zig
+++ b/port/stmicro/stm32/src/hals/STM32F103/rcc.zig
@@ -1,23 +1,20 @@
-//NOTE: this file is only valid for densities: Low, Medium, High, and XL. Connectivity line devices are not supported in this version.
+//NOTE: this file is only valid for densities: Low, Medium and High. Connectivity/XL line devices are not supported in this version.
 //TODO: Add support for 105/107
+
 const std = @import("std");
+const ClockTree = @import("ClockTree").get_mcu_tree(microzig.config.chip_name);
 const microzig = @import("microzig");
-
-const find_clocktree = @import("util.zig").find_clock_tree;
-const ClockTree = find_clocktree(microzig.config.chip_name);
 const power = @import("power.zig");
 
 //expose only the configuration structs
 pub const Config = ClockTree.Config;
-pub const ConfigWithRef = ClockTree.ConfigWithRef;
-
 const flash_v1 = microzig.chip.types.peripherals.flash_f1;
 const flash = microzig.chip.peripherals.FLASH;
 const PLLMUL = microzig.chip.types.peripherals.rcc_f1.PLLMUL;
 const PLLSRC = microzig.chip.types.peripherals.rcc_f1.PLLSRC;
 const PLLXTPRE = microzig.chip.types.peripherals.rcc_f1.PLLXTPRE;
-const PRE = microzig.chip.types.peripherals.rcc_f1.PPRE;
-const HPRE = microzig.chip.types.peripherals.rcc_f1.HPRE;
+const PPRE = microzig.chip.types.peripherals.rcc_f1.PPRE; //apb prescaler
+const HPRE = microzig.chip.types.peripherals.rcc_f1.HPRE; // ahb prescaler
 const ADCPRE = microzig.chip.types.peripherals.rcc_f1.ADCPRE;
 const USBPRE = microzig.chip.types.peripherals.rcc_f1.USBPRE;
 const RTCSEL = microzig.chip.types.peripherals.rcc_f1.RTCSEL;
@@ -88,25 +85,6 @@ pub const ResetReason = enum {
     NRST,
 };
 
-pub const ClockOutputs = struct {
-    //system clock
-    SYS: u32 = 0,
-
-    //Bus Clocks
-    AHB: u32 = 0,
-    APB1: u32 = 0,
-    APB2: u32 = 0,
-
-    //Peripheral clocks
-    FSMC: u32 = 0,
-    SDIO: u32 = 0,
-    TimAPB1: u32 = 0,
-    TimAPB2: u32 = 0,
-    ADC: u32 = 0,
-    USB: u32 = 0,
-    RTC: u32 = 0,
-};
-
 pub const Bus = enum {
     // AHB, //AHB cannot be reset by software
     APB1,
@@ -114,94 +92,117 @@ pub const Bus = enum {
 };
 
 //default clock config
-var corrent_clocks: ClockOutputs = validate_clocks(.{});
+var current_clocks: ClockTree.Clock_Output = blk: {
+    const out = ClockTree.get_clocks(.{}) catch unreachable;
+    break :blk out.clock;
+};
 
 //NOTE: procedural style or loop through all elements of the struct?
 ///Configures the system clocks
 ///NOTE: to configure the backup domain clocks (RTC) it is necessary to enable it through the power
 ///register before configuring the clocks
-pub fn apply_clock(comptime config: ClockTree.Config) ClockInitError!void {
-    const clck = comptime validate_clocks(config);
+pub fn apply(comptime config: ClockTree.Config) ClockInitError!ClockTree.Clock_Output {
+    const out_data = comptime ClockTree.get_clocks(config) catch unreachable;
+    try apply_internal(out_data.config);
+    current_clocks = out_data.clock;
+    return out_data.clock;
+}
 
-    set_flash(clck.SYS);
+fn apply_internal(config: ClockTree.Config_Output) ClockInitError!void {
+    const latency: flash_v1.LATENCY = if (config.FLatency) |lat| @enumFromInt(@as(u3, @intFromEnum(lat))) else .WS0;
+    const prefetch = config.flags.PREFETCH_ENABLE;
+    const apb1: ?PPRE = if (config.APB1CLKDivider) |pre| @enumFromInt(@as(u3, @intFromEnum(pre))) else null;
+    const apb2: ?PPRE = if (config.APB2CLKDivider) |pre| @enumFromInt(@as(u3, @intFromEnum(pre))) else null;
+    const ahb: ?HPRE = if (config.AHBCLKDivider) |pre| @enumFromInt(@as(u4, @intFromEnum(pre))) else null;
+    const adc: ?ADCPRE = if (config.ADCPresc) |pre| @enumFromInt(@as(u2, @intFromEnum(pre))) else null;
+    const sys_clk: SW = if (config.SYSCLKSource) |src| @enumFromInt(@as(u2, @intFromEnum(src))) else .HSI;
+    //USB prescaler enum is inverted
+    const usb: ?USBPRE = if (config.USBPrescaler) |pre| @enumFromInt(@as(u1, @intFromEnum(pre)) ^ 1) else null;
 
-    //rest all clock configs
     secure_enable();
-    if (config.HSICalibrationValue) |val| {
-        config_HSI(@intFromEnum(val));
-    }
+    set_flash(latency, prefetch);
 
-    try config_PLL(config);
-    config_peripherals(config);
-    try config_RTC(config);
-    try config_system_clock(config);
-    config_MCO(config);
-    corrent_clocks = clck;
-}
+    if (config.flags.EnableHSE) {
+        const timout = if (config.HSE_Timout) |t| @as(usize, @intFromFloat(t)) else null;
+        try enable_hse(config.flags.HSEByPass, config.flags.EnbaleCSS, timout);
+    } else {
+        disable_hse();
+    }
 
-//check clocks and return all used outputs
-fn validate_clocks(comptime config: ClockTree.Config) ClockOutputs {
-    const tree_values = ClockTree.ClockTree.init_comptime(config);
-    var outputs: ClockOutputs = .{};
+    if (config.flags.PLLUsed) {
+        const source: PLLSRC = if (config.PLLSource) |src| @enumFromInt(@as(u1, @intFromEnum(src))) else PLLSRC.HSI_Div2;
+        const mul: PLLMUL = if (config.PLLMUL) |pre| @enumFromInt(@as(u4, @intFromEnum(pre))) else PLLMUL.Mul2;
+        const pre_div: PLLXTPRE = if (config.HSEDivPLL) |pre| @enumFromInt(@as(u1, @intFromEnum(pre))) else PLLXTPRE.Div1;
+        config_pll(source, mul, pre_div);
+        enable_pll();
+    } else {
+        disable_pll();
+    }
 
-    //checks if the clocks of the used peripherals are valid
-    outputs.SYS = @intFromFloat(tree_values.SysCLKOutput.get_comptime());
+    set_peripherals_prescaler(apb1, apb2, ahb, adc, usb);
 
-    outputs.AHB = @intFromFloat(tree_values.AHBOutput.get_comptime());
-    outputs.APB1 = @intFromFloat(tree_values.APB1Output.get_comptime());
-    outputs.APB2 = @intFromFloat(tree_values.APB2Output.get_comptime());
-    outputs.TimAPB1 = @intFromFloat(tree_values.TimPrescOut1.get_comptime());
-    outputs.TimAPB2 = @intFromFloat(tree_values.TimPrescOut2.get_comptime());
+    //BACKUP DOMAIN CLOCK CONFIG
 
-    if (config.MCOMult) |_| {
-        _ = tree_values.MCOoutput.get_comptime();
+    if (config.flags.EnableLSE) {
+        const timeout = if (config.LSE_Timout) |t| @as(usize, @intFromFloat(t)) else null;
+        const bypass = config.flags.LSEByPass;
+        try enable_lse(timeout, bypass);
+    } else {
+        disable_lse();
     }
 
-    if (config.USBPrescaler) |_| {
-        outputs.USB = @intFromFloat(tree_values.USBoutput.get_comptime());
-        if (config.PLLSource) |src| {
-            if (src == .RCC_PLLSOURCE_HSI_DIV2) {
-                @compileError("USB clock is not stable when PLL source is HSI");
+    set_lsi(config.flags.LSIUsed);
+
+    rtc_config: {
+        if (config.flags.RTCEnable) {
+            if (config.RTCClockSelection) |s| {
+                const source = switch (s) {
+                    .RCC_RTCCLKSOURCE_HSE_DIV128 => RTCSEL.HSE,
+                    .RCC_RTCCLKSOURCE_LSE => RTCSEL.LSE,
+                    .RCC_RTCCLKSOURCE_LSI => RTCSEL.LSI,
+                };
+                config_rtc(source);
+                break :rtc_config;
             }
         }
+        config_rtc(.DISABLE);
     }
 
-    if (config.ADCprescaler) |_| {
-        outputs.ADC = @intFromFloat(tree_values.ADCoutput.get_comptime());
+    mco_config: {
+        if (config.flags.MCOEnable) {
+            if (config.RCC_MCOSource) |src| {
+                const source: MCOSEL = switch (src) {
+                    .RCC_MCO1SOURCE_HSE => .HSE,
+                    .RCC_MCO1SOURCE_HSI => .HSI,
+                    .RCC_MCO1SOURCE_PLLCLK => .PLL,
+                    .RCC_MCO1SOURCE_SYSCLK => .SYS,
+                };
+                config_mco(source);
+                break :mco_config;
+            }
+        }
+        config_mco(.DISABLE);
     }
 
-    if (config.RTCClkSource) |_| {
-        outputs.RTC = @intFromFloat(tree_values.RTCOutput.get_comptime());
-    }
+    //SYSTEM CLOCK CONFIG
+    config_system_clock(sys_clk);
 
-    return outputs;
+    //in case of HSI not used, we have to disable it here
+    //becuse the system clock configuration 'secure_enable' enables it by default
+    if (config.HSICalibrationValue) |val| {
+        calib_hsi(@intFromFloat(val));
+    }
+    set_hsi(config.flags.HSIUsed);
 }
 
-fn set_flash(clock: u32) void {
-    if (clock <= 24_000_000) {
-        flash.ACR.modify(.{
-            .LATENCY = flash_v1.LATENCY.WS0,
-            .PRFTBE = 0,
-        });
-    } else if (clock <= 48_000_000) {
-        flash.ACR.modify(.{
-            .LATENCY = flash_v1.LATENCY.WS1,
-            .PRFTBE = 1,
-        });
-    } else {
-        flash.ACR.modify(.{
-            .LATENCY = flash_v1.LATENCY.WS2,
-            .PRFTBE = 1,
-        });
-    }
+pub inline fn set_flash(latency: flash_v1.LATENCY, prefetch: bool) void {
+    flash.ACR.modify_one("LATENCY", latency);
+    flash.ACR.modify_one("PRFTBE", @intFromBool(prefetch));
 }
 
 //force HSI Clock and clear any clock configs
-fn secure_enable() void {
-    rcc.CR.modify(.{ .HSION = 1 });
-    while (rcc.CR.read().HSIRDY != 1) {
-        asm volatile ("" ::: .{ .memory = true });
-    }
+pub fn secure_enable() void {
+    set_hsi(true);
 
     rcc.BDCR.raw = 0;
     rcc.CFGR.raw = 0;
@@ -217,9 +218,19 @@ fn secure_enable() void {
     });
 }
 
-fn config_HSI(value: usize) void {
+pub fn set_hsi(on: bool) void {
+    rcc.CR.modify(.{ .HSION = @intFromBool(on) });
+    if (on) {
+        while (rcc.CR.read().HSIRDY == 0) {
+            asm volatile ("" ::: .{ .memory = true });
+        }
+    }
+}
+
+///configure the HSI calibration value
+pub fn calib_hsi(calib: usize) void {
     //secure_enable has already started the HSE
-    const trim: u5 = @truncate(value);
+    const trim: u5 = @truncate(calib);
     rcc.CR.modify(.{ .HSITRIM = trim });
 
     //wait for the HSI to stabilize
@@ -228,167 +239,148 @@ fn config_HSI(value: usize) void {
     }
 }
 
-fn config_LSI() void {
-    rcc.CSR.modify(.{ .LSION = 1 });
-    while (rcc.CSR.read().LSIRDY == 0) {
-        asm volatile ("" ::: .{ .memory = true });
+fn set_lsi(on: bool) void {
+    rcc.CSR.modify(.{ .LSION = @intFromBool(on) });
+    if (on) {
+        while (rcc.CSR.read().LSIRDY == 0) {
+            asm volatile ("" ::: .{ .memory = true });
+        }
     }
 }
 
-fn config_HSE(comptime config: ClockTree.Config) ClockInitError!void {
-    rcc.CR.modify(.{ .HSEON = 1 });
+pub fn enable_hse(bypass: bool, css: bool, timeout: ?usize) ClockInitError!void {
+    const max_wait: u32 = blk: {
+        if (timeout) |val| {
+            if (val != 0) {
+                break :blk val;
+            }
+        }
+        break :blk std.math.maxInt(usize);
+    };
+    var ticks: usize = calc_wait_ticks(max_wait - 1);
 
-    const max_wait: u32 = if (config.HSE_Timeout) |val| @intFromEnum(val) else std.math.maxInt(u32);
-    var ticks: usize = 0;
+    rcc.CR.modify(.{
+        .HSEON = 1,
+        .HSEBYP = @intFromBool(bypass),
+        .CSSON = @intFromBool(css),
+    });
     while (rcc.CR.read().HSERDY == 0) {
-        if (ticks == max_wait - 1) return error.HSETimeout;
-        ticks += 1;
+        if (ticks == 0) return error.HSETimeout;
+        ticks -= 1;
         asm volatile ("" ::: .{ .memory = true });
     }
 }
 
-fn config_LSE(comptime config: ClockTree.Config) ClockInitError!void {
-    const max_wait: u32 = if (config.LSE_Timeout) |val| @intFromEnum(val) else std.math.maxInt(u32);
-    var ticks: usize = 0;
+pub inline fn disable_hse() void {
+    rcc.CR.modify(.{ .CSSON = 0 });
+    rcc.CR.modify(.{ .HSEON = 0 });
+}
+
+fn enable_lse(timeout: ?usize, bypass: bool) ClockInitError!void {
+    const max_wait: u32 = blk: {
+        if (timeout) |val| {
+            if (val != 0) {
+                break :blk val;
+            }
+        }
+        break :blk std.math.maxInt(u32);
+    };
+    var ticks: usize = calc_wait_ticks(max_wait - 1);
+
+    rcc.BDCR.modify_one("LSEBYP", @intFromBool(bypass));
     rcc.BDCR.modify(.{ .LSEON = 1 });
     while (rcc.BDCR.read().LSERDY == 0) {
-        if (ticks == max_wait - 1) return error.LSETimeout;
-        ticks += 1;
+        if (ticks == 0) return error.LSETimeout;
+        ticks -= 1;
         asm volatile ("" ::: .{ .memory = true });
     }
 }
 
-fn config_PLL(comptime config: ClockTree.Config) ClockInitError!void {
-    if (config.PLLSource) |src| {
-        const s: u1 = @intFromEnum(src);
-        const val: PLLSRC = @enumFromInt(s);
-        rcc.CFGR.modify(.{ .PLLSRC = val });
-        if (val == .HSE_Div_PREDIV) {
-            try config_HSE(config);
-        }
-    }
-
-    if (config.HSEDivPLL) |pre| {
-        const p: u1 = @intFromEnum(pre);
-        const val: PLLXTPRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .PLLXTPRE = val });
-    }
+pub inline fn disable_lse() void {
+    rcc.BDCR.modify(.{ .LSEON = 0 });
+}
 
-    if (config.PLLMUL) |pre| {
-        const p: u32 = @intFromEnum(pre);
-        const val: PLLMUL = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .PLLMUL = val });
-    }
+pub fn config_pll(source: PLLSRC, mul: PLLMUL, pre_div: PLLXTPRE) void {
+    rcc.CFGR.modify(.{ .PLLSRC = source });
+    rcc.CFGR.modify(.{ .PLLMUL = mul });
+    rcc.CFGR.modify(.{ .PLLXTPRE = pre_div });
 }
 
 //TODO: Add STM32F105/7 devices peri
-fn config_peripherals(comptime config: ClockTree.Config) void {
-    if (config.APB1Prescaler) |pre| {
-        const p: u32 = @intFromEnum(pre);
-        const val: PRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .PPRE1 = val });
+pub fn set_peripherals_prescaler(
+    apb1: ?PPRE,
+    apb2: ?PPRE,
+    ahb: ?HPRE,
+    adc: ?ADCPRE,
+    usb: ?USBPRE,
+) void {
+    if (apb1) |pre| {
+        rcc.CFGR.modify(.{ .PPRE1 = pre });
     }
 
-    if (config.APB2Prescaler) |pre| {
-        const p: u32 = @intFromEnum(pre);
-        const val: PRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .PPRE2 = val });
+    if (apb2) |pre| {
+        rcc.CFGR.modify(.{ .PPRE2 = pre });
     }
 
-    if (config.AHBPrescaler) |pre| {
-        const p: u32 = @intFromEnum(pre);
-        const val: HPRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .HPRE = val });
+    if (ahb) |pre| {
+        rcc.CFGR.modify(.{ .HPRE = pre });
     }
 
-    if (config.ADCprescaler) |pre| {
-        const p: u32 = @intFromEnum(pre);
-        const val: ADCPRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .ADCPRE = val });
+    if (adc) |pre| {
+        rcc.CFGR.modify(.{ .ADCPRE = pre });
     }
 
-    if (config.USBPrescaler) |pre| {
-        const p: u1 = switch (pre) {
-            .RCC_USBCLKSOURCE_PLL_DIV1_5 => 0,
-            .RCC_USBCLKSOURCE_PLL => 1,
-        };
-        const val: USBPRE = @enumFromInt(p);
-        rcc.CFGR.modify(.{ .USBPRE = val });
+    if (usb) |pre| {
+        rcc.CFGR.modify(.{ .USBPRE = pre });
     }
 }
 
-fn config_system_clock(comptime config: ClockTree.Config) ClockInitError!void {
-    if (config.SysClkSource) |src| {
-        const val: u2 = @intFromEnum(src);
-        const e_val: SW = @enumFromInt(val);
-        switch (val) {
-            1 => try config_HSE(config),
-            2 => init_pll(),
-            else => {},
-        }
-
-        rcc.CFGR.modify(.{ .SW = e_val });
-        while (true) {
-            const sws = rcc.CFGR.read().SWS;
-            if (sws == e_val) break;
-            asm volatile ("" ::: .{ .memory = true });
-        }
+fn config_system_clock(system_clock: SW) void {
+    rcc.CFGR.modify(.{ .SW = system_clock });
+    while (true) {
+        const sws = rcc.CFGR.read().SWS;
+        if (sws == system_clock) break;
+        asm volatile ("" ::: .{ .memory = true });
     }
 }
 
-fn init_pll() void {
+pub fn enable_pll() void {
     rcc.CR.modify(.{ .PLLON = 1 });
     while (rcc.CR.read().PLLRDY == 0) {
         asm volatile ("" ::: .{ .memory = true });
     }
 }
 
-fn config_RTC(comptime config: ClockTree.Config) ClockInitError!void {
-    if (config.RTCClkSource) |src| {
-        //enable backup domain
-        enable_clock(.PWR);
-        enable_clock(.BKP);
-        power.backup_domain_protection(false);
-
-        var rtcs: RTCSEL = .DISABLE;
-        switch (src) {
-            .RCC_RTCCLKSOURCE_HSE_DIV128 => {
-                rtcs = .HSE;
-                reset_backup_domain(); //HSE as RTC source requires full reset of the bkp domain
-                power.backup_domain_protection(false);
-                try config_HSE(config);
-            },
-            .RCC_RTCCLKSOURCE_LSE => {
-                rtcs = .LSE;
-                try config_LSE(config);
-            },
-            .RCC_RTCCLKSOURCE_LSI => {
-                rtcs = .LSI;
-                config_LSI();
-            },
-        }
+pub fn disable_pll() void {
+    rcc.CR.modify(.{ .PLLON = 0 });
+    while (rcc.CR.read().PLLRDY != 0) {
+        asm volatile ("" ::: .{ .memory = true });
+    }
+}
 
-        rcc.BDCR.modify(.{ .RTCSEL = rtcs });
-        power.backup_domain_protection(true);
+pub fn config_rtc(source: RTCSEL) void {
 
-        // Disable and reset clocks to avoid potential conflicts with the main application
-        disable_clock(.BKP);
-        reset_clock(.BKP);
-        disable_clock(.PWR);
-        reset_clock(.PWR);
+    //enable backup domain write acess
+    enable_clock(.PWR);
+    enable_clock(.BKP);
+    power.backup_domain_protection(false);
+    if (source == .HSE) {
+        reset_backup_domain(); //HSE as RTC source requires full reset of the bkp domain
+        power.backup_domain_protection(false);
     }
+
+    rcc.BDCR.modify(.{ .RTCSEL = source });
+    power.backup_domain_protection(true);
+
+    // Disable and reset clocks to avoid potential conflicts with the main application
+    disable_clock(.BKP);
+    reset_clock(.BKP);
+    disable_clock(.PWR);
+    reset_clock(.PWR);
 }
 
-fn config_MCO(comptime config: ClockTree.Config) void {
-    if (config.MCOMult) |src| {
-        const mco: MCOSEL = switch (src) {
-            .RCC_MCO1SOURCE_HSE => .HSE,
-            .RCC_MCO1SOURCE_HSI => .HSI,
-            .RCC_MCO1SOURCE_PLLCLK => .PLL,
-            .RCC_MCO1SOURCE_SYSCLK => .SYS,
-        };
-        rcc.CFGR.modify(.{ .MCOSEL = mco });
-    }
+pub fn config_mco(source: MCOSEL) void {
+    rcc.CFGR.modify(.{ .MCOSEL = source });
 }
 
 ///after the reset, the BDRD becomes read_only until access is released by the power register
@@ -403,7 +395,7 @@ pub fn reset_backup_domain() void {
 
 ///configure the power and clock registers before enabling the RTC
 ///this function also can be called from `rtc.enable()`
-pub fn enable_RTC(on: bool) void {
+pub fn enable_rtc(on: bool) void {
     rcc.BDCR.modify(.{ .RTCEN = @intFromBool(on) });
 }
 
@@ -530,7 +522,7 @@ pub fn set_clock(peri: RccPeriferals, state: u1) void {
         .BKP => rcc.APB1ENR.modify(.{ .BKPEN = state }),
         .PWR => rcc.APB1ENR.modify(.{ .PWREN = state }),
         .DAC => rcc.APB1ENR.modify(.{ .DACEN = state }), //F103xE
-        .RTC => enable_RTC(state != 0),
+        .RTC => enable_rtc(state != 0),
     }
 }
 
@@ -577,17 +569,17 @@ pub fn reset_bus(bus: Bus) void {
 //errors at comptime appear for peripherals manually configured like USB.
 ///if requests the clock of an unconfigured peripheral, 0 means error, != 0 means ok
 pub fn get_clock(comptime source: RccPeriferals) u32 {
-    return switch (source) {
+    return @intFromFloat(switch (source) {
         // AHB peripherals
         .DMA1,
         .DMA2,
         .SRAM,
         .FLASH,
         .CRC,
-        => corrent_clocks.AHB,
+        => current_clocks.AHBOutput,
 
-        .FSMC => corrent_clocks.FSMC,
-        .SDIO => corrent_clocks.SDIO,
+        .FSMC => current_clocks.FSMClkOutput,
+        .SDIO => current_clocks.SDIOClkOutput,
 
         // APB2 peripherals
         .AFIO,
@@ -600,16 +592,16 @@ pub fn get_clock(comptime source: RccPeriferals) u32 {
         .GPIOG,
         .SPI1,
         .USART1,
-        => corrent_clocks.APB2,
+        => current_clocks.APB2Prescaler,
 
-        .ADC1, .ADC2 => corrent_clocks.ADC,
+        .ADC1, .ADC2 => current_clocks.ADCoutput,
 
-        .TIM1 => corrent_clocks.TimAPB2,
+        .TIM1 => current_clocks.TimPrescalerAPB2,
 
         // APB1 peripherals
-        .TIM2, .TIM3, .TIM4, .TIM5, .TIM6, .TIM7 => corrent_clocks.TimAPB1,
+        .TIM2, .TIM3, .TIM4, .TIM5, .TIM6, .TIM7 => current_clocks.TimPrescalerAPB1,
 
-        .DAC => corrent_clocks.APB1,
+        .DAC => current_clocks.APB1Output,
 
         .WWDG,
         .SPI2,
@@ -623,13 +615,19 @@ pub fn get_clock(comptime source: RccPeriferals) u32 {
         .CAN,
         .BKP,
         .PWR,
-        => corrent_clocks.APB1,
+        => current_clocks.APB1Output,
 
-        .USB => corrent_clocks.USB,
-        .RTC => corrent_clocks.RTC,
-    };
+        .USB => current_clocks.USBoutput,
+        .RTC => current_clocks.RTCOutput,
+    });
 }
 
 pub inline fn get_sys_clk() u32 {
-    return corrent_clocks.SYS;
+    return @intFromFloat(current_clocks.SysCLKOutput);
+}
+
+inline fn calc_wait_ticks(val: usize) usize {
+    const corrent_clock: usize = @intFromFloat(current_clocks.SysCLKOutput);
+    const ms_per_tick = corrent_clock / 1000;
+    return ms_per_tick * val;
 }
diff --git a/port/stmicro/stm32/src/hals/STM32F103/rtc.zig b/port/stmicro/stm32/src/hals/STM32F103/rtc.zig
index c4d6bd747..5d8ba7ecc 100644
--- a/port/stmicro/stm32/src/hals/STM32F103/rtc.zig
+++ b/port/stmicro/stm32/src/hals/STM32F103/rtc.zig
@@ -5,7 +5,7 @@ const rtc = microzig.chip.peripherals.RTC;
 ///enable the RTC clock.
 ///this function is the same as `hal.rcc.enable_RTC()`.
 ///it is here for convenience.
-pub const enable = rcc.enable_RTC;
+pub const enable = rcc.enable_rtc;
 pub const is_running = rcc.rtc_running;
 
 ///RTC clock source is selected in the clock configs