diff --git a/examples_v30x/pll_clock_test/HSI_PLL.png b/examples_v30x/pll_clock_test/HSI_PLL.png
new file mode 100644
index 00000000..13bfee65
Binary files /dev/null and b/examples_v30x/pll_clock_test/HSI_PLL.png differ
diff --git a/examples_v30x/pll_clock_test/Makefile b/examples_v30x/pll_clock_test/Makefile
new file mode 100644
index 00000000..c04099fb
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+++ b/examples_v30x/pll_clock_test/Makefile
@@ -0,0 +1,12 @@
+all : flash
+
+TARGET:=pll_clock_test
+TARGET_MCU:=CH32V303
+TARGET_MCU_PACKAGE:=CH32V303
+
+include ../../ch32fun/ch32fun.mk
+
+flash : cv_flash
+clean : cv_clean
+
+
diff --git a/examples_v30x/pll_clock_test/README.md b/examples_v30x/pll_clock_test/README.md
new file mode 100644
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+++ b/examples_v30x/pll_clock_test/README.md
@@ -0,0 +1,22 @@
+# DMA ADC & op-amp example
+Simple example that demonstrates how to configure different PLL multipliers
+for the HSI clock source.
+
+## In order to change the PLL multipler value
+- first switch the peripheral clock to HSI.
+- turn off PLL, set the PLL multiplier value, and turn on PLL
+- finally, switch the peripheral clock back to use PLL
+
+## Descriptions
+This example cycles through different PLLMUL[3:0] values 0 to 15.
+Depending on what chip you are using the PLLMUL value represents different multipliers.
+For example, CH32V30x_D8 PLLMUL = 0 = PLL input clock * 2
+whereas, CH32V30x_D8C PLLMUL = 0 = PLL input clock * 18
+Since the PLL input clock changes without any adjustment to the Delay_Ms function
+The delay time will change based on the PLL multiplier value.
+
+The HSI clock source starts at 8MHz
+min_multiplier 8MHz * 2 = 16MHz (uses about 2.5mA)
+max_multiplier: 8Mhz * 18 = 144MHz (uses about 17.5mA)
+
+![Screenshot](HSI_PLL.png)
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diff --git a/examples_v30x/pll_clock_test/funconfig.h b/examples_v30x/pll_clock_test/funconfig.h
new file mode 100644
index 00000000..18486fdd
--- /dev/null
+++ b/examples_v30x/pll_clock_test/funconfig.h
@@ -0,0 +1,13 @@
+#ifndef _FUNCONFIG_H
+#define _FUNCONFIG_H
+
+#define FUNCONF_SYSTICK_USE_HCLK 1
+#define FUNCONF_USE_HSI 1
+#define FUNCONF_USE_PLL 0
+#define FUNCONF_PLL_MULTIPLIER 2
+
+#define FUNCONF_USE_DEBUGPRINTF 1
+#define FUNCONF_SYSTEM_CORE_CLOCK 8 * 1000 * 1000 
+
+#endif
+
diff --git a/examples_v30x/pll_clock_test/pll_clock_test.c b/examples_v30x/pll_clock_test/pll_clock_test.c
new file mode 100644
index 00000000..2b23f3d6
--- /dev/null
+++ b/examples_v30x/pll_clock_test/pll_clock_test.c
@@ -0,0 +1,46 @@
+// Simple example that demonstrates how to configure different PLL multipliers
+// for the HSI clock source.
+
+#include "ch32fun.h"
+#include <stdio.h>
+
+void PLL_configure(u8 pll_indexValue) {
+	if (pll_indexValue > 15) return;
+
+	// Switch to HSI first
+	RCC->CFGR0 &= ~RCC_SW;		   // Clear clock source bits
+	RCC->CFGR0 |= RCC_SW_HSI;		// Switch to HSI clock source
+	while((RCC->CFGR0 & RCC_SWS) != RCC_SWS_HSI); // Wait for switch
+
+	// Turn off PLL and wait for it to stop
+	RCC->CTLR &= ~RCC_PLLON;
+	while(RCC->CTLR & RCC_PLLRDY);   // Wait for PLL to fully stop
+	
+	// Clear existing multiplier bits and set new one
+	RCC->CFGR0 &= ~RCC_PLLMULL;	  // Clear all PLLMUL bits
+	RCC->CFGR0 |= (pll_indexValue << 18); // Set new multiplier
+	
+	// Turn on PLL and wait for it to lock
+	RCC->CTLR |= RCC_PLLON;
+	while(!(RCC->CTLR & RCC_PLLRDY)); // Wait for PLL to lock
+	
+	// Switch to PLL
+	RCC->CFGR0 &= ~RCC_SW;		   // Clear clock source bits
+	RCC->CFGR0 |= RCC_SW_PLL;		// Switch clock source to PLL
+	while((RCC->CFGR0 & RCC_SWS) != RCC_SWS_PLL); // Wait for switch
+}
+
+int main() {
+	SystemInit();
+	Delay_Ms(100);
+
+	printf("\n~ PLL Test ~\n");
+
+	while(1) {
+		for (int i = 0; i < 16; i++) {
+			printf("PLL multiplier index %d\n", i);
+			PLL_configure(i);
+			Delay_Ms(12000);
+		}
+	}
+}
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