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/**************************************************************************/
/*!
@file lpc134x.h
@author K. Townsend (microBuilder.eu)
@date 22 March 2010
@version 0.10
@section DESCRIPTION
LPC1343 header file, based on V0.10 of the LPC1343 User Manual.
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2010, microBuilder SARL
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************/
#ifndef _LPC134X_H_
#define _LPC134X_H_
#include "sysdefs.h"
#include "projectconfig.h"
/*##############################################################################
## System Control Block
##############################################################################*/
#define SCB_BASE_ADDRESS (*(pREG32 (0x40048000))) // System control block base address
#define SCB_MEMREMAP (*(pREG32 (0x40048000))) // System memory remap
#define SCB_PRESETCTRL (*(pREG32 (0x40048004))) // Peripheral reset control
#define SCB_PLLCTRL (*(pREG32 (0x40048008))) // System PLL control
#define SCB_PLLSTAT (*(pREG32 (0x4004800C))) // System PLL status
#define SCB_USBPLLCTRL (*(pREG32 (0x40048010))) // USB PLL control
#define SCB_USBPLLSTAT (*(pREG32 (0x40048014))) // USB PLL status
#define SCB_SYSOSCCTRL (*(pREG32 (0x40048020))) // System oscillator control
#define SCB_WDTOSCCTRL (*(pREG32 (0x40048024))) // Watchdog oscillator control
#define SCB_IRCCTRL (*(pREG32 (0x40048028))) // IRC control
#define SCB_RESETSTAT (*(pREG32 (0x40048030))) // System reset status register
#define SCB_PLLCLKSEL (*(pREG32 (0x40048040))) // System PLL clock source select
#define SCB_PLLCLKUEN (*(pREG32 (0x40048044))) // System PLL clock source update enable
#define SCB_USBPLLCLKSEL (*(pREG32 (0x40048048))) // USB PLL clock source select
#define SCB_USBPLLCLKUEN (*(pREG32 (0x4004804C))) // USB PLL clock source update enable
#define SCB_MAINCLKSEL (*(pREG32 (0x40048070))) // Main clock source select
#define SCB_MAINCLKUEN (*(pREG32 (0x40048074))) // Main clock source update enable
#define SCB_SYSAHBCLKDIV (*(pREG32 (0x40048078))) // System AHB clock divider
#define SCB_SYSAHBCLKCTRL (*(pREG32 (0x40048080))) // System AHB clock control
#define SCB_SSP0CLKDIV (*(pREG32 (0x40048094))) // SSP0 clock divider
#define SCB_UARTCLKDIV (*(pREG32 (0x40048098))) // UART clock divider
#define SCB_SYSTICKCLKDIV (*(pREG32 (0x400480B0))) // System tick clock divider
#define SCB_USBCLKSEL (*(pREG32 (0x400480C0))) // USB clock source select
#define SCB_USBCLKUEN (*(pREG32 (0x400480C4))) // USB clock source update enable
#define SCB_USBCLKDIV (*(pREG32 (0x400480C8))) // USB clock divider
#define SCB_WDTCLKSEL (*(pREG32 (0x400480D0))) // Watchdog clock source select
#define SCB_WDTCLKUEN (*(pREG32 (0x400480D4))) // Watchdog clock source update enable
#define SCB_WDTCLKDIV (*(pREG32 (0x400480D8))) // Watchdog clock divider
#define SCB_CLKOUTCLKSEL (*(pREG32 (0x400480E0))) // CLKOUT clock source select
#define SCB_CLKOUTCLKUEN (*(pREG32 (0x400480E4))) // CLKOUT clock source update enable
#define SCB_CLKOUTCLKDIV (*(pREG32 (0x400480E8))) // CLKOUT clock divider
#define SCB_PIOPORCAP0 (*(pREG32 (0x40048100))) // POR captured PIO status 0
#define SCB_PIOPORCAP1 (*(pREG32 (0x40048104))) // POR captured PIO status 1
#define SCB_BODCTRL (*(pREG32 (0x40048150))) // Brown-out detector control
#define SCB_SYSTICKCCAL (*(pREG32 (0x40048158))) // System tick counter calibration
#define SCB_STARTAPRP0 (*(pREG32 (0x40048200))) // Start logic edge control register 0; bottom 32 interrupts
#define SCB_STARTERP0 (*(pREG32 (0x40048204))) // Start logic signal enable register 0; bottom 32 interrupts
#define SCB_STARTRSRP0CLR (*(pREG32 (0x40048208))) // Start logic reset register 0; bottom 32 interrupts
#define SCB_STARTSRP0 (*(pREG32 (0x4004820C))) // Start logic status register 0; bottom 32 interrupts
#define SCB_STARTAPRP1 (*(pREG32 (0x40048210))) // Start logic edge control register 1; top 8 interrupts
#define SCB_STARTERP1 (*(pREG32 (0x40048214))) // Start logic signal enable register 1; top 8 interrupts
#define SCB_STARTRSRP1CLR (*(pREG32 (0x40048218))) // Start logic reset register 1; top 8 interrupts
#define SCB_STARTSRP1 (*(pREG32 (0x4004821C))) // Start logic status register 1; top 8 interrupts
#define SCB_PDSLEEPCFG (*(pREG32 (0x40048230))) // Power-down states in Deep-sleep mode
#define SCB_PDAWAKECFG (*(pREG32 (0x40048234))) // Power-down states after wake-up from Deep-sleep mode
#define SCB_PDRUNCFG (*(pREG32 (0x40048238))) // Power-down configuration register
#define SCB_DEVICEID (*(pREG32 (0x400483F4))) // Device ID
#define SCB_MMFAR (*(pREG32 (0xE000ED34))) // Memory Manage Address Register (MMAR)
#define SCB_BFAR (*(pREG32 (0xE000ED38))) // Bus Fault Manage Address Register (BFAR)
#define SCB_DEMCR (*(pREG32 (0xE000EDFC)))
/* CPU ID Base Register */
#define SCB_CPUID (*(pREG32 (0xE000ED00)))
#define SCB_CPUID_REVISION_MASK ((unsigned int) 0x0000000F) // Revision Code
#define SCB_CPUID_PARTNO_MASK ((unsigned int) 0x0000FFF0) // Part Number
#define SCB_CPUID_CONSTANT_MASK ((unsigned int) 0x000F0000) // Constant
#define SCB_CPUID_VARIANT_MASK ((unsigned int) 0x00F00000) // Variant
#define SCB_CPUID_IMPLEMENTER_MASK ((unsigned int) 0xFF000000) // Implementer
/* System Control Register */
#define SCB_SCR (*(pREG32 (0xE000ED10)))
#define SCB_SCR_SLEEPONEXIT_MASK ((unsigned int) 0x00000002) // Enable sleep on exit
#define SCB_SCR_SLEEPONEXIT ((unsigned int) 0x00000002)
#define SCB_SCR_SLEEPDEEP_MASK ((unsigned int) 0x00000004)
#define SCB_SCR_SLEEPDEEP ((unsigned int) 0x00000004) // Enable deep sleep
#define SCB_SCR_SEVONPEND_MASK ((unsigned int) 0x00000010) // Wake up from WFE is new int is pended regardless of priority
#define SCB_SCR_SEVONPEND ((unsigned int) 0x00000010)
/* Application Interrupt and Reset Control Register */
#define SCB_AIRCR (*(pREG32 (0xE000ED0C)))
#define SCB_AIRCR_VECTKEY_VALUE ((unsigned int) 0x05FA0000) // Vect key needs to be set to 05FA for reset to work
#define SCB_AIRCR_VECTKEY_MASK ((unsigned int) 0xFFFF0000)
#define SCB_AIRCR_ENDIANESS ((unsigned int) 0x00008000) // Read Endianness (1=Big, 0=Little)
#define SCB_AIRCR_ENDIANESS_MASK ((unsigned int) 0x00008000)
#define SCB_AIRCR_PRIGROUP ((unsigned int) 0x00000700)
#define SCB_AIRCR_PRIGROUP_MASK ((unsigned int) 0x00000700)
#define SCB_AIRCR_SYSRESETREQ ((unsigned int) 0x00000004) // Request system reset
#define SCB_AIRCR_SYSRESETREQ_MASK ((unsigned int) 0x00000004)
#define SCB_AIRCR_VECTCLRACTIVE ((unsigned int) 0x00000002) // Used to prevent accidental reset
#define SCB_AIRCR_VECTCLRACTIVE_MASK ((unsigned int) 0x00000002)
#define SCB_AIRCR_VECTRESET ((unsigned int) 0x00000001)
#define SCB_AIRCR_VECTRESET_MASK ((unsigned int) 0x00000001)
/* Memory Management Fault Status Register */
#define SCB_MMFSR (*(pREG32 (0xE000ED28)))
#define SCB_MMFSR_IACCVIOL_MASK ((unsigned int) 0x00000001) // Instruction access violation
#define SCB_MMFSR_IACCVIOL ((unsigned int) 0x00000001)
#define SCB_MMFSR_DACCVIOL_MASK ((unsigned int) 0x00000002) // Data access violation
#define SCB_MMFSR_DACCVIOL ((unsigned int) 0x00000002)
#define SCB_MMFSR_MUNSTKERR_MASK ((unsigned int) 0x00000008) // Unstacking error
#define SCB_MMFSR_MUNSTKERR ((unsigned int) 0x00000008)
#define SCB_MMFSR_MSTKERR_MASK ((unsigned int) 0x00000010) // Stacking error
#define SCB_MMFSR_MSTKERR ((unsigned int) 0x00000010)
#define SCB_MMFSR_MMARVALID_MASK ((unsigned int) 0x00000080) // Indicates MMAR is valid
#define SCB_MMFSR_MMARVALID ((unsigned int) 0x00000080)
/* Bus Fault Status Register */
#define SCB_BFSR (*(pREG32 (0xE000ED29)))
#define SCB_BFSR_IBUSERR_MASK ((unsigned int) 0x00000001) // Instruction access violation
#define SCB_BFSR_IBUSERR ((unsigned int) 0x00000001)
#define SCB_BFSR_PRECISERR_MASK ((unsigned int) 0x00000002) // Precise data access violation
#define SCB_BFSR_PRECISERR ((unsigned int) 0x00000002)
#define SCB_BFSR_IMPRECISERR_MASK ((unsigned int) 0x00000004) // Imprecise data access violation
#define SCB_BFSR_IMPRECISERR ((unsigned int) 0x00000004)
#define SCB_BFSR_UNSTKERR_MASK ((unsigned int) 0x00000008) // Unstacking error
#define SCB_BFSR_UNSTKERR ((unsigned int) 0x00000008)
#define SCB_BFSR_STKERR_MASK ((unsigned int) 0x00000010) // Stacking error
#define SCB_BFSR_STKERR ((unsigned int) 0x00000010)
#define SCB_BFSR_BFARVALID_MASK ((unsigned int) 0x00000080) // Indicates BFAR is valid
#define SCB_BFSR_BFARVALID ((unsigned int) 0x00000080)
/* Usage Fault Status Register */
#define SCB_UFSR (*(pREG32 (0xE000ED2A)))
#define SCB_UFSR_UNDEFINSTR_MASK ((unsigned int) 0x00000001) // Attempt to execute an undefined instruction
#define SCB_UFSR_UNDEFINSTR ((unsigned int) 0x00000001)
#define SCB_UFSR_INVSTATE_MASK ((unsigned int) 0x00000002) // Attempt to switch to invalid state (i.e. ARM)
#define SCB_UFSR_INVSTATE ((unsigned int) 0x00000002)
#define SCB_UFSR_INVPC_MASK ((unsigned int) 0x00000004) // Attempt to do exception with bad value in EXC_RETURN number
#define SCB_UFSR_INVPC ((unsigned int) 0x00000004)
#define SCB_UFSR_NOCP_MASK ((unsigned int) 0x00000008) // Attempt to execute a coprocessor instruction
#define SCB_UFSR_NOCP ((unsigned int) 0x00000008)
#define SCB_UFSR_UNALIGNED_MASK ((unsigned int) 0x00000100) // Unaligned access
#define SCB_UFSR_UNALIGNED ((unsigned int) 0x00000100)
#define SCB_UFSR_DIVBYZERO_MASK ((unsigned int) 0x00000200) // Divide by zero
#define SCB_UFSR_DIVBYZERO ((unsigned int) 0x00000200)
/* Hard Fault Status Register */
#define SCB_HFSR (*(pREG32 (0xE000ED2C)))
#define SCB_HFSR_VECTTBL_MASK ((unsigned int) 0x00000002) // Hard fault caused by failed vector fetch
#define SCB_HFSR_VECTTBL ((unsigned int) 0x00000002)
#define SCB_HFSR_FORCED_MASK ((unsigned int) 0x40000000) // Hard fault taken because of bus/mem man/usage fault
#define SCB_HFSR_FORCED ((unsigned int) 0x40000000)
#define SCB_HFSR_DEBUGEVT_MASK ((unsigned int) 0x80000000) // Hard fault triggered by debug event
#define SCB_HFSR_DEBUGEVT ((unsigned int) 0x80000000)
/* Debug Fault Status Register */
#define SCB_DFSR (*(pREG32 (0xE000ED30)))
#define SCB_DFSR_HALTED_MASK ((unsigned int) 0x00000001) // Halt requested in NVIC
#define SCB_DFSR_HALTED ((unsigned int) 0x00000001)
#define SCB_DFSR_BKPT_MASK ((unsigned int) 0x00000002) // BKPT instruction executed
#define SCB_DFSR_BKPT ((unsigned int) 0x00000002)
#define SCB_DFSR_DWTTRAP_MASK ((unsigned int) 0x00000004) // DWT match occurred
#define SCB_DFSR_DWTTRAP ((unsigned int) 0x00000004)
#define SCB_DFSR_VCATCH_MASK ((unsigned int) 0x00000008) // Vector fetch occurred
#define SCB_DFSR_VCATCH ((unsigned int) 0x00000008)
#define SCB_DFSR_EXTERNAL_MASK ((unsigned int) 0x00000010) // EDBGRQ signal asserted
#define SCB_DFSR_EXTERNAL ((unsigned int) 0x00000010)
/* SCB_MEMREMAP (System memory remap register)
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM. */
#define SCB_MEMREMAP_MODE_BOOTLOADER ((unsigned int) 0x00000000) // Interrupt vectors are remapped to Boot ROM
#define SCB_MEMREMAP_MODE_RAM ((unsigned int) 0x00000001) // Interrupt vectors are remapped to Static ROM
#define SCB_MEMREMAP_MODE_FLASH ((unsigned int) 0x00000002) // Interrupt vectors are not remapped and reside in Flash
#define SCB_MEMREMAP_MASK ((unsigned int) 0x00000003)
/* PRESETCTRL (Peripheral reset control register) */
#define SCB_PRESETCTRL_SSP0_RESETENABLED ((unsigned int) 0x00000000)
#define SCB_PRESETCTRL_SSP0_RESETDISABLED ((unsigned int) 0x00000001)
#define SCB_PRESETCTRL_SSP0_MASK ((unsigned int) 0x00000001)
#define SCB_PRESETCTRL_I2C_RESETENABLED ((unsigned int) 0x00000000)
#define SCB_PRESETCTRL_I2C_RESETDISABLED ((unsigned int) 0x00000002)
#define SCB_PRESETCTRL_I2C_MASK ((unsigned int) 0x00000002)
/* SYSPLLCTRL (System PLL control register)
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and optionally the USB
subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
produce a clock up to the maximum allowed for the CPU, which is 72 MHz. */
#define SCB_PLLCTRL_MSEL_1 ((unsigned int) 0x00000000)
#define SCB_PLLCTRL_MSEL_2 ((unsigned int) 0x00000001)
#define SCB_PLLCTRL_MSEL_3 ((unsigned int) 0x00000002)
#define SCB_PLLCTRL_MSEL_4 ((unsigned int) 0x00000003)
#define SCB_PLLCTRL_MSEL_5 ((unsigned int) 0x00000004)
#define SCB_PLLCTRL_MSEL_6 ((unsigned int) 0x00000005)
#define SCB_PLLCTRL_MSEL_7 ((unsigned int) 0x00000006)
#define SCB_PLLCTRL_MSEL_8 ((unsigned int) 0x00000007)
#define SCB_PLLCTRL_MSEL_9 ((unsigned int) 0x00000008)
#define SCB_PLLCTRL_MSEL_10 ((unsigned int) 0x00000009)
#define SCB_PLLCTRL_MSEL_11 ((unsigned int) 0x0000000A)
#define SCB_PLLCTRL_MSEL_12 ((unsigned int) 0x0000000B)
#define SCB_PLLCTRL_MSEL_13 ((unsigned int) 0x0000000C)
#define SCB_PLLCTRL_MSEL_14 ((unsigned int) 0x0000000D)
#define SCB_PLLCTRL_MSEL_15 ((unsigned int) 0x0000000E)
#define SCB_PLLCTRL_MSEL_16 ((unsigned int) 0x0000000F)
#define SCB_PLLCTRL_MSEL_17 ((unsigned int) 0x00000010)
#define SCB_PLLCTRL_MSEL_18 ((unsigned int) 0x00000011)
#define SCB_PLLCTRL_MSEL_19 ((unsigned int) 0x00000012)
#define SCB_PLLCTRL_MSEL_20 ((unsigned int) 0x00000013)
#define SCB_PLLCTRL_MSEL_21 ((unsigned int) 0x00000014)
#define SCB_PLLCTRL_MSEL_22 ((unsigned int) 0x00000015)
#define SCB_PLLCTRL_MSEL_23 ((unsigned int) 0x00000016)
#define SCB_PLLCTRL_MSEL_24 ((unsigned int) 0x00000017)
#define SCB_PLLCTRL_MSEL_25 ((unsigned int) 0x00000018)
#define SCB_PLLCTRL_MSEL_26 ((unsigned int) 0x00000019)
#define SCB_PLLCTRL_MSEL_27 ((unsigned int) 0x0000001A)
#define SCB_PLLCTRL_MSEL_28 ((unsigned int) 0x0000001B)
#define SCB_PLLCTRL_MSEL_29 ((unsigned int) 0x0000001C)
#define SCB_PLLCTRL_MSEL_30 ((unsigned int) 0x0000001D)
#define SCB_PLLCTRL_MSEL_31 ((unsigned int) 0x0000001E)
#define SCB_PLLCTRL_MSEL_32 ((unsigned int) 0x0000001F)
#define SCB_PLLCTRL_MSEL_MASK ((unsigned int) 0x0000001F)
#define SCB_PLLCTRL_PSEL_2 ((unsigned int) 0x00000000)
#define SCB_PLLCTRL_PSEL_4 ((unsigned int) 0x00000020)
#define SCB_PLLCTRL_PSEL_8 ((unsigned int) 0x00000040)
#define SCB_PLLCTRL_PSEL_16 ((unsigned int) 0x00000060)
#define SCB_PLLCTRL_PSEL_BIT (5)
#define SCB_PLLCTRL_PSEL_MASK ((unsigned int) 0x00000060)
#define SCB_PLLCTRL_DIRECT_MASK ((unsigned int) 0x00000080) // Direct CCO clock output control
#define SCB_PLLCTRL_BYPASS_MASK ((unsigned int) 0x00000100) // Input clock bypass control
#define SCB_PLLCTRL_MASK ((unsigned int) 0x000001FF)
/* SYSPLLSTAT (System PLL status register)
This register is a Read-only register and supplies the PLL lock status */
#define SCB_PLLSTAT_LOCK ((unsigned int) 0x00000001) // 0 = PLL not locked, 1 = PLL locked
#define SCB_PLLSTAT_LOCK_MASK ((unsigned int) 0x00000001)
/* USBPLLCTRL (USB PLL control register)
The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
the USB block if available. The USB PLL should be always connected to the system
oscillator to produce a stable USB clock. */
#define SCB_USBPLLCTRL_MULT_1 ((unsigned int) 0x00000000)
#define SCB_USBPLLCTRL_MULT_2 ((unsigned int) 0x00000001)
#define SCB_USBPLLCTRL_MULT_3 ((unsigned int) 0x00000002)
#define SCB_USBPLLCTRL_MULT_4 ((unsigned int) 0x00000003)
#define SCB_USBPLLCTRL_MULT_5 ((unsigned int) 0x00000004)
#define SCB_USBPLLCTRL_MULT_6 ((unsigned int) 0x00000005)
#define SCB_USBPLLCTRL_MULT_7 ((unsigned int) 0x00000006)
#define SCB_USBPLLCTRL_MULT_8 ((unsigned int) 0x00000007)
#define SCB_USBPLLCTRL_MULT_9 ((unsigned int) 0x00000008)
#define SCB_USBPLLCTRL_MULT_10 ((unsigned int) 0x00000009)
#define SCB_USBPLLCTRL_MULT_11 ((unsigned int) 0x0000000A)
#define SCB_USBPLLCTRL_MULT_12 ((unsigned int) 0x0000000B)
#define SCB_USBPLLCTRL_MULT_13 ((unsigned int) 0x0000000C)
#define SCB_USBPLLCTRL_MULT_14 ((unsigned int) 0x0000000D)
#define SCB_USBPLLCTRL_MULT_15 ((unsigned int) 0x0000000E)
#define SCB_USBPLLCTRL_MULT_16 ((unsigned int) 0x0000000F)
#define SCB_USBPLLCTRL_MULT_17 ((unsigned int) 0x00000010)
#define SCB_USBPLLCTRL_MULT_18 ((unsigned int) 0x00000011)
#define SCB_USBPLLCTRL_MULT_19 ((unsigned int) 0x00000012)
#define SCB_USBPLLCTRL_MULT_20 ((unsigned int) 0x00000013)
#define SCB_USBPLLCTRL_MULT_21 ((unsigned int) 0x00000014)
#define SCB_USBPLLCTRL_MULT_22 ((unsigned int) 0x00000015)
#define SCB_USBPLLCTRL_MULT_23 ((unsigned int) 0x00000016)
#define SCB_USBPLLCTRL_MULT_24 ((unsigned int) 0x00000017)
#define SCB_USBPLLCTRL_MULT_25 ((unsigned int) 0x00000018)
#define SCB_USBPLLCTRL_MULT_26 ((unsigned int) 0x00000019)
#define SCB_USBPLLCTRL_MULT_27 ((unsigned int) 0x0000001A)
#define SCB_USBPLLCTRL_MULT_28 ((unsigned int) 0x0000001B)
#define SCB_USBPLLCTRL_MULT_29 ((unsigned int) 0x0000001C)
#define SCB_USBPLLCTRL_MULT_30 ((unsigned int) 0x0000001D)
#define SCB_USBPLLCTRL_MULT_31 ((unsigned int) 0x0000001E)
#define SCB_USBPLLCTRL_MULT_32 ((unsigned int) 0x0000001F)
#define SCB_USBPLLCTRL_MULT_MASK ((unsigned int) 0x0000001F)
#define SCB_USBPLLCTRL_DIV_2 ((unsigned int) 0x00000000)
#define SCB_USBPLLCTRL_DIV_4 ((unsigned int) 0x00000020)
#define SCB_USBPLLCTRL_DIV_8 ((unsigned int) 0x00000040)
#define SCB_USBPLLCTRL_DIV_16 ((unsigned int) 0x00000060)
#define SCB_USBPLLCTRL_DIV_BIT (5)
#define SCB_USBPLLCTRL_DIV_MASK ((unsigned int) 0x00000060)
#define SCB_USBPLLCTRL_DIRECT_MASK ((unsigned int) 0x00000080) // Direct CCO clock output control
#define SCB_USBPLLCTRL_BYPASS_MASK ((unsigned int) 0x00000100) // Input clock bypass control
#define SCB_USBPLLCTRL_MASK ((unsigned int) 0x000001FF)
/* USBPLLSTAT (System PLL status register)
This register is a Read-only register and supplies the PLL lock status. */
#define SCB_USBPLLSTAT_LOCK ((unsigned int) 0x00000001) // 0 = PLL not locked, 1 = PLL locked
#define SCB_USBPLLSTAT_LOCK_MASK ((unsigned int) 0x00000001)
/* SYSOSCCTRL (System oscillator control register)
This register configures the frequency range for the system oscillator. */
#define SCB_SYSOSCCTRL_BYPASS_DISABLED ((unsigned int) 0x00000000) // Oscillator is not bypassed.
#define SCB_SYSOSCCTRL_BYPASS_ENABLED ((unsigned int) 0x00000001) // Bypass enabled
#define SCB_SYSOSCCTRL_BYPASS_MASK ((unsigned int) 0x00000001)
#define SCB_SYSOSCCTRL_FREQRANGE_1TO20MHZ ((unsigned int) 0x00000000) // 1-20 MHz frequency range
#define SCB_SYSOSCCTRL_FREQRANGE_15TO25MHZ ((unsigned int) 0x00000002) // 15-25 MHz frequency range
#define SCB_SYSOSCCTRL_FREQRANGE_MASK ((unsigned int) 0x00000002)
/* WDTOSCTRL (Watchdog oscillator control register)
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.7 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.*/
#define SCB_WDTOSCCTRL_DIVSEL_DIV2 ((unsigned int) 0x00000000) // Reset value
#define SCB_WDTOSCCTRL_DIVSEL_DIV4 ((unsigned int) 0x00000001)
#define SCB_WDTOSCCTRL_DIVSEL_DIV6 ((unsigned int) 0x00000002)
#define SCB_WDTOSCCTRL_DIVSEL_DIV8 ((unsigned int) 0x00000003)
#define SCB_WDTOSCCTRL_DIVSEL_DIV10 ((unsigned int) 0x00000004)
#define SCB_WDTOSCCTRL_DIVSEL_DIV12 ((unsigned int) 0x00000005)
#define SCB_WDTOSCCTRL_DIVSEL_DIV14 ((unsigned int) 0x00000006)
#define SCB_WDTOSCCTRL_DIVSEL_DIV16 ((unsigned int) 0x00000007)
#define SCB_WDTOSCCTRL_DIVSEL_DIV18 ((unsigned int) 0x00000008)
#define SCB_WDTOSCCTRL_DIVSEL_DIV20 ((unsigned int) 0x00000009)
#define SCB_WDTOSCCTRL_DIVSEL_DIV22 ((unsigned int) 0x0000000A)
#define SCB_WDTOSCCTRL_DIVSEL_DIV24 ((unsigned int) 0x0000000B)
#define SCB_WDTOSCCTRL_DIVSEL_DIV26 ((unsigned int) 0x0000000C)
#define SCB_WDTOSCCTRL_DIVSEL_DIV28 ((unsigned int) 0x0000000D)
#define SCB_WDTOSCCTRL_DIVSEL_DIV30 ((unsigned int) 0x0000000E)
#define SCB_WDTOSCCTRL_DIVSEL_DIV32 ((unsigned int) 0x0000000F)
#define SCB_WDTOSCCTRL_DIVSEL_DIV34 ((unsigned int) 0x00000010)
#define SCB_WDTOSCCTRL_DIVSEL_DIV36 ((unsigned int) 0x00000011)
#define SCB_WDTOSCCTRL_DIVSEL_DIV38 ((unsigned int) 0x00000012)
#define SCB_WDTOSCCTRL_DIVSEL_DIV40 ((unsigned int) 0x00000013)
#define SCB_WDTOSCCTRL_DIVSEL_DIV42 ((unsigned int) 0x00000014)
#define SCB_WDTOSCCTRL_DIVSEL_DIV44 ((unsigned int) 0x00000015)
#define SCB_WDTOSCCTRL_DIVSEL_DIV46 ((unsigned int) 0x00000016)
#define SCB_WDTOSCCTRL_DIVSEL_DIV48 ((unsigned int) 0x00000017)
#define SCB_WDTOSCCTRL_DIVSEL_DIV50 ((unsigned int) 0x00000018)
#define SCB_WDTOSCCTRL_DIVSEL_DIV52 ((unsigned int) 0x00000019)
#define SCB_WDTOSCCTRL_DIVSEL_DIV54 ((unsigned int) 0x0000001A)
#define SCB_WDTOSCCTRL_DIVSEL_DIV56 ((unsigned int) 0x0000001B)
#define SCB_WDTOSCCTRL_DIVSEL_DIV58 ((unsigned int) 0x0000001C)
#define SCB_WDTOSCCTRL_DIVSEL_DIV60 ((unsigned int) 0x0000001D)
#define SCB_WDTOSCCTRL_DIVSEL_DIV62 ((unsigned int) 0x0000001E)
#define SCB_WDTOSCCTRL_DIVSEL_DIV64 ((unsigned int) 0x0000001F)
#define SCB_WDTOSCCTRL_DIVSEL_MASK ((unsigned int) 0x0000001F)
#define SCB_WDTOSCCTRL_FREQSEL_0_5MHZ ((unsigned int) 0x00000020)
#define SCB_WDTOSCCTRL_FREQSEL_0_8MHZ ((unsigned int) 0x00000040)
#define SCB_WDTOSCCTRL_FREQSEL_1_1MHZ ((unsigned int) 0x00000060)
#define SCB_WDTOSCCTRL_FREQSEL_1_4MHZ ((unsigned int) 0x00000080)
#define SCB_WDTOSCCTRL_FREQSEL_1_6MHZ ((unsigned int) 0x000000A0) // Reset value
#define SCB_WDTOSCCTRL_FREQSEL_1_8MHZ ((unsigned int) 0x000000C0)
#define SCB_WDTOSCCTRL_FREQSEL_2_0MHZ ((unsigned int) 0x000000E0)
#define SCB_WDTOSCCTRL_FREQSEL_2_2MHZ ((unsigned int) 0x00000100)
#define SCB_WDTOSCCTRL_FREQSEL_2_4MHZ ((unsigned int) 0x00000120)
#define SCB_WDTOSCCTRL_FREQSEL_2_6MHZ ((unsigned int) 0x00000140)
#define SCB_WDTOSCCTRL_FREQSEL_2_7MHZ ((unsigned int) 0x00000160)
#define SCB_WDTOSCCTRL_FREQSEL_2_9MHZ ((unsigned int) 0x00000180)
#define SCB_WDTOSCCTRL_FREQSEL_3_1MHZ ((unsigned int) 0x000001A0)
#define SCB_WDTOSCCTRL_FREQSEL_3_2MHZ ((unsigned int) 0x000001C0)
#define SCB_WDTOSCCTRL_FREQSEL_3_4MHZ ((unsigned int) 0x000001E0)
#define SCB_WDTOSCCTRL_FREQSEL_MASK ((unsigned int) 0x000001E0)
/* IRCCTRL (Internal resonant crystal control register)
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up. */
#define SCB_IRCCTRL_MASK ((unsigned int) 0x000000FF)
/* SYSRSTSTAT (System reset status register)
The SYSRSTSTAT register shows the source of the latest reset event. The bits are
cleared by writing a one to any of the bits. The POR event clears all other bits in this
register, but if another reset signal (e.g., EXTRST) remains asserted after the POR signal
is negated, then its bit is set to detected. */
#define SCB_RESETSTAT_POR_MASK ((unsigned int) 0x00000001) // POR reset status
#define SCB_RESETSTAT_EXTRST_MASK ((unsigned int) 0x00000002) // Status of the external reset pin
#define SCB_RESETSTAT_WDT_MASK ((unsigned int) 0x00000004) // Status of the watchdog reset
#define SCB_RESETSTAT_BOD_MASK ((unsigned int) 0x00000008) // Status of the brown-out detect reset
#define SCB_RESETSTAT_SYSRST_MASK ((unsigned int) 0x00000010) // Status of the software system reset
#define SCB_RESETSTAT_MASK ((unsigned int) 0x00000010)
/* SYSPLLCLKSEL (System PLL clock source select register)
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
must be toggled from LOW to HIGH for the update to take effect.
Remark: The system oscillator must be selected if the system PLL is used to generate a
48 MHz clock to the USB block.
*/
#define SCB_CLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000)
#define SCB_CLKSEL_SOURCE_MAINOSC ((unsigned int) 0x00000001)
#define SCB_CLKSEL_SOURCE_RTCOSC ((unsigned int) 0x00000002)
#define SCB_CLKSEL_SOURCE_MASK ((unsigned int) 0x00000002)
/* SYSPLLUEN (System PLL clock source update enable register)
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. */
#define SCB_PLLCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_PLLCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_PLLCLKUEN_MASK ((unsigned int) 0x00000001)
/* USBPLLCLKSEL (USB PLL clock source select register)
his register selects the clock source for the dedicated USB PLL. The SYSPLLCLKUEN
register must be toggled from LOW to HIGH for the update to take effect.
Remark: Always select the system oscillator to produce a stable 48 MHz clock for
the USB block. */
#define SCB_USBPLLCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Do NOT use (even though this is the default value)
#define SCB_USBPLLCLKSEL_SOURCE_MAINOSC ((unsigned int) 0x00000001) // Main oscillator should always be used for USB clock
#define SCB_USBPLLCLKSEL_SOURCE_MASK ((unsigned int) 0x00000002)
/* USBPLLUEN (USB PLL clock source update enable register)
This register updates the clock source of the USB PLL with the new input clock after the
USBPLLCLKSEL register has been written to. In order for the update to take effect at the
USB PLL input, first write a zero to the USBPLLUEN register and then write a one to
USBPLLUEN. */
#define SCB_USBPLLCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_USBPLLCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_USBPLLCLKUEN_MASK ((unsigned int) 0x00000001)
/* MAINCLKSEL (Main clock source select register)
This register selects the main system clock which can be either the output from the
system PLL or the IRC, system, or Watchdog oscillators directly. The main system clock
clocks the core, the peripherals, and optionally the USB block.
The MAINCLKUEN register must be toggled from LOW to HIGH for the update to take effect.*/
#define SCB_MAINCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Use IRC oscillator for main clock source
#define SCB_MAINCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use Input clock to system PLL for main clock source
#define SCB_MAINCLKSEL_SOURCE_WDTOSC ((unsigned int) 0x00000002) // Use watchdog oscillator for main clock source
#define SCB_MAINCLKSEL_SOURCE_SYSPLLCLKOUT ((unsigned int) 0x00000003) // Use system PLL clock out for main clock source
#define SCB_MAINCLKSEL_MASK ((unsigned int) 0x00000003)
/* MAINCLKUEN (Main clock source update enable register)
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINUEN register and then write a one to MAINCLKUEN. */
#define SCB_MAINCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_MAINCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_MAINCLKUEN_MASK ((unsigned int) 0x00000001)
/* SYSAHBCLKDIV (System AHB clock divider register)
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0. */
#define SCB_SYSAHBCLKDIV_DISABLE ((unsigned int) 0x00000000) // 0 will shut the system clock down completely
#define SCB_SYSAHBCLKDIV_DIV1 ((unsigned int) 0x00000001) // 1, 2 or 4 are the most common values
#define SCB_SYSAHBCLKDIV_DIV2 ((unsigned int) 0x00000002)
#define SCB_SYSAHBCLKDIV_DIV4 ((unsigned int) 0x00000004)
#define SCB_SYSAHBCLKDIV_MASK ((unsigned int) 0x000000FF) // AHB clock divider can be from 0 to 255
/* AHBCLKCTRL (System AHB clock control register)
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M3, the Syscon block, and
the PMU. This clock cannot be disabled. */
#define SCB_SYSAHBCLKCTRL_SYS ((unsigned int) 0x00000001) // Enables clock for AHB and APB bridges, FCLK, HCLK, SysCon and PMU
#define SCB_SYSAHBCLKCTRL_SYS_MASK ((unsigned int) 0x00000001)
#define SCB_SYSAHBCLKCTRL_ROM ((unsigned int) 0x00000002) // Enables clock for ROM
#define SCB_SYSAHBCLKCTRL_ROM_MASK ((unsigned int) 0x00000002)
#define SCB_SYSAHBCLKCTRL_RAM ((unsigned int) 0x00000004) // Enables clock for SRAM
#define SCB_SYSAHBCLKCTRL_RAM_MASK ((unsigned int) 0x00000004)
#define SCB_SYSAHBCLKCTRL_FLASH1 ((unsigned int) 0x00000008) // Enables clock for flash1
#define SCB_SYSAHBCLKCTRL_FLASH1_MASK ((unsigned int) 0x00000008)
#define SCB_SYSAHBCLKCTRL_FLASH2 ((unsigned int) 0x00000010) // Enables clock for flash2
#define SCB_SYSAHBCLKCTRL_FLASH2_MASK ((unsigned int) 0x00000010)
#define SCB_SYSAHBCLKCTRL_I2C ((unsigned int) 0x00000020) // Enables clock for I2C
#define SCB_SYSAHBCLKCTRL_I2C_MASK ((unsigned int) 0x00000020)
#define SCB_SYSAHBCLKCTRL_GPIO ((unsigned int) 0x00000040) // Enables clock for GPIO
#define SCB_SYSAHBCLKCTRL_GPIO_MASK ((unsigned int) 0x00000040)
#define SCB_SYSAHBCLKCTRL_CT16B0 ((unsigned int) 0x00000080) // Enables clock for 16-bit counter/timer 0
#define SCB_SYSAHBCLKCTRL_CT16B0_MASK ((unsigned int) 0x00000080)
#define SCB_SYSAHBCLKCTRL_CT16B1 ((unsigned int) 0x00000100) // Enables clock for 16-bit counter/timer 1
#define SCB_SYSAHBCLKCTRL_CT16B1_MASK ((unsigned int) 0x00000100)
#define SCB_SYSAHBCLKCTRL_CT32B0 ((unsigned int) 0x00000200) // Enables clock for 32-bit counter/timer 0
#define SCB_SYSAHBCLKCTRL_CT32B0_MASK ((unsigned int) 0x00000200)
#define SCB_SYSAHBCLKCTRL_CT32B1 ((unsigned int) 0x00000400) // Enables clock for 32-bit counter/timer 1
#define SCB_SYSAHBCLKCTRL_CT32B1_MASK ((unsigned int) 0x00000400)
#define SCB_SYSAHBCLKCTRL_SSP0 ((unsigned int) 0x00000800) // Enables clock for SSP0
#define SCB_SYSAHBCLKCTRL_SSP0_MASK ((unsigned int) 0x00000800)
#define SCB_SYSAHBCLKCTRL_UART ((unsigned int) 0x00001000) // Enables clock for UART. UART pins must be configured
#define SCB_SYSAHBCLKCTRL_UART_MASK ((unsigned int) 0x00001000) // in the IOCON block before the UART clock can be enabled.
#define SCB_SYSAHBCLKCTRL_ADC ((unsigned int) 0x00002000) // Enables clock for ADC
#define SCB_SYSAHBCLKCTRL_ADC_MASK ((unsigned int) 0x00002000)
#define SCB_SYSAHBCLKCTRL_USB_REG ((unsigned int) 0x00004000) // Enables clock for USB_REG
#define SCB_SYSAHBCLKCTRL_USB_REG_MASK ((unsigned int) 0x00004000)
#define SCB_SYSAHBCLKCTRL_WDT ((unsigned int) 0x00008000) // Enables clock for watchdog timer
#define SCB_SYSAHBCLKCTRL_WDT_MASK ((unsigned int) 0x00008000)
#define SCB_SYSAHBCLKCTRL_IOCON ((unsigned int) 0x00010000) // Enables clock for IO configuration block
#define SCB_SYSAHBCLKCTRL_IOCON_MASK ((unsigned int) 0x00010000)
#define SCB_SYSAHBCLKCTRL_ALL_MASK ((unsigned int) 0x0001FFFF)
/* SSP0CLKDIV (SSP0 clock divider register)
This register configures the SSP0 peripheral clock SSP_PCLK. The SSP_PCLK can be
shut down by setting the DIV bits to 0x0. It can be set from 1..255. */
#define SCB_SSP0CLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_SSP0CLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide SSP0 clock by 1 (can be set from 1..255)
#define SCB_SSP0CLKDIV_DIV2 ((unsigned int) 0x00000002)
#define SCB_SSP0CLKDIV_DIV3 ((unsigned int) 0x00000003)
#define SCB_SSP0CLKDIV_DIV4 ((unsigned int) 0x00000004)
#define SCB_SSP0CLKDIV_DIV6 ((unsigned int) 0x00000006)
#define SCB_SSP0CLKDIV_DIV10 ((unsigned int) 0x0000000A)
#define SCB_SSP0CLKDIV_DIV12 ((unsigned int) 0x0000000C)
#define SCB_SSP0CLKDIV_DIV20 ((unsigned int) 0x00000014)
#define SCB_SSP0CLKDIV_DIV40 ((unsigned int) 0x00000028)
#define SCB_SSP0CLKDIV_MASK ((unsigned int) 0x000000FF)
/* UARTCLKDIV (UART clock divider register)
This register configures the UART peripheral. The UART_PCLK can be shut down by
setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled. */
#define SCB_UARTCLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_UARTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide UART clock by 1 (can be set from 1..255)
#define SCB_UARTCLKDIV_DIV2 ((unsigned int) 0x00000002)
#define SCB_UARTCLKDIV_DIV4 ((unsigned int) 0x00000004)
#define SCB_UARTCLKDIV_MASK ((unsigned int) 0x000000FF)
/* SYSTICKCLKDIV (SYSTICK clock divider register)
This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be
shut down by setting the DIV bits to 0x0. */
#define SCB_SYSTICKCLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_SYSTICKCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide SYSTICK clock by 1 (can be set from 1..255)
#define SCB_SYSTICKCLKDIV_DIV2 ((unsigned int) 0x00000002) // Divide SYSTICK clock by 2
#define SCB_SYSTICKCLKDIV_DIV4 ((unsigned int) 0x00000004) // Divide SYSTICK clock by 4
#define SCB_SYSTICKCLKDIV_DIV8 ((unsigned int) 0x00000008) // Divide SYSTICK clock by 8
#define SCB_SYSTICKCLKDIV_MASK ((unsigned int) 0x000000FF)
/* USBCLKSEL (USB clock source select register)
This register selects the clock source for the USB usb_clk. The clock source can be either
the USB PLL output or the main clock, and the clock can be further divided by the
USBCLKDIV register to obtain a 48 MHz clock. The USBCLKUEN register must be toggled from
LOW to HIGH for the update to take effect. */
#define SCB_USBCLKSEL_SOURCE_USBPLLOUT ((unsigned int) 0x00000000) // USB PLL output
#define SCB_USBCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
#define SCB_USBCLKSEL_MASK ((unsigned int) 0x00000003)
/* USBCLKUEN (USB clock source update enable register)
This register updates the clock source of the USB with the new input clock after the
USBCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the USBCLKUEN register and then write a one to USBCLKUEN. */
#define SCB_USBCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_USBCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_USBCLKUEN_MASK ((unsigned int) 0x00000001)
/* USBCLKDIV (USB clock divider register)
This register allows the USB clock usb_clk to be divided to 48 MHz. The usb_clk can be
shut down by setting the DIV bits to 0x0. */
#define SCB_USBCLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_USBCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide USB clock by 1 (can be set from 1..255)
#define SCB_USBCLKDIV_MASK ((unsigned int) 0x000000FF)
/* WDTCLKSEL (WDT clock source select register)
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
must be toggled from LOW to HIGH for the update to take effect. */
#define SCB_WDTCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Use the internal oscillator
#define SCB_WDTCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
#define SCB_WDTCLKSEL_SOURCE_WATCHDOGOSC ((unsigned int) 0x00000002) // Use the watchdog oscillator
#define SCB_WDTCLKSEL_MASK ((unsigned int) 0x00000003)
/* WDTCLKUEN (WDT clock source update enable register)
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN. */
#define SCB_WDTCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_WDTCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_WDTCLKUEN_MASK ((unsigned int) 0x00000001)
/* WDTCLKDIV (WDT clock divider register)
This register determines the divider values for the watchdog clock wdt_clk. */
#define SCB_WDTCLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_WDTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide clock by 1 (can be set from 1..255)
#define SCB_WDTCLKDIV_MASK ((unsigned int) 0x000000FF)
/* CLKOUTCLKSEL (CLKOUT clock source select register)
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register must be toggled from LOW to HIGH for the update to take effect. */
#define SCB_CLKOUTCLKSEL_SOURCE_USBPLLOUT ((unsigned int) 0x00000000) // USB PLL output
#define SCB_CLKOUTCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
#define SCB_CLKOUTCLKSEL_MASK ((unsigned int) 0x00000003)
/* CLKOUTUEN (CLKOUT clock source update enable register)
This register updates the clock source of the CLKOUT pin with the new clock after the
CLKOUTCLKSEL register has been written to. In order for the update to take effect at the
input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a
one to CLKCLKUEN. */
#define SCB_CLKOUTCLKUEN_DISABLE ((unsigned int) 0x00000000)
#define SCB_CLKOUTCLKUEN_UPDATE ((unsigned int) 0x00000001)
#define SCB_CLKOUTCLKUEN_MASK ((unsigned int) 0x00000001)
/* CLKOUTCLKDIV (CLKOUT clock divider register)
This register determines the divider value for the clkout_clk signal on the CLKOUT pin. */
#define SCB_CLKOUTCLKDIV_DISABLE ((unsigned int) 0x00000000)
#define SCB_CLKOUTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide clock by 1 (can be set from 1..255)
#define SCB_CLKOUTCLKDIV_MASK ((unsigned int) 0x000000FF)
/* PIOPORCAP0 (POR captured PIO status register 0)
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register. */
#define SCB_PIOPORCAP0_PIO0_0 ((unsigned int) 0x00000001)
#define SCB_PIOPORCAP0_PIO0_0_MASK ((unsigned int) 0x00000001)
#define SCB_PIOPORCAP0_PIO0_1 ((unsigned int) 0x00000002)
#define SCB_PIOPORCAP0_PIO0_1_MASK ((unsigned int) 0x00000002)
#define SCB_PIOPORCAP0_PIO0_2 ((unsigned int) 0x00000004)
#define SCB_PIOPORCAP0_PIO0_2_MASK ((unsigned int) 0x00000004)
#define SCB_PIOPORCAP0_PIO0_3 ((unsigned int) 0x00000008)
#define SCB_PIOPORCAP0_PIO0_3_MASK ((unsigned int) 0x00000008)
#define SCB_PIOPORCAP0_PIO0_4 ((unsigned int) 0x00000010)
#define SCB_PIOPORCAP0_PIO0_4_MASK ((unsigned int) 0x00000010)
#define SCB_PIOPORCAP0_PIO0_5 ((unsigned int) 0x00000020)
#define SCB_PIOPORCAP0_PIO0_5_MASK ((unsigned int) 0x00000020)
#define SCB_PIOPORCAP0_PIO0_6 ((unsigned int) 0x00000040)
#define SCB_PIOPORCAP0_PIO0_6_MASK ((unsigned int) 0x00000040)
#define SCB_PIOPORCAP0_PIO0_7 ((unsigned int) 0x00000080)
#define SCB_PIOPORCAP0_PIO0_7_MASK ((unsigned int) 0x00000080)
#define SCB_PIOPORCAP0_PIO0_8 ((unsigned int) 0x00000100)
#define SCB_PIOPORCAP0_PIO0_8_MASK ((unsigned int) 0x00000100)
#define SCB_PIOPORCAP0_PIO0_9 ((unsigned int) 0x00000200)
#define SCB_PIOPORCAP0_PIO0_9_MASK ((unsigned int) 0x00000200)
#define SCB_PIOPORCAP0_PIO0_10 ((unsigned int) 0x00000400)
#define SCB_PIOPORCAP0_PIO0_10_MASK ((unsigned int) 0x00000400)
#define SCB_PIOPORCAP0_PIO0_11 ((unsigned int) 0x00000800)
#define SCB_PIOPORCAP0_PIO0_11_MASK ((unsigned int) 0x00000800)
#define SCB_PIOPORCAP0_PIO1_0 ((unsigned int) 0x00001000)
#define SCB_PIOPORCAP0_PIO1_0_MASK ((unsigned int) 0x00001000)
#define SCB_PIOPORCAP0_PIO1_1 ((unsigned int) 0x00002000)
#define SCB_PIOPORCAP0_PIO1_1_MASK ((unsigned int) 0x00002000)
#define SCB_PIOPORCAP0_PIO1_2 ((unsigned int) 0x00004000)
#define SCB_PIOPORCAP0_PIO1_2_MASK ((unsigned int) 0x00004000)
#define SCB_PIOPORCAP0_PIO1_3 ((unsigned int) 0x00008000)
#define SCB_PIOPORCAP0_PIO1_3_MASK ((unsigned int) 0x00008000)
#define SCB_PIOPORCAP0_PIO1_4 ((unsigned int) 0x00010000)
#define SCB_PIOPORCAP0_PIO1_4_MASK ((unsigned int) 0x00010000)
#define SCB_PIOPORCAP0_PIO1_5 ((unsigned int) 0x00020000)
#define SCB_PIOPORCAP0_PIO1_5_MASK ((unsigned int) 0x00020000)
#define SCB_PIOPORCAP0_PIO1_6 ((unsigned int) 0x00040000)
#define SCB_PIOPORCAP0_PIO1_6_MASK ((unsigned int) 0x00040000)
#define SCB_PIOPORCAP0_PIO1_7 ((unsigned int) 0x00080000)
#define SCB_PIOPORCAP0_PIO1_7_MASK ((unsigned int) 0x00080000)
#define SCB_PIOPORCAP0_PIO1_8 ((unsigned int) 0x00100000)
#define SCB_PIOPORCAP0_PIO1_8_MASK ((unsigned int) 0x00100000)
#define SCB_PIOPORCAP0_PIO1_9 ((unsigned int) 0x00200000)
#define SCB_PIOPORCAP0_PIO1_9_MASK ((unsigned int) 0x00200000)
#define SCB_PIOPORCAP0_PIO1_10 ((unsigned int) 0x00400000)
#define SCB_PIOPORCAP0_PIO1_10_MASK ((unsigned int) 0x00400000)
#define SCB_PIOPORCAP0_PIO1_11 ((unsigned int) 0x00800000)
#define SCB_PIOPORCAP0_PIO1_11_MASK ((unsigned int) 0x00800000)
#define SCB_PIOPORCAP0_PIO2_0 ((unsigned int) 0x01000000)
#define SCB_PIOPORCAP0_PIO2_0_MASK ((unsigned int) 0x01000000)
#define SCB_PIOPORCAP0_PIO2_1 ((unsigned int) 0x02000000)
#define SCB_PIOPORCAP0_PIO2_1_MASK ((unsigned int) 0x02000000)
#define SCB_PIOPORCAP0_PIO2_2 ((unsigned int) 0x04000000)
#define SCB_PIOPORCAP0_PIO2_2_MASK ((unsigned int) 0x04000000)
#define SCB_PIOPORCAP0_PIO2_3 ((unsigned int) 0x08000000)
#define SCB_PIOPORCAP0_PIO2_3_MASK ((unsigned int) 0x08000000)
#define SCB_PIOPORCAP0_PIO2_4 ((unsigned int) 0x10000000)
#define SCB_PIOPORCAP0_PIO2_4_MASK ((unsigned int) 0x10000000)
#define SCB_PIOPORCAP0_PIO2_5 ((unsigned int) 0x20000000)
#define SCB_PIOPORCAP0_PIO2_5_MASK ((unsigned int) 0x20000000)
#define SCB_PIOPORCAP0_PIO2_6 ((unsigned int) 0x40000000)
#define SCB_PIOPORCAP0_PIO2_6_MASK ((unsigned int) 0x40000000)
#define SCB_PIOPORCAP0_PIO2_7 ((unsigned int) 0x80000000)
#define SCB_PIOPORCAP0_PIO2_7_MASK ((unsigned int) 0x80000000)
/* PIOPORCAP1 (POR captured PIO status register 1)
The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of
one PIO pin. This register is a read-only status register. */
#define SCB_PIOPORCAP1_PIO2_8 ((unsigned int) 0x00000001)
#define SCB_PIOPORCAP1_PIO2_8_MASK ((unsigned int) 0x00000001)
#define SCB_PIOPORCAP1_PIO2_9 ((unsigned int) 0x00000002)
#define SCB_PIOPORCAP1_PIO2_9_MASK ((unsigned int) 0x00000002)
#define SCB_PIOPORCAP1_PIO2_10 ((unsigned int) 0x00000004)
#define SCB_PIOPORCAP1_PIO2_10_MASK ((unsigned int) 0x00000004)
#define SCB_PIOPORCAP1_PIO2_11 ((unsigned int) 0x00000008)
#define SCB_PIOPORCAP1_PIO2_11_MASK ((unsigned int) 0x00000008)
#define SCB_PIOPORCAP1_PIO3_0 ((unsigned int) 0x00000010)
#define SCB_PIOPORCAP1_PIO3_0_MASK ((unsigned int) 0x00000010)
#define SCB_PIOPORCAP1_PIO3_1 ((unsigned int) 0x00000020)
#define SCB_PIOPORCAP1_PIO3_1_MASK ((unsigned int) 0x00000020)
#define SCB_PIOPORCAP1_PIO3_2 ((unsigned int) 0x00000040)
#define SCB_PIOPORCAP1_PIO3_2_MASK ((unsigned int) 0x00000040)
#define SCB_PIOPORCAP1_PIO3_3 ((unsigned int) 0x00000080)
#define SCB_PIOPORCAP1_PIO3_3_MASK ((unsigned int) 0x00000080)
#define SCB_PIOPORCAP1_PIO3_4 ((unsigned int) 0x00000100)
#define SCB_PIOPORCAP1_PIO3_4_MASK ((unsigned int) 0x00000100)
#define SCB_PIOPORCAP1_PIO3_5 ((unsigned int) 0x00000200)
#define SCB_PIOPORCAP1_PIO3_5_MASK ((unsigned int) 0x00000200)
/* BODCTRL (Brown-out detection control register)
The BOD control register selects four separate threshold values for sending a BOD
interrupt to the NVIC. Only one level is allowed for forced reset. */
#define SCB_BODCTRL_RSTLEVEL_MASK ((unsigned int) 0x00000003)
#define SCB_BODCTRL_INTLEVEL_1_69V_1_84V ((unsigned int) 0x00000000)
#define SCB_BODCTRL_INTLEVEL_2_29V_2_44V ((unsigned int) 0x00000004)
#define SCB_BODCTRL_INTLEVEL_2_59V_2_74V ((unsigned int) 0x00000008)
#define SCB_BODCTRL_INTLEVEL_2_87V_2_98V ((unsigned int) 0x0000000C)
#define SCB_BODCTRL_INTLEVEL_MASK ((unsigned int) 0x0000000C)
#define SCB_BODCTRL_RSTENABLE_DISABLE ((unsigned int) 0x00000000)
#define SCB_BODCTRL_RSTENABLE_ENABLE ((unsigned int) 0x00000010)
#define SCB_BODCTRL_RSTENABLE_MASK ((unsigned int) 0x00000010)
/* SYSTCKCAL (System tick counter calibration register) */
#define SCB_SYSTICKCCAL_MASK ((unsigned int) 0x03FFFFFF) // Undefined as of v0.07 of the LPC1343 User Manual
/* STARTAPRP0 (Start logic edge control register 0)
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This
register selects a falling or rising edge on the corresponding PIO input to produce a falling
or rising clock edge, respectively, for the start logic (see Section 3Â9.3).
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc.. The bottom 32 interrupts are contained this register,
the top 8 interrupts are contained in the STARTAPRP1 register for total of 40 wake-up
interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode. */
#define SCB_STARTAPRP0_APRPIO0_0 ((unsigned int) 0x00000001)
#define SCB_STARTAPRP0_APRPIO0_0_MASK ((unsigned int) 0x00000001)
#define SCB_STARTAPRP0_APRPIO0_1 ((unsigned int) 0x00000002)
#define SCB_STARTAPRP0_APRPIO0_1_MASK ((unsigned int) 0x00000002)
#define SCB_STARTAPRP0_APRPIO0_2 ((unsigned int) 0x00000004)
#define SCB_STARTAPRP0_APRPIO0_2_MASK ((unsigned int) 0x00000004)
#define SCB_STARTAPRP0_APRPIO0_3 ((unsigned int) 0x00000008)
#define SCB_STARTAPRP0_APRPIO0_3_MASK ((unsigned int) 0x00000008)
#define SCB_STARTAPRP0_APRPIO0_4 ((unsigned int) 0x00000010)
#define SCB_STARTAPRP0_APRPIO0_4_MASK ((unsigned int) 0x00000010)
#define SCB_STARTAPRP0_APRPIO0_5 ((unsigned int) 0x00000020)
#define SCB_STARTAPRP0_APRPIO0_5_MASK ((unsigned int) 0x00000020)
#define SCB_STARTAPRP0_APRPIO0_6 ((unsigned int) 0x00000040)
#define SCB_STARTAPRP0_APRPIO0_6_MASK ((unsigned int) 0x00000040)
#define SCB_STARTAPRP0_APRPIO0_7 ((unsigned int) 0x00000080)
#define SCB_STARTAPRP0_APRPIO0_7_MASK ((unsigned int) 0x00000080)
#define SCB_STARTAPRP0_APRPIO0_8 ((unsigned int) 0x00000100)
#define SCB_STARTAPRP0_APRPIO0_8_MASK ((unsigned int) 0x00000100)
#define SCB_STARTAPRP0_APRPIO0_9 ((unsigned int) 0x00000200)
#define SCB_STARTAPRP0_APRPIO0_9_MASK ((unsigned int) 0x00000200)
#define SCB_STARTAPRP0_APRPIO0_10 ((unsigned int) 0x00000400)
#define SCB_STARTAPRP0_APRPIO0_10_MASK ((unsigned int) 0x00000400)
#define SCB_STARTAPRP0_APRPIO0_11 ((unsigned int) 0x00000800)
#define SCB_STARTAPRP0_APRPIO0_11_MASK ((unsigned int) 0x00000800)
#define SCB_STARTAPRP0_APRPIO1_0 ((unsigned int) 0x00001000)
#define SCB_STARTAPRP0_APRPIO1_0_MASK ((unsigned int) 0x00001000)
#define SCB_STARTAPRP0_APRPIO1_1 ((unsigned int) 0x00002000)
#define SCB_STARTAPRP0_APRPIO1_1_MASK ((unsigned int) 0x00002000)
#define SCB_STARTAPRP0_APRPIO1_2 ((unsigned int) 0x00004000)
#define SCB_STARTAPRP0_APRPIO1_2_MASK ((unsigned int) 0x00004000)
#define SCB_STARTAPRP0_APRPIO1_3 ((unsigned int) 0x00008000)
#define SCB_STARTAPRP0_APRPIO1_3_MASK ((unsigned int) 0x00008000)
#define SCB_STARTAPRP0_APRPIO1_4 ((unsigned int) 0x00010000)
#define SCB_STARTAPRP0_APRPIO1_4_MASK ((unsigned int) 0x00010000)
#define SCB_STARTAPRP0_APRPIO1_5 ((unsigned int) 0x00020000)
#define SCB_STARTAPRP0_APRPIO1_5_MASK ((unsigned int) 0x00020000)
#define SCB_STARTAPRP0_APRPIO1_6 ((unsigned int) 0x00040000)
#define SCB_STARTAPRP0_APRPIO1_6_MASK ((unsigned int) 0x00040000)
#define SCB_STARTAPRP0_APRPIO1_7 ((unsigned int) 0x00080000)
#define SCB_STARTAPRP0_APRPIO1_7_MASK ((unsigned int) 0x00080000)
#define SCB_STARTAPRP0_APRPIO1_8 ((unsigned int) 0x00100000)
#define SCB_STARTAPRP0_APRPIO1_8_MASK ((unsigned int) 0x00100000)
#define SCB_STARTAPRP0_APRPIO1_9 ((unsigned int) 0x00200000)
#define SCB_STARTAPRP0_APRPIO1_9_MASK ((unsigned int) 0x00200000)
#define SCB_STARTAPRP0_APRPIO1_10 ((unsigned int) 0x00400000)
#define SCB_STARTAPRP0_APRPIO1_10_MASK ((unsigned int) 0x00400000)
#define SCB_STARTAPRP0_APRPIO1_11 ((unsigned int) 0x00800000)
#define SCB_STARTAPRP0_APRPIO1_11_MASK ((unsigned int) 0x00800000)
#define SCB_STARTAPRP0_APRPIO2_0 ((unsigned int) 0x01000000)
#define SCB_STARTAPRP0_APRPIO2_0_MASK ((unsigned int) 0x01000000)
#define SCB_STARTAPRP0_APRPIO2_1 ((unsigned int) 0x02000000)
#define SCB_STARTAPRP0_APRPIO2_1_MASK ((unsigned int) 0x02000000)
#define SCB_STARTAPRP0_APRPIO2_2 ((unsigned int) 0x04000000)
#define SCB_STARTAPRP0_APRPIO2_2_MASK ((unsigned int) 0x04000000)
#define SCB_STARTAPRP0_APRPIO2_3 ((unsigned int) 0x08000000)
#define SCB_STARTAPRP0_APRPIO2_3_MASK ((unsigned int) 0x08000000)
#define SCB_STARTAPRP0_APRPIO2_4 ((unsigned int) 0x10000000)
#define SCB_STARTAPRP0_APRPIO2_4_MASK ((unsigned int) 0x10000000)
#define SCB_STARTAPRP0_APRPIO2_5 ((unsigned int) 0x20000000)
#define SCB_STARTAPRP0_APRPIO2_5_MASK ((unsigned int) 0x20000000)
#define SCB_STARTAPRP0_APRPIO2_6 ((unsigned int) 0x40000000)
#define SCB_STARTAPRP0_APRPIO2_6_MASK ((unsigned int) 0x40000000)
#define SCB_STARTAPRP0_APRPIO2_7 ((unsigned int) 0x80000000)
#define SCB_STARTAPRP0_APRPIO2_7_MASK ((unsigned int) 0x80000000)
#define SCB_STARTAPRP0_MASK ((unsigned int) 0xFFFFFFFF)
/* STARTERP0 (Start logic signal enable register 0)
This STARTERP0 register enables or disables the start signal bits in the start logic. */
#define SCB_STARTERP0_ERPIO0_0 ((unsigned int) 0x00000001)
#define SCB_STARTERP0_ERPIO0_0_MASK ((unsigned int) 0x00000001)
#define SCB_STARTERP0_ERPIO0_1 ((unsigned int) 0x00000002)
#define SCB_STARTERP0_ERPIO0_1_MASK ((unsigned int) 0x00000002)
#define SCB_STARTERP0_ERPIO0_2 ((unsigned int) 0x00000004)
#define SCB_STARTERP0_ERPIO0_2_MASK ((unsigned int) 0x00000004)
#define SCB_STARTERP0_ERPIO0_3 ((unsigned int) 0x00000008)
#define SCB_STARTERP0_ERPIO0_3_MASK ((unsigned int) 0x00000008)
#define SCB_STARTERP0_ERPIO0_4 ((unsigned int) 0x00000010)
#define SCB_STARTERP0_ERPIO0_4_MASK ((unsigned int) 0x00000010)
#define SCB_STARTERP0_ERPIO0_5 ((unsigned int) 0x00000020)
#define SCB_STARTERP0_ERPIO0_5_MASK ((unsigned int) 0x00000020)
#define SCB_STARTERP0_ERPIO0_6 ((unsigned int) 0x00000040)
#define SCB_STARTERP0_ERPIO0_6_MASK ((unsigned int) 0x00000040)
#define SCB_STARTERP0_ERPIO0_7 ((unsigned int) 0x00000080)
#define SCB_STARTERP0_ERPIO0_7_MASK ((unsigned int) 0x00000080)
#define SCB_STARTERP0_ERPIO0_8 ((unsigned int) 0x00000100)
#define SCB_STARTERP0_ERPIO0_8_MASK ((unsigned int) 0x00000100)
#define SCB_STARTERP0_ERPIO0_9 ((unsigned int) 0x00000200)
#define SCB_STARTERP0_ERPIO0_9_MASK ((unsigned int) 0x00000200)
#define SCB_STARTERP0_ERPIO0_10 ((unsigned int) 0x00000400)
#define SCB_STARTERP0_ERPIO0_10_MASK ((unsigned int) 0x00000400)
#define SCB_STARTERP0_ERPIO0_11 ((unsigned int) 0x00000800)
#define SCB_STARTERP0_ERPIO0_11_MASK ((unsigned int) 0x00000800)
#define SCB_STARTERP0_ERPIO1_0 ((unsigned int) 0x00001000)
#define SCB_STARTERP0_ERPIO1_0_MASK ((unsigned int) 0x00001000)
#define SCB_STARTERP0_ERPIO1_1 ((unsigned int) 0x00002000)
#define SCB_STARTERP0_ERPIO1_1_MASK ((unsigned int) 0x00002000)
#define SCB_STARTERP0_ERPIO1_2 ((unsigned int) 0x00004000)
#define SCB_STARTERP0_ERPIO1_2_MASK ((unsigned int) 0x00004000)
#define SCB_STARTERP0_ERPIO1_3 ((unsigned int) 0x00008000)
#define SCB_STARTERP0_ERPIO1_3_MASK ((unsigned int) 0x00008000)
#define SCB_STARTERP0_ERPIO1_4 ((unsigned int) 0x00010000)
#define SCB_STARTERP0_ERPIO1_4_MASK ((unsigned int) 0x00010000)
#define SCB_STARTERP0_ERPIO1_5 ((unsigned int) 0x00020000)
#define SCB_STARTERP0_ERPIO1_5_MASK ((unsigned int) 0x00020000)
#define SCB_STARTERP0_ERPIO1_6 ((unsigned int) 0x00040000)
#define SCB_STARTERP0_ERPIO1_6_MASK ((unsigned int) 0x00040000)
#define SCB_STARTERP0_ERPIO1_7 ((unsigned int) 0x00080000)
#define SCB_STARTERP0_ERPIO1_7_MASK ((unsigned int) 0x00080000)
#define SCB_STARTERP0_ERPIO1_8 ((unsigned int) 0x00100000)
#define SCB_STARTERP0_ERPIO1_8_MASK ((unsigned int) 0x00100000)
#define SCB_STARTERP0_ERPIO1_9 ((unsigned int) 0x00200000)
#define SCB_STARTERP0_ERPIO1_9_MASK ((unsigned int) 0x00200000)
#define SCB_STARTERP0_ERPIO1_10 ((unsigned int) 0x00400000)
#define SCB_STARTERP0_ERPIO1_10_MASK ((unsigned int) 0x00400000)
#define SCB_STARTERP0_ERPIO1_11 ((unsigned int) 0x00800000)
#define SCB_STARTERP0_ERPIO1_11_MASK ((unsigned int) 0x00800000)
#define SCB_STARTERP0_ERPIO2_0 ((unsigned int) 0x01000000)
#define SCB_STARTERP0_ERPIO2_0_MASK ((unsigned int) 0x01000000)
#define SCB_STARTERP0_ERPIO2_1 ((unsigned int) 0x02000000)
#define SCB_STARTERP0_ERPIO2_1_MASK ((unsigned int) 0x02000000)
#define SCB_STARTERP0_ERPIO2_2 ((unsigned int) 0x04000000)
#define SCB_STARTERP0_ERPIO2_2_MASK ((unsigned int) 0x04000000)
#define SCB_STARTERP0_ERPIO2_3 ((unsigned int) 0x08000000)
#define SCB_STARTERP0_ERPIO2_3_MASK ((unsigned int) 0x08000000)
#define SCB_STARTERP0_ERPIO2_4 ((unsigned int) 0x10000000)
#define SCB_STARTERP0_ERPIO2_4_MASK ((unsigned int) 0x10000000)
#define SCB_STARTERP0_ERPIO2_5 ((unsigned int) 0x20000000)
#define SCB_STARTERP0_ERPIO2_5_MASK ((unsigned int) 0x20000000)
#define SCB_STARTERP0_ERPIO2_6 ((unsigned int) 0x40000000)
#define SCB_STARTERP0_ERPIO2_6_MASK ((unsigned int) 0x40000000)
#define SCB_STARTERP0_ERPIO2_7 ((unsigned int) 0x80000000)
#define SCB_STARTERP0_ERPIO2_7_MASK ((unsigned int) 0x80000000)
#define SCB_STARTERP0_MASK ((unsigned int) 0xFFFFFFFF)
/* STARTRSRP0CLR (Start logic reset register 0)
Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The
start-up logic uses the input signals to generate a clock edge for registering a start
signal. This clock edge (falling or rising) sets the interrupt for waking up from
Deep-sleep mode. Therefore, the start-up logic states must be cleared before being used. */
#define SCB_STARTRSRP0CLR_RSRPIO0_0 ((unsigned int) 0x00000001)
#define SCB_STARTRSRP0CLR_RSRPIO0_0_MASK ((unsigned int) 0x00000001)
#define SCB_STARTRSRP0CLR_RSRPIO0_1 ((unsigned int) 0x00000002)
#define SCB_STARTRSRP0CLR_RSRPIO0_1_MASK ((unsigned int) 0x00000002)
#define SCB_STARTRSRP0CLR_RSRPIO0_2 ((unsigned int) 0x00000004)
#define SCB_STARTRSRP0CLR_RSRPIO0_2_MASK ((unsigned int) 0x00000004)
#define SCB_STARTRSRP0CLR_RSRPIO0_3 ((unsigned int) 0x00000008)
#define SCB_STARTRSRP0CLR_RSRPIO0_3_MASK ((unsigned int) 0x00000008)
#define SCB_STARTRSRP0CLR_RSRPIO0_4 ((unsigned int) 0x00000010)
#define SCB_STARTRSRP0CLR_RSRPIO0_4_MASK ((unsigned int) 0x00000010)
#define SCB_STARTRSRP0CLR_RSRPIO0_5 ((unsigned int) 0x00000020)
#define SCB_STARTRSRP0CLR_RSRPIO0_5_MASK ((unsigned int) 0x00000020)
#define SCB_STARTRSRP0CLR_RSRPIO0_6 ((unsigned int) 0x00000040)
#define SCB_STARTRSRP0CLR_RSRPIO0_6_MASK ((unsigned int) 0x00000040)
#define SCB_STARTRSRP0CLR_RSRPIO0_7 ((unsigned int) 0x00000080)
#define SCB_STARTRSRP0CLR_RSRPIO0_7_MASK ((unsigned int) 0x00000080)
#define SCB_STARTRSRP0CLR_RSRPIO0_8 ((unsigned int) 0x00000100)
#define SCB_STARTRSRP0CLR_RSRPIO0_8_MASK ((unsigned int) 0x00000100)
#define SCB_STARTRSRP0CLR_RSRPIO0_9 ((unsigned int) 0x00000200)
#define SCB_STARTRSRP0CLR_RSRPIO0_9_MASK ((unsigned int) 0x00000200)
#define SCB_STARTRSRP0CLR_RSRPIO0_10 ((unsigned int) 0x00000400)
#define SCB_STARTRSRP0CLR_RSRPIO0_10_MASK ((unsigned int) 0x00000400)
#define SCB_STARTRSRP0CLR_RSRPIO0_11 ((unsigned int) 0x00000800)
#define SCB_STARTRSRP0CLR_RSRPIO0_11_MASK ((unsigned int) 0x00000800)
#define SCB_STARTRSRP0CLR_RSRPIO1_0 ((unsigned int) 0x00001000)
#define SCB_STARTRSRP0CLR_RSRPIO1_0_MASK ((unsigned int) 0x00001000)
#define SCB_STARTRSRP0CLR_RSRPIO1_1 ((unsigned int) 0x00002000)
#define SCB_STARTRSRP0CLR_RSRPIO1_1_MASK ((unsigned int) 0x00002000)
#define SCB_STARTRSRP0CLR_RSRPIO1_2 ((unsigned int) 0x00004000)
#define SCB_STARTRSRP0CLR_RSRPIO1_2_MASK ((unsigned int) 0x00004000)
#define SCB_STARTRSRP0CLR_RSRPIO1_3 ((unsigned int) 0x00008000)
#define SCB_STARTRSRP0CLR_RSRPIO1_3_MASK ((unsigned int) 0x00008000)
#define SCB_STARTRSRP0CLR_RSRPIO1_4 ((unsigned int) 0x00010000)
#define SCB_STARTRSRP0CLR_RSRPIO1_4_MASK ((unsigned int) 0x00010000)
#define SCB_STARTRSRP0CLR_RSRPIO1_5 ((unsigned int) 0x00020000)
#define SCB_STARTRSRP0CLR_RSRPIO1_5_MASK ((unsigned int) 0x00020000)
#define SCB_STARTRSRP0CLR_RSRPIO1_6 ((unsigned int) 0x00040000)
#define SCB_STARTRSRP0CLR_RSRPIO1_6_MASK ((unsigned int) 0x00040000)
#define SCB_STARTRSRP0CLR_RSRPIO1_7 ((unsigned int) 0x00080000)
#define SCB_STARTRSRP0CLR_RSRPIO1_7_MASK ((unsigned int) 0x00080000)
#define SCB_STARTRSRP0CLR_RSRPIO1_8 ((unsigned int) 0x00100000)
#define SCB_STARTRSRP0CLR_RSRPIO1_8_MASK ((unsigned int) 0x00100000)
#define SCB_STARTRSRP0CLR_RSRPIO1_9 ((unsigned int) 0x00200000)
#define SCB_STARTRSRP0CLR_RSRPIO1_9_MASK ((unsigned int) 0x00200000)
#define SCB_STARTRSRP0CLR_RSRPIO1_10 ((unsigned int) 0x00400000)
#define SCB_STARTRSRP0CLR_RSRPIO1_10_MASK ((unsigned int) 0x00400000)
#define SCB_STARTRSRP0CLR_RSRPIO1_11 ((unsigned int) 0x00800000)
#define SCB_STARTRSRP0CLR_RSRPIO1_11_MASK ((unsigned int) 0x00800000)
#define SCB_STARTRSRP0CLR_RSRPIO2_0 ((unsigned int) 0x01000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_0_MASK ((unsigned int) 0x01000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_1 ((unsigned int) 0x02000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_1_MASK ((unsigned int) 0x02000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_2 ((unsigned int) 0x04000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_2_MASK ((unsigned int) 0x04000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_3 ((unsigned int) 0x08000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_3_MASK ((unsigned int) 0x08000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_4 ((unsigned int) 0x10000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_4_MASK ((unsigned int) 0x10000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_5 ((unsigned int) 0x20000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_5_MASK ((unsigned int) 0x20000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_6 ((unsigned int) 0x40000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_6_MASK ((unsigned int) 0x40000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_7 ((unsigned int) 0x80000000)
#define SCB_STARTRSRP0CLR_RSRPIO2_7_MASK ((unsigned int) 0x80000000)
#define SCB_STARTRSRP0CLR_MASK ((unsigned int) 0xFFFFFFFF)
/* (Start logic status register 0)
This register reflects the status of the enabled start signal bits. Each bit
(if enabled) reflects the state of the start logic, i.e. whether or not a
wake-up signal has been received for a given pin. */
#define SCB_STARTSRP0_SRPIO0_0 ((unsigned int) 0x00000001)
#define SCB_STARTSRP0_SRPIO0_0_MASK ((unsigned int) 0x00000001)
#define SCB_STARTSRP0_SRPIO0_1 ((unsigned int) 0x00000002)