From 87f2bcdbbf436665cb812f812109cf8e85313ab3 Mon Sep 17 00:00:00 2001 From: Eldred Habert Date: Thu, 16 Oct 2025 03:39:46 +0200 Subject: [PATCH] Document NR43 values freezing the channel Turns out EVER and ETOV are not connected to ETYR (https://github.com/furrtek/DMG-CPU-Inside/blob/master/Schematics/20_CHANNEL4.png) which means that 14 and 15 don't select any clock source at all, freezing the channel. --- src/Audio_Registers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Audio_Registers.md b/src/Audio_Registers.md index 8ddf19c1..90fcbf23 100644 --- a/src/Audio_Registers.md +++ b/src/Audio_Registers.md @@ -402,7 +402,7 @@ This register allows controlling the way the amplitude is randomly switched. - **Clock divider**: See the frequency formula below. Note that divider = 0 is treated as divider = 0.5 instead. -The frequency at which the LFSR is clocked is 262144divider×2shift Hz. +The frequency at which the LFSR is clocked is 262144divider×2shift Hz, except that shift being equal to 14 or 15 stops the channel from being clocked entirely. If the bit shifted out is a 0, the channel emits a 0; otherwise, it emits the volume selected in `NR42`.