Merge remote-tracking branch 'origin/sycl' into abi/submission_info

Author: againull

.github/workflows/sycl-ur-perf-benchmarking.yml

@@ -24,6 +24,7 @@ on:
           - Full
           - SYCL
           - Minimal
+          - Core
           - Normal
           - Test
           - Gromacs

clang/test/Driver/sycl-offload-new-driver.c

@@ -237,7 +237,7 @@
 
 // Verify for multiple targets with -Xsycl-target-backend= with commas in the values
 // are passed correctly to llvm-offload-binary.
-// RUN: %clangxx -fsycl -### --offload-new-driver \
+// RUN: %clangxx -fsycl -### --offload-new-driver -fno-sycl-libspirv \
 // RUN:  -fsycl-targets=nvptx64-nvidia-cuda,amdgcn-amd-amdhsa,spir64_gen \
 // RUN:  -Xsycl-target-backend=amdgcn-amd-amdhsa --offload-arch=gfx908,gfx1010 \
 // RUN:  -Xsycl-target-backend=nvptx64-nvidia-cuda --offload-arch=sm_86,sm_87,sm_89 \

devops/scripts/benchmarks/README.md

@@ -115,6 +115,7 @@ The available benchmarks options are:
 * `Full` (BenchDNN, Compute, Gromacs, llama, SYCL, Velocity and UMF benchmarks)
 * `SYCL` (Compute, llama, SYCL, Velocity)
 * `Minimal` (Compute)
+* `Core` (Compute: SubmitKernel)
 * `Normal` (BenchDNN, Compute, Gromacs, llama, Velocity)
 * `Gromacs` (Gromacs)
 * `OneDNN` (BenchDNN)

devops/scripts/benchmarks/benches/compute.py

@@ -353,6 +353,41 @@ def createRrBench(variant_name: str, **kwargs):
         return benches
 
 
+class ComputeBenchCoreSuite(ComputeBench):
+    """
+    A suite for core compute benchmarks scenarios for quick runs.
+    """
+
+    def name(self) -> str:
+        return "Compute Benchmarks Core"
+
+    def benchmarks(self) -> list[Benchmark]:
+        core_benches = []
+        submit_kernel_params = product(
+            list(RUNTIMES),
+            [0, 1],  # in_order_queue
+            [0, 1],  # measure_completion
+            [0, 1],  # use_events
+        )
+        for (
+            runtime,
+            in_order_queue,
+            measure_completion,
+            use_events,
+        ) in submit_kernel_params:
+            core_benches.append(
+                SubmitKernel(
+                    self,
+                    runtime,
+                    in_order_queue,
+                    measure_completion,
+                    use_events,
+                    KernelExecTime=1,
+                )
+            )
+        return core_benches
+
+
 class ComputeBenchmark(Benchmark):
     def __init__(
         self,

devops/scripts/benchmarks/compare.py

@@ -411,7 +411,7 @@ def print_regression(entry: dict, is_warning: bool = False):
             log_func(f"-- Delta: {entry['delta']}")
             log_func("")
             if args.produce_github_summary:
-                gh_summary.append(f"#### {entry['name']}:")
+                gh_summary.append(f"##### {entry['name']}:")
                 gh_summary.append(
                     f"- Historic {entry['avg_type']}: {entry['hist_avg']}"
                 )
@@ -427,12 +427,16 @@ def print_regression(entry: dict, is_warning: bool = False):
                 )
                 gh_summary.append("")
 
+        if args.produce_github_summary:
+            gh_summary.append("")
+            gh_summary.append("### Regressions and Improvements")
+
         if improvements:
             log.info("#")
             log.info("# Improvements:")
             log.info("#")
             if args.produce_github_summary:
-                gh_summary.append(f"### Improvements")
+                gh_summary.append(f"#### Improvements")
                 gh_summary.append(
                     f"<details><summary>{len(improvements)} improved tests:</summary>"
                 )
@@ -444,12 +448,16 @@ def print_regression(entry: dict, is_warning: bool = False):
                 gh_summary.append("")
         if regressions_ignored:
             log.info("#")
-            log.info("# Regressions (filtered out by --regression-filter):")
+            log.info(
+                f"# Regressions Ignored (filtered out by --regression-filter: {filter_type_capitalized})"
+            )
             log.info("#")
             if args.produce_github_summary:
-                gh_summary.append(f"### Non-{filter_type_capitalized} Regressions")
                 gh_summary.append(
-                    f"<details><summary>{len(regressions_ignored)} non-{args.regression_filter_type} regressions:</summary>"
+                    f"#### Regressions Ignored (filtered out by --regression-filter: {filter_type_capitalized})"
+                )
+                gh_summary.append(
+                    f"<details><summary>{len(regressions_ignored)} non-'{args.regression_filter_type}' regressions:</summary>"
                 )
                 gh_summary.append("")
             for test in regressions_ignored:
@@ -462,7 +470,7 @@ def print_regression(entry: dict, is_warning: bool = False):
             log.warning("# Regressions:")
             log.warning("#")
             if args.produce_github_summary:
-                gh_summary.append(f"### {filter_type_capitalized} Regressions")
+                gh_summary.append(f"#### {filter_type_capitalized} Regressions")
                 gh_summary.append(
                     f"{len(regressions_of_concern)} {args.regression_filter_type} regressions. These regressions warrant a CI failure:"
                 )
@@ -480,8 +488,6 @@ def print_regression(entry: dict, is_warning: bool = False):
 
         log.info("No unexpected regressions found!")
         if args.produce_github_summary:
-            gh_summary.append("")
-            gh_summary.append("### Regressions")
             gh_summary.append("No unexpected regressions found!")
             with open(options.github_summary_regression_filename, "w") as f:
                 f.write("\n".join(gh_summary))

devops/scripts/benchmarks/main.py

@@ -269,6 +269,7 @@ def main(directory, additional_env_vars, compare_names, filter, execution_stats)
 
     suites = [
         ComputeBench(),
+        ComputeBenchCoreSuite(),
         VelocityBench(),
         SyclBench(),
         LlamaCppBench(),

devops/scripts/benchmarks/presets.py

@@ -26,6 +26,9 @@
     "Minimal": [
         "Compute Benchmarks",
     ],
+    "Core": [
+        "Compute Benchmarks Core",
+    ],
     "Normal": [
         "BenchDNN",
         "Compute Benchmarks",

llvm/lib/SYCLLowerIR/CompileTimePropertiesPass.cpp

@@ -27,24 +27,21 @@ using namespace llvm;
 
 namespace {
 
-constexpr StringRef SYCL_HOST_ACCESS_ATTR = "sycl-host-access";
-constexpr StringRef SYCL_PIPELINED_ATTR = "sycl-pipelined";
-constexpr StringRef SYCL_REGISTER_ALLOC_MODE_ATTR = "sycl-register-alloc-mode";
-constexpr StringRef SYCL_GRF_SIZE_ATTR = "sycl-grf-size";
+constexpr StringRef SyclHostAccessAttr = "sycl-host-access";
+constexpr StringRef SyclPipelinedAttr = "sycl-pipelined";
+constexpr StringRef SyclRegisterAllocModeAttr = "sycl-register-alloc-mode";
+constexpr StringRef SyclGrfSizeAttr = "sycl-grf-size";
 
-constexpr StringRef SPIRV_DECOR_MD_KIND = "spirv.Decorations";
-constexpr StringRef SPIRV_PARAM_DECOR_MD_KIND = "spirv.ParameterDecorations";
+constexpr StringRef SpirvDecorMdKind = "spirv.Decorations";
+constexpr StringRef SpirvParamDecorMdKind = "spirv.ParameterDecorations";
 // The corresponding SPIR-V OpCode for the host_access property is documented
 // in the SPV_INTEL_global_variable_decorations design document:
 // https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/DeviceGlobal/SPV_INTEL_global_variable_decorations.asciidoc#decoration
-constexpr uint32_t SPIRV_HOST_ACCESS_DECOR = 6147;
-constexpr uint32_t SPIRV_HOST_ACCESS_DEFAULT_VALUE = 2; // Read/Write
+constexpr uint32_t SpirvHostAccessDecor = 6147;
+constexpr uint32_t SpirvHostAccessDefaultValue = 2; // Read/Write
 
-constexpr uint32_t SPIRV_INITIATION_INTERVAL_DECOR = 5917;
-constexpr uint32_t SPIRV_PIPELINE_ENABLE_DECOR = 5919;
-
-constexpr uint32_t SPIRV_CACHE_CONTROL_READ_DECOR = 6442;
-constexpr uint32_t SPIRV_CACHE_CONTROL_WRITE_DECOR = 6443;
+constexpr uint32_t SpirvInitiationIntervalDecor = 5917;
+constexpr uint32_t SpirvPipelineEnableDecor = 5919;
 
 enum class DecorValueTy {
   uint32,
@@ -89,12 +86,12 @@ enum FloatControlMask {
 // These opcodes are specified in SPIRV specification (SPV_KHR_float_controls
 // and SPV_INTEL_float_controls2 extensions):
 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.pdf
-constexpr uint32_t SPIRV_ROUNDING_MODE_RTE = 4462;       // RoundingModeRTE
-constexpr uint32_t SPIRV_ROUNDING_MODE_RTZ = 4463;       // RoundingModeRTZ
-constexpr uint32_t SPIRV_ROUNDING_MODE_RTP_INTEL = 5620; // RoundingModeRTPINTEL
-constexpr uint32_t SPIRV_ROUNDING_MODE_RTN_INTEL = 5621; // RoundingModeRTNINTEL
-constexpr uint32_t SPIRV_DENORM_FLUSH_TO_ZERO = 4460;    // DenormFlushToZero
-constexpr uint32_t SPIRV_DENORM_PRESERVE = 4459;         // DenormPreserve
+constexpr uint32_t SpirvRoundingModeRte = 4462;      // RoundingModeRTE
+constexpr uint32_t SpirvRoundingModeRtz = 4463;      // RoundingModeRTZ
+constexpr uint32_t SpirvRoundingModeRtpIntel = 5620; // RoundingModeRTPINTEL
+constexpr uint32_t SpirvRoundingModeRtnIntel = 5621; // RoundingModeRTNINTEL
+constexpr uint32_t SpirvDenormFlushToZero = 4460;    // DenormFlushToZero
+constexpr uint32_t SpirvDenormPreserve = 4459;       // DenormPreserve
 
 /// Builds a metadata node for a SPIR-V decoration (decoration code is
 /// \c uint32_t integers) with no value.
@@ -147,15 +144,15 @@ MDNode *buildSpirvDecorCacheProp(LLVMContext &Ctx, StringRef Name,
                                  uint32_t OpCode, uint32_t CacheMode,
                                  uint32_t CacheLevel) {
   // SPIR-V encodings of read control
-  enum cache_control_read_type {
+  enum CacheControlReadType {
     read_uncached = 0,
     read_cached = 1,
     read_streaming = 2,
     read_invalidate = 3,
     read_const_cached = 4
   };
   // SPIR-V encodings of write control
-  enum cache_control_write_type {
+  enum CacheControlWriteType {
     write_uncached = 0,
     write_through = 1,
     write_back = 2,
@@ -338,28 +335,28 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
     };
 
     if (IsFPModeSet(RTE))
-      AddFPControlMetadata(SPIRV_ROUNDING_MODE_RTE);
+      AddFPControlMetadata(SpirvRoundingModeRte);
 
     if (IsFPModeSet(RTP))
-      AddFPControlMetadata(SPIRV_ROUNDING_MODE_RTP_INTEL);
+      AddFPControlMetadata(SpirvRoundingModeRtpIntel);
 
     if (IsFPModeSet(RTN))
-      AddFPControlMetadata(SPIRV_ROUNDING_MODE_RTN_INTEL);
+      AddFPControlMetadata(SpirvRoundingModeRtnIntel);
 
     if (IsFPModeSet(RTZ))
-      AddFPControlMetadata(SPIRV_ROUNDING_MODE_RTZ);
+      AddFPControlMetadata(SpirvRoundingModeRtz);
 
     if (IsFPModeSet(DENORM_FTZ))
-      AddFPControlMetadata(SPIRV_DENORM_FLUSH_TO_ZERO);
+      AddFPControlMetadata(SpirvDenormFlushToZero);
 
     if (IsFPModeSet(DENORM_HF_ALLOW))
-      AddFPControlMetadataForWidth(SPIRV_DENORM_PRESERVE, 16);
+      AddFPControlMetadataForWidth(SpirvDenormPreserve, 16);
 
     if (IsFPModeSet(DENORM_F_ALLOW))
-      AddFPControlMetadataForWidth(SPIRV_DENORM_PRESERVE, 32);
+      AddFPControlMetadataForWidth(SpirvDenormPreserve, 32);
 
     if (IsFPModeSet(DENORM_D_ALLOW))
-      AddFPControlMetadataForWidth(SPIRV_DENORM_PRESERVE, 64);
+      AddFPControlMetadataForWidth(SpirvDenormPreserve, 64);
   }
 
   static constexpr std::tuple<const char *, const char *> SimpleWGAttrs[] = {
@@ -483,12 +480,12 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
                                             MDNode::get(Ctx, ClusterMDArgs));
   }
 
-  if ((AttrKindStr == SYCL_REGISTER_ALLOC_MODE_ATTR ||
-       AttrKindStr == SYCL_GRF_SIZE_ATTR) &&
+  if ((AttrKindStr == SyclRegisterAllocModeAttr ||
+       AttrKindStr == SyclGrfSizeAttr) &&
       !llvm::esimd::isESIMD(F)) {
     // TODO: Remove SYCL_REGISTER_ALLOC_MODE_ATTR support in next ABI break.
     uint32_t PropVal = getAttributeAsInteger<uint32_t>(Attr);
-    if (AttrKindStr == SYCL_GRF_SIZE_ATTR) {
+    if (AttrKindStr == SyclGrfSizeAttr) {
       // The RegisterAllocMode metadata supports only 0, 128, and 256 for
       // PropVal.
       if (PropVal != 0 && PropVal != 128 && PropVal != 256)
@@ -570,9 +567,9 @@ void getUserListIgnoringCast(
 PreservedAnalyses CompileTimePropertiesPass::run(Module &M,
                                                  ModuleAnalysisManager &MAM) {
   LLVMContext &Ctx = M.getContext();
-  unsigned MDKindID = Ctx.getMDKindID(SPIRV_DECOR_MD_KIND);
+  unsigned MDKindID = Ctx.getMDKindID(SpirvDecorMdKind);
   bool CompileTimePropertiesMet = false;
-  unsigned MDParamKindID = Ctx.getMDKindID(SPIRV_PARAM_DECOR_MD_KIND);
+  unsigned MDParamKindID = Ctx.getMDKindID(SpirvParamDecorMdKind);
 
   // Let's process all the globals
   for (auto &GV : M.globals()) {
@@ -594,19 +591,18 @@ PreservedAnalyses CompileTimePropertiesPass::run(Module &M,
     // of the variable.
     if (isDeviceGlobalVariable(GV)) {
       auto HostAccessDecorValue =
-          GV.hasAttribute(SYCL_HOST_ACCESS_ATTR)
-              ? getAttributeAsInteger<uint32_t>(GV, SYCL_HOST_ACCESS_ATTR)
-              : SPIRV_HOST_ACCESS_DEFAULT_VALUE;
+          GV.hasAttribute(SyclHostAccessAttr)
+              ? getAttributeAsInteger<uint32_t>(GV, SyclHostAccessAttr)
+              : SpirvHostAccessDefaultValue;
       auto VarName = getGlobalVariableUniqueId(GV);
-      MDOps.push_back(buildSpirvDecorMetadata(Ctx, SPIRV_HOST_ACCESS_DECOR,
+      MDOps.push_back(buildSpirvDecorMetadata(Ctx, SpirvHostAccessDecor,
                                               HostAccessDecorValue, VarName));
     }
 
     if (isHostPipeVariable(GV)) {
       auto VarName = getGlobalVariableUniqueId(GV);
-      MDOps.push_back(buildSpirvDecorMetadata(Ctx, SPIRV_HOST_ACCESS_DECOR,
-                                              SPIRV_HOST_ACCESS_DEFAULT_VALUE,
-                                              VarName));
+      MDOps.push_back(buildSpirvDecorMetadata(
+          Ctx, SpirvHostAccessDecor, SpirvHostAccessDefaultValue, VarName));
     }
 
     // Add the generated metadata to the variable
@@ -668,26 +664,25 @@ PreservedAnalyses CompileTimePropertiesPass::run(Module &M,
     for (const Attribute &Attribute : F.getAttributes().getFnAttrs()) {
       // Handle pipelined attribute as a special case.
       if (Attribute.isStringAttribute() &&
-          Attribute.getKindAsString() == SYCL_PIPELINED_ATTR) {
+          Attribute.getKindAsString() == SyclPipelinedAttr) {
         auto PipelineOrInitiationInterval =
             getAttributeAsInteger<int32_t>(Attribute);
         MDNode *SPIRVMetadata;
         if (PipelineOrInitiationInterval < 0) {
           // Default pipelining desired
           SPIRVMetadata =
-              buildSpirvDecorMetadata(Ctx, SPIRV_PIPELINE_ENABLE_DECOR, 1);
+              buildSpirvDecorMetadata(Ctx, SpirvPipelineEnableDecor, 1);
         } else if (PipelineOrInitiationInterval == 0) {
           // No pipelining desired
           SPIRVMetadata =
-              buildSpirvDecorMetadata(Ctx, SPIRV_PIPELINE_ENABLE_DECOR, 0);
+              buildSpirvDecorMetadata(Ctx, SpirvPipelineEnableDecor, 0);
         } else {
           // Pipelining desired, with specified Initiation Interval
           SPIRVMetadata =
-              buildSpirvDecorMetadata(Ctx, SPIRV_PIPELINE_ENABLE_DECOR, 1);
+              buildSpirvDecorMetadata(Ctx, SpirvPipelineEnableDecor, 1);
           MDOps.push_back(SPIRVMetadata);
-          SPIRVMetadata =
-              buildSpirvDecorMetadata(Ctx, SPIRV_INITIATION_INTERVAL_DECOR,
-                                      PipelineOrInitiationInterval);
+          SPIRVMetadata = buildSpirvDecorMetadata(
+              Ctx, SpirvInitiationIntervalDecor, PipelineOrInitiationInterval);
         }
         MDOps.push_back(SPIRVMetadata);
       } else if (MDNode *SPIRVMetadata =
@@ -946,7 +941,7 @@ bool CompileTimePropertiesPass::transformSYCLPropertiesAnnotation(
 
   if (CacheProp) {
     LLVMContext &Ctx = M.getContext();
-    unsigned MDKindID = Ctx.getMDKindID(SPIRV_DECOR_MD_KIND);
+    unsigned MDKindID = Ctx.getMDKindID(SpirvDecorMdKind);
     if (!FPGAProp && llvm::isa<llvm::Instruction>(IntrInst->getArgOperand(0))) {
       // If there are no annotations other than cache controls we can apply the
       // controls to the pointer and remove the intrinsic.

sycl/doc/EnvironmentVariables.md

@@ -272,6 +272,8 @@ older hardware or when SYCL_UR_USE_LEVEL_ZERO_V2=0 is set.</span>
 | Environment variable | Values | Description | Adapter Support |
 | -------------------- | ------ | ----------- | --------------- |
 | `UR_L0_V2_FORCE_DISABLE_COPY_OFFLOAD` | Integer | By default, copy operations submitted to any queue can be offloaded to dedicated copy engines. Setting this variable instructs the driver to keep all copy operations on the engine behind the original queue. The default value is 0. | V2 |
+| `UR_L0_V2_DISABLE_ZE_LAUNCH_KERNEL_WITH_ARGS` | Integer | By default, `ZeCommandListAppendLaunchKernelWithArguments()` will be called. Setting this variable instructs the adapter to not call `ZeCommandListAppendLaunchKernelWithArguments()` and use the old path using `ZeCommandListAppendLaunchKernel()`. The default value is 0. | V2 |
+| `UR_L0_V2_FORCE_BATCHED` | Any(\*) | Adds UR_QUEUE_FLAG_SUBMISSION_BATCHED flag to the flags passed to urQueueCreate as arguments. The variable does not overwrite other passed flags, therefore invalid combinations (such as setting both UR_QUEUE_FLAG_SUBMISSION_IMMEDIATE and UR_QUEUE_FLAG_SUBMISSION_BATCHED) are possible. | V2 |
 | `SYCL_PI_LEVEL_ZERO_SINGLE_THREAD_MODE` | Integer | A single-threaded app has an opportunity to enable this mode to avoid overhead from mutex locking in the Level Zero adapter. A value greater than 0 enables single thread mode. A value of 0 disables single thread mode. The default is 0. | Legacy |
 | `SYCL_PI_LEVEL_ZERO_USM_ALLOCATOR` | [EnableBuffers][;[MaxPoolSize][;[host\|device\|shared:][MaxPoolableSize][,[Capacity][,SlabMinSize]]]...] | EnableBuffers enables pooling for SYCL buffers, default 1, set to 0 to disable. MaxPoolSize is the maximum size of the pool, by default there is no size limit. MemType is host, device, shared or read_only_shared. Other parameters are values specified as positive integers with optional K, M or G suffix. MaxPoolableSize is the maximum allocation size that may be pooled, default 0 for shared, 2MB for host, 4MB for device and read_only_shared. Capacity is the number of allocations in each size range freed by the program but retained in the pool for reallocation, default 4. Size ranges follow this pattern: 64, 96, 128, 192, and so on, i.e., powers of 2, with one range in between. SlabMinSize is the minimum allocation size, 64KB for host and device, 2MB for shared and read_only_shared. Example: SYCL_PI_LEVEL_ZERO_USM_ALLOCATOR=1;32M;host:1M,4,64K;device:1M,4,64K;shared:0,0,2M| Legacy and V2 |
 | `SYCL_PI_LEVEL_ZERO_BATCH_SIZE` | Integer | Sets a preferred number of compute commands to batch into a command list before executing the command list. A value of 0 causes the batch size to be adjusted dynamically. A value greater than 0 specifies fixed size batching, with the batch size set to the specified value. The default is 0. | Legacy |
@@ -292,6 +294,8 @@ older hardware or when SYCL_UR_USE_LEVEL_ZERO_V2=0 is set.</span>
 | `SYCL_PI_LEVEL_ZERO_USM_RESIDENT` | Integer | Bit-mask controls if/where to make USM allocations resident at the time of allocation. Input value is of the form 0xHSD, where 4-bits of D control device allocations, 4-bits of S control shared allocations, and 4-bits of H control host allocations. Each 4-bit component is holding one of the following values: "0" - then no special residency is forced, "1" - then allocation is made resident at the device of allocation, or "2" - then allocation is made resident on all devices in the context of allocation that have P2P access to the device of allocation. Default is 0x002, i.e. force full residency for device allocations only. | Legacy |
 | `SYCL_PI_LEVEL_ZERO_USE_NATIVE_USM_MEMCPY2D` | Integer | When set to a positive value enables the use of Level Zero USM 2D memory copy operations. Default is 0. | Legacy |
 
+`(*) Note: Any means this environment variable is effective when set to any non-null value.`
+
 ## Debugging variables for CUDA Adapter
 
 :warning: **Warning:** <span style="color:red">the environment variables