Ningbo University Hardware Design Course — MIPS-like CPU

CPU32.bdf is the top-level schematic for the single-cycle CPU, while CPU32_MC.bdf is the multi-cycle version. Instruction decoding and control signal generation are separated into two modules: IDU.bdf is shared by both the single-cycle and multi-cycle versions, CTU.bdf is the control unit for the single-cycle version, and CTU_MC.bdf is the control unit for the multi-cycle version.

In the multi-cycle version, instead of a hardwired control design, we use a timing unit TU.bdf for stage generation. Instructions and ALU results are buffered so that the same instruction can generate different control signals at different stages — this approach is more flexible and easier to debug.

A Toy Compiler

A toy compiler for this CPU, written in JavaScript (compiler.js). It compiles ARM-like assembly into the CPU's machine code (.mif format).

Assembly Programs

The assembly programs are instr.mif and instr_final.mif (compiled directly into the ROM and flashed to the FPGA board). See instr_final.txt for the corresponding ARM-like assembly source.

FPGA Design

There are two FPGA top-level designs: FPGA_SC.bdf for the single-cycle version and FPGA_MC.bdf for the multi-cycle version.

The 7-segment display decoder is in SSD.bdf.

Report

For more details, see report.pdf (note: heavy LLM usage means accuracy is not guaranteed).