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16 | 16 | #include "driver/spi_master.h" |
17 | 17 | #include "freertos/FreeRTOS.h" |
18 | 18 | #include "freertos/task.h" |
19 | | - #include "esp_check.h |
| 19 | + #include "esp_check.h" |
20 | 20 |
|
21 | 21 | static void _reset_gpios(int64_t gpio_mask) |
22 | 22 | { |
|
46 | 46 | ARG_sda, |
47 | 47 | ARG_cs, |
48 | 48 | ARG_freq, |
49 | | - ARG_polarity |
50 | | - ARG_phase |
51 | | - ARG_use_dc_bit |
52 | | - ARG_dc_data_high |
53 | | - ARG_lsb_first |
54 | | - ARG_cs_active_high |
55 | | - ARG_del_keep_cs_active |
| 49 | + ARG_polarity, |
| 50 | + ARG_phase, |
| 51 | + ARG_use_dc_bit, |
| 52 | + ARG_dc_data_high, |
| 53 | + ARG_lsb_first, |
| 54 | + ARG_cs_active_high, |
| 55 | + ARG_del_keep_cs_active, |
56 | 56 | }; |
57 | 57 |
|
58 | 58 | const mp_arg_t make_new_args[] = { |
59 | 59 | { MP_QSTR_scl, MP_ARG_INT | MP_ARG_KW_ONLY | MP_ARG_REQUIRED }, |
60 | 60 | { MP_QSTR_sda, MP_ARG_INT | MP_ARG_KW_ONLY | MP_ARG_REQUIRED }, |
61 | 61 | { MP_QSTR_cs, MP_ARG_INT | MP_ARG_KW_ONLY | MP_ARG_REQUIRED }, |
62 | | - { MP_QSTR_freq, MP_ARG_INT | MP_ARG_KW_ONLY, { .u_int = LCD_SPI_3WIRE_CLK_MAX } }, |
| 62 | + { MP_QSTR_freq, MP_ARG_INT | MP_ARG_KW_ONLY, { .u_int = SPI_3WIRE_CLK_MAX } }, |
63 | 63 | { MP_QSTR_polarity, MP_ARG_INT | MP_ARG_KW_ONLY, { .u_int = 0 } }, |
64 | 64 | { MP_QSTR_phase, MP_ARG_INT | MP_ARG_KW_ONLY, { .u_int = 0 } }, |
65 | 65 | { MP_QSTR_use_dc_bit, MP_ARG_BOOL | MP_ARG_KW_ONLY, { .u_bool = false } }, |
|
86 | 86 | self->scl_half_period_us = 1000000 / ((uint32_t)args[ARG_freq].u_int * 2); |
87 | 87 |
|
88 | 88 | if ((bool)args[ARG_use_dc_bit].u_bool) { |
89 | | - self->param_dc_bit = (bool)args[ARG_dc_data_high].u_bool ? LCD_SPI_3WIRE_DATA_DC_BIT_1 : LCD_SPI_3WIRE_DATA_DC_BIT_0; |
90 | | - self->cmd_dc_bit = (bool)args[ARG_dc_data_high].u_bool ? LCD_SPI_3WIRE_DATA_DC_BIT_0 : LCD_SPI_3WIRE_DATA_DC_BIT_1; |
| 89 | + self->param_dc_bit = (bool)args[ARG_dc_data_high].u_bool ? SPI_3WIRE_DATA_DC_BIT_1 : SPI_3WIRE_DATA_DC_BIT_0; |
| 90 | + self->cmd_dc_bit = (bool)args[ARG_dc_data_high].u_bool ? SPI_3WIRE_DATA_DC_BIT_0 : SPI_3WIRE_DATA_DC_BIT_1; |
91 | 91 | } else { |
92 | | - self->param_dc_bit = LCD_SPI_3WIRE_DATA_NO_DC_BIT; |
93 | | - self->cmd_dc_bit = LCD_SPI_3WIRE_DATA_NO_DC_BIT; |
| 92 | + self->param_dc_bit = SPI_3WIRE_DATA_NO_DC_BIT; |
| 93 | + self->cmd_dc_bit = SPI_3WIRE_DATA_NO_DC_BIT; |
94 | 94 | } |
95 | 95 |
|
96 | | - self->write_order_mask = (bool)args[ARG_lsb_first].u_bool ? LCD_SPI_3WIRE_WRITE_ORDER_LSB_MASK : LCD_SPI_3WIRE_WRITE_ORDER_MSB_MASK; |
97 | | - self->cs_high_active = (int)args[ARG_cs_active_high].u_bool |
| 96 | + self->write_order_mask = (bool)args[ARG_lsb_first].u_bool ? SPI_3WIRE_WRITE_ORDER_LSB_MASK : SPI_3WIRE_WRITE_ORDER_MSB_MASK; |
| 97 | + self->cs_high_active = (int)args[ARG_cs_active_high].u_bool; |
98 | 98 | self->del_keep_cs_inactive = (bool)args[ARG_del_keep_cs_active].u_bool ? 0 : 1; |
99 | 99 |
|
100 | 100 | uint32_t spi_mode = (uint32_t)args[ARG_phase].u_int | ((uint32_t)args[ARG_polarity].u_int << 1); |
|
184 | 184 | } |
185 | 185 |
|
186 | 186 |
|
187 | | - static mp_obj_t lcd_spi_3wire_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) |
| 187 | + static mp_obj_t spi_3wire_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) |
188 | 188 | { |
189 | 189 | enum { ARG_self, ARG_cmd_bits, ARG_param_bits }; |
190 | 190 | const mp_arg_t allowed_args[] = { |
|
201 | 201 | self, |
202 | 202 | (uint8_t)args[ARG_cmd_bits].u_int, |
203 | 203 | (uint8_t)args[ARG_param_bits].u_int |
204 | | - ) |
| 204 | + ); |
205 | 205 | return mp_const_none; |
206 | 206 | } |
207 | 207 |
|
208 | | - static MP_DEFINE_CONST_FUN_OBJ_KW(lcd_spi_3wire_init_obj, 3, lcd_spi_3wire_init); |
| 208 | + static MP_DEFINE_CONST_FUN_OBJ_KW(spi_3wire_init_obj, 3, spi_3wire_init); |
209 | 209 |
|
210 | 210 |
|
211 | 211 | void mp_spi_3wire_tx_param(mp_spi_3wire_obj_t *self, int lcd_cmd, const void *param, size_t param_size) |
|
287 | 287 | static esp_err_t spi_3wire_write_byte(mp_spi_3wire_obj_t *self, int dc_bit, uint8_t data) |
288 | 288 | { |
289 | 289 | uint16_t data_temp = data; |
290 | | - uint8_t data_bits = (dc_bit != DATA_NO_DC_BIT) ? 9 : 8; |
| 290 | + uint8_t data_bits = (dc_bit != SPI_3WIRE_DATA_NO_DC_BIT) ? 9 : 8; |
291 | 291 | uint16_t write_order_mask = self->write_order_mask; |
292 | 292 | uint32_t scl_active_before_level = self->scl_active_rising_edge ? 0 : 1; |
293 | 293 | uint32_t scl_active_after_level = !scl_active_before_level; |
|
301 | 301 | // SDA set to data bit |
302 | 302 | gpio_set_level(self->sda, data_temp & write_order_mask); |
303 | 303 | // Get next bit |
304 | | - data_temp = (write_order_mask == WRITE_ORDER_LSB_MASK) ? data_temp >> 1 : data_temp << 1; |
| 304 | + data_temp = (write_order_mask == SPI_3WIRE_WRITE_ORDER_LSB_MASK) ? data_temp >> 1 : data_temp << 1; |
305 | 305 | } |
306 | 306 | // Generate SCL active edge |
307 | 307 | gpio_set_level(self->scl, scl_active_before_level); |
|
337 | 337 | if (i == 0) { |
338 | 338 | spi_3wire_write_byte(self, data_dc_bit, swap_data & 0xff); |
339 | 339 | } else { |
340 | | - spi_3wire_write_byte(self, DATA_NO_DC_BIT, swap_data & 0xff); |
| 340 | + spi_3wire_write_byte(self, SPI_3WIRE_DATA_NO_DC_BIT, swap_data & 0xff); |
341 | 341 | } |
342 | 342 | swap_data >>= 8; |
343 | 343 | } |
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