diff --git a/software/fpga/ov3/Makefile b/software/fpga/ov3/Makefile
index 7282ab1..f2a56f1 100644
--- a/software/fpga/ov3/Makefile
+++ b/software/fpga/ov3/Makefile
@@ -15,7 +15,7 @@ $(FWPKG): $(BITFILE)
 	$(PYTHON) -m zipfile -c $@ $< $(BUILD)/map.txt
 
 $(BITFILE): $(PY_FILES)
-	$(PYTHON) build.py build_dir $(BUILD) build_name ov3
+	$(PYTHON) build.py $(BUILD) ov3
 
 clean:
 	rm -rf $(BUILD)/*
diff --git a/software/fpga/ov3/build.py b/software/fpga/ov3/build.py
index 9b62665..9e7e9c6 100644
--- a/software/fpga/ov3/build.py
+++ b/software/fpga/ov3/build.py
@@ -21,11 +21,13 @@ def gen_mapfile(ov3_mod):
     return r
 
 if __name__ == "__main__":
+    import sys
+
     plat = Platform()
     top = OV3(plat)
 
-    # Build the register map
-    # FIXME: build dir should come from command line arg
-    open("build/map.txt", "w").write(gen_mapfile(top))
+    _, build_dir, build_name = sys.argv
+
+    open("{}/map.txt".format(build_dir), "w").write(gen_mapfile(top))
 
-    plat.build(top)
+    plat.build(top, build_dir=build_dir, build_name=build_name)