From a4985de024db32d070ce957d4a3b28d3a51b3e5b Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Mon, 7 Jul 2025 13:51:20 +0200 Subject: [PATCH 01/17] Annoyingly simple fix for PC_IM unclocking (with the perspective of how long it took to find) --- mips-lib/src/gui_egui/components/mips_im.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/mips-lib/src/gui_egui/components/mips_im.rs b/mips-lib/src/gui_egui/components/mips_im.rs index adaca143..fafd9030 100644 --- a/mips-lib/src/gui_egui/components/mips_im.rs +++ b/mips-lib/src/gui_egui/components/mips_im.rs @@ -26,6 +26,12 @@ impl InstrMem { .borrow_mut() .set_reg_values(*reg.registers.borrow()); } + fn update_mem_view_dynamic_symbols(&self, sim: &Simulator) { + self.mem_view.borrow_mut().set_dynamic_symbol( + "PC_IM", + std::convert::TryInto::::try_into((sim).get_input_value(&self.pc)).unwrap(), + ); + } } #[typetag::serde] @@ -76,8 +82,9 @@ impl EguiComponent for InstrMem { }); // handle mem_window and load of new file - if let Some(sim) = &simulator { + if let Some(ref sim) = simulator { self.update_mem_view_register_values(sim); + self.update_mem_view_dynamic_symbols(sim); #[allow(clippy::expect_fun_call)] let phys_mem: &PhysicalMem = find_component_with_type(sim, &self.phys_mem_id).expect( &format!("can't find {} with type PhysicalMem", self.regfile_id), From 604505586cae4f62bc8cce37908eb8a2cadb92bf Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Wed, 9 Jul 2025 00:08:56 +0200 Subject: [PATCH 02/17] divided into 4 pipeline stages. But there are issues when taking multiple steps at a time (PC_DE, PC_EX and PC_DM are not updated correctly, nor does their unclock work as intended) --- mips-lib/mips_pipe.json | 5 ++- mips-lib/src/components/mips_im.rs | 36 ++++++++++++++++++--- mips-lib/src/gui_egui/components/mips_im.rs | 22 ++++++++++--- 3 files changed, 54 insertions(+), 9 deletions(-) diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index 75ea5154..14e8dc59 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -422,7 +422,10 @@ 0, 0, 0, 0, 0, 0, 2147483648, 0, 0 ], "dynamic_symbols": { - "PC_IM": [0, true] + "PC_IM": [0, true], + "PC_DE": [0, false], + "PC_EX": [0, false], + "PC_DM": [0, false] }, "break_points": [] } diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 3c484d98..f6c27701 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -26,6 +26,9 @@ pub struct InstrMem { pub regfile_id: String, #[cfg(feature = "gui-egui")] pub mem_view: RefCell, + + #[serde(skip)] + pub pc_history: RefCell>, } impl InstrMem { @@ -44,9 +47,10 @@ impl InstrMem { pos, pc: pc_input, phys_mem_id, + regfile_id, #[cfg(feature = "gui-egui")] mem_view: RefCell::new(mem_view), - regfile_id, + pc_history: RefCell::new(vec![]), } } pub fn rc_new( @@ -77,9 +81,10 @@ impl Component for InstrMem { pos, pc: dummy_input, phys_mem_id: "dummy".into(), + regfile_id: "dummy".into(), #[cfg(feature = "gui-egui")] mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), - regfile_id: "dummy".into(), + pc_history: RefCell::new(vec![]), })) } @@ -127,9 +132,14 @@ impl Component for InstrMem { .get(pc, MemOpSize::Word, false, true) }; - // update dynamic symbol PC_IM #[cfg(feature = "gui-egui")] - self.mem_view.borrow_mut().set_dynamic_symbol("PC_IM", pc); + self.pc_history + .borrow_mut() + .push(self.mem_view.borrow().get_dynamic_symbol("PC_IM").unwrap()); + + // update dynamic symbol PC_IM + //#[cfg(feature = "gui-egui")] + //self.mem_view.borrow_mut().set_dynamic_symbol("PC_IM", pc); // Get a word at PC with the size of 32bits, read as big endian, // sign extend doesn't mater since we have 32 bits so extending to 32bits does nothing @@ -148,4 +158,22 @@ impl Component for InstrMem { Err(_) => Err(Condition::Error(format!("Unaligned Read, PC = {:#0x}", pc))), } } + fn un_clock(&self) { + let mut pc_history = self.pc_history.borrow_mut(); + #[cfg(feature = "gui-egui")] + let mut mem_view = self.mem_view.borrow_mut(); + #[cfg(feature = "gui-egui")] + if (pc_history.len() >= 1) && (mem_view.get_dynamic_symbol("PC_IM") != None) { + mem_view.set_dynamic_symbol("PC_IM", pc_history.pop().unwrap()); + if (pc_history.len() >= 1) && (mem_view.get_dynamic_symbol("PC_DE") != None) { + mem_view.set_dynamic_symbol("PC_DE", pc_history[pc_history.len() - 1]); + if (pc_history.len() >= 2) && (mem_view.get_dynamic_symbol("PC_EX") != None) { + mem_view.set_dynamic_symbol("PC_EX", pc_history[pc_history.len() - 2]); + if (pc_history.len() >= 3) && (mem_view.get_dynamic_symbol("PC_DM") != None) { + mem_view.set_dynamic_symbol("PC_DM", pc_history[pc_history.len() - 3]); + } + } + } + } + } } diff --git a/mips-lib/src/gui_egui/components/mips_im.rs b/mips-lib/src/gui_egui/components/mips_im.rs index fafd9030..e22100ef 100644 --- a/mips-lib/src/gui_egui/components/mips_im.rs +++ b/mips-lib/src/gui_egui/components/mips_im.rs @@ -27,10 +27,24 @@ impl InstrMem { .set_reg_values(*reg.registers.borrow()); } fn update_mem_view_dynamic_symbols(&self, sim: &Simulator) { - self.mem_view.borrow_mut().set_dynamic_symbol( - "PC_IM", - std::convert::TryInto::::try_into((sim).get_input_value(&self.pc)).unwrap(), - ); + let mut mem_view = self.mem_view.borrow_mut(); + let pc_history = self.pc_history.borrow(); + if mem_view.get_dynamic_symbol("PC_IM") != None { + mem_view.set_dynamic_symbol( + "PC_IM", + std::convert::TryInto::::try_into((sim).get_input_value(&self.pc)).unwrap(), + ); + } + + if (pc_history.len() >= 2) && (mem_view.get_dynamic_symbol("PC_DE") != None) { + mem_view.set_dynamic_symbol("PC_DE", pc_history[pc_history.len() - 1]); + if (pc_history.len() >= 3) && (mem_view.get_dynamic_symbol("PC_EX") != None) { + mem_view.set_dynamic_symbol("PC_EX", pc_history[pc_history.len() - 2]); + if (pc_history.len() >= 4) && (mem_view.get_dynamic_symbol("PC_DM") != None) { + mem_view.set_dynamic_symbol("PC_DM", pc_history[pc_history.len() - 3]); + } + } + } } } From 9de5c05f5034dcf6a13787aed68c984dff5ff314 Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Thu, 17 Jul 2025 05:42:51 +0200 Subject: [PATCH 03/17] It finally works as intended. Though code may need cleanup and final adjustments --- mips-lib/mips_pipe.json | 2097 +++++++++++++---- mips-lib/src/components/mips_im.rs | 94 +- mips-lib/src/gui_egui/components/mips_im.rs | 24 +- mips-lib/src/gui_egui/mips_mem_view_window.rs | 15 + 4 files changed, 1787 insertions(+), 443 deletions(-) diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index 14e8dc59..b579fd8b 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -3,7 +3,10 @@ { "type": "Register", "id": "pc+4_reg", - "pos": [240.0, 380.0], + "pos": [ + 240.0, + 380.0 + ], "r_in": { "id": "pc+4", "field": "add_out" @@ -12,7 +15,10 @@ { "type": "Register", "id": "mux_b2_reg", - "pos": [1100.0, 420.0], + "pos": [ + 1100.0, + 420.0 + ], "r_in": { "id": "pc+4_pass", "field": "pass_through_out" @@ -21,7 +27,10 @@ { "type": "Register", "id": "pc", - "pos": [0.0, 390.0], + "pos": [ + 0.0, + 390.0 + ], "r_in": { "id": "mux_jump_merge", "field": "mux_out" @@ -30,7 +39,10 @@ { "type": "Register", "id": "zero_extend_reg", - "pos": [1100.0, 110.0], + "pos": [ + 1100.0, + 110.0 + ], "r_in": { "id": "instruction_split", "field": "shamt_out" @@ -39,7 +51,10 @@ { "type": "Register", "id": "reg_addr_reg", - "pos": [1920.0, 520.0], + "pos": [ + 1920.0, + 520.0 + ], "r_in": { "id": "reg_addr_MEM_pass", "field": "pass_through_out" @@ -48,7 +63,10 @@ { "type": "Register", "id": "operand_a_reg", - "pos": [1100.0, 215.0], + "pos": [ + 1100.0, + 215.0 + ], "r_in": { "id": "alu_forward_A_mux", "field": "mux_out" @@ -57,7 +75,10 @@ { "type": "Register", "id": "control_MEM_reg", - "pos": [1470.0, -40.0], + "pos": [ + 1470.0, + -40.0 + ], "r_in": { "id": "control_EX_pass", "field": "pass_through_out" @@ -66,7 +87,10 @@ { "type": "Register", "id": "mux_b3_reg", - "pos": [1100.0, 475.0], + "pos": [ + 1100.0, + 475.0 + ], "r_in": { "id": "signzero_extend", "field": "sz_out" @@ -75,7 +99,10 @@ { "type": "Register", "id": "result_reg_EX", - "pos": [1920.0, 270.0], + "pos": [ + 1920.0, + 270.0 + ], "r_in": { "id": "write_back_mux", "field": "mux_out" @@ -84,7 +111,10 @@ { "type": "Register", "id": "reg_addr_EX_reg", - "pos": [1100.0, 520.0], + "pos": [ + 1100.0, + 520.0 + ], "r_in": { "id": "mux_write_addr", "field": "mux_out" @@ -93,7 +123,10 @@ { "type": "Register", "id": "operand_b_reg", - "pos": [1100.0, 325.0], + "pos": [ + 1100.0, + 325.0 + ], "r_in": { "id": "alu_forward_B_mux", "field": "mux_out" @@ -102,7 +135,10 @@ { "type": "Register", "id": "control_EX_reg", - "pos": [1100.0, -40.0], + "pos": [ + 1100.0, + -40.0 + ], "r_in": { "id": "InMem_pass", "field": "pass_through_out" @@ -111,7 +147,10 @@ { "type": "Register", "id": "reg_addr_MEM_reg", - "pos": [1470.0, 520.0], + "pos": [ + 1470.0, + 520.0 + ], "r_in": { "id": "reg_addr_EX_pass", "field": "pass_through_out" @@ -120,7 +159,10 @@ { "type": "Register", "id": "InMem_reg", - "pos": [240.0, 475.0], + "pos": [ + 240.0, + 475.0 + ], "r_in": { "id": "instr_mem", "field": "instruction" @@ -129,7 +171,10 @@ { "type": "Register", "id": "alu_reg", - "pos": [1470.0, 250.0], + "pos": [ + 1470.0, + 250.0 + ], "r_in": { "id": "alu", "field": "alu_out" @@ -138,7 +183,10 @@ { "type": "Register", "id": "merge_reg", - "pos": [240.0, 580.0], + "pos": [ + 240.0, + 580.0 + ], "r_in": { "id": "jump_merge", "field": "merge_out" @@ -147,7 +195,10 @@ { "type": "Register", "id": "data_MEM_reg", - "pos": [1470.0, 585.0], + "pos": [ + 1470.0, + 585.0 + ], "r_in": { "id": "operand_b_pass", "field": "pass_through_out" @@ -156,7 +207,10 @@ { "type": "Register", "id": "control_WB_reg", - "pos": [1920.0, -40.0], + "pos": [ + 1920.0, + -40.0 + ], "r_in": { "id": "control_MEM_pass", "field": "pass_through_out" @@ -165,13 +219,19 @@ { "type": "Constant", "id": "+4", - "pos": [80.0, 400.0], + "pos": [ + 80.0, + 400.0 + ], "value": { "data": { "Data": 4 }, "fmt": { - "Hex": ["_32", false] + "Hex": [ + "_32", + false + ] } } }, @@ -179,9 +239,18 @@ "type": "Wire", "id": "from pc:register_out to instr_mem:pc", "pos": [ - [10.0, 390.0], - [30.0, 390.0], - [31.0, 551.5] + [ + 10.0, + 390.0 + ], + [ + 30.0, + 390.0 + ], + [ + 31.0, + 551.5 + ] ], "input": { "id": "pc", @@ -192,8 +261,14 @@ "type": "Wire", "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", "pos": [ - [1110.0, 110.0], - [1124.0, 110.0] + [ + 1110.0, + 110.0 + ], + [ + 1124.0, + 110.0 + ] ], "input": { "id": "zero_extend_reg", @@ -204,10 +279,22 @@ "type": "Wire", "id": "from mux_b2_reg:register_out to mux_source_b:in1", "pos": [ - [1110.0, 420.0], - [1160.0, 420.0], - [1160.0, 325.0], - [1230.0, 325.0] + [ + 1110.0, + 420.0 + ], + [ + 1160.0, + 420.0 + ], + [ + 1160.0, + 325.0 + ], + [ + 1230.0, + 325.0 + ] ], "input": { "id": "mux_b2_reg", @@ -218,11 +305,26 @@ "type": "Wire", "id": "from reg_addr_reg:register_out to reg_file:write_address_in", "pos": [ - [1930.0, 520.0], - [1950.0, 520.0], - [1951.6001, 642.0], - [641.60004, 642.0], - [640.0, 406.0] + [ + 1930.0, + 520.0 + ], + [ + 1950.0, + 520.0 + ], + [ + 1951.6001, + 642.0 + ], + [ + 641.60004, + 642.0 + ], + [ + 640.0, + 406.0 + ] ], "input": { "id": "reg_addr_reg", @@ -232,7 +334,10 @@ { "type": "ZeroExtend", "id": "zero_extend_for_shamt", - "pos": [1165.0, 110.0], + "pos": [ + 1165.0, + 110.0 + ], "signal_in": { "id": "zero_extend_reg", "field": "register_out" @@ -242,10 +347,22 @@ "type": "Wire", "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", "pos": [ - [1206.0, 110.0], - [1220.0, 110.0], - [1220.0, 190.0], - [1230.0, 190.0] + [ + 1206.0, + 110.0 + ], + [ + 1220.0, + 110.0 + ], + [ + 1220.0, + 190.0 + ], + [ + 1230.0, + 190.0 + ] ], "input": { "id": "zero_extend_for_shamt", @@ -255,7 +372,10 @@ { "type": "ControlUnit", "id": "control_unit_3", - "pos": [1695.0, 0.0], + "pos": [ + 1695.0, + 0.0 + ], "a_in": { "id": "control_MEM_reg", "field": "register_out" @@ -265,32 +385,57 @@ "type": "Wire", "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", "pos": [ - [1690.0, 13.5], - [1690.0, 551.5] + [ + 1690.0, + 13.5 + ], + [ + 1690.0, + 551.5 + ] ], "input": { "id": "control_unit_3", "field": "mem_mode" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_3:reg_write_src to write_back_mux:select", "pos": [ - [1790.0, 13.5], - [1790.0, 240.0] + [ + 1790.0, + 13.5 + ], + [ + 1790.0, + 240.0 + ] ], "input": { "id": "control_unit_3", "field": "reg_write_src" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "PassThrough", "id": "control_MEM_pass", - "pos": [1510.0, -40.0], + "pos": [ + 1510.0, + -40.0 + ], "input": { "id": "control_MEM_reg", "field": "register_out" @@ -300,10 +445,22 @@ "type": "Wire", "id": "from operand_a_reg:register_out to mux_source_a:in1", "pos": [ - [1110.0, 215.0], - [1140.0, 215.0], - [1140.0, 210.0], - [1230.0, 210.0] + [ + 1110.0, + 215.0 + ], + [ + 1140.0, + 215.0 + ], + [ + 1140.0, + 210.0 + ], + [ + 1230.0, + 210.0 + ] ], "input": { "id": "operand_a_reg", @@ -314,11 +471,26 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to alu_forward_B:a_in", "pos": [ - [1130.0, 520.0], - [1130.0, 497.0], - [930.0, 497.0], - [930.0, 395.0], - [960.0, 395.0] + [ + 1130.0, + 520.0 + ], + [ + 1130.0, + 497.0 + ], + [ + 930.0, + 497.0 + ], + [ + 930.0, + 395.0 + ], + [ + 960.0, + 395.0 + ] ], "input": { "id": "reg_addr_EX_reg", @@ -328,7 +500,10 @@ { "type": "PassThrough", "id": "reg_addr_EX_pass", - "pos": [1165.0, 520.0], + "pos": [ + 1165.0, + 520.0 + ], "input": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -338,8 +513,14 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", "pos": [ - [1110.0, 520.0], - [1165.0, 520.0] + [ + 1110.0, + 520.0 + ], + [ + 1165.0, + 520.0 + ] ], "input": { "id": "reg_addr_EX_reg", @@ -350,26 +531,61 @@ "type": "Wire", "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", "pos": [ - [820.0, 155.0], - [820.0, 395.0], - [808.5, 395.0] + [ + 820.0, + 155.0 + ], + [ + 820.0, + 395.0 + ], + [ + 808.5, + 395.0 + ] ], "input": { "id": "control_unit_3", "field": "reg_write_enable" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "InstrMem", "id": "instr_mem", - "pos": [45.0, 585.0], + "pos": [ + 45.0, + 585.0 + ], "pc": { "id": "pc", "field": "register_out" }, "phys_mem_id": "phys_mem", "regfile_id": "reg_file", + "dynamic_symbols": { + "PC_IM": [ + 0, + true + ], + "PC_DE": [ + 0, + false + ], + "PC_EX": [ + 0, + false + ], + "PC_DM": [ + 0, + false + ] + }, "mem_view": { "visible": false, "title": "instruction memory view", @@ -418,22 +634,67 @@ ] }, "register_values": [ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 2147483648, 0, 0 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 ], + "break_points": [], "dynamic_symbols": { - "PC_IM": [0, true], - "PC_DE": [0, false], - "PC_EX": [0, false], - "PC_DM": [0, false] - }, - "break_points": [] + "PC_IM": [ + 0, + true + ], + "PC_DE": [ + 0, + false + ], + "PC_EX": [ + 0, + false + ], + "PC_DM": [ + 0, + false + ] + } } }, { "type": "JumpMerge", "id": "jump_merge", - "pos": [180.0, 530.0], + "pos": [ + 180.0, + 530.0 + ], "instr_addr_in": { "id": "pc", "field": "register_out" @@ -447,9 +708,18 @@ "type": "Wire", "id": "from jump_merge:merge_out to merge_reg:r_in", "pos": [ - [180.0, 544.0], - [180.0, 580.0], - [230.0, 580.0] + [ + 180.0, + 544.0 + ], + [ + 180.0, + 580.0 + ], + [ + 230.0, + 580.0 + ] ], "input": { "id": "jump_merge", @@ -460,8 +730,14 @@ "type": "Wire", "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", "pos": [ - [85.0, 530.0], - [140.0, 530.0] + [ + 85.0, + 530.0 + ], + [ + 140.0, + 530.0 + ] ], "input": { "id": "instr_mem", @@ -472,8 +748,14 @@ "type": "Wire", "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", "pos": [ - [1110.0, 325.0], - [1140.0, 325.0] + [ + 1110.0, + 325.0 + ], + [ + 1140.0, + 325.0 + ] ], "input": { "id": "operand_b_reg", @@ -484,9 +766,18 @@ "type": "Wire", "id": "from instr_mem:instruction to InMem_reg:r_in", "pos": [ - [85.0, 551.5], - [85.0, 475.0], - [230.0, 475.0] + [ + 85.0, + 551.5 + ], + [ + 85.0, + 475.0 + ], + [ + 230.0, + 475.0 + ] ], "input": { "id": "instr_mem", @@ -496,13 +787,19 @@ { "type": "Constant", "id": "0_a_inp", - "pos": [1190.0, 230.0], + "pos": [ + 1190.0, + 230.0 + ], "value": { "data": { "Data": 4 }, "fmt": { - "Hex": ["_32", false] + "Hex": [ + "_32", + false + ] } } }, @@ -510,9 +807,18 @@ "type": "Wire", "id": "from pc:register_out to jump_merge:merge_instr_addr_in", "pos": [ - [30.0, 465.0], - [180.0, 465.0], - [180.0, 517.0] + [ + 30.0, + 465.0 + ], + [ + 180.0, + 465.0 + ], + [ + 180.0, + 517.0 + ] ], "input": { "id": "pc", @@ -523,10 +829,22 @@ "type": "Wire", "id": "from mux_b3_reg:register_out to mux_source_b:in2", "pos": [ - [1110.0, 475.0], - [1180.0, 475.0], - [1180.0, 345.0], - [1230.0, 345.0] + [ + 1110.0, + 475.0 + ], + [ + 1180.0, + 475.0 + ], + [ + 1180.0, + 345.0 + ], + [ + 1230.0, + 345.0 + ] ], "input": { "id": "mux_b3_reg", @@ -537,8 +855,14 @@ "type": "Wire", "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", "pos": [ - [1110.0, -40.0], - [1140.0, -40.0] + [ + 1110.0, + -40.0 + ], + [ + 1140.0, + -40.0 + ] ], "input": { "id": "control_EX_reg", @@ -549,8 +873,14 @@ "type": "Wire", "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", "pos": [ - [1110.0, -40.0], - [1079.0, 0.0] + [ + 1110.0, + -40.0 + ], + [ + 1079.0, + 0.0 + ] ], "input": { "id": "control_EX_reg", @@ -560,7 +890,10 @@ { "type": "PassThrough", "id": "control_EX_pass", - "pos": [1140.0, -40.0], + "pos": [ + 1140.0, + -40.0 + ], "input": { "id": "control_EX_reg", "field": "register_out" @@ -570,8 +903,14 @@ "type": "Wire", "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", "pos": [ - [1140.0, -40.0], - [1460.0, -40.0] + [ + 1140.0, + -40.0 + ], + [ + 1460.0, + -40.0 + ] ], "input": { "id": "control_EX_pass", @@ -581,7 +920,10 @@ { "type": "PassThrough", "id": "pc+4_pass", - "pos": [260.0, 370.0], + "pos": [ + 260.0, + 370.0 + ], "input": { "id": "pc+4_reg", "field": "register_out" @@ -591,9 +933,18 @@ "type": "Wire", "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", "pos": [ - [260.0, 380.0], - [260.0, 420.0], - [1090.0, 420.0] + [ + 260.0, + 380.0 + ], + [ + 260.0, + 420.0 + ], + [ + 1090.0, + 420.0 + ] ], "input": { "id": "pc+4_pass", @@ -604,8 +955,14 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", "pos": [ - [1480.0, 520.0], - [1520.0, 520.0] + [ + 1480.0, + 520.0 + ], + [ + 1520.0, + 520.0 + ] ], "input": { "id": "reg_addr_MEM_reg", @@ -616,8 +973,14 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", "pos": [ - [760.0, 395.0], - [790.0, 395.0] + [ + 760.0, + 395.0 + ], + [ + 790.0, + 395.0 + ] ], "input": { "id": "reg_addr_MEM_reg", @@ -628,8 +991,14 @@ "type": "Wire", "id": "from 0_a_inp:constant_out to mux_source_a:in2", "pos": [ - [1190.0, 230.0], - [1230.0, 230.0] + [ + 1190.0, + 230.0 + ], + [ + 1230.0, + 230.0 + ] ], "input": { "id": "0_a_inp", @@ -640,24 +1009,50 @@ "type": "Wire", "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", "pos": [ - [1540.0, 13.5], - [1540.0, 80.0], - [820.0, 80.0], - [820.0, 155.0], - [809.0, 155.0] + [ + 1540.0, + 13.5 + ], + [ + 1540.0, + 80.0 + ], + [ + 820.0, + 80.0 + ], + [ + 820.0, + 155.0 + ], + [ + 809.0, + 155.0 + ] ], "input": { "id": "control_unit_3", "field": "reg_write_enable" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from +4:constant_out to pc+4:b_in", "pos": [ - [80.0, 400.0], - [110.0, 400.0] + [ + 80.0, + 400.0 + ], + [ + 110.0, + 400.0 + ] ], "input": { "id": "+4", @@ -667,7 +1062,10 @@ { "type": "ControlUnit", "id": "control_unit_2", - "pos": [1285.0, 0.0], + "pos": [ + 1285.0, + 0.0 + ], "a_in": { "id": "control_EX_reg", "field": "register_out" @@ -677,19 +1075,33 @@ "type": "Wire", "id": "from control_unit_2:alu_src_a to mux_source_a:select", "pos": [ - [1240.0, 13.5], - [1240.0, 170.0] + [ + 1240.0, + 13.5 + ], + [ + 1240.0, + 170.0 + ] ], "input": { "id": "control_unit_2", "field": "alu_src_a" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Mux", "id": "mux_source_a", - "pos": [1250.0, 210.0], + "pos": [ + 1250.0, + 210.0 + ], "select": { "id": "control_unit_2", "field": "alu_src_a" @@ -714,10 +1126,22 @@ "type": "Wire", "id": "from mux_source_a:mux_out to alu:full_add_a_in", "pos": [ - [1260.0, 210.0], - [1320.0, 210.0], - [1320.0, 220.0], - [1380.0, 220.0] + [ + 1260.0, + 210.0 + ], + [ + 1320.0, + 210.0 + ], + [ + 1320.0, + 220.0 + ], + [ + 1380.0, + 220.0 + ] ], "input": { "id": "mux_source_a", @@ -728,94 +1152,193 @@ "type": "Wire", "id": "from control_unit_2:alu_src_b to mux_source_b:select", "pos": [ - [1280.0, 13.5], - [1280.0, 270.0], - [1240.0, 270.0], - [1240.0, 285.0] + [ + 1280.0, + 13.5 + ], + [ + 1280.0, + 270.0 + ], + [ + 1240.0, + 270.0 + ], + [ + 1240.0, + 285.0 + ] ], "input": { "id": "control_unit_2", "field": "alu_src_b" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_2:alu_op to alu:full_add_op_in", "pos": [ - [1390.0, 13.5], - [1390.0, 210.0] + [ + 1390.0, + 13.5 + ], + [ + 1390.0, + 210.0 + ] ], "input": { "id": "control_unit_2", "field": "alu_op" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_2:mem_mode to alu_forward_B:load_in", "pos": [ - [1000.0, 160.0], - [1000.0, 402.5], - [980.0, 402.5] + [ + 1000.0, + 160.0 + ], + [ + 1000.0, + 402.5 + ], + [ + 980.0, + 402.5 + ] ], "input": { "id": "control_unit_2", "field": "mem_mode" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", "pos": [ - [1140.0, 13.5], - [1140.0, 70.0], - [990.0, 70.0], - [990.0, 150.0], - [980.0, 150.0] + [ + 1140.0, + 13.5 + ], + [ + 1140.0, + 70.0 + ], + [ + 990.0, + 70.0 + ], + [ + 990.0, + 150.0 + ], + [ + 980.0, + 150.0 + ] ], "input": { "id": "control_unit_2", "field": "reg_write_enable" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_2:reg_write_enable to alu_forward_B:we_in", "pos": [ - [990.0, 150.0], - [990.0, 390.0], - [980.0, 390.0] + [ + 990.0, + 150.0 + ], + [ + 990.0, + 390.0 + ], + [ + 980.0, + 390.0 + ] ], "input": { "id": "control_unit_2", "field": "reg_write_enable" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", "pos": [ - [1110.0, 13.5], - [1110.0, 50.0], - [1000.0, 50.0], - [1000.0, 160.0], - [980.0, 160.0] + [ + 1110.0, + 13.5 + ], + [ + 1110.0, + 50.0 + ], + [ + 1000.0, + 50.0 + ], + [ + 1000.0, + 160.0 + ], + [ + 980.0, + 160.0 + ] ], "input": { "id": "control_unit_2", "field": "mem_mode" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "ControlUnit", "id": "control_unit_1", - "pos": [670.0, 0.0], + "pos": [ + 670.0, + 0.0 + ], "a_in": { "id": "InMem_reg", "field": "register_out" @@ -825,22 +1348,42 @@ "type": "Wire", "id": "from control_unit_1:reg_dest to mux_write_addr:select", "pos": [ - [710.0, 14.0], - [710.0, 480.0] + [ + 710.0, + 14.0 + ], + [ + 710.0, + 480.0 + ] ], "input": { "id": "control_unit_1", "field": "reg_dest" }, - "color_rgba": [0, 0, 0, 30] + "color_rgba": [ + 0, + 0, + 0, + 30 + ] }, { "type": "Wire", "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", "pos": [ - [434.0, -40.0], - [434.0, 0.0], - [464.0, 0.0] + [ + 434.0, + -40.0 + ], + [ + 434.0, + 0.0 + ], + [ + 464.0, + 0.0 + ] ], "input": { "id": "InMem_reg", @@ -850,7 +1393,10 @@ { "type": "InstrSplit", "id": "instruction_split", - "pos": [400.0, 275.0], + "pos": [ + 400.0, + 275.0 + ], "instruction_in": { "id": "InMem_reg", "field": "register_out" @@ -859,7 +1405,10 @@ { "type": "SignZeroExtend", "id": "signzero_extend", - "pos": [400.0, 475.0], + "pos": [ + 400.0, + 475.0 + ], "signzero_signal_in": { "id": "instruction_split", "field": "immediate_out" @@ -873,12 +1422,30 @@ "type": "Wire", "id": "from signzero_extend:sz_out to branch_shift:shift_in", "pos": [ - [458.5, 475.0], - [468.5, 475.0], - [468.5, 560.0], - [356.0, 560.0], - [356.0, 585.0], - [366.5, 585.0] + [ + 458.5, + 475.0 + ], + [ + 468.5, + 475.0 + ], + [ + 468.5, + 560.0 + ], + [ + 356.0, + 560.0 + ], + [ + 356.0, + 585.0 + ], + [ + 366.5, + 585.0 + ] ], "input": { "id": "signzero_extend", @@ -889,8 +1456,14 @@ "type": "Wire", "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", "pos": [ - [469.0, 475.0], - [1090.0, 475.0] + [ + 469.0, + 475.0 + ], + [ + 1090.0, + 475.0 + ] ], "input": { "id": "signzero_extend", @@ -900,7 +1473,10 @@ { "type": "ShiftConst", "id": "branch_shift", - "pos": [400.0, 585.0], + "pos": [ + 400.0, + 585.0 + ], "signal_in": { "id": "signzero_extend", "field": "sz_out" @@ -910,7 +1486,10 @@ { "type": "Add", "id": "pc_add_branch", - "pos": [530.0, 565.0], + "pos": [ + 530.0, + 565.0 + ], "a_in": { "id": "pc+4_reg", "field": "register_out" @@ -925,12 +1504,30 @@ "type": "Wire", "id": "from pc_add_branch:add_out to mux_jump_merge:in0", "pos": [ - [550.0, 565.0], - [560.0, 565.0], - [561.0, 640.0], - [-114.0, 640.0], - [-114.0, 360.0], - [-74.0, 360.0] + [ + 550.0, + 565.0 + ], + [ + 560.0, + 565.0 + ], + [ + 561.0, + 640.0 + ], + [ + -114.0, + 640.0 + ], + [ + -114.0, + 360.0 + ], + [ + -74.0, + 360.0 + ] ], "input": { "id": "pc_add_branch", @@ -941,9 +1538,18 @@ "type": "Wire", "id": "from instruction_split:rt_out to data_forward_B:b_in", "pos": [ - [585.0, 465.0], - [800.0, 465.0], - [800.0, 408.0] + [ + 585.0, + 465.0 + ], + [ + 800.0, + 465.0 + ], + [ + 800.0, + 408.0 + ] ], "input": { "id": "instruction_split", @@ -953,7 +1559,10 @@ { "type": "AluForward", "id": "alu_forward_B", - "pos": [970.0, 395.0], + "pos": [ + 970.0, + 395.0 + ], "a_in": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -975,8 +1584,14 @@ "type": "Wire", "id": "from alu_forward_B:equals_forward_out to alu_forward_B_mux:select", "pos": [ - [970.0, 381.0], - [960.0, 355.0] + [ + 970.0, + 381.0 + ], + [ + 960.0, + 355.0 + ] ], "input": { "id": "alu_forward_B", @@ -986,7 +1601,10 @@ { "type": "AluForward", "id": "alu_forward_A", - "pos": [970.0, 155.0], + "pos": [ + 970.0, + 155.0 + ], "a_in": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -1008,8 +1626,14 @@ "type": "Wire", "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", "pos": [ - [970.0, 167.0], - [960.0, 195.0] + [ + 970.0, + 167.0 + ], + [ + 960.0, + 195.0 + ] ], "input": { "id": "alu_forward_A", @@ -1020,9 +1644,18 @@ "type": "Wire", "id": "from instruction_split:rt_out to alu_forward_B:b_in", "pos": [ - [800.0, 465.0], - [970.0, 465.0], - [970.0, 408.0] + [ + 800.0, + 465.0 + ], + [ + 970.0, + 465.0 + ], + [ + 970.0, + 408.0 + ] ], "input": { "id": "instruction_split", @@ -1033,11 +1666,26 @@ "type": "Wire", "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", "pos": [ - [400.0, 381.5], - [400.0, 391.0], - [320.0, 391.0], - [320.0, 475.5], - [341.5, 475.0] + [ + 400.0, + 381.5 + ], + [ + 400.0, + 391.0 + ], + [ + 320.0, + 391.0 + ], + [ + 320.0, + 475.5 + ], + [ + 341.5, + 475.0 + ] ], "input": { "id": "instruction_split", @@ -1048,9 +1696,18 @@ "type": "Wire", "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", "pos": [ - [395.0, 170.0], - [395.0, 100.0], - [1090.0, 100.0] + [ + 395.0, + 170.0 + ], + [ + 395.0, + 100.0 + ], + [ + 1090.0, + 100.0 + ] ], "input": { "id": "instruction_split", @@ -1061,10 +1718,22 @@ "type": "Wire", "id": "from instruction_split:rt_out to mux_write_addr:in0", "pos": [ - [430.0, 332.0], - [495.19995, 332.8], - [494.39996, 500.0], - [700.0, 500.0] + [ + 430.0, + 332.0 + ], + [ + 495.19995, + 332.8 + ], + [ + 494.39996, + 500.0 + ], + [ + 700.0, + 500.0 + ] ], "input": { "id": "instruction_split", @@ -1075,9 +1744,18 @@ "type": "Wire", "id": "from instruction_split:rs_out to data_forward_A:b_in", "pos": [ - [585.0, 120.0], - [800.0, 120.0], - [800.0, 142.0] + [ + 585.0, + 120.0 + ], + [ + 800.0, + 120.0 + ], + [ + 800.0, + 142.0 + ] ], "input": { "id": "instruction_split", @@ -1087,7 +1765,10 @@ { "type": "DataForward", "id": "data_forward_A", - "pos": [800.0, 155.0], + "pos": [ + 800.0, + 155.0 + ], "a_in": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -1105,8 +1786,14 @@ "type": "Wire", "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", "pos": [ - [800.0, 168.0], - [790.0, 195.0] + [ + 800.0, + 168.0 + ], + [ + 790.0, + 195.0 + ] ], "input": { "id": "data_forward_A", @@ -1117,9 +1804,18 @@ "type": "Wire", "id": "from instruction_split:rs_out to alu_forward_A:b_in", "pos": [ - [800.0, 120.0], - [970.0, 120.0], - [970.0, 142.0] + [ + 800.0, + 120.0 + ], + [ + 970.0, + 120.0 + ], + [ + 970.0, + 142.0 + ] ], "input": { "id": "instruction_split", @@ -1130,8 +1826,14 @@ "type": "Wire", "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", "pos": [ - [250.0, 475.0], - [250.0, 475.0] + [ + 250.0, + 475.0 + ], + [ + 250.0, + 475.0 + ] ], "input": { "id": "InMem_reg", @@ -1142,10 +1844,22 @@ "type": "Wire", "id": "from alu_reg:register_out to write_back_mux:in0", "pos": [ - [1480.0, 250.0], - [1750.0, 250.0], - [1750.0, 260.0], - [1780.0, 260.0] + [ + 1480.0, + 250.0 + ], + [ + 1750.0, + 250.0 + ], + [ + 1750.0, + 260.0 + ], + [ + 1780.0, + 260.0 + ] ], "input": { "id": "alu_reg", @@ -1155,7 +1869,10 @@ { "type": "DataForward", "id": "data_forward_B", - "pos": [800.0, 395.0], + "pos": [ + 800.0, + 395.0 + ], "a_in": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -1173,8 +1890,14 @@ "type": "Wire", "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", "pos": [ - [800.0, 382.0], - [790.0, 355.0] + [ + 800.0, + 382.0 + ], + [ + 790.0, + 355.0 + ] ], "input": { "id": "data_forward_B", @@ -1185,8 +1908,14 @@ "type": "Wire", "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", "pos": [ - [1510.0, -40.0], - [1910.0, -40.0] + [ + 1510.0, + -40.0 + ], + [ + 1910.0, + -40.0 + ] ], "input": { "id": "control_MEM_pass", @@ -1197,12 +1926,30 @@ "type": "Wire", "id": "from merge_reg:register_out to mux_jump_merge:in2", "pos": [ - [250.0, 580.0], - [260.0, 580.0], - [260.0, 630.0], - [-94.0, 630.0], - [-94.0, 400.0], - [-74.0, 400.0] + [ + 250.0, + 580.0 + ], + [ + 260.0, + 580.0 + ], + [ + 260.0, + 630.0 + ], + [ + -94.0, + 630.0 + ], + [ + -94.0, + 400.0 + ], + [ + -74.0, + 400.0 + ] ], "input": { "id": "merge_reg", @@ -1213,11 +1960,26 @@ "type": "Wire", "id": "from result_reg_EX:register_out to reg_file:write_data_in", "pos": [ - [1930.0, 270.0], - [1970.0, 270.0], - [1970.0, 655.0], - [620.0, 655.0], - [620.0, 406.0] + [ + 1930.0, + 270.0 + ], + [ + 1970.0, + 270.0 + ], + [ + 1970.0, + 655.0 + ], + [ + 620.0, + 655.0 + ], + [ + 620.0, + 406.0 + ] ], "input": { "id": "result_reg_EX", @@ -1228,9 +1990,18 @@ "type": "Wire", "id": "from pc+4_reg:register_out to pc_add_branch:a_in", "pos": [ - [305.0, 420.0], - [305.0, 545.0], - [510.0, 545.0] + [ + 305.0, + 420.0 + ], + [ + 305.0, + 545.0 + ], + [ + 510.0, + 545.0 + ] ], "input": { "id": "pc+4_reg", @@ -1241,8 +2012,14 @@ "type": "Wire", "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", "pos": [ - [1480.0, 585.0], - [1594.0, 585.0] + [ + 1480.0, + 585.0 + ], + [ + 1594.0, + 585.0 + ] ], "input": { "id": "data_MEM_reg", @@ -1252,7 +2029,10 @@ { "type": "DataMem", "id": "data_mem", - "pos": [1660.0, 585.0], + "pos": [ + 1660.0, + 585.0 + ], "address_input": { "id": "alu_reg", "field": "register_out" @@ -1319,11 +2099,44 @@ ] }, "register_values": [ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 2147483648, 0, 0 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 ], "dynamic_symbols": { - "DM_ADRS": [0, false] + "DM_ADRS": [ + 0, + false + ] }, "break_points": [] } @@ -1331,7 +2144,10 @@ { "type": "Mux", "id": "write_back_mux", - "pos": [1800.0, 270.0], + "pos": [ + 1800.0, + 270.0 + ], "select": { "id": "control_unit_3", "field": "reg_write_src" @@ -1352,8 +2168,14 @@ "type": "Wire", "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", "pos": [ - [740.0, 335.0], - [780.0, 335.0] + [ + 740.0, + 335.0 + ], + [ + 780.0, + 335.0 + ] ], "input": { "id": "write_back_mux", @@ -1364,11 +2186,26 @@ "type": "Wire", "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", "pos": [ - [1830.0, 270.0], - [1830.0, 440.0], - [740.0, 440.0], - [740.0, 235.0], - [780.0, 235.0] + [ + 1830.0, + 270.0 + ], + [ + 1830.0, + 440.0 + ], + [ + 740.0, + 440.0 + ], + [ + 740.0, + 235.0 + ], + [ + 780.0, + 235.0 + ] ], "input": { "id": "write_back_mux", @@ -1379,8 +2216,14 @@ "type": "Wire", "id": "from write_back_mux:mux_out to result_reg_EX:r_in", "pos": [ - [1810.0, 270.0], - [1910.0, 270.0] + [ + 1810.0, + 270.0 + ], + [ + 1910.0, + 270.0 + ] ], "input": { "id": "write_back_mux", @@ -1391,10 +2234,22 @@ "type": "Wire", "id": "from data_mem:data_out to write_back_mux:in1", "pos": [ - [1726.0, 585.0], - [1750.0, 585.0], - [1750.0, 280.0], - [1780.0, 280.0] + [ + 1726.0, + 585.0 + ], + [ + 1750.0, + 585.0 + ], + [ + 1750.0, + 280.0 + ], + [ + 1780.0, + 280.0 + ] ], "input": { "id": "data_mem", @@ -1404,7 +2259,10 @@ { "type": "Mux", "id": "mux_source_b", - "pos": [1250.0, 325.0], + "pos": [ + 1250.0, + 325.0 + ], "select": { "id": "control_unit_2", "field": "alu_src_b" @@ -1429,10 +2287,22 @@ "type": "Wire", "id": "from mux_source_b:mux_out to alu:full_add_b_in", "pos": [ - [1260.0, 325.0], - [1320.0, 325.0], - [1320.0, 280.0], - [1380.0, 280.0] + [ + 1260.0, + 325.0 + ], + [ + 1320.0, + 325.0 + ], + [ + 1320.0, + 280.0 + ], + [ + 1380.0, + 280.0 + ] ], "input": { "id": "mux_source_b", @@ -1442,7 +2312,10 @@ { "type": "ALU", "id": "alu", - "pos": [1400.0, 250.0], + "pos": [ + 1400.0, + 250.0 + ], "a_in": { "id": "mux_source_a", "field": "mux_out" @@ -1460,8 +2333,14 @@ "type": "Wire", "id": "from alu:alu_out to alu_reg:r_in", "pos": [ - [1420.0, 250.0], - [1460.0, 250.0] + [ + 1420.0, + 250.0 + ], + [ + 1460.0, + 250.0 + ] ], "input": { "id": "alu", @@ -1472,9 +2351,18 @@ "type": "Wire", "id": "from alu:alu_out to alu_forward_A_mux:in1", "pos": [ - [910.0, 335.0], - [910.0, 235.0], - [950.0, 235.0] + [ + 910.0, + 335.0 + ], + [ + 910.0, + 235.0 + ], + [ + 950.0, + 235.0 + ] ], "input": { "id": "alu", @@ -1485,11 +2373,26 @@ "type": "Wire", "id": "from alu:alu_out to alu_forward_B_mux:in1", "pos": [ - [1440.0, 250.0], - [1440.0, 570.0], - [910.0, 570.0], - [910.0, 335.0], - [950.0, 335.0] + [ + 1440.0, + 250.0 + ], + [ + 1440.0, + 570.0 + ], + [ + 910.0, + 570.0 + ], + [ + 910.0, + 335.0 + ], + [ + 950.0, + 335.0 + ] ], "input": { "id": "alu", @@ -1500,8 +2403,14 @@ "type": "Wire", "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", "pos": [ - [250.0, 380.0], - [260.0, 380.0] + [ + 250.0, + 380.0 + ], + [ + 260.0, + 380.0 + ] ], "input": { "id": "pc+4_reg", @@ -1512,9 +2421,18 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", "pos": [ - [930.0, 395.0], - [930.0, 155.0], - [960.0, 155.0] + [ + 930.0, + 395.0 + ], + [ + 930.0, + 155.0 + ], + [ + 960.0, + 155.0 + ] ], "input": { "id": "reg_addr_EX_reg", @@ -1525,8 +2443,14 @@ "type": "Wire", "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", "pos": [ - [1930.0, -40.0], - [2014.0, 0.0] + [ + 1930.0, + -40.0 + ], + [ + 2014.0, + 0.0 + ] ], "input": { "id": "control_WB_reg", @@ -1536,7 +2460,10 @@ { "type": "ControlUnit", "id": "control_unit_4", - "pos": [2220.0, 0.0], + "pos": [ + 2220.0, + 0.0 + ], "a_in": { "id": "control_WB_reg", "field": "register_out" @@ -1545,7 +2472,10 @@ { "type": "RegFile", "id": "reg_file", - "pos": [585.0, 275.0], + "pos": [ + 585.0, + 275.0 + ], "rs_address_in": { "id": "instruction_split", "field": "rs_out" @@ -1570,7 +2500,10 @@ { "type": "Mux", "id": "data_forward_A_mux", - "pos": [800.0, 225.0], + "pos": [ + 800.0, + 225.0 + ], "select": { "id": "data_forward_A", "field": "data_forward_out" @@ -1590,7 +2523,10 @@ { "type": "Mux", "id": "alu_forward_A_mux", - "pos": [970.0, 225.0], + "pos": [ + 970.0, + 225.0 + ], "select": { "id": "alu_forward_A", "field": "equals_forward_out" @@ -1611,8 +2547,14 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", "pos": [ - [1010.0, 225.0], - [1010.0, 262.0] + [ + 1010.0, + 225.0 + ], + [ + 1010.0, + 262.0 + ] ], "input": { "id": "alu_forward_A_mux", @@ -1623,8 +2565,14 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", "pos": [ - [1020.0, 215.5], - [1090.0, 215.0] + [ + 1020.0, + 215.5 + ], + [ + 1090.0, + 215.0 + ] ], "input": { "id": "alu_forward_A_mux", @@ -1635,12 +2583,30 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", "pos": [ - [980.0, 225.0], - [1020.0, 225.0], - [1020.0, 40.0], - [-94.0, 40.0], - [-94.0, 380.0], - [-74.0, 380.0] + [ + 980.0, + 225.0 + ], + [ + 1020.0, + 225.0 + ], + [ + 1020.0, + 40.0 + ], + [ + -94.0, + 40.0 + ], + [ + -94.0, + 380.0 + ], + [ + -74.0, + 380.0 + ] ], "input": { "id": "alu_forward_A_mux", @@ -1651,8 +2617,14 @@ "type": "Wire", "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", "pos": [ - [651.0, 315.0], - [780.0, 315.0] + [ + 651.0, + 315.0 + ], + [ + 780.0, + 315.0 + ] ], "input": { "id": "reg_file", @@ -1662,7 +2634,10 @@ { "type": "Mux", "id": "data_forward_B_mux", - "pos": [800.0, 325.0], + "pos": [ + 800.0, + 325.0 + ], "select": { "id": "data_forward_B", "field": "data_forward_out" @@ -1682,7 +2657,10 @@ { "type": "Mux", "id": "alu_forward_B_mux", - "pos": [970.0, 325.0], + "pos": [ + 970.0, + 325.0 + ], "select": { "id": "alu_forward_B", "field": "equals_forward_out" @@ -1703,8 +2681,14 @@ "type": "Wire", "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", "pos": [ - [980.0, 325.0], - [1090.0, 325.0] + [ + 980.0, + 325.0 + ], + [ + 1090.0, + 325.0 + ] ], "input": { "id": "alu_forward_B_mux", @@ -1714,7 +2698,10 @@ { "type": "BranchLogic", "id": "branch", - "pos": [1040.0, 275.0], + "pos": [ + 1040.0, + 275.0 + ], "op_in": { "id": "instruction_split", "field": "op_out" @@ -1740,23 +2727,46 @@ "type": "Wire", "id": "from branch:branch_out to mux_jump_merge:select", "pos": [ - [1040.0, 262.0], - [1040.0, 60.0], - [-64.0, 60.0], - [-64.0, 340.0] + [ + 1040.0, + 262.0 + ], + [ + 1040.0, + 60.0 + ], + [ + -64.0, + 60.0 + ], + [ + -64.0, + 340.0 + ] ], "input": { "id": "branch", "field": "branch_out" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", "pos": [ - [1010.0, 325.0], - [1010.0, 288.0] + [ + 1010.0, + 325.0 + ], + [ + 1010.0, + 288.0 + ] ], "input": { "id": "alu_forward_B_mux", @@ -1767,10 +2777,22 @@ "type": "Wire", "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", "pos": [ - [2030.0, 13.0], - [2030.0, 670.0], - [600.0, 670.0], - [600.0, 406.0] + [ + 2030.0, + 13.0 + ], + [ + 2030.0, + 670.0 + ], + [ + 600.0, + 670.0 + ], + [ + 600.0, + 406.0 + ] ], "input": { "id": "control_unit_4", @@ -1781,8 +2803,14 @@ "type": "Wire", "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", "pos": [ - [433.5, 585.0], - [510.0, 585.0] + [ + 433.5, + 585.0 + ], + [ + 510.0, + 585.0 + ] ], "input": { "id": "branch_shift", @@ -1793,27 +2821,62 @@ "type": "Wire", "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", "pos": [ - [480.0, 13.5], - [480.0, 80.0], - [340.0, 80.0], - [340.0, 440.0], - [400.0, 440.0], - [400.0, 454.0] + [ + 480.0, + 13.5 + ], + [ + 480.0, + 80.0 + ], + [ + 340.0, + 80.0 + ], + [ + 340.0, + 440.0 + ], + [ + 400.0, + 440.0 + ], + [ + 400.0, + 454.0 + ] ], "input": { "id": "control_unit_1", "field": "extend_select" }, - "color_rgba": [0, 0, 0, 30] + "color_rgba": [ + 0, + 0, + 0, + 30 + ] }, { "type": "Wire", "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", "pos": [ - [810.0, 225.0], - [860.0, 225.0], - [860.0, 215.0], - [950.0, 215.0] + [ + 810.0, + 225.0 + ], + [ + 860.0, + 225.0 + ], + [ + 860.0, + 215.0 + ], + [ + 950.0, + 215.0 + ] ], "input": { "id": "data_forward_A_mux", @@ -1824,10 +2887,22 @@ "type": "Wire", "id": "from instruction_split:rd_out to mux_write_addr:in1", "pos": [ - [431.0, 350.0], - [480.0, 350.0], - [480.0, 519.2], - [700.0, 520.0] + [ + 431.0, + 350.0 + ], + [ + 480.0, + 350.0 + ], + [ + 480.0, + 519.2 + ], + [ + 700.0, + 520.0 + ] ], "input": { "id": "instruction_split", @@ -1837,20 +2912,29 @@ { "type": "Constant", "id": "0x_1F", - "pos": [670.0, 540.0], + "pos": [ + 670.0, + 540.0 + ], "value": { "data": { "Data": 31 }, "fmt": { - "Hex": ["_32", false] + "Hex": [ + "_32", + false + ] } } }, { "type": "Mux", "id": "mux_write_addr", - "pos": [720.0, 520.0], + "pos": [ + 720.0, + 520.0 + ], "select": { "id": "control_unit_1", "field": "reg_dest" @@ -1875,8 +2959,14 @@ "type": "Wire", "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", "pos": [ - [730.0, 520.0], - [1090.0, 520.0] + [ + 730.0, + 520.0 + ], + [ + 1090.0, + 520.0 + ] ], "input": { "id": "mux_write_addr", @@ -1887,8 +2977,14 @@ "type": "Wire", "id": "from 0x_1F:constant_out to mux_write_addr:in2", "pos": [ - [670.0, 540.0], - [700.0, 540.0] + [ + 670.0, + 540.0 + ], + [ + 700.0, + 540.0 + ] ], "input": { "id": "0x_1F", @@ -1899,10 +2995,22 @@ "type": "Wire", "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", "pos": [ - [810.0, 325.0], - [860.0, 325.0], - [860.0, 315.0], - [950.0, 315.0] + [ + 810.0, + 325.0 + ], + [ + 860.0, + 325.0 + ], + [ + 860.0, + 315.0 + ], + [ + 950.0, + 315.0 + ] ], "input": { "id": "data_forward_B_mux", @@ -1913,11 +3021,26 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", "pos": [ - [1500.0, 520.0], - [1500.0, 450.0], - [760.0, 450.0], - [760.0, 155.0], - [790.0, 155.0] + [ + 1500.0, + 520.0 + ], + [ + 1500.0, + 450.0 + ], + [ + 760.0, + 450.0 + ], + [ + 760.0, + 155.0 + ], + [ + 790.0, + 155.0 + ] ], "input": { "id": "reg_addr_MEM_reg", @@ -1927,7 +3050,10 @@ { "type": "PassThrough", "id": "InMem_pass", - "pos": [250.0, 475.0], + "pos": [ + 250.0, + 475.0 + ], "input": { "id": "InMem_reg", "field": "register_out" @@ -1937,10 +3063,22 @@ "type": "Wire", "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", "pos": [ - [250.0, 475.0], - [280.0, 475.0], - [280.0, -40.0], - [1090.0, -40.0] + [ + 250.0, + 475.0 + ], + [ + 280.0, + 475.0 + ], + [ + 280.0, + -40.0 + ], + [ + 1090.0, + -40.0 + ] ], "input": { "id": "InMem_pass", @@ -1951,8 +3089,14 @@ "type": "Wire", "id": "from InMem_reg:register_out to instruction_split:instruction_in", "pos": [ - [279.0, 275.0], - [359.0, 275.0] + [ + 279.0, + 275.0 + ], + [ + 359.0, + 275.0 + ] ], "input": { "id": "InMem_reg", @@ -1962,12 +3106,18 @@ { "type": "PhysicalMem", "id": "phys_mem", - "pos": [800.0, 600.0] + "pos": [ + 800.0, + 600.0 + ] }, { "type": "Add", "id": "pc+4", - "pos": [130.0, 380.0], + "pos": [ + 130.0, + 380.0 + ], "a_in": { "id": "pc", "field": "register_out" @@ -1981,7 +3131,10 @@ { "type": "Mux", "id": "mux_jump_merge", - "pos": [-54.0, 390.0], + "pos": [ + -54.0, + 390.0 + ], "select": { "id": "branch", "field": "branch_out" @@ -2010,8 +3163,14 @@ "type": "Wire", "id": "from mux_jump_merge:mux_out to pc:r_in", "pos": [ - [-44.0, 390.0], - [-10.0, 390.0] + [ + -44.0, + 390.0 + ], + [ + -10.0, + 390.0 + ] ], "input": { "id": "mux_jump_merge", @@ -2022,12 +3181,30 @@ "type": "Wire", "id": "from pc+4:add_out to mux_jump_merge:in3", "pos": [ - [150.0, 380.0], - [170.0, 380.0], - [170.0, 455.0], - [-80.0, 455.0], - [-80.0, 420.0], - [-74.0, 420.0] + [ + 150.0, + 380.0 + ], + [ + 170.0, + 380.0 + ], + [ + 170.0, + 455.0 + ], + [ + -80.0, + 455.0 + ], + [ + -80.0, + 420.0 + ], + [ + -74.0, + 420.0 + ] ], "input": { "id": "pc+4", @@ -2038,8 +3215,14 @@ "type": "Wire", "id": "from pc+4:add_out to pc+4_reg:r_in", "pos": [ - [150.0, 380.0], - [230.0, 380.0] + [ + 150.0, + 380.0 + ], + [ + 230.0, + 380.0 + ] ], "input": { "id": "pc+4", @@ -2050,11 +3233,26 @@ "type": "Wire", "id": "from instruction_split:rt_out to reg_file:rt_address_in", "pos": [ - [431.0, 310.0], - [505.0, 310.0], - [505.0, 465.0], - [585.0, 465.0], - [585.0, 406.0] + [ + 431.0, + 310.0 + ], + [ + 505.0, + 310.0 + ], + [ + 505.0, + 465.0 + ], + [ + 585.0, + 465.0 + ], + [ + 585.0, + 406.0 + ] ], "input": { "id": "instruction_split", @@ -2065,8 +3263,14 @@ "type": "Wire", "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", "pos": [ - [1480.0, -40.0], - [1489.0, 0.0] + [ + 1480.0, + -40.0 + ], + [ + 1489.0, + 0.0 + ] ], "input": { "id": "control_MEM_reg", @@ -2076,7 +3280,10 @@ { "type": "PassThrough", "id": "operand_b_pass", - "pos": [1140.0, 325.0], + "pos": [ + 1140.0, + 325.0 + ], "input": { "id": "operand_b_reg", "field": "register_out" @@ -2086,9 +3293,18 @@ "type": "Wire", "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", "pos": [ - [1140.0, 325.0], - [1140.0, 585.0], - [1460.0, 585.0] + [ + 1140.0, + 325.0 + ], + [ + 1140.0, + 585.0 + ], + [ + 1460.0, + 585.0 + ] ], "input": { "id": "operand_b_pass", @@ -2099,11 +3315,26 @@ "type": "Wire", "id": "from instruction_split:rs_out to reg_file:rs_address_in", "pos": [ - [431.0, 196.0], - [440.0, 196.0], - [440.0, 120.0], - [585.0, 120.0], - [585.0, 144.0] + [ + 431.0, + 196.0 + ], + [ + 440.0, + 196.0 + ], + [ + 440.0, + 120.0 + ], + [ + 585.0, + 120.0 + ], + [ + 585.0, + 144.0 + ] ], "input": { "id": "instruction_split", @@ -2114,9 +3345,18 @@ "type": "Wire", "id": "from operand_b_reg:register_out to mux_source_b:in0", "pos": [ - [1140.0, 325.0], - [1140.0, 305.0], - [1230.0, 305.0] + [ + 1140.0, + 325.0 + ], + [ + 1140.0, + 305.0 + ], + [ + 1230.0, + 305.0 + ] ], "input": { "id": "operand_b_reg", @@ -2126,7 +3366,10 @@ { "type": "PassThrough", "id": "reg_addr_MEM_pass", - "pos": [1520.0, 520.0], + "pos": [ + 1520.0, + 520.0 + ], "input": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -2136,8 +3379,14 @@ "type": "Wire", "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", "pos": [ - [1520.0, 520.0], - [1910.0, 520.0] + [ + 1520.0, + 520.0 + ], + [ + 1910.0, + 520.0 + ] ], "input": { "id": "reg_addr_MEM_pass", @@ -2148,8 +3397,14 @@ "type": "Wire", "id": "from alu_reg:register_out to data_mem:data_mem_address_in", "pos": [ - [1630.0, 250.0], - [1630.0, 551.5] + [ + 1630.0, + 250.0 + ], + [ + 1630.0, + 551.5 + ] ], "input": { "id": "alu_reg", @@ -2160,8 +3415,14 @@ "type": "Wire", "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", "pos": [ - [651.0, 215.0], - [780.0, 215.0] + [ + 651.0, + 215.0 + ], + [ + 780.0, + 215.0 + ] ], "input": { "id": "reg_file", @@ -2172,8 +3433,14 @@ "type": "Wire", "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", "pos": [ - [1165.0, 520.0], - [1460.0, 520.0] + [ + 1165.0, + 520.0 + ], + [ + 1460.0, + 520.0 + ] ], "input": { "id": "reg_addr_EX_pass", @@ -2184,9 +3451,18 @@ "type": "Wire", "id": "from pc:register_out to pc+4:a_in", "pos": [ - [30.0, 390.0], - [30.0, 360.0], - [110.0, 360.0] + [ + 30.0, + 390.0 + ], + [ + 30.0, + 360.0 + ], + [ + 110.0, + 360.0 + ] ], "input": { "id": "pc", @@ -2197,8 +3473,14 @@ "type": "Wire", "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", "pos": [ - [1480.0, -40.0], - [1510.0, -40.0] + [ + 1480.0, + -40.0 + ], + [ + 1510.0, + -40.0 + ] ], "input": { "id": "control_MEM_reg", @@ -2209,14 +3491,25 @@ "type": "Wire", "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", "pos": [ - [1660.0, 13.5], - [1660.0, 551.5] + [ + 1660.0, + 13.5 + ], + [ + 1660.0, + 551.5 + ] ], "input": { "id": "control_unit_3", "field": "mem_write_enable" }, - "color_rgba": [0, 0, 0, 40] + "color_rgba": [ + 0, + 0, + 0, + 40 + ] } ] -} +} \ No newline at end of file diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index f6c27701..ac7e2316 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -1,4 +1,5 @@ use core::cell::RefCell; +use std::collections::HashMap; // use log::*; use serde::{Deserialize, Serialize}; use std::rc::Rc; @@ -29,6 +30,8 @@ pub struct InstrMem { #[serde(skip)] pub pc_history: RefCell>, + + pub dynamic_symbols: RefCell>, } impl InstrMem { @@ -51,6 +54,7 @@ impl InstrMem { #[cfg(feature = "gui-egui")] mem_view: RefCell::new(mem_view), pc_history: RefCell::new(vec![]), + dynamic_symbols: RefCell::new(HashMap::new()), } } pub fn rc_new( @@ -62,6 +66,53 @@ impl InstrMem { ) -> Rc { Rc::new(InstrMem::new(id, pos, pc_input, phys_mem_id, regfile_id)) } + pub fn update_dynamic_symbols(&self, new_pc: u32) { + let pc_history = self.pc_history.borrow(); + let mut new_dynamic_symbols = self.dynamic_symbols.borrow_mut().clone(); + if new_dynamic_symbols.contains_key("PC_IM") { + new_dynamic_symbols.insert( + "PC_IM".to_string(), + ( + new_pc, + new_dynamic_symbols.get_key_value("PC_IM").unwrap().1 .1, + ), + ); + } + if pc_history.len() > 1 { + if new_dynamic_symbols.contains_key("PC_DE") { + new_dynamic_symbols.insert( + "PC_DE".to_string(), + ( + pc_history[pc_history.len() - 1], + new_dynamic_symbols.get_key_value("PC_DE").unwrap().1 .1, + ), + ); + } + if pc_history.len() > 2 { + if new_dynamic_symbols.contains_key("PC_EX") { + new_dynamic_symbols.insert( + "PC_EX".to_string(), + ( + pc_history[pc_history.len() - 2], + new_dynamic_symbols.get_key_value("PC_EX").unwrap().1 .1, + ), + ); + } + if pc_history.len() > 3 { + if new_dynamic_symbols.contains_key("PC_DM") { + new_dynamic_symbols.insert( + "PC_DM".to_string(), + ( + pc_history[pc_history.len() - 3], + new_dynamic_symbols.get_key_value("PC_DM").unwrap().1 .1, + ), + ); + } + } + } + } + *self.dynamic_symbols.borrow_mut() = new_dynamic_symbols; + } } #[typetag::serde()] @@ -85,6 +136,7 @@ impl Component for InstrMem { #[cfg(feature = "gui-egui")] mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), pc_history: RefCell::new(vec![]), + dynamic_symbols: RefCell::new(HashMap::new()), })) } @@ -132,14 +184,10 @@ impl Component for InstrMem { .get(pc, MemOpSize::Word, false, true) }; - #[cfg(feature = "gui-egui")] self.pc_history .borrow_mut() - .push(self.mem_view.borrow().get_dynamic_symbol("PC_IM").unwrap()); - - // update dynamic symbol PC_IM - //#[cfg(feature = "gui-egui")] - //self.mem_view.borrow_mut().set_dynamic_symbol("PC_IM", pc); + .push(self.dynamic_symbols.borrow().get("PC_IM").unwrap().0); + self.update_dynamic_symbols(pc); // Get a word at PC with the size of 32bits, read as big endian, // sign extend doesn't mater since we have 32 bits so extending to 32bits does nothing @@ -159,21 +207,27 @@ impl Component for InstrMem { } } fn un_clock(&self) { - let mut pc_history = self.pc_history.borrow_mut(); - #[cfg(feature = "gui-egui")] - let mut mem_view = self.mem_view.borrow_mut(); - #[cfg(feature = "gui-egui")] - if (pc_history.len() >= 1) && (mem_view.get_dynamic_symbol("PC_IM") != None) { - mem_view.set_dynamic_symbol("PC_IM", pc_history.pop().unwrap()); - if (pc_history.len() >= 1) && (mem_view.get_dynamic_symbol("PC_DE") != None) { - mem_view.set_dynamic_symbol("PC_DE", pc_history[pc_history.len() - 1]); - if (pc_history.len() >= 2) && (mem_view.get_dynamic_symbol("PC_EX") != None) { - mem_view.set_dynamic_symbol("PC_EX", pc_history[pc_history.len() - 2]); - if (pc_history.len() >= 3) && (mem_view.get_dynamic_symbol("PC_DM") != None) { - mem_view.set_dynamic_symbol("PC_DM", pc_history[pc_history.len() - 3]); - } - } + let previous_pc: u32 = self.pc_history.borrow_mut().pop().unwrap(); + self.update_dynamic_symbols(previous_pc); + } + fn reset(&self) { + if self.pc_history.borrow().len() >= 1 { + let start_pc = self.pc_history.borrow()[0]; + let current_symbol_keys: Vec = + self.dynamic_symbols.borrow().keys().cloned().collect(); + + let mut new_symbols: HashMap = HashMap::new(); + for symbol_name in current_symbol_keys { + new_symbols.insert( + symbol_name.clone(), + ( + start_pc, + self.dynamic_symbols.borrow().get(&symbol_name).unwrap().1, + ), + ); } + *self.dynamic_symbols.borrow_mut() = new_symbols; + self.pc_history.borrow_mut().clear(); } } } diff --git a/mips-lib/src/gui_egui/components/mips_im.rs b/mips-lib/src/gui_egui/components/mips_im.rs index e22100ef..49ae414a 100644 --- a/mips-lib/src/gui_egui/components/mips_im.rs +++ b/mips-lib/src/gui_egui/components/mips_im.rs @@ -26,26 +26,6 @@ impl InstrMem { .borrow_mut() .set_reg_values(*reg.registers.borrow()); } - fn update_mem_view_dynamic_symbols(&self, sim: &Simulator) { - let mut mem_view = self.mem_view.borrow_mut(); - let pc_history = self.pc_history.borrow(); - if mem_view.get_dynamic_symbol("PC_IM") != None { - mem_view.set_dynamic_symbol( - "PC_IM", - std::convert::TryInto::::try_into((sim).get_input_value(&self.pc)).unwrap(), - ); - } - - if (pc_history.len() >= 2) && (mem_view.get_dynamic_symbol("PC_DE") != None) { - mem_view.set_dynamic_symbol("PC_DE", pc_history[pc_history.len() - 1]); - if (pc_history.len() >= 3) && (mem_view.get_dynamic_symbol("PC_EX") != None) { - mem_view.set_dynamic_symbol("PC_EX", pc_history[pc_history.len() - 2]); - if (pc_history.len() >= 4) && (mem_view.get_dynamic_symbol("PC_DM") != None) { - mem_view.set_dynamic_symbol("PC_DM", pc_history[pc_history.len() - 3]); - } - } - } - } } #[typetag::serde] @@ -98,7 +78,9 @@ impl EguiComponent for InstrMem { // handle mem_window and load of new file if let Some(ref sim) = simulator { self.update_mem_view_register_values(sim); - self.update_mem_view_dynamic_symbols(sim); + self.mem_view + .borrow_mut() + .set_all_dynamic_symbols(self.dynamic_symbols.borrow().clone()); #[allow(clippy::expect_fun_call)] let phys_mem: &PhysicalMem = find_component_with_type(sim, &self.phys_mem_id).expect( &format!("can't find {} with type PhysicalMem", self.regfile_id), diff --git a/mips-lib/src/gui_egui/mips_mem_view_window.rs b/mips-lib/src/gui_egui/mips_mem_view_window.rs index f9f9c798..9922ed4a 100644 --- a/mips-lib/src/gui_egui/mips_mem_view_window.rs +++ b/mips-lib/src/gui_egui/mips_mem_view_window.rs @@ -129,6 +129,21 @@ impl MemViewWindow { } } } + pub fn set_all_dynamic_symbols(&mut self, new_dynamic_symbols: HashMap) { + for symbol in new_dynamic_symbols { + self.dynamic_symbols.insert( + symbol.0.clone(), + ( + symbol.1 .0, + self.dynamic_symbols + .get_key_value((symbol.0).as_str()) + .unwrap() + .1 + .1, + ), + ); + } + } /// Get the address of a symbol, if no such symbol exist return None pub fn get_dynamic_symbol(&self, symbol: &str) -> Option { self.dynamic_symbols.get(symbol).map(|(adrs, _)| *adrs) From 5f74dd594a7e626821c36acf07a95809652049e6 Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Thu, 17 Jul 2025 06:20:50 +0200 Subject: [PATCH 04/17] undid unneccessary change --- mips-lib/src/gui_egui/components/mips_im.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mips-lib/src/gui_egui/components/mips_im.rs b/mips-lib/src/gui_egui/components/mips_im.rs index 49ae414a..a22eb5e3 100644 --- a/mips-lib/src/gui_egui/components/mips_im.rs +++ b/mips-lib/src/gui_egui/components/mips_im.rs @@ -76,7 +76,7 @@ impl EguiComponent for InstrMem { }); // handle mem_window and load of new file - if let Some(ref sim) = simulator { + if let Some(sim) = &simulator { self.update_mem_view_register_values(sim); self.mem_view .borrow_mut() From 9db898b1d897308bc0c8fc75908f514c493a33e6 Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Thu, 17 Jul 2025 06:47:47 +0200 Subject: [PATCH 05/17] comments and increasing readability --- mips-lib/src/components/mips_im.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index ac7e2316..5560d70f 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -206,12 +206,15 @@ impl Component for InstrMem { Err(_) => Err(Condition::Error(format!("Unaligned Read, PC = {:#0x}", pc))), } } + // set PC to what it was the previous cycle fn un_clock(&self) { let previous_pc: u32 = self.pc_history.borrow_mut().pop().unwrap(); self.update_dynamic_symbols(previous_pc); } + // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings + // while resetting values and adresses fn reset(&self) { - if self.pc_history.borrow().len() >= 1 { + if self.pc_history.borrow().len() > 0 { let start_pc = self.pc_history.borrow()[0]; let current_symbol_keys: Vec = self.dynamic_symbols.borrow().keys().cloned().collect(); From 6d37a003d3dbf89d02053126abef22460dad9e77 Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Thu, 17 Jul 2025 07:37:12 +0200 Subject: [PATCH 06/17] commenting --- mips-lib/src/gui_egui/mips_mem_view_window.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/mips-lib/src/gui_egui/mips_mem_view_window.rs b/mips-lib/src/gui_egui/mips_mem_view_window.rs index 9922ed4a..4c5522a3 100644 --- a/mips-lib/src/gui_egui/mips_mem_view_window.rs +++ b/mips-lib/src/gui_egui/mips_mem_view_window.rs @@ -129,6 +129,7 @@ impl MemViewWindow { } } } + // replaces all dynamic symbols with the given new_dynamic_symbols pub fn set_all_dynamic_symbols(&mut self, new_dynamic_symbols: HashMap) { for symbol in new_dynamic_symbols { self.dynamic_symbols.insert( From c8fdc9a947bf001397a291d12f0386762f69c4f8 Mon Sep 17 00:00:00 2001 From: Jakob Kieri Date: Thu, 17 Jul 2025 08:03:49 +0200 Subject: [PATCH 07/17] support for single cycle model --- mips-lib/mips_single_cycle.json | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/mips-lib/mips_single_cycle.json b/mips-lib/mips_single_cycle.json index f94af5b1..16a0605f 100644 --- a/mips-lib/mips_single_cycle.json +++ b/mips-lib/mips_single_cycle.json @@ -301,6 +301,12 @@ ] }, "break_points": [] + }, + "dynamic_symbols": { + "PC_IM": [ + 0, + true + ] } }, { @@ -1952,4 +1958,4 @@ } } ] -} +} \ No newline at end of file From 35e8e7ef88122642de1f0c9d4aba32aef5287aeb Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Tue, 26 Aug 2025 01:49:57 +0200 Subject: [PATCH 08/17] instruction memory dynamic symbols are now changed in-place + and fix Combobox deprecation --- mips-lib/src/components/mips_im.rs | 45 +++++-------------- mips-lib/src/gui_egui/mips_reg_view_window.rs | 2 +- 2 files changed, 12 insertions(+), 35 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 5560d70f..8a81d13e 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -68,50 +68,27 @@ impl InstrMem { } pub fn update_dynamic_symbols(&self, new_pc: u32) { let pc_history = self.pc_history.borrow(); - let mut new_dynamic_symbols = self.dynamic_symbols.borrow_mut().clone(); - if new_dynamic_symbols.contains_key("PC_IM") { - new_dynamic_symbols.insert( - "PC_IM".to_string(), - ( - new_pc, - new_dynamic_symbols.get_key_value("PC_IM").unwrap().1 .1, - ), - ); + let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); + + if dynamic_symbols.contains_key("PC_IM") { + dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; } if pc_history.len() > 1 { - if new_dynamic_symbols.contains_key("PC_DE") { - new_dynamic_symbols.insert( - "PC_DE".to_string(), - ( - pc_history[pc_history.len() - 1], - new_dynamic_symbols.get_key_value("PC_DE").unwrap().1 .1, - ), - ); + if dynamic_symbols.contains_key("PC_DE") { + dynamic_symbols.get_mut("PC_DE").unwrap().0 = pc_history[pc_history.len() - 1]; } if pc_history.len() > 2 { - if new_dynamic_symbols.contains_key("PC_EX") { - new_dynamic_symbols.insert( - "PC_EX".to_string(), - ( - pc_history[pc_history.len() - 2], - new_dynamic_symbols.get_key_value("PC_EX").unwrap().1 .1, - ), - ); + if dynamic_symbols.contains_key("PC_EX") { + dynamic_symbols.get_mut("PC_EX").unwrap().0 = pc_history[pc_history.len() - 2]; } if pc_history.len() > 3 { - if new_dynamic_symbols.contains_key("PC_DM") { - new_dynamic_symbols.insert( - "PC_DM".to_string(), - ( - pc_history[pc_history.len() - 3], - new_dynamic_symbols.get_key_value("PC_DM").unwrap().1 .1, - ), - ); + if dynamic_symbols.contains_key("PC_DM") { + dynamic_symbols.get_mut("PC_DM").unwrap().0 = + pc_history[pc_history.len() - 3]; } } } } - *self.dynamic_symbols.borrow_mut() = new_dynamic_symbols; } } diff --git a/mips-lib/src/gui_egui/mips_reg_view_window.rs b/mips-lib/src/gui_egui/mips_reg_view_window.rs index ca398f84..c45d98a2 100644 --- a/mips-lib/src/gui_egui/mips_reg_view_window.rs +++ b/mips-lib/src/gui_egui/mips_reg_view_window.rs @@ -85,7 +85,7 @@ impl RegViewWindow { // show the display format of the register let mut tmp: RegFormat = self.reg_format.clone(); - ComboBox::from_id_source(&self.id) + ComboBox::from_id_salt(&self.id) .selected_text(format!("{:?}", tmp)) .show_ui(ui, |ui| { ui.selectable_value(&mut tmp, RegFormat::Hex, "Hex"); From b16b7a774840213d45213ca93a7323f1cab1717b Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Thu, 28 Aug 2025 20:26:45 +0200 Subject: [PATCH 09/17] spooky scary unclocking, but atleast it shows super nice promise --- mips-lib/src/components/mips_im.rs | 50 ++++++++++-------------------- 1 file changed, 17 insertions(+), 33 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index ac11a6b4..9f928a8f 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -32,12 +32,10 @@ pub struct InstrMem { #[serde(skip)] pub load_err: RefCell>, - #[serde(skip)] pub pc_history: RefCell>, pub dynamic_symbols: RefCell>, - } impl InstrMem { @@ -59,14 +57,11 @@ impl InstrMem { regfile_id, #[cfg(feature = "gui-egui")] mem_view: RefCell::new(mem_view), - - regfile_id, #[cfg(feature = "gui-egui")] load_err: RefCell::new(None), pc_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), - } } pub fn rc_new( @@ -78,29 +73,22 @@ impl InstrMem { ) -> Rc { Rc::new(InstrMem::new(id, pos, pc_input, phys_mem_id, regfile_id)) } - pub fn update_dynamic_symbols(&self, new_pc: u32) { - let pc_history = self.pc_history.borrow(); + pub fn clock_dynamic_symbols(&self, new_pc: u32) { let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); - if dynamic_symbols.contains_key("PC_IM") { - dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; - } - if pc_history.len() > 1 { - if dynamic_symbols.contains_key("PC_DE") { - dynamic_symbols.get_mut("PC_DE").unwrap().0 = pc_history[pc_history.len() - 1]; - } - if pc_history.len() > 2 { - if dynamic_symbols.contains_key("PC_EX") { - dynamic_symbols.get_mut("PC_EX").unwrap().0 = pc_history[pc_history.len() - 2]; - } - if pc_history.len() > 3 { - if dynamic_symbols.contains_key("PC_DM") { - dynamic_symbols.get_mut("PC_DM").unwrap().0 = - pc_history[pc_history.len() - 3]; - } - } - } - } + dynamic_symbols.get_mut("PC_DM").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; + dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; + dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_IM").unwrap().0; + dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; + } + + pub fn unclock_dynamic_symbols(&self, new_pc: u32) { + let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); + + dynamic_symbols.get_mut("PC_IM").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; + dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; + dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DM").unwrap().0; + dynamic_symbols.get_mut("PC_DM").unwrap().0 = new_pc; } } @@ -125,13 +113,9 @@ impl Component for InstrMem { mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), regfile_id: "dummy".into(), load_err: RefCell::new(None), - - regfile_id: "dummy".into(), #[cfg(feature = "gui-egui")] - mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), pc_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), - })) } @@ -182,7 +166,7 @@ impl Component for InstrMem { self.pc_history .borrow_mut() .push(self.dynamic_symbols.borrow().get("PC_IM").unwrap().0); - self.update_dynamic_symbols(pc); + self.clock_dynamic_symbols(pc); // Get a word at PC with the size of 32bits, read as big endian, // sign extend doesn't mater since we have 32 bits so extending to 32bits does nothing @@ -202,9 +186,9 @@ impl Component for InstrMem { } } // set PC to what it was the previous cycle - fn un_clock(&self) { + fn un_clock(&self, simulator: &Simulator) { let previous_pc: u32 = self.pc_history.borrow_mut().pop().unwrap(); - self.update_dynamic_symbols(previous_pc); + self.unclock_dynamic_symbols(previous_pc); } // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses From f54d3299bee09d98fd4e388bbdad1c08b09d28dd Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Thu, 28 Aug 2025 20:45:16 +0200 Subject: [PATCH 10/17] it works yet also not. How: I don't know, perhaps everything will be revealed in my dreams --- mips-lib/src/components/mips_im.rs | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 9f928a8f..b2bfbdbb 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -32,9 +32,6 @@ pub struct InstrMem { #[serde(skip)] pub load_err: RefCell>, - #[serde(skip)] - pub pc_history: RefCell>, - pub dynamic_symbols: RefCell>, } @@ -60,7 +57,6 @@ impl InstrMem { #[cfg(feature = "gui-egui")] load_err: RefCell::new(None), - pc_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), } } @@ -113,8 +109,6 @@ impl Component for InstrMem { mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), regfile_id: "dummy".into(), load_err: RefCell::new(None), - #[cfg(feature = "gui-egui")] - pc_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), })) } @@ -163,9 +157,6 @@ impl Component for InstrMem { .get(pc, MemOpSize::Word, false, true) }; - self.pc_history - .borrow_mut() - .push(self.dynamic_symbols.borrow().get("PC_IM").unwrap().0); self.clock_dynamic_symbols(pc); // Get a word at PC with the size of 32bits, read as big endian, @@ -187,12 +178,13 @@ impl Component for InstrMem { } // set PC to what it was the previous cycle fn un_clock(&self, simulator: &Simulator) { - let previous_pc: u32 = self.pc_history.borrow_mut().pop().unwrap(); - self.unclock_dynamic_symbols(previous_pc); + let pc: u32 = simulator.get_input_value(&self.pc).try_into().unwrap(); + self.unclock_dynamic_symbols(pc); } // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses fn reset(&self) { + /* if self.pc_history.borrow().len() > 0 { let start_pc = self.pc_history.borrow()[0]; let current_symbol_keys: Vec = @@ -210,6 +202,6 @@ impl Component for InstrMem { } *self.dynamic_symbols.borrow_mut() = new_symbols; self.pc_history.borrow_mut().clear(); - } + }*/ } } From 66afa9fc70fbc7b3411830a2a9621cef761a24f3 Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Mon, 1 Sep 2025 18:20:34 +0200 Subject: [PATCH 11/17] I have suceeded in removing if-statements AND learned that "pc_dm_history: RefCell>" may be necessary --- mips-lib/src/components/mips_im.rs | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index b2bfbdbb..3951939e 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -32,6 +32,9 @@ pub struct InstrMem { #[serde(skip)] pub load_err: RefCell>, + #[serde(skip)] + pub pc_dm_history: RefCell>, + pub dynamic_symbols: RefCell>, } @@ -56,6 +59,7 @@ impl InstrMem { mem_view: RefCell::new(mem_view), #[cfg(feature = "gui-egui")] load_err: RefCell::new(None), + pc_dm_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), } @@ -71,6 +75,9 @@ impl InstrMem { } pub fn clock_dynamic_symbols(&self, new_pc: u32) { let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); + let mut pc_dm_history = self.pc_dm_history.borrow_mut(); + // Store previous PC_DM, because unclocking doesn't provide info about PC_DM-stage + pc_dm_history.push(dynamic_symbols.get_mut("PC_DM").unwrap().0); dynamic_symbols.get_mut("PC_DM").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; @@ -78,13 +85,13 @@ impl InstrMem { dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; } - pub fn unclock_dynamic_symbols(&self, new_pc: u32) { + pub fn unclock_dynamic_symbols(&self) { let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); - dynamic_symbols.get_mut("PC_IM").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DM").unwrap().0; - dynamic_symbols.get_mut("PC_DM").unwrap().0 = new_pc; + dynamic_symbols.get_mut("PC_DM").unwrap().0 = + self.pc_dm_history.borrow_mut().pop().unwrap(); } } @@ -109,6 +116,7 @@ impl Component for InstrMem { mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), regfile_id: "dummy".into(), load_err: RefCell::new(None), + pc_dm_history: RefCell::new(vec![]), dynamic_symbols: RefCell::new(HashMap::new()), })) } @@ -178,8 +186,7 @@ impl Component for InstrMem { } // set PC to what it was the previous cycle fn un_clock(&self, simulator: &Simulator) { - let pc: u32 = simulator.get_input_value(&self.pc).try_into().unwrap(); - self.unclock_dynamic_symbols(pc); + self.unclock_dynamic_symbols(); } // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses From 07f24e1decc0a7e3a648a0f7dbc7dac3c5debeb2 Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Mon, 1 Sep 2025 19:10:59 +0200 Subject: [PATCH 12/17] Reset also works as intended --- mips-lib/src/components/mips_im.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 3951939e..82f05d1d 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -1,4 +1,5 @@ use core::cell::RefCell; +use elf::symbol::{self, Symbol}; use std::collections::HashMap; // use log::*; use serde::{Deserialize, Serialize}; @@ -191,6 +192,15 @@ impl Component for InstrMem { // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses fn reset(&self) { + if self.pc_dm_history.borrow().len() > 0 { + let start_pc = self.pc_dm_history.borrow()[0]; + let symbol_keys: Vec = self.dynamic_symbols.borrow().keys().cloned().collect(); + + let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); + for symbol_name in symbol_keys { + dynamic_symbols.get_mut(&symbol_name).unwrap().0 = start_pc; + } + } /* if self.pc_history.borrow().len() > 0 { let start_pc = self.pc_history.borrow()[0]; From bb9af57a6d090ff484671b852295298a2b8f1b47 Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Mon, 1 Sep 2025 19:15:08 +0200 Subject: [PATCH 13/17] cleaning --- mips-lib/src/components/mips_im.rs | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 82f05d1d..c6c46a74 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -1,5 +1,4 @@ use core::cell::RefCell; -use elf::symbol::{self, Symbol}; use std::collections::HashMap; // use log::*; use serde::{Deserialize, Serialize}; @@ -186,7 +185,7 @@ impl Component for InstrMem { } } // set PC to what it was the previous cycle - fn un_clock(&self, simulator: &Simulator) { + fn un_clock(&self, _simulator: &Simulator) { self.unclock_dynamic_symbols(); } // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings @@ -201,24 +200,5 @@ impl Component for InstrMem { dynamic_symbols.get_mut(&symbol_name).unwrap().0 = start_pc; } } - /* - if self.pc_history.borrow().len() > 0 { - let start_pc = self.pc_history.borrow()[0]; - let current_symbol_keys: Vec = - self.dynamic_symbols.borrow().keys().cloned().collect(); - - let mut new_symbols: HashMap = HashMap::new(); - for symbol_name in current_symbol_keys { - new_symbols.insert( - symbol_name.clone(), - ( - start_pc, - self.dynamic_symbols.borrow().get(&symbol_name).unwrap().1, - ), - ); - } - *self.dynamic_symbols.borrow_mut() = new_symbols; - self.pc_history.borrow_mut().clear(); - }*/ } } From c6d100c2a8294044120a4f16c473c67e5b1e31ab Mon Sep 17 00:00:00 2001 From: Jakob Kieri <98048355+jakobkieri@users.noreply.github.com> Date: Tue, 2 Sep 2025 16:54:47 +0200 Subject: [PATCH 14/17] Made comments more accurate --- mips-lib/src/components/mips_im.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index c6c46a74..9b06495f 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -184,11 +184,11 @@ impl Component for InstrMem { Err(_) => Err(Condition::Error(format!("Unaligned Read, PC = {:#0x}", pc))), } } - // set PC to what it was the previous cycle + // set component to what it was the previous cycle fn un_clock(&self, _simulator: &Simulator) { self.unclock_dynamic_symbols(); } - // if the simulator is reset and pc_history isn't empty: move over dynamic_symbol settings + // if the simulator is reset and pc_dm_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses fn reset(&self) { if self.pc_dm_history.borrow().len() > 0 { From 8010ba522c508c4b32bca966e895a28a93c7822a Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Tue, 2 Sep 2025 17:54:56 +0200 Subject: [PATCH 15/17] mips_single_cycle.json also works now --- mips-lib/src/components/mips_im.rs | 38 ++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 9b06495f..148a3681 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -76,22 +76,33 @@ impl InstrMem { pub fn clock_dynamic_symbols(&self, new_pc: u32) { let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); let mut pc_dm_history = self.pc_dm_history.borrow_mut(); - // Store previous PC_DM, because unclocking doesn't provide info about PC_DM-stage - pc_dm_history.push(dynamic_symbols.get_mut("PC_DM").unwrap().0); - dynamic_symbols.get_mut("PC_DM").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; - dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; - dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_IM").unwrap().0; + if dynamic_symbols.contains_key("PC_DM") + && dynamic_symbols.contains_key("PC_EX") + && dynamic_symbols.contains_key("PC_DE") + { + // Store previous PC_DM, because unclocking doesn't provide info about PC_DM-stage + pc_dm_history.push(dynamic_symbols.get_mut("PC_DM").unwrap().0); + + dynamic_symbols.get_mut("PC_DM").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; + dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; + dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_IM").unwrap().0; + } dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; } - pub fn unclock_dynamic_symbols(&self) { + pub fn unclock_dynamic_symbols(&self, new_pc: u32) { let mut dynamic_symbols = self.dynamic_symbols.borrow_mut(); - dynamic_symbols.get_mut("PC_IM").unwrap().0 = dynamic_symbols.get("PC_DE").unwrap().0; - dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; - dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DM").unwrap().0; - dynamic_symbols.get_mut("PC_DM").unwrap().0 = - self.pc_dm_history.borrow_mut().pop().unwrap(); + dynamic_symbols.get_mut("PC_IM").unwrap().0 = new_pc; + if dynamic_symbols.contains_key("PC_DM") + && dynamic_symbols.contains_key("PC_EX") + && dynamic_symbols.contains_key("PC_DE") + { + dynamic_symbols.get_mut("PC_DE").unwrap().0 = dynamic_symbols.get("PC_EX").unwrap().0; + dynamic_symbols.get_mut("PC_EX").unwrap().0 = dynamic_symbols.get("PC_DM").unwrap().0; + dynamic_symbols.get_mut("PC_DM").unwrap().0 = + self.pc_dm_history.borrow_mut().pop().unwrap(); + } } } @@ -185,8 +196,9 @@ impl Component for InstrMem { } } // set component to what it was the previous cycle - fn un_clock(&self, _simulator: &Simulator) { - self.unclock_dynamic_symbols(); + fn un_clock(&self, simulator: &Simulator) { + let pc: u32 = simulator.get_input_value(&self.pc).try_into().unwrap(); + self.unclock_dynamic_symbols(pc); } // if the simulator is reset and pc_dm_history isn't empty: move over dynamic_symbol settings // while resetting values and adresses From f8d33b1eb650b9f17d02f1015c82b6738c1c25e7 Mon Sep 17 00:00:00 2001 From: Jakob Kieri <98048355+jakobkieri@users.noreply.github.com> Date: Tue, 2 Sep 2025 18:16:37 +0200 Subject: [PATCH 16/17] Cleaning removed row removed row fix comment cleaning --- mips-lib/src/components/mips_im.rs | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 148a3681..863d33bb 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -27,14 +27,11 @@ pub struct InstrMem { pub regfile_id: String, #[cfg(feature = "gui-egui")] pub mem_view: RefCell, - #[cfg(feature = "gui-egui")] #[serde(skip)] pub load_err: RefCell>, - #[serde(skip)] pub pc_dm_history: RefCell>, - pub dynamic_symbols: RefCell>, } @@ -60,7 +57,6 @@ impl InstrMem { #[cfg(feature = "gui-egui")] load_err: RefCell::new(None), pc_dm_history: RefCell::new(vec![]), - dynamic_symbols: RefCell::new(HashMap::new()), } } @@ -123,7 +119,6 @@ impl Component for InstrMem { pos, pc: dummy_input, phys_mem_id: "dummy".into(), - mem_view: RefCell::new(MemViewWindow::new("dummy".into(), "IM dummy".into())), regfile_id: "dummy".into(), load_err: RefCell::new(None), @@ -201,7 +196,7 @@ impl Component for InstrMem { self.unclock_dynamic_symbols(pc); } // if the simulator is reset and pc_dm_history isn't empty: move over dynamic_symbol settings - // while resetting values and adresses + // while resetting adresses fn reset(&self) { if self.pc_dm_history.borrow().len() > 0 { let start_pc = self.pc_dm_history.borrow()[0]; From 464bf35062bb14a5f40e245b41d9ee8eda46abd1 Mon Sep 17 00:00:00 2001 From: jakobkieri Date: Wed, 3 Sep 2025 14:10:09 +0200 Subject: [PATCH 17/17] clear the pc_dm_history vector --- mips-lib/src/components/mips_im.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/mips-lib/src/components/mips_im.rs b/mips-lib/src/components/mips_im.rs index 863d33bb..7304d8f4 100644 --- a/mips-lib/src/components/mips_im.rs +++ b/mips-lib/src/components/mips_im.rs @@ -206,6 +206,7 @@ impl Component for InstrMem { for symbol_name in symbol_keys { dynamic_symbols.get_mut(&symbol_name).unwrap().0 = start_pc; } + self.pc_dm_history.borrow_mut().clear(); } } }