Timing closure issue

[radomirvr]

First of all, many thanks for this great port!

Issue Description

I'm trying to make the bitstream, but the design fails to meet the timing requirements by around 80 ps. Most of the paths are inter clock, between the rfdc_clk_x411_ps_rfdc_bd_data_clock_mmcm_0 and the rfdc_clk_2x_x411_ps_rfdc_bd_data_clock_mmcm_0 clock. I'm attaching the timing summary below.

The original ettus design (tag v4.4.0.0, commit 5fac246) passes timing successfully.

Should the design pass the timing or is this perhaps expected?

Setup Details

• Vivado v2021.1_AR76780
• x411 branch (commit f2901c6)
• X411_X4_200 design

Expected Behavior

Timing pass.

Actual Behaviour

Timing closure failed:

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Steps to reproduce the problem

make X411_X4_200

Additional Information

post_route_timing_summary.log

[ptrkrysik]

This is not expected behavior. I had some issues with 10 MHz reference clock when I tried to port newer code with X440 support, but this older design should meet timing requirements. I'll try to run the build on this code again.

[ptrkrysik]

I got also failure to meet timing requirements. Thank you for reporting this issue.
I'll try to find out where it came from.

[penavy]

Hi, is there any update on this issue? I am also getting failures in meeting the timing requirements. Vivado v2021.1_AR76780, commit f2901c6, various targets (X411_X4_200, X411_X4_400, experimental X411_C1_200).

Thank you!

[ptrkrysik]

Hi @penavy. I don't have update and I don't have the setup to build the bitstream for X411 currently. The log says that there's negative slack for PLL_REFCLK_FPGA_P - which is needed by RFDC. I don't have a good idea what my cause this but I would disable all FPGA pins that is not strictly necessary:

• base ref clock output which even is not needed e0a3626 to anything,
• control of GPIO output with use of a lowest bit from signal sample a627549,
• BASE_REFCLK_FPGA_P (10MHz ref),
• PPS_IN (PPS) ,
• GPIO pins on PMOD bb4846e,
• LMK sync 70e9e59,
• TRIG_IO 92fa1ec

and if the bitstream will be built successfully add those of these features that are needed.

[ptrkrysik]

Also replay block (defined for example in x411_200_rfnoc_image_core.yml) is not strictly necessary. @penavy - do you have environment needed to perform building of FPGA bitstream?

[ptrkrysik]

Issue solved by commits a6b127d, d47aed1, 2181014.
Some functionality is lost (external time synchronization, GPIO pins, control of GPIO pins with samples).
This can be brought back by user in case some of those functionalities are needed.

[penavy]

Thank you for your quick response! Yes, I have the environment for building the bitstream. I have reverted the changes by the commits you suggested (I have kept the replay block in rfnoc), and the timing requirements are met. Your last commit (a6b127d) also passes.