Align I2C and PIO on rp2040 and rp2350

ithinuel · ithinuel · commit 62be79ea6e81 · 2025-03-21T20:21:58.000Z
diff --git a/rp2040-hal/src/pio.rs b/rp2040-hal/src/pio.rs
@@ -665,8 +665,8 @@ impl<SM: ValidStateMachine, State> StateMachine<SM, State> {
     pub fn clear_fifos(&mut self) {
         // Safety: all accesses to these registers are controlled by this instance
         unsafe {
-            let sm = &self.sm.sm();
-            let sm_shiftctrl = &sm.sm_shiftctrl();
+            let sm = self.sm.sm();
+            let sm_shiftctrl = sm.sm_shiftctrl();
             let mut current = false;
             // Toggling the FIFO join state clears the fifo
             sm_shiftctrl.modify(|r, w| {
@@ -699,10 +699,10 @@ impl<SM: ValidStateMachine, State> StateMachine<SM, State> {
 
         // Safety: all accesses to these registers are controlled by this instance
         unsafe {
-            let sm = &self.sm.sm();
-            let sm_pinctrl = &sm.sm_pinctrl();
-            let sm_instr = &sm.sm_instr();
-            let fstat = &self.sm.pio().fstat();
+            let sm = self.sm.sm();
+            let sm_pinctrl = sm.sm_pinctrl();
+            let sm_instr = sm.sm_instr();
+            let fstat = self.sm.pio().fstat();
 
             let operands = if sm.sm_shiftctrl().read().autopull().bit_is_set() {
                 OUT
@@ -793,9 +793,9 @@ impl<SM: ValidStateMachine> StateMachine<SM, Stopped> {
         // Safety: all accesses to these registers are controlled by this instance
         unsafe {
             let sm = self.sm.sm();
-            let sm_pinctrl = &sm.sm_pinctrl();
-            let sm_execctrl = &sm.sm_execctrl();
-            let sm_instr = &sm.sm_instr();
+            let sm_pinctrl = sm.sm_pinctrl();
+            let sm_execctrl = sm.sm_execctrl();
+            let sm_instr = sm.sm_instr();
 
             // sideset_count is implicitly set to 0 when the set_base/set_count are written (rather
             // than modified)
@@ -1294,8 +1294,8 @@ impl<SM: ValidStateMachine> StateMachine<SM, Running> {
         // Safety: all accesses to these registers are controlled by this instance
         unsafe {
             let sm = self.sm.sm();
-            let sm_pinctrl = &sm.sm_pinctrl();
-            let sm_instr = &sm.sm_instr();
+            let sm_pinctrl = sm.sm_pinctrl();
+            let sm_instr = sm.sm_instr();
 
             // save exec_ctrl & make side_set optional
             let mut saved_sideset_count = 0;
diff --git a/rp235x-hal/src/i2c/peripheral.rs b/rp235x-hal/src/i2c/peripheral.rs
@@ -210,10 +210,10 @@ impl<T: Deref<Target = RegisterBlock>, PINS> Iterator for I2C<T, PINS, Periphera
     }
 }
 impl<T: Deref<Target = RegisterBlock>, PINS> I2C<T, PINS, Peripheral> {
-    /// Returns the next i2c event if any.
-    pub fn next_event(&mut self) -> Option<Event> {
-        let stat = self.i2c.ic_raw_intr_stat().read();
-
+    fn internal_next_event(
+        &mut self,
+        stat: rp235x_pac::i2c0::ic_raw_intr_stat::R,
+    ) -> Option<Event> {
         match self.mode.state {
             State::Idle if stat.start_det().bit_is_set() => {
                 self.i2c.ic_clr_start_det().read();
@@ -241,7 +241,7 @@ impl<T: Deref<Target = RegisterBlock>, PINS> I2C<T, PINS, Peripheral> {
             State::Read if stat.rd_req().bit_is_set() => Some(Event::TransferRead),
             State::Write if !self.rx_fifo_empty() => Some(Event::TransferWrite),
 
-            State::Read | State::Write if stat.restart_det().bit_is_set() => {
+            State::Read | State::Write | State::Active if stat.restart_det().bit_is_set() => {
                 self.i2c.ic_clr_restart_det().read();
                 self.i2c.ic_clr_start_det().read();
                 self.mode.state = State::Active;
@@ -258,6 +258,13 @@ impl<T: Deref<Target = RegisterBlock>, PINS> I2C<T, PINS, Peripheral> {
             _ => None,
         }
     }
+
+    /// Returns the next i2c event if any.
+    pub fn next_event(&mut self) -> Option<Event> {
+        let stat = self.i2c.ic_raw_intr_stat().read();
+
+        self.internal_next_event(stat)
+    }
 }
 
 macro_rules! impl_wakeable {
@@ -291,12 +298,13 @@ where
 {
     /// Asynchronously waits for an Event.
     pub async fn wait_next(&mut self) -> Event {
+        let mut stat = self.i2c.ic_raw_intr_stat().read();
         loop {
-            if let Some(evt) = self.next_event() {
+            if let Some(evt) = self.internal_next_event(stat) {
                 return evt;
             }
 
-            CancellablePollFn::new(
+            stat = CancellablePollFn::new(
                 self,
                 |me| {
                     let stat = me.i2c.ic_raw_intr_stat().read();
@@ -306,7 +314,7 @@ where
                         || stat.rd_req().bit_is_set()
                         || stat.rx_full().bit_is_set()
                     {
-                        Poll::Ready(())
+                        Poll::Ready(stat)
                     } else {
                         Poll::Pending
                     }
diff --git a/rp235x-hal/src/pio.rs b/rp235x-hal/src/pio.rs
@@ -15,16 +15,27 @@ use crate::{
     typelevel::Sealed,
 };
 
+mod non_blocking;
+
 const PIO_INSTRUCTION_COUNT: usize = 32;
 
 impl Sealed for PIO0 {}
 impl Sealed for PIO1 {}
 
 /// PIO Instance
 pub trait PIOExt: Deref<Target = RegisterBlock> + SubsystemReset + Sized + Send + Sealed {
+    /// RX FIFO depth
+    const RX_FIFO_DEPTH: usize;
+
+    /// TX FIFO depth
+    const TX_FIFO_DEPTH: usize;
+
     /// Associated Pin Function.
     type PinFunction: Function;
 
+    /// Returns a pointer to the PIO’s Register Block
+    fn ptr() -> *const RegisterBlock;
+
     /// Create a new PIO wrapper and split the state machines into individual objects.
     #[allow(clippy::type_complexity)] // Required for symmetry with PIO::free().
     fn split(
@@ -77,13 +88,23 @@ pub trait PIOExt: Deref<Target = RegisterBlock> + SubsystemReset + Sized + Send
 }
 
 impl PIOExt for PIO0 {
+    const RX_FIFO_DEPTH: usize = 4;
+    const TX_FIFO_DEPTH: usize = 4;
     type PinFunction = FunctionPio0;
+    fn ptr() -> *const RegisterBlock {
+        PIO0::ptr()
+    }
     fn id() -> usize {
         0
     }
 }
 impl PIOExt for PIO1 {
+    const RX_FIFO_DEPTH: usize = 4;
+    const TX_FIFO_DEPTH: usize = 4;
     type PinFunction = FunctionPio1;
+    fn ptr() -> *const RegisterBlock {
+        PIO1::ptr()
+    }
     fn id() -> usize {
         1
     }
@@ -586,9 +607,9 @@ pub struct Running;
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum PioIRQ {
     #[allow(missing_docs)]
-    Irq0,
+    Irq0 = 0,
     #[allow(missing_docs)]
-    Irq1,
+    Irq1 = 1,
 }
 impl PioIRQ {
     const fn to_index(self) -> usize {
@@ -1392,6 +1413,32 @@ impl<SM: ValidStateMachine, RxSize: TransferSize> Rx<SM, RxSize> {
         unsafe { self.block().fstat().read().rxfull().bits() & (1 << SM::id()) != 0 }
     }
 
+    /// Reads the number of word in the fifo
+    pub fn fifo_level(&self) -> usize {
+        // Safety: read-only access without side-effect
+        let flevel = unsafe { self.block().flevel().read() };
+        (match SM::id() {
+            0 => flevel.rx0().bits(),
+            1 => flevel.rx1().bits(),
+            2 => flevel.rx2().bits(),
+            3 => flevel.rx3().bits(),
+            _ => unreachable!(),
+        }) as usize
+    }
+
+    /// Returns the FIFO depth.
+    pub fn fifo_depth(&self) -> usize {
+        // Safety: read-only access without side-effect
+        let block = unsafe { self.block() };
+        let join_rx = block.sm(SM::id()).sm_shiftctrl().read().fjoin_rx().bit();
+        let depth = block.dbg_cfginfo().read().fifo_depth().bits() as usize;
+        if join_rx {
+            depth * 2
+        } else {
+            depth
+        }
+    }
+
     /// Enable RX FIFO not empty interrupt.
     ///
     /// This interrupt is raised when the RX FIFO is not empty, i.e. one could read more data from it.
@@ -1510,7 +1557,7 @@ impl<SM: ValidStateMachine, TxSize: TransferSize> Tx<SM, TxSize> {
     /// This is a value between 0 and 39. Each FIFO on each state machine on
     /// each PIO has a unique value.
     pub fn dreq_value(&self) -> u8 {
-        if self.block as usize == 0x5020_0000usize {
+        if self.block == PIO0::ptr() {
             TREQ_SEL_A::PIO0_TX0 as u8 + (SM::id() as u8)
         } else {
             TREQ_SEL_A::PIO1_TX0 as u8 + (SM::id() as u8)
@@ -1600,6 +1647,32 @@ impl<SM: ValidStateMachine, TxSize: TransferSize> Tx<SM, TxSize> {
         unsafe { self.block().fstat().read().txfull().bits() & (1 << SM::id()) != 0 }
     }
 
+    /// Reads the number of word in the FIFO
+    pub fn fifo_level(&self) -> usize {
+        // Safety: read-only access without side-effect
+        let flevel = unsafe { self.block().flevel().read() };
+        (match SM::id() {
+            0 => flevel.tx0().bits(),
+            1 => flevel.tx1().bits(),
+            2 => flevel.tx2().bits(),
+            3 => flevel.tx3().bits(),
+            _ => unreachable!(),
+        }) as usize
+    }
+
+    /// Returns the FIFO depth.
+    pub fn fifo_depth(&self) -> usize {
+        // Safety: read-only access without side-effect
+        let block = unsafe { self.block() };
+        let join_tx = block.sm(SM::id()).sm_shiftctrl().read().fjoin_tx().bit();
+        let depth = block.dbg_cfginfo().read().fifo_depth().bits() as usize;
+        if join_tx {
+            depth * 2
+        } else {
+            depth
+        }
+    }
+
     /// Enable TX FIFO not full interrupt.
     ///
     /// This interrupt is raised when the TX FIFO is not full, i.e. one could push more data to it.
diff --git a/rp235x-hal/src/pio/non_blocking.rs b/rp235x-hal/src/pio/non_blocking.rs
