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Chris Andersonrusefillc
Chris Anderson
authored and
rusefillc
committed
gdi4 boost duration
initial microcode and memory locations for boost duration
1 parent a21f3ee commit d69d0f1

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12 files changed

+75
-58
lines changed

12 files changed

+75
-58
lines changed

‎pt2001/include/rusefi/pt2001_memory_map.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ enum class MC33816Mem {
1818
Thold_tot = PT2001_D1_Thold_tot,
1919
Tboost_min = PT2001_D1_Tboost_min,
2020
Tboost_max = PT2001_D1_Tboost_max,
21+
Tboost_inj12 = PT2001_D1_Tboost_inj12,
22+
Tboost_inj34 = PT2001_D1_Tboost_inj34,
2123
// see dram2.def values, base 64 for channel 2
2224
Vboost_high = PT2001_D2_Vboost_high,
2325
Vboost_low = PT2001_D2_Vboost_low,

‎pt2001/project/rusefi/MicrocodeCh1/ch1.psc‎

Lines changed: 26 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ init0: stgn gain12.6 sssc; * Set the gain of the opamp
99
ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
1010
ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
1111
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
12+
13+
* stoc on sssc;
1214

1315
* ### Idle phase- the uPC loops here until start signal is present ###
1416
idle0: joslr inj1_start start1; * Perform an actuation on inj1 if start 1 (only) is active
@@ -42,7 +44,7 @@ boost0: load Iboost dac_sssc _ofs; * Load the boost phase curre
4244
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
4345
cwer boost0_err tc2 row5; * Jump to boost0_err in case boost phase takes too long
4446

45-
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
47+
stf low b1; * set flag1 low to force the DC-DC converter in idle mode
4648
stos off on on; * Turn VBAT off, BOOST on, LS on
4749
wait row1245; * Wait for one of the previously defined conditions
4850

@@ -51,17 +53,24 @@ boost0_mintime: wait row135; * Minimum time for boost pha
5153

5254
boost0_err: stos off off off; * Turn off all drivers
5355
stf low b10; * Set ch1 error flag (OA_1) to signal MCU
54-
stf high b0; * set flag0 high to release the DC-DC converter idle mode
56+
stf high b1; * set flag0 high to release the DC-DC converter idle mode
5557
wait row1; * Wait for start signal to go low for the next injection attempt
5658

5759
* ### Peak phase continue on Vbat ###
58-
peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
60+
peak0: store cnt2 Tboost_inj12 _ofs;
61+
stos keep off keep;
62+
ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
5963
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
6064
cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
6165
cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count
6266
cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold
63-
stf high b0; * set flag0 high to release the DC-DC converter idle mode
67+
stf high b1; * set flag0 high to release the DC-DC converter idle mode
6468

69+
* we are not waiting until discharge to the current?
70+
* discharge down to a known current
71+
cwer peak_off0 _ocur row5; * Jump to peak_off when own-current is discharged
72+
wait row125;
73+
6574
peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
6675
wait row124; * Wait for one of the previously defined conditions
6776

@@ -91,7 +100,7 @@ hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hol
91100

92101
* ### End of injection phase ###
93102
eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off
94-
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
103+
stf high b1; * set flag1 to high to release the DC-DC converter idle mode
95104
jmpf jr2; * Jump back to idle phase
96105

97106
* ### End of Channel 1 - uCore0 code ###
@@ -139,26 +148,31 @@ boost1: load Iboost dac_sssc _ofs; * Load the boost phase curre
139148
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
140149
cwer boost1_err tc2 row5; * Jump to boost1_err in case boost phase takes too long
141150

142-
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
151+
stf low b1; * set flag0 low to force the DC-DC converter in idle mode
143152
stos off on on; * Turn VBAT off, BOOST on, LS on
144153
wait row1245; * Wait for one of the previously defined conditions
145154

146155
* ### Boost phase - minimum time reached ###
147156
boost1_mintime: wait row135; * Minimum time for boost phase has been reached, now wait for !start, overcurrent or timeout
148157

149158
boost1_err: stos off off off; * Turn off all drivers
150-
stf low b11; * Set ch1 error flag (OA_1) to signal MCU
151-
stf high b0; * set flag0 high to release the DC-DC converter idle mode
159+
stf low b11; * Set ch1 error flag (OA_2) to signal MCU
160+
stf high b1; * set flag0 high to release the DC-DC converter idle mode
152161
wait row1; * Wait for start signal to go low for the next injection attempt
153162

154-
155163
* ### Peak phase continue on Vbat ###
156-
peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
164+
peak1: store cnt2 Tboost_inj34 _ofs;
165+
stos keep off keep;
166+
ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
157167
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
158168
cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
159169
cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count
160170
cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold
161-
stf high b0; * set flag0 high to release the DC-DC converter idle mode
171+
stf high b1; * set flag0 high to release the DC-DC converter idle mode
172+
173+
* discharge down to a known current
174+
cwer peak_off1 _ocur row5; * Jump to peak_off when own-current is discharged
175+
wait row125;
162176

163177
peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
164178
wait row124; * Wait for one of the previously defined conditions
@@ -189,7 +203,7 @@ hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hol
189203

190204
* ### End of injection phase ###
191205
eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off
192-
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
206+
stf high b1; * set flag0 to high to release the DC-DC converter idle mode
193207
jmpf jr2; * Jump back to idle phase
194208

195209
* ### End of Channel 1 - uCore1 code ###

‎pt2001/project/rusefi/MicrocodeCh1/dram1.def‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,5 @@
88
#define Thold_tot 7;
99
#define Tboost_max 8;
1010
#define Tboost_min 9;
11+
#define Tboost_inj12 32;
12+
#define Tboost_inj34 33;

‎pt2001/project/rusefi/MicrocodeCh2/ch2.psc‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,27 +6,24 @@ init0: stgn gain5.8 ossc; * Set the gain of the op
66
load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L
77
load Isense4_high dac4h4n _ofs; * Load Isense4_high current threshold in DAC 4H
88
stdm null; * Set the boost voltage DAC access mode
9-
cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition
9+
cwer dcdc_idle _f1 row1; * Wait table entry for flag1 going low
1010
cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition
1111
cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition
1212

1313
* ### Asynchronous phase ###
1414
dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
15-
stf high b1;
1615
stdcctl async; * Enable asynchronous mode
1716
wait row13; * Wait for one of the previously defined conditions
1817

1918
* ### Synchronous phase ###
2019
dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
21-
stf low b1;
2220
stdcctl sync; * Enable synchronous mode
2321
wait row12; * Wait for one of the previously defined conditions
2422

2523
* ### Idle phase ###
2624
dcdc_idle: stdcctl sync; * Enable synchronous mode
27-
stf low b1;
28-
stf high b1;
29-
jocr dcdc_idle _f0; * jump to previous line while flag 0 is low
25+
stos keep off keep;
26+
jocr dcdc_idle _f1; * jump to previous line while flag 0 is low
3027
jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high
3128

3229
* ### End of Channel 2 - uCore0 code ###

‎pt2001/project/rusefi/Registers/ch1_config_reg.bin‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55
0000001100000011
66
0000000000000000
77
0000000000000000
8-
0000000001110010
9-
1001000111100111
10-
0101011011010110
8+
0000000001111010
9+
0100000110110100
10+
1001000000011000
1111
0000000000000000
12-
0000000000111001
12+
0000000000111101
1313
0000000000000000
1414
0000000000000000
1515
0000000000000000

‎pt2001/project/rusefi/Registers/ch2_config_reg.bin‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55
0000110000000000
66
0000000000000000
77
0000000000000000
8-
0000000000101011
9-
0010000110001100
10-
1101110010110110
8+
0000000000101000
9+
0010111011111100
10+
0110110101111000
1111
0000000000000000
12-
0000000000010100
12+
0000000000010001
1313
0000000000000000
1414
0000000000000000
1515
0000000000000000

‎pt2001/project/rusefi/Registers/dram1.bin‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
0000000011000000
2-
0000000010010010
3-
0000000001001001
1+
0000000010001101
2+
0000000001101101
3+
0000000000111010
44
0000000000111100
55
0001000001101000
66
0000000000111100

‎pt2001/project/rusefi/Registers/main_config_reg.bin‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
0000000000000011
2-
0001001111111110
2+
0001001111111100
33
0000000000000000
44
0001111000000000
55
0000000000000000

‎pt2001/project/rusefi/project.xml‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
<MicroCodeFile channel="2" type="hex" date="133028335145068598">bin\ch2.hex</MicroCodeFile>
2222
<DPramFile channel="1">Registers\dram1.hex</DPramFile>
2323
<DPramFile channel="2">Registers\dram2.hex</DPramFile>
24-
<LabelFile>labels.xml</LabelFile>
2524
<ActuatorFile>Actuator\inj1.xml</ActuatorFile>
2625
<ActuatorFile>Actuator\inj2.xml</ActuatorFile>
2726
<ActuatorFile>Actuator\inj3.xml</ActuatorFile>

‎pt2001/project/rusefi/sample_code/PT2001_LoadData.c‎

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*******************************************************************************
22
* Example Code
33
*
4-
* Copyright(C) 2023 NXP Semiconductors
4+
* Copyright(C) 2025 NXP Semiconductors
55
* NXP Semiconductors Confidential and Proprietary
66
*
77
* Software that is described herein is for illustrative purposes only
@@ -48,36 +48,37 @@
4848
#include "PT2001_LoadData.h"
4949

5050
// Data to be loaded into the Code RAM 1 memory space
51-
unsigned short const PT2001_code_RAM1[114] =
51+
unsigned short const PT2001_code_RAM1[122] =
5252
{
53-
0x7612, 0x6C57, 0x917F, 0xA514, 0x8DD6, 0xC288, 0x4F9B, 0x1EC9, 0x5C0D, 0xF99D,
53+
0x7612, 0x6C67, 0x917F, 0xA514, 0x8DD6, 0xC288, 0x4F9B, 0x1EC9, 0x5C0D, 0xF99D,
5454
0x4129, 0x2EEE, 0x97B0, 0x3534, 0x93BA, 0x5D25, 0xEE21, 0x2AAD, 0xE457, 0x2DB8,
55-
0xBED3, 0xBEB9, 0x2F08, 0xDA3C, 0x0499, 0x8DDE, 0xB519, 0x8E21, 0xAE4D, 0xF3E1,
56-
0x6E41, 0x9F0E, 0x2476, 0xBA8B, 0x4422, 0x0133, 0x6DAC, 0xA368, 0xE91F, 0x5E97,
57-
0x7820, 0x4662, 0xFEE0, 0x6F02, 0x8A92, 0x9A83, 0xE194, 0x6FD0, 0x1895, 0x80AB,
58-
0x4F93, 0xE1DA, 0x51BF, 0x70D8, 0xF25E, 0x7021, 0x2270, 0xF748, 0x51C5, 0xA4F1,
59-
0x329C, 0x5ADC, 0xD84C, 0xF054, 0x6E39, 0x2389, 0xCD76, 0x52F5, 0xF072, 0x8D02,
60-
0x4045, 0xDFEA, 0x1D65, 0xAD07, 0x33F3, 0x6650, 0x8854, 0x210D, 0x3A3C, 0xD20B,
61-
0x25B3, 0x8090, 0x27DE, 0xDF3E, 0xE928, 0x7D95, 0x83CC, 0xA366, 0x7879, 0x8A2C,
62-
0xE2E2, 0x1E41, 0x6530, 0x24F8, 0xB726, 0xF030, 0xCEA7, 0xF3FF, 0x4080, 0xF1DD,
63-
0xB433, 0xBFCB, 0x95C2, 0xDEDE, 0x2E14, 0xF672, 0x0567, 0x102E, 0xE0BC, 0xBD5F,
64-
0x21BF, 0x4D2B, 0x2ABD, 0x01B5
55+
0xBED3, 0xBEB8, 0x2F08, 0xDA3C, 0x0499, 0x8DDE, 0xB519, 0x8E20, 0xAE4D, 0x2E64,
56+
0xDBC7, 0x1D6A, 0x6315, 0xA415, 0xBA73, 0xF9AB, 0x6C56, 0x1A14, 0xE85A, 0x5FF6,
57+
0x3DAE, 0x0274, 0x0E54, 0x6F0C, 0xAA10, 0x2C14, 0xF516, 0x9E78, 0x8E6C, 0x360F,
58+
0xAAF8, 0x753D, 0xA317, 0x71B9, 0xF300, 0x1497, 0x2F8B, 0xF777, 0xE42C, 0x00F4,
59+
0x1B15, 0x6760, 0x5095, 0x6D56, 0x47B8, 0xA3D2, 0xEB76, 0xD610, 0xE6D4, 0x8D36,
60+
0x4041, 0xD7CB, 0xE618, 0xFF52, 0x4CFB, 0x2A72, 0x0C62, 0x3092, 0x5ED5, 0x2AB1,
61+
0x40E0, 0x7EA4, 0x276A, 0xDF8F, 0xE8C3, 0x7D81, 0xE79D, 0x164F, 0x9EE8, 0x798C,
62+
0xA799, 0x1EF5, 0x0152, 0x9031, 0x1105, 0x0EC7, 0x375E, 0xB78B, 0xBDEA, 0x002C,
63+
0xB55C, 0xDAC7, 0x6743, 0x3AE8, 0xDFB2, 0x4009, 0x0554, 0xE1C7, 0x85F3, 0xD90E,
64+
0x967A, 0xA91E, 0xDAEC, 0xFEE6, 0xCF46, 0x2C9A, 0x9695, 0xD631, 0x6520, 0x2DC3,
65+
0x53BE, 0xF116
6566
};
6667

6768
// Data to be loaded into the Code RAM 2 memory space
68-
unsigned short const PT2001_code_RAM2[43] =
69+
unsigned short const PT2001_code_RAM2[40] =
6970
{
70-
0x761B, 0x6F45, 0x838D, 0x80B4, 0x53F2, 0x0EBC, 0x8F2D, 0xA78E, 0xE8AB, 0xE3DB,
71-
0xF477, 0x800F, 0x2336, 0x2F77, 0x267B, 0xBC19, 0x007E, 0x4E55, 0x28AA, 0x52E4,
72-
0x40CF, 0x0AFD, 0x8B32, 0xFF03, 0x3D8E, 0x802E, 0x1340, 0x95D0, 0x1E86, 0x6591,
73-
0xDBEB, 0x786D, 0xB2DF, 0xF4BF, 0xBEB2, 0xF1F4, 0x9E53, 0xE743, 0xE842, 0x3DD7,
74-
0x3DA2, 0x4663, 0x03AF
71+
0x761B, 0x6F45, 0x838D, 0x80B4, 0x57F3, 0x0EBC, 0x8D2D, 0xA78E, 0xE919, 0xE39D,
72+
0x4090, 0x34AF, 0x22D4, 0x2F77, 0x273C, 0x8965, 0x1B88, 0x4F99, 0xA82F, 0xEDA4,
73+
0x65D6, 0x865B, 0x22F7, 0x7D94, 0x1E8D, 0x3C41, 0x4787, 0x8EB9, 0xAE4F, 0xF3ED,
74+
0x6949, 0x830E, 0x2676, 0xB481, 0x44BA, 0x005E, 0x0EE0, 0xE62C, 0xE91D, 0x523D
75+
7576
};
7677

7778
// Data to be loaded into the Data RAM memory space
7879
unsigned short const PT2001_data_RAM[128] =
7980
{
80-
0x00C0, 0x0092, 0x0049, 0x003C, 0x1068, 0x003C, 0x0168, 0xEA60, 0x0960, 0x0258,
81+
0x008D, 0x006D, 0x003A, 0x003C, 0x1068, 0x003C, 0x0168, 0xEA60, 0x0960, 0x0258,
8182
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
8283
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
8384
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
@@ -95,16 +96,16 @@ unsigned short const PT2001_data_RAM[128] =
9596
// Data to be loaded into the Main register memory space
9697
unsigned short const PT2001_main_config[29] =
9798
{
98-
0x0003, 0x13FE, 0x0000, 0x1E00, 0x0000, 0x0000, 0x0001, 0x0000, 0x001F, 0x0000,
99+
0x0003, 0x13FC, 0x0000, 0x1E00, 0x0000, 0x0000, 0x0001, 0x0000, 0x001F, 0x0000,
99100
0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
100101
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
101102
};
102103

103104
// Data to be loaded into the CH1 register memory space
104105
unsigned short const PT2001_ch1_config[19] =
105106
{
106-
0x0008, 0x0000, 0x0000, 0x0000, 0x0303, 0x0000, 0x0000, 0x0072, 0x91E7, 0x56D6,
107-
0x0000, 0x0039, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
107+
0x0008, 0x0000, 0x0000, 0x0000, 0x0303, 0x0000, 0x0000, 0x007A, 0x41B4, 0x9018,
108+
0x0000, 0x003D, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
108109
};
109110

110111
// Data to be loaded into the CH2 register memory space

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