Merge pull request #3248 from verilog-to-routing/hotfix_sg

[Scatter-Gather] [Hotfix] Fix issue parsing the wireconn tag

Author: vaughnbetz

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -177,26 +177,26 @@ static t_wireconn_inf parse_wireconn_inline(pugi::xml_node node,
     parse_num_conns(char_prop, wc);
 
     // get from type
-    char_prop = get_attribute(node, "from_type", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "from_type", loc_data, from_to_required).as_string();
+    if (*char_prop) { // if from_to_required is ReqOpt::REQUIRED, char_prop is definitely not null. Otherwise, it's optional and should be null checked.
         parse_comma_separated_wire_types(char_prop, wc.from_switchpoint_set);
     }
 
     // get to type
-    char_prop = get_attribute(node, "to_type", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "to_type", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_types(char_prop, wc.to_switchpoint_set);
     }
 
     // get the source wire point
-    char_prop = get_attribute(node, "from_switchpoint", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "from_switchpoint", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_points(char_prop, wc.from_switchpoint_set);
     }
 
     // get the destination wire point
-    char_prop = get_attribute(node, "to_switchpoint", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "to_switchpoint", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_points(char_prop, wc.to_switchpoint_set);
     }
 

libs/libarchfpga/src/read_xml_arch_file_sg.cpp

@@ -125,10 +125,10 @@ void process_sg_tag(pugi::xml_node sg_list_tag,
         // Parse scatter pattern
         pugi::xml_node scatter_node = pugiutil::get_single_child(sg_tag, "scatter", loc_data);
         t_wireconn_inf scatter_wireconn = parse_wireconn(pugiutil::get_single_child(scatter_node, "wireconn", loc_data), loc_data, switches, true);
-        if (!gather_wireconn.from_switchpoint_set.empty()) {
+        if (!scatter_wireconn.from_switchpoint_set.empty()) {
             archfpga_throw(loc_data.filename_c_str(), loc_data.line(sg_tag), "Scatter wireconn specification should not set any 'from' switchpoints");
         }
-        if (gather_wireconn.to_switchpoint_set.empty()) {
+        if (scatter_wireconn.to_switchpoint_set.empty()) {
             archfpga_throw(loc_data.filename_c_str(), loc_data.line(sg_tag), "Scatter wireconn specification does not include any switchpoints.");
         }
         sg.scatter_pattern = scatter_wireconn;

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scatter_gather/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_frac_N10_frac_chain_mem32K_40nm.xml	ch_intrinsics.v	common	1.74	vpr	70.43 MiB		-1	-1	0.14	28940	3	0.06	-1	-1	37152	-1	-1	68	99	1	0	success	v9.0.0-1551-g5240fc93b-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 15.1.1 on Linux-6.14.9-300.fc42.x86_64 x86_64	2025-07-25T11:50:33	betzgrp-pcamir.eecg	/home/amirpoolad/Dev/vtr-verilog-to-routing	72124	99	130	344	474	1	227	298	12	12	144	clb	auto	31.5 MiB	0.13	1668.56	665	69948	18708	40810	10430	70.4 MiB	0.11	0.00	2.40104	1.86413	-122.75	-1.86413	1.86413	0.09	0.000472085	0.000440172	0.0346065	0.0322238	-1	-1	-1	-1	44	1308	13	5.66058e+06	4.21279e+06	360780.	2505.42	0.63	0.188011	0.172087	13374	71755	-1	1113	9	385	601	24354	7746	1.97022	1.97022	-144.54	-1.97022	0	0	470760.	3269.17	0.01	0.03	0.04	-1	-1	0.01	0.0150696	0.0142759	
+k6_frac_N10_frac_chain_mem32K_40nm_sg.xml	ch_intrinsics.v	common	2.49	vpr	71.47 MiB		-1	-1	0.16	30900	3	0.07	-1	-1	37084	-1	-1	68	99	1	0	success	v8.0.0-13673-g028e6044f-dirty	release VTR_ASSERT_LEVEL=2	GNU 15.1.1 on Linux-6.14.9-300.fc42.x86_64 x86_64	2025-08-25T13:13:32	betzgrp-pcamir.eecg	/home/amirpoolad/Dev/vtr-verilog-to-routing	73184	99	130	344	474	1	227	298	12	12	144	clb	auto	32.5 MiB	0.15	1668.56	665	69948	18708	40810	10430	71.5 MiB	0.19	0.00	2.40104	1.86413	-122.75	-1.86413	1.86413	0.12	0.000537934	0.000489526	0.0618774	0.0565413	-1	-1	-1	-1	44	1308	13	5.66058e+06	4.21279e+06	360780.	2505.42	0.92	0.280685	0.252587	13374	71755	-1	1113	9	385	601	24354	7746	1.97022	1.97022	-144.54	-1.97022	0	0	470760.	3269.17	0.01	0.03	0.05	-1	-1	0.01	0.0184111	0.0172572