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amin1377amin1377
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Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into placement_search_range
2 parents 8955b02 + 98c8a0f commit a15f70a

30 files changed

+683
-388
lines changed

‎libs/EXTERNAL/libcatch2‎

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 46 additions & 115 deletions
Large diffs are not rendered by default.

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 25 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -335,19 +335,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
335335
fprintf(Echo, "*************************************************\n");
336336
fprintf(Echo, "Clock:\n");
337337
if (arch->clocks) {
338-
for (int i = 0; i < arch->clocks->num_global_clocks; i++) {
339-
if (arch->clocks->clock_inf[i].autosize_buffer) {
340-
fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1,
341-
arch->clocks->clock_inf->C_wire);
338+
for (size_t i = 0; i < arch->clocks->size(); i++) {
339+
if ((*arch->clocks)[i].autosize_buffer) {
340+
fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1,
341+
(*arch->clocks)[i].C_wire);
342342
} else {
343-
fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1,
344-
arch->clocks->clock_inf[i].buffer_size,
345-
arch->clocks->clock_inf[i].C_wire);
343+
fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1,
344+
(*arch->clocks)[i].buffer_size,
345+
(*arch->clocks)[i].C_wire);
346346
}
347347
fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e",
348-
arch->clocks->clock_inf[i].prob,
349-
arch->clocks->clock_inf[i].dens,
350-
arch->clocks->clock_inf[i].period);
348+
(*arch->clocks)[i].prob,
349+
(*arch->clocks)[i].dens,
350+
(*arch->clocks)[i].period);
351351
}
352352
}
353353

@@ -381,51 +381,45 @@ static void print_model(FILE* echo, const t_model& model) {
381381
}
382382

383383
static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) {
384-
char* tabs;
384+
std::string tabs = std::string(level, '\t');
385385

386-
tabs = (char*)vtr::malloc((level + 1) * sizeof(char));
387-
for (int i = 0; i < level; i++) {
388-
tabs[i] = '\t';
389-
}
390-
tabs[level] = '\0';
391-
392-
fprintf(Echo, "%spb_type name: %s\n", tabs, pb_type->name);
393-
fprintf(Echo, "%s\tblif_model: %s\n", tabs, pb_type->blif_model);
394-
fprintf(Echo, "%s\tclass_type: %d\n", tabs, pb_type->class_type);
395-
fprintf(Echo, "%s\tnum_modes: %d\n", tabs, pb_type->num_modes);
396-
fprintf(Echo, "%s\tnum_ports: %d\n", tabs, pb_type->num_ports);
386+
fprintf(Echo, "%spb_type name: %s\n", tabs.c_str(), pb_type->name);
387+
fprintf(Echo, "%s\tblif_model: %s\n", tabs.c_str(), pb_type->blif_model);
388+
fprintf(Echo, "%s\tclass_type: %d\n", tabs.c_str(), pb_type->class_type);
389+
fprintf(Echo, "%s\tnum_modes: %d\n", tabs.c_str(), pb_type->num_modes);
390+
fprintf(Echo, "%s\tnum_ports: %d\n", tabs.c_str(), pb_type->num_ports);
397391
for (int i = 0; i < pb_type->num_ports; i++) {
398-
fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs,
392+
fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs.c_str(),
399393
pb_type->ports[i].name, pb_type->ports[i].type,
400394
pb_type->ports[i].num_pins);
401395
}
402396

403397
if (pb_type->num_modes > 0) { /*one or more modes*/
404398
for (int i = 0; i < pb_type->num_modes; i++) {
405-
fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name);
399+
fprintf(Echo, "%s\tmode %s:\n", tabs.c_str(), pb_type->modes[i].name);
406400
for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
407401
PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j],
408402
level + 2, models);
409403
}
410404
for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) {
411-
fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs,
405+
fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(),
412406
pb_type->modes[i].interconnect[j].type,
413407
pb_type->modes[i].interconnect[j].input_string,
414408
pb_type->modes[i].interconnect[j].output_string);
415409
for (int k = 0;
416410
k < pb_type->modes[i].interconnect[j].num_annotations;
417411
k++) {
418-
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs,
412+
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(),
419413
pb_type->modes[i].interconnect[j].annotations[k].input_pins,
420414
pb_type->modes[i].interconnect[j].annotations[k].output_pins,
421415
pb_type->modes[i].interconnect[j].annotations[k].format,
422-
pb_type->modes[i].interconnect[j].annotations[k].value[0]);
416+
pb_type->modes[i].interconnect[j].annotations[k].annotation_entries[0].second.c_str());
423417
}
424418
//Print power info for interconnects
425419
if (pb_type->modes[i].interconnect[j].interconnect_power) {
426420
if (pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic
427421
|| pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage) {
428-
fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs,
422+
fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs.c_str(),
429423
pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic,
430424
pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage);
431425
}
@@ -442,20 +436,19 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
442436
&& pb_type_model_name != LogicalModels::MODEL_INPUT
443437
&& pb_type_model_name != LogicalModels::MODEL_OUTPUT) {
444438
for (int k = 0; k < pb_type->num_annotations; k++) {
445-
fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs,
439+
fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(),
446440
pb_type->annotations[k].clock,
447441
pb_type->annotations[k].input_pins,
448442
pb_type->annotations[k].output_pins,
449443
pb_type->annotations[k].format,
450-
pb_type->annotations[k].value[0]);
444+
pb_type->annotations[k].annotation_entries[0].second.c_str());
451445
}
452446
}
453447
}
454448

455449
if (pb_type->pb_type_power) {
456-
PrintPb_types_recPower(Echo, pb_type, tabs);
450+
PrintPb_types_recPower(Echo, pb_type, tabs.c_str());
457451
}
458-
free(tabs);
459452
}
460453

461454
//Added May 2013 Daniel Chen, help dump arch info after loading from XML

‎libs/libarchfpga/src/logic_types.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ void LogicalModels::free_model_data(t_model& model) {
148148
while (vptr) {
149149
vtr::t_linked_vptr* vptr_prev = vptr;
150150
vptr = vptr->next;
151-
vtr::free(vptr_prev);
151+
delete vptr_prev;
152152
}
153153

154154
if (model.instances)

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 101 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,6 @@
4343
#include "clock_types.h"
4444

4545
//Forward declarations
46-
struct t_clock_arch;
4746
struct t_clock_network;
4847
struct t_power_arch;
4948
struct t_interconnect_pins;
@@ -407,12 +406,6 @@ struct t_grid_def {
407406

408407
/************************* POWER ***********************************/
409408

410-
/* Global clock architecture */
411-
struct t_clock_arch {
412-
int num_global_clocks;
413-
t_clock_network* clock_inf; /* Details about each clock */
414-
};
415-
416409
/* Architecture information for a single clock */
417410
struct t_clock_network {
418411
bool autosize_buffer; /* autosize clock buffers */
@@ -422,6 +415,15 @@ struct t_clock_network {
422415
float prob; /* Static probability of net assigned to this clock */
423416
float dens; /* Switching density of net assigned to this clock */
424417
float period; /* Period of clock */
418+
419+
t_clock_network() {
420+
autosize_buffer = false;
421+
buffer_size = 0.0f;
422+
C_wire = 0.0f;
423+
prob = 0.0f;
424+
dens = 0.0f;
425+
period = 0.0f;
426+
}
425427
};
426428

427429
/* Power-related architecture information */
@@ -434,12 +436,26 @@ struct t_power_arch {
434436
float mux_transistor_size;
435437
float FF_size;
436438
float LUT_transistor_size;
439+
440+
t_power_arch() {
441+
C_wire_local = 0.0f;
442+
logical_effort_factor = 0.0f;
443+
local_interc_factor = 0.0f;
444+
transistors_per_SRAM_bit = 0.0f;
445+
mux_transistor_size = 0.0f;
446+
FF_size = 0.0f;
447+
LUT_transistor_size = 0.0f;
448+
}
437449
};
438450

439451
/* Power usage for an entity */
440452
struct t_power_usage {
441453
float dynamic;
442454
float leakage;
455+
t_power_usage() {
456+
dynamic = 0.0f;
457+
leakage = 0.0f;
458+
}
443459
};
444460

445461
/*************************************************************************************************/
@@ -534,6 +550,18 @@ struct t_port_power {
534550
t_port* scaled_by_port;
535551
int scaled_by_port_pin_idx;
536552
bool reverse_scaled; /* Scale by (1-prob) */
553+
554+
t_port_power() {
555+
wire_type = (e_power_wire_type)0;
556+
wire = {0.0f}; // Default to C = 0.0f
557+
buffer_type = (e_power_buffer_type)0;
558+
buffer_size = 0.0f;
559+
pin_toggle_initialized = false;
560+
energy_per_toggle = 0.0f;
561+
scaled_by_port = nullptr;
562+
scaled_by_port_pin_idx = 0;
563+
reverse_scaled = false;
564+
}
537565
};
538566

539567
/**
@@ -1153,24 +1181,39 @@ struct t_mode {
11531181
*/
11541182
struct t_interconnect {
11551183
enum e_interconnect type;
1156-
char* name = nullptr;
1184+
char* name;
11571185

1158-
char* input_string = nullptr;
1159-
char* output_string = nullptr;
1186+
char* input_string;
1187+
char* output_string;
11601188

1161-
t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */
1162-
int num_annotations = 0;
1163-
bool infer_annotations = false;
1189+
t_pin_to_pin_annotation* annotations; /* [0..num_annotations-1] */
1190+
int num_annotations;
1191+
bool infer_annotations;
11641192

1165-
int line_num = 0; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
1193+
int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
11661194

1167-
int parent_mode_index = 0;
1195+
int parent_mode_index;
11681196

11691197
/* Power related members */
1170-
t_mode* parent_mode = nullptr;
1198+
t_mode* parent_mode;
11711199

1172-
t_interconnect_power* interconnect_power = nullptr;
1200+
t_interconnect_power* interconnect_power;
11731201
t_metadata_dict meta;
1202+
1203+
t_interconnect() {
1204+
type = (e_interconnect)0;
1205+
name = nullptr;
1206+
input_string = nullptr;
1207+
output_string = nullptr;
1208+
annotations = nullptr;
1209+
num_annotations = 0;
1210+
infer_annotations = false;
1211+
line_num = 0;
1212+
parent_mode_index = 0;
1213+
parent_mode = nullptr;
1214+
interconnect_power = nullptr;
1215+
meta = t_metadata_dict();
1216+
}
11741217
};
11751218

11761219
/** Describes I/O and clock ports
@@ -1208,6 +1251,22 @@ struct t_port {
12081251
int absolute_first_pin_index;
12091252

12101253
t_port_power* port_power;
1254+
1255+
t_port() {
1256+
name = nullptr;
1257+
model_port = nullptr;
1258+
type = (PORTS)0;
1259+
is_clock = false;
1260+
is_non_clock_global = false;
1261+
num_pins = 0;
1262+
equivalent = (PortEquivalence)0;
1263+
parent_pb_type = nullptr;
1264+
port_class = nullptr;
1265+
index = 0;
1266+
port_index_by_type = 0;
1267+
absolute_first_pin_index = 0;
1268+
port_power = nullptr;
1269+
}
12111270
};
12121271

12131272
struct t_pb_type_power {
@@ -1234,6 +1293,15 @@ struct t_interconnect_power {
12341293
int num_output_ports;
12351294
int num_pins_per_port;
12361295
float transistor_cnt;
1296+
1297+
t_interconnect_power() {
1298+
power_usage = t_power_usage();
1299+
port_info_initialized = false;
1300+
num_input_ports = 0;
1301+
num_output_ports = 0;
1302+
num_pins_per_port = 0;
1303+
transistor_cnt = 0.0f;
1304+
}
12371305
};
12381306

12391307
struct t_interconnect_pins {
@@ -1252,18 +1320,16 @@ struct t_mode_power {
12521320
* This is later for additional information.
12531321
*
12541322
* Data Members:
1255-
* value: value/property pair
1256-
* prop: value/property pair
1323+
* annotation_entries: pairs of annotation subtypes and the annotation values
12571324
* type: type of annotation
12581325
* format: formatting of data
12591326
* input_pins: input pins as string affected by annotation
12601327
* output_pins: output pins as string affected by annotation
12611328
* clock_pin: clock as string affected by annotation
12621329
*/
12631330
struct t_pin_to_pin_annotation {
1264-
char** value; /* [0..num_value_prop_pairs - 1] */
1265-
int* prop; /* [0..num_value_prop_pairs - 1] */
1266-
int num_value_prop_pairs;
1331+
1332+
std::vector<std::pair<int, std::string>> annotation_entries;
12671333

12681334
enum e_pin_to_pin_annotation_type type;
12691335
enum e_pin_to_pin_annotation_format format;
@@ -1273,6 +1339,17 @@ struct t_pin_to_pin_annotation {
12731339
char* clock;
12741340

12751341
int line_num; /* used to report what line number this annotation is found in architecture file */
1342+
1343+
t_pin_to_pin_annotation() {
1344+
annotation_entries = std::vector<std::pair<int, std::string>>();
1345+
input_pins = nullptr;
1346+
output_pins = nullptr;
1347+
clock = nullptr;
1348+
1349+
line_num = 0;
1350+
type = (e_pin_to_pin_annotation_type)0;
1351+
format = (e_pin_to_pin_annotation_format)0;
1352+
}
12761353
};
12771354

12781355
/*************************************************************************************************
@@ -2210,7 +2287,8 @@ struct t_arch {
22102287
LogicalModels models;
22112288

22122289
t_power_arch* power = nullptr;
2213-
t_clock_arch* clocks = nullptr;
2290+
2291+
std::shared_ptr<std::vector<t_clock_network>> clocks;
22142292

22152293
//determine which layers in multi-die FPGAs require to build global routing resources
22162294
std::vector<bool> layer_global_routing;

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