The issue was observed for VREG_W = 512. The sld unit sends out the instr_done signal after receiving the last cycle. However, since the sld unit uses the alt_counter in the pipeline, the pipeline waits for the alt_last_cycle. Therefore the instr_done signal could be send out before the state_done signal was asserted in the pipeline That is why it is possible for the instruction to still be valid in the pipeline but not in the instr_state.
The issue was observed for VREG_W = 512. The sld unit sends out the instr_done signal after receiving the last cycle. However, since the sld unit uses the alt_counter in the pipeline, the pipeline waits for the alt_last_cycle. Therefore the instr_done signal could be send out before the state_done signal was asserted in the pipeline That is why it is possible for the instruction to still be valid in the pipeline but not in the instr_state.