I was doing some RVV fixed-point rounding verification (testing vxrm behavior for INT8 AI kernels) and ran into a couple of integration gotchas in both Vicuna and Vicuna2.
First, the external CSR input ports in vproc_core.sv (csr_vxrm_i, csr_vstart_i, plus their _set_i signals) are declared on the module interface but are totally unconnected inside. The internal XIF decode path works fine, but if a host core tries to drive the rounding mode via these external ports, the writes just get dropped and Vicuna stays stuck on rnu.
Second, in vproc_top.sv for the CV32E40X config, the write-enable is hardwired to zero (assign vect_csr_we = '{default:'0};). This cascades down and zeroes out csr_vxrm_wren, which completely breaks CSR updates for this host config.
The main issue here is that silently dropping vxrm requests (like rne for banker's rounding) breaks instructions like vssrl.vi and vnclip, which messes up the expected math for quant-aware training.
I've got a minimal Spike reproducer showing the element-by-element divergence if it helps. I'm guessing the external ports might just be legacy holdovers from before XIF was fully wired up?
Figured I'd flag them though since it causes silent rounding failures for non-XIF integrations.
Let me know if I'm just misinterpreting the routing!
I was doing some RVV fixed-point rounding verification (testing vxrm behavior for INT8 AI kernels) and ran into a couple of integration gotchas in both Vicuna and Vicuna2.
First, the external CSR input ports in vproc_core.sv (
csr_vxrm_i,csr_vstart_i, plus their_set_isignals) are declared on the module interface but are totally unconnected inside. The internal XIF decode path works fine, but if a host core tries to drive the rounding mode via these external ports, the writes just get dropped and Vicuna stays stuck on rnu.Second, in
vproc_top.sv for theCV32E40Xconfig, the write-enable is hardwired to zero (assign vect_csr_we = '{default:'0};). This cascades down and zeroes out csr_vxrm_wren, which completely breaks CSR updates for this host config.The main issue here is that silently dropping vxrm requests (like rne for banker's rounding) breaks instructions like vssrl.vi and vnclip, which messes up the expected math for quant-aware training.
I've got a minimal Spike reproducer showing the element-by-element divergence if it helps. I'm guessing the external ports might just be legacy holdovers from before XIF was fully wired up?
Figured I'd flag them though since it causes silent rounding failures for non-XIF integrations.
Let me know if I'm just misinterpreting the routing!