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arch: arm: cortex_m: Allow VTOR to be relocated to TCM
Relocate VTOR from SRAM to ITCM/DTCM to minimize interrupt latency. TCM offers single-cycle access compared to multi-cycle SRAM reads. This improves exception handling speed for real-time workloads. Signed-off-by: Peter van der Perk <[email protected]>
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arch/arm/Kconfig

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@@ -190,4 +190,40 @@ config HAS_SWO
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help
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When enabled, indicates that SoC has an SWO output
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DT_CHOSEN_Z_DTCM := zephyr,dtcm
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DT_CHOSEN_Z_ITCM := zephyr,itcm
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choice
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prompt "Vector table memory location"
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depends on SRAM_VECTOR_TABLE
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default VECTOR_TABLE_SRAM
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config VECTOR_TABLE_SRAM
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bool "SRAM"
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help
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Place the vector table in SRAM.
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config VECTOR_TABLE_DTCM
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bool "DTCM"
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depends on $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
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help
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Place the interrupt vector table in Data Tightly Coupled Memory (DTCM).
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While the vector table is instruction-fetched during exception entry, a DTCM
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option is provided for systems where ITCM is unavailable. DTCM still offers
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low-latency, deterministic access compared to normal RAM, but is not the
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optimal location for instruction fetch performance.
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config VECTOR_TABLE_ITCM
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bool "ITCM"
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depends on $(dt_chosen_enabled,$(DT_CHOSEN_Z_ITCM))
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help
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Place the interrupt vector table in Instruction Tightly Coupled Memory (ITCM).
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ITCM is accessed via the CPU instruction bus and provides single-cycle,
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deterministic instruction fetches. This typically yields the lowest possible
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interrupt latency and is the preferred location when available.
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endchoice
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endmenu

arch/arm/core/cortex_m/ram_vector_table.ld

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@@ -28,5 +28,11 @@ SECTION_PROLOGUE(.sram_vt,,)
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. += _vector_end - _vector_start;
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MPU_ALIGN(_sram_vector_size);
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_sram_vector_end = .;
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#if defined(CONFIG_VECTOR_TABLE_ITCM)
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} GROUP_DATA_LINK_IN(ITCM, ROMABLE_REGION)
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#elif defined(CONFIG_VECTOR_TABLE_DTCM)
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} GROUP_DATA_LINK_IN(DTCM, ROMABLE_REGION)
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#else
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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#endif
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_sram_vector_size = _sram_vector_end - _sram_vector_start;

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