A lightweight developer tool that helps chip design engineers make sense of long, messy EDA (Electronic Design Automation) logs from synthesis, timing, placement, routing, and verification runs.
- Automatic Error Extraction - Parses logs and identifies errors, warnings, and critical issues
- Smart Grouping - Clusters repeated messages and removes duplicate noise
- Root Cause Detection - Identifies likely first failures vs. cascading errors
- Stage Classification - Categorizes issues by flow stage (synthesis, placement, routing, etc.)
- AI-Powered Explanations - Plain-English explanations with actionable fix suggestions (optional)
- Clean Dashboard - Web interface with summary statistics and issue breakdown
Currently optimized for:
- OpenLane (Yosys, OpenROAD, Magic)
- Generic EDA logs with standard error formats
Can handle logs from:
- Synthesis (Yosys, ABC)
- Placement & Routing (OpenROAD)
- Static Timing Analysis (OpenSTA)
- DRC (Magic, other DRC tools)
- LVS verification
pip install -r requirements.txtpython run.pyOr directly:
uvicorn eda_log_analyzer.backend.api:app --host 0.0.0.0 --port 8000Navigate to: http://localhost:8000
- Drag & drop or click to browse
- Supports
.log,.txt,.rptfiles - Click "Analyze Log" to process
For enhanced plain-English explanations using Gemini or Claude AI:
export GEMINI_API_KEY=your_api_key_here
export ANTHROPIC_API_KEY=your_api_key_here
python run.pyWithout an API key, the tool will use rule-based explanations (still very useful!).
log_analyzer/
├── eda_log_analyzer/
│ ├── backend/
│ │ └── api.py # FastAPI backend
│ ├── frontend/
│ │ └── index.html # Web dashboard
│ └── utils/
│ ├── parser.py # Log parsing & grouping
│ └── explainer.py # AI & rule-based explanations
├── sample_eda_logs/ # Test dataset
├── requirements.txt
├── run.py # Entry point
└── README.md
Upload and analyze a log file
Request:
curl -X POST -F "file=@your_log.log" http://localhost:8000/analyzeResponse:
{
"summary": "❌ 47 errors found...",
"statistics": {
"total_issues": 125,
"error_count": 47,
"warning_count": 78
},
"issue_groups": [
{
"severity": "error",
"stage": "synthesis",
"count": 15,
"explanation": "...",
"recommendation": "..."
}
]
}Check service status
Get supported severities and stages
The sample_eda_logs/ directory contains real EDA logs for testing:
openlane.log- Complete OpenLane flow (successful)synthesis_error_example.log- ABC tool failuretiming_violations.log- Setup timing violationsdrc_violations.log- Design rule check failuresplacement_routing_errors.log- P&R congestion issues
Try uploading these to see the analyzer in action!
python -c "
from eda_log_analyzer.utils.parser import LogParser
from eda_log_analyzer.utils.explainer import IssueExplainer
parser = LogParser()
issues = parser.parse_file('sample_eda_logs/synthesis_error_example.log')
groups = parser.group_issues(issues)
explainer = IssueExplainer()
for group in groups:
explanation = explainer.explain_group(group)
print(f'{group.severity.value}: {explanation[\"explanation\"][:100]}...')
"from eda_log_analyzer.utils.parser import LogParser
parser = LogParser()
issues = parser.parse_file('your_log.log')
stats = parser.get_statistics(issues)
print(f"Total issues: {stats['total_issues']}")
print(f"Errors: {stats['error_count']}")
print(f"Warnings: {stats['warning_count']}")- Parse - Regex-based extraction of ERROR/WARNING/CRITICAL messages
- Classify - Stage detection (synthesis vs. routing) and severity ranking
- Group - Normalize messages to cluster similar issues (e.g., "net_123" → "net_X")
- Explain - AI or rule-based plain-English explanations
- Present - Clean web dashboard with actionable insights
python -m eda_log_analyzer.utils.parserEdit parser.py to add new regex patterns:
STAGE_PATTERNS = {
Stage.YOUR_STAGE: re.compile(r'\byour_tool_keyword\b', re.IGNORECASE),
}The current iteration of the EDA Log Analyzer uses zero-shot prompting with general-purpose LLMs (Gemini/Claude) and rule-based regex parsing. To elevate the tool to production-grade accuracy for complex chip design flows, the following phased upgrades are planned to drastically improve the quality of log analysis:
To immediately improve the accuracy of LLM recommendations and eliminate "EDA hallucination" without training new models:
- Retrieval-Augmented Generation (RAG): Integrate a local vector database (e.g., ChromaDB) loaded with specific foundry PDK manuals (e.g., Skywater 130nm standard cell libraries), EDA tool documentation (OpenROAD, Yosys), and company-specific design guidelines. Error logs will query this DB to pull exact cell definitions before prompting the AI safely.
- Cross-Stage Correlation Engine: Expand the parser to link failures across stages. If a routing congestion error is caused by a poor floorplan density target from an earlier stage, the system will correlate the logs and highlight the initial root cause rather than treating them as isolated issues.
- Structured Context Extraction: Upgrade
parser.pyto extract multi-line timing reports and floorplan constraints into structured JSON objects, rather than passing raw text blobs to the AI.
To move beyond general-purpose models parsing logs:
- EDA Fine-Tuned Models: Fine-tune open-source models (or use LoRA adapters) explicitly trained on massive datasets of Verilog/VHDL, Tcl synthesis scripts, and standard EDA error signatures. This creates a specialized "EDA-LLM" that intrinsically understands standard cell architecture, clock domain crossing, and constraint generation (e.g.,
set_false_path) without heavy prompting. - Statistical Anomaly Detection: Train lightweight machine-learning classifiers strictly on the statistical features of logs (e.g., the ratio of warnings to errors, slack time drift) to flag regressions compared to previous continuous integration runs before engaging a heavy LLM.
General software architecture upgrades:
- Multi-File & Multi-Corner Analysis: Support uploading an entire directory of logs across different PVT (Process, Voltage, Temperature) corners to perform comparative drift analysis.
- CI/CD Pipeline Integration: Package the tool as a GitHub Action or GitLab pipeline step to automatically annotate Pull Requests with AI-explained DRC/LVS failures.
- Commercial Toolchain Expansion: Formally expand the parser's regex signatures to support proprietary formats like Cadence (Innovus/Genus) and Synopsys (Design Compiler/IC Compiler II).
- Export & Reporting: One-click generation of PDF/Markdown physical design summary reports for design reviews or sign-off meetings.
This is an MVP built in one day. Contributions welcome!
MIT License - see LICENSE file
Built for Silimate interview - demonstrating practical EDA tooling skills.
Note: This tool is for analysis only. It does not modify your design files or logs.