fix: USB OTG FS PHY reset for reliable re-enumeration after st-flash#35
fix: USB OTG FS PHY reset for reliable re-enumeration after st-flash#35Amperstrand wants to merge 1 commit into
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| unsafe { | ||
| // GRSTCTL = CSRST (bit 0) | ||
| otg_global.add(0x010 / 4).write_volatile(1); | ||
| while otg_global.add(0x010 / 4).read_volatile() & 1 != 0 {} |
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This loop waits indefinitely for GRSTCTL.CSRST to clear, so if the OTG core never reports reset completion (for example when the AHB state is not idle after an unusual reset path), firmware boot will block forever before USB initialization. Because this code now runs on every boot, a single stuck condition turns into a hard startup hang with no recovery path; adding a timeout/fallback (and logging) would prevent bricking the boot sequence.
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… soft reset After a soft reset (SYSRESETREQ from st-flash), the USB OTG FS PHY can be left in an inconsistent state where it doesn't re-enumerate on the host. This cycles the RCC clock, asserts peripheral reset, performs a core soft reset (GRSTCTL.CSRST), and power-cycles the PHY via GCCFG.PWRDWN before the USB driver initializes. Mirrors the fix in ccid-firmware-rs commit 28e6fee (issue #15).
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Closing in favor of direct commit to main. The code here uses the pre-fix PAC method names ( |
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Summary
Fixes #34 — USB OTG FS doesn't re-enumerate after
st-flashsoft reset.Adds an explicit PHY reset sequence between
embassy_stm32::init()andDriver::new_fs():Why This Is Needed
After
st-flash(SYSRESETREQ without NRST), the USB PHY retains stale state. Neitherembassy-usb-synopsys-otgnorembassy-stm32's RCC init performs the full reset sequence needed to unwedge the PHY.Verification
Same fix hardware-verified on STM32F746-DISCO in ccid-firmware-rs (commit 28e6fee, issue #15). The STM32F469 uses an identical OTG FS peripheral at the same base address (0x5000_0000).
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