Add ROCm support #1576
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Add ROCm support #1576
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wsmoses
reviewed
Nov 5, 2025
wsmoses
reviewed
Nov 5, 2025
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EnzymeJAX Benchmarks
| Benchmark suite | Current: f46684e | Previous: b55ffd4 | Ratio |
|---|---|---|---|
scatter_sum / JaX / cpu / Primal |
0.0000043525060871616 s |
0.000004338932399696205 s |
1.00 |
scatter_sum / JaXPipe / cpu / Primal |
0.000004293832019902766 s |
0.000004298453299998073 s |
1.00 |
scatter_sum / JaX / tpu / Primal |
0.0001354218465974 s |
0.0001558048111997 s |
0.87 |
scatter_sum / JaXPipe / tpu / Primal |
0.0001336760675068 s |
0.0001522772955002 s |
0.88 |
This comment was automatically generated by workflow using github-action-benchmark.
vimarsh6739
reviewed
Nov 20, 2025
| } | ||
| }; | ||
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| struct GPUShuffleOpToROCDL : public ConvertOpToLLVMPattern<gpu::ShuffleOp> { |
vimarsh6739
reviewed
Nov 20, 2025
| } // namespace mlir | ||
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| // https://rocm.docs.amd.com/projects/HIP/en/docs-6.4.0/reference/hardware_features.html | ||
| struct GPULaneIdOpToROCDL : ConvertOpToLLVMPattern<gpu::LaneIdOp> { |
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vimarsh6739
requested changes
Nov 20, 2025
Comment on lines
+3959
to
+3993
| } else if (gpuTarget == "rocm") { | ||
| using namespace mlir::gpu::index_lowering; | ||
| PatternBenefit benefit(1); | ||
| PatternBenefit highBenefit(2); | ||
| patterns.add<gpu::index_lowering::OpLowering< | ||
| gpu::ThreadIdOp, ROCDL::ThreadIdXOp, ROCDL::ThreadIdYOp, | ||
| ROCDL::ThreadIdZOp>>(typeConverter, IndexKind::Block, IntrType::Id, | ||
| benefit); | ||
| patterns.add<gpu::index_lowering::OpLowering< | ||
| gpu::BlockDimOp, ROCDL::BlockDimXOp, ROCDL::BlockDimYOp, | ||
| ROCDL::BlockDimZOp>>(typeConverter, IndexKind::Block, IntrType::Dim, | ||
| benefit); | ||
| patterns.add<gpu::index_lowering::OpLowering< | ||
| gpu::BlockIdOp, ROCDL::BlockIdXOp, ROCDL::BlockIdYOp, | ||
| ROCDL::BlockIdZOp>>(typeConverter, IndexKind::Grid, IntrType::Id, | ||
| benefit); | ||
| patterns.add<gpu::index_lowering::OpLowering< | ||
| gpu::GridDimOp, ROCDL::GridDimXOp, ROCDL::GridDimYOp, | ||
| ROCDL::GridDimZOp>>(typeConverter, IndexKind::Grid, IntrType::Dim, | ||
| benefit); | ||
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| patterns.add<GPULaneIdOpToROCDL>(typeConverter, benefit); | ||
| patterns.add<GPUShuffleOpToROCDL>(typeConverter, benefit); | ||
| patterns.add<GPUBarrierToROCDL>(typeConverter, benefit); | ||
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| populateMathToLLVMConversionPatterns(typeConverter, patterns); | ||
| populateMathToROCDLConversionPatterns(typeConverter, patterns, | ||
| std::nullopt); | ||
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| patterns.add<ClusterIdOpToROCDL>(typeConverter, highBenefit); | ||
| patterns.add<ClusterDimOpToROCDL>(typeConverter, highBenefit); | ||
| patterns.add<ClusterBlockIdToBlockIdLowering>(&typeConverter.getContext(), | ||
| highBenefit); | ||
| patterns.add<ClusterDimBlocksToGridDimLowering>( | ||
| &typeConverter.getContext(), highBenefit); |
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Suggested change
| } else if (gpuTarget == "rocm") { | |
| using namespace mlir::gpu::index_lowering; | |
| PatternBenefit benefit(1); | |
| PatternBenefit highBenefit(2); | |
| patterns.add<gpu::index_lowering::OpLowering< | |
| gpu::ThreadIdOp, ROCDL::ThreadIdXOp, ROCDL::ThreadIdYOp, | |
| ROCDL::ThreadIdZOp>>(typeConverter, IndexKind::Block, IntrType::Id, | |
| benefit); | |
| patterns.add<gpu::index_lowering::OpLowering< | |
| gpu::BlockDimOp, ROCDL::BlockDimXOp, ROCDL::BlockDimYOp, | |
| ROCDL::BlockDimZOp>>(typeConverter, IndexKind::Block, IntrType::Dim, | |
| benefit); | |
| patterns.add<gpu::index_lowering::OpLowering< | |
| gpu::BlockIdOp, ROCDL::BlockIdXOp, ROCDL::BlockIdYOp, | |
| ROCDL::BlockIdZOp>>(typeConverter, IndexKind::Grid, IntrType::Id, | |
| benefit); | |
| patterns.add<gpu::index_lowering::OpLowering< | |
| gpu::GridDimOp, ROCDL::GridDimXOp, ROCDL::GridDimYOp, | |
| ROCDL::GridDimZOp>>(typeConverter, IndexKind::Grid, IntrType::Dim, | |
| benefit); | |
| patterns.add<GPULaneIdOpToROCDL>(typeConverter, benefit); | |
| patterns.add<GPUShuffleOpToROCDL>(typeConverter, benefit); | |
| patterns.add<GPUBarrierToROCDL>(typeConverter, benefit); | |
| populateMathToLLVMConversionPatterns(typeConverter, patterns); | |
| populateMathToROCDLConversionPatterns(typeConverter, patterns, | |
| std::nullopt); | |
| patterns.add<ClusterIdOpToROCDL>(typeConverter, highBenefit); | |
| patterns.add<ClusterDimOpToROCDL>(typeConverter, highBenefit); | |
| patterns.add<ClusterBlockIdToBlockIdLowering>(&typeConverter.getContext(), | |
| highBenefit); | |
| patterns.add<ClusterDimBlocksToGridDimLowering>( | |
| &typeConverter.getContext(), highBenefit); | |
| } else if (gpuTarget == "rocm") { | |
| mlir::populateGpuToROCDLConversionPatterns(typeConverter, patterns, mlir::gpu::amd::Runtime::HIP, amdgpu::Chipset()); |
I think we can figure out how to get the actual chipset details later.
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I have not added lit tests yet