Design with FPGA — Workshop

A progressive, hands-on workshop for designing digital hardware using SystemVerilog on the Sipeed Tang Nano 20K (and 9K). From toolchain setup to HDMI video output — build real circuits on real hardware.

The entire site is static HTML/CSS/JS — no framework, no bundler, no server required. Open index.html directly in any browser, including over file://.

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Features

• 12 chapters covering FPGA fundamentals through advanced peripherals
• Interactive SVG diagrams embedded inline in each chapter — no external deps, file:// compatible
  • LUT4 truth-table explorer (16-cell SRAM grid, 12 presets)
  • Logic Cell block diagram (combinational / registered modes, CE/SR controls, CLK pulse animation)
  • BSRAM memory explorer (8×8 cell grid, single-port / pseudo-dual-port modes)
  • SystemVerilog Module anatomy diagram (black-box ↔ anatomy views, live port annotations)
  • MUX / always_comb signal-flow diagram (active path highlighting, output ripple animation)
  • D Flip-Flop / always_ff diagram (CLK pulse animation, synchronous reset, pending badge)
  • Parameter explorer (live WIDTH selector, bus-bar width scaling, live instantiation syntax)
  • Module Instantiation hierarchy explorer (named vs. implicit port styles, signal annotations)
• Progress tracking — chapter completion saved to localStorage
• Dark / light theme toggle, persisted across sessions
• Syntax-highlighted code via highlight.js (bundled locally, no CDN)
• Lab source files for hands-on chapters (SystemVerilog + constraint files)

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Structure

FPGADesignWithTangNano20k/
├── index.html              # Landing page — chapter grid, board comparison
├── css/
│   ├── style.css           # Main stylesheet (CSS custom properties, dark/light themes)
│   ├── hljs-dark.min.css   # Highlight.js dark theme
│   └── hljs-light.min.css  # Highlight.js light theme
├── js/
│   ├── main.js             # Sidebar, progress tracking, theme toggle
│   └── highlight.min.js    # Bundled highlight.js
├── chapters/
│   ├── 01-intro/           # Introduction to FPGAs
│   ├── 02-toolchain/       # Gowin EDA + OSS CAD Suite setup
│   ├── 03-fpga-arch/       # FPGA Architecture (LUT4, LC, BSRAM, DSP)
│   ├── 04-sv-basics/       # SystemVerilog Basics
│   ├── 05-gpio/            # GPIO: LEDs & Buttons
│   ├── 06-combinational/   # Combinational Logic
│   ├── 07-sequential/      # Sequential Logic & FSMs
│   ├── 08-clocks-plls/     # Clocks & PLLs
│   ├── 09-simulation/      # Simulation (Icarus + GTKWave)
│   ├── 10-uart/            # UART Communication
│   ├── 11-display/         # Display Interfaces (RGB LCD, HDMI)
│   └── 12-memory/          # Memory (BSRAM, PSRAM)
├── labs/
│   ├── 05-gpio/            # blink.sv, button_debounce.sv, .cst files
│   ├── 06-combinational/
│   ├── 07-sequential/
│   ├── 08-clocks-plls/
│   ├── 09-simulation/
│   ├── 10-uart/            # uart_tx.sv, uart_rx.sv, uart_top.sv
│   ├── 11-display/
│   └── 12-memory/          # bram_sp.sv, psram_rw.sv
└── assets/
    └── images/

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Getting Started

1. Clone the repository:

   git clone https://github.com/ErickOF/FPGADesignWithTangNano20k.git
   cd FPGADesignWithTangNano20k

2. Open index.html in your browser — no build step, no server needed:

   # Linux / macOS
   xdg-open index.html   # or open index.html on macOS

3. Work through chapters in order. Each chapter page includes:

   • Concept explanations with interactive diagrams
   • Syntax-highlighted SystemVerilog code examples
   • Lab exercises with source files in labs/

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Target Hardware

Board	FPGA	LUTs	BSRAM	PLL	Notes
Tang Nano 20K	GW2AR-18	20,736	46×18kbit	2	Primary target
Tang Nano 9K	GW1NR-9	8,640	26×18kbit	1	Alternate; PSRAM lab

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Toolchain

The workshop supports two toolchains:

• Gowin EDA (official IDE) — GUI-based synthesis, place-and-route, programmer
• OSS CAD Suite — fully open-source: yosys (synthesis) + nextpnr-gowin (P&R) + openFPGALoader (flash)

Setup instructions are covered in Chapter 02.

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Chapter Overview

#	Title	Tags
01	Introduction to FPGAs	Concepts
02	Toolchain Setup	Setup
03	FPGA Architecture	Concepts
04	SystemVerilog Basics	HDL
05	GPIO: LEDs & Buttons	Lab, GPIO
06	Combinational Logic	Lab, Logic
07	Sequential Logic	Lab, FSM
08	Clocks & PLLs	Lab, Timing
09	Simulation	Lab, Verification
10	UART Communication	Lab, Serial
11	Display Interfaces	Lab, Video
12	Memory	Lab, Memory

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License

MIT