Issues

• UVM Register model with UVM-IEEE version

  Juniper/open-register-design-tool#97 · Filter by author bshiva1987 opened on Feb 10, 2025
  1

• Solving decoding congestion

  Juniper/open-register-design-tool#94 · Filter by author ehudeliaz opened on Sep 30, 2024
  3

• How to dump JSON file from a rdl?

  Juniper/open-register-design-tool#91 · Filter by author EngRaff92 opened on Nov 19, 2021

• Build in Debian/testing does not work

  Juniper/open-register-design-tool#89 · Filter by author wzab opened on Aug 18, 2021
  1

• Struct Generation not working

  Juniper/open-register-design-tool#88 · Filter by author abagchi opened on Feb 25, 2021

• Sticky interrupt with hardware precedence and write-one-to-clear can not be cleared

  Juniper/open-register-design-tool#87 · Filter by author tenaliram opened on Dec 15, 2020

• addressing and alignment properties of addressmap not being followed

  Juniper/open-register-design-tool#85 · Filter by author tenaliram opened on Aug 25, 2020
  1

• Control bit-width of address bus in addrmap

  Juniper/open-register-design-tool#84 · Filter by author tenaliram opened on Aug 16, 2020
  2

• Cannot get Ordt-viewer to work

  Juniper/open-register-design-tool#83 · Filter by author jyaghutiel opened on Jun 25, 2020

• clock gating issue

  Juniper/open-register-design-tool#82 · Filter by author xinhui-zhang opened on May 7, 2020

• When there is a secondary processor, decoder logic is out of sync.

  Juniper/open-register-design-tool#81 · Filter by author kongty opened on Apr 14, 2020

• Is there an option to enable address channel for each write and read, instead of one address channel?

  Juniper/open-register-design-tool#80 · Filter by author kongty opened on Apr 10, 2020

• How to have holding registers

  Juniper/open-register-design-tool#79 · Filter by author tkafafi opened on Feb 25, 2020

• External Reset signals Causing RTL generation to fail

  Juniper/open-register-design-tool#78 · Filter by author neenuprince opened on Dec 19, 2019
  2

• Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?

  Juniper/open-register-design-tool#75 · Filter by author neenuprince opened on Oct 18, 2019
  1

• How to connect the APB bus to the generated verilog module？

  Juniper/open-register-design-tool#73 · Filter by author zhajio1988 opened on Aug 21, 2019
  3

• New commits will be made to the sdnellen fork

  Juniper/open-register-design-tool#71 · Filter by author sdnellen opened on Jul 30, 2019

• RTl code has floating signals for HWRead SWwrite registers causing X's

  Juniper/open-register-design-tool#70 · Filter by author neenuprince opened on Jul 18, 2019
  2

• Register field ordering is broken.

  Juniper/open-register-design-tool#69 · Filter by author sjalloq opened on Jul 2, 2019
  2

• Ordt should generate an error on { sw=rw; hw=w; } with no hw we.

  Juniper/open-register-design-tool#68 · Filter by author sjalloq opened on Jun 14, 2019
  1

• Build error from source

  Juniper/open-register-design-tool#63 · Filter by author sjalloq opened on Jun 11, 2019
  2

• Incomplete reset specification on external register interface

  Juniper/open-register-design-tool#62 · Filter by author petenixon opened on Jun 6, 2019
  5

• XML Data Dictionary

  Juniper/open-register-design-tool#52 · Filter by author WebMonkey007 opened on Dec 5, 2018
  2

• Add support for callbacks to cppmod output

  Juniper/open-register-design-tool#36 · Filter by author ebertland opened on Nov 9, 2017
  3

• Feature Request: C header file output

  Juniper/open-register-design-tool#22 · Filter by author ebertland opened on Sep 5, 2017
  3