I am an incoming Master's student in Big Data Technology at The Hong Kong University of Science and Technology (HKUST), and a graduate of Jilin University (B.Eng. in CS, Top 13%). Currently, I am a Research Intern & Algorithm Engineer at Tencent WeChat Headquarters. My work thrives at the intersection of Large Language Models (LLMs), Agent Systems Infrastructure, and Hardware-Software Co-Design for Deep Learning. Research Framework & Focus: • LLM Optimization: Parameter-efficient fine-tuning (PEFT/LoRA), active learning, and data-centric efficiency. • Agent Infrastructure: Multi-turn tool integration, high-concurrency/low-latency workflows, and topological scaling. • AI Architecture & HPC: Near-Memory Processing (NMP) systems and trace-driven hardware-software co-simulation.

• First Author | Accepted to the Conference on Language Modeling (COLM) 2026
• Designed a two-stage active learning pipeline integrating entropy pre-filtering, SVD cold-start stabilization, and K-FAC curvature-aware influence scoring optimized for the LoRA manifold.
• Streamlined candidate evaluations by 70-80% via adaptive entropy thresholding, constraining data selection to a strict 20% budget.
• Achieved LLaMA-3.2-3B accuracies of 71.13% / 66.8% / 73.0% on GSM8K/BBH/StrategyQA, consistently outperforming full-data LoRA baselines.
• Accelerated end-to-end selection to 1.67h on a single V100 GPU (5.73× speedup over LESS, 2.80× over DataInf) with a peak VRAM of 16.6GB.

• First Author | Supervised by Prof. Xiaohui Wei @ Jilin University HPC Center
• Proposed a novel dimension-based dataflow mapping (as opposed to token-level partitioning) for Near-Memory Processing (NMP) systems, enforcing strict load balancing across parallel DRAM bank arrays.
• Developed a trace-driven hardware-software co-simulation engine using PyTorch hooks and SimPy discrete-event modeling to simulate physical DRAM row-buffer conflicts.
• Achieved a 27.7% reduction in end-to-end LLM inference step latency ($6920\text{ ns} \rightarrow 5000\text{ ns}$) and minimized workload variance (C.V. dropped from 23.89% to 7.09%).

Research Intern (E-commerce Governance Team) | 05/2026 - Present

• Algorithmic Optimization for Multi-Turn Tool Integration: Formulated an in-context tool composition mechanism within hierarchical skill abstractions, accelerating end-to-end response velocity by 2.0x (20s $\rightarrow$ 10s).
• Topological Design of Agentic Execution Systems: Conceptualized a hybrid architecture integrating heuristic routing, stateful workflows, and autonomous agentic fallbacks; achieved a state-of-the-art first-token latency of 5-6s under high-concurrency settings.

Research Intern | 12/2025 - 05/2026

• Mitigating Catastrophic Forgetting: Developed an interactive conversational decision framework; fine-tuned parameterized LLMs (Qwen3-8B) via synthetic, chain-of-thought (CoT) alignment topologies to mitigate knowledge degradation.
• High-Dimensional Representation Pipelines: Engineered a dual-stage cascade infrastructure leveraging dense neural vector retrieval coupled with fine-grained LLM classification; expanded the evaluation space from 31 to 340 semantic classes while maintaining Precision/Recall > 95%.