PWM optimization for RA6M5

targets/arm/mikroe/common/include/flatten_me.h

@@ -0,0 +1,71 @@
+/****************************************************************************
+**
+** Copyright (C)  MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  flatten_me.h
+ * @brief mikroSDK code flattener level selection.
+ */
+
+#ifndef __FLATTEN_ME_H__
+#define __FLATTEN_ME_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Flattening levels.
+ *   @ref FLATTEN_ME_LEVEL_NONE - no code flattening done.
+ *   @ref FLATTEN_ME_LEVEL_LOW  - flatten only HAL_LL APIs.
+ *   @ref FLATTEN_ME_LEVEL_MID  - flatten only HAL_LL and HAL APIs.
+ *   @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV).
+ */
+#define FLATTEN_ME_LEVEL_NONE (0)
+#define FLATTEN_ME_LEVEL_LOW  (1)
+#define FLATTEN_ME_LEVEL_MID  (2)
+#define FLATTEN_ME_LEVEL_HIGH (3)
+
+// Flatten code or not?
+#define FLATTEN_ME
+
+// Flatten level selection.
+#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLATTEN_ME_H__

targets/arm/mikroe/renesas/include/hal_ll_mstpcr.h

@@ -65,6 +65,7 @@ extern "C"{
     #define _MSTPCRB   ( uint32_t * )0x40084004
     #define _MSTPCRC   ( uint32_t * )0x40084008
     #define _MSTPCRD   ( uint32_t * )0x4008400C
+    #define _MSTPCRE   ( uint32_t * )0x40084010
 #endif
 
 #define MSTPCRA_MSTPA0_POS 0 // SRAM0
@@ -106,6 +107,7 @@ extern "C"{
 #define MSTPCRD_MSTPD20_POS 20 // DAC12
 #define MSTPCRD_MSTPD29_POS 29 // ACMPLP
 #define MSTPCRD_MSTPD31_POS 31 // OPAMP
+#define MSTPCRE_MSTPE31_POS 31 // GPT-enable/offset
 
 typedef struct
 {

targets/arm/mikroe/renesas/src/tim/implementation_1/hal_ll_tim.c

@@ -321,6 +321,7 @@ hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handl
 
     *hal_module_id = pin_check_result;
 
+
     hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle =
                         ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
 
@@ -489,17 +490,25 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
 }
 
 static void hal_ll_tim_module_enable( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) {
-    if ( true == hal_ll_state ) {
-        if ( 1 >= map->module_index )
-            clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS );
-        else if ( 7 >= map->module_index )
-            clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS );
-    } else {
-        if ( 1 >= map->module_index )
-            set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS );
-        else if ( 7 >= map->module_index )
-            set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS );
-    }
+    #if ( defined(R7FA4M1) || defined(R7FA6M3))
+        if ( true == hal_ll_state ) {
+            if ( 1 >= map->module_index )
+                clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS );
+            else if ( 7 >= map->module_index )
+                clear_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS );
+        } else {
+            if ( 1 >= map->module_index )
+                set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD5_POS );
+            else if ( 7 >= map->module_index )
+                set_reg_bit( _MSTPCRD, MSTPCRD_MSTPD6_POS );
+        }
+    #elif ( defined(R7FA6M5))
+        if ( true == hal_ll_state ) {
+                clear_reg_bit( _MSTPCRE, MSTPCRE_MSTPE31_POS -  map->module_index );
+        } else { 
+                set_reg_bit( _MSTPCRE, MSTPCRE_MSTPE31_POS - map->module_index );
+        }
+    #endif
 }
 
 static uint32_t hal_ll_tim_clock_source() {
@@ -588,6 +597,7 @@ static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) {
 }
 
 static uint32_t hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) {
+hal_ll_gpio_pin_t pin;
 
     hal_ll_tim_module_enable( map, true );