Update G33 for virtual encoder indexes - #104
staskaaa-netizen wants to merge 2 commits into
Conversation
|
I want to bench test this G33 module using my spindle simulator on an ESP32 (RP2350 is ordered). The idea is to set the actual PPR to 16 and ENCODER0_VIRTUAL_INDEX_CPR to 2 or 4; That would result in a 8 or 4 PPR virtual encoder. The synchronization can than be compared to the current (latest) G33 module. When I compile I get an error: When I use the G33 and esp32_pcnt_encoder module from your pull request staskaaa-netizen:encoder-backends-g33 #105 it does compile. cnc_hal_overrides.h changes |
|
Will look into it. esp32 was orphaned/not hard tested on my side after discovering rp2350. Just two different worlds. |
|
I will test your fix tomorrow. Why favor the RP2350 and not the RP2040? |
|
More Sram. I need 234.4 KiB ~ half of total of 520 for last mile video buffer . And 12 Pio. External ram is present too, but i cant make it work nicely with DMA. Only drawing buffers. |
|
I compared (bench test) the G33 synchronization PR #104 to the current #107 release. I simulated a 4 PPR and 8 PPR encoder with index and used an ESP32 processor. It seems #104 is partially based on #103 and has the same "issues": Synchronization can't handle well RPM speed changes during the initial ramp up and PPR changes requires tuning of the error correction speed. These issues are solved in #107. If your goal is to implement virtual encoder indexes, than adding this feature to the #107 release would be an option. If you would like me to test using a different setup, let me know. Below you find my test results and the configuration I used to test #104. Check my config because it is possible the issues are due to my configuration. Results: Pull request G33 release #104 <Idle|MPos:0.000,0.000,0.000|FS:0.000,149|Buf:19,128> |
|
Question - mine does not work / was not designed for scenario for spindle on/off just before sync. it may not not ram normally. it was made for all time running one. So this one will be an issue. Or some paramas must be adjusted On setup - this is minimal setup for rp2350 one, should be same for rp2040 too. : ` #define ENABLE_RP2350_PIO_ENCODER #ifdef ENABLE_RP2350_PIO_ENCODER #define ENCODERS 1 //pins should be not arvitrary order, B must follow A //pio setup #define ENC0_IS_INCREMENTAL //#define ENCODER_DEBUG_PRINT_100MS 1 // optional test only #define SPINDLE_PWM_RPM_ENCODER ENC0 #define G33_ENCODER ENC0 #define G33_DEBUG #define ENC0_VIRTUAL_INDEX 1 Later grbl should send back all 3 counters + spindle rpm : ?23:52:11.332 > <Idle|MPos:0.000,0.000,0.000|FS:0.000,197|EC:3298985|ECB:89|ECI:800,-8400,800,3849|Ln:0|Pn:XZ|WCO:0.000,0.000,0.000> |
The bench test was performed using the spindle simulator that doesn't stop between passes. The simulator is an ESP32-C3 that continuously generates index and sync pulses. I can publish the code if you want it.
My spindle simulator only generates a synchronization pulse on 1 channel. It does not simulate a quadrature encoder. My lathe also has an index pulse and a single synchronization pulse. In the encoder configuration channel B is not assigned. Since it is all about changing the behavior of the encoder module, I wonder if it is not possible to get the same results by just changing the encoder module. I am thinking about binding the encoder pin interrupt to the counter interrupt. Maybe I am confused because I thought you wanted to reduce the encoder sync pulses by counting them using a timer. |
|
I finished testing the #107 G33 module using different PPR encoder settings and different pitches. I tested using 2 to 16 PPR and G33_SYNCHRONIZATION_SPEED settings of 4 to 16. Previous testing showed that the time to synchronize does not change when the RPM changes. So at higher RPM the distance to synchronize will increase. Also all tested processors (Aruino Mega, STM32 bluepill, RP2040, ESP32, SAMD21) perform the same. Based on the results below I found that:
I included the full test results: For the record, I still think it is a good idea to use encoder pulses for G33 synchronization as long as there is a hardware index pulse. |
No description provided.