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f2b119f
#TestCICD merge fix for simulation phase in CICD.
Sep 21, 2023
22bbc17
#TestCICD : checking merge fix for simulation
Sep 21, 2023
49e6065
#TestCICD : checking merge fix for simulation
Sep 21, 2023
10df0da
#TestCICD : back allowing simulation phase to fail.
Sep 21, 2023
031c622
Merge commit 'cd3882' (21/12/22) of official openpiton-dev into merg…
Sep 22, 2023
6776049
Merge remote-tracking branch 'origin/merge/openpiton-dev-test' into m…
Sep 22, 2023
b7a58ad
#TestCICD Merge commit 'b32615' (21/07/23) of official openpiton-dev…
Sep 22, 2023
4faa0cd
#TestCICD Decreasing difference with official openpiton-dev.
Sep 24, 2023
5407eaa
#TestCICD Reducing unnecessary changes comparing with official openpi…
Sep 26, 2023
5b86edd
#TestCICD Fix for simulation stage in CICD, decreasing difference wit…
Sep 28, 2023
11aa98a
#TestCICD update of protosyn/setup scripts, eth/uart verilogs (minor …
Sep 29, 2023
315cdb4
#TestCICD Removing extra xci files.
Sep 30, 2023
f6b3a60
#TestCICD Fix: Rolling back Makefile going to support UART boot.
Sep 30, 2023
ab36501
#TestCICD Adding dummy uart_data.coe file needed to initialize UART f…
Sep 30, 2023
3e14839
#TestCICD making rtl_setup.tcl max close to one in official OP.
Oct 1, 2023
49f8c6d
Replacement of BSC Ariane to official one. So far after bootrom stage…
Oct 4, 2023
3b350a0
Excluding SD actions from bootrom main. Baremetal through UART by pit…
Oct 5, 2023
9c329ed
Fixes for Lagarto case.
Oct 5, 2023
d78e3a4
Making bootrom scripts like for BSC Ariane. The Linux doesn't start b…
Oct 5, 2023
ea95ec7
Roll back to `cbbcf3` (3/06/20) commit of official Ariane: Linux boot…
Oct 7, 2023
c9d304d
Restoring script/makefiles relating to `rv64_platform` bootrom genera…
Oct 8, 2023
b3c9152
Restoring "Removed zeroed memory checking. PCIe must zero cpu mapped …
Oct 8, 2023
d223e75
#TestCICD Update of official Ariane to commit `934bfeaf` (04/10/19 ->…
Oct 10, 2023
d088119
#TestCICD : allowing simulation phase to fail in CICD.
Oct 10, 2023
82fe6ab
#TestCICD Ariane list in rtl_setup.tcl like in official OP.
Oct 10, 2023
10f0c42
Making flexible length of NOC read data packet in NOC serialization p…
Oct 11, 2023
c3a8b37
Rolling back NOC serialization process to have fixed length of NOC re…
Oct 11, 2023
bce7ba9
Update of Alveo section in Readme
Oct 12, 2023
6660a92
#TestCICD Making correct flexible length of NOC read data packet in N…
Oct 13, 2023
77c17bf
Rolling back again NOC serialization process to have fixed length of …
Oct 15, 2023
b0f6597
Update to official Ariane to commit `575cb4` (26/08/20) with patches …
Oct 15, 2023
ea7d27c
#TestCICD Merge branch 'merge/openpiton-dev' into merge/offic_ariane
Oct 15, 2023
38a2ea4
#TestCICD Merge into merge/openpiton-dev branch all of 'merge/offic_…
Oct 16, 2023
eacee0a
#TestCICD fixes for BSC Ariane.
Oct 16, 2023
6a7c3e9
#TestCICD noc_axi4_bridge.v : making explicit effectively used AXI4…
Oct 18, 2023
3a8d682
#TestCICD Enabling Eth core AXI stub if `--eth` flag is absent in ord…
Oct 18, 2023
a47a274
#TestCICD Merge 'origin/merge/offic_ariane' into merge/openpiton-dev…
Oct 19, 2023
8bfe555
#TestCICD Update of NOC-AXI4 bridge to support flexible AXI burst len…
Oct 22, 2023
165be56
#TestCICD light timing fix for 300 MHz DDR memory define case.
Oct 23, 2023
86badde
#TestCICD Merge branch 'merge/offic_ariane' into merge/openpiton-dev…
Oct 23, 2023
8952938
Updating the paths in .gitmodules and updating .gitlab-ci.yml to trig…
fcano3 Oct 25, 2023
774d6d7
#TestCICD Update of NOC-AXI4 bridge to support `define L2_SEND_NC_REQ
Oct 26, 2023
2d6944b
#TestCICD Making unified DTS/Bootrom generation for both Ariane and L…
Oct 31, 2023
bde2bef
#TestCICD Light cosmetics in Readme
Nov 1, 2023
a0f6851
#TestCICD Adding buffer simplified structure diagram as a comment to…
Nov 2, 2023
38b28a4
Starting "minimal" merge with official "openpiton-dev" branch. First …
Nov 2, 2023
4fb1649
Partial remove of Lagarto dependencies, and remove of sub-optimal rou…
Nov 3, 2023
a76c99f
Unified usage of `PITON_RV64_PLATFORM` definition for both PITON_LAGA…
Nov 3, 2023
87b1814
#TestCICD More unification with `PITON_RV64_PLATFORM` definition.
Nov 4, 2023
8c6fb3c
#TestCICD Merge branch 'merge/offic_ariane' into merge/openpiton-dev
Nov 4, 2023
143a575
Merge of `merge/offic_ariane` into `merge/openpiton-dev_min`
Nov 5, 2023
3a7ff71
initial files added and some modified to add u55c
Nov 6, 2023
2527156
#TestCICD Restoring original location of AXI-Lite bus definitions (no…
Nov 6, 2023
4d09eda
#TestCICD Roll-back of previous restore of AXI-lite definitions locat…
Nov 6, 2023
d876893
#TestCICD Merge branch 'merge/offic_ariane' into merge/openpiton-dev
Nov 6, 2023
8ac4dfc
Merge branch 'merge/offic_ariane' into merge/openpiton-dev_min
Nov 7, 2023
0ef8ea2
#TestCICD Merge remote-tracking branch 'upstream/openpiton-dev' into…
Nov 7, 2023
7540ef8
#TestCICD Removing new submodile `u-boot` untill it gets free access …
Nov 7, 2023
7724953
#TestCICD Removing once again new submodile u-boot untill it gets fre…
Nov 7, 2023
a4780e7
#TestCICD Merge branch 'merge/offic_ariane' into merge/openpiton-dev
Nov 7, 2023
adab8e1
#TestCICD Merge branch 'merge/offic_ariane' into merge/openpiton-dev,…
Nov 8, 2023
45eeca6
#TestCICD update drac-inorder: set back access xcpts to original stat…
bscabancens Nov 8, 2023
daaf70c
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Nov 8, 2023
eb6d289
#TestCICD Making noc_axi4_bridge compliant with Verilator.
Nov 8, 2023
b563b46
#TestCICD Merge branch 'merge/openpiton-dev' into merge/bsc_ariane
Nov 8, 2023
91d4339
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Nov 8, 2023
e9968bf
Update QUesta version
joancabre Nov 10, 2023
7edd9e3
Eliminating functionality related to removed submodules: lagarto, mem…
Nov 10, 2023
cef4e79
#TestCICD Some cleanup.
Nov 10, 2023
d09c8c2
#TestCICD Merge branch 'merge/openpiton-dev' into merge/bsc_ariane
Nov 10, 2023
b3400be
#TestCICD Elimination of `mentor` mentioning in setup scripts.
Nov 11, 2023
4178f56
#TestCICD Removing simulation stage for Ariane in CICD since it fail…
Nov 11, 2023
8aa6328
#TestCICD Merge branch 'merge/openpiton-dev' into merge/bsc_ariane
Nov 11, 2023
34b6b5b
#TestCICD Further elimination of outdated/not-needed developments of…
Nov 13, 2023
683d030
#TestCICD Further elimination of outdated/not-needed developments of…
Nov 13, 2023
873d9ac
#TestCICD Merge branch 'merge/bsc_ariane' into merge/openpiton-dev
Nov 14, 2023
ed12963
VPU access fix: Merge remote-tracking branch 'origin/fix/vpu_xcp_ld/m…
Nov 15, 2023
e8629e4
#TestCICD Adding `u-boot` submodule from github as in latest officia…
Nov 15, 2023
e9b73cd
Elimination of CICD support since it anyway doesn't work without Laga…
Nov 15, 2023
58ba19a
#TestCICD Trying to suppress some Verilog compile errors breaking sim…
Nov 15, 2023
2c10f67
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Nov 15, 2023
08a56f6
#TestCICD Fix in suppressing errors for Queta simulation in CICD: th…
Nov 16, 2023
09c4f8d
#TestCICD Some refactoring of `eth_top` module: returning back resync…
Nov 20, 2023
4582bb3
meep_shell.tcl updated
Nov 20, 2023
8f83e9e
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Nov 21, 2023
d4f465a
meep_shell.tcl updated
Nov 21, 2023
74bd807
Returning back Verilog type to top `chip` source instead of SystemVer…
Nov 21, 2023
2f2e33a
Elimination of support of "wrapper" MEEP shell.
Nov 22, 2023
6680dd2
#TestCICD Cleanup: Removing unreacheable code.
Nov 22, 2023
48e95b0
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Nov 23, 2023
6d7d315
#TestCICD noc_axi4_bridge: Wrapping up functions to the package in o…
Nov 28, 2023
f9653ef
scripts updated
Nov 28, 2023
a4afdd4
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_min (noc_…
Nov 28, 2023
b4e350f
Merge branch 'merge/openpiton-dev_min' into merge/openpiton-dev_upstr…
Nov 28, 2023
e0bb87d
macros added
Nov 29, 2023
b8724d8
#TestCICD Fixing some incompatibilities with Synopsys DC realted to n…
Nov 29, 2023
c933770
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Nov 29, 2023
8c0942c
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_u55c
Nov 29, 2023
456def7
Some alignment with current `merge/openpiton-dev`.
Nov 29, 2023
5499e24
More alignment with current `merge/openpiton-dev`.
Nov 29, 2023
e5fc67f
Moving Eth CMAC IP to `io_ctrl` common location instead of U280 speci…
Nov 29, 2023
ea6ece8
Restoring board.tcl file for U55C
Nov 29, 2023
3cada86
generates bitstream but linux doesn´t boot
Nov 29, 2023
c0fe27d
Merge remote-tracking branch 'origin/origin/merge/add_u55c_board' int…
Nov 30, 2023
4843e2b
Some refactoring to support multiple Alveo boards.
Dec 2, 2023
1c1b173
Refactoring baremetal sram_test.c to more general mem_test.c, by defa…
Dec 3, 2023
8bf369e
#TestCICD Getting rid of an option to implement exchange SRAM in Embe…
Dec 4, 2023
0c06a53
Making soft links to `devices_...xml` for different Alveo boards inst…
Dec 5, 2023
5eaf428
#TestCICD Initial refactoring of Embedded Shell to support just only …
Dec 6, 2023
550ca21
#TestCICD Final refactoring of Embedded Shell to support mutulay excl…
Dec 8, 2023
4f8fee8
#TestCICD Making Embed shell TCL independent of FPGA part.
Dec 10, 2023
6318705
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 11, 2023
6d54176
#TestCICD Successfull build by protosyn flow for Alveo U55C. Boot of …
Dec 12, 2023
5f187e9
#TestCICD Update of U55C Ethernet constraints.
Dec 12, 2023
4c270d0
#TestCICD Refactoring address space assignment in Embed Shell, moving…
Dec 13, 2023
8142739
#TestCICD Embed Shell: Moving PCIe AXI to channel 31 of HBM. U55C bit…
Dec 14, 2023
46b743c
#TestCICD Embed Shell: changing HBM channel for PCIe QDMA to 30. Boot…
Dec 14, 2023
f28cc53
#TestCICD Embed Shell: fixing a typo.
Dec 15, 2023
be19ab6
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Dec 15, 2023
37be746
Merge remote-tracking branch 'origin/merge/openpiton-dev' into merge/…
Dec 15, 2023
65c90b3
#TestCICD JTAG interface from MEEP Shell is enabled by default.
Dec 20, 2023
32358aa
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 20, 2023
34649f1
Initial map to Vivado-2023.2. Baremetal DDR test through `pitonstream…
Dec 21, 2023
4b369ff
#TestCICD `protosyn` flow: Fix of pins for reference clock for DDR a…
Dec 21, 2023
b591f94
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 21, 2023
7f8b0b7
#TestCICD Update of JTAG usage for MEEP shell, now in pure JTAG mode,…
Dec 22, 2023
cb9ad3f
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 22, 2023
17a2cc4
#TestCICD Returning back diff port at U55C for HBM reference clock wh…
Dec 27, 2023
8b3e629
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 27, 2023
1cf33b7
#TestCICD Adding small JTAG shell based on FPGA builtin BSCAN chain.
Dec 27, 2023
efbc1e5
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 27, 2023
9f1d13d
#TestCICD Embedded Shell: refactoring `jtag_chain` to `jtag_shell`.
Dec 28, 2023
c779758
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 28, 2023
3f1cc33
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Dec 28, 2023
ea3b6f4
#TestCICD Proper propagation of set sytem clock frequency to FPGA imp…
Dec 29, 2023
fa3b9c2
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 29, 2023
9a05102
#TestCICD Adding CDC constraints for HBM APB interface clocked by fix…
Dec 29, 2023
d65e4fc
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Dec 29, 2023
781277a
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Dec 29, 2023
8a87f2c
#TestCICD Proper constraints for JTAG CDC.
Jan 2, 2024
3f48d37
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 2, 2024
d05f32f
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Jan 3, 2024
80bda8f
#TestCICD Making 50 MHz default freq for U55C board since it provides…
Jan 7, 2024
f8351e5
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 7, 2024
6410567
#TestCICD Clean-up of timing constraints, primarily elimination of "s…
Jan 12, 2024
07e11ec
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 12, 2024
132c744
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Jan 13, 2024
f6d648b
#TestCICD NOC-AXI bridge: changing default synthesis of "Outstanding …
Jan 14, 2024
30a035a
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 14, 2024
14c60e7
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Jan 15, 2024
79540b4
#TestCICD Enabling "performance optimized" strategies for Vivado impl…
Jan 17, 2024
16a6e7e
#TestCICD Merge remote-tracking branch 'upstream/openpiton-dev' into …
Jan 17, 2024
625f9e2
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 17, 2024
2b38eaa
#TestCICD Fix of file type.
Jan 17, 2024
b5dbf65
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 17, 2024
a959296
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Jan 17, 2024
96e85fd
#TestCICD Refactoring of port list in `chipset_impl`, closer to origi…
Jan 24, 2024
1a97a96
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Jan 24, 2024
a1f8218
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_2023.2
Jan 24, 2024
acfa9dd
#TestCICD Getting rid of MMCM xci file.
Feb 28, 2024
9b6cab8
#TestCICD Getting rid of all xci files.
Feb 29, 2024
896b142
#TestCICD Fix for wrapper MEEP_SHELL: generation of Xilinx async FIFO…
Mar 1, 2024
c0c856a
#TestCICD Proper fix for wrapper MEEP_SHELL: generation of Xilinx asy…
Mar 1, 2024
dae3e09
added xilinx fifo and clock manager IP files for u250
sahmedbsc Mar 7, 2024
780e93c
uart ip files
sahmedbsc Mar 7, 2024
4534b86
added board support for u250 in protosyn
sahmedbsc Mar 7, 2024
3c8af17
constraints files for u250
sahmedbsc Mar 7, 2024
c9ee15a
added qdma IP location for u250
sahmedbsc Mar 7, 2024
b41b876
added 100gb ethernet support for u250
sahmedbsc Mar 7, 2024
1e139f1
#TestCICD noc_axi4_bridge: propagation of few updates due to fixes o…
Mar 8, 2024
bc0f7b3
#TestCICD Some better alignment with original `openpiton-dev`
Mar 14, 2024
5f9e8ec
#TestCICD Extra light alignment with original `openpiton-dev`
Mar 14, 2024
06f95da
#TestCICD Merge branch 'merge/openpiton-dev' into merge/openpiton-de…
Mar 14, 2024
04968a6
#TestCICD Adapting timing closure to more strict Vivado-2023.2. Adapt…
Mar 15, 2024
715fead
#TestCICD light comment fix
Mar 18, 2024
e0bee79
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Mar 19, 2024
aabce4b
Adding error suppression for simulation of Ariane in Questa.
Mar 19, 2024
4122a4a
added Alveou250 board option to differentiate DDR input clock period
sahmedbsc Mar 20, 2024
e781cd0
updated USER_SLR_ASSIGNMENT to include all blocks in to SRL1
sahmedbsc Mar 20, 2024
2734f78
updated DDR port connections to DIMM 1 in SLR1
sahmedbsc Mar 20, 2024
021fa92
updated package pins for input clocks
sahmedbsc Mar 20, 2024
ed31b14
Adding U250 board option to sims script.
Mar 25, 2024
9a0e002
noc_axi4_bridge: Introducing NOC2AXI_DESER_ORDER_AUTO parmeter (enabl…
Mar 27, 2024
b2662d6
#TestCICD Merge branch 'openpiton-dev' into merge/openpiton-dev
Mar 27, 2024
6ed10ce
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Mar 27, 2024
48267e7
#TestCICD Bug fix in `noc_axi4_bridge` deserializer state machine lea…
Mar 28, 2024
4b0884e
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
Mar 29, 2024
318ab1c
#TestCICD Update of 100GbE: support of AXI clock out range 50...250 M…
Apr 30, 2024
90c87c3
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
May 1, 2024
28b3d3c
#TestCICD Fix in write/read modules of noc_axi4_bridge: earlier assig…
May 7, 2024
bfa1a0b
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
May 7, 2024
e84ef91
Merge branch 'merge/openpiton-dev' into alveou250
May 16, 2024
a4a1de1
Setting board level input frequency to MMCM 300 MHz for `alveo250`, f…
May 18, 2024
ed3392f
Making MMCM input frequency dependent on board type.
May 20, 2024
6a944c5
Initial clean-up of `meep_shell` and `100GbE shell`.
May 21, 2024
5851fc4
Proper assignments of QSFP/CMAC locations, other refactorings and cle…
May 22, 2024
c464b46
#TestCICD Merge alveou250 to merge/openpiton_dev (Last commit: Minor …
May 22, 2024
7f347b6
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
May 23, 2024
badf5e4
Changing `devices.xml` for U250 to symbolic links to U280.
May 24, 2024
989de19
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
May 24, 2024
ebd3e71
#TestCICD Light refactoring of constraints
May 26, 2024
05c67e1
#TestCICD Refactoring of SDRAM-related constraints.
May 28, 2024
7f549c5
Merge branch 'merge/openpiton-dev' into merge/openpiton-dev_upstr
May 28, 2024
dca9b3b
Included DDR4 options, disabled by default
Jun 13, 2024
1e64ce1
DDR compatible options
Jun 13, 2024
4a4ff08
new flavour for DDR call to protosyn
Jun 13, 2024
8dba55e
Merge branch 'ft/DDR4_acc' of https://gitlab.bsc.es/hwdesign/framewor…
Jun 19, 2024
8a7f6a9
#TestCICD Update of 100GbE test app to support execution on Lagarto-Ox.
Jun 27, 2024
b7f21dd
#TestCICD Update of Eth app to support Standalone Lagarto-Ox SOC.
Jul 1, 2024
631a77a
solved DDR flavour
Jul 2, 2024
12c2a37
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Jul 2, 2024
26bb5fd
#TestCICD Changing default JTAG for Wrapper MEEP Shell in `accelerato…
Jul 6, 2024
639d12b
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Jul 8, 2024
553fb1f
Merge branch 'production_origCVA6' into ft/DDR4_acc
Aug 29, 2024
a3bde0c
Excluding explicit `ddr` option, absence of `hbm` should be enough.
Aug 29, 2024
3bc9ece
Merge branch 'openpiton-dev' into ft/DDR4_acc
Aug 30, 2024
4d9f5b8
Fix of rounding in UART divisor calculation, critical for low freq (2…
Aug 30, 2024
e4f55d7
Sync with production.
Sep 16, 2024
102ceed
`accelerator_def.csv`: update of memory type notion for PCIe/Eth/Aurora
Sep 16, 2024
d611ad1
`meep_shell/accelerator_def.csv `: adding support of multiple AXI por…
Sep 18, 2024
263e321
Eth test app: extending HBM case to DDR option.
Sep 19, 2024
ec1bbff
100GbE: update of Xilinx bare-metal drivers to 2024.1
Sep 23, 2024
83b681c
#TestCICD Merge branch 'ft/DDR4_acc' into production_origCVA6
Sep 25, 2024
a255cf1
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Sep 27, 2024
31b5622
#TestCICD Using `git apply` for Ariane patching.
Sep 29, 2024
3d0cb7e
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Sep 29, 2024
50966d8
#TestCICD Board dependent parameter for SDRAM address width (DDR or …
Oct 2, 2024
ad39b4f
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Oct 3, 2024
e935d99
Removing non-submodule based 100GbE.
Jan 10, 2025
be5a185
#TestCICD Replacing just TCL file for 100GbE with a repo as submodul…
Jan 13, 2025
98b0ccd
Merge remote-tracking branch 'origin/production_origCVA6' into merge/…
Jan 20, 2025
58f0703
#TestCICD Update of 100GbE IP: making single DMA master port configu…
Jan 29, 2025
6ad7aac
#TestCICD 100GbE: some updates of both sw apps: syst and proto.
Jan 31, 2025
d98ef70
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Feb 3, 2025
97c488a
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Feb 3, 2025
ad59c69
#TestCICD Extension of using embedded 100GbE with DRAM as DMA memory.
Feb 20, 2025
5ce45ce
#TestCICD After adding 322MHz 100GbE domain, update of placement con…
Feb 20, 2025
70d1e59
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Feb 23, 2025
35149f1
Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Feb 24, 2025
6673bcf
#TestCICD Introduction of non-cached logical access to DRAM through …
Feb 27, 2025
57ed727
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Feb 28, 2025
fe4d1b6
Removing all physical hardware under `PITON_NONCACH_MEM` and `PROTOSY…
Feb 28, 2025
021c656
Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Mar 2, 2025
983dd62
#TestCICD Moving Ethernet specific constraints inside 100GbE submodule.
Mar 5, 2025
9cc9e29
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Mar 5, 2025
57cf1e2
Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Mar 6, 2025
02b4368
#TestCICD Update of 100GbE IP: custom smart eth_rx_fifo is used inste…
Apr 25, 2025
58573d1
#TestCICD Update of 100GbE: increase of Rx FIFO depth.
Apr 26, 2025
5b6a722
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
May 4, 2025
54b575f
Merge remote-tracking branch 'origin/merge/openpiton-dev_upstr' into …
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5 changes: 4 additions & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,7 @@
url = https://github.com/PrincetonUniversity/openpiton-aws.git
[submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"]
path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot
url = [email protected]:u-boot/u-boot.git
url = https://github.com/u-boot/u-boot.git
[submodule "piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst"]
path = piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst
url = https://github.com/bsc-loca/100gb-ethernet
61 changes: 61 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -505,3 +505,64 @@ The command will tell print the afi and agfi of your image. You can track the sy

8. After the synthesis is done - you can go load it in your F1 instance!

### Synthesizing OpenPiton for ALVEO boards

This section has been added under MEEP project. For an eventual PR to OpenPiton team, we will need to review it.

The flow is very simillar to synthesizing image for any other FPGA OpenPiton supports:

1. Clone OpenPiton repo (MEEP version): git clone https://gitlab.bsc.es/hwdesign/frameworks/meep_openpiton.git

2. cd into repo, run these bash commands:

```
source piton/piton_settings.bash
source piton/ariane_setup.sh
(Follow instructions in the top of the README in case this is the first time you install OpenPiton in your machine.)
```

4. Run the synthesis:

```
protosyn --board alveou280 --design system --core ariane --x_tiles 1 --y_tiles 1 --uart-dmw ddr --zeroer_off

Extra avaialble protosyn options:
--eth # adding CMAC based Ethernet unit
--ethport <num> # optional board-level Ethernet port (default=0)

--hbm # define HBM as primary system memory
--multimc <num> # implement design with multiple <num> connections to system memory (valid only for HBM)
--multimc_indices <coma separated list> # optional list of particular edge tiles for above `multimc` option

--bram-test hello_world.c # compiling and runniing VCS-based simulation before synthesis
--verdi-dbg # creating Verdi compliant simulation database for above test (verdi run inside ./build dir (-sx is optional): verdi -ssf ./novas.fsdb)
```

This will create a Vivado design under $ROOT_DIR/build/...

5. After the synthesis is complete (takes about 2-3 hours on fast PC), you can program the FPGA via JTAG

6. Probably you would need to reboot to be able to use the new QDMA PCIe interface.

7. Now you can download from the intranet the bbl containing the Linux kernel, a script to load it to the SDRAM and the bitstream itself in case you want to skip steps above.

```
/home/fpga-runnerMEEP/lagarto_sdk_deploy/rv64gc/
```

In a separated bash window, open a client for the UART:

```
picocom -b 115200 /dev/ttyUSB2
```

8. Clone FPGA tools repo: https://gitlab.bsc.es/hwdesign/fpga/integration-lab/fpga-tools.git

Issue the next commands inside the downloaded repo:

```
./fpga/load-bitstream-onic.sh qdma <fpga_bistream_name>.bit
./boot_riscv/boot_acme.sh <osbi_buildroot>.bin
```

You should be able to see Linux booting on the other terminal.
104 changes: 104 additions & 0 deletions piton/design/chip/rtl/chip.v.pyv
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// Modified by Barcelona Supercomputing Center on March 3rd, 2022
// Modified by Princeton University on June 9th, 2015
// ========== Copyright Header Begin ==========================================
//
Expand Down Expand Up @@ -139,6 +140,17 @@ module chip(
output offchip_processor_noc3_yummy
`endif // endif PITON_NO_CHIP_BRIDGE

`ifdef PITON_EXTRA_MEMS
,
output [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] processor_mcx_noc2_data,
output [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_valid,
input [`PITON_EXTRA_MEMS-1:0] processor_mcx_noc2_yummy,

input [`PITON_EXTRA_MEMS * `NOC_DATA_WIDTH -1:0] mcx_processor_noc3_data,
input [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_valid,
output [`PITON_EXTRA_MEMS-1:0] mcx_processor_noc3_yummy
`endif

`ifdef PITON_RV64_PLATFORM
`ifdef PITON_RV64_DEBUGUNIT
// Debug
Expand Down Expand Up @@ -1037,6 +1049,15 @@ module chip(
assign default_total_num_tiles = `PITON_NUM_TILES;
// Generate tile instances
<%
sub_assign = r'''
assign default_coreid_x [_FLAT_ID_] =COREIDX;
assign default_coreid_y [_FLAT_ID_] =COREIDY;
assign flat_tileid [_FLAT_ID_] = _FLAT_ID_;
'''
assign = r'''


'''
template = r'''
tile #(.TILE_TYPE(TYPE_OF_TILE))
tile0 (
Expand Down Expand Up @@ -1114,6 +1135,32 @@ module chip(
template = template[:-1] + r'''
);
'''


edge_sub1=r'''
assign default_coreid_x [ENDP] = COREIDX;
assign default_coreid_y [ENDP] = COREIDY;
assign flat_tileid [ENDP]= ENDP;

assign dataOut_NN [ENDP] = endp_DatOut_NN;
assign validOut_NN[ENDP] = endp_ValidOut_NN;
assign endp_YummyIn_NN = yummyIn_NN[ENDP];
'''
edge_sub2=r'''
assign endp_DatIn_NN = dataIn_NN [ENDP];
assign endp_ValidIn_NN = validIn_NN[ENDP];
assign yummyOut_NN[ENDP] = endp_YummyOut_NN;

'''
edge_assign=r'''

'''


MC_POS=get_mc_mapping(PITON_X_TILES,PITON_Y_TILES,PITON_MC_INDICES,PITON_EXTRA_MEMS,PITON_NETWORK_CONFIG)
edge_idx=len(MC_POS)



# generate the tiles
for i in range(PITON_X_TILES):
Expand All @@ -1122,10 +1169,67 @@ module chip(
flatid = i + (j * PITON_X_TILES);
# print template
currenttile = template.replace("tile0", "tile%d" % (flatid));
# special case for core 0
if i == 0 and j == 0:
for k in [1,2,3]:
tmp = edge_sub1 + edge_sub2;
tmp = tmp.replace("endp_DatOut_NN","offchip_out_E_noc%d_data" %k);
tmp = tmp.replace("endp_ValidOut_NN","offchip_out_E_noc%d_valid" %k);
tmp = tmp.replace("endp_YummyOut_NN","offchip_out_E_noc%d_yummy" %k);
tmp = tmp.replace("endp_DatIn_NN","tile_0_0_out_W_noc%d_data" %k);
tmp = tmp.replace("endp_ValidIn_NN","tile_0_0_out_W_noc%d_valid" %k);
tmp = tmp.replace("endp_YummyIn_NN","tile_0_0_out_W_noc%d_yummy" %k);
tmp = tmp.replace("_NN", str(k))
tmp = tmp.replace("ENDP","CHIP_SET_ID");
tmp = tmp.replace("COREIDX", "8'd" + repr(i));
tmp = tmp.replace("COREIDY", "8'd" + repr(j));

edge_assign=edge_assign + tmp;
# place the memory controllers
for k in range(edge_idx):
ax = MC_POS[k]['x']
ay = MC_POS[k]['y']
ap = MC_POS[k]['p']
id = MC_POS[k]['endp']
if(i==ax and j==ay):
currenttile = currenttile.replace("out_%s_noc2_data" % MC_POS[k]['p'], "processor_mcx_noc2_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k);
currenttile = currenttile.replace("out_%s_noc2_valid" % MC_POS[k]['p'], "processor_mcx_noc2_valid[%d]" % k);
currenttile = currenttile.replace("in_%s_noc2_yummy" % MC_POS[k]['p'], "processor_mcx_noc2_yummy[%d]" % k);
currenttile = currenttile.replace("in_%s_noc3_data" % MC_POS[k]['p'], "mcx_processor_noc3_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k);
currenttile = currenttile.replace("in_%s_noc3_valid" % MC_POS[k]['p'], "mcx_processor_noc3_valid[%d]" % k);
currenttile = currenttile.replace("out_%s_noc3_yummy" % MC_POS[k]['p'], "mcx_processor_noc3_yummy[%d]" % k);
tmp = ("//Connect MC %d to enp %d:\n" % (k,id))
tmp = tmp + edge_sub1;
tmp = tmp.replace("ENDP",str(id));
tmp = tmp.replace("COREIDX", "8'd" + repr(i));
tmp = tmp.replace("COREIDY", "8'd" + repr(j));
tmp = tmp.replace("endp_DatOut_NN","mcx_processor_noc3_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k);
tmp = tmp.replace("endp_ValidOut_NN","mcx_processor_noc3_valid[%d]" % k);
tmp = tmp.replace("endp_YummyIn_NN","mcx_processor_noc3_yummy[%d]" % k);
tmp = tmp.replace("_NN", "3");
edge_assign=edge_assign + tmp;
tmp = edge_sub2 ;
tmp = tmp.replace("ENDP",str(id));
tmp = tmp.replace("COREIDX", "8'd" + repr(i));
tmp = tmp.replace("COREIDY", "8'd" + repr(j));
tmp = tmp.replace("endp_DatIn_NN","processor_mcx_noc2_data [%d * `NOC_DATA_WIDTH +: `NOC_DATA_WIDTH]" % k);
tmp = tmp.replace("endp_ValidIn_NN","processor_mcx_noc2_valid[%d]" % k);
tmp = tmp.replace("endp_YummyOut_NN", "processor_mcx_noc2_yummy[%d]" % k);
tmp = tmp.replace("_NN", "2");
edge_assign=edge_assign + tmp;

currenttile = currenttile.replace("COREIDX", "8'd" + repr(i));
currenttile = currenttile.replace("COREIDY", "8'd" + repr(j));
currenttile = currenttile.replace("out_", "tile_%d_%d_out_" % (j,i));
currenttile = currenttile.replace("_FLAT_ID_", repr(flatid));

assign_tmp = sub_assign
assign_tmp = assign_tmp.replace("COREIDX", "8'd" + repr(i));
assign_tmp = assign_tmp.replace("COREIDY", "8'd" + repr(j));
assign_tmp = assign_tmp.replace("_FLAT_ID_", repr(flatid));

assign = assign + assign_tmp;

currenttype = "`SPARC_TILE"

if (PITON_PICO_HET):
Expand Down
2 changes: 1 addition & 1 deletion piton/design/chip/tile/ariane
36 changes: 36 additions & 0 deletions piton/design/chip/tile/ariane_patch/ariane.patch
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
diff --git a/Flist.ariane b/Flist.ariane
--- a/Flist.ariane
+++ b/Flist.ariane
@@ -76,6 +76,8 @@ src/axi_mem_if/src/axi2mem.sv
src/tech_cells_generic/src/pulp_clock_gating.sv
src/tech_cells_generic/src/cluster_clock_inverter.sv
src/tech_cells_generic/src/pulp_clock_mux2.sv
+src/pmp/src/pmp.sv
+src/pmp/src/pmp_entry.sv
src/axi_adapter.sv
src/alu.sv
src/fpu_wrap.sv
@@ -133,8 +135,6 @@ src/riscv-dbg/src/dmi_jtag_tap.sv
src/riscv-dbg/debug_rom/debug_rom.sv
openpiton/ariane_verilog_wrap.sv
openpiton/riscv_peripherals.sv
-openpiton/bootrom/baremetal/bootrom.sv
-openpiton/bootrom/linux/bootrom_linux.sv
src/rv_plic/rtl/rv_plic_target.sv
src/rv_plic/rtl/rv_plic_gateway.sv
src/rv_plic/rtl/plic_regmap.sv
diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv
--- a/src/frontend/frontend.sv
+++ b/src/frontend/frontend.sv
@@ -343,10 +343,8 @@ module frontend #(
icache_data_q <= icache_data;
icache_vaddr_q <= icache_dreq_i.vaddr;
// Map the only three exceptions which can occur in the frontend to a two bit enum
- if (icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin
+ if (icache_dreq_i.ex.valid) begin
icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT;
- end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin
- icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT;
end else icache_ex_valid_q <= ariane_pkg::FE_NONE;
// save the uppermost prediction
btb_q <= btb_prediction[INSTR_PER_FETCH-1];
4 changes: 4 additions & 0 deletions piton/design/chip/tile/ariane_patch/ariane_patch.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@

echo "Patching Ariane submodule..."
cd $ARIANE_ROOT
git apply $DV_ROOT/design/chip/tile/ariane_patch/ariane.patch
3 changes: 3 additions & 0 deletions piton/design/chip/tile/l15/rtl/noc1encoder.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// Modified by Barcelona Supercomputing Center on March 3rd, 2022
/*
Copyright (c) 2015 Princeton University
All rights reserved.
Expand Down Expand Up @@ -436,6 +437,8 @@ begin
msg_options_2[`MSG_CACHE_TYPE_] = msg_cache_type;
msg_options_2[`MSG_SUBLINE_VECTOR_] = msg_subline_vector;

msg_options_3[`MSG_INI_X_] = coreid_x;
msg_options_3[`MSG_INI_Y_] = coreid_y;
msg_options_3[`MSG_SDID_] = req_csm_sdid;
msg_options_3[`MSG_LSID_] = req_csm_lsid;
end
Expand Down
4 changes: 4 additions & 0 deletions piton/design/chip/tile/l15/rtl/noc3encoder.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// Modified by Barcelona Supercomputing Center on March 3rd, 2022
/*
Copyright (c) 2015 Princeton University
All rights reserved.
Expand Down Expand Up @@ -231,6 +232,9 @@ begin
msg_options_2[`MSG_CACHE_TYPE_] = msg_cache_type;
msg_options_2[`MSG_SUBLINE_VECTOR_] = msg_subline_vector;

msg_options_3[`MSG_INI_X_] = coreid_x;
msg_options_3[`MSG_INI_Y_] = coreid_y;

msg_options_4[`MSG_LAST_SUBLINE] = msg_last_subline || (l15_noc3encoder_req_type == `L15_NOC3_REQTYPE_ICACHE_INVAL_ACK);
msg_options_4[`MSG_SUBLINE_ID] = l15_noc3encoder_req_sequenceid;
// does not need to specify cache line state
Expand Down
1 change: 1 addition & 0 deletions piton/design/chip/tile/l2/rtl/Flist.l2
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ l2_config_regs.v
l2_priority_encoder.v
l2_broadcast_counter.v
l2_broadcast_counter_wrap.v
l2_to_mc.v

sram_wrappers/sram_l2_tag.v
sram_wrappers/sram_l2_data.v
Expand Down
1 change: 1 addition & 0 deletions piton/design/chip/tile/l2/rtl/l2.core
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ generate:
[l2_pipe2_dpath.v.pyv, l2_pipe2_dpath.tmp.v],
[l2_priority_encoder.v.pyv, l2_priority_encoder.tmp.v],
[l2_smc.v.pyv, l2_smc.tmp.v],
[l2_to_mc.v.pyv, l2_to_mc.v],
[l2_state.v.pyv, l2_state.tmp.v]]


Expand Down
6 changes: 6 additions & 0 deletions piton/design/chip/tile/l2/rtl/l2.v
Original file line number Diff line number Diff line change
Expand Up @@ -659,6 +659,12 @@ l2_pipe1 pipe1(
.smc_tag_out (smc_tag_out),
`endif

`ifdef PITON_EXTRA_MEMS
.chipid (chipid),
.coreid_x (coreid_x),
.coreid_y (coreid_y),
`endif

.data_clk_en (data_clk_en_p1),
.data_rdw_en (data_rdw_en_p1),
.data_addr (data_addr_p1),
Expand Down
5 changes: 5 additions & 0 deletions piton/design/chip/tile/l2/rtl/l2_decoder.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
// Modified by Barcelona Supercomputing Center on March 3rd, 2022
/*
Copyright (c) 2015 Princeton University
All rights reserved.
Expand Down Expand Up @@ -59,6 +60,8 @@ module l2_decoder(
output reg [`MSG_SRC_CHIPID_WIDTH-1:0] msg_src_chipid,
output reg [`MSG_SRC_X_WIDTH-1:0] msg_src_x,
output reg [`MSG_SRC_Y_WIDTH-1:0] msg_src_y,
output reg [`MSG_SRC_X_WIDTH-1:0] msg_ini_x,
output reg [`MSG_SRC_Y_WIDTH-1:0] msg_ini_y,
output reg [`MSG_SRC_FBITS_WIDTH-1:0] msg_src_fbits,
output reg [`MSG_SDID_WIDTH-1:0] msg_sdid,
output reg [`MSG_LSID_WIDTH-1:0] msg_lsid,
Expand All @@ -81,6 +84,8 @@ begin
msg_src_chipid = msg_header[`MSG_SRC_CHIPID];
msg_src_x = msg_header[`MSG_SRC_X];
msg_src_y = msg_header[`MSG_SRC_Y];
msg_ini_x = msg_header[`MSG_INI_X];
msg_ini_y = msg_header[`MSG_INI_Y];
msg_src_fbits = msg_header[`MSG_SRC_FBITS];
msg_sdid = msg_header[`MSG_SDID];
msg_lsid = msg_header[`MSG_LSID];
Expand Down
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