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[Comgr][hotswap] Add the per-kernel raise context - #3720

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[Comgr][hotswap] Add the per-kernel raise context#3720
ftynse wants to merge 19 commits into
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@ftynse ftynse commented Jul 30, 2026 •
edited by martin-luecke
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Add the per-kernel RaiseContext used by upcoming instruction handlers for operand resolution, register access, wave projection, and kernel layout state.
Register writes now keep EXEC caching, SGPR tracking, pointer provenance, and M0 tracking consistent. The change also handles the high and low halves of VCC and FLAT_SCR correctly and reports unsupported register operands.
Focused tests cover register mapping and state updates.
This PR is stacked on #3869. The following handler PR in this stack adds the production callers.

@ftynse
ftynse requested review from harsh-amd and xintin July 30, 2026 21:11
@github-actions github-actions Bot added comgr Related to Code Object Manager hotswap Related to the Comgr Hotswap feature labels Jul 30, 2026
tgymnich
tgymnich reviewed Aug 3, 2026
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Comment thread amd/comgr/src/hotswap/raiser/raise-context.cpp Outdated
tgymnich
tgymnich reviewed Aug 3, 2026
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Comment thread amd/comgr/src/hotswap/raiser/raise-context.cpp Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.cpp Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.cpp Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
Comment thread amd/comgr/src/hotswap/raiser/raise-context.h Outdated
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ftynse force-pushed the users/ftynse/hotswap-m0-07-layouts branch from 6816886 to 6ce2386 Compare August 5, 2026 11:38
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Base automatically changed from users/ftynse/hotswap-m0-07-layouts to amd-staging August 11, 2026 23:22
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An error occurred while trying to automatically change base from users/mluecke/hotswap-reject-dylib-linkage to amd-staging August 13, 2026 12:55
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@martin-luecke
[Comgr] Select static LLVM components independently
22249e4 
Teach llvm_add_library to preserve both the monolithic LLVM and component-library interfaces when LLVM is configured to link the dylib. A final consumer target property can select the component interface without changing the producer-wide default.

Use this interface for COMGR_STATIC_LLVM and capture COMGR's effective LLVM and Clang linkage before repeated package discovery. This lets the shared COMGR library embed its complete LLVM, Clang, and LLD closure while normal consumers continue using the configured dylibs.

This addresses #2927.
@martin-luecke martin-luecke mentioned this pull request Aug 14, 2026
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ftynse and others added 18 commits August 14, 2026 10:19
@ftynse @claude @martin-luecke
[Comgr][hotswap] Add the per-kernel raise context
ecde01f 
RaiseContext is the mutable state threaded through every instruction handler:
the IRBuilder and module, the register file, the wave projection, the MC state,
the decoded block-to-BasicBlock map, and the operand resolver that turns a
decoded operand into an SSA value or a register write. It ties together the
register file, projection, and layouts from the preceding patches into the
single object the handlers operate on.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
@martin-luecke
[Comgr][hotswap] Use unsigned register widths
e6d53af
@martin-luecke
[Comgr][hotswap] Clean up raise context state types
bbc11ad 
Use optional and unsigned types for register indices, consistently name the MC state, and append SmallVector ranges directly. This removes sentinel values and redundant casts without changing behavior.
@martin-luecke
[Comgr][hotswap] Remove derivable raise context state
27db3ff 
The IRBuilder provides the LLVMContext and canonical scalar types, while the per-kernel function identifies its module. Drop the duplicated fields and derive these values at their use sites.
@martin-luecke
[Comgr][hotswap] Trim raise context comments
8c0ff81
@martin-luecke
[Comgr][hotswap] Propagate operand read failures
0eca235
@martin-luecke
[Comgr][hotswap] Fix raise context register mapping
2c07e85
@martin-luecke
[Comgr][hotswap] Test VCC half writes with dword masks
f45f5e2 
Use an i32 input so the half-write test exercises wave-mask decoding instead of the per-lane i1 shortcut.
@martin-luecke
[Comgr][hotswap] Tighten raise context comments
8d2da02
@martin-luecke
[Comgr][hotswap] Fail closed on register decoding
4eceb3e 
Treat XNACK mask operands as unsupported instead of silently mapping them to zero, and make unknown register classification propagate a structured refusal. Null-register writes remain explicit discard operations.

Size VGPR bank adjustments from the decoded instruction and descriptor rather than a fixed operand limit. Assert decoded operand-shape invariants and cover the new refusal and discard paths directly.
@martin-luecke
[Comgr][hotswap] Keep register write state in RaiseContext
1d03340 
Make RaiseContext update its EXEC cache, SGPR shadows and provenance, and M0 constant state as part of each handler-visible register write. Entry initialization can continue using direct AllocaRegFile stores without installing mutable callbacks.

This removes the register-file callback hooks and covers the coupled state changes through the normal RaiseContext write path.
@martin-luecke
[Comgr][hotswap] Remove redundant raise context state
722cba7 
Obtain the source and target ISA from the wave projection, require the descriptor-derived user-SGPR layout by reference, and drop the unused kernel and lane-cache block fields.

Use the provenance map itself to identify precomputed block state, and leave the handler result type for the handler-dispatch patch that first consumes it.
@martin-luecke
[Comgr][hotswap] Complete raise context refusal handling
ea19dfb 
Reject unsupported architectural registers while parsing both source and destination operands, and invalidate every SGPR shadow touched by an EXEC-width write. Trust the AMDGPU operand tables to identify instructions affected by VGPR-MSB state instead of duplicating their classification.
@martin-luecke
[Comgr][hotswap] Make VGPR adjustment infallible
df51a71 
The AMDGPU operand-role table is authoritative for whether an instruction uses S_SET_VGPR_MSB state. Treat malformed table entries as compiler invariants and remove the unused recoverable-error path.
@martin-luecke
[Comgr][hotswap] Derive register widths from operand classes
1b9c469 
AMDGPU subregister indices include composite ranges and cannot be counted as consecutive dword lanes. Query the active hardware-mode operand register class instead, and refuse decoded registers that the class does not accept.

Add focused coverage for an eight-dword scalar destination, mismatched register classes, and both null-register sink halves.
@martin-luecke
[Comgr][hotswap] Simplify VGPR adjustment sizing
e6f1db2
@martin-luecke
[Comgr][hotswap] Correct raise context state tracking
44280a2 
Preserve kernarg offsets across unrelated loads and keep source-wave shadow validity unchanged for inactive waves. Make RaiseContext own its per-SGPR shadow storage and report AMDGPU encoding formats through structured failures. Add focused coverage for each behavior.
@martin-luecke
[Comgr][hotswap] Fix source-wave mask tracking
c178c32 
Project VCC, EXEC, and zero-predicate reads to the current source wave when the target mask is wider. Keep SGPR shadow pair width in the alloca-backed state so a high-half write invalidates stale pair masks after a block boundary.

Add focused coverage for distinct widened mask halves and cross-block pair invalidation.
@martin-luecke
martin-luecke changed the base branch from amd-staging to users/mluecke/comgr-static-closure-2927 August 14, 2026 10:25
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martin-luecke force-pushed the users/ftynse/hotswap-m0-08-raise-context branch from a081014 to c178c32 Compare August 14, 2026 10:25
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martin-luecke force-pushed the users/mluecke/comgr-static-closure-2927 branch from 22249e4 to 2499e97 Compare August 14, 2026 12:02
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