[pull] master from verilog-to-routing:master #565
+21,821,155
−311,198
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removed
VPR
libarchfpga
lang-python
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libvtrutil
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LibSDCParse was made a sub-tree; however, I have been reviving the LibSDCParse repo. Since updates will be happening on that repo, this should be a submodule.
…submodule [Libs] Turned LibSDCParse into Submodule
[Spelling] Renamed Misspelled "Unknown" and "callibration"
…h_id Remove ipin rr switch
Move node_tilable_track_nums_ to rr_graph_storage and add remove_node
There was an unused build sweeping script in the root of VTR which is going unused. This script has fallen behind the build support of VTR. VTR has moved to using the CI to check for build configurations. Instead of maintaining this script, we can just remove it.
[Infra] Removed Unused Build Script
Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `31ee3be` to `e849735`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](catchorg/Catch2@31ee3be...e849735) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: e849735e11f23ce9ec819e053b107f2ec3c3c1c4 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
…s/libs/EXTERNAL/libcatch2-e849735 Bump libs/EXTERNAL/libcatch2 from `31ee3be` to `e849735`
…h_fix Fix interposer wire drawing
Add Schema ID to RR Graph Formats
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