Important
This repository is archived and no longer maintained.
TAPA has moved to github.com/tuna/tapa, which is the only actively maintained repository. Please use it for the latest code, releases, documentation, issues, and pull requests.
Install the latest release from the new repository:
curl -fsSL https://raw.githubusercontent.com/tuna/tapa/main/install.sh | sh -s -- -qWith root privileges, this installs to /opt/tapa (symlinks in
/usr/local/bin). Without root, it installs to ~/.tapa and updates your
shell PATH.
To install a specific version:
curl -fsSL https://raw.githubusercontent.com/tuna/tapa/main/install.sh \
| TAPA_VERSION=<version> sh -s -- -qSee all releases at github.com/tuna/tapa/releases.
Requirements: Linux (Ubuntu 18.04+, Debian 10+, RHEL 9+, Fedora 34+, Amazon
Linux 2023), g++ 7.5.0+, and the CBC ILP
solver (coinor-cbc on Ubuntu/Debian, coin-or-Cbc on Fedora/EPEL) for
floorplanning. Vitis HLS 2022.1+ is required for RTL synthesis and on-board
execution — not for software simulation.
To build from source instead, clone the new repository and follow its instructions:
git clone https://github.com/tuna/tapa.git
cd tapaTAPA (Task-Parallel) is a powerful framework for designing high-frequency FPGA dataflow accelerators. It combines a powerful C++ API for expressing task-parallel designs with advanced optimization techniques to deliver exceptional design performance and productivity.
- High-Frequency Performance: Achieve 2× higher frequency on average compared to Vivado1.
- Rapid Development: 7× faster compilation and 3× faster software simulation than Vitis HLS2.
- Expressive API: Rich C++ syntax with dedicated APIs for complex memory access patterns and explicit parallelism.
- HBM Optimizations: Automated design space exploration and physical optimizations for HBM FPGAs.
This repository contains the publication version of TAPA accompanying the papers listed below. It is kept for archival and reproducibility purposes only.
Documentation is maintained with the new repository:
- Serpens (DAC'22): 270 MHz on Xilinx Alveo U280 HBM board with 24 HBM channels, while the Vitis HLS baseline failed in routing.
- Sextans (FPGA'22): 260 MHz on Xilinx Alveo U250 board with 4 DDR channels, while the Vivado baseline achieves only 189 MHz.
- SPLAG (FPGA'22): Up to 4.9× speedup over state-of-the-art FPGA accelerators, up to 2.6× speedup over 32-thread CPU running at 4.4 GHz, and up to 0.9× speedup over an A100 GPU.
- AutoSA Systolic-Array Compiler (FPGA'21): Significant frequency improvements over the Vitis HLS baseline.
- KNN (FPT'20): 252 MHz on Xilinx Alveo U280 board, compared to 165 MHz with the Vivado baseline.
- Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs. FPGA, 2021. (Best Paper Award)
- Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong. Extending high-level synthesis for task-Parallel programs. FCCM, 2021.
- Young-kyu Choi, Yuze Chi, Jason Lau, Jason Cong. TARO: Automatic optimization for free-running kernels in FPGA high-level synthesis. TCAD, 2022.
- Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong. RapidStream 2.0: Automated parallel implementation of latency insensitive FPGA designs through partial reconfiguration. TRETS, 2023.
- Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong. TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design. TRETS, 2023.
TAPA is open-source software licensed under the MIT license. For full license details, please refer to the LICENSE file.
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.
Copyright (c) 2020 Yuze Chi and contributors.