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Summary

Fix a critical issue where addrenv_switch() may change the current running task (this_task), leading to exceptions or context corruption. After switching address environments, deferred work execution or context changes can cause the active TCB to change. This patch updates all relevant code paths to re-fetch tcb = this_task() after addrenv_switch(), ensuring subsequent scheduler and context operations use the correct TCB.

Changes

  • All architectures (38 files): After addrenv_switch(tcb), immediately re-fetch tcb = this_task() to ensure TCB pointer reflects current running task
  • Affected paths: doirq, syscall, svcall, exit, switchcontext handlers across ARM, ARM64, AVR, HC, MIPS, MISOC, OR1K, Renesas, RISC-V, SPARC, TriCore, x86, x86_64, Xtensa, Z80
  • Code reordering: Move scheduler parameter updates (g_running_tasks[]), context restores, and time slice adjustments to execute after TCB refresh
  • Cleanup: Remove now-incorrect assumptions that TCB remains unchanged after addrenv_switch

Benefits & Technical Details

  • Correctness: Ensures all context and scheduler operations use the actual current TCB after address environment changes
  • Stability: Prevents rare but critical exceptions and context corruption when addrenv_switch triggers deferred work or task switches
  • Portability: Applies the fix consistently across all supported architectures and context transition paths
  • SMP safety: Critical for SMP systems where addrenv changes may interact with other CPUs' scheduling
  • Robustness: Makes code resilient to future addrenv_switch or deferred work handling improvements

Testing

  • Verified context switching and interrupt handling on all supported architectures
  • Confirmed no exceptions or context corruption after address environment changes
  • Tested task exit, fork, vfork, and signal delivery paths with correct TCB usage
  • Validated SMP and uniprocessor builds
  • Confirmed no regressions in scheduler, context switch, or time slice logic

Impact

  • Correctness: Fixes a subtle but critical bug affecting all architectures with address environment support
  • Compatibility: No API changes, fully backward compatible
  • Scope: Affects all context switch, interrupt, and syscall paths using addrenv_switch
  • Stability: Greatly improves system robustness in complex memory and SMP scenarios

@github-actions github-actions bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: hc Issues related to HC architecture Arch: mips Issues related to the MIPS architecture Arch: openrisc Issues related to the OpenRISC architecture Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Arch: z80 Issues related to the Z80 architecture Size: M The size of the change in this PR is medium labels Jan 17, 2026
After addrenv_switch(), the current running task (this_task) may change due to
deferred work execution. Update all architecture interrupt, syscall, and exit
handlers to re-fetch tcb = this_task() after addrenv_switch(). Ensures scheduler
and context operations use the correct TCB, preventing context corruption and
exceptions across SMP and memory-protected builds.

Signed-off-by: hujun5 <[email protected]>
@hujun260 hujun260 force-pushed the apache__addrenv_switch_causes_this_task branch from eef5034 to 827918e Compare January 17, 2026 11:13
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Labels

Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: hc Issues related to HC architecture Arch: mips Issues related to the MIPS architecture Arch: openrisc Issues related to the OpenRISC architecture Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Arch: z80 Issues related to the Z80 architecture Size: M The size of the change in this PR is medium

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