Windows 11, using latest version of Verilator and extension, both build from git today.
Test modules are:
top.v
module top(
input wire test1,
input wire [31:0] test2
);
submodule my_submodule(
.test_input(1'b0),
.test_output(test2),
.non_existing_input(1'b0)
);
endmodule
submodule.v
module submodule
(
input wire [23:0] test_input, // test input comment
output reg [7:0] test_output // test output comment
);
endmodule
Verilator output is:
%Error-PINNOTFOUND: C:\tmp\vscode_verilog_testenvs\verilator/sources\top.v:9:4: Pin not found: 'non_existing_input'
9 | .non_existing_input(1'b0)
| ^~~~~~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/PINNOTFOUND?v=0.000
%Error-ASSIGNIN: C:\tmp\vscode_verilog_testenvs\verilator/sources\top.v:8:16: Assigning to input/const variable: 'test2'
8 | .test_output(test2),
| ^~~~~
%Error: Exiting due to 2 error(s)
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
Which leads to no problems being detected.
From what I've deduced from using a regex debugger, the issue comes from file line being included with column name and general mismatch between match groups in regex and sections
Adding regex to match Verilog and SystemVerilog file extensions and fixing group indexes so that problem matcher objects are as listed below, seems to fix the issue.
package.json
{
"name": "verilator-error",
"owner": "Verilator",
"source": "systemverilog",
"severity": "error",
"fileLocation": "autoDetect",
"pattern": [
{
"regexp": "%Error(-[A-Z0-9]+)?: ((\\S+((\\.sv)|(\\.v))):(\\d+):((\\d+):)? )?(.*)$",
"severity": 1,
"file": 3,
"line": 7,
"column": 9,
"message": 10
}
]
},
{
"name": "verilator-warning",
"owner": "Verilator",
"source": "systemverilog",
"severity": "warning",
"fileLocation": "autoDetect",
"pattern": [
{
"regexp": "%Warning(-[A-Z0-9]+)?: ((\\S+((\\.sv)|(\\.v))):(\\d+):((\\d+):)? )?(.*)$",
"severity": 1,
"file": 3,
"line": 7,
"column": 9,
"message": 10
}
]
},
Windows 11, using latest version of Verilator and extension, both build from git today.
Test modules are:
top.v
submodule.v
Verilator output is:
Which leads to no problems being detected.
From what I've deduced from using a regex debugger, the issue comes from file line being included with column name and general mismatch between match groups in regex and sections
Adding regex to match Verilog and SystemVerilog file extensions and fixing group indexes so that problem matcher objects are as listed below, seems to fix the issue.
package.json