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[Ascend] Fix tl.sum over an i1 mask returning 1 instead of the count - #1402

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zhzhcookie merged 1 commit into
flagos-ai:triton_v3.5.xfrom
togepro:issue1220
Oct 21, 2026
Merged

zhzhcookie merged 1 commit into
flagos-ai:triton_v3.5.xfrom
togepro:issue1220

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@togepro togepro commented Oct 19, 2026

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Summary

tl.sum over an i1 mask only ever returns 0 or 1: 1 if any lane is set, 0 if none. The actual count is lost. No error, no warning, just silently wrong results at runtime.

Upstream Triton is unaffected because _pick_sum_dtype promotes first. int1 has a bit width of 1 and is classified in UINT_TYPES, so upstream picks uint32 and accumulates there. The Ascend spec override has that promotion commented out, from the triton 3.5 sync commit 8c30adb6c9; the comment only claims it is not needed and gives no reason. cumsum in the same file kept its promotion call, and that inconsistency is itself the clue.

Changes

  • Restore _pick_sum_dtype and promotes i1 to int32 and nothing else.
  • Only i1 is promoted. int8/int16 keep the native width Ascend already uses.

After the fix the extui moves ahead of the reduce and the accumulation happens in i32.

Related

  • Issues in triton-ascend with the same problem( issue446).

Comment thread python/setup_tools/utils/__init__.py Outdated
Comment thread python/setup_tools/utils/__init__.py
`a + b` on i1 is a 1-bit add, which is a logical or, so any non-zero
number of set lanes saturates to 1. The extui after the reduce cannot
recover the count.

Restore the promotion for i1 only, leaving int8/int16 at their native
width.

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LGTM

@zhzhcookie
zhzhcookie merged commit df9531a into flagos-ai:triton_v3.5.x Oct 21, 2026
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@togepro
togepro deleted the issue1220 branch October 21, 2026 09:31
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3 participants