feat(codegen): codegen support for system.bar_{all,v,m}

[Shenggan]

Summary

This PR adds PTO codegen support for the sync ops below:

• system.bar_all -> pto.barrier <PIPE_ALL>
• system.bar_v -> pto.barrier <PIPE_V>
• system.bar_m -> pto.barrier <PIPE_M>

It also adds unit tests to verify the emitted MLIR and updates the IR operator docs to describe the exact PTO lowering.

Motivation

system.bar_all, system.bar_v, and system.bar_m are already exposed at the IR / Python API level, but PTO backend codegen did not yet register these ops.

This change closes that gap so these sync ops lower cleanly during PTO codegen and have explicit test coverage.

Changes

• register system.bar_all, system.bar_v, and system.bar_m in PTO backend codegen
• lower them to:
  • pto.barrier <PIPE_ALL>
  • pto.barrier <PIPE_V>
  • pto.barrier <PIPE_M>
• add codegen unit tests for all three barrier ops
• update English and Chinese IR operator docs with the exact lowering forms

Testing

Added unit tests covering:

• pl.system.bar_all() emits pto.barrier <PIPE_ALL>
• pl.system.bar_v() emits pto.barrier <PIPE_V>
• pl.system.bar_m() emits pto.barrier <PIPE_M>

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📝 Walkthrough

Walkthrough

The change adds PTO code generation for system.bar_all, system.bar_v, and system.bar_m. Tests verify their pipeline scopes. English and Chinese IR documentation now describe the lowering targets.

Changes

PTO barrier lowering

Layer / File(s)	Summary
Register and validate barrier lowering src/backend/common/pto_ops_memory.cpp, tests/ut/codegen/test_pto_codegen_ops.py, docs/en/dev/ir/05-operators.md, docs/zh/dev/ir/05-operators.md	The backend registers no-argument barriers for PIPE_ALL, PIPE_V, and PIPE_M. Code-generation tests verify the emitted MLIR. Both documentation files describe the corresponding PTO barriers.

Estimated code review effort: 2 (Simple) | ~10 minutes

Possibly related PRs

• hw-native-sys/pypto#2018: Extends related memory operation registration and PTO code-generation tests.
• hw-native-sys/pypto#2091: Modifies shared PTO synchronization code and documentation.
• hw-native-sys/pypto#2168: Updates RegisterMemoryOps and its PTO code-generation tests.

Poem

A rabbit hops through barriers three,
PIPE_ALL, PIPE_V, PIPE_M with glee.
The MLIR marks each proper lane,
Tests check the paths again and again.
Docs now tell the tale clearly.

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly summarizes the main change: PTO codegen support for the three system barrier operations.
Description check	✅ Passed	The description directly explains the codegen changes, lowering targets, tests, and documentation updates.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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[chatgpt-codex-connector]

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[chatgpt-codex-connector]

Set core affinity for pipe-specific barriers

When these newly lowered ops appear in mixed InCore kernels, the split pass still sees system.bar_v/system.bar_m as no-arg ops with no explicit IR core affinity, so ClassifyCallAffinity falls through to SHARED and BuildCoreBody keeps the statement on both AIC and AIV lanes. That means pl.system.bar_m() can emit pto.barrier <PIPE_M> in the AIV function, and pl.system.bar_v() can be duplicated into the AIC function; set the IR op entries to CoreAffinity::VECTOR/CoreAffinity::CUBE (or classify them specially) before exposing the PTO lowering.

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