This repository is part of a family of open-source RV32 cores targeting different cost/performance points:
| Core | Pipeline | ISA | Target | Status |
|---|---|---|---|---|
| JV32 | 3-stage, single-issue | RV32IMAC + B (Zba/Zbb/Zbs) |
Low-cost embedded processors | This repo — WIP |
| KV32 | 5-stage, dual-issue | RV32IMAC + B + F/D (floating-point) | General-purpose processor | In development |
| LV32 | 8-stage, dual-issue | RV32GC + Linux-capable MMU | Linux-capable application processor | In planning |
JV32 is a compact RV32IMAC RISC-V system-on-chip for RTL simulation, software bring-up, and ASIC/FPGA experimentation. The project includes a 3-stage in-order core, tightly-coupled memories, AXI peripherals, JTAG debug support, verification flows, and an OpenRAM/OpenLane-based synthesis path.
WIP