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Pull requests list

[Comb] Add canonicalization for comb.truth_table
#9214 opened Nov 8, 2025 by MrRoy09 Loading…
[Arcilator] Move pipeline into separate library.
#9213 opened Nov 8, 2025 by SimonEbner Loading…
[Arcilator] Timing scopes for JIT
#9210 opened Nov 7, 2025 by SimonEbner Loading…
[circt-verilog] Move pipeline into ImportVerilog.
#9208 opened Nov 7, 2025 by SimonEbner Loading…
[RTG] Add ImplicitConstraintOpInterface RTG Involving the `rtg` dialect
#9205 opened Nov 7, 2025 by maerhart Loading…
[RTG] Add folders for most set operations RTG Involving the `rtg` dialect
#9190 opened Nov 5, 2025 by maerhart Loading…
[Comb] Canonicalize power-of-two unsigned div/mod.
#9177 opened Nov 3, 2025 by uenoku Loading…
[ESI] Add missing ensureValid calls
#9137 opened Oct 24, 2025 by mortbopet Loading…
[FIRRTL] Domain inference
#9106 opened Oct 17, 2025 by rwy7 Draft
[ESI] Add serde support for wide integers
#9091 opened Oct 14, 2025 by mortbopet Loading…
No custom printer for CompReg - leading to loss of quotation marks Resolves #8833 bug Something isn't working Seq Involving the `seq` dialect
#9049 opened Oct 4, 2025 by KaiS987 Loading…
fix: corner cases in aggregate generation
#9036 opened Sep 30, 2025 by tianrui-wei Loading…
[DoNotMerge] Add signal trace capability to arcilator Arc Involving the `arc` dialect
#8986 opened Sep 18, 2025 by fzi-hielscher Draft
[ESI] Throw exceptions on invalid deserialization
#8914 opened Sep 2, 2025 by mortbopet Loading…
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