[RISCV] Change RISCVABI::computeTargetABI() to return Expected<ABI> - #213410
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@llvm/pr-subscribers-lld @llvm/pr-subscribers-backend-risc-v Author: Alexander Richardson (arichardson) ChangesReturn Expected<ABI> instead of printing to errs()/reportFatalUsageError This change was created with the help of AI tools Patch is 28.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213410.diff 10 Files Affected:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 8563f678464a6..591ea72d5e857 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -330,28 +330,22 @@ class RISCVAsmParser : public MCTargetAsmParser {
Parser.addAliasForDirective(".dword", ".8byte");
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
- auto ABIName = StringRef(getTargetOptions().ABIName);
- if (ABIName.ends_with("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
- errs() << "Hard-float 'f' ABI can't be used for a target that "
- "doesn't support the F instruction set extension (ignoring "
- "target-abi)\n";
- } else if (ABIName.ends_with("d") &&
- !getSTI().hasFeature(RISCV::FeatureStdExtD)) {
- errs() << "Hard-float 'd' ABI can't be used for a target that "
- "doesn't support the D instruction set extension (ignoring "
- "target-abi)\n";
- }
-
- // Use computeTargetABI to check if ABIName is valid. If invalid, output
- // error message.
- RISCVABI::computeTargetABI(STI, ABIName);
-
const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo();
ParserOptions.IsPicEnabled = MOFI->isPositionIndependent();
if (AddBuildAttributes)
getTargetStreamer().emitTargetAttributes(STI, /*EmitStackAlign*/ false);
}
+
+ // Validate the requested -target-abi now that the lexer has been primed
+ // with the first token, so diagnostics can be reported with a real source
+ // location instead of being printed with no location information.
+ void onBeginOfFile() override {
+ Expected<RISCVABI::ABI> ABIOrErr =
+ RISCVABI::computeTargetABI(getSTI(), getTargetOptions().ABIName);
+ if (!ABIOrErr)
+ getParser().printError(getLoc(), toString(ABIOrErr.takeError()));
+ }
};
/// RISCVOperand - Instances of this class represent a parsed machine
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 7753a0d118eef..110dce5e3e928 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -53,7 +53,7 @@ namespace RISCV {
} // namespace RISCV
namespace RISCVABI {
-ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
+Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
const Triple &TT = STI.getTargetTriple();
const FeatureBitset &FeatureBits = STI.getFeatureBits();
auto TargetABI = getTargetABI(ABIName);
@@ -62,37 +62,43 @@ ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
bool IsXCheriot = FeatureBits[RISCV::FeatureVendorXCheriot];
if (!ABIName.empty() && TargetABI == ABI_Unknown) {
- errs()
- << "'" << ABIName
- << "' is not a recognized ABI for this target (ignoring target-abi)\n";
- } else if (ABIName.starts_with("ilp32") && IsRV64) {
- errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
- "target-abi)\n";
- TargetABI = ABI_Unknown;
- } else if (ABIName.starts_with("lp64") && !IsRV64) {
- errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
- "target-abi)\n";
- TargetABI = ABI_Unknown;
- } else if (!IsRV64 && IsRVE && !IsXCheriot && TargetABI != ABI_ILP32E &&
- TargetABI != ABI_Unknown) {
- // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
- errs()
- << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
- TargetABI = ABI_Unknown;
- } else if (!IsRV64 && IsRVE && IsXCheriot && TargetABI != ABI_CHERIOT &&
- TargetABI != ABI_Unknown) {
- errs() << "Only the cheriot ABI is supported for XCheriot (ignoring "
- "target-abi)\n";
- TargetABI = ABI_Unknown;
- } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
- TargetABI != ABI_Unknown) {
- // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
- errs()
- << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
- TargetABI = ABI_Unknown;
+ return createStringError(Twine("'") + ABIName +
+ "' is not a recognized ABI for this target");
+ }
+ if (ABIName.starts_with("ilp32") && IsRV64) {
+ return createStringError(
+ "32-bit ABIs are not supported for 64-bit targets");
+ }
+ if (ABIName.starts_with("lp64") && !IsRV64) {
+ return createStringError(
+ "64-bit ABIs are not supported for 32-bit targets");
+ }
+ if (ABIName.ends_with("f") && !FeatureBits[RISCV::FeatureStdExtF]) {
+ return createStringError(
+ "hard-float 'f' ABI can't be used for a target that doesn't "
+ "support the F instruction set extension");
+ }
+ if (ABIName.ends_with("d") && !FeatureBits[RISCV::FeatureStdExtD]) {
+ return createStringError(
+ "hard-float 'd' ABI can't be used for a target that doesn't "
+ "support the D instruction set extension");
+ }
+ if (!IsRV64 && IsRVE && !IsXCheriot && TargetABI != ABI_ILP32E &&
+ TargetABI != ABI_Unknown) {
+ return createStringError("only the ilp32e ABI is supported for RV32E");
+ }
+ if (!IsRV64 && IsRVE && IsXCheriot && TargetABI != ABI_CHERIOT &&
+ TargetABI != ABI_Unknown) {
+ return createStringError(
+ "only the cheriot ABI is supported for XCheriot");
+ }
+ if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
+ TargetABI != ABI_Unknown) {
+ return createStringError("only the lp64e ABI is supported for RV64E");
}
- if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
+ // Unconditionally fatal: no sensible default ABI to fall back to here.
+ if ((TargetABI == ABI_ILP32E ||
(TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
FeatureBits[RISCV::FeatureStdExtD])
reportFatalUsageError("ILP32E cannot be used with the D ISA extension");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index e54d57d9f4451..a34db0fda3c9b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -20,6 +20,7 @@
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/StringTable.h"
#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Support/Error.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/SubtargetFeature.h"
@@ -733,8 +734,8 @@ enum ABI {
};
// Returns the target ABI, or else a StringError if the requested ABIName is
-// not supported for the subtargets triple and FeatureBits combination.
-ABI computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName);
+// not supported for the subtarget's triple and FeatureBits combination.
+Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName);
ABI getTargetABI(StringRef ABIName);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 032a6a014436a..9fb15105a9056 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -21,6 +21,7 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -30,8 +31,15 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
: RISCVTargetStreamer(S), CurrentVendor("riscv") {
MCAssembler &MCA = getStreamer().getAssembler();
auto &MAB = static_cast<RISCVAsmBackend &>(MCA.getBackend());
- setTargetABI(
- RISCVABI::computeTargetABI(STI, MAB.getTargetOptions().getABIName()));
+ // See RISCVSubtarget::initializeSubtargetDependencies: can't be fatal.
+ auto ABIOrErr =
+ RISCVABI::computeTargetABI(STI, MAB.getTargetOptions().getABIName());
+ if (ABIOrErr) {
+ setTargetABI(*ABIOrErr);
+ } else {
+ errs() << toString(ABIOrErr.takeError()) << " (ignoring target-abi)\n";
+ setTargetABI(cantFail(RISCVABI::computeTargetABI(STI, "")));
+ }
setFlagsFromFeatures(STI);
// Compute the initial ISA string. This serves two purposes:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index aad62e7d40c54..92fc27c33c0d2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -137,20 +137,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
-
- if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
- !Subtarget.hasStdExtF()) {
- errs() << "Hard-float 'f' ABI can't be used for a target that "
- "doesn't support the F instruction set extension (ignoring "
- "target-abi)\n";
- ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
- } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&
- !Subtarget.hasStdExtD()) {
- errs() << "Hard-float 'd' ABI can't be used for a target that "
- "doesn't support the D instruction set extension (ignoring "
- "target-abi)\n";
- ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
- }
+ // Hard-float ABIs that don't match the F/D extensions are already rejected
+ // by RISCVABI::computeTargetABI() when the subtarget is constructed.
+ assert(((ABI != RISCVABI::ABI_ILP32F && ABI != RISCVABI::ABI_LP64F) ||
+ Subtarget.hasStdExtF()) &&
+ "F ABI without F extension");
+ assert(((ABI != RISCVABI::ABI_ILP32D && ABI != RISCVABI::ABI_LP64D) ||
+ Subtarget.hasStdExtD()) &&
+ "D ABI without D extension");
switch (ABI) {
default:
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index b807534e986c1..e112213742bfd 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -25,6 +25,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -117,7 +118,15 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
HasStdExtC = hasFeature(RISCV::FeatureStdExtC);
HasStdExtZce = hasFeature(RISCV::FeatureStdExtZce);
- TargetABI = RISCVABI::computeTargetABI(*this, ABIName);
+ // Can't be fatal: per-function subtargets mean this one may just be the
+ // module-level default with no matching function, e.g. -target-abi ilp32f
+ // with no global -mattr=+f but all functions have their own "+f" attribute.
+ if (auto ABIOrErr = RISCVABI::computeTargetABI(*this, ABIName)) {
+ TargetABI = *ABIOrErr;
+ } else {
+ errs() << toString(ABIOrErr.takeError()) << " (ignoring target-abi)\n";
+ TargetABI = cantFail(RISCVABI::computeTargetABI(*this, ""));
+ }
RISCVFeatures::validate(TT, getFeatureBits());
return *this;
}
diff --git a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
index 5893ae275e3b1..e7bab947b3507 100644
--- a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
+++ b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
@@ -5,7 +5,7 @@
; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s
-; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension
+; RV32I-ILP32F-FAILED: hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension
define float @foo(i32 %a) nounwind #0 {
diff --git a/llvm/test/CodeGen/RISCV/target-abi-invalid.ll b/llvm/test/CodeGen/RISCV/target-abi-invalid.ll
index 41c08f1f19d19..e383a16dcb345 100644
--- a/llvm/test/CodeGen/RISCV/target-abi-invalid.ll
+++ b/llvm/test/CodeGen/RISCV/target-abi-invalid.ll
@@ -36,8 +36,8 @@
; RUN: llc -mtriple=riscv64 -target-abi lp64f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV64I-LP64F %s
-; RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
-; RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+; RV32I-ILP32F: hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
+; RV64I-LP64F: hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
; RUN: llc -mtriple=riscv32 -target-abi ilp32d < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32I-ILP32D %s
@@ -48,10 +48,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64d < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV64IF-LP64D %s
-; RV32I-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
-; RV32IF-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
-; RV64I-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
-; RV64IF-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV32I-ILP32D: hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV32IF-ILP32D: hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV64I-LP64D: hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
+; RV64IF-LP64D: hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
define void @nothing() nounwind {
ret void
diff --git a/llvm/test/MC/RISCV/target-abi-invalid.s b/llvm/test/MC/RISCV/target-abi-invalid.s
index 35b42a88618b7..06df035a6176a 100644
--- a/llvm/test/MC/RISCV/target-abi-invalid.s
+++ b/llvm/test/MC/RISCV/target-abi-invalid.s
@@ -1,107 +1,109 @@
-# RUN: llvm-mc -triple=riscv32 -target-abi foo < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -target-abi foo < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32I-FOO %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32foof < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+f -target-abi ilp32foof < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32IF-ILP32FOOF %s
-# RV32I-FOO: 'foo' is not a recognized ABI for this target (ignoring target-abi)
-# RV32IF-ILP32FOOF: 'ilp32foof' is not a recognized ABI for this target (ignoring target-abi)
+# RV32I-FOO: <stdin>:1:1: error: 'foo' is not a recognized ABI for this target
+# RV32IF-ILP32FOOF: <stdin>:1:1: error: 'ilp32foof' is not a recognized ABI for this target
-# RUN: llvm-mc -triple=riscv64 -target-abi ilp32 < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -target-abi ilp32 < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV64I-ILP32 %s
-# RUN: llvm-mc -triple=riscv64 -mattr=+f -target-abi ilp32f < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -mattr=+f -target-abi ilp32f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV64IF-ILP32F %s
-# RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi ilp32d < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -mattr=+d -target-abi ilp32d < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV64IFD-ILP32D %s
-# RUN: llvm-mc -triple=riscv64 -target-abi ilp32e < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -target-abi ilp32e < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV64I-ILP32E %s
-# RV64I-ILP32: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
-# RV64IF-ILP32F: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
-# RV64IFD-ILP32D: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
-# RV64I-ILP32E: 32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)
+# RV64I-ILP32: <stdin>:1:1: error: 32-bit ABIs are not supported for 64-bit targets
+# RV64IF-ILP32F: <stdin>:1:1: error: 32-bit ABIs are not supported for 64-bit targets
+# RV64IFD-ILP32D: <stdin>:1:1: error: 32-bit ABIs are not supported for 64-bit targets
+# RV64I-ILP32E: <stdin>:1:1: error: 32-bit ABIs are not supported for 64-bit targets
-# RUN: llvm-mc -triple=riscv32 -target-abi lp64 < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -target-abi lp64 < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32I-LP64 %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32IF-LP64F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32IFD-LP64D %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64 < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64 < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32E-LP64 %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EF-LP64F %s
-# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64d < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32EFD-LP64D %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32E-LP64E %s
-# RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32E-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32E-LP64E: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EFD-LP64D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
+# RV32I-LP64: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32IF-LP64F: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32IFD-LP64D: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32E-LP64: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32EF-LP64F: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32EFD-LP64D: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
+# RV32E-LP64E: <stdin>:1:1: error: 64-bit ABIs are not supported for 32-bit targets
-# RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
+# An explicit ABI that matches the RVE requirement (so it isn't rejected by earlier checks)
+# RUN: not llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32e < %s 2>&1 \
+# RUN: | FileCheck -check-prefix=RV32E-ILP32E-D %s
+# RV32E-ILP32E-D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
+
+# RUN: not llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32I-ILP32F %s
-# RUN: llvm-mc -triple=riscv64 -target-abi lp64f < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -target-abi lp64f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV64I-LP64F %s
-# RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
-# RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that do...
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✅ With the latest revision this PR passed the C/C++ code formatter. |
arichardson
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arichardson
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Created using spr 1.3.8-beta.1-arichardson
topperc
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Created using spr 1.3.8-beta.1-arichardson
Created using spr 1.3.8-beta.1-arichardson
Created using spr 1.3.8-beta.1-arichardson [skip ci]
…avoid duplicate message Created using spr 1.3.8-beta.1-arichardson
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Created using spr 1.3.8-beta.1-arichardson
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No change intended here, just adding this test coverage to show that llvm/llvm-project#213410 does not change it. Pull Request: llvm/llvm-project#214079
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No change intended here, just adding this test coverage to show that llvm/llvm-project#213410 does not change it. Pull Request: llvm/llvm-project#214079
Created using spr 1.3.8-beta.1-arichardson [skip ci]
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🪟 Windows x64 Test Results
All executed tests passed, but another part of the build failed. Click on a failure below to see the details. [code=1] tools/clang/lib/Options/CMakeFiles/obj.clangOptions.dir/DriverOptions.cpp.objIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
Created using spr 1.3.8-beta.1-arichardson [skip ci]
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…cted<ABI> Return Expected<ABI> instead of printing to errs()/reportFatalUsageError internally, so callers decide whether to fall back to the default ABI or treat the failure as fatal, and so it's unit-testable. Also fold the duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest coverage for the error paths. This change was created with the help of AI tools Reviewed By: lenary Pull Request: llvm/llvm-project#213410
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…cted<ABI> Return Expected<ABI> instead of printing to errs()/reportFatalUsageError internally, so callers decide whether to fall back to the default ABI or treat the failure as fatal, and so it's unit-testable. Also fold the duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest coverage for the error paths. This change was created with the help of AI tools Reviewed By: lenary Pull Request: llvm/llvm-project#213410
Contributor
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This change over the weekend broke riscv64 Android builds. When compiling for riscv64-linux-android with -flto, any module-level inline assembly causes LTO linking (ld.lld) to fail with: Minimal Reproducer Command: Can you fix this issue for LTO or revert the change? |
Member
Author
Thanks for the repro. |
Contributor
I am good to wait till tomorrow for a fix. |
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One thing that's strange is that module-level inline assembly now does contain |
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Author
|
I had hoped that #214079 would be sufficient coverage, but I didn't include any module global assembly there so that's why I did't see it. Working on a minimal fix for this right now. |
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|
#223606 should be a hopefully minimal fix for this. Missing propagation of target features with LTO has been a long running issue, and there is probably something cleaner that can be done but I think for now this restores the existing behaviour while keeping the new diagnostics for llvm-mc. |
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Return Expected<ABI> instead of printing to errs()/reportFatalUsageError internally, so callers decide whether to fall back to the default ABI or treat the failure as fatal, and so it's unit-testable. Also fold the duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest coverage for the error paths. This change was created with the help of AI tools Reviewed By: lenary Pull Request: llvm#213410
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…d by streamer Commit 105ff16 (llvm#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools
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cc @llvm/android-maintainers |
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Return Expected<ABI> instead of printing to errs()/reportFatalUsageError internally, so callers decide whether to fall back to the default ABI or treat the failure as fatal, and so it's unit-testable. Also fold the duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest coverage for the error paths. This change was created with the help of AI tools Reviewed By: lenary Pull Request: llvm#213410
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…d by streamer (#223606) Commit 105ff16 (#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools
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…ady resolved by streamer (#223606) Commit 105ff16 (llvm/llvm-project#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools
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…ady resolved by streamer (#223606) Commit 105ff16 (llvm/llvm-project#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools
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…d by streamer (llvm#223606) Commit 105ff16 (llvm#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools
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Sep 20, 2026
…d by streamer (#223606) Commit 0ba30f2 (llvm/llvm-project#213410) changed RISCVABI::computeTargetABI() to return Expected<ABI> and added validation to RISCVAsmParser::onBeginOfFile() to report invalid -target-abi flags with real source location in llvm-mc. However, this broke LTO builds containing inline assembly (e.g. Android riscv64 builds and downstream Rust in rust-lang/rust#162783). During LTO, LLD sets TargetOptions.MCOptions.ABIName from the module's target-abi metadata ("lp64d"), while the linker's default TargetMachine subtarget lacks "+d" (individual functions specify "+d" in target-features). RISCVSubtarget handles this gracefully by emitting a diagnostic note and falling back to lp64 for code generation. When inline assembly was subsequently parsed, AsmPrinter::emitInlineAsm instantiated RISCVAsmParser with a subtarget lacking "+d", causing onBeginOfFile() to re-validate TargetOptions.ABIName and fail with a fatal error. To fix this, skip the parser validation whenever the streamer has already resolved an ABI. This preserves llvm-mc diagnostics on invalid command-line flags while avoiding conflicting validation when assembling inline asm during code generation. This commit was created with the help of AI tools Signed-off-by: Hafidz Muzakky <ais.muzakky@gmail.com>
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Return Expected instead of printing to errs()/reportFatalUsageError
internally, so callers decide whether to fall back to the default ABI
or treat the failure as fatal, and so it's unit-testable. Also fold the
duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and
RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest
coverage for the error paths.
This change was created with the help of AI tools