feat: add Verilator simulation tool support

[martin-velay]

Summary

Add Verilator as a DVSim simulation tool.

The new tool plugin:

• recognizes release and development Verilator version banners;
• extracts build and simulation wall time from Verilator's log footers;
• extracts simulated time from Verilator or UVM log output;
• parses verilator_coverage --report summary, including line, toggle, branch,
  expression, FSM, and user coverage; and
• maps those metrics to DVSim's coverage model.

The registration change is kept in a separate commit from the plugin and its
tests, which should make the generic tool-discovery change easy to review.

This is the DVSim dependency for
lowRISC/opentitan-embargoed-peppermint#163.

Validation

• ruff format --check src tests
• ruff check --config=ruff-ci.toml src tests
• pyright --pythonpath .venv/bin/python src/dvsim/sim/tool/verilator.py src/dvsim/tool/utils.py
• pytest --strict -q tests/tool/test_verilator.py tests/tool/test_utils.py
  (29 passed)
• Checked against Peppermint's real Verilator output: build wall time
  442.667 s, run wall time 20.321 s, and simulated time 545 us are
  extracted correctly.
• Exercised through Peppermint's generic DVSim --waves fst path: the
  wave-enabled Verilator build and chip_soc_mbx_ahb_smoke passed and produced
  a 2.8 MiB waves.fst. FST and VCD selection remain project configuration,
  using DVSim's existing {waves} substitution and waves build mode.

The full local suite reached 425 passing tests. Four Git tests are not runnable
in this workspace because its /tmp/.git sandbox marker changes repository
detection. The local-backend long-line stress test timed out under the full-suite
load, but passes when run by itself.