#2475 makes the Zcmp encodings (cm.push, cm.pop, cm.popret(z), cm.mvsa01, cm.mva01s) illegal when cheriot_enable_i == IbexMuBiOn, because their expansions are incompatible with CHERIoT: cm_sp_addi() expands to addi x2, x2, imm, which writes a NULL capability and so destroys csp's tag and bounds; the register saves/restores use sw/lw, so cra's backward sentry is lost and the jalr x0, 0(x1) from cm_ret_ra() then takes a tag violation.
Trapping is the safe interim behaviour, but it means the opentitan config carries Zcmp hardware that is unusable in CHERIoT mode. The open question is whether to support Zcmp properly or declare it permanently incompatible.
The blocker for supporting it is the stack stride: Zcmp adjusts sp by 4 bytes per register, while capabilities need 8. The CHERIoT spec says nothing about Zcmp; CHERI-RISC-V declares it incompatible and defines its own unratified variant.
To decide:
- whether an 8-byte-stride CHERIoT variant is worth defining, and whether it should follow the CHERI-RISC-V proposal
- if not, whether Zcmp should be disallowed at elaboration time for
BaseIsaRV32IorCHERIoT rather than trapped at runtime
@SamuelRiedel has a copy of the RTL using an 8-byte stack element. Context: #2475 (comment)
#2475 makes the Zcmp encodings (
cm.push,cm.pop,cm.popret(z),cm.mvsa01,cm.mva01s) illegal whencheriot_enable_i == IbexMuBiOn, because their expansions are incompatible with CHERIoT:cm_sp_addi()expands toaddi x2, x2, imm, which writes a NULL capability and so destroyscsp's tag and bounds; the register saves/restores usesw/lw, socra's backward sentry is lost and thejalr x0, 0(x1)fromcm_ret_ra()then takes a tag violation.Trapping is the safe interim behaviour, but it means the
opentitanconfig carries Zcmp hardware that is unusable in CHERIoT mode. The open question is whether to support Zcmp properly or declare it permanently incompatible.The blocker for supporting it is the stack stride: Zcmp adjusts
spby 4 bytes per register, while capabilities need 8. The CHERIoT spec says nothing about Zcmp; CHERI-RISC-V declares it incompatible and defines its own unratified variant.To decide:
BaseIsaRV32IorCHERIoTrather than trapped at runtime@SamuelRiedel has a copy of the RTL using an 8-byte stack element. Context: #2475 (comment)