Vendor in latest OpenTitan IPs

check_tool_requirements.core

@@ -7,9 +7,10 @@ description: "Check tool requirements"
 
 filesets:
   files_check_tool_requirements:
+    file_type: user
     files:
-      - ./util/check_tool_requirements.py : { copyto: util/check_tool_requirements.py }
-      - ./tool_requirements.py : { copyto: tool_requirements.py }
+      - util/check_tool_requirements.py : { copyto: util/check_tool_requirements.py }
+      - util/tool_requirements.py : { copyto: util/tool_requirements.py }
 
 scripts:
   check_tool_requirements:

dv/cs_registers/tb_cs_registers.core

@@ -56,7 +56,7 @@ scripts:
     cmd:
       - make
       - -C
-      - ../src/lowrisc_ibex_tb_cs_registers_0
+      - src/lowrisc_ibex_tb_cs_registers_0
 
 parameters:
   PMPEnable:
@@ -106,13 +106,13 @@ targets:
       vcs:
         vcs_options:
           - '-xlrm uniq_prior_final'
-          - '../src/lowrisc_ibex_tb_cs_registers_0/build/bin/reg_dpi.so'
+          - 'src/lowrisc_ibex_tb_cs_registers_0/build/bin/reg_dpi.so'
           - '-debug_access+all'
 
       verilator:
         mode: cc
         libs:
-          - '../src/lowrisc_ibex_tb_cs_registers_0/build/bin/reg_dpi.so'
+          - 'src/lowrisc_ibex_tb_cs_registers_0/build/bin/reg_dpi.so'
         verilator_options:
           # Disabling tracing reduces compile times but doesn't have a
           # huge influence on runtime performance.

dv/formal/build_all.ys

@@ -5,7 +5,7 @@
 
 # Parse and lower the Ibex and specification RTL. LOWRISC_SAIL_SRC is replaced in Makefile.
 read_slang --top top -DSYNTHESIS -DYOSYS \
-	-F build/fusesoc/default-vcs/lowrisc_ibex_ibex_formal_0.1.scr \
+	-F build/fusesoc/lowrisc_ibex_ibex_formal_0.1/default-vcs/lowrisc_ibex_ibex_formal_0.1.scr \
 	build/ibexspec.sv spec/stub.sv spec/spec_api.sv check/peek/alt_lsu.sv check/top.sv \
 	-I LOWRISC_SAIL_SRC/lib/sv/ --single-unit --no-proc
 setattr -set keep 1 n:\\* # Keep all named wires. FIXME: Is this still necessary?

dv/formal/check/top.sv

@@ -43,69 +43,73 @@ module top import ibex_pkg::*; #(
   parameter int unsigned PMPNumRegions    = 4
 ) (
   // Clock and Reset
-  input  logic                         clk_i,
+  input  logic                                                         clk_i,
 
   `ifndef YOSYS
-  input  logic                         rst_ni,
+  input  logic                                                         rst_ni,
   `endif
 
-  input  logic                         test_en_i,     // enable all clock gates for testing
-  input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
+  input  logic                                                         test_en_i,
+  input  prim_ram_1p_pkg::ram_1p_cfg_t                                 ram_cfg_icache_tag_i,
+  output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o,
+  input  prim_ram_1p_pkg::ram_1p_cfg_t                                 ram_cfg_icache_data_i,
+  output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o,
 
-  input  logic [31:0]                  hart_id_i,
-  input  logic [31:0]                  boot_addr_i,
+  input  logic [31:0]                                                  hart_id_i,
+  input  logic [31:0]                                                  boot_addr_i,
 
   // Instruction memory interface
-  output logic                         instr_req_o,
-  input  logic                         instr_gnt_i,
-  input  logic                         instr_rvalid_i,
-  output logic [31:0]                  instr_addr_o,
-  input  logic [31:0]                  instr_rdata_i,
-  input  logic [6:0]                   instr_rdata_intg_i,
-  input  logic                         instr_err_i,
+  output logic                                                         instr_req_o,
+  input  logic                                                         instr_gnt_i,
+  input  logic                                                         instr_rvalid_i,
+  output logic [31:0]                                                  instr_addr_o,
+  input  logic [31:0]                                                  instr_rdata_i,
+  input  logic [6:0]                                                   instr_rdata_intg_i,
+  input  logic                                                         instr_err_i,
 
   // Data memory interface
-  output logic                         data_req_o,
-  output logic                         data_is_cap_o,
-  input  logic                         data_gnt_i,
-  input  logic                         data_rvalid_i,
-  output logic                         data_we_o,
-  output logic [3:0]                   data_be_o,
-  output logic [31:0]                  data_addr_o,
-  output logic [31:0]                  data_wdata_o,
-  output logic [6:0]                   data_wdata_intg_o,
-  input  logic [31:0]                  data_rdata_i,
-  input  logic [6:0]                   data_rdata_intg_i,
-  input  logic                         data_err_i,
+  output logic                                                         data_req_o,
+  output logic                                                         data_is_cap_o,
+  input  logic                                                         data_gnt_i,
+  input  logic                                                         data_rvalid_i,
+  output logic                                                         data_we_o,
+  output logic [3:0]                                                   data_be_o,
+  output logic [31:0]                                                  data_addr_o,
+  output logic [31:0]                                                  data_wdata_o,
+  output logic [6:0]                                                   data_wdata_intg_o,
+  input  logic [31:0]                                                  data_rdata_i,
+  input  logic [6:0]                                                   data_rdata_intg_i,
+  input  logic                                                         data_err_i,
 
   // Interrupt inputs
-  input  logic                         irq_software_i,
-  input  logic                         irq_timer_i,
-  input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
-  input  logic                         irq_nm_i,       // non-maskable interrupt
+  input  logic                                                         irq_software_i,
+  input  logic                                                         irq_timer_i,
+  input  logic                                                         irq_external_i,
+  input  logic [14:0]                                                  irq_fast_i,
+  // non-maskable interrupt
+  input  logic                                                         irq_nm_i,
 
   // Scrambling Interface
-  input  logic                         scramble_key_valid_i,
-  input  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_i,
-  input  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_i,
-  output logic                         scramble_req_o,
+  input  logic                                                         scramble_key_valid_i,
+  input  logic [SCRAMBLE_KEY_W-1:0]                                    scramble_key_i,
+  input  logic [SCRAMBLE_NONCE_W-1:0]                                  scramble_nonce_i,
+  output logic                                                         scramble_req_o,
 
   // Debug Interface
-  input  logic                         debug_req_i,
-  output crash_dump_t                  crash_dump_o,
-  output logic                         double_fault_seen_o,
+  input  logic                                                         debug_req_i,
+  output crash_dump_t                                                  crash_dump_o,
+  output logic                                                         double_fault_seen_o,
 
   // CPU Control Signals
-  input  ibex_mubi_t                   fetch_enable_i,
-  output logic                         core_sleep_o,
-  output logic                         alert_minor_o,
-  output logic                         alert_major_internal_o,
-  output logic                         alert_major_bus_o,
+  input  ibex_mubi_t                                                   fetch_enable_i,
+  output logic                                                         core_sleep_o,
+  output logic                                                         alert_minor_o,
+  output logic                                                         alert_major_internal_o,
+  output logic                                                         alert_major_bus_o,
 
 
   // DFT bypass controls
-  input logic                          scan_rst_ni
+  input logic                                                          scan_rst_ni
 );
 
 // Yosys based tools have no inherent understanding of a reset signal (unlike jasper, which has the

dv/formal/ibex_formal.core

@@ -10,19 +10,9 @@ filesets:
     depend:
       - lowrisc:ibex:ibex_pkg
       - lowrisc:ibex:ibex_core
-      - lowrisc:prim:buf
-      - lowrisc:prim:clock_gating
-      - lowrisc:prim:secded
-      - lowrisc:prim:assert
-      - lowrisc:prim:ram_1p_pkg
-      - lowrisc:prim_generic:buf
-      - lowrisc:prim_generic:clock_gating
-    files:
-      - ../../rtl/ibex_register_file_ff.sv # generic FF-based
-      - ../../rtl/ibex_register_file_fpga.sv # FPGA
-      - ../../rtl/ibex_register_file_latch.sv # ASIC
-      - ../../rtl/ibex_top.sv
-    file_type: systemVerilogSource
+      - lowrisc:ibex:ibex_top
+      - "fileset_partner ? (partner:prim_generic:all)"
+      - "!fileset_partner ? (lowrisc:prim_generic:all)"
 
 targets:
   default:

dv/formal/pyproject.toml

@@ -14,8 +14,8 @@ dependencies = [
   "hjson == 3.1.0",
   "mako == 1.1.6",
   "pyyaml == 6.0.2",
-  "edalize @ git+https://github.com/lowRISC/[email protected]",
-  "fusesoc @ git+https://github.com/lowRISC/[email protected]",
+  "edalize == 0.6.1",
+  "fusesoc == 2.4.3",
   "psutil>=7.0.0",
 ]
 

dv/formal/verify.tcl

@@ -16,7 +16,7 @@ set_prove_cache_mode coi
 set_prove_per_property_time_limit 10s
 
 # Load all Ibex RTL, using the filelist generated by fusesoc
-analyze -sv12 +define+SYNTHESIS -f_relative_to_file_location build/fusesoc/default-vcs/lowrisc_ibex_ibex_formal_0.1.scr
+analyze -sv12 +define+SYNTHESIS -f_relative_to_file_location build/fusesoc/lowrisc_ibex_ibex_formal_0.1/default-vcs/lowrisc_ibex_ibex_formal_0.1.scr
 
 set sail_lib_dir $env(LOWRISC_SAIL_SRC)/lib/sv
 analyze -sv12 -incdir $sail_lib_dir build/ibexspec.sv

dv/riscv_compliance/ibex_riscv_compliance.cc

@@ -13,9 +13,7 @@ int main(int argc, char **argv) {
   simctrl.SetTop(&top, &top.IO_CLK, &top.IO_RST_N,
                  VerilatorSimCtrlFlags::ResetPolarityNegative);
 
-  MemArea ram(
-      "TOP.ibex_riscv_compliance.u_ram.u_ram.gen_generic.u_impl_generic",
-      64 * 1024 / 4, 4);
+  MemArea ram("TOP.ibex_riscv_compliance.u_ram.u_ram", 64 * 1024 / 4, 4);
 
   memutil.RegisterMemoryArea("ram", 0x0, &ram);
   simctrl.RegisterExtension(&memutil);