This design is modeled after the LC-3 Instruction Set Architecture. It features a 16-bit Program Counter, 16-bit instructions, and a set of registers. The processor executes a subset of LC-3 opcodes, including operations like ADD, AND, NOT, BR, JMP, JSR, LDR, and STR. Its operation is divided into three main phases: FETCH, DECODE, and EXECUTE. During the FETCH phase, the processor retrieves the instruction from memory. In the DECODE phase, the instruction is interpreted, and necessary control signals are set. Finally, the EXECUTE phase carries out the operation specified by the instruction. The SLC3's architecture supports branching functionalities which could allow us to build loops and conditional operations like if statements. By integrating these features, the SLC3 provides a comprehensive platform for exploring computer architecture and system design within an FPGA environment.

The SLC3 simplifies the LC3 architecture by removing several instructions (JSR, LD, LDI, LEA, RET, RTI, ST, STI, TRAP) and I/O components like keyboard/display interfaces. It introduces a new pause instruction using the previously reserved opcode and stays there until we reach CONTINUE. Since FPGA lacks internal tristate buffers, the lc3 uses multiplexers controlled by gate signals. Memory connections with mar and mdr are managed through a cpu_to_io module interfacing with FPGA IO BRAM. Memory read/write states are extended to three sequential cycles instead of using the R signal. Finally, a halt state is also included for reset functionality.