[WIP] vendor/riscv/riscv-isa-sim: fix yaml-cpp build

[cathales]

There are several issues building spike in CVA6 CI:

1. The yaml-cpp target added by Valentin outputs .h files so it must be run before compiling riscv which directly depends on it, and spike_main which indirectly depends on it.
   The way it was added did not guarantee that so we encountered non-deterministic "missing included .h file" errors at compile-time.
   This should be fixed in this PR thanks to gen_hdrs variables.
2. (There was an issue with submodule recursive clone but that is solved in CVA6 repository)
3. There is the same issue at link-time. An _LDFLAGS variable has been added but I feel it does not fix the thing. So this change might not be relevant, and I unfortunately have no time to fix now.
4. With the current version, some VCS-UVM simulations fail.