[DRAFT] RVH-tests

[NicolasDerumigny]

First draft of our RVH testing c-test suite, implemented in verif/tests/custom/rvh and triggered by verif/regress/hypervisor-tests-cv64a6_imafdch_sv39.sh.

It features:

• paging tests in host mode (S-mode)
• paging tests in host mode (U-mode)
• paging tests in virtual mode (VS-mode), both at hgatp and vsatp level (guest and host page table)

This is by far not exhaustive of all H-Mode quirks, and is only SV39 (64-bit) compliant.

cva6.py, Makefile, ariane_testharness.sv, ariane_tb.cpp and various project files were modified to:

• execute prints from the verilator harness: a from_host value is added along with the to_host, to answer on syscall completion. This requires CBO operations and HPDCache to ensure that the cache do not interfere on read/writes to these values.
• explicitly support/show hart id (not very relevant here, but we use it on our fork).
• allow diff of the output print between spike and verilator (with an additional option to cva6.py).
• allow diff between verilator and a reference file containing regular expressions (unused in this PR) (with an additional option to cva6.py).
• add a --no-ecall-exit-marker as ecalls seem to trigger exits on one tool (VCS?) but are required in our H-Mode test suite.

Also:

• verible-format was run on ariane_testharness.sv, resulting in (lots of) formatting changes.
• verible-format was run on corev_apu/tb/rvfi_tracer.sv, resulting in (lots of) formatting changes.
• VS-mode tests require fix: no error on h-mode SV39x4 translation #3221 to pass, so this PR is based on the top of it

The goal of this PR is to know what need to be kept, what breaks the current CI and what should be saved for final merge, as discussed in last weekly meeting.

[cainria]

Please convert your PR to a Draft PR (below the list of reviewers in the right column of this page). It will prevent from an accidental merge.

[github-actions]

👋 Hi there!

This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊

[NicolasDerumigny]

I have updated the PR to be rebased on the top of #3221, and removed the useless multicore support in cva6.py. It should be now much clearer to read!

[NicolasDerumigny]

I cannot see the failure log of the CI, is this expected?

[cainria]

Tue, 19 May 2026 10:31:43 INFO     [veri-testharness] Running ISS simulation: /home/runner/work/cva6/cva6/verif/sim/out_2026-05-19/directed_tests/cadd-01.o ...done

Tue, 19 May 2026 10:31:43 INFO     Incomplete TANDEM YAML report
Tue, 19 May 2026 10:31:43 INFO     Processing verilator log : /home/runner/work/cva6/cva6/verif/sim/out_2026-05-19/veri-testharness_sim/rv32im-cadd-01.cv32a65x_hart_00.log

/home/runner/work/cva6/cva6/verif/sim/out_2026-05-19/directed_tests/cadd-01.o
/home/runner/work/cva6/cva6/verif/sim/out_2026-05-19/directed_tests/cadd-01.o
Traceback (most recent call last):
  File "/home/runner/work/cva6/cva6/verif/sim/cva6.py", line 1352, in <module>
    main()
  File "/home/runner/work/cva6/cva6/verif/sim/cva6.py", line 1313, in main
    run_test(path_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts,
  File "/home/runner/work/cva6/cva6/verif/sim/cva6.py", line 557, in run_test
    tandem_postprocess(yaml, target, isa, test_log_name, log, testlist, iss,
  File "/home/runner/work/cva6/cva6/verif/sim/cva6.py", line 421, in tandem_postprocess
    process_verilator_sim_log(logfile + ".log", logfile + ".csv", exit_on_ecall=exit_on_ecall)
  File "/home/runner/work/cva6/cva6/verif/sim/verilator_log_to_trace_csv.py", line 209, in process_verilator_sim_log
    for (entry, illegal) in read_verilator_trace(verilator_log, full_trace, exit_on_ecall):
  File "/home/runner/work/cva6/cva6/verif/sim/verilator_log_to_trace_csv.py", line 125, in read_verilator_trace
    with open(path, 'r') as handle:
         ^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/home/runner/work/cva6/cva6/verif/sim/out_2026-05-19/veri-testharness_sim/rv32im-cadd-01.cv32a65x_hart_00.log'

Did you change the RVFI output file path?

[NicolasDerumigny]

Yes. I splitted output into .log and .out with .log being the old one without extension, and .out everything output by verilator during execution (internal messages + output of "printf"). Is there a way to run tandem locally? I cannot reproduce it using solely sim/verif/dv-riscv-arch-test.

[cainria]

Have you set SPIKE_TANDEM to 1 in the environment?

cva6/.gitlab-ci.yml

Line 147 in 9c2cf60

SPIKE_TANDEM: 1

[NicolasDerumigny]

After quite some trouble, tests should now be passing.

However, the printf calls in tests require Zicbom extension in order to behave correctly, else a deadlock can happen as communications with the harness take place in a cacheable zone. I left the hello_word test as untouched, but it is fundamentally broken (syscall API is not respected, fromhost is never correctly read, it only pass because no syscall is in fact issued thanks to the printf buffering mechanism).

I believe that hello world tests should be removed from tests without Zicbom, as such tests currently do not work as they should (i.e. do not issue syscalls), and cannot without a proper way to bypass cache, which may be:

• Zicbom. As far as I have tested, spike crashes on cbo.inval in 32-bit (and we may not want to test only with it enabled
• Cache activation / deactivation. As far as I have tested, MSR 0x7c1 results in hangs if used with the C harness (I suspect conflicts at the cache level, I have tracked the bug down to the cache directory where all ways where fetching without answers)
• specification of an uncachable region. That I have not tried, as it should be specific for the test harness and therefore should not be in the preset: I do not think this is a good idea

[github-actions]

👋 Hi there!

This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊