Draft: Add Svadu, Svpbmt, and Svinval support

[sjo99-kr]

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Note: This PR will be discussed on next CVA6 community meeting (15th July).

This draft PR adds initial support for several RISC-V virtual-memory-related extensions in CVA6:

• Svadu: hardware update of PTE A/D bits
• Svpbmt: page-based memory types
• Svinval: fine-grained address-translation cache invalidation instructions

I am opening this as a draft PR to make the implementation visible early and to get feedback from the CVA6 community on the overall architecture, interfaces, and review direction.
Sorry for one BIG PR rather than separate PRs, since those extensions are all for virtual address-related modifications

New Module for Svadu

• pte_update_unit.sv : For Svadu extension, I added new module for atomic operation on page-table entry. Briefy, it resides in store_unit.sv and shared AMO port wtih amo_buffer.sv.

You can find detailed descriptions of this in google doc file.
(doc: https://docs.google.com/document/d/1ypJdJz2CnGH1iI8uIijN8Pk9YOaYb5urEnP2yZa9vrY/edit?usp=sharing)

Verification

• RISC-V ACT-4 Based coverage tests : I have implemented ACT-4 based assembly codes for testing architectural conflicts, and added some directed tests, which is not covered by current RISC-V ACT-4.
• Regression tests : For verifying regression, I have tested this codes with current regression tests in CVA6, changing the configurations for UseSharedTLB, SvaduEn, SvpbmtEn, SvinvalEn.

You can find detailed descriptions of coverage tests and regression tests, the following results in google doc file.
(doc : https://docs.google.com/document/d/1ypJdJz2CnGH1iI8uIijN8Pk9YOaYb5urEnP2yZa9vrY/edit?usp=sharing)

Related Issue

• Privileged extenion tests in current CVA6.py : As following closed PR Add Spike-specific extension option in cva6.py for issue #3249 #3280, I couldn't figure out how to add spike-only options in current cva6.py beyond cv32a60x and cv32a65x, which both already have spike.yaml file. So I just added specific option spike_extension in cva6.py file. I mainly used this for verification, and I don't think this modification needs to be reviewed for merge, it's just for verification.
• sfence.vma bug in cva6_tlb.sv : Issue [BUG] SFENCE.VMA selective flush appears to use a stale vaddr/ASID selector #3307 raises the bug of sfence.vma, and I found that the issue was caused by a bit-width mismatch, fixed it in this PR, and confirmed that the related test no longer fails.
• PMP-related fault issue : Issue [BUG] CVA6 reports load access fault for PMP-denied AMO instead of store/AMO access fault #3338 raises the bug of PMP fault handling, I fixed the main problem related to store_i timing on the PMP side and confirmed that the related test no longer fails.
• Shared TLB flush : The cva6_shared_tlb.sv in my PR is based on the PR Improved TLB flushing logic for Supervisor mode #3312, because Svinval is directly related to TLB flush/invalidation behavior. I adapted the shared-TLB flush flow from that PR for the Svinval implementation.

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There could be more issues related my PR and tests, but I'm happy to hang on here, and modify all concerns to be merged. So, feel free to tell me concerns, and really thank you guys for reviewing :)

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