test: add misaligned branch regression with RVC disabled

[Srinidhi-Magesh]

Summary

• Adds a directed regression for issue [TASK] Add a test for misaligned branches #1720.
• Verifies that a taken branch to a 2-byte-aligned but non-4-byte-aligned target traps when RVC is disabled.
• Preserves explicit -march and -mabi options for directed tests.

Validation

• GCC ISA: rv32im_zba_zbb_zbs_zbc_zicsr_zifencei
• Spike ISA: rv32im_zba_zbb_zbs_zbc_zicsr_zifencei
• Observed trap_instruction_address_misaligned
• mcause = 0
• Spike simulation completed successfully

Address layout

• main: 0x80003000
• misaligned_target: 0x8000300a
• handle_trap: 0x80003010

Closes #1720